[PATCH V2 1/1] watchdog: stm32_iwdg: don't print an error on probe deferral

[Christophe Roullier]

From: Etienne Carriere 

Do not print an error trace when deferring probe for clock resources.

Signed-off-by: Etienne Carriere 
Signed-off-by: Christophe Roullier 
---
 drivers/watchdog/stm32_iwdg.c | 13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c
index 25188d6bbe15..a3436c296c97 100644
--- a/drivers/watchdog/stm32_iwdg.c
+++ b/drivers/watchdog/stm32_iwdg.c
@@ -162,18 +162,15 @@ static int stm32_iwdg_clk_init(struct platform_device 
*pdev,
u32 ret;
 
wdt->clk_lsi = devm_clk_get(dev, "lsi");
-   if (IS_ERR(wdt->clk_lsi)) {
-   dev_err(dev, "Unable to get lsi clock\n");
-   return PTR_ERR(wdt->clk_lsi);
-   }
+   if (IS_ERR(wdt->clk_lsi))
+   return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get 
lsi clock\n");
 
/* optional peripheral clock */
if (wdt->data->has_pclk) {
wdt->clk_pclk = devm_clk_get(dev, "pclk");
-   if (IS_ERR(wdt->clk_pclk)) {
-   dev_err(dev, "Unable to get pclk clock\n");
-   return PTR_ERR(wdt->clk_pclk);
-   }
+   if (IS_ERR(wdt->clk_pclk))
+   return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk),
+"Unable to get pclk clock\n");
 
ret = clk_prepare_enable(wdt->clk_pclk);
if (ret) {
-- 
2.17.1

[PATCH V2 0/1] watchdog: stm32_iwdg: don't print an error on probe deferral

[Christophe Roullier]

Do not print an error trace when deferring probe for clock resources.

Version 2: Remark from Guenter and Ahmad
use dev_err_probe instead 

Etienne Carriere (1):
  watchdog: stm32_iwdg: don't print an error on probe deferral

 drivers/watchdog/stm32_iwdg.c | 13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

-- 
2.17.1

[PATCH 1/1] watchdog: stm32_iwdg: don't print an error on probe deferral

[Christophe Roullier]

From: Etienne Carriere 

Do not print an error trace when deferring probe for clock resources.

Signed-off-by: Etienne Carriere 
Signed-off-by: Christophe Roullier 
---
 drivers/watchdog/stm32_iwdg.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c
index 25188d6bbe15..1b71c205cee0 100644
--- a/drivers/watchdog/stm32_iwdg.c
+++ b/drivers/watchdog/stm32_iwdg.c
@@ -163,7 +163,8 @@ static int stm32_iwdg_clk_init(struct platform_device *pdev,
 
wdt->clk_lsi = devm_clk_get(dev, "lsi");
if (IS_ERR(wdt->clk_lsi)) {
-   dev_err(dev, "Unable to get lsi clock\n");
+   if (PTR_ERR(wdt->clk_lsi) != -EPROBE_DEFER)
+   dev_err(dev, "Unable to get lsi clock\n");
return PTR_ERR(wdt->clk_lsi);
}
 
@@ -171,7 +172,8 @@ static int stm32_iwdg_clk_init(struct platform_device *pdev,
if (wdt->data->has_pclk) {
wdt->clk_pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(wdt->clk_pclk)) {
-   dev_err(dev, "Unable to get pclk clock\n");
+   if (PTR_ERR(wdt->clk_pclk) != -EPROBE_DEFER)
+   dev_err(dev, "Unable to get pclk clock\n");
return PTR_ERR(wdt->clk_pclk);
}
 
-- 
2.17.1

Re: [PATCH v3 0/1] net: ethernet: stmmac: simplify phy modes management for stm32

[Christophe ROULLIER]

Hi,

Just a "gentleman ping"

Regards,

Christophe.

On 27/04/2020 12:00, Christophe Roullier wrote:
> No new feature, just to simplify stm32 part to be easier to use.
> Add by default all Ethernet clocks in DT, and activate or not in function
> of phy mode, clock frequency, if property "st,ext-phyclk" is set or not.
> Keep backward compatibility
>
> version 3:
> Add acked from Alexandre Torgue
> Rebased on top of v5.7-rc2
>
> Christophe Roullier (1):
>net: ethernet: stmmac: simplify phy modes management for stm32
>
>   .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 74 +++
>   1 file changed, 44 insertions(+), 30 deletions(-)
>

Re: [PATCH 0/5] net: ethernet: stmmac: some fixes and optimization

[Christophe ROULLIER]

Hi Jakub, all,

It is not urgent, no problem to wait next merge window (release 5.5)

For patch 1 and 3, it is improvement/cleanup because now syscfg clock is 
not mandatory (I put code backward compatible).

Regards,

Christophe

On 9/23/19 12:12 AM, Jakub Kicinski wrote:
> On Fri, 20 Sep 2019 07:38:12 +0200, Christophe Roullier wrote:
>> Some improvements (manage syscfg as optional clock, update slew rate of
>> ETH_MDIO pin, Enable gating of the MAC TX clock during TX low-power mode)
>> Fix warning build message when W=1
> There seems to be some new features/cleanups (or improvements as
> you say) here. Could you explain the negative impact not applying
> these changes will have? Patches 1 and 3 in particular.
>
> net-next is now closed [1], and will reopen some time after the merge
> window is over. For now we are only expecting fixes for the net tree.
>
> Could you (a) provide stronger motivation these changes are fixes; or
> (b) separate the fixes from improvements?
>
> Thank you!
>
> [1] https://www.kernel.org/doc/html/latest/networking/netdev-FAQ.html

[PATCH 2/5] net: ethernet: stmmac: fix warning when w=1 option is used during build

[Christophe Roullier]

This patch fix the following warning:

warning: variable ‘ret’ set but not used [-Wunused-but-set-variable]
  int val, ret;

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 7e6619868cc1..167a5e99960a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -184,7 +184,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data 
*plat_dat)
 {
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
u32 reg = dwmac->mode_reg;
-   int val, ret;
+   int val;
 
switch (plat_dat->interface) {
case PHY_INTERFACE_MODE_MII:
@@ -220,8 +220,8 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data 
*plat_dat)
}
 
/* Need to update PMCCLRR (clear register) */
-   ret = regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
-  dwmac->ops->syscfg_eth_mask);
+   regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
+dwmac->ops->syscfg_eth_mask);
 
/* Update PMCSETR (set register) */
return regmap_update_bits(dwmac->regmap, reg,
-- 
2.17.1

[PATCH 4/5] ARM: dts: stm32: adjust slew rate for Ethernet

[Christophe Roullier]

ETH_MDIO slew-rate should be set to "0" instead of "2"

Signed-off-by: Christophe Roullier 
---
 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index df6470133574..7667fe758957 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -239,13 +239,18 @@
 , 
/* ETH_RGMII_TXD2 */
 , 
/* ETH_RGMII_TXD3 */
 , 
/* ETH_RGMII_TX_CTL */
-, 
/* ETH_MDIO */
 ; 
/* ETH_MDC */
bias-disable;
drive-push-pull;
-   slew-rate = <3>;
+   slew-rate = <2>;
};
pins2 {
+   pinmux = ; 
/* ETH_MDIO */
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins3 {
pinmux = , 
/* ETH_RGMII_RXD0 */
 , 
/* ETH_RGMII_RXD1 */
 , 
/* ETH_RGMII_RXD2 */
-- 
2.17.1

[PATCH 0/5] net: ethernet: stmmac: some fixes and optimization

[Christophe Roullier]

Some improvements (manage syscfg as optional clock, update slew rate of
ETH_MDIO pin, Enable gating of the MAC TX clock during TX low-power mode)
Fix warning build message when W=1

Christophe Roullier (5):
  net: ethernet: stmmac: Add support for syscfg clock
  net: ethernet: stmmac: fix warning when w=1 option is used during
build
  ARM: dts: stm32: remove syscfg clock on stm32mp157c ethernet
  ARM: dts: stm32: adjust slew rate for Ethernet
  ARM: dts: stm32: Enable gating of the MAC TX clock during TX low-power
mode on stm32mp157c

 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi |  9 +++-
 arch/arm/boot/dts/stm32mp157c.dtsi|  7 ++--
 .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 42 ---
 3 files changed, 38 insertions(+), 20 deletions(-)

-- 
2.17.1

[PATCH 3/5] ARM: dts: stm32: remove syscfg clock on stm32mp157c ethernet

[Christophe Roullier]

Syscfg is now activated automatically when syscfg registers are used

Signed-off-by: Christophe Roullier 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index 0c4e6ebc3529..f51d6222a0e8 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -1285,13 +1285,11 @@
clock-names = "stmmaceth",
  "mac-clk-tx",
  "mac-clk-rx",
- "ethstp",
- "syscfg-clk";
+ "ethstp";
clocks = < ETHMAC>,
 < ETHTX>,
 < ETHRX>,
-< ETHSTP>,
-< SYSCFG>;
+< ETHSTP>;
st,syscon = < 0x4>;
snps,mixed-burst;
snps,pbl = <2>;
-- 
2.17.1

[PATCH 5/5] ARM: dts: stm32: Enable gating of the MAC TX clock during TX low-power mode on stm32mp157c

[Christophe Roullier]

When there is no activity on ethernet phy link, the ETH_GTX_CLK is cut

Signed-off-by: Christophe Roullier 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index f51d6222a0e8..d78dfc44a1fb 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -1293,6 +1293,7 @@
st,syscon = < 0x4>;
snps,mixed-burst;
snps,pbl = <2>;
+   snps,en-tx-lpi-clockgating;
snps,axi-config = <_axi_config_0>;
snps,tso;
status = "disabled";
-- 
2.17.1

[PATCH 1/5] net: ethernet: stmmac: Add support for syscfg clock

[Christophe Roullier]

Add optional support for syscfg clock in dwmac-stm32.c
Now Syscfg clock is activated automatically when syscfg
registers are used

Signed-off-by: Christophe Roullier 
---
 .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 36 +--
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 4ef041bdf6a1..7e6619868cc1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -152,23 +152,32 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac 
*dwmac, bool prepare)
int ret = 0;
 
if (prepare) {
-   ret = clk_prepare_enable(dwmac->syscfg_clk);
-   if (ret)
-   return ret;
-
+   if (dwmac->syscfg_clk) {
+   ret = clk_prepare_enable(dwmac->syscfg_clk);
+   if (ret)
+   return ret;
+   }
if (dwmac->clk_eth_ck) {
ret = clk_prepare_enable(dwmac->clk_eth_ck);
if (ret) {
-   clk_disable_unprepare(dwmac->syscfg_clk);
+   if (dwmac->syscfg_clk)
+   goto unprepare_syscfg;
return ret;
}
}
} else {
-   clk_disable_unprepare(dwmac->syscfg_clk);
+   if (dwmac->syscfg_clk)
+   clk_disable_unprepare(dwmac->syscfg_clk);
+
if (dwmac->clk_eth_ck)
clk_disable_unprepare(dwmac->clk_eth_ck);
}
return ret;
+
+unprepare_syscfg:
+   clk_disable_unprepare(dwmac->syscfg_clk);
+
+   return ret;
 }
 
 static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
@@ -296,7 +305,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
 {
struct platform_device *pdev = to_platform_device(dev);
struct device_node *np = dev->of_node;
-   int err = 0;
+   int err;
 
/* Gigabit Ethernet 125MHz clock selection. */
dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");
@@ -320,13 +329,17 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
return PTR_ERR(dwmac->clk_ethstp);
}
 
-   /*  Clock for sysconfig */
+   /*  Optional Clock for sysconfig */
dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
if (IS_ERR(dwmac->syscfg_clk)) {
-   dev_err(dev, "No syscfg clock provided...\n");
-   return PTR_ERR(dwmac->syscfg_clk);
+   err = PTR_ERR(dwmac->syscfg_clk);
+   if (err != -ENOENT)
+   return err;
+   dwmac->syscfg_clk = NULL;
}
 
+   err = 0;
+
/* Get IRQ information early to have an ability to ask for deferred
 * probe if needed before we went too far with resource allocation.
 */
@@ -436,7 +449,8 @@ static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
return ret;
 
clk_disable_unprepare(dwmac->clk_tx);
-   clk_disable_unprepare(dwmac->syscfg_clk);
+   if (dwmac->syscfg_clk)
+   clk_disable_unprepare(dwmac->syscfg_clk);
if (dwmac->clk_eth_ck)
clk_disable_unprepare(dwmac->clk_eth_ck);
 
-- 
2.17.1

[PATCH 1/1] ARM: dts: stm32: replace rgmii mode with rgmii-id on stm32mp15 boards

[Christophe Roullier]

On disco and eval board, Tx and Rx delay are applied (pull-up of 4.7k
put on VDD) so which correspond to RGMII-ID mode with internal RX and TX
delays provided by the PHY, the MAC should not add the RX or TX delays
in this case

Signed-off-by: Christophe Roullier 
---
 arch/arm/boot/dts/stm32mp157a-dk1.dts | 2 +-
 arch/arm/boot/dts/stm32mp157c-ev1.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts 
b/arch/arm/boot/dts/stm32mp157a-dk1.dts
index 098dbfb06b61..2c105740dfad 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
@@ -51,7 +51,7 @@
pinctrl-0 = <_rgmii_pins_a>;
pinctrl-1 = <_rgmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
-   phy-mode = "rgmii";
+   phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <>;
 
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts 
b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index b6aca40b9b90..ab1393caf799 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -79,7 +79,7 @@
pinctrl-0 = <_rgmii_pins_a>;
pinctrl-1 = <_rgmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
-   phy-mode = "rgmii";
+   phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <>;
 
-- 
2.17.1

[PATCH 0/1] ARM: dts: stm32: replace rgmii mode with rgmii-id on stm32mp15 boards

[Christophe Roullier]

On disco and eval board, Tx and Rx delay are applied (pull-up of 4.7k
put on VDD) so which correspond to RGMII-ID mode with internal RX and TX
delays provided by the PHY, the MAC should not add the RX or TX delays
in this case

Christophe Roullier (1):
  ARM: dts: stm32: replace rgmii mode with rgmii-id on stm32mp15 boards

 arch/arm/boot/dts/stm32mp157a-dk1.dts | 2 +-
 arch/arm/boot/dts/stm32mp157c-ev1.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

-- 
2.17.1

[PATCH V3 5/6] dt-bindings: net: stmmac: remove syscfg clock property

[Christophe Roullier]

Syscfg clock is no more needed.

Signed-off-by: Christophe Roullier 
---
 Documentation/devicetree/bindings/net/stm32-dwmac.txt | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt 
b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index 3524e80..a90eef1 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -14,8 +14,7 @@ Required properties:
 - clock-names: Should be "stmmaceth" for the host clock.
   Should be "mac-clk-tx" for the MAC TX clock.
   Should be "mac-clk-rx" for the MAC RX clock.
-  For MPU family need to add also "ethstp" for power mode clock 
and,
-  "syscfg-clk" for SYSCFG clock.
+  For MPU family need to add also "ethstp" for power mode clock
 - interrupt-names: Should contain a list of interrupt names corresponding to
the interrupts in the interrupts property, if available.
   Should be "macirq" for the main MAC IRQ
-- 
2.7.4

[PATCH V3 2/6] net: ethernet: stmmac: update to support all PHY config for stm32mp157c.

[Christophe Roullier]

Update glue codes to support all PHY config on stm32mp157c
 PHY_MODE   (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config.

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 107 +-
 1 file changed, 86 insertions(+), 21 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index d1cf145..062a600f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -25,9 +25,24 @@
 
 #define SYSCFG_MCU_ETH_MASKBIT(23)
 #define SYSCFG_MP1_ETH_MASKGENMASK(23, 16)
+#define SYSCFG_PMCCLRR_OFFSET  0x40
 
 #define SYSCFG_PMCR_ETH_CLK_SELBIT(16)
 #define SYSCFG_PMCR_ETH_REF_CLK_SELBIT(17)
+
+/*  Ethernet PHY interface selection in register SYSCFG Configuration
+ *--
+ * src  |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
+ *--
+ * MII   |   0  |   0|   0|   1   |
+ *--
+ * GMII  |   0  |   0|   0|   0   |
+ *--
+ * RGMII |   0  |   0|   1|  n/a  |
+ *--
+ * RMII  |   1  |   0|   0|  n/a  |
+ *--
+ */
 #define SYSCFG_PMCR_ETH_SEL_MIIBIT(20)
 #define SYSCFG_PMCR_ETH_SEL_RGMII  BIT(21)
 #define SYSCFG_PMCR_ETH_SEL_RMII   BIT(23)
@@ -35,15 +50,54 @@
 #define SYSCFG_MCU_ETH_SEL_MII 0
 #define SYSCFG_MCU_ETH_SEL_RMII1
 
+/* STM32MP1 register definitions
+ *
+ * Below table summarizes the clock requirement and clock sources for
+ * supported phy interface modes.
+ * __
+ *|PHY_MODE | Normal | PHY wo crystal|   PHY wo crystal   |No 125Mhz from PHY|
+ *| ||  25MHz|50MHz   |  |
+ * ---
+ *|  MII|   -   | eth-ck|n/a |   n/a|
+ *| ||  ||  |
+ * ---
+ *|  GMII   |   -   | eth-ck|n/a |   n/a|
+ *| ||   || |
+ * ---
+ *| RGMII   |   -   | eth-ck|n/a |  eth-ck (no pin) |
+ *| ||   ||  st,eth-clk-sel  |
+ * ---
+ *| RMII|   -   | eth-ck|  eth-ck|   n/a|
+ *| ||  | st,eth-ref-clk-sel |  |
+ * ---
+ *
+ * BIT(17) : set this bit in RMII mode when you have PHY without crystal 50MHz
+ * BIT(16) : set this bit in GMII/RGMII PHY when you do not want use 125Mhz
+ * from PHY
+ *-
+ * src  | BIT(17)   |   BIT(16)  |
+ *-
+ * MII   |   n/a| n/a|
+ *-
+ * GMII  |   n/a |   st,eth-clk-sel   |
+ *-
+ * RGMII |   n/a |   st,eth-clk-sel   |
+ *-
+ * RMII  |   st,eth-ref-clk-sel | n/a|
+ *-
+ *
+ */
+
 struct stm32_dwmac {
struct clk *clk_tx;
struct clk *clk_rx;
struct clk *clk_eth_ck;
struct clk *clk_ethstp;
struct clk *syscfg_clk;
-   bool int_phyclk;/* Clock from RCC to drive PHY */
+   int eth_clk_sel_reg;
+   int eth_ref_clk_sel_reg;
int irq_pwr_wakeup;
-   u32 mode_reg;   /* MAC glue-logic mode register */
+   u32 mode_reg;/* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
const struct stm32_ops *ops;
@@ -103,7 +157,7 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, 
bool prepare)
if (ret)
return ret;
 
-   if (dwmac->int_phyclk) {
+   if (dwmac->clk_eth_ck) {
ret = clk_prepare_enable(dwmac->clk_eth_ck);
if (ret) {
clk_disable_unprepare(dwmac->syscfg_clk);
@@ -112,7 +166,7 @@ static int stm32mp1

[PATCH V3 6/6] ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it for eval and disco boards

[Christophe Roullier]

Synopsys GMAC 4.10 is used. And Phy mode for eval and disco is RMII
with PHY SMSC LAN8742

Signed-off-by: Christophe Roullier 
---
 arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 15 +++
 arch/arm/boot/dts/stm32h743.dtsi | 13 +
 arch/arm/boot/dts/stm32h743i-disco.dts   | 17 +
 arch/arm/boot/dts/stm32h743i-eval.dts| 17 +
 4 files changed, 62 insertions(+)

diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index 24be8e6..980b276 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -173,6 +173,21 @@
};
};
 
+   ethernet_rmii: rmii@0 {
+   pins {
+   pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+   slew-rate = <2>;
+   };
+   };
+
usart1_pins: usart1@0 {
pins1 {
pinmux = ; 
/* USART1_TX */
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index cbdd69c..e103b29 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -511,6 +511,19 @@
status = "disabled";
};
};
+
+   mac: ethernet@40028000 {
+   compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
+   reg = <0x40028000 0x8000>;
+   reg-names = "stmmaceth";
+   interrupts = <61>;
+   interrupt-names = "macirq";
+   clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+   clocks = < ETH1MAC_CK>, < ETH1TX_CK>, < 
ETH1RX_CK>;
+   st,syscon = < 0x4>;
+   snps,pbl = <8>;
+   status = "disabled";
+   };
};
 };
 
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts 
b/arch/arm/boot/dts/stm32h743i-disco.dts
index 45e088c..83ef63d 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -66,6 +66,23 @@
clock-frequency = <2500>;
 };
 
+ {
+   status = "disabled";
+   pinctrl-0   = <_rmii>;
+   pinctrl-names   = "default";
+   phy-mode= "rmii";
+   phy-handle  = <>;
+
+   mdio0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+   };
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts 
b/arch/arm/boot/dts/stm32h743i-eval.dts
index 3f8e0c4..383c5bb 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -104,6 +104,23 @@
status = "okay";
 };
 
+ {
+   status = "disabled";
+   pinctrl-0   = <_rmii>;
+   pinctrl-names   = "default";
+   phy-mode= "rmii";
+   phy-handle  = <>;
+
+   mdio0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+   };
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
-- 
2.7.4

[PATCH V3 0/6] stmmac: add some fixes for stm32

[Christophe Roullier]

For common stmmac:
- Add support to set CSR Clock range selection in DT
For stm32mpu:
- Glue codes to support magic packet
- Glue codes to support all PHY config :
PHY_MODE (MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config
For stm32mcu:
- Add Ethernet support for stm32h7

Changes in V3:
- Reverse for syscfg management because it is manage by these patches
  https://lkml.org/lkml/2018/12/12/133
  https://lkml.org/lkml/2018/12/12/134
  https://lkml.org/lkml/2018/12/12/131
  https://lkml.org/lkml/2018/12/12/132


Christophe Roullier (6):
  net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c.
  net: ethernet: stmmac: update to support all PHY config for
stm32mp157c.
  dt-bindings: net: stmmac: add phys config properties
  net: ethernet: stmmac: add management of clk_csr property
  dt-bindings: net: stmmac: remove syscfg clock property
  ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it
for eval and disco boards

 .../devicetree/bindings/net/stm32-dwmac.txt|   9 +-
 arch/arm/boot/dts/stm32h743-pinctrl.dtsi   |  15 +++
 arch/arm/boot/dts/stm32h743.dtsi   |  13 ++
 arch/arm/boot/dts/stm32h743i-disco.dts |  17 +++
 arch/arm/boot/dts/stm32h743i-eval.dts  |  17 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c  | 135 +
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   3 +
 7 files changed, 183 insertions(+), 26 deletions(-)

-- 
2.7.4

[PATCH V3 4/6] net: ethernet: stmmac: add management of clk_csr property

[Christophe Roullier]

In Documentation stmmac.txt there is possibility to
fixed CSR Clock range selection with property clk_csr.
This patch add the management of this property
For example to use it, add in your ethernet node DT:
clk_csr = <3>;

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 2b800ce..3031f2b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -408,6 +408,9 @@ stmmac_probe_config_dt(struct platform_device *pdev, const 
char **mac)
/* Default to phy auto-detection */
plat->phy_addr = -1;
 
+   /* Get clk_csr from device tree */
+   of_property_read_u32(np, "clk_csr", >clk_csr);
+
/* "snps,phy-addr" is not a standard property. Mark it as deprecated
 * and warn of its use. Remove this when phy node support is added.
 */
-- 
2.7.4

[PATCH V3 1/6] net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c.

[Christophe Roullier]

Add glue codes to support magic packet on stm32mp157c

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 30 ++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 7e2e79d..d1cf145 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -42,6 +42,7 @@ struct stm32_dwmac {
struct clk *clk_ethstp;
struct clk *syscfg_clk;
bool int_phyclk;/* Clock from RCC to drive PHY */
+   int irq_pwr_wakeup;
u32 mode_reg;   /* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
@@ -232,7 +233,9 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
 static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
   struct device *dev)
 {
+   struct platform_device *pdev = to_platform_device(dev);
struct device_node *np = dev->of_node;
+   int err = 0;
 
dwmac->int_phyclk = of_property_read_bool(np, "st,int-phyclk");
 
@@ -260,7 +263,26 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
return PTR_ERR(dwmac->syscfg_clk);
}
 
-   return 0;
+   /* Get IRQ information early to have an ability to ask for deferred
+* probe if needed before we went too far with resource allocation.
+*/
+   dwmac->irq_pwr_wakeup = platform_get_irq_byname(pdev,
+   "stm32_pwr_wakeup");
+   if (!dwmac->int_phyclk && dwmac->irq_pwr_wakeup >= 0) {
+   err = device_init_wakeup(>dev, true);
+   if (err) {
+   dev_err(>dev, "Failed to init wake up irq\n");
+   return err;
+   }
+   err = dev_pm_set_dedicated_wake_irq(>dev,
+   dwmac->irq_pwr_wakeup);
+   if (err) {
+   dev_err(>dev, "Failed to set wake up irq\n");
+   device_init_wakeup(>dev, false);
+   }
+   device_set_wakeup_enable(>dev, false);
+   }
+   return err;
 }
 
 static int stm32_dwmac_probe(struct platform_device *pdev)
@@ -326,9 +348,15 @@ static int stm32_dwmac_remove(struct platform_device *pdev)
struct net_device *ndev = platform_get_drvdata(pdev);
struct stmmac_priv *priv = netdev_priv(ndev);
int ret = stmmac_dvr_remove(>dev);
+   struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
 
stm32_dwmac_clk_disable(priv->plat->bsp_priv);
 
+   if (dwmac->irq_pwr_wakeup >= 0) {
+   dev_pm_clear_wake_irq(>dev);
+   device_init_wakeup(>dev, false);
+   }
+
return ret;
 }
 
-- 
2.7.4

[PATCH V3 3/6] dt-bindings: net: stmmac: add phys config properties

[Christophe Roullier]

Add properties to support all Phy config
 PHY_MODE   (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
 PHY wo crystal (50Mhz), No 125Mhz from PHY config.

Signed-off-by: Christophe Roullier 
---
 Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt 
b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index 1341012..3524e80 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -24,9 +24,9 @@ Required properties:
   encompases the glue register, and the offset of the control 
register.
 
 Optional properties:
-- clock-names: For MPU family "mac-clk-ck" for PHY without quartz
-- st,int-phyclk (boolean) :  valid only where PHY do not have quartz and need 
to be clock
-  by RCC
+- clock-names: For MPU family "eth-ck" for PHY without quartz
+- st,eth-clk-sel (boolean) : set this property in RGMII PHY when you want to 
select RCC clock instead of ETH_CLK125.
+- st,eth-ref-clk-sel (boolean) :  set this property in RMII mode when you have 
PHY without crystal 50MHz and want to select RCC clock instead of ETH_REF_CLK.
 
 Example:
 
-- 
2.7.4

Re: [PATCH V2 3/8] dt-bindings: net: stmmac: add phys config properties

[Christophe ROULLIER]

On 2/23/19 1:16 AM, Rob Herring wrote:
> On Fri, Feb 22, 2019 at 09:28:04AM +0100, Christophe Roullier wrote:
>> Add properties to support all Phy config
>>   PHY_MODE   (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
>>   PHY wo crystal (50Mhz), No 125Mhz from PHY config.
>>
>> Signed-off-by: Christophe Roullier 
>> ---
>>   Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt 
>> b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
>> index 1341012..f42dc68 100644
>> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
>> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
>> @@ -24,9 +24,9 @@ Required properties:
>> encompases the glue register, and the offset of the control 
>> register.
>>   
>>   Optional properties:
>> -- clock-names: For MPU family "mac-clk-ck" for PHY without quartz
>> -- st,int-phyclk (boolean) :  valid only where PHY do not have quartz and 
>> need to be clock
>> -   by RCC
> 
> You can't just remove properties.

There is no risk to remove/rename these 2 properties, because it is 
specific board which is never deployed.
With new properties (renaming clock (eth-ck) + st,eth_clk_sel and 
st,eth_ref_clk_sel, we are managed all kind of specific boards stm32mp1
So no risk of backward compatible.

> 
>> +- clock-names: For MPU family "eth-ck" for PHY without quartz
>> +- st,eth_clk_sel (boolean) : set this property in RGMII PHY when you do not 
>> want use 125Mhz
>> +- st,eth_ref_clk_sel (boolean) :  set this property in RMII mode when you 
>> have PHY without crystal 50MHz
> 
> s/_/-/
> 
> 'sel' I assume is short for select, but the naming here and description
> don't really tell me what I'm getting.
> 

Ok, Rob, I will update with your recommendations

> Rob
> 

[PATCH V2 3/8] dt-bindings: net: stmmac: add phys config properties

[Christophe Roullier]

Add properties to support all Phy config
 PHY_MODE   (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
 PHY wo crystal (50Mhz), No 125Mhz from PHY config.

Signed-off-by: Christophe Roullier 
---
 Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt 
b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index 1341012..f42dc68 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -24,9 +24,9 @@ Required properties:
   encompases the glue register, and the offset of the control 
register.
 
 Optional properties:
-- clock-names: For MPU family "mac-clk-ck" for PHY without quartz
-- st,int-phyclk (boolean) :  valid only where PHY do not have quartz and need 
to be clock
-  by RCC
+- clock-names: For MPU family "eth-ck" for PHY without quartz
+- st,eth_clk_sel (boolean) : set this property in RGMII PHY when you do not 
want use 125Mhz
+- st,eth_ref_clk_sel (boolean) :  set this property in RMII mode when you have 
PHY without crystal 50MHz
 
 Example:
 
-- 
2.7.4

[PATCH V2 4/8] net: ethernet: stmmac: add management of clk_csr property

[Christophe Roullier]

In Documentation stmmac.txt there is possibility to
fixed CSR Clock range selection with property clk_csr.
This patch add the management of this property
For example to use it, add in your ethernet node DT:
clk_csr = <3>;

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 2b800ce..3031f2b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -408,6 +408,9 @@ stmmac_probe_config_dt(struct platform_device *pdev, const 
char **mac)
/* Default to phy auto-detection */
plat->phy_addr = -1;
 
+   /* Get clk_csr from device tree */
+   of_property_read_u32(np, "clk_csr", >clk_csr);
+
/* "snps,phy-addr" is not a standard property. Mark it as deprecated
 * and warn of its use. Remove this when phy node support is added.
 */
-- 
2.7.4

[PATCH V2 0/8] stmmac: add some fixes for stm32

[Christophe Roullier]

For common stmmac:
- Add support to set CSR Clock range selection in DT
For stm32mpu:
- Glue codes to support magic packet
- Glue codes to support all PHY config :
PHY_MODE (MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config
For stm32mcu:
- Add Ethernet support for stm32h7
- Add syscfg clk support for stm32f4

Changes in V2:
  Apply remarks from andrew lunn
- add all interfaces RGMII* 
- reg value should be the same as ethernet-phy@X

Christophe Roullier (8):
  net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c.
  net: ethernet: stmmac: update to support all PHY config for
stm32mp157c.
  dt-bindings: net: stmmac: add phys config properties
  net: ethernet: stmmac: add management of clk_csr property
  net: ethernet: stmmac: update to be compatible with MCU family
(stm32f4, stm32h7)
  dt-bindings: net: stmmac: add syscfg clock property
  ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it
for eval and disco boards
  ARM: dts: stm32: add syscfg clock support for Ethernet on STM32F429
SoC

 .../devicetree/bindings/net/stm32-dwmac.txt|  10 +-
 arch/arm/boot/dts/stm32f429.dtsi   |   6 +-
 arch/arm/boot/dts/stm32h743-pinctrl.dtsi   |  15 ++
 arch/arm/boot/dts/stm32h743.dtsi   |  19 +++
 arch/arm/boot/dts/stm32h743i-disco.dts |  17 ++
 arch/arm/boot/dts/stm32h743i-eval.dts  |  17 ++
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c  | 182 +
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   3 +
 8 files changed, 233 insertions(+), 36 deletions(-)

-- 
2.7.4

[PATCH V2 1/8] net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c.

[Christophe Roullier]

Add glue codes to support magic packet on stm32mp157c

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 30 ++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 7e2e79d..d1cf145 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -42,6 +42,7 @@ struct stm32_dwmac {
struct clk *clk_ethstp;
struct clk *syscfg_clk;
bool int_phyclk;/* Clock from RCC to drive PHY */
+   int irq_pwr_wakeup;
u32 mode_reg;   /* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
@@ -232,7 +233,9 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
 static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
   struct device *dev)
 {
+   struct platform_device *pdev = to_platform_device(dev);
struct device_node *np = dev->of_node;
+   int err = 0;
 
dwmac->int_phyclk = of_property_read_bool(np, "st,int-phyclk");
 
@@ -260,7 +263,26 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
return PTR_ERR(dwmac->syscfg_clk);
}
 
-   return 0;
+   /* Get IRQ information early to have an ability to ask for deferred
+* probe if needed before we went too far with resource allocation.
+*/
+   dwmac->irq_pwr_wakeup = platform_get_irq_byname(pdev,
+   "stm32_pwr_wakeup");
+   if (!dwmac->int_phyclk && dwmac->irq_pwr_wakeup >= 0) {
+   err = device_init_wakeup(>dev, true);
+   if (err) {
+   dev_err(>dev, "Failed to init wake up irq\n");
+   return err;
+   }
+   err = dev_pm_set_dedicated_wake_irq(>dev,
+   dwmac->irq_pwr_wakeup);
+   if (err) {
+   dev_err(>dev, "Failed to set wake up irq\n");
+   device_init_wakeup(>dev, false);
+   }
+   device_set_wakeup_enable(>dev, false);
+   }
+   return err;
 }
 
 static int stm32_dwmac_probe(struct platform_device *pdev)
@@ -326,9 +348,15 @@ static int stm32_dwmac_remove(struct platform_device *pdev)
struct net_device *ndev = platform_get_drvdata(pdev);
struct stmmac_priv *priv = netdev_priv(ndev);
int ret = stmmac_dvr_remove(>dev);
+   struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
 
stm32_dwmac_clk_disable(priv->plat->bsp_priv);
 
+   if (dwmac->irq_pwr_wakeup >= 0) {
+   dev_pm_clear_wake_irq(>dev);
+   device_init_wakeup(>dev, false);
+   }
+
return ret;
 }
 
-- 
2.7.4

[PATCH V2 2/8] net: ethernet: stmmac: update to support all PHY config for stm32mp157c.

[Christophe Roullier]

Update glue codes to support all PHY config on stm32mp157c
 PHY_MODE   (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config.

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 105 +-
 1 file changed, 85 insertions(+), 20 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index d1cf145..8d5150a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -25,9 +25,24 @@
 
 #define SYSCFG_MCU_ETH_MASKBIT(23)
 #define SYSCFG_MP1_ETH_MASKGENMASK(23, 16)
+#define SYSCFG_PMCCLRR_OFFSET  0x40
 
 #define SYSCFG_PMCR_ETH_CLK_SELBIT(16)
 #define SYSCFG_PMCR_ETH_REF_CLK_SELBIT(17)
+
+/*  Ethernet PHY interface selection in register SYSCFG Configuration
+ *--
+ * src  |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
+ *--
+ * MII   |   0  |   0|   0|   1   |
+ *--
+ * GMII  |   0  |   0|   0|   0   |
+ *--
+ * RGMII |   0  |   0|   1|  n/a  |
+ *--
+ * RMII  |   1  |   0|   0|  n/a  |
+ *--
+ */
 #define SYSCFG_PMCR_ETH_SEL_MIIBIT(20)
 #define SYSCFG_PMCR_ETH_SEL_RGMII  BIT(21)
 #define SYSCFG_PMCR_ETH_SEL_RMII   BIT(23)
@@ -35,15 +50,54 @@
 #define SYSCFG_MCU_ETH_SEL_MII 0
 #define SYSCFG_MCU_ETH_SEL_RMII1
 
+/* STM32MP1 register definitions
+ *
+ * Below table summarizes the clock requirement and clock sources for
+ * supported phy interface modes.
+ * __
+ *|PHY_MODE | Normal | PHY wo crystal|   PHY wo crystal   |No 125Mhz from PHY|
+ *| ||  25MHz|50MHz   |  |
+ * ---
+ *|  MII|   -   | eth-ck|n/a |   n/a|
+ *| ||  ||  |
+ * ---
+ *|  GMII   |   -   | eth-ck|n/a |   n/a|
+ *| ||   || |
+ * ---
+ *| RGMII   |   -   | eth-ck|n/a |  eth-ck (no pin) |
+ *| ||   ||  st,eth_clk_sel  |
+ * ---
+ *| RMII|   -   | eth-ck|  eth-ck|   n/a|
+ *| ||  | st,eth_ref_clk_sel |  |
+ * ---
+ *
+ * BIT(17) : set this bit in RMII mode when you have PHY without crystal 50MHz
+ * BIT(16) : set this bit in GMII/RGMII PHY when you do not want use 125Mhz
+ * from PHY
+ *-
+ * src  | BIT(17)   |   BIT(16)  |
+ *-
+ * MII   |   n/a| n/a|
+ *-
+ * GMII  |   n/a |   st,eth_clk_sel   |
+ *-
+ * RGMII |   n/a |   st,eth_clk_sel   |
+ *-
+ * RMII  |   st,eth_ref_clk_sel | n/a|
+ *-
+ *
+ */
+
 struct stm32_dwmac {
struct clk *clk_tx;
struct clk *clk_rx;
struct clk *clk_eth_ck;
struct clk *clk_ethstp;
struct clk *syscfg_clk;
-   bool int_phyclk;/* Clock from RCC to drive PHY */
+   int eth_clk_sel_reg;
+   int eth_ref_clk_sel_reg;
int irq_pwr_wakeup;
-   u32 mode_reg;   /* MAC glue-logic mode register */
+   u32 mode_reg;/* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
const struct stm32_ops *ops;
@@ -103,7 +157,7 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, 
bool prepare)
if (ret)
return ret;
 
-   if (dwmac->int_phyclk) {
+   if (dwmac->clk_eth_ck) {
ret = clk_prepare_enable(dwmac->clk_eth_ck);
if (ret) {
clk_disable_unprepare(dwmac->syscfg_clk);
@@ -112,7 +166,7 @@ static int stm32mp1

[PATCH V2 7/8] ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it for eval and disco boards

[Christophe Roullier]

Synopsys GMAC 4.10 is used. And Phy mode for eval and disco is RMII
with PHY SMSC LAN8742

Signed-off-by: Christophe Roullier 
---
 arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 15 +++
 arch/arm/boot/dts/stm32h743.dtsi | 19 +++
 arch/arm/boot/dts/stm32h743i-disco.dts   | 17 +
 arch/arm/boot/dts/stm32h743i-eval.dts| 17 +
 4 files changed, 68 insertions(+)

diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index 24be8e6..980b276 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -173,6 +173,21 @@
};
};
 
+   ethernet_rmii: rmii@0 {
+   pins {
+   pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+   slew-rate = <2>;
+   };
+   };
+
usart1_pins: usart1@0 {
pins1 {
pinmux = ; 
/* USART1_TX */
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index cbdd69c..f6384af 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -511,6 +511,25 @@
status = "disabled";
};
};
+
+   syscfg: system-config@58000400 {
+   compatible = "syscon";
+   reg = <0x58000400 0x400>;
+   };
+
+   mac: ethernet@40028000 {
+   compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
+   reg = <0x40028000 0x8000>;
+   reg-names = "stmmaceth";
+   interrupts = <61>;
+   interrupt-names = "macirq";
+   clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx",
+   "syscfg-clk";
+   clocks = < ETH1MAC_CK>, < ETH1TX_CK>, < 
ETH1RX_CK>, < SYSCFG_CK>;
+   st,syscon = < 0x4>;
+   snps,pbl = <8>;
+   status = "disabled";
+   };
};
 };
 
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts 
b/arch/arm/boot/dts/stm32h743i-disco.dts
index 45e088c..26ddd52 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -66,6 +66,23 @@
clock-frequency = <2500>;
 };
 
+ {
+   status = "okay";
+   pinctrl-0   = <_rmii>;
+   pinctrl-names   = "default";
+   phy-mode= "rmii";
+   phy-handle  = <>;
+
+   mdio0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+   };
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts 
b/arch/arm/boot/dts/stm32h743i-eval.dts
index 3f8e0c4..c1c1cc1 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -104,6 +104,23 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+   pinctrl-0   = <_rmii>;
+   pinctrl-names   = "default";
+   phy-mode= "rmii";
+   phy-handle  = <>;
+
+   mdio0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+   };
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
-- 
2.7.4

[PATCH V2 6/8] dt-bindings: net: stmmac: add syscfg clock property

[Christophe Roullier]

Need syscfg clock for MCU family in case bootloader does not
activate it.

Signed-off-by: Christophe Roullier 
---
 Documentation/devicetree/bindings/net/stm32-dwmac.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt 
b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index f42dc68..524f8a0 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -14,8 +14,8 @@ Required properties:
 - clock-names: Should be "stmmaceth" for the host clock.
   Should be "mac-clk-tx" for the MAC TX clock.
   Should be "mac-clk-rx" for the MAC RX clock.
-  For MPU family need to add also "ethstp" for power mode clock 
and,
-  "syscfg-clk" for SYSCFG clock.
+  Should be "syscfg-clk" for the SYSCFG clock.
+  For MPU family need to add also "ethstp" for power mode clock
 - interrupt-names: Should contain a list of interrupt names corresponding to
the interrupts in the interrupts property, if available.
   Should be "macirq" for the main MAC IRQ
-- 
2.7.4

[PATCH V2 8/8] ARM: dts: stm32: add syscfg clock support for Ethernet on STM32F429 SoC

[Christophe Roullier]

This patch add syscfg clock support for Ethernet of the STM32F429 SoC.
Needed if bootloader do not manage it.

Signed-off-by: Christophe Roullier 
---
 arch/arm/boot/dts/stm32f429.dtsi | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 8d6f028..6f78346 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -657,10 +657,12 @@
reg-names = "stmmaceth";
interrupts = <61>;
interrupt-names = "macirq";
-   clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+   clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx",
+   "syscfg-clk";
clocks = < 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
< 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
-   < 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
+   < 0 STM32F4_AHB1_CLOCK(ETHMACRX)>,
+   < 0 STM32F4_APB2_CLOCK(SYSCFG)>;
st,syscon = < 0x4>;
snps,pbl = <8>;
snps,mixed-burst;
-- 
2.7.4

[PATCH V2 5/8] net: ethernet: stmmac: update to be compatible with MCU family (stm32f4, stm32h7)

[Christophe Roullier]

Update glue codes to be compatible with MCU family.

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 ++-
 1 file changed, 41 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 8d5150a..66d95c2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -6,7 +6,6 @@
  * License terms:  GNU General Public License (GPL), version 2
  *
  */
-
 #include 
 #include 
 #include 
@@ -119,12 +118,6 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data 
*plat_dat)
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
int ret;
 
-   if (dwmac->ops->set_mode) {
-   ret = dwmac->ops->set_mode(plat_dat);
-   if (ret)
-   return ret;
-   }
-
ret = clk_prepare_enable(dwmac->clk_tx);
if (ret)
return ret;
@@ -139,13 +132,26 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data 
*plat_dat)
 
if (dwmac->ops->clk_prepare) {
ret = dwmac->ops->clk_prepare(dwmac, true);
+   if (ret)
+   goto err_clk_disable;
+   }
+
+   if (dwmac->ops->set_mode) {
+   ret = dwmac->ops->set_mode(plat_dat);
if (ret) {
-   clk_disable_unprepare(dwmac->clk_rx);
-   clk_disable_unprepare(dwmac->clk_tx);
+   if (dwmac->ops->clk_prepare)
+   dwmac->ops->clk_prepare(dwmac, false);
+   goto err_clk_disable;
}
}
 
return ret;
+
+err_clk_disable:
+   clk_disable_unprepare(dwmac->clk_rx);
+   clk_disable_unprepare(dwmac->clk_tx);
+
+   return ret;
 }
 
 static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
@@ -243,7 +249,19 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data 
*plat_dat)
}
 
return regmap_update_bits(dwmac->regmap, reg,
-dwmac->ops->syscfg_eth_mask, val);
+dwmac->ops->syscfg_eth_mask, val << 23);
+}
+
+static int stm32mcu_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
+{
+   int ret = 0;
+
+   if (prepare)
+   ret = clk_prepare_enable(dwmac->syscfg_clk);
+   else
+   clk_disable_unprepare(dwmac->syscfg_clk);
+
+   return ret;
 }
 
 static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
@@ -350,6 +368,17 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
return err;
 }
 
+static int stm32mcu_parse_data(struct stm32_dwmac *dwmac,
+  struct device *dev)
+{
+   /*  Clock for sysconfig */
+   dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
+   if (IS_ERR(dwmac->syscfg_clk))
+   dev_warn(dev, "No syscfg clock provided...\n");
+
+   return 0;
+}
+
 static int stm32_dwmac_probe(struct platform_device *pdev)
 {
struct plat_stmmacenet_data *plat_dat;
@@ -496,7 +525,9 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
 
 static struct stm32_ops stm32mcu_dwmac_data = {
.set_mode = stm32mcu_set_mode,
+   .clk_prepare = stm32mcu_clk_prepare,
.suspend = stm32mcu_suspend,
+   .parse_data = stm32mcu_parse_data,
.syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
 };
 
-- 
2.7.4

Re: [PATCH 2/8] net: ethernet: stmmac: update to support all PHY config for stm32mp157c.

[Christophe ROULLIER]

On 2/14/19 4:15 PM, Andrew Lunn wrote:
>> Sorry, I've misunderstood your question ;-)
>>
>> And you spoke about :
>>
>> case PHY_INTERFACE_MODE_RGMII:
>> case PHY_INTERFACE_MODE_RGMII_ID:
>> case PHY_INTERFACE_MODE_RGMII_RXID:
>> case PHY_INTERFACE_MODE_RGMII_TXID:
>>
>> So in my setup I've only RGMII interface, so I've never tested 3 others
>> interfaces (_ID, _RXID, _TXID).
>>
>> So do I need to add cases in my driver ?
> 
> Yes. They all indicate the MAC should be using RGMII.
> 
> This appears to be an old issue, but now would be a good time to fix
> it.
> 
>   Andrew
> 
Ok Andrew, I will update with these

Thanks

Christophe

Re: [PATCH 2/8] net: ethernet: stmmac: update to support all PHY config for stm32mp157c.

[Christophe ROULLIER]

On 2/14/19 2:40 PM, Andrew Lunn wrote:
>   On Thu, Feb 14, 2019 at 07:45:57AM +0100, Christophe Roullier wrote:
>> @@ -131,19 +185,19 @@ static int stm32mp1_set_mode(struct 
>> plat_stmmacenet_data *plat_dat)
>>  case PHY_INTERFACE_MODE_RGMII:
>>  val = SYSCFG_PMCR_ETH_SEL_RGMII;
>> -if (dwmac->int_phyclk)
>> +if (dwmac->eth_clk_sel_reg)
>>  val |= SYSCFG_PMCR_ETH_CLK_SEL;
>>  pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
>>  break;
> 
> Hi Christophe
> 
> This code should handle all 4 PHY_INTERFACE_MODE_RGMII* values.
> 
>   Andrew
> 


ReReHi Andrew,

Sorry, I've misunderstood your question ;-)

And you spoke about :

case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:

So in my setup I've only RGMII interface, so I've never tested 3 others 
interfaces (_ID, _RXID, _TXID).

So do I need to add cases in my driver ?

Thanks

Christophe

Re: [PATCH 7/8] ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it for eval and disco boards

[Christophe ROULLIER]

On 2/14/19 2:44 PM, Andrew Lunn wrote:
> On Thu, Feb 14, 2019 at 07:46:02AM +0100, Christophe Roullier wrote:
>> +mdio0 {
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +compatible = "snps,dwmac-mdio";
>> +phy1: ethernet-phy@1 {
>> +reg = <0>;
>> +};
> 
> The reg value should be the same as ethernet-phy@X.
> 
>  Andrew
>> +mdio0 {
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +compatible = "snps,dwmac-mdio";
>> +phy1: ethernet-phy@1 {
>> +reg = <0>;
>> +};
> 
> Here as well.
> 
>   Andrew
> 

Hi Andrew,

Ok I will update.

Thanks.

Christophe

Re: [PATCH 2/8] net: ethernet: stmmac: update to support all PHY config for stm32mp157c.

[Christophe ROULLIER]

On 2/14/19 2:40 PM, Andrew Lunn wrote:
>   On Thu, Feb 14, 2019 at 07:45:57AM +0100, Christophe Roullier wrote:
>> @@ -131,19 +185,19 @@ static int stm32mp1_set_mode(struct 
>> plat_stmmacenet_data *plat_dat)
>>  case PHY_INTERFACE_MODE_RGMII:
>>  val = SYSCFG_PMCR_ETH_SEL_RGMII;
>> -if (dwmac->int_phyclk)
>> +if (dwmac->eth_clk_sel_reg)
>>  val |= SYSCFG_PMCR_ETH_CLK_SEL;
>>  pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
>>  break;
> 
> Hi Christophe
> 
> This code should handle all 4 PHY_INTERFACE_MODE_RGMII* values.
> 
>   Andrew
> 

Hi Andrew,

For RGMII we are supporting 3 modes:
- normal mode (with PHY with quartz)
- Phy wo crystal and phy is clocking with PLL to 25Mhz.
- other mode where we used PLL from RCC (125Mhz) to clock Ethernet 
IP (save one pin "ETH_CK125")

In driver source code I put table to sum-up all configs supported for 
each phy mode:
+ * Below table summarizes the clock requirement and clock sources for
+ * supported phy interface modes.
+ * 
__
+ *|PHY_MODE | Normal | PHY wo crystal|   PHY wo crystal   |No 125Mhz 
from PHY|
+ *| ||  25MHz|50MHz   | 
  |
+ * 
---
+ *|  MII|   -   | eth-ck|n/a |   n/a|
+ *| ||  ||  |
+ * 
---
+ *|  GMII   |   -   | eth-ck|n/a |   n/a|
+ *| ||   || |
+ * 
---
+ *| RGMII   |   -   | eth-ck|n/a |  eth-ck (no pin) |
+ *| ||   || 
st,eth_clk_sel  |
+ * 
---
+ *| RMII|   -   | eth-ck|  eth-ck|   n/a|
+ *| ||  | st,eth_ref_clk_sel |  |
+ * 
---

Regards,

Christophe

[PATCH 0/8] stmmac: add some fixes for stm32

[Christophe Roullier]

For common stmmac:
- Add support to set CSR Clock range selection in DT
For stm32mpu:
- Glue codes to support magic packet
- Glue codes to support all PHY config :
PHY_MODE (MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config
For stm32mcu:
- Add Ethernet support for stm32h7
- Add syscfg clk support for stm32f4

Christophe Roullier (8):
  net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c.
  net: ethernet: stmmac: update to support all PHY config for
stm32mp157c.
  dt-bindings: net: stmmac: add phys config properties
  net: ethernet: stmmac: add management of clk_csr property
  net: ethernet: stmmac: update to be compatible with MCU family
(stm32f4, stm32h7)
  dt-bindings: net: stmmac: add syscfg clock property
  ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it
for eval and disco boards
  ARM: dts: stm32: add syscfg clock support for Ethernet on STM32F429
SoC

 .../devicetree/bindings/net/stm32-dwmac.txt|  10 +-
 arch/arm/boot/dts/stm32f429.dtsi   |   6 +-
 arch/arm/boot/dts/stm32h743-pinctrl.dtsi   |  15 ++
 arch/arm/boot/dts/stm32h743.dtsi   |  19 +++
 arch/arm/boot/dts/stm32h743i-disco.dts |  17 ++
 arch/arm/boot/dts/stm32h743i-eval.dts  |  17 ++
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c  | 179 +
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   3 +
 8 files changed, 230 insertions(+), 36 deletions(-)

-- 
2.7.4

[PATCH 4/8] net: ethernet: stmmac: add management of clk_csr property

[Christophe Roullier]

In Documentation stmmac.txt there is possibility to
fixed CSR Clock range selection with property clk_csr.
This patch add the management of this property
For example to use it, add in your ethernet node DT:
clk_csr = <3>;

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 2b800ce..3031f2b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -408,6 +408,9 @@ stmmac_probe_config_dt(struct platform_device *pdev, const 
char **mac)
/* Default to phy auto-detection */
plat->phy_addr = -1;
 
+   /* Get clk_csr from device tree */
+   of_property_read_u32(np, "clk_csr", >clk_csr);
+
/* "snps,phy-addr" is not a standard property. Mark it as deprecated
 * and warn of its use. Remove this when phy node support is added.
 */
-- 
2.7.4

[PATCH 6/8] dt-bindings: net: stmmac: add syscfg clock property

[Christophe Roullier]

Need syscfg clock for MCU family in case bootloader does not
activate it.

Signed-off-by: Christophe Roullier 
---
 Documentation/devicetree/bindings/net/stm32-dwmac.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt 
b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index f42dc68..524f8a0 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -14,8 +14,8 @@ Required properties:
 - clock-names: Should be "stmmaceth" for the host clock.
   Should be "mac-clk-tx" for the MAC TX clock.
   Should be "mac-clk-rx" for the MAC RX clock.
-  For MPU family need to add also "ethstp" for power mode clock 
and,
-  "syscfg-clk" for SYSCFG clock.
+  Should be "syscfg-clk" for the SYSCFG clock.
+  For MPU family need to add also "ethstp" for power mode clock
 - interrupt-names: Should contain a list of interrupt names corresponding to
the interrupts in the interrupts property, if available.
   Should be "macirq" for the main MAC IRQ
-- 
2.7.4

[PATCH 5/8] net: ethernet: stmmac: update to be compatible with MCU family (stm32f4, stm32h7)

[Christophe Roullier]

Update glue codes to be compatible with MCU family.

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 ++-
 1 file changed, 41 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index cee59e8..20a2daa 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -6,7 +6,6 @@
  * License terms:  GNU General Public License (GPL), version 2
  *
  */
-
 #include 
 #include 
 #include 
@@ -119,12 +118,6 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data 
*plat_dat)
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
int ret;
 
-   if (dwmac->ops->set_mode) {
-   ret = dwmac->ops->set_mode(plat_dat);
-   if (ret)
-   return ret;
-   }
-
ret = clk_prepare_enable(dwmac->clk_tx);
if (ret)
return ret;
@@ -139,13 +132,26 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data 
*plat_dat)
 
if (dwmac->ops->clk_prepare) {
ret = dwmac->ops->clk_prepare(dwmac, true);
+   if (ret)
+   goto err_clk_disable;
+   }
+
+   if (dwmac->ops->set_mode) {
+   ret = dwmac->ops->set_mode(plat_dat);
if (ret) {
-   clk_disable_unprepare(dwmac->clk_rx);
-   clk_disable_unprepare(dwmac->clk_tx);
+   if (dwmac->ops->clk_prepare)
+   dwmac->ops->clk_prepare(dwmac, false);
+   goto err_clk_disable;
}
}
 
return ret;
+
+err_clk_disable:
+   clk_disable_unprepare(dwmac->clk_rx);
+   clk_disable_unprepare(dwmac->clk_tx);
+
+   return ret;
 }
 
 static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
@@ -240,7 +246,19 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data 
*plat_dat)
}
 
return regmap_update_bits(dwmac->regmap, reg,
-dwmac->ops->syscfg_eth_mask, val);
+dwmac->ops->syscfg_eth_mask, val << 23);
+}
+
+static int stm32mcu_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
+{
+   int ret = 0;
+
+   if (prepare)
+   ret = clk_prepare_enable(dwmac->syscfg_clk);
+   else
+   clk_disable_unprepare(dwmac->syscfg_clk);
+
+   return ret;
 }
 
 static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
@@ -347,6 +365,17 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
return err;
 }
 
+static int stm32mcu_parse_data(struct stm32_dwmac *dwmac,
+  struct device *dev)
+{
+   /*  Clock for sysconfig */
+   dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
+   if (IS_ERR(dwmac->syscfg_clk))
+   dev_warn(dev, "No syscfg clock provided...\n");
+
+   return 0;
+}
+
 static int stm32_dwmac_probe(struct platform_device *pdev)
 {
struct plat_stmmacenet_data *plat_dat;
@@ -493,7 +522,9 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
 
 static struct stm32_ops stm32mcu_dwmac_data = {
.set_mode = stm32mcu_set_mode,
+   .clk_prepare = stm32mcu_clk_prepare,
.suspend = stm32mcu_suspend,
+   .parse_data = stm32mcu_parse_data,
.syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
 };
 
-- 
2.7.4

[PATCH 2/8] net: ethernet: stmmac: update to support all PHY config for stm32mp157c.

[Christophe Roullier]

Update glue codes to support all PHY config on stm32mp157c
 PHY_MODE   (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config.

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 102 +-
 1 file changed, 82 insertions(+), 20 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index d1cf145..cee59e8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -25,9 +25,24 @@
 
 #define SYSCFG_MCU_ETH_MASKBIT(23)
 #define SYSCFG_MP1_ETH_MASKGENMASK(23, 16)
+#define SYSCFG_PMCCLRR_OFFSET  0x40
 
 #define SYSCFG_PMCR_ETH_CLK_SELBIT(16)
 #define SYSCFG_PMCR_ETH_REF_CLK_SELBIT(17)
+
+/*  Ethernet PHY interface selection in register SYSCFG Configuration
+ *--
+ * src  |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
+ *--
+ * MII   |   0  |   0|   0|   1   |
+ *--
+ * GMII  |   0  |   0|   0|   0   |
+ *--
+ * RGMII |   0  |   0|   1|  n/a  |
+ *--
+ * RMII  |   1  |   0|   0|  n/a  |
+ *--
+ */
 #define SYSCFG_PMCR_ETH_SEL_MIIBIT(20)
 #define SYSCFG_PMCR_ETH_SEL_RGMII  BIT(21)
 #define SYSCFG_PMCR_ETH_SEL_RMII   BIT(23)
@@ -35,15 +50,54 @@
 #define SYSCFG_MCU_ETH_SEL_MII 0
 #define SYSCFG_MCU_ETH_SEL_RMII1
 
+/* STM32MP1 register definitions
+ *
+ * Below table summarizes the clock requirement and clock sources for
+ * supported phy interface modes.
+ * __
+ *|PHY_MODE | Normal | PHY wo crystal|   PHY wo crystal   |No 125Mhz from PHY|
+ *| ||  25MHz|50MHz   |  |
+ * ---
+ *|  MII|   -   | eth-ck|n/a |   n/a|
+ *| ||  ||  |
+ * ---
+ *|  GMII   |   -   | eth-ck|n/a |   n/a|
+ *| ||   || |
+ * ---
+ *| RGMII   |   -   | eth-ck|n/a |  eth-ck (no pin) |
+ *| ||   ||  st,eth_clk_sel  |
+ * ---
+ *| RMII|   -   | eth-ck|  eth-ck|   n/a|
+ *| ||  | st,eth_ref_clk_sel |  |
+ * ---
+ *
+ * BIT(17) : set this bit in RMII mode when you have PHY without crystal 50MHz
+ * BIT(16) : set this bit in GMII/RGMII PHY when you do not want use 125Mhz
+ * from PHY
+ *-
+ * src  | BIT(17)   |   BIT(16)  |
+ *-
+ * MII   |   n/a| n/a|
+ *-
+ * GMII  |   n/a |   st,eth_clk_sel   |
+ *-
+ * RGMII |   n/a |   st,eth_clk_sel   |
+ *-
+ * RMII  |   st,eth_ref_clk_sel | n/a|
+ *-
+ *
+ */
+
 struct stm32_dwmac {
struct clk *clk_tx;
struct clk *clk_rx;
struct clk *clk_eth_ck;
struct clk *clk_ethstp;
struct clk *syscfg_clk;
-   bool int_phyclk;/* Clock from RCC to drive PHY */
+   int eth_clk_sel_reg;
+   int eth_ref_clk_sel_reg;
int irq_pwr_wakeup;
-   u32 mode_reg;   /* MAC glue-logic mode register */
+   u32 mode_reg;/* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
const struct stm32_ops *ops;
@@ -103,7 +157,7 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, 
bool prepare)
if (ret)
return ret;
 
-   if (dwmac->int_phyclk) {
+   if (dwmac->clk_eth_ck) {
ret = clk_prepare_enable(dwmac->clk_eth_ck);
if (ret) {
clk_disable_unprepare(dwmac->syscfg_clk);
@@ -112,7 +166,7 @@ static int stm32mp1

[PATCH 1/8] net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c.

[Christophe Roullier]

Add glue codes to support magic packet on stm32mp157c

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 30 ++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 7e2e79d..d1cf145 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -42,6 +42,7 @@ struct stm32_dwmac {
struct clk *clk_ethstp;
struct clk *syscfg_clk;
bool int_phyclk;/* Clock from RCC to drive PHY */
+   int irq_pwr_wakeup;
u32 mode_reg;   /* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
@@ -232,7 +233,9 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
 static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
   struct device *dev)
 {
+   struct platform_device *pdev = to_platform_device(dev);
struct device_node *np = dev->of_node;
+   int err = 0;
 
dwmac->int_phyclk = of_property_read_bool(np, "st,int-phyclk");
 
@@ -260,7 +263,26 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
return PTR_ERR(dwmac->syscfg_clk);
}
 
-   return 0;
+   /* Get IRQ information early to have an ability to ask for deferred
+* probe if needed before we went too far with resource allocation.
+*/
+   dwmac->irq_pwr_wakeup = platform_get_irq_byname(pdev,
+   "stm32_pwr_wakeup");
+   if (!dwmac->int_phyclk && dwmac->irq_pwr_wakeup >= 0) {
+   err = device_init_wakeup(>dev, true);
+   if (err) {
+   dev_err(>dev, "Failed to init wake up irq\n");
+   return err;
+   }
+   err = dev_pm_set_dedicated_wake_irq(>dev,
+   dwmac->irq_pwr_wakeup);
+   if (err) {
+   dev_err(>dev, "Failed to set wake up irq\n");
+   device_init_wakeup(>dev, false);
+   }
+   device_set_wakeup_enable(>dev, false);
+   }
+   return err;
 }
 
 static int stm32_dwmac_probe(struct platform_device *pdev)
@@ -326,9 +348,15 @@ static int stm32_dwmac_remove(struct platform_device *pdev)
struct net_device *ndev = platform_get_drvdata(pdev);
struct stmmac_priv *priv = netdev_priv(ndev);
int ret = stmmac_dvr_remove(>dev);
+   struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
 
stm32_dwmac_clk_disable(priv->plat->bsp_priv);
 
+   if (dwmac->irq_pwr_wakeup >= 0) {
+   dev_pm_clear_wake_irq(>dev);
+   device_init_wakeup(>dev, false);
+   }
+
return ret;
 }
 
-- 
2.7.4

[PATCH 3/8] dt-bindings: net: stmmac: add phys config properties

[Christophe Roullier]

Add properties to support all Phy config
 PHY_MODE   (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
 PHY wo crystal (50Mhz), No 125Mhz from PHY config.

Signed-off-by: Christophe Roullier 
---
 Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt 
b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index 1341012..f42dc68 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -24,9 +24,9 @@ Required properties:
   encompases the glue register, and the offset of the control 
register.
 
 Optional properties:
-- clock-names: For MPU family "mac-clk-ck" for PHY without quartz
-- st,int-phyclk (boolean) :  valid only where PHY do not have quartz and need 
to be clock
-  by RCC
+- clock-names: For MPU family "eth-ck" for PHY without quartz
+- st,eth_clk_sel (boolean) : set this property in RGMII PHY when you do not 
want use 125Mhz
+- st,eth_ref_clk_sel (boolean) :  set this property in RMII mode when you have 
PHY without crystal 50MHz
 
 Example:
 
-- 
2.7.4

[PATCH 8/8] ARM: dts: stm32: add syscfg clock support for Ethernet on STM32F429 SoC

[Christophe Roullier]

This patch add syscfg clock support for Ethernet of the STM32F429 SoC.
Needed if bootloader do not manage it.

Signed-off-by: Christophe Roullier 
---
 arch/arm/boot/dts/stm32f429.dtsi | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 8d6f028..6f78346 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -657,10 +657,12 @@
reg-names = "stmmaceth";
interrupts = <61>;
interrupt-names = "macirq";
-   clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+   clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx",
+   "syscfg-clk";
clocks = < 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
< 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
-   < 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
+   < 0 STM32F4_AHB1_CLOCK(ETHMACRX)>,
+   < 0 STM32F4_APB2_CLOCK(SYSCFG)>;
st,syscon = < 0x4>;
snps,pbl = <8>;
snps,mixed-burst;
-- 
2.7.4

[PATCH 7/8] ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it for eval and disco boards

[Christophe Roullier]

Synopsys GMAC 4.10 is used. And Phy mode for eval and disco is RMII
with PHY SMSC LAN8742

Signed-off-by: Christophe Roullier 
---
 arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 15 +++
 arch/arm/boot/dts/stm32h743.dtsi | 19 +++
 arch/arm/boot/dts/stm32h743i-disco.dts   | 17 +
 arch/arm/boot/dts/stm32h743i-eval.dts| 17 +
 4 files changed, 68 insertions(+)

diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index 24be8e6..980b276 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -173,6 +173,21 @@
};
};
 
+   ethernet_rmii: rmii@0 {
+   pins {
+   pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+   slew-rate = <2>;
+   };
+   };
+
usart1_pins: usart1@0 {
pins1 {
pinmux = ; 
/* USART1_TX */
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index cbdd69c..f6384af 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -511,6 +511,25 @@
status = "disabled";
};
};
+
+   syscfg: system-config@58000400 {
+   compatible = "syscon";
+   reg = <0x58000400 0x400>;
+   };
+
+   mac: ethernet@40028000 {
+   compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
+   reg = <0x40028000 0x8000>;
+   reg-names = "stmmaceth";
+   interrupts = <61>;
+   interrupt-names = "macirq";
+   clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx",
+   "syscfg-clk";
+   clocks = < ETH1MAC_CK>, < ETH1TX_CK>, < 
ETH1RX_CK>, < SYSCFG_CK>;
+   st,syscon = < 0x4>;
+   snps,pbl = <8>;
+   status = "disabled";
+   };
};
 };
 
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts 
b/arch/arm/boot/dts/stm32h743i-disco.dts
index 45e088c..0f738d0 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -66,6 +66,23 @@
clock-frequency = <2500>;
 };
 
+ {
+   status = "okay";
+   pinctrl-0   = <_rmii>;
+   pinctrl-names   = "default";
+   phy-mode= "rmii";
+   phy-handle  = <>;
+
+   mdio0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   phy1: ethernet-phy@1 {
+   reg = <0>;
+   };
+   };
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts 
b/arch/arm/boot/dts/stm32h743i-eval.dts
index 3f8e0c4..44997ba 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -104,6 +104,23 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+   pinctrl-0   = <_rmii>;
+   pinctrl-names   = "default";
+   phy-mode= "rmii";
+   phy-handle  = <>;
+
+   mdio0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   phy1: ethernet-phy@1 {
+   reg = <0>;
+   };
+   };
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
-- 
2.7.4

[PATCH V0:net-next 0/4] net: ethernet: stmmac: add support for stm32mp1

[Christophe Roullier]

Patches to have Ethernet support on stm32mp1

Christophe Roullier (4):
  net: ethernet: stmmac: add adaptation for stm32mp157c.
  dt-bindings: stm32-dwmac: add support of MPU families
  net: stmmac: add dwmac-4.20a compatible
  dt-bindings: stm32: add compatible for syscon

 .../devicetree/bindings/arm/stm32/stm32-syscon.txt |  14 ++
 .../devicetree/bindings/arm/{ => stm32}/stm32.txt  |   0
 .../devicetree/bindings/net/stm32-dwmac.txt|  18 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c  | 267 +++--
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   3 +-
 5 files changed, 284 insertions(+), 18 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
 rename Documentation/devicetree/bindings/arm/{ => stm32}/stm32.txt (100%)

-- 
1.9.1

[PATCH V0:net-next 0/4] net: ethernet: stmmac: add support for stm32mp1

[Christophe Roullier]

Patches to have Ethernet support on stm32mp1

Christophe Roullier (4):
  net: ethernet: stmmac: add adaptation for stm32mp157c.
  dt-bindings: stm32-dwmac: add support of MPU families
  net: stmmac: add dwmac-4.20a compatible
  dt-bindings: stm32: add compatible for syscon

 .../devicetree/bindings/arm/stm32/stm32-syscon.txt |  14 ++
 .../devicetree/bindings/arm/{ => stm32}/stm32.txt  |   0
 .../devicetree/bindings/net/stm32-dwmac.txt|  18 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c  | 267 +++--
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   3 +-
 5 files changed, 284 insertions(+), 18 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
 rename Documentation/devicetree/bindings/arm/{ => stm32}/stm32.txt (100%)

-- 
1.9.1

[PATCH V0:net-next 4/4] dt-bindings: stm32: add compatible for syscon

[Christophe Roullier]

This patch describes syscon DT bindings.

Signed-off-by: Christophe Roullier <christophe.roull...@st.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/arm/stm32/stm32-syscon.txt | 14 ++
 .../devicetree/bindings/arm/{ => stm32}/stm32.txt  |  0
 2 files changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
 rename Documentation/devicetree/bindings/arm/{ => stm32}/stm32.txt (100%)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt 
b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
new file mode 100644
index 000..99980ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
@@ -0,0 +1,14 @@
+STMicroelectronics STM32 Platforms System Controller
+
+Properties:
+   - compatible : should contain two values. First value must be :
+ - " st,stm32mp157-syscfg " - for stm32mp157 based SoCs,
+ second value must be always "syscon".
+   - reg : offset and length of the register set.
+
+ Example:
+ syscfg: syscon@5002 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x5002 0x400>;
+ };
+
diff --git a/Documentation/devicetree/bindings/arm/stm32.txt 
b/Documentation/devicetree/bindings/arm/stm32/stm32.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/stm32.txt
rename to Documentation/devicetree/bindings/arm/stm32/stm32.txt
-- 
1.9.1

[PATCH V0:net-next 2/4] dt-bindings: stm32-dwmac: add support of MPU families

[Christophe Roullier]

Add description for Ethernet MPU families fields

Signed-off-by: Christophe Roullier <christophe.roull...@st.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/net/stm32-dwmac.txt | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt 
b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index 489dbcb..1341012 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -6,14 +6,28 @@ Please see stmmac.txt for the other unchanged properties.
 The device node has following properties.
 
 Required properties:
-- compatible:  Should be "st,stm32-dwmac" to select glue, and
+- compatible:  For MCU family should be "st,stm32-dwmac" to select glue, and
   "snps,dwmac-3.50a" to select IP version.
+  For MPU family should be "st,stm32mp1-dwmac" to select
+  glue, and "snps,dwmac-4.20a" to select IP version.
 - clocks: Must contain a phandle for each entry in clock-names.
 - clock-names: Should be "stmmaceth" for the host clock.
   Should be "mac-clk-tx" for the MAC TX clock.
   Should be "mac-clk-rx" for the MAC RX clock.
+  For MPU family need to add also "ethstp" for power mode clock 
and,
+  "syscfg-clk" for SYSCFG clock.
+- interrupt-names: Should contain a list of interrupt names corresponding to
+   the interrupts in the interrupts property, if available.
+  Should be "macirq" for the main MAC IRQ
+  Should be "eth_wake_irq" for the IT which wake up system
 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node 
which
- encompases the glue register, and the offset of the control 
register.
+  encompases the glue register, and the offset of the control 
register.
+
+Optional properties:
+- clock-names: For MPU family "mac-clk-ck" for PHY without quartz
+- st,int-phyclk (boolean) :  valid only where PHY do not have quartz and need 
to be clock
+  by RCC
+
 Example:
 
ethernet@40028000 {
-- 
1.9.1

[PATCH V0:net-next 4/4] dt-bindings: stm32: add compatible for syscon

[Christophe Roullier]

This patch describes syscon DT bindings.

Signed-off-by: Christophe Roullier 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/arm/stm32/stm32-syscon.txt | 14 ++
 .../devicetree/bindings/arm/{ => stm32}/stm32.txt  |  0
 2 files changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
 rename Documentation/devicetree/bindings/arm/{ => stm32}/stm32.txt (100%)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt 
b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
new file mode 100644
index 000..99980ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
@@ -0,0 +1,14 @@
+STMicroelectronics STM32 Platforms System Controller
+
+Properties:
+   - compatible : should contain two values. First value must be :
+ - " st,stm32mp157-syscfg " - for stm32mp157 based SoCs,
+ second value must be always "syscon".
+   - reg : offset and length of the register set.
+
+ Example:
+ syscfg: syscon@5002 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x5002 0x400>;
+ };
+
diff --git a/Documentation/devicetree/bindings/arm/stm32.txt 
b/Documentation/devicetree/bindings/arm/stm32/stm32.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/stm32.txt
rename to Documentation/devicetree/bindings/arm/stm32/stm32.txt
-- 
1.9.1

[PATCH V0:net-next 2/4] dt-bindings: stm32-dwmac: add support of MPU families

[Christophe Roullier]

Add description for Ethernet MPU families fields

Signed-off-by: Christophe Roullier 
Reviewed-by: Rob Herring 
---
 Documentation/devicetree/bindings/net/stm32-dwmac.txt | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt 
b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index 489dbcb..1341012 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -6,14 +6,28 @@ Please see stmmac.txt for the other unchanged properties.
 The device node has following properties.
 
 Required properties:
-- compatible:  Should be "st,stm32-dwmac" to select glue, and
+- compatible:  For MCU family should be "st,stm32-dwmac" to select glue, and
   "snps,dwmac-3.50a" to select IP version.
+  For MPU family should be "st,stm32mp1-dwmac" to select
+  glue, and "snps,dwmac-4.20a" to select IP version.
 - clocks: Must contain a phandle for each entry in clock-names.
 - clock-names: Should be "stmmaceth" for the host clock.
   Should be "mac-clk-tx" for the MAC TX clock.
   Should be "mac-clk-rx" for the MAC RX clock.
+  For MPU family need to add also "ethstp" for power mode clock 
and,
+  "syscfg-clk" for SYSCFG clock.
+- interrupt-names: Should contain a list of interrupt names corresponding to
+   the interrupts in the interrupts property, if available.
+  Should be "macirq" for the main MAC IRQ
+  Should be "eth_wake_irq" for the IT which wake up system
 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node 
which
- encompases the glue register, and the offset of the control 
register.
+  encompases the glue register, and the offset of the control 
register.
+
+Optional properties:
+- clock-names: For MPU family "mac-clk-ck" for PHY without quartz
+- st,int-phyclk (boolean) :  valid only where PHY do not have quartz and need 
to be clock
+  by RCC
+
 Example:
 
ethernet@40028000 {
-- 
1.9.1

[PATCH V0:net-next 1/4] net: ethernet: stmmac: add adaptation for stm32mp157c.

[Christophe Roullier]

Glue codes to support stm32mp157c device and stay
compatible with stm32 mcu familly

Signed-off-by: Christophe Roullier <christophe.roull...@st.com>
Acked-by: Alexandre TORGUE <alexandre.tor...@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 267 --
 1 file changed, 252 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 9e6db16..7e2e79d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -16,49 +16,180 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
 #include "stmmac_platform.h"
 
-#define MII_PHY_SEL_MASK   BIT(23)
+#define SYSCFG_MCU_ETH_MASKBIT(23)
+#define SYSCFG_MP1_ETH_MASKGENMASK(23, 16)
+
+#define SYSCFG_PMCR_ETH_CLK_SELBIT(16)
+#define SYSCFG_PMCR_ETH_REF_CLK_SELBIT(17)
+#define SYSCFG_PMCR_ETH_SEL_MIIBIT(20)
+#define SYSCFG_PMCR_ETH_SEL_RGMII  BIT(21)
+#define SYSCFG_PMCR_ETH_SEL_RMII   BIT(23)
+#define SYSCFG_PMCR_ETH_SEL_GMII   0
+#define SYSCFG_MCU_ETH_SEL_MII 0
+#define SYSCFG_MCU_ETH_SEL_RMII1
 
 struct stm32_dwmac {
struct clk *clk_tx;
struct clk *clk_rx;
+   struct clk *clk_eth_ck;
+   struct clk *clk_ethstp;
+   struct clk *syscfg_clk;
+   bool int_phyclk;/* Clock from RCC to drive PHY */
u32 mode_reg;   /* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
+   const struct stm32_ops *ops;
+   struct device *dev;
+};
+
+struct stm32_ops {
+   int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
+   int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);
+   int (*suspend)(struct stm32_dwmac *dwmac);
+   void (*resume)(struct stm32_dwmac *dwmac);
+   int (*parse_data)(struct stm32_dwmac *dwmac,
+ struct device *dev);
+   u32 syscfg_eth_mask;
 };
 
 static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
 {
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
-   u32 reg = dwmac->mode_reg;
-   u32 val;
int ret;
 
-   val = (plat_dat->interface == PHY_INTERFACE_MODE_MII) ? 0 : 1;
-   ret = regmap_update_bits(dwmac->regmap, reg, MII_PHY_SEL_MASK, val);
-   if (ret)
-   return ret;
+   if (dwmac->ops->set_mode) {
+   ret = dwmac->ops->set_mode(plat_dat);
+   if (ret)
+   return ret;
+   }
 
ret = clk_prepare_enable(dwmac->clk_tx);
if (ret)
return ret;
 
-   ret = clk_prepare_enable(dwmac->clk_rx);
-   if (ret)
-   clk_disable_unprepare(dwmac->clk_tx);
+   if (!dwmac->dev->power.is_suspended) {
+   ret = clk_prepare_enable(dwmac->clk_rx);
+   if (ret) {
+   clk_disable_unprepare(dwmac->clk_tx);
+   return ret;
+   }
+   }
+
+   if (dwmac->ops->clk_prepare) {
+   ret = dwmac->ops->clk_prepare(dwmac, true);
+   if (ret) {
+   clk_disable_unprepare(dwmac->clk_rx);
+   clk_disable_unprepare(dwmac->clk_tx);
+   }
+   }
 
return ret;
 }
 
+static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
+{
+   int ret = 0;
+
+   if (prepare) {
+   ret = clk_prepare_enable(dwmac->syscfg_clk);
+   if (ret)
+   return ret;
+
+   if (dwmac->int_phyclk) {
+   ret = clk_prepare_enable(dwmac->clk_eth_ck);
+   if (ret) {
+   clk_disable_unprepare(dwmac->syscfg_clk);
+   return ret;
+   }
+   }
+   } else {
+   clk_disable_unprepare(dwmac->syscfg_clk);
+   if (dwmac->int_phyclk)
+   clk_disable_unprepare(dwmac->clk_eth_ck);
+   }
+   return ret;
+}
+
+static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
+{
+   struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+   u32 reg = dwmac->mode_reg;
+   int val;
+
+   switch (plat_dat->interface) {
+   case PHY_INTERFACE_MODE_MII:
+   val = SYSCFG_PMCR_ETH_SEL_MII;
+   pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
+   break;
+   case PHY_INTERFACE_MODE_GMII:
+   val = SYSCFG_PMCR_ETH_SEL_GMII;
+   if (dwmac->int_phyclk)
+   val |= SYSCFG_PMCR_ETH_CLK_SEL;
+   pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
+   

[PATCH V0:net-next 1/4] net: ethernet: stmmac: add adaptation for stm32mp157c.

[Christophe Roullier]

Glue codes to support stm32mp157c device and stay
compatible with stm32 mcu familly

Signed-off-by: Christophe Roullier 
Acked-by: Alexandre TORGUE 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 267 --
 1 file changed, 252 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 9e6db16..7e2e79d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -16,49 +16,180 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
 #include "stmmac_platform.h"
 
-#define MII_PHY_SEL_MASK   BIT(23)
+#define SYSCFG_MCU_ETH_MASKBIT(23)
+#define SYSCFG_MP1_ETH_MASKGENMASK(23, 16)
+
+#define SYSCFG_PMCR_ETH_CLK_SELBIT(16)
+#define SYSCFG_PMCR_ETH_REF_CLK_SELBIT(17)
+#define SYSCFG_PMCR_ETH_SEL_MIIBIT(20)
+#define SYSCFG_PMCR_ETH_SEL_RGMII  BIT(21)
+#define SYSCFG_PMCR_ETH_SEL_RMII   BIT(23)
+#define SYSCFG_PMCR_ETH_SEL_GMII   0
+#define SYSCFG_MCU_ETH_SEL_MII 0
+#define SYSCFG_MCU_ETH_SEL_RMII1
 
 struct stm32_dwmac {
struct clk *clk_tx;
struct clk *clk_rx;
+   struct clk *clk_eth_ck;
+   struct clk *clk_ethstp;
+   struct clk *syscfg_clk;
+   bool int_phyclk;/* Clock from RCC to drive PHY */
u32 mode_reg;   /* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
+   const struct stm32_ops *ops;
+   struct device *dev;
+};
+
+struct stm32_ops {
+   int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
+   int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);
+   int (*suspend)(struct stm32_dwmac *dwmac);
+   void (*resume)(struct stm32_dwmac *dwmac);
+   int (*parse_data)(struct stm32_dwmac *dwmac,
+ struct device *dev);
+   u32 syscfg_eth_mask;
 };
 
 static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
 {
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
-   u32 reg = dwmac->mode_reg;
-   u32 val;
int ret;
 
-   val = (plat_dat->interface == PHY_INTERFACE_MODE_MII) ? 0 : 1;
-   ret = regmap_update_bits(dwmac->regmap, reg, MII_PHY_SEL_MASK, val);
-   if (ret)
-   return ret;
+   if (dwmac->ops->set_mode) {
+   ret = dwmac->ops->set_mode(plat_dat);
+   if (ret)
+   return ret;
+   }
 
ret = clk_prepare_enable(dwmac->clk_tx);
if (ret)
return ret;
 
-   ret = clk_prepare_enable(dwmac->clk_rx);
-   if (ret)
-   clk_disable_unprepare(dwmac->clk_tx);
+   if (!dwmac->dev->power.is_suspended) {
+   ret = clk_prepare_enable(dwmac->clk_rx);
+   if (ret) {
+   clk_disable_unprepare(dwmac->clk_tx);
+   return ret;
+   }
+   }
+
+   if (dwmac->ops->clk_prepare) {
+   ret = dwmac->ops->clk_prepare(dwmac, true);
+   if (ret) {
+   clk_disable_unprepare(dwmac->clk_rx);
+   clk_disable_unprepare(dwmac->clk_tx);
+   }
+   }
 
return ret;
 }
 
+static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
+{
+   int ret = 0;
+
+   if (prepare) {
+   ret = clk_prepare_enable(dwmac->syscfg_clk);
+   if (ret)
+   return ret;
+
+   if (dwmac->int_phyclk) {
+   ret = clk_prepare_enable(dwmac->clk_eth_ck);
+   if (ret) {
+   clk_disable_unprepare(dwmac->syscfg_clk);
+   return ret;
+   }
+   }
+   } else {
+   clk_disable_unprepare(dwmac->syscfg_clk);
+   if (dwmac->int_phyclk)
+   clk_disable_unprepare(dwmac->clk_eth_ck);
+   }
+   return ret;
+}
+
+static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
+{
+   struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+   u32 reg = dwmac->mode_reg;
+   int val;
+
+   switch (plat_dat->interface) {
+   case PHY_INTERFACE_MODE_MII:
+   val = SYSCFG_PMCR_ETH_SEL_MII;
+   pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
+   break;
+   case PHY_INTERFACE_MODE_GMII:
+   val = SYSCFG_PMCR_ETH_SEL_GMII;
+   if (dwmac->int_phyclk)
+   val |= SYSCFG_PMCR_ETH_CLK_SEL;
+   pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
+   break;
+   case PHY_INTERFACE_MODE_RMII:
+   val

[PATCH V0:net-next 3/4] net: stmmac: add dwmac-4.20a compatible

[Christophe Roullier]

Manage dwmac-4.20a version from synopsys

Signed-off-by: Christophe Roullier <christophe.roull...@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index ebd3e5f..6d141f3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -472,7 +472,8 @@ struct plat_stmmacenet_data *
}
 
if (of_device_is_compatible(np, "snps,dwmac-4.00") ||
-   of_device_is_compatible(np, "snps,dwmac-4.10a")) {
+   of_device_is_compatible(np, "snps,dwmac-4.10a") ||
+   of_device_is_compatible(np, "snps,dwmac-4.20a")) {
plat->has_gmac4 = 1;
plat->has_gmac = 0;
plat->pmt = 1;
-- 
1.9.1

[PATCH V0:net-next 3/4] net: stmmac: add dwmac-4.20a compatible

[Christophe Roullier]

Manage dwmac-4.20a version from synopsys

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index ebd3e5f..6d141f3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -472,7 +472,8 @@ struct plat_stmmacenet_data *
}
 
if (of_device_is_compatible(np, "snps,dwmac-4.00") ||
-   of_device_is_compatible(np, "snps,dwmac-4.10a")) {
+   of_device_is_compatible(np, "snps,dwmac-4.10a") ||
+   of_device_is_compatible(np, "snps,dwmac-4.20a")) {
plat->has_gmac4 = 1;
plat->has_gmac = 0;
plat->pmt = 1;
-- 
1.9.1

[PATCH] net: ethernet: stmmac: add ARP management

[Christophe Roullier]

DWC_ether_qos supports the Address Recognition
Protocol (ARP) Offload for IPv4 packets. This feature
allows the processing of the IPv4 ARP request packet
in the receive path and generating corresponding ARP
response packet in the transmit path. DWC_ether_qos
generates the ARP reply packets for appropriate ARP
request packets.

Signed-off-by: Christophe Roullier <christophe.roull...@st.com>
---
 drivers/net/ethernet/stmicro/stmmac/common.h   |  4 
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h   |  3 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c  | 15 ++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c   | 23 ++
 drivers/net/ethernet/stmicro/stmmac/stmmac.h   |  1 +
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 13 
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |  1 +
 include/linux/stmmac.h |  1 +
 8 files changed, 61 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h 
b/drivers/net/ethernet/stmicro/stmmac/common.h
index 75e2666..1d1c815 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -306,6 +306,7 @@ struct dma_features {
unsigned int pmt_remote_wake_up;
unsigned int pmt_magic_frame;
unsigned int rmon;
+   unsigned int arpoffsel;
/* IEEE 1588-2002 */
unsigned int time_stamp;
/* IEEE 1588-2008 */
@@ -447,6 +448,7 @@ struct stmmac_dma_ops {
void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
+   void (*set_arp_addr)(void __iomem *ioaddr, bool en, u32 addr);
 };
 
 struct mac_device_info;
@@ -459,6 +461,8 @@ struct stmmac_ops {
int (*rx_ipc)(struct mac_device_info *hw);
/* Enable RX Queues */
void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);
+   /* Enable and verify that the ARP feature is supported */
+   int (*arp_en)(struct mac_device_info *hw);
/* Dump MAC registers */
void (*dump_regs)(struct mac_device_info *hw);
/* Handle extra events on specific interrupts hw dependent */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h 
b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index db45134..d1e2e37 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -35,6 +35,7 @@
 #define GMAC_HW_FEATURE2   0x0124
 #define GMAC_MDIO_ADDR 0x0200
 #define GMAC_MDIO_DATA 0x0204
+#define GMAC_ARP_ADDR  0x0210
 #define GMAC_ADDR_HIGH(reg)(0x300 + reg * 8)
 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
 
@@ -116,6 +117,7 @@ enum power_event {
 #define GMAC_DEBUG_RPESTS  BIT(0)
 
 /* MAC config */
+#define GMAC_CONFIG_ARPEN  BIT(31)
 #define GMAC_CONFIG_IPCBIT(27)
 #define GMAC_CONFIG_2K BIT(22)
 #define GMAC_CONFIG_ACSBIT(20)
@@ -135,6 +137,7 @@ enum power_event {
 #define GMAC_HW_FEAT_TXCOSEL   BIT(14)
 #define GMAC_HW_FEAT_EEESELBIT(13)
 #define GMAC_HW_FEAT_TSSEL BIT(12)
+#define GMAC_HW_FEAT_ARPOFFSEL BIT(9)
 #define GMAC_HW_FEAT_MMCSELBIT(8)
 #define GMAC_HW_FEAT_MGKSELBIT(7)
 #define GMAC_HW_FEAT_RWKSELBIT(6)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index 834f40f..33d0fb3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -102,6 +102,20 @@ static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
return !!(value & GMAC_CONFIG_IPC);
 }
 
+static int dwmac4_arp_enable(struct mac_device_info *hw)
+{
+   void __iomem *ioaddr = hw->pcsr;
+   u32 value = readl(ioaddr + GMAC_CONFIG);
+
+   value |= GMAC_CONFIG_ARPEN;
+
+   writel(value, ioaddr + GMAC_CONFIG);
+
+   value = readl(ioaddr + GMAC_CONFIG);
+
+   return !!(value & GMAC_CONFIG_ARPEN);
+}
+
 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 {
void __iomem *ioaddr = hw->pcsr;
@@ -463,6 +477,7 @@ static void dwmac4_debug(void __iomem *ioaddr, struct 
stmmac_extra_stats *x)
.core_init = dwmac4_core_init,
.rx_ipc = dwmac4_rx_ipc_enable,
.rx_queue_enable = dwmac4_rx_queue_enable,
+   .arp_en = dwmac4_arp_enable,
.dump_regs = dwmac4_dump_regs,
.host_irq_status = dwmac4_irq_status,
.flow_ctrl = dwmac4_flow_ctrl,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 377d1b4..fbbd303 100644
--- a/drivers/net/ethernet/stmicro

[PATCH] net: ethernet: stmmac: add ARP management

[Christophe Roullier]

DWC_ether_qos supports the Address Recognition
Protocol (ARP) Offload for IPv4 packets. This feature
allows the processing of the IPv4 ARP request packet
in the receive path and generating corresponding ARP
response packet in the transmit path. DWC_ether_qos
generates the ARP reply packets for appropriate ARP
request packets.

Signed-off-by: Christophe Roullier 
---
 drivers/net/ethernet/stmicro/stmmac/common.h   |  4 
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h   |  3 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c  | 15 ++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c   | 23 ++
 drivers/net/ethernet/stmicro/stmmac/stmmac.h   |  1 +
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 13 
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |  1 +
 include/linux/stmmac.h |  1 +
 8 files changed, 61 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h 
b/drivers/net/ethernet/stmicro/stmmac/common.h
index 75e2666..1d1c815 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -306,6 +306,7 @@ struct dma_features {
unsigned int pmt_remote_wake_up;
unsigned int pmt_magic_frame;
unsigned int rmon;
+   unsigned int arpoffsel;
/* IEEE 1588-2002 */
unsigned int time_stamp;
/* IEEE 1588-2008 */
@@ -447,6 +448,7 @@ struct stmmac_dma_ops {
void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
+   void (*set_arp_addr)(void __iomem *ioaddr, bool en, u32 addr);
 };
 
 struct mac_device_info;
@@ -459,6 +461,8 @@ struct stmmac_ops {
int (*rx_ipc)(struct mac_device_info *hw);
/* Enable RX Queues */
void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);
+   /* Enable and verify that the ARP feature is supported */
+   int (*arp_en)(struct mac_device_info *hw);
/* Dump MAC registers */
void (*dump_regs)(struct mac_device_info *hw);
/* Handle extra events on specific interrupts hw dependent */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h 
b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index db45134..d1e2e37 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -35,6 +35,7 @@
 #define GMAC_HW_FEATURE2   0x0124
 #define GMAC_MDIO_ADDR 0x0200
 #define GMAC_MDIO_DATA 0x0204
+#define GMAC_ARP_ADDR  0x0210
 #define GMAC_ADDR_HIGH(reg)(0x300 + reg * 8)
 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
 
@@ -116,6 +117,7 @@ enum power_event {
 #define GMAC_DEBUG_RPESTS  BIT(0)
 
 /* MAC config */
+#define GMAC_CONFIG_ARPEN  BIT(31)
 #define GMAC_CONFIG_IPCBIT(27)
 #define GMAC_CONFIG_2K BIT(22)
 #define GMAC_CONFIG_ACSBIT(20)
@@ -135,6 +137,7 @@ enum power_event {
 #define GMAC_HW_FEAT_TXCOSEL   BIT(14)
 #define GMAC_HW_FEAT_EEESELBIT(13)
 #define GMAC_HW_FEAT_TSSEL BIT(12)
+#define GMAC_HW_FEAT_ARPOFFSEL BIT(9)
 #define GMAC_HW_FEAT_MMCSELBIT(8)
 #define GMAC_HW_FEAT_MGKSELBIT(7)
 #define GMAC_HW_FEAT_RWKSELBIT(6)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index 834f40f..33d0fb3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -102,6 +102,20 @@ static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
return !!(value & GMAC_CONFIG_IPC);
 }
 
+static int dwmac4_arp_enable(struct mac_device_info *hw)
+{
+   void __iomem *ioaddr = hw->pcsr;
+   u32 value = readl(ioaddr + GMAC_CONFIG);
+
+   value |= GMAC_CONFIG_ARPEN;
+
+   writel(value, ioaddr + GMAC_CONFIG);
+
+   value = readl(ioaddr + GMAC_CONFIG);
+
+   return !!(value & GMAC_CONFIG_ARPEN);
+}
+
 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 {
void __iomem *ioaddr = hw->pcsr;
@@ -463,6 +477,7 @@ static void dwmac4_debug(void __iomem *ioaddr, struct 
stmmac_extra_stats *x)
.core_init = dwmac4_core_init,
.rx_ipc = dwmac4_rx_ipc_enable,
.rx_queue_enable = dwmac4_rx_queue_enable,
+   .arp_en = dwmac4_arp_enable,
.dump_regs = dwmac4_dump_regs,
.host_irq_status = dwmac4_irq_status,
.flow_ctrl = dwmac4_flow_ctrl,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 377d1b4..fbbd303 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/driver