Re: [RESEND PATCH v3] MAINTAINERS: add Dan Murphy as TI LP8xxx drivers maintainer
Krzysztof On 2/10/21 11:29 AM, Krzysztof Kozlowski wrote: Milo Kim's email in TI bounces with permanent error (550: Invalid recipient). Last email from him on LKML was in 2017. Move Milo Kim to credits and add Dan Murphy from TI to look after: - TI LP855x backlight driver, - TI LP8727 charger driver, - TI LP8788 MFD (ADC, LEDs, charger and regulator) drivers. Signed-off-by: Krzysztof Kozlowski Cc: Dan Murphy Unfortunately I need to remove my ACK. My TI email will be disabled this Friday. No replacement has been identified Dan
Re: [PATCH V3 1/2] dt-bindings: power: bq27xxx: add bq78z10
Li On 2/4/21 5:37 PM, Rob Herring wrote: On Wed, 03 Feb 2021 10:40:59 +, LI Qingwu wrote: Add bindings for TI BQ78Z100. An I2C interface gas gauge. It provides a fully integrated safety protection and authentication for 1 to 2-series cell Li-Ion and Li-Polymer battery packs. $subject has the wrong part number Dan Signed-off-by: LI Qingwu --- Documentation/devicetree/bindings/power/supply/bq27xxx.yaml | 1 + 1 file changed, 1 insertion(+) Acked-by: Rob Herring
Re: [PATCH 2/2] leds: lp50xx: remove unused regulator
Pavel On 2/3/21 8:23 AM, Pavel Machek wrote: On Wed 2021-02-03 07:49:35, Dan Murphy wrote: Pavel On 2/3/21 3:02 AM, Pavel Machek wrote: On Wed 2021-02-03 08:34:08, Sven Schuchmann wrote: The regulator for vled-supply is unused in the driver. It is just assigned from DT and disabled in lp50xx_remove. So the code can be removed from the driver. Dan, what is going on here? Do we need to also enable the regulator, or is the removal correct thing to do? I think it would be better to do an enable as opposed to removing the code. This would be needed especially in applications that have to meet strict power management requirements. Users may want to disable or enable the regulator during suspend/resume. Otherwise it would be considered always-on and the regulator does not need to be populated. Do you have set up where this is needed and you can test this? Will you submit the fixes? No I use an always on regulator in my setup. I have no managed supplies exposed. Dan Best regards, Pavel
Re: [PATCH 2/2] leds: lp50xx: remove unused regulator
Pavel On 2/3/21 3:02 AM, Pavel Machek wrote: On Wed 2021-02-03 08:34:08, Sven Schuchmann wrote: The regulator for vled-supply is unused in the driver. It is just assigned from DT and disabled in lp50xx_remove. So the code can be removed from the driver. Dan, what is going on here? Do we need to also enable the regulator, or is the removal correct thing to do? I think it would be better to do an enable as opposed to removing the code. This would be needed especially in applications that have to meet strict power management requirements. Users may want to disable or enable the regulator during suspend/resume. Otherwise it would be considered always-on and the regulator does not need to be populated. Dan
Re: [PATCH 2/2] iio:adc:ti-ads124s08: Fix packet read from the ADC
Jonathan
On 1/24/21 9:12 AM, Jonathan Cameron wrote:
On Thu, 21 Jan 2021 13:14:31 -0600
Dan Murphy wrote:
Fix the spi_transfer array in the reading of the data from the ADC.
Fixes: ("e717f8c6dfec iio: adc: Add the TI ads124s08 ADC code")
Signed-off-by: Dan Murphy
I'm not really following the changes below..
I will have to dig into it deeper our HW team reported this.
Patch 1/2 is relevant and is not dependent on this patch
Dan
[PATCH 1/2] iio:adc:ti-ads124s08: Fix start stop conversion command
Fix start and stop conversion commands. The proper command is not be
sent.
Fixes: ("e717f8c6dfec iio: adc: Add the TI ads124s08 ADC code")
Signed-off-by: Dan Murphy
---
drivers/iio/adc/ti-ads124s08.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/adc/ti-ads124s08.c b/drivers/iio/adc/ti-ads124s08.c
index b4a128b19188..f05d4e0e1c9d 100644
--- a/drivers/iio/adc/ti-ads124s08.c
+++ b/drivers/iio/adc/ti-ads124s08.c
@@ -237,7 +237,7 @@ static int ads124s_read_raw(struct iio_dev *indio_dev,
goto out;
}
- ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
+ ret = ads124s_write_cmd(indio_dev, ADS124S08_CMD_START);
if (ret) {
dev_err(>spi->dev, "Start conversions failed\n");
goto out;
@@ -251,7 +251,7 @@ static int ads124s_read_raw(struct iio_dev *indio_dev,
*val = ret;
- ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
+ ret = ads124s_write_cmd(indio_dev, ADS124S08_CMD_STOP);
if (ret) {
dev_err(>spi->dev, "Stop conversions failed\n");
goto out;
--
2.29.2
[PATCH 2/2] iio:adc:ti-ads124s08: Fix packet read from the ADC
Fix the spi_transfer array in the reading of the data from the ADC.
Fixes: ("e717f8c6dfec iio: adc: Add the TI ads124s08 ADC code")
Signed-off-by: Dan Murphy
---
drivers/iio/adc/ti-ads124s08.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/iio/adc/ti-ads124s08.c b/drivers/iio/adc/ti-ads124s08.c
index f05d4e0e1c9d..023d81c7e8da 100644
--- a/drivers/iio/adc/ti-ads124s08.c
+++ b/drivers/iio/adc/ti-ads124s08.c
@@ -201,12 +201,10 @@ static int ads124s_read(struct iio_dev *indio_dev,
unsigned int chan)
struct spi_transfer t[] = {
{
.tx_buf = >data[0],
- .len = 4,
- .cs_change = 1,
}, {
- .tx_buf = >data[1],
.rx_buf = >data[1],
.len = 4,
+ .cs_change = 1,
},
};
--
2.29.2
Re: [PATCH v2 -next] leds: convert comma to semicolon
Hello On 1/8/21 3:24 AM, Zheng Yongjun wrote: Replace a comma between expression statements by a semicolon. Can you add a "Fixes" tag here? Dan
Re: [PATCH net-next v4 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew
On 11/19/20 7:49 PM, Andrew Lunn wrote:
+static int dp83td510_config_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ int ret = 0;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ if (dp83td510->rgmii_delay) {
+ ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR,
+ DP83TD510_MAC_CFG_1,
+ dp83td510->rgmii_delay);
Just to be safe, you should always write rgmii_delay, even if it is
zero. We have had too many bugs with RGMII delays which cause bad
backwards compatibility problems, so i would prefer to do a write
which might be unneeded, that find a bug here in a few years time.
OK.
+ if (ret)
+ return ret;
+ }
+ }
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
+ ret = phy_modify(phydev, DP83TD510_GEN_CFG,
+DP83TD510_FIFO_DEPTH_MASK,
+dp83td510->tx_fifo_depth);
So there is no need to set the FIFO depth for the other three RGMII
modes? Or should this also be phy_interface_is_rgmii(phydev)?
According to the data sheet the FIFO depth is for RMII.
"Fifo depth for RMII Tx fifo"
But I will ask the HW team for clarification.
+#if IS_ENABLED(CONFIG_OF_MDIO)
+static int dp83td510_of_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ struct device *dev = >mdio.dev;
+ struct device_node *of_node = dev->of_node;
You need to move this assignment to later in order to keep with
reverse christmas tree.
Well this is only used once so I will just remove the of_node declaration
+#else
+static int dp83869_of_init(struct phy_device *phydev)
+{
+ dp83td510->hi_diff_output = DP83TD510_2_4V_P2P
+ dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_5_B_NIB
You don't have DT, so there is no fine control, but you still need to
do the basic 2ns delay as indicated by the phydev->interface value. So
i think you still need to set dp83td510->rgmii_delay depending on
which RGMII mode is requested.
The RGMII delay is fixed in the PHY. The user can either turn it on or
off. The default is 'off' which is 0.
I can explicitly set the rgmii_delay to 0 in non-OF cases.
Dan
Re: [PATCH 29/38] ASoC: tas2562: skip of_device_id table when !CONFIG_OF
Hello
On 11/20/20 10:16 AM, Krzysztof Kozlowski wrote:
The driver can match by multiple methods. Its of_device_id table is
referenced via of_match_ptr() so it will be unused for !CONFIG_OF
builds:
sound/soc/codecs/tas2562.c:805:34: warning: ‘tas2562_of_match’ defined but
not used [-Wunused-const-variable=]
Signed-off-by: Krzysztof Kozlowski
---
sound/soc/codecs/tas2562.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/sound/soc/codecs/tas2562.c b/sound/soc/codecs/tas2562.c
index f1ff204e3ad0..19965fabe949 100644
--- a/sound/soc/codecs/tas2562.c
+++ b/sound/soc/codecs/tas2562.c
@@ -802,6 +802,7 @@ static const struct i2c_device_id tas2562_id[] = {
};
MODULE_DEVICE_TABLE(i2c, tas2562_id);
+#ifdef CONFIG_OF
Should we use #if IS_ENABLED(CONFIG_OF) ?
Dan
Re: [PATCH v2] leds: lp50xx: add missing fwnode_handle_put in error handling case
Hello
On 11/19/20 1:08 AM, Qinglang Miao wrote:
Fix to set ret and goto child_out for fwnode_handle_put(child)
in the error handling case rather than simply return, as done
elsewhere in this function.
Fixes: 242b81170fb8 ("leds: lp50xx: Add the LP50XX family of the RGB LED
driver")
Reported-by: Hulk Robot
Suggested-by: Pavel Machek
Signed-off-by: Qinglang Miao
---
v2: forget to set ret on v1
drivers/leds/leds-lp50xx.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/leds/leds-lp50xx.c b/drivers/leds/leds-lp50xx.c
index 5fb4f24ae..f13117eed 100644
--- a/drivers/leds/leds-lp50xx.c
+++ b/drivers/leds/leds-lp50xx.c
@@ -487,8 +487,10 @@ static int lp50xx_probe_dt(struct lp50xx *priv)
*/
mc_led_info = devm_kcalloc(priv->dev, LP50XX_LEDS_PER_MODULE,
sizeof(*mc_led_info), GFP_KERNEL);
- if (!mc_led_info)
- return -ENOMEM;
+ if (!mc_led_info) {
+ ret = -ENOMEM;
+ goto child_out;
+ }
fwnode_for_each_child_node(child, led_node) {
ret = fwnode_property_read_u32(led_node, "color",
Reviewed-by: Dan Murphy
Re: [PATCH net-next v4 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L
Andrew On 11/17/20 2:31 PM, Andrew Lunn wrote: On Tue, Nov 17, 2020 at 02:15:53PM -0600, Dan Murphy wrote: Per the 802.3cg spec the 10base T1L can operate at 2 different differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to ability Ack drive that output is dependent on the PHY's on board power supply. This common feature is applicable to all 10base T1L PHYs so this binding property belongs in a top level ethernet document. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 6dd72faebd89..bda1ce51836b 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -174,6 +174,12 @@ properties: PHY's that have configurable TX internal delays. If this property is present then the PHY applies the TX delay. + max-tx-rx-p2p-microvolt: +description: | + Configures the Tx/Rx p2p differential output voltage for 10base-T1L PHYs. Does it configure, or does it limit? I _think_ this is a negotiation parameter, so the PHY might decide to do 1100mV if the link peer is near by even when max-tx-rx-p2p-microvolt has the higher value. For this device we can configure or force it to only work at 1.1v p2p otherwise 2.4 is the default. But each LP's have to be configured for the same voltage. unless auto negotiation is on then it negotiates the voltage. Dan Andrew
[PATCH net-next v4 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
The DP83TD510 is a 10M single twisted pair Ethernet PHY
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83td510.yaml | 64 +++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
new file mode 100644
index ..d3c97bb4d820
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: TI DP83TD510 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+ - $ref: "ethernet-phy.yaml#"
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
+ RGMII interfaces.
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
+
+properties:
+ reg:
+maxItems: 1
+
+ tx-fifo-depth:
+description: |
+ Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
+ depths. The valid nibble depths are 4, 5, 6 and 8.
+enum: [ 4, 5, 6, 8 ]
+default: 5
+
+ rx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 30ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY has a range of -4 to 4ns
+ relative to transmit data.
+
+unevaluatedProperties: false
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+tx-rx-output-high;
+tx-fifo-depth = <5>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
--
2.29.2
[PATCH net-next v4 1/4] ethtool: Add 10base-T1L link mode entries
Add entries for the 10base-T1L full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ TP ]
Supported link modes: 10baseT1L/Half 10baseT1L/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT1L/Half 10baseT1L/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Full
Auto-negotiation: on
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x (0)
Link detected: yes
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Dan Murphy
---
drivers/net/phy/phy-core.c | 4 +++-
include/uapi/linux/ethtool.h | 2 ++
net/ethtool/common.c | 2 ++
net/ethtool/linkmodes.c | 2 ++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 8d333d3084ed..616fae7f0c86 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 94,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync.
"
"If a speed or mode has been added please update
phy_speed_to_str "
"and the PHY settings array.\n");
@@ -175,6 +175,8 @@ static const struct phy_setting settings[] = {
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
+ PHY_SETTING( 10, FULL, 10baseT1L_Full ),
+ PHY_SETTING( 10, HALF, 10baseT1L_Half ),
};
#undef PHY_SETTING
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 9ca87bc73c44..16b6ea7548d3 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1619,6 +1619,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT = 92,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 93,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 24036e3055a1..95f87febc742 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -194,6 +194,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(40, CR4, Full),
__DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Half),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index c5bcb9abc8b9..a8fab6fb1b30 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -264,6 +264,8 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(40, CR4, Full),
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Half),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
};
const struct nla_policy ethnl_linkmodes_set_policy[] = {
--
2.29.2
[PATCH net-next v4 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L
Per the 802.3cg spec the 10base T1L can operate at 2 different differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to drive that output is dependent on the PHY's on board power supply. This common feature is applicable to all 10base T1L PHYs so this binding property belongs in a top level ethernet document. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 6dd72faebd89..bda1ce51836b 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -174,6 +174,12 @@ properties: PHY's that have configurable TX internal delays. If this property is present then the PHY applies the TX delay. + max-tx-rx-p2p-microvolt: +description: | + Configures the Tx/Rx p2p differential output voltage for 10base-T1L PHYs. +enum: [ 1100, 2400 ] +default: 2400 + required: - reg -- 2.29.2
[PATCH net-next v4 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
v4 - Considerable rework of the code after secondary test setup was created.
This version also uses the handle_interrupt call back and reduces the
configuration arrays as it was determined that 80% of the array was the same.
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile| 1 +
drivers/net/phy/dp83td510.c | 505
3 files changed, 512 insertions(+)
create mode 100644 drivers/net/phy/dp83td510.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..017252e1504c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -302,6 +302,12 @@ config DP83869_PHY
Currently supports the DP83869 PHY. This PHY supports copper and
fiber connections.
+config DP83TD510_PHY
+ tristate "Texas Instruments DP83TD510 10M Single Pair Ethernet PHY"
+ help
+ Support for the DP83TD510 Ethernet PHY. This PHY supports a 10M single
+ pair Ethernet connection.
+
config VITESSE_PHY
tristate "Vitesse PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..bf62ce211eb4 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
obj-$(CONFIG_DP83867_PHY) += dp83867.o
obj-$(CONFIG_DP83869_PHY) += dp83869.o
obj-$(CONFIG_DP83TC811_PHY)+= dp83tc811.o
+obj-$(CONFIG_DP83TD510_PHY)+= dp83td510.o
obj-$(CONFIG_FIXED_PHY)+= fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
new file mode 100644
index ..a4456e0da447
--- /dev/null
+++ b/drivers/net/phy/dp83td510.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Driver for the Texas Instruments DP83TD510 PHY
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DP83TD510E_PHY_ID 0x2180
+#define DP83TD510_DEVADDR_AN 0x7
+#define DP83TD510_DEVADDR 0x1f
+#define DP83TD510_PMD_DEVADDR 0x1
+
+#define DP83TD510_PHY_STAT 0x10
+#define DP83TD510_GEN_CFG 0x11
+#define DP83TD510_INT_REG1 0x12
+#define DP83TD510_INT_REG2 0x13
+#define DP83TD510_MAC_CFG_10x17
+#define DP83TD510_CTRL_REG 0x1f
+
+#define DP83TD510_ANEG_CTRL0x200
+#define DP83TD510_PMD_CTRL 0x834
+#define DP83TD510_M_S_CTRL 0x8f6
+
+#define DP83TD510_SOR_10x467
+
+#define DP83TD510_HW_RESET BIT(15)
+#define DP83TD510_SW_RESET BIT(14)
+
+#define DP83TD510_LINK_STS BIT(0)
+
+/* GEN CFG bits */
+#define DP83TD510_INT_OE BIT(0)
+#define DP83TD510_INT_EN BIT(1)
+
+/* INT REG 1 bits */
+#define DP83TD510_INT1_ESD_EN BIT(3)
+#define DP83TD510_INT1_LINK_EN BIT(5)
+#define DP83TD510_INT1_RHF_EN BIT(7)
+#define DP83TD510_INT1_ESD BIT(11)
+#define DP83TD510_INT1_LINKBIT(13)
+#define DP83TD510_INT1_RHF BIT(15)
+
+/* INT REG 2 bits */
+#define DP83TD510_INT2_POR_EN BIT(0)
+#define DP83TD510_INT2_POL_EN BIT(1)
+#define DP83TD510_INT2_PAGE_EN BIT(5)
+#define DP83TD510_INT2_POR BIT(8)
+#define DP83TD510_INT2_POL BIT(9)
+#define DP83TD510_INT2_PAGEBIT(13)
+
+/* MAC CFG bits */
+#define DP83TD510_RX_CLK_SHIFT BIT(12)
+#define DP83TD510_TX_CLK_SHIFT BIT(11)
+
+#define DP83TD510_MASTER_MODE BIT(14)
+#define DP83TD510_AUTO_NEG_EN BIT(12)
+#define DP83TD510_RGMIIBIT(8)
+
+#define DP83TD510_FIFO_DEPTH_MASK GENMASK(6, 5)
+#define DP83TD510_FIFO_DEPTH_4_B_NIB 0
+#define DP83TD510_FIFO_DEPTH_5_B_NIB BIT(5)
+#define DP83TD510_FIFO_DEPTH_6_B_NIB BIT(6)
+#define DP83TD510_FIFO_DEPTH_8_B_NIB (BIT(5) | BIT(6))
+
+#define DP83TD510_2_4V BIT(12)
+#define DP83TD510_2_4V_P2P 2400
+#define DP83TD510_1_1V_P2P 1100
+#define DP83TD510_AUTO_NEG_P2P 0
+
+const int dp83td510_feature_array[4] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+};
+
+struct dp83td510_private {
+ u32 hi_diff_output;
+ u32 tx_fifo_depth;
+ u32 rgmii_delay;
+ bool is_rgmii;
+};
+
+struct dp83td510_init_reg {
+ int reg;
+ int val;
+};
+
+static struct dp83td510_init_reg dp83td510_errata[] = {
+ { 0x608, 0x003b }, /* disable_0_transition */
+ { 0x862, 0x39f8 }, /* AGC Gain during Autoneg */
+ { 0x8
[PATCH net-next v4 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Add the 10BASE-T1L linkmodes for ethtool to properly advertise the PHY's capability. Dan Dan Murphy (4): ethtool: Add 10base-T1L link mode entries dt-bindings: net: Add Rx/Tx output configuration for 10base T1L dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ethernet-phy.yaml | 6 + .../devicetree/bindings/net/ti,dp83td510.yaml | 64 +++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 505 ++ drivers/net/phy/phy-core.c| 4 +- include/uapi/linux/ethtool.h | 2 + net/ethtool/common.c | 2 + net/ethtool/linkmodes.c | 2 + 9 files changed, 591 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.29.2
Re: [PATCH] leds: lp50xx: add missing fwnode_handle_put in error handling case
Hello
On 11/10/20 9:21 PM, Qinglang Miao wrote:
Fix to goto child_out to do fwnode_handle_put(child)
from the error handling case rather than simply return,
as done elsewhere in this function.
Fixes: 242b81170fb8 ("leds: lp50xx: Add the LP50XX family of the RGB LED
driver")
Reported-by: Hulk Robot
Signed-off-by: Qinglang Miao
---
drivers/leds/leds-lp50xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/leds/leds-lp50xx.c b/drivers/leds/leds-lp50xx.c
index 5fb4f24aeb2e..49a997b2c781 100644
--- a/drivers/leds/leds-lp50xx.c
+++ b/drivers/leds/leds-lp50xx.c
@@ -488,7 +488,7 @@ static int lp50xx_probe_dt(struct lp50xx *priv)
mc_led_info = devm_kcalloc(priv->dev, LP50XX_LEDS_PER_MODULE,
sizeof(*mc_led_info), GFP_KERNEL);
if (!mc_led_info)
- return -ENOMEM;
+ goto child_out;
Thanks for the patch.
Need to set ret = -ENOMEM; then do child_out so the error is reported
properly
Dan
Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew
On 11/3/20 11:18 AM, Andrew Lunn wrote:
On Tue, Nov 03, 2020 at 11:07:00AM -0600, Dan Murphy wrote:
Andrew
On 10/30/20 3:15 PM, Andrew Lunn wrote:
+static int dp83td510_config_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ int mst_slave_cfg;
+ int ret = 0;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ if (dp83td510->rgmii_delay) {
+ ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR,
+ DP83TD510_MAC_CFG_1,
dp83td510->rgmii_delay);
+ if (ret)
+ return ret;
+ }
+ }
Hi Dan
I'm getting a bit paranoid about RGMII delays...
Not sure what this means.
See the discussion and breakage around the realtek PHY. It wrongly
implemented RGMII delays. When it was fixed, lots of board broke
because the bug in the PHY driver hid bugs in the DT.
I will have to go find that thread. Do you have a link?
Please don't use device_property_read_foo API, we don't want to give
the impression it is O.K. to stuff DT properties in ACPI
tables. Please use of_ API calls.
Hmm. Is this a new stance in DT handling for the networking tree?
If it is should I go back and rework some of my other drivers that use
device_property APIs
There is a slowly growing understanding what ACPI support in this area
means. It seems to mean that the firmware should actually do all the
setup, and the kernel should not touch the hardware configuration. But
some developers are ignoring this, and just stuffing DT properties
into ACPI tables and letting the kernel configure the hardware, if it
happens to use the device_property_read API. So i want to make it
clear that these properties are for device tree, and if you want to
use ACPI, you should do things the ACPI way.
For new code, i will be pushing for OF only calls. Older code is a bit
more tricky. There might be boards out there using ACPI, but doing it
wrongly, and stuffing OF properties into ACPI tables. We should try to
avoid breaking them.
Got it. I will move back to of_* calls
Dan
Andrew
Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew
On 11/3/20 11:21 AM, Andrew Lunn wrote:
On Tue, Nov 03, 2020 at 11:09:44AM -0600, Dan Murphy wrote:
Hello
On 10/30/20 6:03 PM, Jakub Kicinski wrote:
On Fri, 30 Oct 2020 12:29:50 -0500 Dan Murphy wrote:
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
drivers/net/phy/dp83td510.c:70:11: warning: symbol 'dp83td510_feature_array'
was not declared. Should it be static?
I did not see this warning. Did you use W=1?
I _think_ that one is W=1. All the PHY drivers are W=1 clean, and i
want to keep it that way. And i hope to make it the default in a lot
of the network code soon.
OK I built with the W=1 before submission I did not see this but I will
try some other things.
Also this:
WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
#429: FILE: drivers/net/phy/dp83td510.c:371:
+ return -ENOTSUPP;
WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
#524: FILE: drivers/net/phy/dp83td510.c:466:
+ return -ENOTSUPP;
Same with these warnings how where they reproduced?
Same as above
ERROR: space required before the open parenthesis '('
#580: FILE: drivers/net/phy/dp83td510.c:522:
+ if(phydev->autoneg) {
ERROR: space required before the open parenthesis '('
#588: FILE: drivers/net/phy/dp83td510.c:530:
+ if(phydev->autoneg) {
These look like checkpatch.
These I missed
And please try to wrap the code on 80 chars on the non trivial lines:
What is the LoC limit for networking just for my clarification and I will
align with that.
80. I would not be too surprised to see checkpatch getting a patch to
set it to 80 for networking code.
OK I will align the lines to 80 then.
Dan
Andrew
Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Hello
On 10/30/20 6:03 PM, Jakub Kicinski wrote:
On Fri, 30 Oct 2020 12:29:50 -0500 Dan Murphy wrote:
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
drivers/net/phy/dp83td510.c:70:11: warning: symbol 'dp83td510_feature_array'
was not declared. Should it be static?
I did not see this warning. Did you use W=1?
Also this:
WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
#429: FILE: drivers/net/phy/dp83td510.c:371:
+ return -ENOTSUPP;
WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
#524: FILE: drivers/net/phy/dp83td510.c:466:
+ return -ENOTSUPP;
Same with these warnings how where they reproduced?
ERROR: space required before the open parenthesis '('
#580: FILE: drivers/net/phy/dp83td510.c:522:
+ if(phydev->autoneg) {
ERROR: space required before the open parenthesis '('
#588: FILE: drivers/net/phy/dp83td510.c:530:
+ if(phydev->autoneg) {
And please try to wrap the code on 80 chars on the non trivial lines:
What is the LoC limit for networking just for my clarification and I
will align with that.
I know some maintainers like to keep the 80 LoC and some allow a longer
line.
Dan
Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew
On 10/30/20 3:15 PM, Andrew Lunn wrote:
+static int dp83td510_config_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ int mst_slave_cfg;
+ int ret = 0;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ if (dp83td510->rgmii_delay) {
+ ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR,
+ DP83TD510_MAC_CFG_1,
dp83td510->rgmii_delay);
+ if (ret)
+ return ret;
+ }
+ }
Hi Dan
I'm getting a bit paranoid about RGMII delays...
Not sure what this means.
+static int dp83td510_read_straps(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ int strap;
+
+ strap = phy_read_mmd(phydev, DP83TD510_DEVADDR, DP83TD510_SOR_1);
+ if (strap < 0)
+ return strap;
+
+ if (strap & DP83TD510_RGMII)
+ dp83td510->is_rgmii = true;
+
+ return 0;
+};
So dp83td510->is_rgmii is the strapping configuration. So if one of
the four RGMII modes is selected, your appear to ignore which of the
four is selected, and program the hardware with the strapping?
That seems like a bad idea.
I will re-look at this code.
+#if IS_ENABLED(CONFIG_OF_MDIO)
+static int dp83td510_of_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ struct device *dev = >mdio.dev;
+ struct device_node *of_node = dev->of_node;
+ s32 rx_int_delay;
+ s32 tx_int_delay;
+ int ret;
+
+ if (!of_node)
+ return -ENODEV;
+
+ ret = dp83td510_read_straps(phydev);
+ if (ret)
+ return ret;
+
+ dp83td510->hi_diff_output = device_property_read_bool(>mdio.dev,
+
"tx-rx-output-high");
+
+ if (device_property_read_u32(>mdio.dev, "tx-fifo-depth",
+>tx_fifo_depth))
+ dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_5_B_NIB;
Please don't use device_property_read_foo API, we don't want to give
the impression it is O.K. to stuff DT properties in ACPI
tables. Please use of_ API calls.
Hmm. Is this a new stance in DT handling for the networking tree?
If it is should I go back and rework some of my other drivers that use
device_property APIs
Dan
Re: [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L
Andrew On 10/30/20 2:56 PM, Andrew Lunn wrote: On Fri, Oct 30, 2020 at 12:29:48PM -0500, Dan Murphy wrote: Per the 802.3cg spec the 10base T1L can operate at 2 different differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to drive that output is dependent on the PHY's on board power supply. Hi Dan So this property is about the board being able to support the needed voltages? The PHY is not forced into 2.4v p2p, it just says the PHY can operate at 2.4v and the board will not melt, blow a fuse, etc? I actually think it is normal to specify the reverse. List the maximum that device can do because of board restrictions. e.g. - maximum-power-milliwatt : Maximum module power consumption Specifies the maximum power consumption allowable by a module in the slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W. - max-link-speed: If present this property specifies PCI gen for link capability. Host drivers could add this as a strategy to avoid unnecessary operation for unsupported link speed, for instance, trying to do training for unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are invalid. - max-microvolt : The maximum voltage value supplied to the haptic motor. [The unit of the voltage is a micro] So i think this property should be max-tx-rx-p2p = <1000>; When I was re-writing the code I couldn't come up with a better property name but I like this one. I will implement it. Do you have any issue with the property being in the ethernet-phy.yaml? Dan
Re: [PATCH v7 0/6] Add support for the IEI WT61P803 PUZZLE MCU
Hello On 11/2/20 1:03 PM, Pavel Machek wrote: On Mon 2020-11-02 12:29:59, Dan Murphy wrote: Hello On 11/1/20 3:56 AM, Luka Kovacic wrote: Hello Pavel, On Thu, Oct 29, 2020 at 7:01 PM Pavel Machek wrote: Hi! +What: /sys/bus/serial/devices/.../iei_wt61p803_puzzle_core/power_status +Date:September 2020 +Contact: Luka Kovacic +Description: (RO) Power status indicates the host platform power on method. + Value mapping (bitwise list): + 0x80 - Null + 0x40 - Firmware flag + 0x20 - Power loss detection flag (powered off) + 0x10 - Power loss detection flag (AC mode) + 0x08 - Button power on + 0x04 - WOL power on + 0x02 - RTC alarm power on + 0x01 - AC recover power on It would be nice to put this into standard place somewhere. Many machines will want to expose this information. As this is specific to this microcontroller and to how it encodes these values, I don't see a need to change this. This isn't used anywhere else. If not, at least spell out WoL, as it is not that common of acronym. Okay. WoL is a very common acronym especially in the networking space WoL is common. WOL is not. Better spell it out. Agreed. Especially if WOL does not mean Wake On Lan Dan
Re: [PATCH v7 0/6] Add support for the IEI WT61P803 PUZZLE MCU
Hello On 11/1/20 3:56 AM, Luka Kovacic wrote: Hello Pavel, On Thu, Oct 29, 2020 at 7:01 PM Pavel Machek wrote: Hi! +What: /sys/bus/serial/devices/.../iei_wt61p803_puzzle_core/power_status +Date:September 2020 +Contact: Luka Kovacic +Description: (RO) Power status indicates the host platform power on method. + Value mapping (bitwise list): + 0x80 - Null + 0x40 - Firmware flag + 0x20 - Power loss detection flag (powered off) + 0x10 - Power loss detection flag (AC mode) + 0x08 - Button power on + 0x04 - WOL power on + 0x02 - RTC alarm power on + 0x01 - AC recover power on It would be nice to put this into standard place somewhere. Many machines will want to expose this information. As this is specific to this microcontroller and to how it encodes these values, I don't see a need to change this. This isn't used anywhere else. If not, at least spell out WoL, as it is not that common of acronym. Okay. WoL is a very common acronym especially in the networking space But the overall this section does not make sense The description says that it indicates platform power on method but what is NULL power on? There are flags for power loss detection. Does the RTC mean that the processor real time clock woke up the uC? Or that the internal RTC woke up the controller? And for the /sys/bus/serial/devices/.../iei_wt61p803_puzzle_core/ac_recovery_status what are those values? It seems like some ABI's are documented well with formats and others are just described without a format. For instance /sys/bus/serial/devices/.../iei_wt61p803_puzzle_core/version the format of this version is not described but /sys/bus/serial/devices/.../iei_wt61p803_puzzle_core/build_info is. Dan
[PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
The DP83TD510 is a 10M single twisted pair Ethernet PHY
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
new file mode 100644
index ..aef949c1cfdd
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: TI DP83TD510 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+ - $ref: "ethernet-phy.yaml#"
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
+ RGMII interfaces.
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
+
+properties:
+ reg:
+maxItems: 1
+
+ tx-fifo-depth:
+description: |
+ Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
+ depths. The valid nibble depths are 4, 5, 6 and 8.
+enum: [ 4, 5, 6, 8 ]
+default: 5
+
+ rx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 30ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY has a range of -4 to 4ns
+ relative to transmit data.
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+tx-rx-output-high;
+tx-fifo-depth = <5>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
--
2.28.0.585.ge1cfff676549
[PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile| 1 +
drivers/net/phy/dp83td510.c | 681
3 files changed, 688 insertions(+)
create mode 100644 drivers/net/phy/dp83td510.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..017252e1504c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -302,6 +302,12 @@ config DP83869_PHY
Currently supports the DP83869 PHY. This PHY supports copper and
fiber connections.
+config DP83TD510_PHY
+ tristate "Texas Instruments DP83TD510 10M Single Pair Ethernet PHY"
+ help
+ Support for the DP83TD510 Ethernet PHY. This PHY supports a 10M single
+ pair Ethernet connection.
+
config VITESSE_PHY
tristate "Vitesse PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..bf62ce211eb4 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
obj-$(CONFIG_DP83867_PHY) += dp83867.o
obj-$(CONFIG_DP83869_PHY) += dp83869.o
obj-$(CONFIG_DP83TC811_PHY)+= dp83tc811.o
+obj-$(CONFIG_DP83TD510_PHY)+= dp83td510.o
obj-$(CONFIG_FIXED_PHY)+= fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
new file mode 100644
index ..0d1471bdcd45
--- /dev/null
+++ b/drivers/net/phy/dp83td510.c
@@ -0,0 +1,681 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Driver for the Texas Instruments DP83TD510 PHY
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DP83TD510E_PHY_ID 0x2180
+#define DP83TD510_DEVADDR_AN 0x7
+#define DP83TD510_DEVADDR 0x1f
+#define DP83TD510_PMD_DEVADDR 0x1
+
+#define DP83TD510_MII_REG 0x0
+#define DP83TD510_PHY_STAT 0x10
+#define DP83TD510_GEN_CFG 0x11
+#define DP83TD510_INT_REG1 0x12
+#define DP83TD510_INT_REG2 0x13
+#define DP83TD510_MAC_CFG_10x17
+
+#define DP83TD510_ANEG_CTRL0x200
+#define DP83TD510_PMD_CTRL 0x834
+
+#define DP83TD510_SOR_10x467
+
+#define DP83TD510_HW_RESET BIT(15)
+#define DP83TD510_SW_RESET BIT(14)
+
+/* GEN CFG bits */
+#define DP83TD510_INT_OE BIT(0)
+#define DP83TD510_INT_EN BIT(1)
+
+/* INT REG 1 bits */
+#define DP83TD510_INT1_ESD_EN BIT(3)
+#define DP83TD510_INT1_LINK_EN BIT(5)
+#define DP83TD510_INT1_RHF_EN BIT(7)
+#define DP83TD510_INT1_ESD BIT(11)
+#define DP83TD510_INT1_LINKBIT(13)
+#define DP83TD510_INT1_RHF BIT(15)
+
+/* INT REG 2 bits */
+#define DP83TD510_INT2_POR_EN BIT(0)
+#define DP83TD510_INT2_POL_EN BIT(1)
+#define DP83TD510_INT2_PAGE_EN BIT(5)
+#define DP83TD510_INT2_POR BIT(8)
+#define DP83TD510_INT2_POL BIT(9)
+#define DP83TD510_INT2_PAGEBIT(13)
+
+/* MAC CFG bits */
+#define DP83TD510_RX_CLK_SHIFT BIT(12)
+#define DP83TD510_TX_CLK_SHIFT BIT(11)
+
+#define DP83TD510_MASTER_MODE BIT(14)
+#define DP83TD510_AUTO_NEG_EN BIT(12)
+#define DP83TD510_2_4V BIT(7)
+#define DP83TD510_RGMIIBIT(8)
+
+#define DP83TD510_FIFO_DEPTH_MASK GENMASK(6, 5)
+#define DP83TD510_FIFO_DEPTH_4_B_NIB 0
+#define DP83TD510_FIFO_DEPTH_5_B_NIB BIT(5)
+#define DP83TD510_FIFO_DEPTH_6_B_NIB BIT(6)
+#define DP83TD510_FIFO_DEPTH_8_B_NIB (BIT(5) | BIT(6))
+
+const int dp83td510_feature_array[3] = {
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+};
+
+struct dp83td510_private {
+ bool hi_diff_output;
+ u32 tx_fifo_depth;
+ u32 rgmii_delay;
+ bool is_rgmii;
+};
+
+struct dp83td510_init_reg {
+ int reg;
+ int val;
+};
+
+static struct dp83td510_init_reg dp83td510_master_1_0[] = {
+ { 0x000d, 0x0001 }, /* force 1.0v swing */
+ { 0x000e, 0x08f6 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x },
+ { 0x0608, 0x003b }, /* disable_0_transition */
+ { 0x0862, 0x39f8 }, /* AGC Gain during Autoneg */
+ { 0x081a, 0x67c0 }, /* deq offset for 1V swing */
+ { 0x081c, 0xfb62 }, /* deq offset for 2.4V swing */
+ { 0x0830, 0x05a3 }, /* Enable energy lost fallback */
+ { 0x0855, 0x1b55 }, /* MSE Threshold change */
+ { 0x0831, 0x0403 }, /* energy detect threshold */
+ { 0x0856, 0x1800 }, /*
[PATCH net-next v3 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Add the 10BASE-T1L linkmodes for ethtool to properly advertise the PHY's capability. Dan Dan Murphy (4): ethtool: Add 10base-T1L link mode entries dt-bindings: net: Add Rx/Tx output configuration for 10base T1L dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ethernet-phy.yaml | 5 + .../devicetree/bindings/net/ti,dp83td510.yaml | 62 ++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 681 ++ drivers/net/phy/phy-core.c| 4 +- include/uapi/linux/ethtool.h | 2 + net/ethtool/common.c | 2 + net/ethtool/linkmodes.c | 2 + 9 files changed, 764 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.28.0.585.ge1cfff676549
[PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries
Add entries for the 10base-T1L full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ TP ]
Supported link modes: 10baseT1L/Half 10baseT1L/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT1L/Half 10baseT1L/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Full
Auto-negotiation: on
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x (0)
Link detected: yes
Signed-off-by: Dan Murphy
---
drivers/net/phy/phy-core.c | 4 +++-
include/uapi/linux/ethtool.h | 2 ++
net/ethtool/common.c | 2 ++
net/ethtool/linkmodes.c | 2 ++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 8d333d3084ed..616fae7f0c86 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 94,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync.
"
"If a speed or mode has been added please update
phy_speed_to_str "
"and the PHY settings array.\n");
@@ -175,6 +175,8 @@ static const struct phy_setting settings[] = {
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
+ PHY_SETTING( 10, FULL, 10baseT1L_Full ),
+ PHY_SETTING( 10, HALF, 10baseT1L_Half ),
};
#undef PHY_SETTING
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 9ca87bc73c44..16b6ea7548d3 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1619,6 +1619,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT = 92,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 93,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 24036e3055a1..95f87febc742 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -194,6 +194,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(40, CR4, Full),
__DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Half),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index c5bcb9abc8b9..a8fab6fb1b30 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -264,6 +264,8 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(40, CR4, Full),
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Half),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
};
const struct nla_policy ethnl_linkmodes_set_policy[] = {
--
2.28.0.585.ge1cfff676549
[PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L
Per the 802.3cg spec the 10base T1L can operate at 2 different differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to drive that output is dependent on the PHY's on board power supply. This common feature is applicable to all 10base T1L PHYs so this binding property belongs in a top level ethernet document. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 6dd72faebd89..5cad653e143b 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -174,6 +174,11 @@ properties: PHY's that have configurable TX internal delays. If this property is present then the PHY applies the TX delay. + tx-rx-output-high: +type: boolean +description: | + Enable the 2.4v p2p differential output voltage for 10base-T1L PHYs. + required: - reg -- 2.28.0.585.ge1cfff676549
Re: [PATCH net-next v2 2/3] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
Andrew On 10/20/20 2:07 PM, Andrew Lunn wrote: Humm. Are 1v and 2.4v advertised so it can be auto negotiated? Maybe a PHY tunable is not correct? Is this voltage selection actually more like pause and EEE? [Goes and looks at the datasheet] Register 0x20E, bit 13: 1 = Advertise that the 10BASE-T1L PHY has increased transmit/ receive level ability 0 = Do not advertise that the 10BASE-T1L PHY has increased transmit/receive level ability (default) So does this mean 2.4v? This can also be strapped to a certain voltage level. The device may not have the regulators on board to drive a 2.4v signal. 1v signal AVDD is 1.8v and 2.4v the AVDD needs to be at least 3.3v This Strap defines the voltage level requested by PHY during auto negotiation. It is reflected in bit 12 of 0x20E. While using Force mode for Linkup, the strap controls the output voltage and reflects in bit 12 of 0x18F6 Bit 12 1 = Enable 2.4 Vpp operating mode 0 = Enable 1.0 Vpp operating mode So maybe this is a hybrid of tunable for master/slave and a DT for voltage level since the ability of the board to drive the signal can vary. Dan Andrew
[PATCH net-next v2 3/3] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile| 1 +
drivers/net/phy/dp83td510.c | 600
3 files changed, 607 insertions(+)
create mode 100644 drivers/net/phy/dp83td510.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..017252e1504c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -302,6 +302,12 @@ config DP83869_PHY
Currently supports the DP83869 PHY. This PHY supports copper and
fiber connections.
+config DP83TD510_PHY
+ tristate "Texas Instruments DP83TD510 10M Single Pair Ethernet PHY"
+ help
+ Support for the DP83TD510 Ethernet PHY. This PHY supports a 10M single
+ pair Ethernet connection.
+
config VITESSE_PHY
tristate "Vitesse PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..bf62ce211eb4 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
obj-$(CONFIG_DP83867_PHY) += dp83867.o
obj-$(CONFIG_DP83869_PHY) += dp83869.o
obj-$(CONFIG_DP83TC811_PHY)+= dp83tc811.o
+obj-$(CONFIG_DP83TD510_PHY)+= dp83td510.o
obj-$(CONFIG_FIXED_PHY)+= fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
new file mode 100644
index ..756497c592bc
--- /dev/null
+++ b/drivers/net/phy/dp83td510.c
@@ -0,0 +1,600 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Driver for the Texas Instruments DP83TD510 PHY
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DP83TD510E_PHY_ID 0x2180
+#define DP83TD510_DEVADDR_AN 0x7
+#define DP83TD510_DEVADDR 0x1f
+
+#define DP83TD510_MII_REG 0x0
+#define DP83TD510_PHY_STAT 0x10
+#define DP83TD510_GEN_CFG 0x11
+#define DP83TD510_INT_REG1 0x12
+#define DP83TD510_INT_REG2 0x13
+#define DP83TD510_MAC_CFG_10x17
+
+#define DP83TD510_SOR_10x467
+
+#define DP83TD510_HW_RESET BIT(15)
+#define DP83TD510_SW_RESET BIT(14)
+
+/* GEN CFG bits */
+#define DP83TD510_INT_OE BIT(0)
+#define DP83TD510_INT_EN BIT(1)
+
+/* INT REG 1 bits */
+#define DP83TD510_INT1_ESD_EN BIT(3)
+#define DP83TD510_INT1_LINK_EN BIT(5)
+#define DP83TD510_INT1_RHF_EN BIT(7)
+#define DP83TD510_INT1_ESD BIT(11)
+#define DP83TD510_INT1_LINKBIT(13)
+#define DP83TD510_INT1_RHF BIT(15)
+
+/* INT REG 2 bits */
+#define DP83TD510_INT2_POR_EN BIT(0)
+#define DP83TD510_INT2_POL_EN BIT(1)
+#define DP83TD510_INT2_PAGE_EN BIT(5)
+#define DP83TD510_INT2_POR BIT(8)
+#define DP83TD510_INT2_POL BIT(9)
+#define DP83TD510_INT2_PAGEBIT(13)
+
+/* MAC CFG bits */
+#define DP83TD510_RX_CLK_SHIFT BIT(12)
+#define DP83TD510_TX_CLK_SHIFT BIT(11)
+
+#define DP83TD510_MASTER_MODE BIT(2)
+#define DP83TD510_2_4V BIT(7)
+#define DP83TD510_RGMIIBIT(8)
+
+#define DP83TD510_FIFO_DEPTH_MASK GENMASK(6, 5)
+#define DP83TD510_FIFO_DEPTH_4_B_NIB 0
+#define DP83TD510_FIFO_DEPTH_5_B_NIB BIT(5)
+#define DP83TD510_FIFO_DEPTH_6_B_NIB BIT(6)
+#define DP83TD510_FIFO_DEPTH_8_B_NIB (BIT(5) | BIT(6))
+
+enum dp83td510_mode_config {
+ DP83TD510_AUTO_NEG = 0,
+ DP83TD510_MASTER_1 = 1,
+ DP83TD510_MASTER_24 = 2,
+ DP83TD510_SLAVE_1 = 3,
+ DP83TD510_SLAVE_24 = 4,
+};
+
+const int dp83td510_feature_array[3] = {
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+};
+
+struct dp83td510_private {
+ u32 forced_mode;
+ u32 tx_fifo_depth;
+ u32 rgmii_delay;
+ bool is_rgmii;
+};
+
+struct dp83td510_init_reg {
+ int reg;
+ int val;
+};
+
+static struct dp83td510_init_reg dp83td510_master_1_0[] = {
+ { 0x000d, 0x0007 }, /* disable auto-neg */
+ { 0x000e, 0x0200 },
+ { 0x000d, 0x4007 },
+ { 0x000e, 0x },
+ { 0x000d, 0x0001 }, /* force master mode */
+ { 0x000e, 0x0834 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x4000 },
+ { 0x000d, 0x0001 }, /* force 1.0v swing */
+ { 0x000e, 0x08f6 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x },
+ { 0x0608, 0x003b }, /* disable_0_transition */
+ { 0x0862, 0x39f8 }, /* AGC Gain during Autoneg */
+ { 0x08
[PATCH net-next v2 1/3] ethtool: Add 10base-T1L link mode entries
Add entries for the 10base-T1L full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ TPMII ]
Supported link modes: 10baseT1L/Half 10baseT1L/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT1L/Half 10baseT1L/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Full
Auto-negotiation: on
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x (0)
Link detected: yes
Signed-off-by: Dan Murphy
---
drivers/net/phy/phy-core.c | 4 +++-
include/uapi/linux/ethtool.h | 2 ++
net/ethtool/common.c | 2 ++
net/ethtool/linkmodes.c | 2 ++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 8d333d3084ed..616fae7f0c86 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 94,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync.
"
"If a speed or mode has been added please update
phy_speed_to_str "
"and the PHY settings array.\n");
@@ -175,6 +175,8 @@ static const struct phy_setting settings[] = {
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
+ PHY_SETTING( 10, FULL, 10baseT1L_Full ),
+ PHY_SETTING( 10, HALF, 10baseT1L_Half ),
};
#undef PHY_SETTING
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 9ca87bc73c44..16b6ea7548d3 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1619,6 +1619,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT = 92,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 93,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 24036e3055a1..95f87febc742 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -194,6 +194,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(40, CR4, Full),
__DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Half),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index c5bcb9abc8b9..a8fab6fb1b30 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -264,6 +264,8 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(40, CR4, Full),
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Half),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
};
const struct nla_policy ethnl_linkmodes_set_policy[] = {
--
2.28.0.585.ge1cfff676549
[PATCH net-next v2 2/3] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
The DP83TD510 is a 10M single twisted pair Ethernet PHY
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83td510.yaml | 72 +++
1 file changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
new file mode 100644
index ..171aed0f2503
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: TI DP83TD510 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+ - $ref: "ethernet-phy.yaml#"
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
+ RGMII interfaces.
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
+
+properties:
+ reg:
+maxItems: 1
+
+ tx-fifo-depth:
+description: |
+ Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
+ depths. The valid nibble depths are 4, 5, 6 and 8.
+default: 5
+
+ rx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 30ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY has a range of -4 to 4ns
+ relative to transmit data.
+
+ ti,master-slave-mode:
+$ref: /schemas/types.yaml#definitions/uint32
+default: 0
+description: |
+ Force the PHY to be configured to a specific mode.
+ Force Auto Negotiation - 0
+ Force Master mode at 1v p2p - 1
+ Force Master mode at 2.4v p2p - 2
+ Force Slave mode at 1v p2p - 3
+ Force Slave mode at 2.4v p2p - 4
+enum: [ 0, 1, 2, 3, 4 ]
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+tx-fifo-depth = <5>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
--
2.28.0.585.ge1cfff676549
[PATCH net-next v2 0/3] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Add the 10BASE-T1L linkmodes for ethtool to properly advertise the PHY's capability. Dan Dan Murphy (3): ethtool: Add 10base-T1L link mode entries dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ti,dp83td510.yaml | 72 +++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 600 ++ drivers/net/phy/phy-core.c| 4 +- include/uapi/linux/ethtool.h | 2 + net/ethtool/common.c | 2 + net/ethtool/linkmodes.c | 2 + 8 files changed, 688 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.28.0.585.ge1cfff676549
Re: [PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew On 10/19/20 5:04 PM, Dan Murphy wrote: Andrew On 10/19/20 4:55 PM, Andrew Lunn wrote: On Mon, Oct 19, 2020 at 04:33:18PM -0500, Dan Murphy wrote: Andrew On 10/16/20 5:02 PM, Andrew Lunn wrote: On Thu, Oct 08, 2020 at 11:23:47AM -0500, Dan Murphy wrote: The DP83TD510E is an ultra-low power Ethernet physical layer transceiver that supports 10M single pair cable. Hi Dan I think you are going to have to add ETHTOOL_LINK_MODE_10baseT1_Full_BIT? We already have 100T1 and 1000T1, but not 10T1 :-( The data sheet says 10baseT1L. Which is not there either and seems to be the latest 802.3cg spec and has a greater max distance and used for IoT and Automotive. Hi Dan Do you know anything about interropibility? Can a T1 and a T1L talk to each other, if suitably close? I'm wondering if this device should say it is both T1 and T1L? Or just T1L? I personally don't know about interoperability my tests were T1L to T1L but I forwarded these questions to my HW PHY team. HW team says no to interoperability. So we can just add T1L and advertise that type. The DP83TD510L capability is limited to 10Base-T1L only. Dan
Re: [PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew On 10/19/20 4:55 PM, Andrew Lunn wrote: On Mon, Oct 19, 2020 at 04:33:18PM -0500, Dan Murphy wrote: Andrew On 10/16/20 5:02 PM, Andrew Lunn wrote: On Thu, Oct 08, 2020 at 11:23:47AM -0500, Dan Murphy wrote: The DP83TD510E is an ultra-low power Ethernet physical layer transceiver that supports 10M single pair cable. Hi Dan I think you are going to have to add ETHTOOL_LINK_MODE_10baseT1_Full_BIT? We already have 100T1 and 1000T1, but not 10T1 :-( The data sheet says 10baseT1L. Which is not there either and seems to be the latest 802.3cg spec and has a greater max distance and used for IoT and Automotive. Hi Dan Do you know anything about interropibility? Can a T1 and a T1L talk to each other, if suitably close? I'm wondering if this device should say it is both T1 and T1L? Or just T1L? I personally don't know about interoperability my tests were T1L to T1L but I forwarded these questions to my HW PHY team. Dan Andrew
Re: [PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew On 10/16/20 5:02 PM, Andrew Lunn wrote: On Thu, Oct 08, 2020 at 11:23:47AM -0500, Dan Murphy wrote: The DP83TD510E is an ultra-low power Ethernet physical layer transceiver that supports 10M single pair cable. Hi Dan I think you are going to have to add ETHTOOL_LINK_MODE_10baseT1_Full_BIT? We already have 100T1 and 1000T1, but not 10T1 :-( The data sheet says 10baseT1L. Which is not there either and seems to be the latest 802.3cg spec and has a greater max distance and used for IoT and Automotive. Dan Andrew
[PATCH v2] dt-bindings: leds: Update devicetree documents for ID_RGB
Update the leds/common.yaml to indicate that the max color ID is 9. Reflect the same change in the leds-class-multicolor.yaml Reported-by: Zhen Lei Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/leds/common.yaml | 2 +- .../devicetree/bindings/leds/leds-class-multicolor.yaml | 9 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml index a2a541bca73c..0c9f912dfee6 100644 --- a/Documentation/devicetree/bindings/leds/common.yaml +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -43,7 +43,7 @@ properties: LED_COLOR_ID available, add a new one. $ref: /schemas/types.yaml#definitions/uint32 minimum: 0 -maximum: 8 +maximum: 9 function-enumerator: description: diff --git a/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml b/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml index b55e1f1308a4..5e2c850ec9c5 100644 --- a/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml +++ b/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml @@ -16,7 +16,7 @@ description: | modules. This is achieved by adding multi-led nodes layer to the monochrome LED bindings. The nodes and properties defined in this document are unique to the multicolor - LED class. Common LED nodes and properties are inherited from the common.txt + LED class. Common LED nodes and properties are inherited from the common.yaml within this documentation directory. patternProperties: @@ -25,10 +25,11 @@ patternProperties: description: Represents the LEDs that are to be grouped. properties: color: -const: 8 # LED_COLOR_ID_MULTI description: | - For multicolor LED support this property should be defined as - LED_COLOR_ID_MULTI which can be found in include/linux/leds/common.h. + For multicolor LED support this property should be defined as either + LED_COLOR_ID_RGB or LED_COLOR_ID_MULTI which can be found in + include/linux/leds/common.h. +enum: [ 8, 9 ] $ref: "common.yaml#" -- 2.28.0.585.ge1cfff676549
Re: [PATCH] power: supply: bq25980: Fix uninitialized wd_reg_val and overrun
Sebastian On 10/9/20 7:12 AM, Dan Murphy wrote: Fix the issue when 'i' is equal to array size then array index over runs the array when checking for the watch dog value. This also fixes the uninitialized wd_reg_val if the for..loop was not successful in finding an appropriate match. Might want to pull this into next as well this is a 0-day bug fix Dan
Re: [PATCH v4 1/2] dt-bindings: power: Add the bq25790 dt bindings
Sebastian On 10/9/20 9:41 AM, Dan Murphy wrote: Add the bindings for the bq25790. Also any updates on this series? Dan
Re: [PATCH 2/6] dt-bindings: mfd: google,cros-ec: explicitly allow additional properties
Zhen On 10/13/20 11:08 AM, Zhen Lei wrote: There are so many properties have not been described in this yaml file, and a lot of errors will be reported. Especially, some yaml files such as google,cros-ec-typec.yaml, extcon-usbc-cros-ec.yaml can not pass the self-check, because of the examples. So temporarily allow additional properties to keep the comprehensive dt_binding_check result clean. My preference is to fix the binding to pass the checks and not just work around the issues. Working around the issues may mean the issues never get fixed. Dan
[PATCH] dt-bindings: leds: Update devicetree documents for ID_RGB
Update the leds/common.yaml to indicate that the max color ID is 9. Reflect the same change in the leds-class-multicolor.yaml Reported-by: Zhen Lei Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/leds/common.yaml | 2 +- .../devicetree/bindings/leds/leds-class-multicolor.yaml | 9 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml index a2a541bca73c..0c9f912dfee6 100644 --- a/Documentation/devicetree/bindings/leds/common.yaml +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -43,7 +43,7 @@ properties: LED_COLOR_ID available, add a new one. $ref: /schemas/types.yaml#definitions/uint32 minimum: 0 -maximum: 8 +maximum: 9 function-enumerator: description: diff --git a/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml b/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml index b55e1f1308a4..f8032e863ecb 100644 --- a/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml +++ b/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml @@ -16,7 +16,7 @@ description: | modules. This is achieved by adding multi-led nodes layer to the monochrome LED bindings. The nodes and properties defined in this document are unique to the multicolor - LED class. Common LED nodes and properties are inherited from the common.txt + LED class. Common LED nodes and properties are inherited from the common.yaml within this documentation directory. patternProperties: @@ -25,10 +25,11 @@ patternProperties: description: Represents the LEDs that are to be grouped. properties: color: -const: 8 # LED_COLOR_ID_MULTI +const: 9 # LED_COLOR_ID_RGB description: | - For multicolor LED support this property should be defined as - LED_COLOR_ID_MULTI which can be found in include/linux/leds/common.h. + For multicolor LED support this property should be defined as either + LED_COLOR_ID_RGB or LED_COLOR_ID_MULTI which can be found in + include/linux/leds/common.h. $ref: "common.yaml#" -- 2.28.0.585.ge1cfff676549
Re: [PATCH 6/6] dt-bindings: misc: correct the property name cmd-gpios to cmd-gpio
Zhen On 10/13/20 11:08 AM, Zhen Lei wrote: The property name used in arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts is cmd-gpio. arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts:235: cmd-gpio = < 155 GPIO_ACTIVE_HIGH>; Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml b/Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml index b3c45c046ba5e37..c7a06a9650db2ed 100644 --- a/Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml +++ b/Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml @@ -24,7 +24,7 @@ properties: compatible: const: olpc,xo1.75-ec - cmd-gpios: + cmd-gpio: Preference is gpios not gpio. But Rob H accept or reject Dan
Re: [PATCH 1/6] dt-bindings: leds: choose correct color value of multi-led
Zhen On 10/13/20 11:08 AM, Zhen Lei wrote: The color value of multi-led is fixed to "const: 8 #LED_COLOR_ID_MULTI", which is required by leds-class-multicolor.yaml. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/leds/leds-lp55xx.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml b/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml index 58e974793a7976b..cd877e817ad1a1c 100644 --- a/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml +++ b/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml @@ -197,7 +197,7 @@ examples: #address-cells = <1>; #size-cells = <0>; reg = <0x2>; - color = ; + color = ; function = LED_FUNCTION_STANDBY; linux,default-trigger = "heartbeat"; This is not correct. ID_RGB is the correct variable here. https://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds.git/commit/?h=for-next=3d93edc77515c6f51fa9bbbe2185e2ec32bad024 Correct fix is to update the leds-class-multicolor.yaml Dan
Re: [PATCH v2] leds: lm3697: Rename struct into more appropriate name
Pavel On 10/10/20 4:50 PM, Marek Behun wrote: On Sat, 10 Oct 2020 20:57:00 +0200 Pavel Machek wrote: On Fri 2020-10-09 15:51:35, Gabriel David wrote: The mentioned struct, lm3697_led, was renamed to lm3697_bank since the structure is representing the control banks. This name, in my opinion, is more semantically correct. The pointers referring to it were also renamed. Signed-off-by: Gabriel David --- Yes, this is the same Gabriel David from ultracool...@tutanota.org and ultracool...@disroot.org. If you want me to confirm it I'll gladly do it. No problem with that, and no need to resend. This can proably wait for 5.11... I'd like some comment from Dan... and perhaps I'd want to understand what the difference between LED and bank is. ...there can be more than one LED connected to the given bank, that's what you are pointing out? ...but these LEDs will always work in unison, and they are handled as single LED by Linux, right? Pavel, the controller can connect 3 LED strips (to 3 different pins on the chip). There are 2 LED control banks (this is where you can set brightness). For each LED strip (each output pin) you can configure to which control bank it connects. So you have 3 LED strips and 2 control banks, that is 2^3 = 8 different configurations of connecting LED control bank to LED strip. From the perspective of Linux you see the two control banks as 2 LED class devices (because you are setting brightness for control banks, not for the LED strips). The way Marek explains it is correct and the way I wrote the driver intially. There is no direct control of the LEDs only controlling the 2 banks. As an example a device can put LED string 1 and 2 on a single bank to control the backlight for a display and put LED string 3 on a different bank to control the backlight of a keyboard. Like in the Droid and Droid 4 devices. 2 strings illuminate the display backlight and 1 string illuminates the keyboard the display backlight can have a independent brightness then the keyboard. To me the name of the structure does not impose any functional changes just semantic changes. And it just makes it a bit more difficult to back port functional fixes as this patch would be made mandatory for cherry picking. But I do not get many requests to back port this driver so it maybe be a moot point. Dan
[PATCH v4 2/2] power: supply: bq25790: Introduce the BQ25790 charger driver
BQ25790 is a highly integrated switch-mode buck-boost charger
for 1-4 cell Li-ion battery and Li-polymer battery.
Signed-off-by: Ricardo Rivera-Matos
Signed-off-by: Dan Murphy
---
drivers/power/supply/Kconfig |8 +
drivers/power/supply/Makefile |1 +
drivers/power/supply/bq25790_charger.c | 1121
drivers/power/supply/bq25790_charger.h | 150
4 files changed, 1280 insertions(+)
create mode 100644 drivers/power/supply/bq25790_charger.c
create mode 100644 drivers/power/supply/bq25790_charger.h
diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig
index eec646c568b7..1cc361238d9a 100644
--- a/drivers/power/supply/Kconfig
+++ b/drivers/power/supply/Kconfig
@@ -628,6 +628,14 @@ config CHARGER_BQ2515X
rail, ADC for battery and system monitoring, and push-button
controller.
+config CHARGER_BQ25790
+ tristate "TI BQ25790 battery charger driver"
+ depends on I2C
+ depends on GPIOLIB || COMPILE_TEST
+ select REGMAP_I2C
+ help
+ Say Y to enable support for the TI BQ25790 battery charger.
+
config CHARGER_BQ25890
tristate "TI BQ25890 battery charger driver"
depends on I2C
diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile
index dd4b86318cd9..29b71cc92550 100644
--- a/drivers/power/supply/Makefile
+++ b/drivers/power/supply/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_CHARGER_BQ24190) += bq24190_charger.o
obj-$(CONFIG_CHARGER_BQ24257) += bq24257_charger.o
obj-$(CONFIG_CHARGER_BQ24735) += bq24735-charger.o
obj-$(CONFIG_CHARGER_BQ2515X) += bq2515x_charger.o
+obj-$(CONFIG_CHARGER_BQ25790) += bq25790_charger.o
obj-$(CONFIG_CHARGER_BQ25890) += bq25890_charger.o
obj-$(CONFIG_CHARGER_BQ25980) += bq25980_charger.o
obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o
diff --git a/drivers/power/supply/bq25790_charger.c
b/drivers/power/supply/bq25790_charger.c
new file mode 100644
index ..838a49c2f9f0
--- /dev/null
+++ b/drivers/power/supply/bq25790_charger.c
@@ -0,0 +1,1121 @@
+// SPDX-License-Identifier: GPL-2.0
+// BQ25790 driver
+// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "bq25790_charger.h"
+
+#define BQ25790_NUM_WD_VAL 8
+
+struct bq25790_init_data {
+ u32 ichg;
+ u32 ilim;
+ u32 vreg;
+ u32 iterm;
+ u32 iprechg;
+ u32 vlim;
+ u32 ichg_max;
+ u32 vreg_max;
+};
+
+struct bq25790_state {
+ bool online;
+ u8 chrg_status;
+ u8 chrg_type;
+ u8 health;
+ u8 chrg_fault;
+ u8 vsys_status;
+ u8 vbus_status;
+ u8 fault_0;
+ u8 fault_1;
+ u32 vbat_adc;
+ u32 vbus_adc;
+ u32 ibat_adc;
+};
+
+struct bq25790_device {
+ struct i2c_client *client;
+ struct device *dev;
+ struct power_supply *charger;
+ struct power_supply *battery;
+ struct mutex lock;
+
+ struct usb_phy *usb2_phy;
+ struct usb_phy *usb3_phy;
+ struct notifier_block usb_nb;
+ struct work_struct usb_work;
+ unsigned long usb_event;
+ struct regmap *regmap;
+
+ char model_name[I2C_NAME_SIZE];
+ int device_id;
+
+ struct bq25790_init_data init_data;
+ struct bq25790_state state;
+ int watchdog_timer;
+};
+
+static struct reg_default bq25790_reg_defs[] = {
+ {BQ25790_INPUT_V_LIM, 0x24},
+ {BQ25790_INPUT_I_LIM_MSB, 0x01},
+ {BQ25790_INPUT_I_LIM_LSB, 0x2c},
+ {BQ25790_PRECHRG_CTRL, 0xc3},
+ {BQ25790_TERM_CTRL, 0x5},
+ {BQ25790_VOTG_REG, 0xdc},
+ {BQ25790_IOTG_REG, 0x4b},
+ {BQ25790_TIMER_CTRL, 0x3d},
+ {BQ25790_CHRG_CTRL_0, 0xa2},
+ {BQ25790_CHRG_CTRL_1, 0x85},
+ {BQ25790_CHRG_CTRL_2, 0x40},
+ {BQ25790_CHRG_CTRL_3, 0x12},
+ {BQ25790_CHRG_CTRL_5, 0x16},
+ {BQ25790_MPPT_CTRL, 0xaa},
+ {BQ25790_TEMP_CTRL, 0xc0},
+ {BQ25790_NTC_CTRL_0, 0x7a},
+ {BQ25790_NTC_CTRL_1, 0x54},
+ {BQ25790_ICO_I_LIM, 0x0},
+ {BQ25790_CHRG_STAT_0, 0x0},
+ {BQ25790_CHRG_STAT_1, 0x0},
+ {BQ25790_CHRG_STAT_2, 0x0},
+ {BQ25790_CHRG_STAT_3, 0x0},
+ {BQ25790_CHRG_STAT_4, 0x0},
+ {BQ25790_FAULT_STAT_0, 0x0},
+ {BQ25790_FAULT_STAT_1, 0x0},
+ {BQ25790_CHRG_FLAG_0, 0x0},
+ {BQ25790_CHRG_FLAG_1, 0x0},
+ {BQ25790_CHRG_FLAG_2, 0x0},
+ {BQ25790_CHRG_FLAG_3, 0x0},
+ {BQ25790_FAULT_FLAG_0, 0x0},
+ {BQ25790_FAULT_FLAG_1, 0x0},
+ {BQ25790_CHRG_MSK_0, 0x0},
+ {BQ25790_CHRG_MSK_1, 0x0},
+ {BQ25790_CHRG_MSK_2, 0x0},
+ {BQ25790_CHRG_MSK_3, 0x0},
+ {BQ25790_FAULT_MSK_0, 0x0},
+ {BQ25790_FAULT_MSK_1, 0x0},
+ {BQ25790_ADC_CTRL, 0x30},
+ {BQ25790_FN_DISABE_0, 0x0},
+
[PATCH v4 1/2] dt-bindings: power: Add the bq25790 dt bindings
Add the bindings for the bq25790.
Reviewed-by: Rob Herring
Signed-off-by: Ricardo Rivera-Matos
Signed-off-by: Dan Murphy
---
.../bindings/power/supply/bq25790.yaml| 95 +++
1 file changed, 95 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/supply/bq25790.yaml
diff --git a/Documentation/devicetree/bindings/power/supply/bq25790.yaml
b/Documentation/devicetree/bindings/power/supply/bq25790.yaml
new file mode 100644
index ..6d9178ce5a2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/supply/bq25790.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/supply/bq25790.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: TI BQ25790 Switch Mode Buck-Boost Charger
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ BQ25790 is a highly integrated switch-mode buck-boost charger for 1-4 cell
+ Li-ion batteries and Li-polymer batteries. The device charges a battery from
a
+ wide range of input sources including legacy USB adapters to high voltage USB
+ PD adapters and traditional barrel adapters.
+
+allOf:
+ - $ref: power-supply.yaml#
+
+properties:
+ compatible:
+enum:
+ - ti,bq25790
+ - ti,bq25792
+
+ reg:
+maxItems: 1
+
+ ti,watchdog-timeout-ms:
+default: 0
+description: |
+ Watchdog timer in milli seconds. 0 (default) disables the watchdog.
+minimum: 0
+maximum: 16
+enum: [ 0, 500, 1000, 2000, 2, 4, 8, 16]
+
+ input-voltage-limit-microvolt:
+description: |
+ Minimum input voltage limit in micro volts with a 10 micro volt step.
+minimum: 360
+maximum: 2200
+
+ input-current-limit-microamp:
+description: |
+ Maximum input current limit in micro amps with a 10 micro amp step.
+minimum: 10
+maximum: 330
+
+ monitored-battery:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: phandle to the battery node being monitored
+
+ interrupts:
+maxItems: 1
+description: |
+ Interrupt sends an active low, 256 μs pulse to host to report the charger
+ device status and faults.
+
+required:
+ - compatible
+ - reg
+ - monitored-battery
+
+unevaluatedProperties: false
+
+examples:
+ - |
+bat: battery {
+ compatible = "simple-battery";
+ constant-charge-current-max-microamp = <200>;
+ constant-charge-voltage-max-microvolt = <420>;
+ precharge-current-microamp = <16>;
+ charge-term-current-microamp = <16>;
+};
+#include
+#include
+i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bq25790: charger@6b {
+ compatible = "ti,bq25790";
+ reg = <0x6b>;
+ interrupt-parent = <>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ ti,watchdog-timeout-ms = <2000>;
+ input-current-limit-microamp = <300>;
+ input-voltage-limit-microvolt = <450>;
+ monitored-battery = <>;
+ };
+};
+
+...
--
2.28.0.585.ge1cfff676549
Re: [PATCH v3 2/2] power: supply: bq25790: Introduce the BQ25790 charger driver
Dan On 10/9/20 7:15 AM, Dan Carpenter wrote: Hi Dan, url: https://github.com/0day-ci/linux/commits/Dan-Murphy/dt-bindings-power-Add-the-bq25790-dt-bindings/20201008-234450 base: https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git for-next config: i386-randconfig-m021-20201009 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot Reported-by: Dan Carpenter smatch warnings: drivers/power/supply/bq25790_charger.c:170 bq25790_usb_work() warn: ignoring unreachable code. drivers/power/supply/bq25790_charger.c:624 bq25790_get_property() warn: should this be a bitwise op? Fixing both of these now Dan
[PATCH] power: supply: bq25980: Fix uninitialized wd_reg_val and overrun
Fix the issue when 'i' is equal to array size then array index over
runs the array when checking for the watch dog value.
This also fixes the uninitialized wd_reg_val if the for..loop was not
successful in finding an appropriate match.
Fixes: 5069185fc18e ("power: supply: bq25980: Add support for the BQ259xx
family")
Signed-off-by: Dan Murphy
---
drivers/power/supply/bq25980_charger.c | 29 +-
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/power/supply/bq25980_charger.c
b/drivers/power/supply/bq25980_charger.c
index 3995fb7cf060..e6a91e43ae5b 100644
--- a/drivers/power/supply/bq25980_charger.c
+++ b/drivers/power/supply/bq25980_charger.c
@@ -1099,28 +1099,29 @@ static int bq25980_power_supply_init(struct
bq25980_device *bq,
static int bq25980_hw_init(struct bq25980_device *bq)
{
struct power_supply_battery_info bat_info = { };
- int wd_reg_val;
+ int wd_reg_val = BQ25980_WATCHDOG_DIS;
+ int wd_max_val = BQ25980_NUM_WD_VAL - 1;
int ret = 0;
int curr_val;
int volt_val;
int i;
- if (!bq->watchdog_timer) {
- ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_3,
-BQ25980_WATCHDOG_DIS,
-BQ25980_WATCHDOG_DIS);
- } else {
- for (i = 0; i < BQ25980_NUM_WD_VAL; i++) {
- if (bq->watchdog_timer > bq25980_watchdog_time[i] &&
- bq->watchdog_timer < bq25980_watchdog_time[i + 1]) {
- wd_reg_val = i;
- break;
+ if (bq->watchdog_timer) {
+ if (bq->watchdog_timer >= bq25980_watchdog_time[wd_max_val])
+ wd_reg_val = wd_max_val;
+ else {
+ for (i = 0; i < wd_max_val; i++) {
+ if (bq->watchdog_timer >
bq25980_watchdog_time[i] &&
+ bq->watchdog_timer <
bq25980_watchdog_time[i + 1]) {
+ wd_reg_val = i;
+ break;
+ }
}
}
-
- ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_3,
- BQ25980_WATCHDOG_MASK, wd_reg_val);
}
+
+ ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_3,
+BQ25980_WATCHDOG_MASK, wd_reg_val);
if (ret)
return ret;
--
2.28.0.585.ge1cfff676549
Re: [PATCH net-next 1/2] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
Florian Thanks for the review On 10/8/20 12:11 PM, Florian Fainelli wrote: On 10/8/2020 9:23 AM, Dan Murphy wrote: The DP83TD510 is a 10M single twisted pair Ethernet PHY Signed-off-by: Dan Murphy --- .../devicetree/bindings/net/ti,dp83td510.yaml | 70 +++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml new file mode 100644 index ..0f0eac77a11a --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#; +$schema: "http://devicetree.org/meta-schemas/core.yaml#; + +title: TI DP83TD510 ethernet PHY + +allOf: + - $ref: "ethernet-controller.yaml#" + +maintainers: + - Dan Murphy + +description: | + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and + RGMII interfaces. + + Specifications about the Ethernet PHY can be found at: + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf + +properties: + reg: + maxItems: 1 + + tx-fifo-depth: + description: | + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble + depths. The valid nibble depths are 4, 5, 6 and 8. + default: 5 + + rx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the RX internal delay + for the PHY. The internal delay for the PHY is fixed to 30ns relative + to receive data. + + tx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the TX internal delay + for the PHY. The internal delay for the PHY has a range of -4 to 4ns + relative to transmit data. Those two properties are already defined as part of Documentation/devicetree/bindings/net/ethernet-phy.yaml, so you can reference that binding, too. OK I referenced the ethernet-controller.yaml for the delay. I am wondering if we should add rx/tx-fifo-depth to the ethernet-phy.yaml as well. That way PHYs only have to reference ethernet-phy.yaml. Or maybe remove the internal-delay from the ethernet-phy.yaml and reference the ethernet-controller.yaml in the ethernet-phy.yaml so we don't have to maintain duplicate properties + + ti,master-slave-mode: + $ref: /schemas/types.yaml#definitions/uint32 + default: 0 + description: | + Force the PHY to be configured to a specific mode. + Force Auto Negotiation - 0 + Force Master mode at 1v p2p - 1 + Force Master mode at 2.4v p2p - 2 + Force Slave mode at 1v p2p - 3 + Force Slave mode at 2.4v p2p - 4 If you accept different values you should be indicating which values are supported with an enumeration. Ah yes forgot the min/max
Re: [PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Heiner
On 10/8/20 11:51 AM, Heiner Kallweit wrote:
On 08.10.2020 18:23, Dan Murphy wrote:
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
drivers/net/phy/Kconfig | 6 +
+static struct phy_driver dp83td510_driver[] = {
+ {
+ PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID),
+ .name = "TI DP83TD510E",
+ .probe = dp83td510_probe,
+ .config_init= dp83td510_config_init,
+ .soft_reset = dp83td510_phy_reset,
+ .features = PHY_BASIC_FEATURES,
Per default phylib uses genphy_read_abilities() to auto-detect
the features. Doesn't your PHY support the needed clause 22
standard registers? Or are they incorrectly populated?
Maybe better than setting PHY_BASIC_FEATURES and then removing
unsuported features in dp83td510_config_init() would be to
implement phy_driver callback get_features. Then you can set
the supported fatures directly.
Thanks for the review. I will have to look at this maybe the call back
will be better.
I will probably post v2 after net-next opens for 5.10.
I wanted to get some reviews on this patch before net-next closes for
the merge window.
Dan
[PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile| 1 +
drivers/net/phy/dp83td510.c | 583
3 files changed, 590 insertions(+)
create mode 100644 drivers/net/phy/dp83td510.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..017252e1504c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -302,6 +302,12 @@ config DP83869_PHY
Currently supports the DP83869 PHY. This PHY supports copper and
fiber connections.
+config DP83TD510_PHY
+ tristate "Texas Instruments DP83TD510 10M Single Pair Ethernet PHY"
+ help
+ Support for the DP83TD510 Ethernet PHY. This PHY supports a 10M single
+ pair Ethernet connection.
+
config VITESSE_PHY
tristate "Vitesse PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..bf62ce211eb4 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
obj-$(CONFIG_DP83867_PHY) += dp83867.o
obj-$(CONFIG_DP83869_PHY) += dp83869.o
obj-$(CONFIG_DP83TC811_PHY)+= dp83tc811.o
+obj-$(CONFIG_DP83TD510_PHY)+= dp83td510.o
obj-$(CONFIG_FIXED_PHY)+= fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
new file mode 100644
index ..0cce9063fd1c
--- /dev/null
+++ b/drivers/net/phy/dp83td510.c
@@ -0,0 +1,583 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Driver for the Texas Instruments DP83TD510 PHY
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DP83TD510E_PHY_ID 0x2180
+#define DP83TD510_DEVADDR_AN 0x7
+#define DP83TD510_DEVADDR 0x1f
+
+#define DP83TD510_MII_REG 0x0
+#define DP83TD510_PHY_STAT 0x10
+#define DP83TD510_GEN_CFG 0x11
+#define DP83TD510_INT_REG1 0x12
+#define DP83TD510_INT_REG2 0x13
+#define DP83TD510_MAC_CFG_10x17
+
+#define DP83TD510_SOR_10x467
+
+#define DP83TD510_HW_RESET BIT(15)
+#define DP83TD510_SW_RESET BIT(14)
+
+/* GEN CFG bits */
+#define DP83TD510_INT_OE BIT(0)
+#define DP83TD510_INT_EN BIT(1)
+
+/* INT REG 1 bits */
+#define DP83TD510_INT1_ESD_EN BIT(3)
+#define DP83TD510_INT1_LINK_EN BIT(5)
+#define DP83TD510_INT1_RHF_EN BIT(7)
+#define DP83TD510_INT1_ESD BIT(11)
+#define DP83TD510_INT1_LINKBIT(13)
+#define DP83TD510_INT1_RHF BIT(15)
+
+/* INT REG 2 bits */
+#define DP83TD510_INT2_POR_EN BIT(0)
+#define DP83TD510_INT2_POL_EN BIT(1)
+#define DP83TD510_INT2_PAGE_EN BIT(5)
+#define DP83TD510_INT2_POR BIT(8)
+#define DP83TD510_INT2_POL BIT(9)
+#define DP83TD510_INT2_PAGEBIT(13)
+
+/* MAC CFG bits */
+#define DP83TD510_RX_CLK_SHIFT BIT(12)
+#define DP83TD510_TX_CLK_SHIFT BIT(11)
+
+#define DP83TD510_MASTER_MODE BIT(2)
+#define DP83TD510_2_4V BIT(7)
+#define DP83TD510_RGMIIBIT(8)
+
+#define DP83TD510_FIFO_DEPTH_MASK GENMASK(6, 5)
+#define DP83TD510_FIFO_DEPTH_4_B_NIB 0
+#define DP83TD510_FIFO_DEPTH_5_B_NIB BIT(5)
+#define DP83TD510_FIFO_DEPTH_6_B_NIB BIT(6)
+#define DP83TD510_FIFO_DEPTH_8_B_NIB (BIT(5) | BIT(6))
+
+enum dp83td510_mode_config {
+ DP83TD510_AUTO_NEG = 0,
+ DP83TD510_MASTER_1 = 1,
+ DP83TD510_MASTER_24 = 2,
+ DP83TD510_SLAVE_1 = 3,
+ DP83TD510_SLAVE_24 = 4,
+};
+
+struct dp83td510_private {
+ u32 forced_mode;
+ u32 tx_fifo_depth;
+ u32 rgmii_delay;
+ bool is_rgmii;
+};
+
+struct dp83td510_init_reg {
+ int reg;
+ int val;
+};
+
+static struct dp83td510_init_reg dp83td510_master_1_0[] = {
+ { 0x000d, 0x0007 }, /* disable auto-neg */
+ { 0x000e, 0x0200 },
+ { 0x000d, 0x4007 },
+ { 0x000e, 0x },
+ { 0x000d, 0x0001 }, /* force master mode */
+ { 0x000e, 0x0834 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x4000 },
+ { 0x000d, 0x0001 }, /* force 1.0v swing */
+ { 0x000e, 0x08f6 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x },
+ { 0x0608, 0x003b }, /* disable_0_transition */
+ { 0x0862, 0x39f8 }, /* AGC Gain during Autoneg */
+ { 0x081a, 0x67c0 }, /* deq offset for 1V swing */
+ { 0x081c, 0xfb62 }, /* deq offset for 2.4V swing */
+ { 0x0830, 0x05a3 }, /* Enable energy lost fallback */
+ { 0x08
[PATCH net-next 1/2] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
The DP83TD510 is a 10M single twisted pair Ethernet PHY
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83td510.yaml | 70 +++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
new file mode 100644
index ..0f0eac77a11a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: TI DP83TD510 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
+ RGMII interfaces.
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
+
+properties:
+ reg:
+maxItems: 1
+
+ tx-fifo-depth:
+description: |
+ Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
+ depths. The valid nibble depths are 4, 5, 6 and 8.
+default: 5
+
+ rx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 30ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY has a range of -4 to 4ns
+ relative to transmit data.
+
+ ti,master-slave-mode:
+$ref: /schemas/types.yaml#definitions/uint32
+default: 0
+description: |
+ Force the PHY to be configured to a specific mode.
+ Force Auto Negotiation - 0
+ Force Master mode at 1v p2p - 1
+ Force Master mode at 2.4v p2p - 2
+ Force Slave mode at 1v p2p - 3
+ Force Slave mode at 2.4v p2p - 4
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+tx-fifo-depth = <5>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
--
2.28.0.585.ge1cfff676549
[PATCH net-next 0/2] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Dan Dan Murphy (2): dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ti,dp83td510.yaml | 70 +++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 583 ++ 4 files changed, 660 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.28.0.585.ge1cfff676549
[PATCH net-next 0/2] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Dan Dan Murphy (2): dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ti,dp83td510.yaml | 70 +++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 583 ++ 4 files changed, 660 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.28.0.585.ge1cfff676549
[PATCH v3 1/2] dt-bindings: power: Add the bq25790 dt bindings
Add the bindings for the bq25790.
Reviewed-by: Rob Herring
Signed-off-by: Ricardo Rivera-Matos
Signed-off-by: Dan Murphy
---
.../bindings/power/supply/bq25790.yaml| 95 +++
1 file changed, 95 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/supply/bq25790.yaml
diff --git a/Documentation/devicetree/bindings/power/supply/bq25790.yaml
b/Documentation/devicetree/bindings/power/supply/bq25790.yaml
new file mode 100644
index ..6d9178ce5a2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/supply/bq25790.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/supply/bq25790.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: TI BQ25790 Switch Mode Buck-Boost Charger
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ BQ25790 is a highly integrated switch-mode buck-boost charger for 1-4 cell
+ Li-ion batteries and Li-polymer batteries. The device charges a battery from
a
+ wide range of input sources including legacy USB adapters to high voltage USB
+ PD adapters and traditional barrel adapters.
+
+allOf:
+ - $ref: power-supply.yaml#
+
+properties:
+ compatible:
+enum:
+ - ti,bq25790
+ - ti,bq25792
+
+ reg:
+maxItems: 1
+
+ ti,watchdog-timeout-ms:
+default: 0
+description: |
+ Watchdog timer in milli seconds. 0 (default) disables the watchdog.
+minimum: 0
+maximum: 16
+enum: [ 0, 500, 1000, 2000, 2, 4, 8, 16]
+
+ input-voltage-limit-microvolt:
+description: |
+ Minimum input voltage limit in micro volts with a 10 micro volt step.
+minimum: 360
+maximum: 2200
+
+ input-current-limit-microamp:
+description: |
+ Maximum input current limit in micro amps with a 10 micro amp step.
+minimum: 10
+maximum: 330
+
+ monitored-battery:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: phandle to the battery node being monitored
+
+ interrupts:
+maxItems: 1
+description: |
+ Interrupt sends an active low, 256 μs pulse to host to report the charger
+ device status and faults.
+
+required:
+ - compatible
+ - reg
+ - monitored-battery
+
+unevaluatedProperties: false
+
+examples:
+ - |
+bat: battery {
+ compatible = "simple-battery";
+ constant-charge-current-max-microamp = <200>;
+ constant-charge-voltage-max-microvolt = <420>;
+ precharge-current-microamp = <16>;
+ charge-term-current-microamp = <16>;
+};
+#include
+#include
+i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bq25790: charger@6b {
+ compatible = "ti,bq25790";
+ reg = <0x6b>;
+ interrupt-parent = <>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ ti,watchdog-timeout-ms = <2000>;
+ input-current-limit-microamp = <300>;
+ input-voltage-limit-microvolt = <450>;
+ monitored-battery = <>;
+ };
+};
+
+...
--
2.28.0.585.ge1cfff676549
[PATCH v3 2/2] power: supply: bq25790: Introduce the BQ25790 charger driver
BQ25790 is a highly integrated switch-mode buck-boost charger
for 1-4 cell Li-ion battery and Li-polymer battery.
Signed-off-by: Ricardo Rivera-Matos
Signed-off-by: Dan Murphy
---
drivers/power/supply/Kconfig |8 +
drivers/power/supply/Makefile |1 +
drivers/power/supply/bq25790_charger.c | 1123
drivers/power/supply/bq25790_charger.h | 150
4 files changed, 1282 insertions(+)
create mode 100644 drivers/power/supply/bq25790_charger.c
create mode 100644 drivers/power/supply/bq25790_charger.h
diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig
index eec646c568b7..1cc361238d9a 100644
--- a/drivers/power/supply/Kconfig
+++ b/drivers/power/supply/Kconfig
@@ -628,6 +628,14 @@ config CHARGER_BQ2515X
rail, ADC for battery and system monitoring, and push-button
controller.
+config CHARGER_BQ25790
+ tristate "TI BQ25790 battery charger driver"
+ depends on I2C
+ depends on GPIOLIB || COMPILE_TEST
+ select REGMAP_I2C
+ help
+ Say Y to enable support for the TI BQ25790 battery charger.
+
config CHARGER_BQ25890
tristate "TI BQ25890 battery charger driver"
depends on I2C
diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile
index dd4b86318cd9..29b71cc92550 100644
--- a/drivers/power/supply/Makefile
+++ b/drivers/power/supply/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_CHARGER_BQ24190) += bq24190_charger.o
obj-$(CONFIG_CHARGER_BQ24257) += bq24257_charger.o
obj-$(CONFIG_CHARGER_BQ24735) += bq24735-charger.o
obj-$(CONFIG_CHARGER_BQ2515X) += bq2515x_charger.o
+obj-$(CONFIG_CHARGER_BQ25790) += bq25790_charger.o
obj-$(CONFIG_CHARGER_BQ25890) += bq25890_charger.o
obj-$(CONFIG_CHARGER_BQ25980) += bq25980_charger.o
obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o
diff --git a/drivers/power/supply/bq25790_charger.c
b/drivers/power/supply/bq25790_charger.c
new file mode 100644
index ..717b238eef2e
--- /dev/null
+++ b/drivers/power/supply/bq25790_charger.c
@@ -0,0 +1,1123 @@
+// SPDX-License-Identifier: GPL-2.0
+// BQ25790 driver
+// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "bq25790_charger.h"
+
+#define BQ25790_NUM_WD_VAL 8
+
+struct bq25790_init_data {
+ u32 ichg;
+ u32 ilim;
+ u32 vreg;
+ u32 iterm;
+ u32 iprechg;
+ u32 vlim;
+ u32 ichg_max;
+ u32 vreg_max;
+};
+
+struct bq25790_state {
+ bool online;
+ u8 chrg_status;
+ u8 chrg_type;
+ u8 health;
+ u8 chrg_fault;
+ u8 vsys_status;
+ u8 vbus_status;
+ u8 fault_0;
+ u8 fault_1;
+ u32 vbat_adc;
+ u32 vbus_adc;
+ u32 ibat_adc;
+};
+
+struct bq25790_device {
+ struct i2c_client *client;
+ struct device *dev;
+ struct power_supply *charger;
+ struct power_supply *battery;
+ struct mutex lock;
+
+ struct usb_phy *usb2_phy;
+ struct usb_phy *usb3_phy;
+ struct notifier_block usb_nb;
+ struct work_struct usb_work;
+ unsigned long usb_event;
+ struct regmap *regmap;
+
+ char model_name[I2C_NAME_SIZE];
+ int device_id;
+
+ struct bq25790_init_data init_data;
+ struct bq25790_state state;
+ int watchdog_timer;
+};
+
+static struct reg_default bq25790_reg_defs[] = {
+ {BQ25790_INPUT_V_LIM, 0x24},
+ {BQ25790_INPUT_I_LIM_MSB, 0x01},
+ {BQ25790_INPUT_I_LIM_LSB, 0x2c},
+ {BQ25790_PRECHRG_CTRL, 0xc3},
+ {BQ25790_TERM_CTRL, 0x5},
+ {BQ25790_VOTG_REG, 0xdc},
+ {BQ25790_IOTG_REG, 0x4b},
+ {BQ25790_TIMER_CTRL, 0x3d},
+ {BQ25790_CHRG_CTRL_0, 0xa2},
+ {BQ25790_CHRG_CTRL_1, 0x85},
+ {BQ25790_CHRG_CTRL_2, 0x40},
+ {BQ25790_CHRG_CTRL_3, 0x12},
+ {BQ25790_CHRG_CTRL_5, 0x16},
+ {BQ25790_MPPT_CTRL, 0xaa},
+ {BQ25790_TEMP_CTRL, 0xc0},
+ {BQ25790_NTC_CTRL_0, 0x7a},
+ {BQ25790_NTC_CTRL_1, 0x54},
+ {BQ25790_ICO_I_LIM, 0x0},
+ {BQ25790_CHRG_STAT_0, 0x0},
+ {BQ25790_CHRG_STAT_1, 0x0},
+ {BQ25790_CHRG_STAT_2, 0x0},
+ {BQ25790_CHRG_STAT_3, 0x0},
+ {BQ25790_CHRG_STAT_4, 0x0},
+ {BQ25790_FAULT_STAT_0, 0x0},
+ {BQ25790_FAULT_STAT_1, 0x0},
+ {BQ25790_CHRG_FLAG_0, 0x0},
+ {BQ25790_CHRG_FLAG_1, 0x0},
+ {BQ25790_CHRG_FLAG_2, 0x0},
+ {BQ25790_CHRG_FLAG_3, 0x0},
+ {BQ25790_FAULT_FLAG_0, 0x0},
+ {BQ25790_FAULT_FLAG_1, 0x0},
+ {BQ25790_CHRG_MSK_0, 0x0},
+ {BQ25790_CHRG_MSK_1, 0x0},
+ {BQ25790_CHRG_MSK_2, 0x0},
+ {BQ25790_CHRG_MSK_3, 0x0},
+ {BQ25790_FAULT_MSK_0, 0x0},
+ {BQ25790_FAULT_MSK_1, 0x0},
+ {BQ25790_ADC_CTRL, 0x30},
+ {BQ25790_FN_DISABE_0, 0x0},
+
[PATCH v3 2/2] ASoC: tas2764: Add the driver for the TAS2764
Introduce the Texas Instruments TAS2764 amplifier driver
with I/V sense for loud speaker applications.
Signed-off-by: Dan Murphy
---
sound/soc/codecs/Kconfig | 5 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/tas2764.c | 688 +
sound/soc/codecs/tas2764.h | 92 +
4 files changed, 787 insertions(+)
create mode 100644 sound/soc/codecs/tas2764.c
create mode 100644 sound/soc/codecs/tas2764.h
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index a62e0fb467d9..34c6dd04b85a 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -195,6 +195,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_STI_SAS
imply SND_SOC_TAS2552
imply SND_SOC_TAS2562
+ imply SND_SOC_TAS2764
imply SND_SOC_TAS2770
imply SND_SOC_TAS5086
imply SND_SOC_TAS571X
@@ -1303,6 +1304,10 @@ config SND_SOC_TAS2562
tristate "Texas Instruments TAS2562 Mono Audio amplifier"
depends on I2C
+config SND_SOC_TAS2764
+ tristate "Texas Instruments TAS2764 Mono Audio amplifier"
+ depends on I2C
+
config SND_SOC_TAS2770
tristate "Texas Instruments TAS2770 speaker amplifier"
depends on I2C
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 0404bc1ddcfb..11ce98c25d6c 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -304,6 +304,7 @@ snd-soc-simple-amplifier-objs := simple-amplifier.o
snd-soc-tpa6130a2-objs := tpa6130a2.o
snd-soc-tas2552-objs := tas2552.o
snd-soc-tas2562-objs := tas2562.o
+snd-soc-tas2764-objs := tas2764.o
obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o
obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o
@@ -517,6 +518,7 @@ obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
obj-$(CONFIG_SND_SOC_STI_SAS) += snd-soc-sti-sas.o
obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o
obj-$(CONFIG_SND_SOC_TAS2562) += snd-soc-tas2562.o
+obj-$(CONFIG_SND_SOC_TAS2764) += snd-soc-tas2764.o
obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o
obj-$(CONFIG_SND_SOC_TAS5720) += snd-soc-tas5720.o
diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c
new file mode 100644
index ..14a193e48dc7
--- /dev/null
+++ b/sound/soc/codecs/tas2764.c
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Driver for the Texas Instruments TAS2764 CODEC
+// Copyright (C) 2020 Texas Instruments Inc.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "tas2764.h"
+
+struct tas2764_priv {
+ struct snd_soc_component *component;
+ struct gpio_desc *reset_gpio;
+ struct gpio_desc *sdz_gpio;
+ struct regmap *regmap;
+ struct device *dev;
+
+ int v_sense_slot;
+ int i_sense_slot;
+};
+
+static void tas2764_reset(struct tas2764_priv *tas2764)
+{
+ if (tas2764->reset_gpio) {
+ gpiod_set_value_cansleep(tas2764->reset_gpio, 0);
+ msleep(20);
+ gpiod_set_value_cansleep(tas2764->reset_gpio, 1);
+ }
+
+ snd_soc_component_write(tas2764->component, TAS2764_SW_RST,
+ TAS2764_RST);
+}
+
+static int tas2764_set_bias_level(struct snd_soc_component *component,
+enum snd_soc_bias_level level)
+{
+ struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
+
+ switch (level) {
+ case SND_SOC_BIAS_ON:
+ snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ TAS2764_PWR_CTRL_ACTIVE);
+ break;
+ case SND_SOC_BIAS_STANDBY:
+ case SND_SOC_BIAS_PREPARE:
+ snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ TAS2764_PWR_CTRL_MUTE);
+ break;
+ case SND_SOC_BIAS_OFF:
+ snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ TAS2764_PWR_CTRL_SHUTDOWN);
+ break;
+
+ default:
+ dev_err(tas2764->dev,
+ "wrong power level setting %d\n", level);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int tas2764_codec_suspend(struct snd_soc_component *component)
+{
+ struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
+ int ret;
+
+
[PATCH v3 1/2] dt-bindings: tas2764: Add the TAS2764 binding doc
Add the binding for the TAS2764 Smart Amplifier.
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/sound/tas2764.yaml| 76 +++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/tas2764.yaml
diff --git a/Documentation/devicetree/bindings/sound/tas2764.yaml
b/Documentation/devicetree/bindings/sound/tas2764.yaml
new file mode 100644
index ..5bf8c76ecda1
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tas2764.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/sound/tas2764.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Texas Instruments TAS2764 Smart PA
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The TAS2764 is a mono, digital input Class-D audio amplifier optimized for
+ efficiently driving high peak power into small loudspeakers.
+ Integrated speaker voltage and current sense provides for
+ real time monitoring of loudspeaker behavior.
+
+properties:
+ compatible:
+enum:
+ - ti,tas2764
+
+ reg:
+maxItems: 1
+description: |
+ I2C address of the device can be between 0x38 to 0x45.
+
+ reset-gpios:
+maxItems: 1
+description: GPIO used to reset the device.
+
+ shutdown-gpios:
+maxItems: 1
+description: GPIO used to control the state of the device.
+
+ interrupts:
+maxItems: 1
+
+ ti,imon-slot-no:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: TDM TX current sense time slot.
+
+ ti,vmon-slot-no:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: TDM TX voltage sense time slot.
+
+ '#sound-dai-cells':
+const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec: codec@38 {
+ compatible = "ti,tas2764";
+ reg = <0x38>;
+ #sound-dai-cells = <1>;
+ interrupt-parent = <>;
+ interrupts = <14>;
+ reset-gpios = < 15 0>;
+ shutdown-gpios = < 15 0>;
+ ti,imon-slot-no = <0>;
+ ti,vmon-slot-no = <2>;
+ };
+ };
+
+...
--
2.28.0.585.ge1cfff676549
Re: [PATCH] lm3697: Rename struct into more appropiate name
Gabriel On 10/7/20 7:21 AM, ultracool...@tutanota.com wrote: The reason I didn't use git send-mail earlier is because Tutanota doesn't supports SMTP and Protonmail requires a paid account for using SMTP/IMAP. However, I made an account creation request for Disroot(which does support SMTP for free), so when/if the account gets created I'll send future patches through there. Oct 6, 2020, 23:26 by ka...@blackhole.sk: Also please note top posting on emails is not preferred. As you will find in the LED domain bottom posts and trimming emails to what is being commented on is preferred. As demonstrated. Dan
[PATCH] power: supply: bq25980: Fix uninitialized wd_reg_val
Fix the uninitialized wd_reg_val if the for..loop was not successful in
finding an appropriate match.
Fixes: 5069185fc18e ("power: supply: bq25980: Add support for the BQ259xx
family")
Reported-by: kernel test robot
Signed-off-by: Dan Murphy
---
drivers/power/supply/bq25980_charger.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/power/supply/bq25980_charger.c
b/drivers/power/supply/bq25980_charger.c
index 3995fb7cf060..24b9c0c8b25d 100644
--- a/drivers/power/supply/bq25980_charger.c
+++ b/drivers/power/supply/bq25980_charger.c
@@ -1099,7 +1099,7 @@ static int bq25980_power_supply_init(struct
bq25980_device *bq,
static int bq25980_hw_init(struct bq25980_device *bq)
{
struct power_supply_battery_info bat_info = { };
- int wd_reg_val;
+ int wd_reg_val = 0;
int ret = 0;
int curr_val;
int volt_val;
--
2.28.0.585.ge1cfff676549
[PATCH v2 2/2] ASoC: tas2764: Add the driver for the TAS2764
Introduce the Texas Instruments TAS2764 amplifier driver
with I/V sense for loud speaker applications.
Signed-off-by: Dan Murphy
---
sound/soc/codecs/Kconfig | 5 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/tas2764.c | 688 +
sound/soc/codecs/tas2764.h | 92 +
4 files changed, 787 insertions(+)
create mode 100644 sound/soc/codecs/tas2764.c
create mode 100644 sound/soc/codecs/tas2764.h
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index a62e0fb467d9..34c6dd04b85a 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -195,6 +195,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_STI_SAS
imply SND_SOC_TAS2552
imply SND_SOC_TAS2562
+ imply SND_SOC_TAS2764
imply SND_SOC_TAS2770
imply SND_SOC_TAS5086
imply SND_SOC_TAS571X
@@ -1303,6 +1304,10 @@ config SND_SOC_TAS2562
tristate "Texas Instruments TAS2562 Mono Audio amplifier"
depends on I2C
+config SND_SOC_TAS2764
+ tristate "Texas Instruments TAS2764 Mono Audio amplifier"
+ depends on I2C
+
config SND_SOC_TAS2770
tristate "Texas Instruments TAS2770 speaker amplifier"
depends on I2C
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 0404bc1ddcfb..11ce98c25d6c 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -304,6 +304,7 @@ snd-soc-simple-amplifier-objs := simple-amplifier.o
snd-soc-tpa6130a2-objs := tpa6130a2.o
snd-soc-tas2552-objs := tas2552.o
snd-soc-tas2562-objs := tas2562.o
+snd-soc-tas2764-objs := tas2764.o
obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o
obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o
@@ -517,6 +518,7 @@ obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
obj-$(CONFIG_SND_SOC_STI_SAS) += snd-soc-sti-sas.o
obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o
obj-$(CONFIG_SND_SOC_TAS2562) += snd-soc-tas2562.o
+obj-$(CONFIG_SND_SOC_TAS2764) += snd-soc-tas2764.o
obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o
obj-$(CONFIG_SND_SOC_TAS5720) += snd-soc-tas5720.o
diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c
new file mode 100644
index ..14a193e48dc7
--- /dev/null
+++ b/sound/soc/codecs/tas2764.c
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Driver for the Texas Instruments TAS2764 CODEC
+// Copyright (C) 2020 Texas Instruments Inc.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "tas2764.h"
+
+struct tas2764_priv {
+ struct snd_soc_component *component;
+ struct gpio_desc *reset_gpio;
+ struct gpio_desc *sdz_gpio;
+ struct regmap *regmap;
+ struct device *dev;
+
+ int v_sense_slot;
+ int i_sense_slot;
+};
+
+static void tas2764_reset(struct tas2764_priv *tas2764)
+{
+ if (tas2764->reset_gpio) {
+ gpiod_set_value_cansleep(tas2764->reset_gpio, 0);
+ msleep(20);
+ gpiod_set_value_cansleep(tas2764->reset_gpio, 1);
+ }
+
+ snd_soc_component_write(tas2764->component, TAS2764_SW_RST,
+ TAS2764_RST);
+}
+
+static int tas2764_set_bias_level(struct snd_soc_component *component,
+enum snd_soc_bias_level level)
+{
+ struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
+
+ switch (level) {
+ case SND_SOC_BIAS_ON:
+ snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ TAS2764_PWR_CTRL_ACTIVE);
+ break;
+ case SND_SOC_BIAS_STANDBY:
+ case SND_SOC_BIAS_PREPARE:
+ snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ TAS2764_PWR_CTRL_MUTE);
+ break;
+ case SND_SOC_BIAS_OFF:
+ snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ TAS2764_PWR_CTRL_SHUTDOWN);
+ break;
+
+ default:
+ dev_err(tas2764->dev,
+ "wrong power level setting %d\n", level);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int tas2764_codec_suspend(struct snd_soc_component *component)
+{
+ struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
+ int ret;
+
+
[PATCH v2 1/2] dt-bindings: tas2764: Add the TAS2764 binding doc
Add the binding for the TAS2764 Smart Amplifier.
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/sound/tas2764.yaml| 74 +++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/tas2764.yaml
diff --git a/Documentation/devicetree/bindings/sound/tas2764.yaml
b/Documentation/devicetree/bindings/sound/tas2764.yaml
new file mode 100644
index ..d2c90c82b13f
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tas2764.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/sound/tas2764.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Texas Instruments TAS2764 Smart PA
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The TAS2764 is a mono, digital input Class-D audio amplifier optimized for
+ efficiently driving high peak power into small loudspeakers.
+ Integrated speaker voltage and current sense provides for
+ real time monitoring of loudspeaker behavior.
+
+properties:
+ compatible:
+enum:
+ - ti,tas2764
+
+ reg:
+maxItems: 1
+description: |
+ I2C address of the device can be between 0x38 to 0x45.
+
+ reset-gpios:
+description: GPIO used to reset the device.
+
+ shutdown-gpios:
+description: GPIO used to control the state of the device.
+
+ interrupts:
+maxItems: 1
+
+ ti,imon-slot-no:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: TDM TX current sense time slot.
+
+ ti,vmon-slot-no:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: TDM TX voltage sense time slot.
+
+ '#sound-dai-cells':
+const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec: codec@38 {
+ compatible = "ti,tas2764";
+ reg = <0x38>;
+ #sound-dai-cells = <1>;
+ interrupt-parent = <>;
+ interrupts = <14>;
+ reset-gpio = < 15 0>;
+ shutdown-gpios = < 15 0>;
+ ti,imon-slot-no = <0>;
+ ti,vmon-slot-no = <2>;
+ };
+ };
+
+...
--
2.28.0.585.ge1cfff676549
Re: [PATCH][next] power: supply: bq25980: remove redundant zero check on ret
Colin
On 10/6/20 12:06 PM, Colin King wrote:
From: Colin Ian King
Currently ret is assigned to zero and the following statement checks
if it is non-zero. This check is redundant and can be removed
Addresses-Coverity: ("Logically dead code")
Fixes: 5069185fc18e ("power: supply: bq25980: Add support for the BQ259xx
family")
Signed-off-by: Colin Ian King
---
drivers/power/supply/bq25980_charger.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/power/supply/bq25980_charger.c
b/drivers/power/supply/bq25980_charger.c
index 3995fb7cf060..f04f9acdb13b 100644
--- a/drivers/power/supply/bq25980_charger.c
+++ b/drivers/power/supply/bq25980_charger.c
@@ -613,9 +613,6 @@ static int bq25980_set_battery_property(struct power_supply
*psy,
struct bq25980_device *bq = power_supply_get_drvdata(psy);
int ret = 0;
- if (ret)
- return ret;
-
switch (psp) {
case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
ret = bq25980_set_const_charge_curr(bq, val->intval);
Thanks for the patch
Acked-by: Dan Murphy
Re: [PATCH] leds: lm3697: Fix out-of-bound access
Marek On 10/6/20 9:41 AM, Marek Behun wrote: Adding Rob to Cc, Rob, could we have your opinion on this? Mine is below. Dan, I looked at the datasheet, I understand this. Nonetheless, device tree should describe how devices are connected to each other. The chip has 3 pins for 3 LED strings. If this controller should be able to support 3 LED strings via 3 outputs, the device tree binding nodes should, in my opinion, describe each pin connected string. The nodes should maybe even be called 'led-string@N' where N is from [0, 1, 2]. The fact that the device is bank controlled and there are only two banks (and it is configurable by which bank each LED string is controlled) is more relevant to the driver, not as much to device tree binding. But yes, I do realize that if we had 3 child nodes, and the driver created 3 LEDs, then changing brithrness on one of the 3 LEDs would change brightness on at least another one, which we do not want. Maybe this driver could parse these 3 `led-string` nodes, each having defined bank via `led-sources`, and then register LED classdevs for each bank that is mentioned. This way the device tree would be more correct, IMO, and the driver would not have the problem mentioned in the paragraph above. Unfortunately we cannot and should not change the ABI now. Using the led-sources as the bank indicator does not conform to the definition of the description of the led-sources in the yaml. The preference was to use the led-sources to define the LED out to the bank. Here is the conversation on how the driver got to where it is. https://lore.kernel.org/patchwork/patch/972337/ Dan
Re: [PATCH] leds: lm3697: Fix out-of-bound access
All On 10/6/20 6:59 AM, ultracool...@tutanota.com wrote: While I do agree with you that having the child nodes be led strings make more sense, would it be possible to have, for example, three strings controlled by the same label? Oct 6, 2020, 07:33 by ka...@blackhole.sk: By the way I just realized that the DT binding in this driver seems incorrect to me. The controller logically supports 3 LED strings, each having configurable control bank. There are two control banks. You can connect the HVLED outputs to either control bank A or B there is no individual control of the LED strings. But the DT binding supports 2 DT nodes, one for each control bank (identified by the `reg` property) and then `led-sources` says which string should be controlled by given bank. But taking in mind that DT should describe how devices are connected to each other, I think the child nodes in the binding should instead describe the 3 supported LED strings... The outputs in this case are virtual outputs which are the banks (A and B). Since the device is bank controlled the actual current sinks are not defined thus making the the banks the actual outputs. This is why the 'reg' property defines the control bank either A or B and the led-sources indicates the strings associated with the control bank. Dan
Re: [PATCH] leds: lm3697: Fix out-of-bound access
Gabriel On 10/5/20 9:38 AM, ultracool...@tutanota.com wrote: I understand. So I should leave it like it was and do the rename in another patch? You should do the fix in one patch and leave the structure name alone. The structure naming if fine and has no benefit and actually will make it more difficult for others to backport future fixes. Unless Pavel finds benefit in accepting the structure rename. Dan
Re: [PATCH] leds: lm3697: Fix out-of-bound access
All On 10/5/20 9:33 AM, Dan Murphy wrote: Marek Sorry not Marek but Gabriel I misread the "To" field Dan
Re: [PATCH] leds: lm3697: Fix out-of-bound access
Marek On 10/5/20 8:57 AM, ultracool...@tutanota.com wrote: I agree with you. Attached patch with changes. Nack to the patch. The subject says it does one thing but you also unnecessarily changed the name of the structure. Renaming the structure does not fix the underlying issue Dan
Re: [PATCH][next] net: phy: dp83869: fix unsigned comparisons against less than zero values
Colin
On 10/2/20 11:54 AM, Colin King wrote:
From: Colin Ian King
Currently the comparisons of u16 integers value and sopass_val with
less than zero for error checking is always false because the values
are unsigned. Fix this by making these variables int. This does not
affect the shift and mask operations performed on these variables
Addresses-Coverity: ("Unsigned compared against zero")
Fixes: 49fc23018ec6 ("net: phy: dp83869: support Wake on LAN")
Signed-off-by: Colin Ian King
---
drivers/net/phy/dp83869.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 0aee5f645b71..cf6dec7b7d8e 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -305,7 +305,7 @@ static int dp83869_set_wol(struct phy_device *phydev,
static void dp83869_get_wol(struct phy_device *phydev,
struct ethtool_wolinfo *wol)
{
- u16 value, sopass_val;
+ int value, sopass_val;
wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
WAKE_MAGICSECURE);
Wonder why this was not reported before as the previous comparison issue
reported by zero day.
Acked-by: Dan Murphy
Re: [PATCH 2/2] ASoC: tas2764: Add the driver for the TAS2764
Mark
Thanks for the review
On 10/1/20 11:25 AM, Mark Brown wrote:
On Wed, Sep 30, 2020 at 11:38:09AM -0500, Dan Murphy wrote:
This all looks good - a few very minor things below but nothing
substantial:
+ default:
+ dev_err(tas2764->dev, "Not supported evevt\n");
+ return -EINVAL;
evevt -> event
OK
+static int tas2764_mute(struct snd_soc_dai *dai, int mute, int direction)
+{
+ struct snd_soc_component *component = dai->component;
+ int ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ mute ? TAS2764_PWR_CTRL_MUTE :
0);
+
+ if (ret < 0)
+ return ret;
This looks weird with the ternery operator and extreme indentation -
could you please at least split the declaration of ret from the call to
make the line length a bit extreme?
I will fix it up
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ case SND_SOC_DAIFMT_DSP_A:
+ tdm_rx_start_slot = 1;
+ break;
+ case SND_SOC_DAIFMT_DSP_B:
+ case SND_SOC_DAIFMT_LEFT_J:
+ tdm_rx_start_slot = 0;
+ break;
I'm not seeing any other handling that distinguishes between the I2S and
DSP modes anywhere - I'm guessing this is because the device is really
only implementing the DSP modes but because it's mono this is compatible
with the I2S modes? It'd be worth having a comment saying this since
while that would be OK not distinguishing between modes properly is a
common error in drivers so it'd help avoid cut'n'paste issues if someone
uses this code as a reference.
Ah it does do LEFT J and Right J so I will fix this
+static int tas2764_register_codec(struct tas2764_priv *tas2764)
+{
+ return devm_snd_soc_register_component(tas2764->dev,
+ _component_driver_tas2764,
+ tas2764_dai_driver,
+ ARRAY_SIZE(tas2764_dai_driver));
+}
This is a bit odd - can we not just inline the component registration
rather than having this function?
I will eliminate this completely and move to i2c_probe
Dan
[PATCH 2/2] ASoC: tas2764: Add the driver for the TAS2764
Introduce the Texas Instruments TAS2764 amplifier driver
with I/V sense for loud speaker applications.
Signed-off-by: Dan Murphy
---
sound/soc/codecs/Kconfig | 5 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/tas2764.c | 683 +
sound/soc/codecs/tas2764.h | 88 +
4 files changed, 778 insertions(+)
create mode 100644 sound/soc/codecs/tas2764.c
create mode 100644 sound/soc/codecs/tas2764.h
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index a62e0fb467d9..34c6dd04b85a 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -195,6 +195,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_STI_SAS
imply SND_SOC_TAS2552
imply SND_SOC_TAS2562
+ imply SND_SOC_TAS2764
imply SND_SOC_TAS2770
imply SND_SOC_TAS5086
imply SND_SOC_TAS571X
@@ -1303,6 +1304,10 @@ config SND_SOC_TAS2562
tristate "Texas Instruments TAS2562 Mono Audio amplifier"
depends on I2C
+config SND_SOC_TAS2764
+ tristate "Texas Instruments TAS2764 Mono Audio amplifier"
+ depends on I2C
+
config SND_SOC_TAS2770
tristate "Texas Instruments TAS2770 speaker amplifier"
depends on I2C
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 0404bc1ddcfb..11ce98c25d6c 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -304,6 +304,7 @@ snd-soc-simple-amplifier-objs := simple-amplifier.o
snd-soc-tpa6130a2-objs := tpa6130a2.o
snd-soc-tas2552-objs := tas2552.o
snd-soc-tas2562-objs := tas2562.o
+snd-soc-tas2764-objs := tas2764.o
obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o
obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o
@@ -517,6 +518,7 @@ obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
obj-$(CONFIG_SND_SOC_STI_SAS) += snd-soc-sti-sas.o
obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o
obj-$(CONFIG_SND_SOC_TAS2562) += snd-soc-tas2562.o
+obj-$(CONFIG_SND_SOC_TAS2764) += snd-soc-tas2764.o
obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o
obj-$(CONFIG_SND_SOC_TAS5720) += snd-soc-tas5720.o
diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c
new file mode 100644
index ..5c34ed4809f9
--- /dev/null
+++ b/sound/soc/codecs/tas2764.c
@@ -0,0 +1,683 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Driver for the Texas Instruments TAS2764 CODEC
+// Copyright (C) 2020 Texas Instruments Inc.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "tas2764.h"
+
+struct tas2764_priv {
+ struct snd_soc_component *component;
+ struct gpio_desc *reset_gpio;
+ struct gpio_desc *sdz_gpio;
+ struct regmap *regmap;
+ struct device *dev;
+
+ int v_sense_slot;
+ int i_sense_slot;
+};
+
+static void tas2764_reset(struct tas2764_priv *tas2764)
+{
+ if (tas2764->reset_gpio) {
+ gpiod_set_value_cansleep(tas2764->reset_gpio, 0);
+ msleep(20);
+ gpiod_set_value_cansleep(tas2764->reset_gpio, 1);
+ }
+
+ snd_soc_component_write(tas2764->component, TAS2764_SW_RST,
+ TAS2764_RST);
+}
+
+static int tas2764_set_bias_level(struct snd_soc_component *component,
+enum snd_soc_bias_level level)
+{
+ struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
+
+ switch (level) {
+ case SND_SOC_BIAS_ON:
+ snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ TAS2764_PWR_CTRL_ACTIVE);
+ break;
+ case SND_SOC_BIAS_STANDBY:
+ case SND_SOC_BIAS_PREPARE:
+ snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ TAS2764_PWR_CTRL_MUTE);
+ break;
+ case SND_SOC_BIAS_OFF:
+ snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
+ TAS2764_PWR_CTRL_MASK,
+ TAS2764_PWR_CTRL_SHUTDOWN);
+ break;
+
+ default:
+ dev_err(tas2764->dev,
+ "wrong power level setting %d\n", level);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int tas2764_codec_suspend(struct snd_soc_component *component)
+{
+ struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
+ int ret;
+
+
[PATCH 1/2] dt-bindings: tas2764: Add the TAS2764 binding doc
Add the binding for the TAS2764 Smart Amplifier.
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/sound/tas2764.yaml| 74 +++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/tas2764.yaml
diff --git a/Documentation/devicetree/bindings/sound/tas2764.yaml
b/Documentation/devicetree/bindings/sound/tas2764.yaml
new file mode 100644
index ..4e758ff81003
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tas2764.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/sound/tas2764.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Texas Instruments TAS2764 Smart PA
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The TAS2764 is a mono, digital input Class-D audio amplifier optimized for
+ efficiently driving high peak power into small loudspeakers.
+ Integrated speaker voltage and current sense provides for
+ real time monitoring of loudspeaker behavior.
+
+properties:
+ compatible:
+enum:
+ - ti,tas2764
+
+ reg:
+maxItems: 1
+description: |
+ I2C address of the device can be between 0x38 to 0x45.
+
+ reset-gpio:
+description: GPIO used to reset the device.
+
+ shutdown-gpios:
+description: GPIO used to control the state of the device.
+
+ interrupts:
+maxItems: 1
+
+ ti,imon-slot-no:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: TDM TX current sense time slot.
+
+ ti,vmon-slot-no:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: TDM TX voltage sense time slot.
+
+ '#sound-dai-cells':
+const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec: codec@38 {
+ compatible = "ti,tas2764";
+ reg = <0x38>;
+ #sound-dai-cells = <1>;
+ interrupt-parent = <>;
+ interrupts = <14>;
+ reset-gpio = < 15 0>;
+ shutdown-gpios = < 15 0>;
+ ti,imon-slot-no = <0>;
+ ti,vmon-slot-no = <2>;
+ };
+ };
+
+...
--
2.28.0.585.ge1cfff676549
[RESEND PATCH net-next v5 2/2] net: phy: dp83869: Add speed optimization feature
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index de68e56faf3d..0aee5f645b71 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
@@ -20,6 +21,7 @@
#define MII_DP83869_PHYCTRL0x10
#define MII_DP83869_MICR 0x12
#define MII_DP83869_ISR0x13
+#define DP83869_CFG2 0x14
#define DP83869_CTRL 0x1f
#define DP83869_CFG4 0x1e
@@ -120,6 +122,18 @@
#define DP83869_WOL_SEC_EN BIT(5)
#define DP83869_WOL_ENH_MACBIT(7)
+/* CFG2 bits */
+#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
+#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
+#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
+#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
+#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
+#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
+#define DP83869_DOWNSHIFT_1_COUNT 1
+#define DP83869_DOWNSHIFT_2_COUNT 2
+#define DP83869_DOWNSHIFT_4_COUNT 4
+#define DP83869_DOWNSHIFT_8_COUNT 8
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -350,6 +364,99 @@ static void dp83869_get_wol(struct phy_device *phydev,
wol->wolopts = 0;
}
+static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val, cnt, enable, count;
+
+ val = phy_read(phydev, DP83869_CFG2);
+ if (val < 0)
+ return val;
+
+ enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
+ cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_1_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_2_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_4_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_8_COUNT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -EINVAL;
+
+ if (!cnt)
+ return phy_clear_bits(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT:
+ count = DP83869_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT:
+ count = DP83869_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT:
+ count = DP83869_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT:
+ count = DP83869_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
+ }
+
+ val = DP83869_DOWNSHIFT_EN;
+ val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
+
+ return phy_modify(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
+ val);
+}
+
+static int dp83869_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int dp83869_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static int dp83869_config_port_mirroring(struct phy_device *phydev)
{
struct dp83869_private *dp83869
[RESEND PATCH net-next v5 1/2] net: phy: dp83869: support Wake on LAN
This adds WoL support on TI DP83869 for magic, magic secure, unicast and
broadcast.
Signed-off-by: Dan Murphy
---
v5 - Fixed 0-day warning for u16, removed defconfig
drivers/net/phy/dp83869.c | 176 ++
1 file changed, 176 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 81899bc99add..de68e56faf3d 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -27,6 +28,13 @@
#define DP83869_RGMIICTL 0x0032
#define DP83869_STRAP_STS1 0x006e
#define DP83869_RGMIIDCTL 0x0086
+#define DP83869_RXFCFG 0x0134
+#define DP83869_RXFPMD10x0136
+#define DP83869_RXFPMD20x0137
+#define DP83869_RXFPMD30x0138
+#define DP83869_RXFSOP10x0139
+#define DP83869_RXFSOP20x013A
+#define DP83869_RXFSOP30x013B
#define DP83869_IO_MUX_CFG 0x0170
#define DP83869_OP_MODE0x01df
#define DP83869_FX_CTRL0x0c00
@@ -104,6 +112,14 @@
#define DP83869_OP_MODE_MIIBIT(5)
#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
+/* RXFCFG bits*/
+#define DP83869_WOL_MAGIC_EN BIT(0)
+#define DP83869_WOL_PATTERN_EN BIT(1)
+#define DP83869_WOL_BCAST_EN BIT(2)
+#define DP83869_WOL_UCAST_EN BIT(4)
+#define DP83869_WOL_SEC_EN BIT(5)
+#define DP83869_WOL_ENH_MACBIT(7)
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -177,6 +193,163 @@ static int dp83869_config_intr(struct phy_device *phydev)
return phy_write(phydev, MII_DP83869_MICR, micr_status);
}
+static int dp83869_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *ndev = phydev->attached_dev;
+ int val_rxcfg, val_micr;
+ u8 *mac;
+ int ret;
+
+ val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
+ if (val_rxcfg < 0)
+ return val_rxcfg;
+
+ val_micr = phy_read(phydev, MII_DP83869_MICR);
+ if (val_micr < 0)
+ return val_micr;
+
+ if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
+ WAKE_BCAST)) {
+ val_rxcfg |= DP83869_WOL_ENH_MAC;
+ val_micr |= MII_DP83869_MICR_WOL_INT_EN;
+
+ if (wol->wolopts & WAKE_MAGIC ||
+ wol->wolopts & WAKE_MAGICSECURE) {
+ mac = (u8 *)ndev->dev_addr;
+
+ if (!is_valid_ether_addr(mac))
+ return -EINVAL;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD1,
+ mac[1] << 8 | mac[0]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD2,
+ mac[3] << 8 | mac[2]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD3,
+ mac[5] << 8 | mac[4]);
+ if (ret)
+ return ret;
+
+ val_rxcfg |= DP83869_WOL_MAGIC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
+ }
+
+ if (wol->wolopts & WAKE_MAGICSECURE) {
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP1,
+ (wol->sopass[1] << 8) |
wol->sopass[0]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP2,
+ (wol->sopass[3] << 8) |
wol->sopass[2]);
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP3,
+ (wol->sopass[5] << 8) |
wol->sopass[4]);
+ if (ret)
+ return ret;
+
+ val_rxcfg |= DP83869_WOL_SEC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_SEC_EN;
+ }
+
+ if (wol-
[RESEND PATCH net-next v5 0/2] DP83869 WoL and Speed optimization
Hello Add the WoL and Speed Optimization (aka downshift) support for the DP83869 Ethernet PHY. Dan Dan Murphy (2): net: phy: dp83869: support Wake on LAN net: phy: dp83869: Add speed optimization feature drivers/net/phy/dp83869.c | 292 ++ 1 file changed, 292 insertions(+) -- 2.28.0.585.ge1cfff676549
Re: [PATCH net-next v5 1/2] net: phy: dp83869: support Wake on LAN
Hello On 9/28/20 9:46 AM, Dan Murphy wrote: This adds WoL support on TI DP83869 for magic, magic secure, unicast and broadcast. Signed-off-by: Dan Murphy --- v5 - Fixed 0-day warning for u16 arch/arm/configs/ti_sdk_omap2_debug_defconfig | 2335 + I have to repost this patch as this got added when updating the patches when I was testing. Dan
[PATCH net-next v5 1/2] net: phy: dp83869: support Wake on LAN
This adds WoL support on TI DP83869 for magic, magic secure, unicast and broadcast. Signed-off-by: Dan Murphy --- v5 - Fixed 0-day warning for u16 arch/arm/configs/ti_sdk_omap2_debug_defconfig | 2335 + drivers/net/phy/dp83869.c | 176 ++ 2 files changed, 2511 insertions(+) create mode 100644 arch/arm/configs/ti_sdk_omap2_debug_defconfig diff --git a/arch/arm/configs/ti_sdk_omap2_debug_defconfig b/arch/arm/configs/ti_sdk_omap2_debug_defconfig new file mode 100644 index ..e340e0cdc7e3 --- /dev/null +++ b/arch/arm/configs/ti_sdk_omap2_debug_defconfig @@ -0,0 +1,2335 @@ +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_PERF_EVENTS=y +CONFIG_MACH_ARTPEC6=y +CONFIG_MACH_ASPEED_G6=y +CONFIG_SOC_SAMA5D2=y +CONFIG_SOC_SAMA5D3=y +CONFIG_SOC_SAMA5D4=y +CONFIG_ARCH_BCM_HR2=y +CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCM_63XX=y +CONFIG_MACH_BERLIN_BG2=y +CONFIG_MACH_BERLIN_BG2CD=y +CONFIG_MACH_BERLIN_BG2Q=y +CONFIG_SOC_IMX50=y +CONFIG_SOC_IMX51=y +CONFIG_SOC_IMX53=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6UL=y +CONFIG_SOC_LS1021A=y +CONFIG_SOC_IMX7D=y +CONFIG_SOC_VF610=y +CONFIG_ARCH_MILBEAUT_M10V=y +CONFIG_ARCH_MMP=y +CONFIG_MACH_MMP2_DT=y +CONFIG_MACH_MMP3_DT=y +CONFIG_MACH_ARMADA_370=y +CONFIG_MACH_ARMADA_375=y +CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_39X=y +CONFIG_MACH_ARMADA_XP=y +CONFIG_MACH_DOVE=y +CONFIG_MACH_SPEAR1310=y +CONFIG_MACH_SPEAR1340=y +CONFIG_SMP=y +CONFIG_EFI=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y +CONFIG_ARM_ZYNQ_CPUIDLE=y +CONFIG_ARM_EXYNOS_CPUIDLE=y +CONFIG_ARM_TEGRA_CPUIDLE=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_TRUSTED_FOUNDATIONS=y +CONFIG_BCM47XX_NVRAM=y +CONFIG_BCM47XX_SPROM=y +CONFIG_EFI_VARS=m +CONFIG_EFI_CAPSULE_LOADER=m +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_CE=m +CONFIG_CRYPTO_SHA2_ARM_CE=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_CRC32_ARM_CE=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_PARTITION_ADVANCED=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_ESP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NET_DSA=m +CONFIG_CAN_AT91=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_SUN4I=y +CONFIG_CAN_XILINXCAN=y +CONFIG_CAN_RCAR=m +CONFIG_CAN_MCP251X=y +CONFIG_BT=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=y +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_MVEBU=y +CONFIG_PCI_TEGRA=y +CONFIG_PCI_RCAR_GEN2=y +CONFIG_PCIE_RCAR=y +CONFIG_OMAP_OCP2SCP=y +CONFIG_SIMPLE_PM_BUS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_NAND_MARVELL=y +CONFIG_MTD_NAND_BRCMNAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_VF610_NFC=y +CONFIG_MTD_NAND_STM32_FMC2=y +CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_ASPEED_SMC=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_VIRTIO_BLK=y +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +CONFIG_ATMEL_TCLIB=y +CONFIG_ICS932S401=y +CONFIG_ATMEL_SSC=m +CONFIG_QCOM_COINCELL=m +CONFIG_APDS9802ALS=y +CONFIG_ISL29003=y +CONFIG_BLK_DEV_SR=y +CONFIG_AHCI_BRCM=y +CONFIG_AHCI_DM816=y +CONFIG_AHCI_ST=y +CONFIG_AHCI_IMX=y +CONFIG_AHCI_SUNXI=y +CONFIG_AHCI_TEGRA=y +CONFIG_SATA_HIGHBANK=y +CONFIG_SATA_MV=y +CONFIG_SATA_RCAR=y +CONFIG_NETDEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_SUN4I_EMAC=y +CONFIG_BGMAC_BCMA=y +CONFIG_MACB=y +CONFIG_NET_CALXEDA_XGMAC=y +CONFIG_FTGMAC100=m +CONFIG_GIANFAR=y +CONFIG_HIX5HD2_GMAC=y +CONFIG_MV643XX_ETH=y +CONFIG_MVNETA=y +CONFIG_PXA168_ETH=m +CONFIG_KS8851=y +CONFIG_R8169=y +CONFIG_SH_ETH=y +CONFIG_SMSC911X=y +CONFIG_SNI_AVE=y +CONFIG_STMMAC_ETH=y +CONFIG_DWMAC_DWC_QOS_ETH=y +CONFIG_XILINX_EMACLITE=y +CONFIG_AT803X_PHY=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_SMSC75XX=y +CONFIG_BRCMFMAC=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_RT2X00=m +CONFIG_RT2800USB=m +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_TEGRA=y +CONFIG_KEYBOARD_PXA27x=m +CONFIG_KEYBOARD_SAMSUNG=m +CONFIG_KEYBOARD_ST_KEYSCAN=y +CONFIG_KEYBOARD_SPEAR=y +CONFIG_KEYBOARD_CROS_EC=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=y +CONFIG_TOUCHSCREEN_ADC=m
[PATCH net-next v5 2/2] net: phy: dp83869: Add speed optimization feature
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index de68e56faf3d..0aee5f645b71 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
@@ -20,6 +21,7 @@
#define MII_DP83869_PHYCTRL0x10
#define MII_DP83869_MICR 0x12
#define MII_DP83869_ISR0x13
+#define DP83869_CFG2 0x14
#define DP83869_CTRL 0x1f
#define DP83869_CFG4 0x1e
@@ -120,6 +122,18 @@
#define DP83869_WOL_SEC_EN BIT(5)
#define DP83869_WOL_ENH_MACBIT(7)
+/* CFG2 bits */
+#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
+#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
+#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
+#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
+#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
+#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
+#define DP83869_DOWNSHIFT_1_COUNT 1
+#define DP83869_DOWNSHIFT_2_COUNT 2
+#define DP83869_DOWNSHIFT_4_COUNT 4
+#define DP83869_DOWNSHIFT_8_COUNT 8
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -350,6 +364,99 @@ static void dp83869_get_wol(struct phy_device *phydev,
wol->wolopts = 0;
}
+static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val, cnt, enable, count;
+
+ val = phy_read(phydev, DP83869_CFG2);
+ if (val < 0)
+ return val;
+
+ enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
+ cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_1_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_2_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_4_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_8_COUNT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -EINVAL;
+
+ if (!cnt)
+ return phy_clear_bits(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT:
+ count = DP83869_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT:
+ count = DP83869_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT:
+ count = DP83869_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT:
+ count = DP83869_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
+ }
+
+ val = DP83869_DOWNSHIFT_EN;
+ val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
+
+ return phy_modify(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
+ val);
+}
+
+static int dp83869_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int dp83869_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static int dp83869_config_port_mirroring(struct phy_device *phydev)
{
struct dp83869_private *dp83869
[PATCH net-next v5 0/2] DP83869 WoL and Speed optimization
Hello Add the WoL and Speed Optimization (aka downshift) support for the DP83869 Ethernet PHY. Dan Dan Murphy (2): net: phy: dp83869: support Wake on LAN net: phy: dp83869: Add speed optimization feature arch/arm/configs/ti_sdk_omap2_debug_defconfig | 2335 + drivers/net/phy/dp83869.c | 292 +++ 2 files changed, 2627 insertions(+) create mode 100644 arch/arm/configs/ti_sdk_omap2_debug_defconfig -- 2.28.0.585.ge1cfff676549
[PATCH net-next v4 1/2] net: phy: dp83869: support Wake on LAN
This adds WoL support on TI DP83869 for magic, magic secure, unicast and
broadcast.
Signed-off-by: Dan Murphy
---
v4 - Added checking error on phy_read
drivers/net/phy/dp83869.c | 176 ++
1 file changed, 176 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 81899bc99add..975b64b4b6c4 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -27,6 +28,13 @@
#define DP83869_RGMIICTL 0x0032
#define DP83869_STRAP_STS1 0x006e
#define DP83869_RGMIIDCTL 0x0086
+#define DP83869_RXFCFG 0x0134
+#define DP83869_RXFPMD10x0136
+#define DP83869_RXFPMD20x0137
+#define DP83869_RXFPMD30x0138
+#define DP83869_RXFSOP10x0139
+#define DP83869_RXFSOP20x013A
+#define DP83869_RXFSOP30x013B
#define DP83869_IO_MUX_CFG 0x0170
#define DP83869_OP_MODE0x01df
#define DP83869_FX_CTRL0x0c00
@@ -104,6 +112,14 @@
#define DP83869_OP_MODE_MIIBIT(5)
#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
+/* RXFCFG bits*/
+#define DP83869_WOL_MAGIC_EN BIT(0)
+#define DP83869_WOL_PATTERN_EN BIT(1)
+#define DP83869_WOL_BCAST_EN BIT(2)
+#define DP83869_WOL_UCAST_EN BIT(4)
+#define DP83869_WOL_SEC_EN BIT(5)
+#define DP83869_WOL_ENH_MACBIT(7)
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -177,6 +193,163 @@ static int dp83869_config_intr(struct phy_device *phydev)
return phy_write(phydev, MII_DP83869_MICR, micr_status);
}
+static int dp83869_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *ndev = phydev->attached_dev;
+ u16 val_rxcfg, val_micr;
+ u8 *mac;
+ int ret;
+
+ val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
+ if (val_rxcfg < 0)
+ return val_rxcfg;
+
+ val_micr = phy_read(phydev, MII_DP83869_MICR);
+ if (val_micr < 0)
+ return val_micr;
+
+ if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
+ WAKE_BCAST)) {
+ val_rxcfg |= DP83869_WOL_ENH_MAC;
+ val_micr |= MII_DP83869_MICR_WOL_INT_EN;
+
+ if (wol->wolopts & WAKE_MAGIC ||
+ wol->wolopts & WAKE_MAGICSECURE) {
+ mac = (u8 *)ndev->dev_addr;
+
+ if (!is_valid_ether_addr(mac))
+ return -EINVAL;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD1,
+ mac[1] << 8 | mac[0]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD2,
+ mac[3] << 8 | mac[2]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD3,
+ mac[5] << 8 | mac[4]);
+ if (ret)
+ return ret;
+
+ val_rxcfg |= DP83869_WOL_MAGIC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
+ }
+
+ if (wol->wolopts & WAKE_MAGICSECURE) {
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP1,
+ (wol->sopass[1] << 8) |
wol->sopass[0]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP2,
+ (wol->sopass[3] << 8) |
wol->sopass[2]);
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP3,
+ (wol->sopass[5] << 8) |
wol->sopass[4]);
+ if (ret)
+ return ret;
+
+ val_rxcfg |= DP83869_WOL_SEC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_SEC_EN;
+ }
+
+ if (wol-
[PATCH net-next v4 2/2] net: phy: dp83869: Add speed optimization feature
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.
Signed-off-by: Dan Murphy
---
v4 - Fixed error from E2BIG to EINVAL
drivers/net/phy/dp83869.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 975b64b4b6c4..8d4440326432 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
@@ -20,6 +21,7 @@
#define MII_DP83869_PHYCTRL0x10
#define MII_DP83869_MICR 0x12
#define MII_DP83869_ISR0x13
+#define DP83869_CFG2 0x14
#define DP83869_CTRL 0x1f
#define DP83869_CFG4 0x1e
@@ -120,6 +122,18 @@
#define DP83869_WOL_SEC_EN BIT(5)
#define DP83869_WOL_ENH_MACBIT(7)
+/* CFG2 bits */
+#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
+#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
+#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
+#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
+#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
+#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
+#define DP83869_DOWNSHIFT_1_COUNT 1
+#define DP83869_DOWNSHIFT_2_COUNT 2
+#define DP83869_DOWNSHIFT_4_COUNT 4
+#define DP83869_DOWNSHIFT_8_COUNT 8
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -350,6 +364,99 @@ static void dp83869_get_wol(struct phy_device *phydev,
wol->wolopts = 0;
}
+static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val, cnt, enable, count;
+
+ val = phy_read(phydev, DP83869_CFG2);
+ if (val < 0)
+ return val;
+
+ enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
+ cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_1_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_2_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_4_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_8_COUNT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -EINVAL;
+
+ if (!cnt)
+ return phy_clear_bits(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT:
+ count = DP83869_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT:
+ count = DP83869_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT:
+ count = DP83869_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT:
+ count = DP83869_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
+ }
+
+ val = DP83869_DOWNSHIFT_EN;
+ val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
+
+ return phy_modify(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
+ val);
+}
+
+static int dp83869_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int dp83869_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static int dp83869_config_port_mirroring(struct phy_device *phydev)
{
[PATCH net-next v4 0/2] DP83869 WoL and Speed optimization
Hello Add the WoL and Speed Optimization (aka downshift) support for the DP83869 Ethernet PHY. Dan Dan Murphy (2): net: phy: dp83869: support Wake on LAN net: phy: dp83869: Add speed optimization feature drivers/net/phy/dp83869.c | 292 ++ 1 file changed, 292 insertions(+) -- 2.28.0
[PATCH] dt-bindings: tas2770: Mark ti,asi-format to deprecated
Mark the property ti,asi-format to deprecated as it is no longer supported. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/sound/tas2770.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sound/tas2770.yaml b/Documentation/devicetree/bindings/sound/tas2770.yaml index 9fdf614add55..07e7f9951d2e 100644 --- a/Documentation/devicetree/bindings/sound/tas2770.yaml +++ b/Documentation/devicetree/bindings/sound/tas2770.yaml @@ -44,6 +44,7 @@ properties: description: TDM TX voltage sense time slot. ti,asi-format: +deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Sets TDM RX capture edge. enum: -- 2.28.0
Re: [RESEND PATCH can-next 1/2] can: tcan4x5x: Rename parse_config function
Mark and Wolfgang
On 4/28/20 2:48 PM, Dan Murphy wrote:
Marc
On 2/27/20 12:38 PM, Dan Murphy wrote:
Rename the tcan4x5x_parse_config function to tcan4x5x_get_gpios since
the function retrieves the gpio configurations from the firmware.
Signed-off-by: Dan Murphy
---
drivers/net/can/m_can/tcan4x5x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/m_can/tcan4x5x.c
b/drivers/net/can/m_can/tcan4x5x.c
index 9821babef55e..37d53ecc560b 100644
--- a/drivers/net/can/m_can/tcan4x5x.c
+++ b/drivers/net/can/m_can/tcan4x5x.c
@@ -381,7 +381,7 @@ static int tcan4x5x_disable_state(struct
m_can_classdev *cdev)
TCAN4X5X_DISABLE_INH_MSK, 0x01);
}
-static int tcan4x5x_parse_config(struct m_can_classdev *cdev)
+static int tcan4x5x_get_gpios(struct m_can_classdev *cdev)
{
struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
int ret;
@@ -507,7 +507,7 @@ static int tcan4x5x_can_probe(struct spi_device
*spi)
if (ret)
return ret;
- ret = tcan4x5x_parse_config(mcan_class);
+ ret = tcan4x5x_get_gpios(mcan_class);
if (ret)
goto out_power;
I noticed this series never was reviewed and applied. They are still
applicable and were requested changes.
Did you need me to combine all the patches on a m_can-next branch and
submit a PR after test?
There are quite a few patches out there and they all seem relevant.
Dan
Dan
Re: [PATCH v2] MAINTAINERS: add Dan Murphy as TP LP8xxx drivers maintainer
Hello On 9/22/20 10:28 AM, Krzysztof Kozlowski wrote: Milo Kim's email in TI bounces with permanent error (550: Invalid recipient). Last email from him on LKML was in 2017. Move Milo Kim to credits and add Dan Murphy from TI to look after: - TI LP855x backlight driver, - TI LP8727 charger driver, - TI LP8788 MFD (ADC, LEDs, charger and regulator) drivers. Cc: Dan Murphy Signed-off-by: Krzysztof Kozlowski Acked-by: Dan Murphy
Re: [PATCH 4/6] dt-bindings: tas2770: Remove ti,asi-format property
Mark On 9/23/20 10:51 AM, Mark Brown wrote: On Wed, Sep 23, 2020 at 08:25:58AM -0500, Dan Murphy wrote: Remove the property ti,asi-format as the driver only reads this property and performs no action against it. We should probably leave the property as documented and move it to deprecated rather than delete the documentation entirely. I mulled this over to just deprecate the property and I know removing these ABIs are not highly accepted. But the support code for it was incomplete and if a user had it populated in the DT and we removed the support then there will be no functional change. This property was supposed to set the RX edge SBCLK detection but this is done based on the dai format. So removing the property will have no affect on the users. Dan
Re: [PATCH] leds: lp50xx: Fix an error handling path in 'lp50xx_probe_dt()'
Christophe
On 9/22/20 4:05 PM, Christophe JAILLET wrote:
In case of memory allocation failure, we must release some resources as
done in all other error handling paths of the function.
'goto child_out' instead of a direct return so that 'fwnode_handle_put()'
is called when we break out of a 'device_for_each_child_node' loop.
Fixes: 242b81170fb8 ("leds: lp50xx: Add the LP50XX family of the RGB LED
driver")
Signed-off-by: Christophe JAILLET
---
drivers/leds/leds-lp50xx.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/leds/leds-lp50xx.c b/drivers/leds/leds-lp50xx.c
index 47144a37cb94..8178782f2a8a 100644
--- a/drivers/leds/leds-lp50xx.c
+++ b/drivers/leds/leds-lp50xx.c
@@ -487,8 +487,10 @@ static int lp50xx_probe_dt(struct lp50xx *priv)
*/
mc_led_info = devm_kcalloc(priv->dev, LP50XX_LEDS_PER_MODULE,
sizeof(*mc_led_info), GFP_KERNEL);
- if (!mc_led_info)
- return -ENOMEM;
+ if (!mc_led_info) {
+ ret = -ENOMEM;
+ goto child_out;
+ }
fwnode_for_each_child_node(child, led_node) {
ret = fwnode_property_read_u32(led_node, "color",
Thanks for the patch
Acked-by: Dan Murphy
[PATCH 6/6] ASoC: tas2770: Remove unused variables
Remove unused variables in the private struct and the code as these
variables are initially set and then there is no additional code
utilizing these variables.
Signed-off-by: Dan Murphy
---
sound/soc/codecs/tas2770.c | 11 ---
sound/soc/codecs/tas2770.h | 8 ++--
2 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/sound/soc/codecs/tas2770.c b/sound/soc/codecs/tas2770.c
index c7a6f7e8200c..a91a0a31e74d 100644
--- a/sound/soc/codecs/tas2770.c
+++ b/sound/soc/codecs/tas2770.c
@@ -249,8 +249,6 @@ static int tas2770_set_bitwidth(struct tas2770_priv
*tas2770, int bitwidth)
if (ret < 0)
return ret;
- tas2770->channel_size = bitwidth;
-
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG5,
TAS2770_TDM_CFG_REG5_VSNS_MASK |
TAS2770_TDM_CFG_REG5_50_MASK,
@@ -312,7 +310,6 @@ static int tas2770_set_samplerate(struct tas2770_priv
*tas2770, int samplerate)
if (ret < 0)
return ret;
- tas2770->sampling_rate = samplerate;
return 0;
}
@@ -400,8 +397,6 @@ static int tas2770_set_dai_tdm_slot(struct snd_soc_dai *dai,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
- struct tas2770_priv *tas2770 =
- snd_soc_component_get_drvdata(component);
int left_slot, right_slot;
int ret;
@@ -466,7 +461,6 @@ static int tas2770_set_dai_tdm_slot(struct snd_soc_dai *dai,
if (ret < 0)
return ret;
- tas2770->slot_width = slot_width;
return 0;
}
@@ -688,8 +682,6 @@ static int tas2770_i2c_probe(struct i2c_client *client,
i2c_set_clientdata(client, tas2770);
dev_set_drvdata(>dev, tas2770);
- tas2770->power_state = TAS2770_POWER_SHUTDOWN;
-
tas2770->regmap = devm_regmap_init_i2c(client, _i2c_regmap);
if (IS_ERR(tas2770->regmap)) {
result = PTR_ERR(tas2770->regmap);
@@ -716,9 +708,6 @@ static int tas2770_i2c_probe(struct i2c_client *client,
}
}
- tas2770->channel_size = 0;
- tas2770->slot_width = 0;
-
result = tas2770_register_codec(tas2770);
if (result)
dev_err(tas2770->dev, "Register codec failed.\n");
diff --git a/sound/soc/codecs/tas2770.h b/sound/soc/codecs/tas2770.h
index 856a7c5cff5a..d15bcc55 100644
--- a/sound/soc/codecs/tas2770.h
+++ b/sound/soc/codecs/tas2770.h
@@ -128,15 +128,11 @@
#define ERROR_CLASSD_PWRBIT(5)
struct tas2770_priv {
- struct device *dev;
- struct regmap *regmap;
struct snd_soc_component *component;
- int power_state;
struct gpio_desc *reset_gpio;
struct gpio_desc *sdz_gpio;
- int sampling_rate;
- int channel_size;
- int slot_width;
+ struct regmap *regmap;
+ struct device *dev;
int v_sense_slot;
int i_sense_slot;
};
--
2.28.0
[PATCH 3/6] ASoC: tas2770: Set regcache when shutting down and waking device
Set the regcache to cache data and mark cache as dirty when the device
is shutdown when suspend is called. When the device is woken up then
sync the cache and set to not caching the data.
Signed-off-by: Dan Murphy
---
sound/soc/codecs/tas2770.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/tas2770.c b/sound/soc/codecs/tas2770.c
index 9f7363927c50..c42e653cd653 100644
--- a/sound/soc/codecs/tas2770.c
+++ b/sound/soc/codecs/tas2770.c
@@ -82,14 +82,20 @@ static int tas2770_codec_suspend(struct snd_soc_component
*component)
struct tas2770_priv *tas2770 = snd_soc_component_get_drvdata(component);
int ret = 0;
+ regcache_cache_only(tas2770->regmap, true);
+ regcache_mark_dirty(tas2770->regmap);
+
if (tas2770->sdz_gpio) {
gpiod_set_value_cansleep(tas2770->sdz_gpio, 0);
} else {
ret = snd_soc_component_update_bits(component, TAS2770_PWR_CTRL,
TAS2770_PWR_CTRL_MASK,
TAS2770_PWR_CTRL_SHUTDOWN);
- if (ret < 0)
+ if (ret < 0) {
+ regcache_cache_only(tas2770->regmap, false);
+ regcache_sync(tas2770->regmap);
return ret;
+ }
ret = 0;
}
@@ -110,11 +116,11 @@ static int tas2770_codec_resume(struct snd_soc_component
*component)
TAS2770_PWR_CTRL_ACTIVE);
if (ret < 0)
return ret;
-
- ret = 0;
}
- return ret;
+ regcache_cache_only(tas2770->regmap, false);
+
+ return regcache_sync(tas2770->regmap);
}
#else
#define tas2770_codec_suspend NULL
--
2.28.0
[PATCH 1/6] dt-bindings: tas2770: Add shutdown gpio property
Add the shutdown-gpios property to the yaml to define the GPIO that can be used to place the device in shutdown mode or wake the device up. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/sound/tas2770.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/tas2770.yaml b/Documentation/devicetree/bindings/sound/tas2770.yaml index bb26d081c9fa..9fdf614add55 100644 --- a/Documentation/devicetree/bindings/sound/tas2770.yaml +++ b/Documentation/devicetree/bindings/sound/tas2770.yaml @@ -29,6 +29,9 @@ properties: reset-gpio: description: GPIO used to reset the device. + shutdown-gpios: +description: GPIO used to control the state of the device. + interrupts: maxItems: 1 @@ -69,6 +72,7 @@ examples: interrupt-parent = <>; interrupts = <14>; reset-gpio = < 15 0>; + shutdown-gpios = < 14 0>; ti,imon-slot-no = <0>; ti,vmon-slot-no = <2>; }; -- 2.28.0
[PATCH 5/6] ASoC: tas2770: Remove ti,asi-format code
Remove the code to support the asi-format binding property. The code
does nothing except read the property and set a variable. No additional
action is taken except to reset the variable. The property is supposed
to set the rising or falling RX edge detection of the SBCLK but this
edge detection is done by checking the DAI_FMT_INV_MASK.
Signed-off-by: Dan Murphy
---
sound/soc/codecs/tas2770.c | 11 ---
sound/soc/codecs/tas2770.h | 1 -
2 files changed, 12 deletions(-)
diff --git a/sound/soc/codecs/tas2770.c b/sound/soc/codecs/tas2770.c
index c42e653cd653..c7a6f7e8200c 100644
--- a/sound/soc/codecs/tas2770.c
+++ b/sound/soc/codecs/tas2770.c
@@ -391,8 +391,6 @@ static int tas2770_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
if (ret < 0)
return ret;
- tas2770->asi_format = fmt;
-
return 0;
}
@@ -646,15 +644,6 @@ static int tas2770_parse_dt(struct device *dev, struct
tas2770_priv *tas2770)
{
int rc = 0;
- rc = fwnode_property_read_u32(dev->fwnode, "ti,asi-format",
- >asi_format);
- if (rc) {
- dev_info(tas2770->dev, "Property %s is missing setting default
slot\n",
-"ti,asi-format");
-
- tas2770->asi_format = 0;
- }
-
rc = fwnode_property_read_u32(dev->fwnode, "ti,imon-slot-no",
>i_sense_slot);
if (rc) {
diff --git a/sound/soc/codecs/tas2770.h b/sound/soc/codecs/tas2770.h
index b3fc4a487033..856a7c5cff5a 100644
--- a/sound/soc/codecs/tas2770.h
+++ b/sound/soc/codecs/tas2770.h
@@ -132,7 +132,6 @@ struct tas2770_priv {
struct regmap *regmap;
struct snd_soc_component *component;
int power_state;
- int asi_format;
struct gpio_desc *reset_gpio;
struct gpio_desc *sdz_gpio;
int sampling_rate;
--
2.28.0
[PATCH 2/6] ASoC: tas2770: Add shutdown capability via a GPIO
Add the hardware shutdown mechanism to shutdown and wake up the device
via a GPIO.
Signed-off-by: Dan Murphy
---
sound/soc/codecs/tas2770.c | 53 --
sound/soc/codecs/tas2770.h | 1 +
2 files changed, 40 insertions(+), 14 deletions(-)
diff --git a/sound/soc/codecs/tas2770.c b/sound/soc/codecs/tas2770.c
index 386aaa11fa08..9f7363927c50 100644
--- a/sound/soc/codecs/tas2770.c
+++ b/sound/soc/codecs/tas2770.c
@@ -79,28 +79,42 @@ static int tas2770_set_bias_level(struct snd_soc_component
*component,
#ifdef CONFIG_PM
static int tas2770_codec_suspend(struct snd_soc_component *component)
{
- int ret;
+ struct tas2770_priv *tas2770 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
- ret = snd_soc_component_update_bits(component, TAS2770_PWR_CTRL,
- TAS2770_PWR_CTRL_MASK,
- TAS2770_PWR_CTRL_SHUTDOWN);
- if (ret < 0)
- return ret;
+ if (tas2770->sdz_gpio) {
+ gpiod_set_value_cansleep(tas2770->sdz_gpio, 0);
+ } else {
+ ret = snd_soc_component_update_bits(component, TAS2770_PWR_CTRL,
+ TAS2770_PWR_CTRL_MASK,
+ TAS2770_PWR_CTRL_SHUTDOWN);
+ if (ret < 0)
+ return ret;
- return 0;
+ ret = 0;
+ }
+
+ return ret;
}
static int tas2770_codec_resume(struct snd_soc_component *component)
{
- int ret;
+ struct tas2770_priv *tas2770 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
- ret = snd_soc_component_update_bits(component, TAS2770_PWR_CTRL,
- TAS2770_PWR_CTRL_MASK,
- TAS2770_PWR_CTRL_ACTIVE);
- if (ret < 0)
- return ret;
+ if (tas2770->sdz_gpio) {
+ gpiod_set_value_cansleep(tas2770->sdz_gpio, 1);
+ } else {
+ ret = snd_soc_component_update_bits(component, TAS2770_PWR_CTRL,
+ TAS2770_PWR_CTRL_MASK,
+ TAS2770_PWR_CTRL_ACTIVE);
+ if (ret < 0)
+ return ret;
- return 0;
+ ret = 0;
+ }
+
+ return ret;
}
#else
#define tas2770_codec_suspend NULL
@@ -498,6 +512,9 @@ static int tas2770_codec_probe(struct snd_soc_component
*component)
tas2770->component = component;
+ if (tas2770->sdz_gpio)
+ gpiod_set_value_cansleep(tas2770->sdz_gpio, 1);
+
tas2770_reset(tas2770);
return 0;
@@ -650,6 +667,14 @@ static int tas2770_parse_dt(struct device *dev, struct
tas2770_priv *tas2770)
tas2770->v_sense_slot = 2;
}
+ tas2770->sdz_gpio = devm_gpiod_get_optional(dev, "shutdown",
GPIOD_OUT_HIGH);
+ if (IS_ERR(tas2770->sdz_gpio)) {
+ if (PTR_ERR(tas2770->sdz_gpio) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ tas2770->sdz_gpio = NULL;
+ }
+
return 0;
}
diff --git a/sound/soc/codecs/tas2770.h b/sound/soc/codecs/tas2770.h
index 07e3556fc702..b3fc4a487033 100644
--- a/sound/soc/codecs/tas2770.h
+++ b/sound/soc/codecs/tas2770.h
@@ -134,6 +134,7 @@ struct tas2770_priv {
int power_state;
int asi_format;
struct gpio_desc *reset_gpio;
+ struct gpio_desc *sdz_gpio;
int sampling_rate;
int channel_size;
int slot_width;
--
2.28.0
[PATCH 4/6] dt-bindings: tas2770: Remove ti,asi-format property
Remove the property ti,asi-format as the driver only reads this property and performs no action against it. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/sound/tas2770.yaml | 7 --- 1 file changed, 7 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/tas2770.yaml b/Documentation/devicetree/bindings/sound/tas2770.yaml index 9fdf614add55..aa8c74575ac9 100644 --- a/Documentation/devicetree/bindings/sound/tas2770.yaml +++ b/Documentation/devicetree/bindings/sound/tas2770.yaml @@ -43,13 +43,6 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: TDM TX voltage sense time slot. - ti,asi-format: -$ref: /schemas/types.yaml#/definitions/uint32 -description: Sets TDM RX capture edge. -enum: - - 0 # Rising edge - - 1 # Falling edge - '#sound-dai-cells': const: 1 -- 2.28.0
Re: [EXTERNAL] Re: [PATCH v3 1/2] dt-bindings: power: Add the bq256xx dt bindings
RIcardo On 9/22/20 5:56 PM, Ricardo Rivera-Matos wrote: Rob On 9/22/20 5:22 PM, Rob Herring wrote: On Thu, Sep 10, 2020 at 11:45:33AM -0500, Ricardo Rivera-Matos wrote: Add the bindings for the bq256xx series of battery charging ICs. Datasheets: - https://www.ti.com/lit/ds/symlink/bq25600.pdf - https://www.ti.com/lit/ds/symlink/bq25601.pdf - https://www.ti.com/lit/ds/symlink/bq25600d.pdf - https://www.ti.com/lit/ds/symlink/bq25601d.pdf - https://www.ti.com/lit/ds/symlink/bq25611d.pdf - https://www.ti.com/lit/ds/symlink/bq25618.pdf - https://www.ti.com/lit/ds/symlink/bq25619.pdf Signed-off-by: Ricardo Rivera-Matos --- .../bindings/power/supply/bq256xx.yaml | 97 +++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/supply/bq256xx.yaml diff --git a/Documentation/devicetree/bindings/power/supply/bq256xx.yaml b/Documentation/devicetree/bindings/power/supply/bq256xx.yaml new file mode 100644 index ..8cc2242f7df0 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/bq256xx.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/supply/bq256xx.yaml#; +$schema: "http://devicetree.org/meta-schemas/core.yaml#; + +title: TI bq256xx Switch Mode Buck Charger + +maintainers: + - Ricardo Rivera-Matos + +description: | + The bq256xx devices are a family of highly-integrated battery charge + management and system power management ICs for single cell Li-ion and Li- + polymer batteries. + + Datasheets: + - https://www.ti.com/lit/ds/symlink/bq25600.pdf + - https://www.ti.com/lit/ds/symlink/bq25601.pdf + - https://www.ti.com/lit/ds/symlink/bq25600d.pdf + - https://www.ti.com/lit/ds/symlink/bq25601d.pdf + - https://www.ti.com/lit/ds/symlink/bq25611d.pdf + - https://www.ti.com/lit/ds/symlink/bq25618.pdf + - https://www.ti.com/lit/ds/symlink/bq25619.pdf + +properties: + compatible: + enum: + - ti,bq25600 + - ti,bq25601 + - ti,bq25600d + - ti,bq25601d + - ti,bq25611d + - ti,bq25618 + - ti,bq25619 + + reg: + maxItems: 1 + + ti,watchdog-timer: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Watchdog timer in ms. 0 (default) disables the watchdog + minimum: 0 + maximum: 16 + enum: [ 0, 4, 8, 16] + + input-voltage-limit-microvolt: + description: | + Minimum input voltage limit in µV with a 10 µV step + minimum: 390 + maximum: 540 + + input-current-limit-microamp: + description: | + Maximum input current limit in µA with a 10 µA step + minimum: 10 + maximum: 320 + +required: + - compatible + - reg + - monitored-battery additionalProperties: false And then fix what breaks in the example. ACK. I will document the monitored-battery and interrupts properties and fix the example. Is ti,watchdog-timer okay as it is currently documented? For TI consistency please use ti,watchdog-timeout-ms Dan
[PATCH 2/2] leds: lm36274: Fix warning for undefined parameters
Fix warnings for undefined parameters when building with W=1.
Fixes: 11e1bbc116a75 ("leds: lm36274: Introduce the TI LM36274 LED driver")
Signed-off-by: Dan Murphy
---
drivers/leds/leds-lm36274.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/leds/leds-lm36274.c b/drivers/leds/leds-lm36274.c
index 10a63b7f2ecc..bf6487e9a1f4 100644
--- a/drivers/leds/leds-lm36274.c
+++ b/drivers/leds/leds-lm36274.c
@@ -26,8 +26,8 @@
* @lmu_data: Register and setting values for common code
* @regmap: Devices register map
* @dev: Pointer to the devices device struct
- * @led_sources - The LED strings supported in this array
- * @num_leds - Number of LED strings are supported in this array
+ * @led_sources: The LED strings supported in this array
+ * @num_leds: Number of LED strings are supported in this array
*/
struct lm36274 {
struct platform_device *pdev;
@@ -163,6 +163,7 @@ static struct platform_driver lm36274_driver = {
.probe = lm36274_probe,
.driver = {
.name = "lm36274-leds",
+ .of_match_table = of_lm36274_leds_match,
},
};
module_platform_driver(lm36274_driver)
--
2.28.0
[PATCH 1/2] leds: lm3552: Fix warnings for undefined parameters
Fix warnings for undefined parameters when W=1 is used.
Fixes: bc1b8492c764f ("leds: lm3532: Introduce the lm3532 LED driver")
Signed-off-by: Dan Murphy
---
drivers/leds/leds-lm3532.c | 50 +++---
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/leds/leds-lm3532.c b/drivers/leds/leds-lm3532.c
index 9b6973217cc0..95221d1e3861 100644
--- a/drivers/leds/leds-lm3532.c
+++ b/drivers/leds/leds-lm3532.c
@@ -96,15 +96,15 @@
/*
* struct lm3532_als_data
- * @config - value of ALS configuration register
- * @als1_imp_sel - value of ALS1 resistor select register
- * @als2_imp_sel - value of ALS2 resistor select register
- * @als_avrg_time - ALS averaging time
- * @als_input_mode - ALS input mode for brightness control
- * @als_vmin - Minimum ALS voltage
- * @als_vmax - Maximum ALS voltage
- * @zone_lo - values of ALS lo ZB(Zone Boundary) registers
- * @zone_hi - values of ALS hi ZB(Zone Boundary) registers
+ * @config: value of ALS configuration register
+ * @als1_imp_sel: value of ALS1 resistor select register
+ * @als2_imp_sel: value of ALS2 resistor select register
+ * @als_avrg_time: ALS averaging time
+ * @als_input_mode: ALS input mode for brightness control
+ * @als_vmin: Minimum ALS voltage
+ * @als_vmax: Maximum ALS voltage
+ * @zone_lo: values of ALS lo ZB(Zone Boundary) registers
+ * @zone_hi: values of ALS hi ZB(Zone Boundary) registers
*/
struct lm3532_als_data {
u8 config;
@@ -121,14 +121,14 @@ struct lm3532_als_data {
/**
* struct lm3532_led
* @led_dev: led class device
- * @priv - Pointer the device data structure
- * @control_bank - Control bank the LED is associated to
- * @mode - Mode of the LED string
- * @ctrl_brt_pointer - Zone target register that controls the sink
- * @num_leds - Number of LED strings are supported in this array
- * @full_scale_current - The full-scale current setting for the current sink.
- * @led_strings - The LED strings supported in this array
- * @enabled - Enabled status
+ * @priv: Pointer the device data structure
+ * @control_bank: Control bank the LED is associated to
+ * @mode: Mode of the LED string
+ * @ctrl_brt_pointer: Zone target register that controls the sink
+ * @num_leds: Number of LED strings are supported in this array
+ * @full_scale_current: The full-scale current setting for the current sink.
+ * @led_strings: The LED strings supported in this array
+ * @enabled: Enabled status
*/
struct lm3532_led {
struct led_classdev led_dev;
@@ -145,16 +145,16 @@ struct lm3532_led {
/**
* struct lm3532_data
- * @enable_gpio - Hardware enable gpio
+ * @enable_gpio: Hardware enable gpio
* @regulator: regulator
* @client: i2c client
- * @regmap - Devices register map
- * @dev - Pointer to the devices device struct
- * @lock - Lock for reading/writing the device
- * @als_data - Pointer to the als data struct
- * @runtime_ramp_up - Runtime ramp up setting
- * @runtime_ramp_down - Runtime ramp down setting
- * @leds - Array of LED strings
+ * @regmap: Devices register map
+ * @dev: Pointer to the devices device struct
+ * @lock: Lock for reading/writing the device
+ * @als_data: Pointer to the als data struct
+ * @runtime_ramp_up: Runtime ramp up setting
+ * @runtime_ramp_down: Runtime ramp down setting
+ * @leds: Array of LED strings
*/
struct lm3532_data {
struct gpio_desc *enable_gpio;
--
2.28.0
Re: [PATCH 2/2] power: bq25980: Add support for the BQ259xx family
Hello On 8/31/20 11:48 AM, Dan Murphy wrote: Add support for the BQ25980, BQ25975 and BQ25960 family of flash chargers. Gentle Bump
Re: [PATCH v2 2/2] power: supply: bq25790: Introduce the BQ25790 charger driver
Hello On 8/17/20 10:16 AM, Dan Murphy wrote: BQ25790 is a highly integrated switch-mode buck-boost charger for 1-4 cell Li-ion battery and Li-polymer battery. Gentle bump
