[PATCH v8 3/3] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[David Daney]

Signed-off-by: David Daney <david.da...@cavium.com>
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9a7f76eadae9..b36371ae590f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3259,6 +3259,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M: Steven J. Hill <steven.h...@cavium.com>
+L: net...@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian <george.cher...@cavium.com>
 L: linux-cry...@vger.kernel.org
-- 
2.14.3

[PATCH v8 1/3] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

Add bindings for Common Ethernet Interface (BGX) block.

Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 .../devicetree/bindings/net/cavium-bgx.txt | 61 ++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index ..830c5f08
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,61 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+A BGX block has several children, each representing an Ethernet
+interface.
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all
+ cn7xxx SOCs.
+
+ "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs
+ for RGMII.
+
+- reg: The index of the interface within the BGX block.
+
+Optional properties:
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- phy-mode: described in ethernet.txt.
+
+- fixed-link: described in fixed-link.txt.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet@0 {
+   compatible = "cavium,octeon-7360-xcv";
+   reg = <0>;
+   local-mac-address = [ 00 01 23 45 67 89 ];
+   phy-handle = <>;
+   phy-mode = "rgmii-rxid"
+   };
+   ethernet@1 {
+   compatible = "cavium,octeon-7890-bgx-port";
+   reg = <1>;
+   local-mac-address = [ 00 01 23 45 67 8a ];
+   phy-handle = <>;
+   phy-mode = "sgmii"
+   };
+   };
-- 
2.14.3

[PATCH v8 1/3] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[David Daney]

From: Carlos Munoz 

Add bindings for Common Ethernet Interface (BGX) block.

Acked-by: Rob Herring 
Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 .../devicetree/bindings/net/cavium-bgx.txt | 61 ++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index ..830c5f08
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,61 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+A BGX block has several children, each representing an Ethernet
+interface.
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all
+ cn7xxx SOCs.
+
+ "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs
+ for RGMII.
+
+- reg: The index of the interface within the BGX block.
+
+Optional properties:
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- phy-mode: described in ethernet.txt.
+
+- fixed-link: described in fixed-link.txt.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet@0 {
+   compatible = "cavium,octeon-7360-xcv";
+   reg = <0>;
+   local-mac-address = [ 00 01 23 45 67 89 ];
+   phy-handle = <>;
+   phy-mode = "rgmii-rxid"
+   };
+   ethernet@1 {
+   compatible = "cavium,octeon-7890-bgx-port";
+   reg = <1>;
+   local-mac-address = [ 00 01 23 45 67 8a ];
+   phy-handle = <>;
+   phy-mode = "sgmii"
+   };
+   };
-- 
2.14.3

[PATCH v8 3/3] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[David Daney]

Signed-off-by: David Daney 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9a7f76eadae9..b36371ae590f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3259,6 +3259,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M: Steven J. Hill 
+L: net...@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian 
 L: linux-cry...@vger.kernel.org
-- 
2.14.3

[PATCH v8 0/3] netdev: octeon-ethernet: Add Cavium Octeon III support.

[David Daney]

We are adding the Cavium OCTEON-III network driver.  Since interacting
with the input and output queues is done via special CPU local memory,
we also need to add support to the MIPS/Octeon architecture code.  The
four patch set to add this prerequisite code has been split out to a
seperate patch set sent to the mips-linux list.

A separate pull request was recently done by Steven Hill for the
firmware required by the driver.

Changes in v8:

o Fixed locking in bgx port functions as noted by davem.

o Corrected SPDX-License-Identifier tags.

o Split driver from prerequisite patches.

Changes in v7:

o There was no v7, we go to v8 to synchronize version numbers with
prerequisites.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs (in
  the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (2):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  netdev: octeon-ethernet: Add Cavium Octeon III support.

David Daney (1):
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   61 +
 MAINTAINERS|6 +
 drivers/net/ethernet/cavium/Kconfig|   59 +-
 drivers/net/ethernet/cavium/octeon/Makefile|7 +
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  417 
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2003 +++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2079 
 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c   |  358 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  823 
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1688 
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  301 +++
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  430 
 12 files changed, 8222 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.14.3

[PATCH v8 0/3] netdev: octeon-ethernet: Add Cavium Octeon III support.

[David Daney]

We are adding the Cavium OCTEON-III network driver.  Since interacting
with the input and output queues is done via special CPU local memory,
we also need to add support to the MIPS/Octeon architecture code.  The
four patch set to add this prerequisite code has been split out to a
seperate patch set sent to the mips-linux list.

A separate pull request was recently done by Steven Hill for the
firmware required by the driver.

Changes in v8:

o Fixed locking in bgx port functions as noted by davem.

o Corrected SPDX-License-Identifier tags.

o Split driver from prerequisite patches.

Changes in v7:

o There was no v7, we go to v8 to synchronize version numbers with
prerequisites.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs (in
  the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (2):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  netdev: octeon-ethernet: Add Cavium Octeon III support.

David Daney (1):
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   61 +
 MAINTAINERS|6 +
 drivers/net/ethernet/cavium/Kconfig|   59 +-
 drivers/net/ethernet/cavium/octeon/Makefile|7 +
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  417 
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2003 +++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2079 
 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c   |  358 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  823 
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1688 
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  301 +++
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  430 
 12 files changed, 8222 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.14.3

[PATCH v8 3/4] staging: octeon: Remove USE_ASYNC_IOBDMA macro.

[David Daney]

Previous patch sets USE_ASYNC_IOBDMA to 1 unconditionally.  Remove
USE_ASYNC_IOBDMA from all if statements.  Remove dead code caused by
the change.

Acked-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 drivers/staging/octeon/ethernet-defines.h |  6 ---
 drivers/staging/octeon/ethernet-rx.c  | 25 -
 drivers/staging/octeon/ethernet-tx.c  | 85 ++-
 3 files changed, 37 insertions(+), 79 deletions(-)

diff --git a/drivers/staging/octeon/ethernet-defines.h 
b/drivers/staging/octeon/ethernet-defines.h
index 33c71f86890b..15db928c4712 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -7,10 +7,6 @@
 
 /*
  * A few defines are used to control the operation of this driver:
- *  USE_ASYNC_IOBDMA
- *  Use asynchronous IO access to hardware. This uses Octeon's asynchronous
- *  IOBDMAs to issue IO accesses without stalling. Set this to zero
- *  to disable this. Note that IOBDMAs require CVMSEG.
  *  REUSE_SKBUFFS_WITHOUT_FREE
  *  Allows the TX path to free an skbuff into the FPA hardware pool. This
  *  can significantly improve performance for forwarding and bridging, but
@@ -29,8 +25,6 @@
 #define REUSE_SKBUFFS_WITHOUT_FREE  1
 #endif
 
-#define USE_ASYNC_IOBDMA   1
-
 /* Maximum number of SKBs to try to free per xmit packet. */
 #define MAX_OUT_QUEUE_DEPTH 1000
 
diff --git a/drivers/staging/octeon/ethernet-rx.c 
b/drivers/staging/octeon/ethernet-rx.c
index 5e271245273c..c1ae60ce11f5 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -198,11 +198,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
/* Prefetch cvm_oct_device since we know we need it soon */
prefetch(cvm_oct_device);
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   }
+   /* Save scratch in case userspace is using it */
+   CVMX_SYNCIOBDMA;
+   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
 
/* Only allow work for our group (and preserve priorities) */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -217,10 +215,8 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
   BIT(rx_group->group));
}
 
-   if (USE_ASYNC_IOBDMA) {
-   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
-   did_work_request = 1;
-   }
+   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+   did_work_request = 1;
 
while (rx_count < budget) {
struct sk_buff *skb = NULL;
@@ -229,7 +225,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_wqe_t *work;
int port;
 
-   if (USE_ASYNC_IOBDMA && did_work_request)
+   if (did_work_request)
work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
else
work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
@@ -257,7 +253,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
sizeof(void *));
prefetch(pskb);
 
-   if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
+   if (rx_count < (budget - 1)) {
cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH,
CVMX_POW_NO_WAIT);
did_work_request = 1;
@@ -400,10 +396,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Restore the scratch area */
-   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
-   }
+   /* Restore the scratch area */
+   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+
cvm_oct_rx_refill_pool(0);
 
return rx_count;
diff --git a/drivers/staging/octeon/ethernet-tx.c 
b/drivers/staging/octeon/ethernet-tx.c
index df3441b815bb..2aa5fcb7ee32 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -176,23 +176,18 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device 
*dev)
qos = 0;
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
-
-   /*
-* Fetch and increment the number o

[PATCH v8 3/4] staging: octeon: Remove USE_ASYNC_IOBDMA macro.

[David Daney]

Previous patch sets USE_ASYNC_IOBDMA to 1 unconditionally.  Remove
USE_ASYNC_IOBDMA from all if statements.  Remove dead code caused by
the change.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: David Daney 
---
 drivers/staging/octeon/ethernet-defines.h |  6 ---
 drivers/staging/octeon/ethernet-rx.c  | 25 -
 drivers/staging/octeon/ethernet-tx.c  | 85 ++-
 3 files changed, 37 insertions(+), 79 deletions(-)

diff --git a/drivers/staging/octeon/ethernet-defines.h 
b/drivers/staging/octeon/ethernet-defines.h
index 33c71f86890b..15db928c4712 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -7,10 +7,6 @@
 
 /*
  * A few defines are used to control the operation of this driver:
- *  USE_ASYNC_IOBDMA
- *  Use asynchronous IO access to hardware. This uses Octeon's asynchronous
- *  IOBDMAs to issue IO accesses without stalling. Set this to zero
- *  to disable this. Note that IOBDMAs require CVMSEG.
  *  REUSE_SKBUFFS_WITHOUT_FREE
  *  Allows the TX path to free an skbuff into the FPA hardware pool. This
  *  can significantly improve performance for forwarding and bridging, but
@@ -29,8 +25,6 @@
 #define REUSE_SKBUFFS_WITHOUT_FREE  1
 #endif
 
-#define USE_ASYNC_IOBDMA   1
-
 /* Maximum number of SKBs to try to free per xmit packet. */
 #define MAX_OUT_QUEUE_DEPTH 1000
 
diff --git a/drivers/staging/octeon/ethernet-rx.c 
b/drivers/staging/octeon/ethernet-rx.c
index 5e271245273c..c1ae60ce11f5 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -198,11 +198,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
/* Prefetch cvm_oct_device since we know we need it soon */
prefetch(cvm_oct_device);
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   }
+   /* Save scratch in case userspace is using it */
+   CVMX_SYNCIOBDMA;
+   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
 
/* Only allow work for our group (and preserve priorities) */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -217,10 +215,8 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
   BIT(rx_group->group));
}
 
-   if (USE_ASYNC_IOBDMA) {
-   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
-   did_work_request = 1;
-   }
+   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+   did_work_request = 1;
 
while (rx_count < budget) {
struct sk_buff *skb = NULL;
@@ -229,7 +225,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_wqe_t *work;
int port;
 
-   if (USE_ASYNC_IOBDMA && did_work_request)
+   if (did_work_request)
work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
else
work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
@@ -257,7 +253,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
sizeof(void *));
prefetch(pskb);
 
-   if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
+   if (rx_count < (budget - 1)) {
cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH,
CVMX_POW_NO_WAIT);
did_work_request = 1;
@@ -400,10 +396,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Restore the scratch area */
-   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
-   }
+   /* Restore the scratch area */
+   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+
cvm_oct_rx_refill_pool(0);
 
return rx_count;
diff --git a/drivers/staging/octeon/ethernet-tx.c 
b/drivers/staging/octeon/ethernet-tx.c
index df3441b815bb..2aa5fcb7ee32 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -176,23 +176,18 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device 
*dev)
qos = 0;
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
-
-   /*
-* Fetch and increment the number of packets to be
-* freed.
-*/
-   cv

[PATCH v8 1/4] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
  (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
  (up to 128) of data to the I/O device and then return a
  variable length (up to 128 bytes) response from the I/O device.

For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.

Reviewed-by: James Hogan <jho...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/setup.c   |  6 ++
 arch/mips/include/asm/octeon/octeon.h | 12 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
 #else
cvmmemctl.s.cvmsegenak = 0;
 #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;
+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
 };
 
-- 
2.14.3

[PATCH v8 1/4] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

From: Carlos Munoz 

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
  (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
  (up to 128) of data to the I/O device and then return a
  variable length (up to 128 bytes) response from the I/O device.

For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.

Reviewed-by: James Hogan 
Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 arch/mips/cavium-octeon/setup.c   |  6 ++
 arch/mips/include/asm/octeon/octeon.h | 12 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
 #else
cvmmemctl.s.cvmsegenak = 0;
 #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;
+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
 };
 
-- 
2.14.3

[PATCH v8 0/4] Prerequisites for Cavium OCTEON-III network driver.

[David Daney]

We want to add the Cavium OCTEON-III network driver.  But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code.  Aren't SoCs nice in this way?  These are the
prerequisite patches that are needed before the network driver can be
merged.

Changes in v8:

o Rebased to v4.16-rc2

Changes in v7:

o Splitting of the patch set only.  These 4 mips patches are unchanged
  from the previous posting.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs
  (in the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (2):
  MIPS: Octeon: Enable LMTDMA/LMTST operations.
  MIPS: Octeon: Add a global resource manager.

David Daney (2):
  MIPS: Octeon: Automatically provision CVMSEG space.
  staging: octeon: Remove USE_ASYNC_IOBDMA macro.

 arch/mips/cavium-octeon/Kconfig|  27 +-
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/cavium-octeon/setup.c|  22 +-
 .../asm/mach-cavium-octeon/kernel-entry-init.h |  20 +-
 arch/mips/include/asm/mipsregs.h   |   2 +
 arch/mips/include/asm/octeon/octeon.h  |  32 +-
 arch/mips/include/asm/processor.h  |   2 +-
 arch/mips/kernel/octeon_switch.S   |   2 -
 arch/mips/mm/tlbex.c   |  29 +-
 drivers/staging/octeon/ethernet-defines.h  |   6 -
 drivers/staging/octeon/ethernet-rx.c   |  25 +-
 drivers/staging/octeon/ethernet-tx.c   |  85 ++---
 13 files changed, 472 insertions(+), 132 deletions(-)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

-- 
2.14.3

[PATCH v8 0/4] Prerequisites for Cavium OCTEON-III network driver.

[David Daney]

We want to add the Cavium OCTEON-III network driver.  But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code.  Aren't SoCs nice in this way?  These are the
prerequisite patches that are needed before the network driver can be
merged.

Changes in v8:

o Rebased to v4.16-rc2

Changes in v7:

o Splitting of the patch set only.  These 4 mips patches are unchanged
  from the previous posting.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs
  (in the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (2):
  MIPS: Octeon: Enable LMTDMA/LMTST operations.
  MIPS: Octeon: Add a global resource manager.

David Daney (2):
  MIPS: Octeon: Automatically provision CVMSEG space.
  staging: octeon: Remove USE_ASYNC_IOBDMA macro.

 arch/mips/cavium-octeon/Kconfig|  27 +-
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/cavium-octeon/setup.c|  22 +-
 .../asm/mach-cavium-octeon/kernel-entry-init.h |  20 +-
 arch/mips/include/asm/mipsregs.h   |   2 +
 arch/mips/include/asm/octeon/octeon.h  |  32 +-
 arch/mips/include/asm/processor.h  |   2 +-
 arch/mips/kernel/octeon_switch.S   |   2 -
 arch/mips/mm/tlbex.c   |  29 +-
 drivers/staging/octeon/ethernet-defines.h  |   6 -
 drivers/staging/octeon/ethernet-rx.c   |  25 +-
 drivers/staging/octeon/ethernet-tx.c   |  85 ++---
 13 files changed, 472 insertions(+), 132 deletions(-)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

-- 
2.14.3

[PATCH v8 2/4] MIPS: Octeon: Automatically provision CVMSEG space.

[David Daney]

Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.

1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE

New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.

Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Carlos Munoz <cmu...@caviumnetworks.com>
---
 arch/mips/cavium-octeon/Kconfig| 27 
 arch/mips/cavium-octeon/setup.c| 16 ++--
 .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +--
 arch/mips/include/asm/mipsregs.h   |  2 ++
 arch/mips/include/asm/octeon/octeon.h  |  2 ++
 arch/mips/include/asm/processor.h  |  2 +-
 arch/mips/kernel/octeon_switch.S   |  2 --
 arch/mips/mm/tlbex.c   | 29 ++
 drivers/staging/octeon/ethernet-defines.h  |  2 +-
 9 files changed, 50 insertions(+), 52 deletions(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index b5eee1a57d6c..a283b73b7fc6 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -11,21 +11,26 @@ config CAVIUM_CN63XXP1
  non-CN63XXP1 hardware, so it is recommended to select "n"
  unless it is known the workarounds are needed.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-   int "Number of L1 cache lines reserved for CVMSEG memory"
-   range 0 54
-   default 1
-   help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
 
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+   int "Number of extra L1 cache lines reserved for CVMSEG memory"
+   range 0 50
+   default 0
+   help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is.  The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
 config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68bc652..51c4d3c3cada 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
 static unsigned long long max_memory = ULLONG_MAX;
 static unsigned long long reserve_low_mem;
 
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 EXPORT_SYMBOL(octeon_bootbus_sem);
 
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
 
/* R/W If set, CVMSEG is available for loads/stores in
 * kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
-   cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
 
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
-   pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+   pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
 
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38ce5a3d..cdcca60978a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+   mfc0v1, CP0_PRID_REG
+   andiv1, 0xff00

[PATCH v8 4/4] MIPS: Octeon: Add a global resource manager.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/include/asm/octeon/octeon.h  |  18 ++
 3 files changed, 370 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..28c0bb75d1a4 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -10,6 +10,7 @@
 #
 
 obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y += resource-mgr.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..74efda5420ff
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   while (cmpxchg(_mgr_info->rlock, 0, 1))
+   ; /* Loop while not zero */
+   rmb();
+}
+
+static void res_mgr_unlock(void)
+{
+   /* Wait until all resource operations finish before unlocking. */
+   wmb();
+   WRITE_ONCE(res_mgr_info->rlock, 0);
+   /* Force a write buffer flush. */
+   wmb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource() - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source was created successfully.
+ * Returns < 0 for error codes.
+ */
+int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt)
+{
+   struct global_resource_entry *res_entry;
+   u64 size;
+   u64 *res_addr;
+   int res_index, i, rc = 0;
+
+   res_mgr_lock();
+
+   /* Make sure resource doesn't already exist. */
+   res_index = res_mgr_find_resource(tag);
+   if (res_index >= 0) {
+   rc = -EEXIST;
+   goto err;
+   }
+
+   if (res_mgr_info->entry_cnt >= MAX_RESOURCES) {
+   pr_err("Resource max limit reached, not created\n");
+   rc = -ENOSPC;
+   goto err;
+   }
+
+   /*
+* Each instance is kept in an array of u64s. The first array element
+* holds the number of allocated instances.
+*/
+   size = sizeof(u64) * (inst_cnt + 1);
+   res_addr = cvmx_bootmem_alloc_range(size, CVMX_CACHE_LINE_SIZE, 0, 0);
+   if (!res_addr) {
+   pr_err("Failed to allocate resource. not created\n");
+   rc = -ENOMEM;
+   goto err;
+   }
+
+   /* Initialize the newly created resource. */
+   *res_addr = inst_cnt;
+   for (i = 1; i <= inst_cnt; i++)
+   res_addr[i] = INST_AVAILABLE;
+
+   res_index = res_mgr_info->entry_cnt;
+   res_entry = _mgr_info->resource_entry[res_index];
+   res_entry->tag = tag;
+   res_entry->phys_addr = virt_to_phys(res_addr);
+   res_entry->size = size;
+   res_mgr_in

[PATCH v8 2/4] MIPS: Octeon: Automatically provision CVMSEG space.

[David Daney]

Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.

1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE

New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.

Signed-off-by: David Daney 
Signed-off-by: Carlos Munoz 
---
 arch/mips/cavium-octeon/Kconfig| 27 
 arch/mips/cavium-octeon/setup.c| 16 ++--
 .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +--
 arch/mips/include/asm/mipsregs.h   |  2 ++
 arch/mips/include/asm/octeon/octeon.h  |  2 ++
 arch/mips/include/asm/processor.h  |  2 +-
 arch/mips/kernel/octeon_switch.S   |  2 --
 arch/mips/mm/tlbex.c   | 29 ++
 drivers/staging/octeon/ethernet-defines.h  |  2 +-
 9 files changed, 50 insertions(+), 52 deletions(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index b5eee1a57d6c..a283b73b7fc6 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -11,21 +11,26 @@ config CAVIUM_CN63XXP1
  non-CN63XXP1 hardware, so it is recommended to select "n"
  unless it is known the workarounds are needed.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-   int "Number of L1 cache lines reserved for CVMSEG memory"
-   range 0 54
-   default 1
-   help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
 
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+   int "Number of extra L1 cache lines reserved for CVMSEG memory"
+   range 0 50
+   default 0
+   help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is.  The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
 config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68bc652..51c4d3c3cada 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
 static unsigned long long max_memory = ULLONG_MAX;
 static unsigned long long reserve_low_mem;
 
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 EXPORT_SYMBOL(octeon_bootbus_sem);
 
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
 
/* R/W If set, CVMSEG is available for loads/stores in
 * kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
-   cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
 
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
-   pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+   pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
 
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38ce5a3d..cdcca60978a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+   mfc0v1, CP0_PRID_REG
+   andiv1, 0xff00
+   li  v0, 0x9500   

[PATCH v8 4/4] MIPS: Octeon: Add a global resource manager.

[David Daney]

From: Carlos Munoz 

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/include/asm/octeon/octeon.h  |  18 ++
 3 files changed, 370 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..28c0bb75d1a4 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -10,6 +10,7 @@
 #
 
 obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y += resource-mgr.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..74efda5420ff
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   while (cmpxchg(_mgr_info->rlock, 0, 1))
+   ; /* Loop while not zero */
+   rmb();
+}
+
+static void res_mgr_unlock(void)
+{
+   /* Wait until all resource operations finish before unlocking. */
+   wmb();
+   WRITE_ONCE(res_mgr_info->rlock, 0);
+   /* Force a write buffer flush. */
+   wmb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource() - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source was created successfully.
+ * Returns < 0 for error codes.
+ */
+int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt)
+{
+   struct global_resource_entry *res_entry;
+   u64 size;
+   u64 *res_addr;
+   int res_index, i, rc = 0;
+
+   res_mgr_lock();
+
+   /* Make sure resource doesn't already exist. */
+   res_index = res_mgr_find_resource(tag);
+   if (res_index >= 0) {
+   rc = -EEXIST;
+   goto err;
+   }
+
+   if (res_mgr_info->entry_cnt >= MAX_RESOURCES) {
+   pr_err("Resource max limit reached, not created\n");
+   rc = -ENOSPC;
+   goto err;
+   }
+
+   /*
+* Each instance is kept in an array of u64s. The first array element
+* holds the number of allocated instances.
+*/
+   size = sizeof(u64) * (inst_cnt + 1);
+   res_addr = cvmx_bootmem_alloc_range(size, CVMX_CACHE_LINE_SIZE, 0, 0);
+   if (!res_addr) {
+   pr_err("Failed to allocate resource. not created\n");
+   rc = -ENOMEM;
+   goto err;
+   }
+
+   /* Initialize the newly created resource. */
+   *res_addr = inst_cnt;
+   for (i = 1; i <= inst_cnt; i++)
+   res_addr[i] = INST_AVAILABLE;
+
+   res_index = res_mgr_info->entry_cnt;
+   res_entry = _mgr_info->resource_entry[res_index];
+   res_entry->tag = tag;
+   res_entry->phys_addr = virt_to_phys(res_addr);
+   res_entry->size = size;
+   res_mgr_info->entry_cnt++;
+
+err:
+   res_mgr_unlock();
+
+   return rc;
+}
+EXPORT_SYMBOL(res_mgr_create_resource);
+
+

[PATCH v6] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Reviewed-by: Rob Herring <r...@kernel.org>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---

Changes from v5:

o removed obsolete call to rtc_valid_tm().

Changes from v4:

o Rebased to rtc-next

o Improvements suggested by Alexandre Belloni

o Added Reviewed-by Rob Herring

Changes from v3:

o Add Reviewed-by

o s/dev_err/dev_warn/ in one place

o Remove redundant ','

Changes from v2:

o More code cleanups suggested by reviewers.

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

 .../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|  10 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 505 +
 4 files changed, 544 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index f6d7e490e714..3bf649cd7b83 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,16 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   depends on OF || COMPILE_TEST
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..ada9849d8d97
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct

[PATCH v6] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Reviewed-by: Rob Herring 
Reviewed-by: Andy Shevchenko 
Signed-off-by: David Daney 
---

Changes from v5:

o removed obsolete call to rtc_valid_tm().

Changes from v4:

o Rebased to rtc-next

o Improvements suggested by Alexandre Belloni

o Added Reviewed-by Rob Herring

Changes from v3:

o Add Reviewed-by

o s/dev_err/dev_warn/ in one place

o Remove redundant ','

Changes from v2:

o More code cleanups suggested by reviewers.

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

 .../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|  10 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 505 +
 4 files changed, 544 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index f6d7e490e714..3bf649cd7b83 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,16 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   depends on OF || COMPILE_TEST
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..ada9849d8d97
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+

Re: [PATCH] MIPS: OCTEON: irq: check for null return on kzalloc allocation

[David Daney]

On 02/22/2018 10:08 AM, Colin King wrote:

From: Colin Ian King <colin.k...@canonical.com>

The allocation of host_data is not null checked, leading to a
null pointer dereference if the allocation fails. Fix this by
adding a null check and return with -ENOMEM.

Fixes: 64b139f97c01 ("MIPS: OCTEON: irq: add CIB and other fixes")
Signed-off-by: Colin Ian King <colin.k...@canonical.com>


Acked-by: David Daney <david.da...@cavium.com>



---
  arch/mips/cavium-octeon/octeon-irq.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/arch/mips/cavium-octeon/octeon-irq.c 
b/arch/mips/cavium-octeon/octeon-irq.c
index b993d9f2c9b9..203e1d2a56d5 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -2277,6 +2277,8 @@ static int __init octeon_irq_init_cib(struct device_node 
*ciu_node,
}
  
  	host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);

+   if (!host_data)
+   return -ENOMEM;
raw_spin_lock_init(_data->lock);
  
  	addr = of_get_address(ciu_node, 0, NULL, NULL);

Re: [PATCH] MIPS: OCTEON: irq: check for null return on kzalloc allocation

[David Daney]

On 02/22/2018 10:08 AM, Colin King wrote:

From: Colin Ian King 

The allocation of host_data is not null checked, leading to a
null pointer dereference if the allocation fails. Fix this by
adding a null check and return with -ENOMEM.

Fixes: 64b139f97c01 ("MIPS: OCTEON: irq: add CIB and other fixes")
Signed-off-by: Colin Ian King 


Acked-by: David Daney 



---
  arch/mips/cavium-octeon/octeon-irq.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/arch/mips/cavium-octeon/octeon-irq.c 
b/arch/mips/cavium-octeon/octeon-irq.c
index b993d9f2c9b9..203e1d2a56d5 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -2277,6 +2277,8 @@ static int __init octeon_irq_init_cib(struct device_node 
*ciu_node,
}
  
  	host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);

+   if (!host_data)
+   return -ENOMEM;
raw_spin_lock_init(_data->lock);
  
  	addr = of_get_address(ciu_node, 0, NULL, NULL);

[PATCH v5] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Reviewed-by: Rob Herring <r...@kernel.org>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
Changes from v4:

o Rebased to rtc-next

o Improvements suggested by Alexandre Belloni

o Added Reviewed-by Rob Herring

Changes from v3:

o Add Reviewed-by

o s/dev_err/dev_warn/ in one place

o Remove redundant ','

Changes from v2:

o More code cleanups suggested by reviewers.

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

.../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|  10 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 505 +
 4 files changed, 544 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index f6d7e490e714..3bf649cd7b83 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,16 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   depends on OF || COMPILE_TEST
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..521511d1cc2d
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_cli

[PATCH v5] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Reviewed-by: Rob Herring 
Reviewed-by: Andy Shevchenko 
Signed-off-by: David Daney 
---
Changes from v4:

o Rebased to rtc-next

o Improvements suggested by Alexandre Belloni

o Added Reviewed-by Rob Herring

Changes from v3:

o Add Reviewed-by

o s/dev_err/dev_warn/ in one place

o Remove redundant ','

Changes from v2:

o More code cleanups suggested by reviewers.

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

.../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|  10 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 505 +
 4 files changed, 544 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index f6d7e490e714..3bf649cd7b83 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,16 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   depends on OF || COMPILE_TEST
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..521511d1cc2d
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+};
+
+static int isl12026_read_reg(struct i2c_cl

Re: [PATCH v4] rtc: isl12026: Add driver.

[David Daney]

On 02/20/2018 03:03 AM, Alexandre Belloni wrote:
[...]



diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..29e5bdf96c67
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,
+* the write cycle to the nvmem takes many ms during which the
+* device does not respond to commands, so holding the lock
+* also prevents access during these times.
+*/
+   struct mutex lock;
+};
+
+static int isl12026_read_reg(struct i2c_client *client, int reg)
+{
+   struct isl12026 *priv = i2c_get_clientdata(client);
+   u8 addr[] = {0, reg};
+   u8 val;
+   int ret;
+
+   struct i2c_msg msgs[] = {
+   {
+   .addr   = client->addr,
+   .flags  = 0,
+   .len= sizeof(addr),
+   .buf= addr
+   }, {
+   .addr   = client->addr,
+   .flags  = I2C_M_RD,
+   .len= 1,
+   .buf= 
+   }
+   };


I'm pretty sure you can use regmap instead of open coding all the i2c
transfers, did you try?


I couldn't figure out how to make it do the device-atomic stores to 
SR.RWEL and SR.WEL that must precede certain register store operations. 
Also, dealing with locking across multiple i2c target addresses seems 
problematical with the regmap helpers.


The open coding doesn't clutter things up too much, and allows us to 
follow the isl12026 protocol without having to jump through too many hoops.





+
+   mutex_lock(>lock);
+


Also, regmap will remove the need for that lock.


Since





+   ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+   if (ret != ARRAY_SIZE(msgs)) {
+   dev_err(>dev, "read reg error, ret=%d\n", ret);
+   ret = ret < 0 ? ret : -EIO;
+   } else {
+   ret = val;
+   }
+
+   mutex_unlock(>lock);
+
+   return ret;
+}
+
+static int isl12026_write_reg(struct i2c_client *client, int reg, u8 val)
+{
+   struct isl12026 *priv = i2c_get_clientdata(client);
+   int ret;
+   u8 op[3];
+   struct i2c_msg msg = {
+   .addr   = client->addr,
+   .flags  = 0,
+   .len= 1,
+   .buf= op
+   };
+
+   mutex_lock(>lock);
+
+   /* Set SR.WEL */
+   op[0] = 0;
+   op[1] = ISL12026_REG_SR;
+   op[2] = ISL12026_REG_SR_WEL;
+   msg.len = 3;
+   ret = i2c_transfer(client->adapter, , 1);
+   if (ret != 1) {
+   dev_err(>dev, "write error SR.WEL, ret=%d\n", ret);
+   ret = ret < 0 ? ret : -EIO;
+   goto out;
+   }


If you don't clear SR.WEL, I don't think you need to set it each time
you write to the RTC. I would just set SR.WEL at probe time and let it
there. That removes two i2c writes for each write operation.


I don't like the idea of leaving the thing partially armed when write 
operations should be rare.



[...]

+static int isl12026_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+   struct i2c_client *client = to_i2c_client(dev);
+   struct isl12026 *priv = i2c_get_clientdata(client);
+   u8 ccr[8];
+   u8 addr[2];
+   u8 sr;
+   int ret;
+   struct i2c_msg msgs[] = {
+   {
+   .addr   = client->addr,
+   .flags  = 0,
+   .len= sizeof(addr),
+   .buf= addr
+   }, {
+   .addr   = client->addr,
+   .flags  = I2C_M_RD,
+   }
+  

Re: [PATCH v4] rtc: isl12026: Add driver.

[David Daney]

On 02/20/2018 03:03 AM, Alexandre Belloni wrote:
[...]



diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..29e5bdf96c67
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,
+* the write cycle to the nvmem takes many ms during which the
+* device does not respond to commands, so holding the lock
+* also prevents access during these times.
+*/
+   struct mutex lock;
+};
+
+static int isl12026_read_reg(struct i2c_client *client, int reg)
+{
+   struct isl12026 *priv = i2c_get_clientdata(client);
+   u8 addr[] = {0, reg};
+   u8 val;
+   int ret;
+
+   struct i2c_msg msgs[] = {
+   {
+   .addr   = client->addr,
+   .flags  = 0,
+   .len= sizeof(addr),
+   .buf= addr
+   }, {
+   .addr   = client->addr,
+   .flags  = I2C_M_RD,
+   .len= 1,
+   .buf= 
+   }
+   };


I'm pretty sure you can use regmap instead of open coding all the i2c
transfers, did you try?


I couldn't figure out how to make it do the device-atomic stores to 
SR.RWEL and SR.WEL that must precede certain register store operations. 
Also, dealing with locking across multiple i2c target addresses seems 
problematical with the regmap helpers.


The open coding doesn't clutter things up too much, and allows us to 
follow the isl12026 protocol without having to jump through too many hoops.





+
+   mutex_lock(>lock);
+


Also, regmap will remove the need for that lock.


Since





+   ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+   if (ret != ARRAY_SIZE(msgs)) {
+   dev_err(>dev, "read reg error, ret=%d\n", ret);
+   ret = ret < 0 ? ret : -EIO;
+   } else {
+   ret = val;
+   }
+
+   mutex_unlock(>lock);
+
+   return ret;
+}
+
+static int isl12026_write_reg(struct i2c_client *client, int reg, u8 val)
+{
+   struct isl12026 *priv = i2c_get_clientdata(client);
+   int ret;
+   u8 op[3];
+   struct i2c_msg msg = {
+   .addr   = client->addr,
+   .flags  = 0,
+   .len= 1,
+   .buf= op
+   };
+
+   mutex_lock(>lock);
+
+   /* Set SR.WEL */
+   op[0] = 0;
+   op[1] = ISL12026_REG_SR;
+   op[2] = ISL12026_REG_SR_WEL;
+   msg.len = 3;
+   ret = i2c_transfer(client->adapter, , 1);
+   if (ret != 1) {
+   dev_err(>dev, "write error SR.WEL, ret=%d\n", ret);
+   ret = ret < 0 ? ret : -EIO;
+   goto out;
+   }


If you don't clear SR.WEL, I don't think you need to set it each time
you write to the RTC. I would just set SR.WEL at probe time and let it
there. That removes two i2c writes for each write operation.


I don't like the idea of leaving the thing partially armed when write 
operations should be rare.



[...]

+static int isl12026_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+   struct i2c_client *client = to_i2c_client(dev);
+   struct isl12026 *priv = i2c_get_clientdata(client);
+   u8 ccr[8];
+   u8 addr[2];
+   u8 sr;
+   int ret;
+   struct i2c_msg msgs[] = {
+   {
+   .addr   = client->addr,
+   .flags  = 0,
+   .len= sizeof(addr),
+   .buf= addr
+   }, {
+   .addr   = client->addr,
+   .flags  = I2C_M_RD,
+   }
+  

Re: [PATCH v4] rtc: isl12026: Add driver.

[David Daney]

On 02/16/2018 12:13 PM, Andy Shevchenko wrote:

On Fri, Feb 16, 2018 at 9:44 PM, David Daney <david.da...@cavium.com> wrote:

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.



+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"


depends on OF


It doesn't depend on CONFIG_OF, it builds just fine without it.




+static struct i2c_driver isl12026_driver = {
+   .driver = {
+   .name   = "rtc-isl12026",
+   .of_match_table = of_match_ptr(isl12026_dt_match),


/of_match_ptr//



of_match_ptr() needed if we build without CONFIG_OF




+   },
+   .probe_new  = isl12026_probe_new,
+   .remove = isl12026_remove,
+};

Re: [PATCH v4] rtc: isl12026: Add driver.

[David Daney]

On 02/16/2018 12:13 PM, Andy Shevchenko wrote:

On Fri, Feb 16, 2018 at 9:44 PM, David Daney  wrote:

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.



+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"


depends on OF


It doesn't depend on CONFIG_OF, it builds just fine without it.




+static struct i2c_driver isl12026_driver = {
+   .driver = {
+   .name   = "rtc-isl12026",
+   .of_match_table = of_match_ptr(isl12026_dt_match),


/of_match_ptr//



of_match_ptr() needed if we build without CONFIG_OF




+   },
+   .probe_new  = isl12026_probe_new,
+   .remove = isl12026_remove,
+};

[PATCH v4] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
Changes from v3:

o Add Reviewed-by

o s/dev_err/dev_warn/ in one place

o Remove redundant ','

Changes from v2:

o More code cleanups suggested by reviewers.

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

 .../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|   9 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 529 +
 4 files changed, 567 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8ab5f0a5d323..85171e9e3ada 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,15 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..29e5bdf96c67
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+ 

[PATCH v4] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Reviewed-by: Andy Shevchenko 
Signed-off-by: David Daney 
---
Changes from v3:

o Add Reviewed-by

o s/dev_err/dev_warn/ in one place

o Remove redundant ','

Changes from v2:

o More code cleanups suggested by reviewers.

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

 .../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|   9 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 529 +
 4 files changed, 567 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8ab5f0a5d323..85171e9e3ada 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,15 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..29e5bdf96c67
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,
+  

[PATCH v3] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Signed-off-by: David Daney <david.da...@cavium.com>
---
Changes from v2:

o More code cleanups suggested by reviewers.

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

.../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|   9 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 529 +
 4 files changed, 567 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8ab5f0a5d323..85171e9e3ada 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,15 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..1cb111e4c442
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,
+* the write cycle to the nvmem takes many ms during which the
+* device does not respon

[PATCH v3] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Signed-off-by: David Daney 
---
Changes from v2:

o More code cleanups suggested by reviewers.

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

.../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|   9 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 529 +
 4 files changed, 567 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8ab5f0a5d323..85171e9e3ada 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,15 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..1cb111e4c442
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* The EEPROM array responds at i2c address 0x57 */
+#define ISL12026_EEPROM_ADDR   0x57
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,
+* the write cycle to the nvmem takes many ms during which the
+* device does not respond to commands, so holding

Re: [PATCH v2] rtc: isl12026: Add driver.

[David Daney]

On 02/15/2018 04:45 AM, Andy Shevchenko wrote:

On Wed, Feb 14, 2018 at 2:55 AM, David Daney <david.da...@cavium.com> wrote:

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.


Thanks for an update, my comments below.


+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,



+* the write cycle to the nvmem takes many mS during which the


What mS means? milliseconds? The standard abbreviation for it 'ms'.


Yes, milliseconds.   OK.




+* device does not respond to commands, so holding the lock
+* also prevents access during these times.
+*/
+   struct mutex lock;
+};



+static int isl12026_read_reg(struct i2c_client *client, int reg)
+{



+   ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+   if (ret != ARRAY_SIZE(msgs)) {
+   dev_err(>dev, "read reg error, ret=%d\n", ret);
+   ret = ret < 0 ? ret : -EIO;
+   } else {
+   ret = val;
+   }



+   return val;


Something wrong. ret is not used after all.


+}


Check entire code for such.


OK.




+   /* 2 bytes of address, most significant first */
+   addr[0] = (offset >> 8) & 0xff;
+   addr[1] = offset & 0xff;


Consider to drop '& 0xff', they are pointless (you have u8 type).


Generated code is the same, but the intent of the code is less clear 
when the explicit masking is removed.  Never the less, since this seems 
to be impeding progress, I will remove it.






+   payload[0] = (offset >> 8) & 0xff;
+   payload[1] = offset & 0xff;


Ditto.


+static void isl12026_force_power_modes(struct i2c_client *client)
+{
+   int ret;
+   int pwr, requested_pwr;
+   u32 bsw_val, sbib_val;



+   bool set_bsw, set_sbib;
+



+   ret = of_property_read_u32(client->dev.of_node,
+  "isil,pwr-bsw", _val);
+   set_bsw = (ret == 0);


Which is not fully correct. Better to do


I think it is correct.  The properties are optional, so it it perfectly 
fine for of_property_read_u32() to fail.  If it fails, we simply keep 
the current value.  I will add comments to document the intended logic.




set_bsw = of_property_present();


There are no occurrences of "of_property_present" in my source tree.




ret = of_property_read...();
if (ret)
   return ret;


+
+   ret = of_property_read_u32(client->dev.of_node,
+  "isil,pwr-sbib", _val);
+   set_sbib = (ret == 0);


Ditto.


+
+   /* Check if PWR.BSW and/or PWR.SBIB need specified values */
+



+   if (set_bsw || set_sbib) {


if (!x && !y)
  return;


OK.




+   pwr = isl12026_read_reg(client, ISL12026_REG_PWR);
+   if (pwr < 0) {
+   dev_err(>dev,
+   "Error: Failed to read PWR %d\n", pwr);
+   return;
+   }
+
+   requested_pwr = pwr;
+
+   if (set_bsw) {
+   if (bsw_val)
+   requested_pwr |= ISL12026_REG_PWR_BSW;
+   else
+   requested_pwr &= ~ISL12026_REG_PWR_BSW;
+   }


Undefined state if no value?


It is defined.  See above.





+   if (set_sbib) {
+   if (sbib_val)
+   requested_pwr |= ISL12026_REG_PWR_SBIB;
+   else
+   requested_pwr &= ~ISL12026_REG_PWR_SBIB;
+   }


Ditto.


+
+   if (pwr >= 0 && pwr != requested_pwr) {



+   dev_info(>dev, "PWR: %02x\n", (u8)pwr);
+   dev_info(>dev,
+"Updating PWR to: %02x\n", (u8)requested_pwr);
+   isl12026_write_reg(client,
+  ISL12026_REG_PWR, requested_pwr);


If you do explicit casting in printf() parameters you are doing
something wrong in 99.9% cases.


OK.



+   }
+   }
+}



+static int isl12026_probe_new(struct i2c_client *client)
+{
+   struct isl12026 *priv;
+   int ret;




+   /* The NVMem array responds at i2c address 0x57 */
+   priv->nvm_client = i2c_new_dummy(client->adapter, 0x57);


Magic. Make it #define and put comment there.


+   i

Re: [PATCH v2] rtc: isl12026: Add driver.

[David Daney]

On 02/15/2018 04:45 AM, Andy Shevchenko wrote:

On Wed, Feb 14, 2018 at 2:55 AM, David Daney  wrote:

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.


Thanks for an update, my comments below.


+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,



+* the write cycle to the nvmem takes many mS during which the


What mS means? milliseconds? The standard abbreviation for it 'ms'.


Yes, milliseconds.   OK.




+* device does not respond to commands, so holding the lock
+* also prevents access during these times.
+*/
+   struct mutex lock;
+};



+static int isl12026_read_reg(struct i2c_client *client, int reg)
+{



+   ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+   if (ret != ARRAY_SIZE(msgs)) {
+   dev_err(>dev, "read reg error, ret=%d\n", ret);
+   ret = ret < 0 ? ret : -EIO;
+   } else {
+   ret = val;
+   }



+   return val;


Something wrong. ret is not used after all.


+}


Check entire code for such.


OK.




+   /* 2 bytes of address, most significant first */
+   addr[0] = (offset >> 8) & 0xff;
+   addr[1] = offset & 0xff;


Consider to drop '& 0xff', they are pointless (you have u8 type).


Generated code is the same, but the intent of the code is less clear 
when the explicit masking is removed.  Never the less, since this seems 
to be impeding progress, I will remove it.






+   payload[0] = (offset >> 8) & 0xff;
+   payload[1] = offset & 0xff;


Ditto.


+static void isl12026_force_power_modes(struct i2c_client *client)
+{
+   int ret;
+   int pwr, requested_pwr;
+   u32 bsw_val, sbib_val;



+   bool set_bsw, set_sbib;
+



+   ret = of_property_read_u32(client->dev.of_node,
+  "isil,pwr-bsw", _val);
+   set_bsw = (ret == 0);


Which is not fully correct. Better to do


I think it is correct.  The properties are optional, so it it perfectly 
fine for of_property_read_u32() to fail.  If it fails, we simply keep 
the current value.  I will add comments to document the intended logic.




set_bsw = of_property_present();


There are no occurrences of "of_property_present" in my source tree.




ret = of_property_read...();
if (ret)
   return ret;


+
+   ret = of_property_read_u32(client->dev.of_node,
+  "isil,pwr-sbib", _val);
+   set_sbib = (ret == 0);


Ditto.


+
+   /* Check if PWR.BSW and/or PWR.SBIB need specified values */
+



+   if (set_bsw || set_sbib) {


if (!x && !y)
  return;


OK.




+   pwr = isl12026_read_reg(client, ISL12026_REG_PWR);
+   if (pwr < 0) {
+   dev_err(>dev,
+   "Error: Failed to read PWR %d\n", pwr);
+   return;
+   }
+
+   requested_pwr = pwr;
+
+   if (set_bsw) {
+   if (bsw_val)
+   requested_pwr |= ISL12026_REG_PWR_BSW;
+   else
+   requested_pwr &= ~ISL12026_REG_PWR_BSW;
+   }


Undefined state if no value?


It is defined.  See above.





+   if (set_sbib) {
+   if (sbib_val)
+   requested_pwr |= ISL12026_REG_PWR_SBIB;
+   else
+   requested_pwr &= ~ISL12026_REG_PWR_SBIB;
+   }


Ditto.


+
+   if (pwr >= 0 && pwr != requested_pwr) {



+   dev_info(>dev, "PWR: %02x\n", (u8)pwr);
+   dev_info(>dev,
+"Updating PWR to: %02x\n", (u8)requested_pwr);
+   isl12026_write_reg(client,
+  ISL12026_REG_PWR, requested_pwr);


If you do explicit casting in printf() parameters you are doing
something wrong in 99.9% cases.


OK.



+   }
+   }
+}



+static int isl12026_probe_new(struct i2c_client *client)
+{
+   struct isl12026 *priv;
+   int ret;




+   /* The NVMem array responds at i2c address 0x57 */
+   priv->nvm_client = i2c_new_dummy(client->adapter, 0x57);


Magic. Make it #define and put comment there.


+   if (!priv->nvm_client)
+ 

[PATCH v2] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Signed-off-by: David Daney <david.da...@cavium.com>
---

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

 .../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|   9 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 526 +
 4 files changed, 564 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8ab5f0a5d323..85171e9e3ada 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,15 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..73bb70a2fde2
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,526 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,
+* the write cycle to the nvmem takes many mS during which the
+* device does not respond to commands, so holding the lock
+* also prevents access during these times.
+*/
+   struct mutex lock;
+};
+
+static int isl12026

[PATCH v2] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Signed-off-by: David Daney 
---

Changes from v1:

o Fixed device tree bindings document example.

o Use RTC_NVMEM facility for eeprom support.

o Small code cleanups suggested by reviewers.

 .../devicetree/bindings/rtc/isil,isl12026.txt  |  28 ++
 drivers/rtc/Kconfig|   9 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 526 +
 4 files changed, 564 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   compatible = "isil,isl12026";
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8ab5f0a5d323..85171e9e3ada 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,15 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..73bb70a2fde2
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,526 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+#define ISL12026_REG_SC0x30
+#define ISL12026_REG_HR0x32
+# define ISL12026_REG_HR_MIL   BIT(7)  /* military or 24 hour time */
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,
+* the write cycle to the nvmem takes many mS during which the
+* device does not respond to commands, so holding the lock
+* also prevents access during these times.
+*/
+   struct mutex lock;
+};
+
+static int isl12026_read_reg(struct i2c_client *cl

Re: [PATCH] rtc: isl12026: Add driver.

[David Daney]

and what? No recovery? No nothing except the message?


I will bail out of this setting or power handling if this happens, that 
seems like all that we could do.






+
+   requested_pwr = pwr;
+
+   if (set_bsw) {
+   if (bsw_val)
+   requested_pwr |= ISL12026_REG_PWR_BSW;
+   else
+   requested_pwr &= ~ISL12026_REG_PWR_BSW;
+   }
+   if (set_sbib) {
+   if (sbib_val)
+   requested_pwr |= ISL12026_REG_PWR_SBIB;
+   else
+   requested_pwr &= ~ISL12026_REG_PWR_SBIB;
+   }
+
+   if (pwr >= 0 && pwr != requested_pwr) {
+   dev_info(>dev, "PWR: %02x\n", pwr);
+   dev_info(>dev,
+"Updating PWR to: %02x\n", (u8)requested_pwr);
+   isl12026_write_reg(client,
+  ISL12026_REG_PWR, requested_pwr);
+   }
+   }


Can you refactor above to a separate function?


Done.




+   priv->rtc = devm_rtc_device_register(>dev, "rtc-isl12026",
+_rtc_ops, THIS_MODULE);



+


Redundant empty line.


+   ret = PTR_ERR_OR_ZERO(priv->rtc);
+   if (ret)
+   return ret;




+   if (IS_ENABLED(CONFIG_NVMEM)) {


I think you don't need this, see below.


+   priv->nvm_client = i2c_new_dummy(client->adapter, 0x57);
+   if (!priv->nvm_client)
+   return -ENOMEM;


i2c_new_secondary_device() ?


+   priv->nvm_dev = nvmem_register(>nvm_cfg);
+


Redundant empty line.


+   if (!priv->nvm_dev)


Should it be IS_ERR() ?


+   return -ENOMEM;


After all rtc_nvmem_register() ?



Yes, I switched to using that.




+   }
+   return 0;
+}
+
+static int isl12026_remove(struct i2c_client *client)
+{
+   struct isl12026 *priv = i2c_get_clientdata(client);
+



+   if (priv->nvm_dev)


How is it


+   nvmem_unregister(priv->nvm_dev);




+   if (priv->nvm_client)


Check with v4.16-rc1. This is duplicate check.


Yes.





+   i2c_unregister_device(priv->nvm_client);
+
+   return 0;
+}



+#ifdef CONFIG_OF


Useless.


+static const struct of_device_id isl12026_dt_match[] = {
+   { .compatible = "isil,isl12026" },
+   { },
+};
+MODULE_DEVICE_TABLE(of, isl12026_dt_match);
+#endif
+



+static const struct i2c_device_id isl12026_id[] = {
+   { "isl12026", 0 },
+   { }
+};
+MODULE_DEVICE_TABLE(i2c, isl12026_id);


Useless. Use ->probe_new() approach.


+#ifdef CONFIG_OF


Ugly and useless.


+   .of_match_table = of_match_ptr(isl12026_dt_match),
+#endif





Should be better in the next version.

Thanks for the review,
David Daney

Re: [PATCH] rtc: isl12026: Add driver.

[David Daney]

and what? No recovery? No nothing except the message?


I will bail out of this setting or power handling if this happens, that 
seems like all that we could do.






+
+   requested_pwr = pwr;
+
+   if (set_bsw) {
+   if (bsw_val)
+   requested_pwr |= ISL12026_REG_PWR_BSW;
+   else
+   requested_pwr &= ~ISL12026_REG_PWR_BSW;
+   }
+   if (set_sbib) {
+   if (sbib_val)
+   requested_pwr |= ISL12026_REG_PWR_SBIB;
+   else
+   requested_pwr &= ~ISL12026_REG_PWR_SBIB;
+   }
+
+   if (pwr >= 0 && pwr != requested_pwr) {
+   dev_info(>dev, "PWR: %02x\n", pwr);
+   dev_info(>dev,
+"Updating PWR to: %02x\n", (u8)requested_pwr);
+   isl12026_write_reg(client,
+  ISL12026_REG_PWR, requested_pwr);
+   }
+   }


Can you refactor above to a separate function?


Done.




+   priv->rtc = devm_rtc_device_register(>dev, "rtc-isl12026",
+_rtc_ops, THIS_MODULE);



+


Redundant empty line.


+   ret = PTR_ERR_OR_ZERO(priv->rtc);
+   if (ret)
+   return ret;




+   if (IS_ENABLED(CONFIG_NVMEM)) {


I think you don't need this, see below.


+   priv->nvm_client = i2c_new_dummy(client->adapter, 0x57);
+   if (!priv->nvm_client)
+   return -ENOMEM;


i2c_new_secondary_device() ?


+   priv->nvm_dev = nvmem_register(>nvm_cfg);
+


Redundant empty line.


+   if (!priv->nvm_dev)


Should it be IS_ERR() ?


+   return -ENOMEM;


After all rtc_nvmem_register() ?



Yes, I switched to using that.




+   }
+   return 0;
+}
+
+static int isl12026_remove(struct i2c_client *client)
+{
+   struct isl12026 *priv = i2c_get_clientdata(client);
+



+   if (priv->nvm_dev)


How is it


+   nvmem_unregister(priv->nvm_dev);




+   if (priv->nvm_client)


Check with v4.16-rc1. This is duplicate check.


Yes.





+   i2c_unregister_device(priv->nvm_client);
+
+   return 0;
+}



+#ifdef CONFIG_OF


Useless.


+static const struct of_device_id isl12026_dt_match[] = {
+   { .compatible = "isil,isl12026" },
+   { },
+};
+MODULE_DEVICE_TABLE(of, isl12026_dt_match);
+#endif
+



+static const struct i2c_device_id isl12026_id[] = {
+   { "isl12026", 0 },
+   { }
+};
+MODULE_DEVICE_TABLE(i2c, isl12026_id);


Useless. Use ->probe_new() approach.


+#ifdef CONFIG_OF


Ugly and useless.


+   .of_match_table = of_match_ptr(isl12026_dt_match),
+#endif





Should be better in the next version.

Thanks for the review,
David Daney

Re: [PATCH] rtc: isl12026: Add driver.

[David Daney]

On 02/12/2018 10:59 AM, David Daney wrote:

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Signed-off-by: David Daney <david.da...@cavium.com>
---
  .../devicetree/bindings/rtc/isil,isl12026.txt  |  27 +
  drivers/rtc/Kconfig|   9 +
  drivers/rtc/Makefile   |   1 +
  drivers/rtc/rtc-isl12026.c | 550 +
  4 files changed, 587 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
  create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..4b6c7177a95a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,27 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {


Two seconds after sending, I see that the compatible went missing.

I will wait several days for feedback and resubmit with the proper 
compatible


Sorry for the snafu,
David Daney



+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }

Re: [PATCH] rtc: isl12026: Add driver.

[David Daney]

On 02/12/2018 10:59 AM, David Daney wrote:

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Signed-off-by: David Daney 
---
  .../devicetree/bindings/rtc/isil,isl12026.txt  |  27 +
  drivers/rtc/Kconfig|   9 +
  drivers/rtc/Makefile   |   1 +
  drivers/rtc/rtc-isl12026.c | 550 +
  4 files changed, 587 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
  create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..4b6c7177a95a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,27 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {


Two seconds after sending, I see that the compatible went missing.

I will wait several days for feedback and resubmit with the proper 
compatible


Sorry for the snafu,
David Daney



+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }

[PATCH] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Signed-off-by: David Daney <david.da...@cavium.com>
---
 .../devicetree/bindings/rtc/isil,isl12026.txt  |  27 +
 drivers/rtc/Kconfig|   9 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 550 +
 4 files changed, 587 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..4b6c7177a95a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,27 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8ab5f0a5d323..85171e9e3ada 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,15 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..a5f04e0faceb
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_SC0x30
+
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* ISL register bits */
+#define ISL12026_HR_MILBIT(7)  /* military or 24 hour time */
+
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_device *nvm_dev;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,
+* the write cycle to the nvmem takes many mS during which the
+* device does not respond to commands, so holding the lock
+* also prevents access during these times.
+*/
+   struct mutex lock;
+};
+
+static int isl12026_read_reg(struct i2c_client *client, int reg)
+{
+   struct isl12026 *priv = i2c_get_clientdata(client);
+   u8 addr[] = {0, reg};
+   u8 val;
+  

[PATCH] rtc: isl12026: Add driver.

[David Daney]

The ISL12026 is a combination RTC and EEPROM device with I2C
interface.  The standard RTC driver interface is provided.  The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.

Signed-off-by: David Daney 
---
 .../devicetree/bindings/rtc/isil,isl12026.txt  |  27 +
 drivers/rtc/Kconfig|   9 +
 drivers/rtc/Makefile   |   1 +
 drivers/rtc/rtc-isl12026.c | 550 +
 4 files changed, 587 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
 create mode 100644 drivers/rtc/rtc-isl12026.c

diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt 
b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index ..4b6c7177a95a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,27 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57.  The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+   value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+value for proper operation.
+
+
+Example:
+
+   rtc@6f {
+   reg = <0x6f>;
+   isil,pwr-bsw = <0>;
+   isil,pwr-sbib = <1>;
+   }
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8ab5f0a5d323..85171e9e3ada 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -407,6 +407,15 @@ config RTC_DRV_ISL12022
  This driver can also be built as a module. If so, the module
  will be called rtc-isl12022.
 
+config RTC_DRV_ISL12026
+   tristate "Intersil ISL12026"
+   help
+ If you say yes here you get support for the
+ Intersil ISL12026 RTC chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-isl12026.
+
 config RTC_DRV_X1205
tristate "Xicor/Intersil X1205"
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e45a7c..f481661a6eae 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
 obj-$(CONFIG_RTC_DRV_HYM8563)  += rtc-hym8563.o
 obj-$(CONFIG_RTC_DRV_IMXDI)+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
+obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o
 obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_LP8788)   += rtc-lp8788.o
diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c
new file mode 100644
index ..a5f04e0faceb
--- /dev/null
+++ b/drivers/rtc/rtc-isl12026.c
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * An I2C driver for the Intersil ISL 12026
+ *
+ * Copyright (c) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* register offsets */
+#define ISL12026_REG_SC0x30
+
+#define ISL12026_REG_SR0x3f
+# define ISL12026_REG_SR_RTCF  BIT(0)
+# define ISL12026_REG_SR_WEL   BIT(1)
+# define ISL12026_REG_SR_RWEL  BIT(2)
+# define ISL12026_REG_SR_MBZ   BIT(3)
+# define ISL12026_REG_SR_OSCF  BIT(4)
+
+/* ISL register bits */
+#define ISL12026_HR_MILBIT(7)  /* military or 24 hour time */
+
+#define ISL12026_REG_PWR   0x14
+# define ISL12026_REG_PWR_BSW  BIT(6)
+# define ISL12026_REG_PWR_SBIB BIT(7)
+
+#define ISL12026_PAGESIZE 16
+#define ISL12026_NVMEM_WRITE_TIME 20
+
+struct isl12026 {
+   struct rtc_device *rtc;
+   struct i2c_client *nvm_client;
+   struct nvmem_device *nvm_dev;
+   struct nvmem_config nvm_cfg;
+   /*
+* RTC write operations require that multiple messages be
+* transmitted, we hold the lock for all accesses to the
+* device so that these sequences cannot be disrupted.  Also,
+* the write cycle to the nvmem takes many mS during which the
+* device does not respond to commands, so holding the lock
+* also prevents access during these times.
+*/
+   struct mutex lock;
+};
+
+static int isl12026_read_reg(struct i2c_client *client, int reg)
+{
+   struct isl12026 *priv = i2c_get_clientdata(client);
+   u8 addr[] = {0, reg};
+   u8 val;
+   int ret;
+
+   struct i2c_msg msgs

Re: [PATCH 1/2] MIPS: Watch: Avoid duplication of bits in mips_install_watch_registers.

[David Daney]

On 01/02/2018 03:31 AM, Matt Redfearn wrote:

Currently the bits to be set in the watchhi register in addition to that
requested by the user is defined inline for each register. To avoid
this, define the bits once and or that in for each register.

Signed-off-by: Matt Redfearn <matt.redfe...@mips.com>


Looks like a good cleanup/simplification...

Acked-by: David Daney <david.da...@cavium.com>


---

  arch/mips/kernel/watch.c | 17 +++--
  1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index 19fcab7348b1..329d2209521d 100644
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -18,27 +18,24 @@
  void mips_install_watch_registers(struct task_struct *t)
  {
struct mips3264_watch_reg_state *watches = >thread.watch.mips3264;
+   unsigned int watchhi = MIPS_WATCHHI_G | /* Trap all ASIDs */
+  MIPS_WATCHHI_IRW;/* Clear result bits */
+
switch (current_cpu_data.watch_reg_use_cnt) {
default:
BUG();
case 4:
write_c0_watchlo3(watches->watchlo[3]);
-   /* Write 1 to the I, R, and W bits to clear them, and
-  1 to G so all ASIDs are trapped. */
-   write_c0_watchhi3(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
- watches->watchhi[3]);
+   write_c0_watchhi3(watchhi | watches->watchhi[3]);
case 3:
write_c0_watchlo2(watches->watchlo[2]);
-   write_c0_watchhi2(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
- watches->watchhi[2]);
+   write_c0_watchhi2(watchhi | watches->watchhi[2]);
case 2:
write_c0_watchlo1(watches->watchlo[1]);
-   write_c0_watchhi1(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
- watches->watchhi[1]);
+   write_c0_watchhi1(watchhi | watches->watchhi[1]);
case 1:
write_c0_watchlo0(watches->watchlo[0]);
-   write_c0_watchhi0(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
- watches->watchhi[0]);
+   write_c0_watchhi0(watchhi | watches->watchhi[0]);
}
  }
  

Re: [PATCH 2/2] MIPS: Watch: Avoid duplication of bits in mips_read_watch_registers

[David Daney]

On 01/02/2018 03:31 AM, Matt Redfearn wrote:

Currently the bits to be masked when watchhi is read is defined inline
for each register. To avoid this, define the bits once and mask each
register with that value.

Signed-off-by: Matt Redfearn <matt.redfe...@mips.com>


Acked-by: David Daney <david.da...@cavium.com>



---

  arch/mips/kernel/watch.c | 14 ++
  1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index 329d2209521d..0e61a5b7647f 100644
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -48,21 +48,19 @@ void mips_read_watch_registers(void)
  {
struct mips3264_watch_reg_state *watches =
>thread.watch.mips3264;
+   unsigned int watchhi_mask = MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW;
+
switch (current_cpu_data.watch_reg_use_cnt) {
default:
BUG();
case 4:
-   watches->watchhi[3] = (read_c0_watchhi3() &
-  (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+   watches->watchhi[3] = (read_c0_watchhi3() & watchhi_mask);
case 3:
-   watches->watchhi[2] = (read_c0_watchhi2() &
-  (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+   watches->watchhi[2] = (read_c0_watchhi2() & watchhi_mask);
case 2:
-   watches->watchhi[1] = (read_c0_watchhi1() &
-  (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+   watches->watchhi[1] = (read_c0_watchhi1() & watchhi_mask);
case 1:
-   watches->watchhi[0] = (read_c0_watchhi0() &
-  (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+   watches->watchhi[0] = (read_c0_watchhi0() & watchhi_mask);
}
if (current_cpu_data.watch_reg_use_cnt == 1 &&
(watches->watchhi[0] & MIPS_WATCHHI_IRW) == 0) {

Re: [PATCH 1/2] MIPS: Watch: Avoid duplication of bits in mips_install_watch_registers.

[David Daney]

On 01/02/2018 03:31 AM, Matt Redfearn wrote:

Currently the bits to be set in the watchhi register in addition to that
requested by the user is defined inline for each register. To avoid
this, define the bits once and or that in for each register.

Signed-off-by: Matt Redfearn 


Looks like a good cleanup/simplification...

Acked-by: David Daney 


---

  arch/mips/kernel/watch.c | 17 +++--
  1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index 19fcab7348b1..329d2209521d 100644
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -18,27 +18,24 @@
  void mips_install_watch_registers(struct task_struct *t)
  {
struct mips3264_watch_reg_state *watches = >thread.watch.mips3264;
+   unsigned int watchhi = MIPS_WATCHHI_G | /* Trap all ASIDs */
+  MIPS_WATCHHI_IRW;/* Clear result bits */
+
switch (current_cpu_data.watch_reg_use_cnt) {
default:
BUG();
case 4:
write_c0_watchlo3(watches->watchlo[3]);
-   /* Write 1 to the I, R, and W bits to clear them, and
-  1 to G so all ASIDs are trapped. */
-   write_c0_watchhi3(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
- watches->watchhi[3]);
+   write_c0_watchhi3(watchhi | watches->watchhi[3]);
case 3:
write_c0_watchlo2(watches->watchlo[2]);
-   write_c0_watchhi2(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
- watches->watchhi[2]);
+   write_c0_watchhi2(watchhi | watches->watchhi[2]);
case 2:
write_c0_watchlo1(watches->watchlo[1]);
-   write_c0_watchhi1(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
- watches->watchhi[1]);
+   write_c0_watchhi1(watchhi | watches->watchhi[1]);
case 1:
write_c0_watchlo0(watches->watchlo[0]);
-   write_c0_watchhi0(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
- watches->watchhi[0]);
+   write_c0_watchhi0(watchhi | watches->watchhi[0]);
}
  }
  

Re: [PATCH 2/2] MIPS: Watch: Avoid duplication of bits in mips_read_watch_registers

[David Daney]

On 01/02/2018 03:31 AM, Matt Redfearn wrote:

Currently the bits to be masked when watchhi is read is defined inline
for each register. To avoid this, define the bits once and mask each
register with that value.

Signed-off-by: Matt Redfearn 


Acked-by: David Daney 



---

  arch/mips/kernel/watch.c | 14 ++
  1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index 329d2209521d..0e61a5b7647f 100644
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -48,21 +48,19 @@ void mips_read_watch_registers(void)
  {
struct mips3264_watch_reg_state *watches =
>thread.watch.mips3264;
+   unsigned int watchhi_mask = MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW;
+
switch (current_cpu_data.watch_reg_use_cnt) {
default:
BUG();
case 4:
-   watches->watchhi[3] = (read_c0_watchhi3() &
-  (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+   watches->watchhi[3] = (read_c0_watchhi3() & watchhi_mask);
case 3:
-   watches->watchhi[2] = (read_c0_watchhi2() &
-  (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+   watches->watchhi[2] = (read_c0_watchhi2() & watchhi_mask);
case 2:
-   watches->watchhi[1] = (read_c0_watchhi1() &
-  (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+   watches->watchhi[1] = (read_c0_watchhi1() & watchhi_mask);
case 1:
-   watches->watchhi[0] = (read_c0_watchhi0() &
-  (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+   watches->watchhi[0] = (read_c0_watchhi0() & watchhi_mask);
}
if (current_cpu_data.watch_reg_use_cnt == 1 &&
(watches->watchhi[0] & MIPS_WATCHHI_IRW) == 0) {

[PATCH v7 2/4] MIPS: Octeon: Automatically provision CVMSEG space.

[David Daney]

Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.

1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE

New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.

Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Carlos Munoz <cmu...@caviumnetworks.com>
---
 arch/mips/cavium-octeon/Kconfig| 27 
 arch/mips/cavium-octeon/setup.c| 16 ++--
 .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +--
 arch/mips/include/asm/mipsregs.h   |  2 ++
 arch/mips/include/asm/octeon/octeon.h  |  2 ++
 arch/mips/include/asm/processor.h  |  2 +-
 arch/mips/kernel/octeon_switch.S   |  2 --
 arch/mips/mm/tlbex.c   | 29 ++
 drivers/staging/octeon/ethernet-defines.h  |  2 +-
 9 files changed, 50 insertions(+), 52 deletions(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 204a1670fd9b..a50d1aa5863b 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -11,21 +11,26 @@ config CAVIUM_CN63XXP1
  non-CN63XXP1 hardware, so it is recommended to select "n"
  unless it is known the workarounds are needed.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-   int "Number of L1 cache lines reserved for CVMSEG memory"
-   range 0 54
-   default 1
-   help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
 
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+   int "Number of extra L1 cache lines reserved for CVMSEG memory"
+   range 0 50
+   default 0
+   help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is.  The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
 config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68bc652..51c4d3c3cada 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
 static unsigned long long max_memory = ULLONG_MAX;
 static unsigned long long reserve_low_mem;
 
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 EXPORT_SYMBOL(octeon_bootbus_sem);
 
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
 
/* R/W If set, CVMSEG is available for loads/stores in
 * kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
-   cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
 
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
-   pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+   pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
 
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38ce5a3d..cdcca60978a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+   mfc0v1, CP0_PRID_REG
+   andiv1, 0xff00

[PATCH v7 2/4] MIPS: Octeon: Automatically provision CVMSEG space.

[David Daney]

Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.

1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE

New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.

Signed-off-by: David Daney 
Signed-off-by: Carlos Munoz 
---
 arch/mips/cavium-octeon/Kconfig| 27 
 arch/mips/cavium-octeon/setup.c| 16 ++--
 .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +--
 arch/mips/include/asm/mipsregs.h   |  2 ++
 arch/mips/include/asm/octeon/octeon.h  |  2 ++
 arch/mips/include/asm/processor.h  |  2 +-
 arch/mips/kernel/octeon_switch.S   |  2 --
 arch/mips/mm/tlbex.c   | 29 ++
 drivers/staging/octeon/ethernet-defines.h  |  2 +-
 9 files changed, 50 insertions(+), 52 deletions(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 204a1670fd9b..a50d1aa5863b 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -11,21 +11,26 @@ config CAVIUM_CN63XXP1
  non-CN63XXP1 hardware, so it is recommended to select "n"
  unless it is known the workarounds are needed.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-   int "Number of L1 cache lines reserved for CVMSEG memory"
-   range 0 54
-   default 1
-   help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
 
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+   int "Number of extra L1 cache lines reserved for CVMSEG memory"
+   range 0 50
+   default 0
+   help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is.  The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
 config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68bc652..51c4d3c3cada 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
 static unsigned long long max_memory = ULLONG_MAX;
 static unsigned long long reserve_low_mem;
 
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 EXPORT_SYMBOL(octeon_bootbus_sem);
 
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
 
/* R/W If set, CVMSEG is available for loads/stores in
 * kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
-   cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
 
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
-   pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+   pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
 
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38ce5a3d..cdcca60978a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+   mfc0v1, CP0_PRID_REG
+   andiv1, 0xff00
+   li  v0, 0x9500   

[PATCH v7 1/4] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
  (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
  (up to 128) of data to the I/O device and then return a
  variable length (up to 128 bytes) response from the I/O device.

For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.

Reviewed-by: James Hogan <jho...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/setup.c   |  6 ++
 arch/mips/include/asm/octeon/octeon.h | 12 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
 #else
cvmmemctl.s.cvmsegenak = 0;
 #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;
+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
 };
 
-- 
2.14.3

[PATCH v7 4/4] MIPS: Octeon: Add a global resource manager.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/include/asm/octeon/octeon.h  |  18 ++
 3 files changed, 370 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..28c0bb75d1a4 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -10,6 +10,7 @@
 #
 
 obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y += resource-mgr.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..74efda5420ff
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   while (cmpxchg(_mgr_info->rlock, 0, 1))
+   ; /* Loop while not zero */
+   rmb();
+}
+
+static void res_mgr_unlock(void)
+{
+   /* Wait until all resource operations finish before unlocking. */
+   wmb();
+   WRITE_ONCE(res_mgr_info->rlock, 0);
+   /* Force a write buffer flush. */
+   wmb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource() - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source was created successfully.
+ * Returns < 0 for error codes.
+ */
+int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt)
+{
+   struct global_resource_entry *res_entry;
+   u64 size;
+   u64 *res_addr;
+   int res_index, i, rc = 0;
+
+   res_mgr_lock();
+
+   /* Make sure resource doesn't already exist. */
+   res_index = res_mgr_find_resource(tag);
+   if (res_index >= 0) {
+   rc = -EEXIST;
+   goto err;
+   }
+
+   if (res_mgr_info->entry_cnt >= MAX_RESOURCES) {
+   pr_err("Resource max limit reached, not created\n");
+   rc = -ENOSPC;
+   goto err;
+   }
+
+   /*
+* Each instance is kept in an array of u64s. The first array element
+* holds the number of allocated instances.
+*/
+   size = sizeof(u64) * (inst_cnt + 1);
+   res_addr = cvmx_bootmem_alloc_range(size, CVMX_CACHE_LINE_SIZE, 0, 0);
+   if (!res_addr) {
+   pr_err("Failed to allocate resource. not created\n");
+   rc = -ENOMEM;
+   goto err;
+   }
+
+   /* Initialize the newly created resource. */
+   *res_addr = inst_cnt;
+   for (i = 1; i <= inst_cnt; i++)
+   res_addr[i] = INST_AVAILABLE;
+
+   res_index = res_mgr_info->entry_cnt;
+   res_entry = _mgr_info->resource_entry[res_index];
+   res_entry->tag = tag;
+   res_entry->phys_addr = virt_to_phys(res_addr);
+   res_entry->size = size;
+   res_mgr_in

[PATCH v7 1/4] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

From: Carlos Munoz 

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
  (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
  (up to 128) of data to the I/O device and then return a
  variable length (up to 128 bytes) response from the I/O device.

For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.

Reviewed-by: James Hogan 
Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 arch/mips/cavium-octeon/setup.c   |  6 ++
 arch/mips/include/asm/octeon/octeon.h | 12 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
 #else
cvmmemctl.s.cvmsegenak = 0;
 #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;
+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
 };
 
-- 
2.14.3

[PATCH v7 4/4] MIPS: Octeon: Add a global resource manager.

[David Daney]

From: Carlos Munoz 

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/include/asm/octeon/octeon.h  |  18 ++
 3 files changed, 370 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..28c0bb75d1a4 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -10,6 +10,7 @@
 #
 
 obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y += resource-mgr.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..74efda5420ff
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   while (cmpxchg(_mgr_info->rlock, 0, 1))
+   ; /* Loop while not zero */
+   rmb();
+}
+
+static void res_mgr_unlock(void)
+{
+   /* Wait until all resource operations finish before unlocking. */
+   wmb();
+   WRITE_ONCE(res_mgr_info->rlock, 0);
+   /* Force a write buffer flush. */
+   wmb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource() - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source was created successfully.
+ * Returns < 0 for error codes.
+ */
+int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt)
+{
+   struct global_resource_entry *res_entry;
+   u64 size;
+   u64 *res_addr;
+   int res_index, i, rc = 0;
+
+   res_mgr_lock();
+
+   /* Make sure resource doesn't already exist. */
+   res_index = res_mgr_find_resource(tag);
+   if (res_index >= 0) {
+   rc = -EEXIST;
+   goto err;
+   }
+
+   if (res_mgr_info->entry_cnt >= MAX_RESOURCES) {
+   pr_err("Resource max limit reached, not created\n");
+   rc = -ENOSPC;
+   goto err;
+   }
+
+   /*
+* Each instance is kept in an array of u64s. The first array element
+* holds the number of allocated instances.
+*/
+   size = sizeof(u64) * (inst_cnt + 1);
+   res_addr = cvmx_bootmem_alloc_range(size, CVMX_CACHE_LINE_SIZE, 0, 0);
+   if (!res_addr) {
+   pr_err("Failed to allocate resource. not created\n");
+   rc = -ENOMEM;
+   goto err;
+   }
+
+   /* Initialize the newly created resource. */
+   *res_addr = inst_cnt;
+   for (i = 1; i <= inst_cnt; i++)
+   res_addr[i] = INST_AVAILABLE;
+
+   res_index = res_mgr_info->entry_cnt;
+   res_entry = _mgr_info->resource_entry[res_index];
+   res_entry->tag = tag;
+   res_entry->phys_addr = virt_to_phys(res_addr);
+   res_entry->size = size;
+   res_mgr_info->entry_cnt++;
+
+err:
+   res_mgr_unlock();
+
+   return rc;
+}
+EXPORT_SYMBOL(res_mgr_create_resource);
+
+

[PATCH v7 0/4] Prerequisites for Cavium OCTEON-III network driver.

[David Daney]

We want to add the Cavium OCTEON-III network driver.  But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code.  Aren't SoCs nice in this way?  These are the
prerequisite patches that are needed before the network driver can be
merged.

Changes in v7:

o Splitting of the patch set only.  These 4 mips patches are unchanged
  from the previous posting.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs (in
  the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (2):
  MIPS: Octeon: Enable LMTDMA/LMTST operations.
  MIPS: Octeon: Add a global resource manager.

David Daney (2):
  MIPS: Octeon: Automatically provision CVMSEG space.
  staging: octeon: Remove USE_ASYNC_IOBDMA macro.

 arch/mips/cavium-octeon/Kconfig|  27 +-
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/cavium-octeon/setup.c|  22 +-
 .../asm/mach-cavium-octeon/kernel-entry-init.h |  20 +-
 arch/mips/include/asm/mipsregs.h   |   2 +
 arch/mips/include/asm/octeon/octeon.h  |  32 +-
 arch/mips/include/asm/processor.h  |   2 +-
 arch/mips/kernel/octeon_switch.S   |   2 -
 arch/mips/mm/tlbex.c   |  29 +-
 drivers/staging/octeon/ethernet-defines.h  |   6 -
 drivers/staging/octeon/ethernet-rx.c   |  25 +-
 drivers/staging/octeon/ethernet-tx.c   |  85 ++---
 13 files changed, 472 insertions(+), 132 deletions(-)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

-- 
2.14.3

[PATCH v7 0/4] Prerequisites for Cavium OCTEON-III network driver.

[David Daney]

We want to add the Cavium OCTEON-III network driver.  But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code.  Aren't SoCs nice in this way?  These are the
prerequisite patches that are needed before the network driver can be
merged.

Changes in v7:

o Splitting of the patch set only.  These 4 mips patches are unchanged
  from the previous posting.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs (in
  the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (2):
  MIPS: Octeon: Enable LMTDMA/LMTST operations.
  MIPS: Octeon: Add a global resource manager.

David Daney (2):
  MIPS: Octeon: Automatically provision CVMSEG space.
  staging: octeon: Remove USE_ASYNC_IOBDMA macro.

 arch/mips/cavium-octeon/Kconfig|  27 +-
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/cavium-octeon/setup.c|  22 +-
 .../asm/mach-cavium-octeon/kernel-entry-init.h |  20 +-
 arch/mips/include/asm/mipsregs.h   |   2 +
 arch/mips/include/asm/octeon/octeon.h  |  32 +-
 arch/mips/include/asm/processor.h  |   2 +-
 arch/mips/kernel/octeon_switch.S   |   2 -
 arch/mips/mm/tlbex.c   |  29 +-
 drivers/staging/octeon/ethernet-defines.h  |   6 -
 drivers/staging/octeon/ethernet-rx.c   |  25 +-
 drivers/staging/octeon/ethernet-tx.c   |  85 ++---
 13 files changed, 472 insertions(+), 132 deletions(-)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

-- 
2.14.3

[PATCH v7 3/4] staging: octeon: Remove USE_ASYNC_IOBDMA macro.

[David Daney]

Previous patch sets USE_ASYNC_IOBDMA to 1 unconditionally.  Remove
USE_ASYNC_IOBDMA from all if statements.  Remove dead code caused by
the change.

Acked-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 drivers/staging/octeon/ethernet-defines.h |  6 ---
 drivers/staging/octeon/ethernet-rx.c  | 25 -
 drivers/staging/octeon/ethernet-tx.c  | 85 ++-
 3 files changed, 37 insertions(+), 79 deletions(-)

diff --git a/drivers/staging/octeon/ethernet-defines.h 
b/drivers/staging/octeon/ethernet-defines.h
index e898df25b87f..21438c804a43 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -10,10 +10,6 @@
 
 /*
  * A few defines are used to control the operation of this driver:
- *  USE_ASYNC_IOBDMA
- *  Use asynchronous IO access to hardware. This uses Octeon's asynchronous
- *  IOBDMAs to issue IO accesses without stalling. Set this to zero
- *  to disable this. Note that IOBDMAs require CVMSEG.
  *  REUSE_SKBUFFS_WITHOUT_FREE
  *  Allows the TX path to free an skbuff into the FPA hardware pool. This
  *  can significantly improve performance for forwarding and bridging, but
@@ -32,8 +28,6 @@
 #define REUSE_SKBUFFS_WITHOUT_FREE  1
 #endif
 
-#define USE_ASYNC_IOBDMA   1
-
 /* Maximum number of SKBs to try to free per xmit packet. */
 #define MAX_OUT_QUEUE_DEPTH 1000
 
diff --git a/drivers/staging/octeon/ethernet-rx.c 
b/drivers/staging/octeon/ethernet-rx.c
index 1a44291318ee..dd76c99d5ae0 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -201,11 +201,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
/* Prefetch cvm_oct_device since we know we need it soon */
prefetch(cvm_oct_device);
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   }
+   /* Save scratch in case userspace is using it */
+   CVMX_SYNCIOBDMA;
+   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
 
/* Only allow work for our group (and preserve priorities) */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -220,10 +218,8 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
   BIT(rx_group->group));
}
 
-   if (USE_ASYNC_IOBDMA) {
-   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
-   did_work_request = 1;
-   }
+   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+   did_work_request = 1;
 
while (rx_count < budget) {
struct sk_buff *skb = NULL;
@@ -232,7 +228,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_wqe_t *work;
int port;
 
-   if (USE_ASYNC_IOBDMA && did_work_request)
+   if (did_work_request)
work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
else
work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
@@ -260,7 +256,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
sizeof(void *));
prefetch(pskb);
 
-   if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
+   if (rx_count < (budget - 1)) {
cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH,
CVMX_POW_NO_WAIT);
did_work_request = 1;
@@ -403,10 +399,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Restore the scratch area */
-   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
-   }
+   /* Restore the scratch area */
+   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+
cvm_oct_rx_refill_pool(0);
 
return rx_count;
diff --git a/drivers/staging/octeon/ethernet-tx.c 
b/drivers/staging/octeon/ethernet-tx.c
index 31f35025d19e..2eede0907924 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -179,23 +179,18 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device 
*dev)
qos = 0;
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
-
-   /*
-* Fetch and increment the number o

[PATCH v7 3/4] staging: octeon: Remove USE_ASYNC_IOBDMA macro.

[David Daney]

Previous patch sets USE_ASYNC_IOBDMA to 1 unconditionally.  Remove
USE_ASYNC_IOBDMA from all if statements.  Remove dead code caused by
the change.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: David Daney 
---
 drivers/staging/octeon/ethernet-defines.h |  6 ---
 drivers/staging/octeon/ethernet-rx.c  | 25 -
 drivers/staging/octeon/ethernet-tx.c  | 85 ++-
 3 files changed, 37 insertions(+), 79 deletions(-)

diff --git a/drivers/staging/octeon/ethernet-defines.h 
b/drivers/staging/octeon/ethernet-defines.h
index e898df25b87f..21438c804a43 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -10,10 +10,6 @@
 
 /*
  * A few defines are used to control the operation of this driver:
- *  USE_ASYNC_IOBDMA
- *  Use asynchronous IO access to hardware. This uses Octeon's asynchronous
- *  IOBDMAs to issue IO accesses without stalling. Set this to zero
- *  to disable this. Note that IOBDMAs require CVMSEG.
  *  REUSE_SKBUFFS_WITHOUT_FREE
  *  Allows the TX path to free an skbuff into the FPA hardware pool. This
  *  can significantly improve performance for forwarding and bridging, but
@@ -32,8 +28,6 @@
 #define REUSE_SKBUFFS_WITHOUT_FREE  1
 #endif
 
-#define USE_ASYNC_IOBDMA   1
-
 /* Maximum number of SKBs to try to free per xmit packet. */
 #define MAX_OUT_QUEUE_DEPTH 1000
 
diff --git a/drivers/staging/octeon/ethernet-rx.c 
b/drivers/staging/octeon/ethernet-rx.c
index 1a44291318ee..dd76c99d5ae0 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -201,11 +201,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
/* Prefetch cvm_oct_device since we know we need it soon */
prefetch(cvm_oct_device);
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   }
+   /* Save scratch in case userspace is using it */
+   CVMX_SYNCIOBDMA;
+   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
 
/* Only allow work for our group (and preserve priorities) */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -220,10 +218,8 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
   BIT(rx_group->group));
}
 
-   if (USE_ASYNC_IOBDMA) {
-   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
-   did_work_request = 1;
-   }
+   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+   did_work_request = 1;
 
while (rx_count < budget) {
struct sk_buff *skb = NULL;
@@ -232,7 +228,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_wqe_t *work;
int port;
 
-   if (USE_ASYNC_IOBDMA && did_work_request)
+   if (did_work_request)
work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
else
work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
@@ -260,7 +256,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
sizeof(void *));
prefetch(pskb);
 
-   if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
+   if (rx_count < (budget - 1)) {
cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH,
CVMX_POW_NO_WAIT);
did_work_request = 1;
@@ -403,10 +399,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Restore the scratch area */
-   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
-   }
+   /* Restore the scratch area */
+   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+
cvm_oct_rx_refill_pool(0);
 
return rx_count;
diff --git a/drivers/staging/octeon/ethernet-tx.c 
b/drivers/staging/octeon/ethernet-tx.c
index 31f35025d19e..2eede0907924 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -179,23 +179,18 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device 
*dev)
qos = 0;
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
-
-   /*
-* Fetch and increment the number of packets to be
-* freed.
-*/
-   cv

[PATCH v6 net-next,mips 3/7] MIPS: Octeon: Automatically provision CVMSEG space.

[David Daney]

Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.

1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE

New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.

Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Carlos Munoz <cmu...@caviumnetworks.com>
---
 arch/mips/cavium-octeon/Kconfig| 27 
 arch/mips/cavium-octeon/setup.c| 16 ++--
 .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +--
 arch/mips/include/asm/mipsregs.h   |  2 ++
 arch/mips/include/asm/octeon/octeon.h  |  2 ++
 arch/mips/include/asm/processor.h  |  2 +-
 arch/mips/kernel/octeon_switch.S   |  2 --
 arch/mips/mm/tlbex.c   | 29 ++
 drivers/staging/octeon/ethernet-defines.h  |  2 +-
 9 files changed, 50 insertions(+), 52 deletions(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 204a1670fd9b..a50d1aa5863b 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -11,21 +11,26 @@ config CAVIUM_CN63XXP1
  non-CN63XXP1 hardware, so it is recommended to select "n"
  unless it is known the workarounds are needed.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-   int "Number of L1 cache lines reserved for CVMSEG memory"
-   range 0 54
-   default 1
-   help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
 
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+   int "Number of extra L1 cache lines reserved for CVMSEG memory"
+   range 0 50
+   default 0
+   help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is.  The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
 config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68bc652..51c4d3c3cada 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
 static unsigned long long max_memory = ULLONG_MAX;
 static unsigned long long reserve_low_mem;
 
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 EXPORT_SYMBOL(octeon_bootbus_sem);
 
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
 
/* R/W If set, CVMSEG is available for loads/stores in
 * kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
-   cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
 
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
-   pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+   pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
 
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38ce5a3d..cdcca60978a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+   mfc0v1, CP0_PRID_REG
+   andiv1, 0xff00

[PATCH v6 net-next,mips 3/7] MIPS: Octeon: Automatically provision CVMSEG space.

[David Daney]

Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.

1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE

New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.

Signed-off-by: David Daney 
Signed-off-by: Carlos Munoz 
---
 arch/mips/cavium-octeon/Kconfig| 27 
 arch/mips/cavium-octeon/setup.c| 16 ++--
 .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +--
 arch/mips/include/asm/mipsregs.h   |  2 ++
 arch/mips/include/asm/octeon/octeon.h  |  2 ++
 arch/mips/include/asm/processor.h  |  2 +-
 arch/mips/kernel/octeon_switch.S   |  2 --
 arch/mips/mm/tlbex.c   | 29 ++
 drivers/staging/octeon/ethernet-defines.h  |  2 +-
 9 files changed, 50 insertions(+), 52 deletions(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 204a1670fd9b..a50d1aa5863b 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -11,21 +11,26 @@ config CAVIUM_CN63XXP1
  non-CN63XXP1 hardware, so it is recommended to select "n"
  unless it is known the workarounds are needed.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-   int "Number of L1 cache lines reserved for CVMSEG memory"
-   range 0 54
-   default 1
-   help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
 
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+   int "Number of extra L1 cache lines reserved for CVMSEG memory"
+   range 0 50
+   default 0
+   help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is.  The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
 config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68bc652..51c4d3c3cada 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
 static unsigned long long max_memory = ULLONG_MAX;
 static unsigned long long reserve_low_mem;
 
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 EXPORT_SYMBOL(octeon_bootbus_sem);
 
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
 
/* R/W If set, CVMSEG is available for loads/stores in
 * kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
-   cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
 
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
-   pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+   pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
 
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38ce5a3d..cdcca60978a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+   mfc0v1, CP0_PRID_REG
+   andiv1, 0xff00
+   li  v0, 0x9500   

[PATCH v6 net-next,mips 1/7] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

Add bindings for Common Ethernet Interface (BGX) block.

Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 .../devicetree/bindings/net/cavium-bgx.txt | 61 ++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index ..830c5f08
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,61 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+A BGX block has several children, each representing an Ethernet
+interface.
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all
+ cn7xxx SOCs.
+
+ "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs
+ for RGMII.
+
+- reg: The index of the interface within the BGX block.
+
+Optional properties:
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- phy-mode: described in ethernet.txt.
+
+- fixed-link: described in fixed-link.txt.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet@0 {
+   compatible = "cavium,octeon-7360-xcv";
+   reg = <0>;
+   local-mac-address = [ 00 01 23 45 67 89 ];
+   phy-handle = <>;
+   phy-mode = "rgmii-rxid"
+   };
+   ethernet@1 {
+   compatible = "cavium,octeon-7890-bgx-port";
+   reg = <1>;
+   local-mac-address = [ 00 01 23 45 67 8a ];
+   phy-handle = <>;
+   phy-mode = "sgmii"
+   };
+   };
-- 
2.14.3

[PATCH v6 net-next,mips 1/7] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[David Daney]

From: Carlos Munoz 

Add bindings for Common Ethernet Interface (BGX) block.

Acked-by: Rob Herring 
Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 .../devicetree/bindings/net/cavium-bgx.txt | 61 ++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index ..830c5f08
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,61 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+A BGX block has several children, each representing an Ethernet
+interface.
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all
+ cn7xxx SOCs.
+
+ "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs
+ for RGMII.
+
+- reg: The index of the interface within the BGX block.
+
+Optional properties:
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- phy-mode: described in ethernet.txt.
+
+- fixed-link: described in fixed-link.txt.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet@0 {
+   compatible = "cavium,octeon-7360-xcv";
+   reg = <0>;
+   local-mac-address = [ 00 01 23 45 67 89 ];
+   phy-handle = <>;
+   phy-mode = "rgmii-rxid"
+   };
+   ethernet@1 {
+   compatible = "cavium,octeon-7890-bgx-port";
+   reg = <1>;
+   local-mac-address = [ 00 01 23 45 67 8a ];
+   phy-handle = <>;
+   phy-mode = "sgmii"
+   };
+   };
-- 
2.14.3

[PATCH v6 net-next,mips 5/7] MIPS: Octeon: Add a global resource manager.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/include/asm/octeon/octeon.h  |  18 ++
 3 files changed, 370 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..28c0bb75d1a4 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -10,6 +10,7 @@
 #
 
 obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y += resource-mgr.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..74efda5420ff
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   while (cmpxchg(_mgr_info->rlock, 0, 1))
+   ; /* Loop while not zero */
+   rmb();
+}
+
+static void res_mgr_unlock(void)
+{
+   /* Wait until all resource operations finish before unlocking. */
+   wmb();
+   WRITE_ONCE(res_mgr_info->rlock, 0);
+   /* Force a write buffer flush. */
+   wmb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource() - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source was created successfully.
+ * Returns < 0 for error codes.
+ */
+int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt)
+{
+   struct global_resource_entry *res_entry;
+   u64 size;
+   u64 *res_addr;
+   int res_index, i, rc = 0;
+
+   res_mgr_lock();
+
+   /* Make sure resource doesn't already exist. */
+   res_index = res_mgr_find_resource(tag);
+   if (res_index >= 0) {
+   rc = -EEXIST;
+   goto err;
+   }
+
+   if (res_mgr_info->entry_cnt >= MAX_RESOURCES) {
+   pr_err("Resource max limit reached, not created\n");
+   rc = -ENOSPC;
+   goto err;
+   }
+
+   /*
+* Each instance is kept in an array of u64s. The first array element
+* holds the number of allocated instances.
+*/
+   size = sizeof(u64) * (inst_cnt + 1);
+   res_addr = cvmx_bootmem_alloc_range(size, CVMX_CACHE_LINE_SIZE, 0, 0);
+   if (!res_addr) {
+   pr_err("Failed to allocate resource. not created\n");
+   rc = -ENOMEM;
+   goto err;
+   }
+
+   /* Initialize the newly created resource. */
+   *res_addr = inst_cnt;
+   for (i = 1; i <= inst_cnt; i++)
+   res_addr[i] = INST_AVAILABLE;
+
+   res_index = res_mgr_info->entry_cnt;
+   res_entry = _mgr_info->resource_entry[res_index];
+   res_entry->tag = tag;
+   res_entry->phys_addr = virt_to_phys(res_addr);
+   res_entry->size = size;
+   res_mgr_in

[PATCH v6 net-next,mips 5/7] MIPS: Octeon: Add a global resource manager.

[David Daney]

From: Carlos Munoz 

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/include/asm/octeon/octeon.h  |  18 ++
 3 files changed, 370 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..28c0bb75d1a4 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -10,6 +10,7 @@
 #
 
 obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y += resource-mgr.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..74efda5420ff
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   while (cmpxchg(_mgr_info->rlock, 0, 1))
+   ; /* Loop while not zero */
+   rmb();
+}
+
+static void res_mgr_unlock(void)
+{
+   /* Wait until all resource operations finish before unlocking. */
+   wmb();
+   WRITE_ONCE(res_mgr_info->rlock, 0);
+   /* Force a write buffer flush. */
+   wmb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource() - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source was created successfully.
+ * Returns < 0 for error codes.
+ */
+int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt)
+{
+   struct global_resource_entry *res_entry;
+   u64 size;
+   u64 *res_addr;
+   int res_index, i, rc = 0;
+
+   res_mgr_lock();
+
+   /* Make sure resource doesn't already exist. */
+   res_index = res_mgr_find_resource(tag);
+   if (res_index >= 0) {
+   rc = -EEXIST;
+   goto err;
+   }
+
+   if (res_mgr_info->entry_cnt >= MAX_RESOURCES) {
+   pr_err("Resource max limit reached, not created\n");
+   rc = -ENOSPC;
+   goto err;
+   }
+
+   /*
+* Each instance is kept in an array of u64s. The first array element
+* holds the number of allocated instances.
+*/
+   size = sizeof(u64) * (inst_cnt + 1);
+   res_addr = cvmx_bootmem_alloc_range(size, CVMX_CACHE_LINE_SIZE, 0, 0);
+   if (!res_addr) {
+   pr_err("Failed to allocate resource. not created\n");
+   rc = -ENOMEM;
+   goto err;
+   }
+
+   /* Initialize the newly created resource. */
+   *res_addr = inst_cnt;
+   for (i = 1; i <= inst_cnt; i++)
+   res_addr[i] = INST_AVAILABLE;
+
+   res_index = res_mgr_info->entry_cnt;
+   res_entry = _mgr_info->resource_entry[res_index];
+   res_entry->tag = tag;
+   res_entry->phys_addr = virt_to_phys(res_addr);
+   res_entry->size = size;
+   res_mgr_info->entry_cnt++;
+
+err:
+   res_mgr_unlock();
+
+   return rc;
+}
+EXPORT_SYMBOL(res_mgr_create_resource);
+
+

[PATCH v6 net-next,mips 2/7] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
  (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
  (up to 128) of data to the I/O device and then return a
  variable length (up to 128 bytes) response from the I/O device.

For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.

Reviewed-by: James Hogan <jho...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/setup.c   |  6 ++
 arch/mips/include/asm/octeon/octeon.h | 12 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
 #else
cvmmemctl.s.cvmsegenak = 0;
 #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;
+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
 };
 
-- 
2.14.3

[PATCH v6 net-next,mips 4/7] staging: octeon: Remove USE_ASYNC_IOBDMA macro.

[David Daney]

Previous patch sets USE_ASYNC_IOBDMA to 1 unconditionally.  Remove
USE_ASYNC_IOBDMA from all if statements.  Remove dead code caused by
the change.

Acked-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 drivers/staging/octeon/ethernet-defines.h |  6 ---
 drivers/staging/octeon/ethernet-rx.c  | 25 -
 drivers/staging/octeon/ethernet-tx.c  | 85 ++-
 3 files changed, 37 insertions(+), 79 deletions(-)

diff --git a/drivers/staging/octeon/ethernet-defines.h 
b/drivers/staging/octeon/ethernet-defines.h
index e898df25b87f..21438c804a43 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -10,10 +10,6 @@
 
 /*
  * A few defines are used to control the operation of this driver:
- *  USE_ASYNC_IOBDMA
- *  Use asynchronous IO access to hardware. This uses Octeon's asynchronous
- *  IOBDMAs to issue IO accesses without stalling. Set this to zero
- *  to disable this. Note that IOBDMAs require CVMSEG.
  *  REUSE_SKBUFFS_WITHOUT_FREE
  *  Allows the TX path to free an skbuff into the FPA hardware pool. This
  *  can significantly improve performance for forwarding and bridging, but
@@ -32,8 +28,6 @@
 #define REUSE_SKBUFFS_WITHOUT_FREE  1
 #endif
 
-#define USE_ASYNC_IOBDMA   1
-
 /* Maximum number of SKBs to try to free per xmit packet. */
 #define MAX_OUT_QUEUE_DEPTH 1000
 
diff --git a/drivers/staging/octeon/ethernet-rx.c 
b/drivers/staging/octeon/ethernet-rx.c
index 1a44291318ee..dd76c99d5ae0 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -201,11 +201,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
/* Prefetch cvm_oct_device since we know we need it soon */
prefetch(cvm_oct_device);
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   }
+   /* Save scratch in case userspace is using it */
+   CVMX_SYNCIOBDMA;
+   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
 
/* Only allow work for our group (and preserve priorities) */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -220,10 +218,8 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
   BIT(rx_group->group));
}
 
-   if (USE_ASYNC_IOBDMA) {
-   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
-   did_work_request = 1;
-   }
+   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+   did_work_request = 1;
 
while (rx_count < budget) {
struct sk_buff *skb = NULL;
@@ -232,7 +228,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_wqe_t *work;
int port;
 
-   if (USE_ASYNC_IOBDMA && did_work_request)
+   if (did_work_request)
work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
else
work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
@@ -260,7 +256,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
sizeof(void *));
prefetch(pskb);
 
-   if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
+   if (rx_count < (budget - 1)) {
cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH,
CVMX_POW_NO_WAIT);
did_work_request = 1;
@@ -403,10 +399,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Restore the scratch area */
-   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
-   }
+   /* Restore the scratch area */
+   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+
cvm_oct_rx_refill_pool(0);
 
return rx_count;
diff --git a/drivers/staging/octeon/ethernet-tx.c 
b/drivers/staging/octeon/ethernet-tx.c
index 31f35025d19e..2eede0907924 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -179,23 +179,18 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device 
*dev)
qos = 0;
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
-
-   /*
-* Fetch and increment the number o

[PATCH v6 net-next,mips 2/7] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

From: Carlos Munoz 

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
  (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
  (up to 128) of data to the I/O device and then return a
  variable length (up to 128 bytes) response from the I/O device.

For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.

Reviewed-by: James Hogan 
Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 arch/mips/cavium-octeon/setup.c   |  6 ++
 arch/mips/include/asm/octeon/octeon.h | 12 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
 #else
cvmmemctl.s.cvmsegenak = 0;
 #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;
+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
 };
 
-- 
2.14.3

[PATCH v6 net-next,mips 4/7] staging: octeon: Remove USE_ASYNC_IOBDMA macro.

[David Daney]

Previous patch sets USE_ASYNC_IOBDMA to 1 unconditionally.  Remove
USE_ASYNC_IOBDMA from all if statements.  Remove dead code caused by
the change.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: David Daney 
---
 drivers/staging/octeon/ethernet-defines.h |  6 ---
 drivers/staging/octeon/ethernet-rx.c  | 25 -
 drivers/staging/octeon/ethernet-tx.c  | 85 ++-
 3 files changed, 37 insertions(+), 79 deletions(-)

diff --git a/drivers/staging/octeon/ethernet-defines.h 
b/drivers/staging/octeon/ethernet-defines.h
index e898df25b87f..21438c804a43 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -10,10 +10,6 @@
 
 /*
  * A few defines are used to control the operation of this driver:
- *  USE_ASYNC_IOBDMA
- *  Use asynchronous IO access to hardware. This uses Octeon's asynchronous
- *  IOBDMAs to issue IO accesses without stalling. Set this to zero
- *  to disable this. Note that IOBDMAs require CVMSEG.
  *  REUSE_SKBUFFS_WITHOUT_FREE
  *  Allows the TX path to free an skbuff into the FPA hardware pool. This
  *  can significantly improve performance for forwarding and bridging, but
@@ -32,8 +28,6 @@
 #define REUSE_SKBUFFS_WITHOUT_FREE  1
 #endif
 
-#define USE_ASYNC_IOBDMA   1
-
 /* Maximum number of SKBs to try to free per xmit packet. */
 #define MAX_OUT_QUEUE_DEPTH 1000
 
diff --git a/drivers/staging/octeon/ethernet-rx.c 
b/drivers/staging/octeon/ethernet-rx.c
index 1a44291318ee..dd76c99d5ae0 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -201,11 +201,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
/* Prefetch cvm_oct_device since we know we need it soon */
prefetch(cvm_oct_device);
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   }
+   /* Save scratch in case userspace is using it */
+   CVMX_SYNCIOBDMA;
+   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
 
/* Only allow work for our group (and preserve priorities) */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -220,10 +218,8 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
   BIT(rx_group->group));
}
 
-   if (USE_ASYNC_IOBDMA) {
-   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
-   did_work_request = 1;
-   }
+   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+   did_work_request = 1;
 
while (rx_count < budget) {
struct sk_buff *skb = NULL;
@@ -232,7 +228,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_wqe_t *work;
int port;
 
-   if (USE_ASYNC_IOBDMA && did_work_request)
+   if (did_work_request)
work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
else
work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
@@ -260,7 +256,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
sizeof(void *));
prefetch(pskb);
 
-   if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
+   if (rx_count < (budget - 1)) {
cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH,
CVMX_POW_NO_WAIT);
did_work_request = 1;
@@ -403,10 +399,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Restore the scratch area */
-   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
-   }
+   /* Restore the scratch area */
+   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+
cvm_oct_rx_refill_pool(0);
 
return rx_count;
diff --git a/drivers/staging/octeon/ethernet-tx.c 
b/drivers/staging/octeon/ethernet-tx.c
index 31f35025d19e..2eede0907924 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -179,23 +179,18 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device 
*dev)
qos = 0;
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
-
-   /*
-* Fetch and increment the number of packets to be
-* freed.
-*/
-   cv

[PATCH v6 net-next,mips 7/7] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[David Daney]

Signed-off-by: David Daney <david.da...@cavium.com>
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4007fa2e193e..b4bf5b205380 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3249,6 +3249,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M: David Daney <david.da...@cavium.com>
+L: net...@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian <george.cher...@cavium.com>
 L: linux-cry...@vger.kernel.org
-- 
2.14.3

[PATCH v6 net-next,mips 7/7] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[David Daney]

Signed-off-by: David Daney 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4007fa2e193e..b4bf5b205380 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3249,6 +3249,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M: David Daney 
+L: net...@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian 
 L: linux-cry...@vger.kernel.org
-- 
2.14.3

[PATCH v6 net-next,mips 0/7] Cavium OCTEON-III network driver.

[David Daney]

We are adding the Cavium OCTEON-III network driver.  But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code.  Aren't SoCs nice in this way?

The first five patches add the SoC support needed by the driver, the
last two add the driver and an entry in MAINTAINERS.

Since these touch several subsystems (mips, netdev), I would
propose merging via netdev, but defer to the maintainers if they think
something else would work better.

A separate pull request was recently done by Steven Hill for the
firmware required by the driver.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs (in
  the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (4):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  MIPS: Octeon: Enable LMTDMA/LMTST operations.
  MIPS: Octeon: Add a global resource manager.
  netdev: octeon-ethernet: Add Cavium Octeon III support.

David Daney (3):
  MIPS: Octeon: Automatically provision CVMSEG space.
  staging: octeon: Remove USE_ASYNC_IOBDMA macro.
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   61 +
 MAINTAINERS|6 +
 arch/mips/cavium-octeon/Kconfig|   27 +-
 arch/mips/cavium-octeon/Makefile   |1 +
 arch/mips/cavium-octeon/resource-mgr.c |  351 
 arch/mips/cavium-octeon/setup.c|   22 +-
 .../asm/mach-cavium-octeon/kernel-entry-init.h |   20 +-
 arch/mips/include/asm/mipsregs.h   |2 +
 arch/mips/include/asm/octeon/octeon.h  |   32 +-
 arch/mips/include/asm/processor.h  |2 +-
 arch/mips/kernel/octeon_switch.S   |2 -
 arch/mips/mm/tlbex.c   |   29 +-
 drivers/net/ethernet/cavium/Kconfig|   59 +-
 drivers/net/ethernet/cavium/octeon/Makefile|7 +
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  417 
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2018 +++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2079 
 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c   |  358 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  823 
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1688 
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  301 +++
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  430 
 drivers/staging/octeon/ethernet-defines.h  |6 -
 drivers/staging/octeon/ethernet-rx.c   |   25 +-
 drivers/staging/octeon/ethernet-tx.c   |   85 +-
 25 files changed, 8709 insertions(+), 142 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.14.3

[PATCH v6 net-next,mips 0/7] Cavium OCTEON-III network driver.

[David Daney]

We are adding the Cavium OCTEON-III network driver.  But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code.  Aren't SoCs nice in this way?

The first five patches add the SoC support needed by the driver, the
last two add the driver and an entry in MAINTAINERS.

Since these touch several subsystems (mips, netdev), I would
propose merging via netdev, but defer to the maintainers if they think
something else would work better.

A separate pull request was recently done by Steven Hill for the
firmware required by the driver.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs (in
  the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (4):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  MIPS: Octeon: Enable LMTDMA/LMTST operations.
  MIPS: Octeon: Add a global resource manager.
  netdev: octeon-ethernet: Add Cavium Octeon III support.

David Daney (3):
  MIPS: Octeon: Automatically provision CVMSEG space.
  staging: octeon: Remove USE_ASYNC_IOBDMA macro.
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   61 +
 MAINTAINERS|6 +
 arch/mips/cavium-octeon/Kconfig|   27 +-
 arch/mips/cavium-octeon/Makefile   |1 +
 arch/mips/cavium-octeon/resource-mgr.c |  351 
 arch/mips/cavium-octeon/setup.c|   22 +-
 .../asm/mach-cavium-octeon/kernel-entry-init.h |   20 +-
 arch/mips/include/asm/mipsregs.h   |2 +
 arch/mips/include/asm/octeon/octeon.h  |   32 +-
 arch/mips/include/asm/processor.h  |2 +-
 arch/mips/kernel/octeon_switch.S   |2 -
 arch/mips/mm/tlbex.c   |   29 +-
 drivers/net/ethernet/cavium/Kconfig|   59 +-
 drivers/net/ethernet/cavium/octeon/Makefile|7 +
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  417 
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2018 +++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2079 
 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c   |  358 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  823 
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1688 
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  301 +++
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  430 
 drivers/staging/octeon/ethernet-defines.h  |6 -
 drivers/staging/octeon/ethernet-rx.c   |   25 +-
 drivers/staging/octeon/ethernet-tx.c   |   85 +-
 25 files changed, 8709 insertions(+), 142 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.14.3

Re: [Bug fix] octeon-i2c driver updates

[David Daney]

On 12/04/2017 10:44 PM, Zhang, Sean C. (NSB - CN/Hangzhou) wrote:

Hi Jan,

Thanks for your comments, I get your point for the second point (retry of START 
after recovery).

Hi David,
For the issue as the first one, would you give your further comments? Thanks in 
advance.

I have an environment with CN6780 (TWSI core has property: compatible = 
"cavium,octeon-3860-twsi"),
And encounter below problem:
During i2c-octeon driver probing, this TWSI core original status is 0x20 (this 
may induced by uboot),
And octeon_i2c_init_lowlevel() function in octeon_i2c_probe() is not enough to 
recover the I2C bus,
If go without full recovery of octeon_i2c_recovery(), the following 
octeon_i2c_hlc_write(),
octeon_i2c_hlc_read(), octeon_i2c_hlc_comp_read() and 
octeon_i2c_hlc_comp_write() will goes error,
because these functions has no bus recovery step.
While after replace octeon_i2c_init_lowlevel() with octeon_i2c_recovery() in 
octeon_i2c_probe(), the
problem has gone.

Once more, this octeon_i2c_recovery() can also recover dead lock (I2C slave 
device stuck low SCL) issue,
so I think use octeon_i2c_recovery() instead will be stronger.


I don't want to do a bus reset unconditionally, as it is currently 
working well on many systems.


Perhaps you could add a module parameter to enable the recovery mode on 
probe as an option.  Would that work or be acceptable?


Thanks,
David Daney





BR,
Sean Zhang


-Original Message-
From: Jan Glauber [mailto:jan.glau...@caviumnetworks.com]
Sent: Friday, December 01, 2017 6:07 PM
To: Zhang, Sean C. (NSB - CN/Hangzhou) <sean.c.zh...@nokia-sbell.com>
Cc: david.da...@cavium.com; w...@the-dreams.de; linux-...@vger.kernel.org; 
linux-kernel@vger.kernel.org
Subject: Re: [Bug fix] octeon-i2c driver updates

Hi Sean,

as you try to solve two different issues I suggest that you create one
patch per issue.

For the second point (retry of START after recovery) I would still like
to hear Wolfram's opinion. I would assume that any i2c user should
be well aware of -EAGAIN, so I wonder if it is worth the additional
complexity of the retry logic.

Also, the first issue changes Octeon MIPS which I'm not able to test,
so David needs to be involved here.

thanks,
Jan

On Thu, Nov 30, 2017 at 01:56:09AM +, Zhang, Sean C. (NSB - CN/Hangzhou) 
wrote:

Hi Jan,

Any other comments for this patch?

BR,
Sean Zhang

-Original Message-
From: Zhang, Sean C. (NSB - CN/Hangzhou)
Sent: Monday, November 27, 2017 4:38 PM
To: 'Jan Glauber' <jan.glau...@caviumnetworks.com>
Cc: david.da...@cavium.com; w...@the-dreams.de; linux-...@vger.kernel.org; 
linux-kernel@vger.kernel.org
Subject: RE: [Bug fix] octeon-i2c driver updates

Hi Jan,

There are two points in this patch.

Point 1. As you see, replaced octeon_i2c_init_lowlevel() by recover bus status 
if TWSI controller is not IDLE.
Please take a scenario like this: when system soft reset without I2C slave 
reset, maybe make this I2C bus
dead lock occurred (I2C slave device stuck low SCL) in chance. Then during 
system goes up and I2C slave
device creating process, if this I2C slave device has a register with less than 
8 bytes to read, but I2C bus was
still stuck low SCL by last system reset, then the read will failed and this 
I2C slave device cannot be created.
If bus recovered before the reading process, this failure can be fixed.

Function flow explanation shown as below:

a. System reset without I2C slave device reset
--make SCL stuck low by I2C slave device
..
b. octeon_i2c_probe（）
-- octeon_i2c_init_lowlevel  //reset TWSI core, but SCL still stuck low by.
..

c. Another I2C slave device creating process
octeon_i2c_xfer()
-- octeon_i2c_hlc_comp_read() //failed due to SCL stuck low.

If full recovery executed in octeon_i2c_probe（), above failure can be avoided.


Point 2. octeon_i2c_recovery() is used in octeon_i2c_start() error branch, in 
the case of octeon_i2c_recovery()
successful, octeon_i2c_start() will return -EAGAIN, and then octeon_i2c_xfer() 
return with error. I understand this like
this: if octeon_i2c_recovery() successful, then i2c START signal can be sent 
again, and all following step can be continue,
octeon_i2c_xfer() should not return error from this condition.

BR,
Sean Zhang

-Original Message-
From: Jan Glauber [mailto:jan.glau...@caviumnetworks.com]
Sent: Friday, November 24, 2017 9:10 PM
To: Zhang, Sean C. (NSB - CN/Hangzhou) <sean.c.zh...@nokia-sbell.com>
Cc: david.da...@cavium.com; w...@the-dreams.de; linux-...@vger.kernel.org; 
linux-kernel@vger.kernel.org
Subject: Re: [Bug fix] octeon-i2c driver updates

On Thu, Nov 23, 2017 at 11:42:36AM +, Zhang, Sean C. (NSB - CN/Hangzhou) 
wrote:

Dear Maintainer,

For octeon TWSI controller, I found below two cases, maybe can be improved.


Hi Sean,

form the description below this looks like you're fixing a bug. Can you
elaborate on when the I2C bus dead lock occurs. Is it always happening?

What I don't like about the p

Re: [Bug fix] octeon-i2c driver updates

[David Daney]

On 12/04/2017 10:44 PM, Zhang, Sean C. (NSB - CN/Hangzhou) wrote:

Hi Jan,

Thanks for your comments, I get your point for the second point (retry of START 
after recovery).

Hi David,
For the issue as the first one, would you give your further comments? Thanks in 
advance.

I have an environment with CN6780 (TWSI core has property: compatible = 
"cavium,octeon-3860-twsi"),
And encounter below problem:
During i2c-octeon driver probing, this TWSI core original status is 0x20 (this 
may induced by uboot),
And octeon_i2c_init_lowlevel() function in octeon_i2c_probe() is not enough to 
recover the I2C bus,
If go without full recovery of octeon_i2c_recovery(), the following 
octeon_i2c_hlc_write(),
octeon_i2c_hlc_read(), octeon_i2c_hlc_comp_read() and 
octeon_i2c_hlc_comp_write() will goes error,
because these functions has no bus recovery step.
While after replace octeon_i2c_init_lowlevel() with octeon_i2c_recovery() in 
octeon_i2c_probe(), the
problem has gone.

Once more, this octeon_i2c_recovery() can also recover dead lock (I2C slave 
device stuck low SCL) issue,
so I think use octeon_i2c_recovery() instead will be stronger.


I don't want to do a bus reset unconditionally, as it is currently 
working well on many systems.


Perhaps you could add a module parameter to enable the recovery mode on 
probe as an option.  Would that work or be acceptable?


Thanks,
David Daney





BR,
Sean Zhang


-Original Message-
From: Jan Glauber [mailto:jan.glau...@caviumnetworks.com]
Sent: Friday, December 01, 2017 6:07 PM
To: Zhang, Sean C. (NSB - CN/Hangzhou) 
Cc: david.da...@cavium.com; w...@the-dreams.de; linux-...@vger.kernel.org; 
linux-kernel@vger.kernel.org
Subject: Re: [Bug fix] octeon-i2c driver updates

Hi Sean,

as you try to solve two different issues I suggest that you create one
patch per issue.

For the second point (retry of START after recovery) I would still like
to hear Wolfram's opinion. I would assume that any i2c user should
be well aware of -EAGAIN, so I wonder if it is worth the additional
complexity of the retry logic.

Also, the first issue changes Octeon MIPS which I'm not able to test,
so David needs to be involved here.

thanks,
Jan

On Thu, Nov 30, 2017 at 01:56:09AM +, Zhang, Sean C. (NSB - CN/Hangzhou) 
wrote:

Hi Jan,

Any other comments for this patch?

BR,
Sean Zhang

-Original Message-
From: Zhang, Sean C. (NSB - CN/Hangzhou)
Sent: Monday, November 27, 2017 4:38 PM
To: 'Jan Glauber' 
Cc: david.da...@cavium.com; w...@the-dreams.de; linux-...@vger.kernel.org; 
linux-kernel@vger.kernel.org
Subject: RE: [Bug fix] octeon-i2c driver updates

Hi Jan,

There are two points in this patch.

Point 1. As you see, replaced octeon_i2c_init_lowlevel() by recover bus status 
if TWSI controller is not IDLE.
Please take a scenario like this: when system soft reset without I2C slave 
reset, maybe make this I2C bus
dead lock occurred (I2C slave device stuck low SCL) in chance. Then during 
system goes up and I2C slave
device creating process, if this I2C slave device has a register with less than 
8 bytes to read, but I2C bus was
still stuck low SCL by last system reset, then the read will failed and this 
I2C slave device cannot be created.
If bus recovered before the reading process, this failure can be fixed.

Function flow explanation shown as below:

a. System reset without I2C slave device reset
--make SCL stuck low by I2C slave device
..
b. octeon_i2c_probe（）
-- octeon_i2c_init_lowlevel  //reset TWSI core, but SCL still stuck low by.
..

c. Another I2C slave device creating process
octeon_i2c_xfer()
-- octeon_i2c_hlc_comp_read() //failed due to SCL stuck low.

If full recovery executed in octeon_i2c_probe（), above failure can be avoided.


Point 2. octeon_i2c_recovery() is used in octeon_i2c_start() error branch, in 
the case of octeon_i2c_recovery()
successful, octeon_i2c_start() will return -EAGAIN, and then octeon_i2c_xfer() 
return with error. I understand this like
this: if octeon_i2c_recovery() successful, then i2c START signal can be sent 
again, and all following step can be continue,
octeon_i2c_xfer() should not return error from this condition.

BR,
Sean Zhang

-Original Message-
From: Jan Glauber [mailto:jan.glau...@caviumnetworks.com]
Sent: Friday, November 24, 2017 9:10 PM
To: Zhang, Sean C. (NSB - CN/Hangzhou) 
Cc: david.da...@cavium.com; w...@the-dreams.de; linux-...@vger.kernel.org; 
linux-kernel@vger.kernel.org
Subject: Re: [Bug fix] octeon-i2c driver updates

On Thu, Nov 23, 2017 at 11:42:36AM +, Zhang, Sean C. (NSB - CN/Hangzhou) 
wrote:

Dear Maintainer,

For octeon TWSI controller, I found below two cases, maybe can be improved.


Hi Sean,

form the description below this looks like you're fixing a bug. Can you
elaborate on when the I2C bus dead lock occurs. Is it always happening?

What I don't like about the patch is that you're removing
octeon_i2c_init_lowlevel() from the probe and replacing it by _always_
going thro

[PATCH v5 net-next,mips 1/7] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

Add bindings for Common Ethernet Interface (BGX) block.

Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 .../devicetree/bindings/net/cavium-bgx.txt | 61 ++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index ..830c5f08
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,61 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+A BGX block has several children, each representing an Ethernet
+interface.
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all
+ cn7xxx SOCs.
+
+ "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs
+ for RGMII.
+
+- reg: The index of the interface within the BGX block.
+
+Optional properties:
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- phy-mode: described in ethernet.txt.
+
+- fixed-link: described in fixed-link.txt.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet@0 {
+   compatible = "cavium,octeon-7360-xcv";
+   reg = <0>;
+   local-mac-address = [ 00 01 23 45 67 89 ];
+   phy-handle = <>;
+   phy-mode = "rgmii-rxid"
+   };
+   ethernet@1 {
+   compatible = "cavium,octeon-7890-bgx-port";
+   reg = <1>;
+   local-mac-address = [ 00 01 23 45 67 8a ];
+   phy-handle = <>;
+   phy-mode = "sgmii"
+   };
+   };
-- 
2.14.3

[PATCH v5 net-next,mips 1/7] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[David Daney]

From: Carlos Munoz 

Add bindings for Common Ethernet Interface (BGX) block.

Acked-by: Rob Herring 
Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 .../devicetree/bindings/net/cavium-bgx.txt | 61 ++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index ..830c5f08
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,61 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+A BGX block has several children, each representing an Ethernet
+interface.
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all
+ cn7xxx SOCs.
+
+ "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs
+ for RGMII.
+
+- reg: The index of the interface within the BGX block.
+
+Optional properties:
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- phy-mode: described in ethernet.txt.
+
+- fixed-link: described in fixed-link.txt.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet@0 {
+   compatible = "cavium,octeon-7360-xcv";
+   reg = <0>;
+   local-mac-address = [ 00 01 23 45 67 89 ];
+   phy-handle = <>;
+   phy-mode = "rgmii-rxid"
+   };
+   ethernet@1 {
+   compatible = "cavium,octeon-7890-bgx-port";
+   reg = <1>;
+   local-mac-address = [ 00 01 23 45 67 8a ];
+   phy-handle = <>;
+   phy-mode = "sgmii"
+   };
+   };
-- 
2.14.3

[PATCH v5 net-next,mips 5/7] MIPS: Octeon: Automatically provision CVMSEG space.

[David Daney]

Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.

1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE

New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.

Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Carlos Munoz <cmu...@caviumnetworks.com>
---
 arch/mips/cavium-octeon/Kconfig| 27 
 arch/mips/cavium-octeon/setup.c| 16 ++--
 .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +--
 arch/mips/include/asm/mipsregs.h   |  2 ++
 arch/mips/include/asm/octeon/octeon.h  |  2 ++
 arch/mips/include/asm/processor.h  |  2 +-
 arch/mips/kernel/octeon_switch.S   |  2 --
 arch/mips/mm/tlbex.c   | 29 ++
 drivers/staging/octeon/ethernet-defines.h  |  2 +-
 9 files changed, 50 insertions(+), 52 deletions(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index ce469f982134..29c4d81364a6 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -11,21 +11,26 @@ config CAVIUM_CN63XXP1
  non-CN63XXP1 hardware, so it is recommended to select "n"
  unless it is known the workarounds are needed.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-   int "Number of L1 cache lines reserved for CVMSEG memory"
-   range 0 54
-   default 1
-   help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
 
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+   int "Number of extra L1 cache lines reserved for CVMSEG memory"
+   range 0 50
+   default 0
+   help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is.  The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
 config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68bc652..51c4d3c3cada 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
 static unsigned long long max_memory = ULLONG_MAX;
 static unsigned long long reserve_low_mem;
 
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 EXPORT_SYMBOL(octeon_bootbus_sem);
 
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
 
/* R/W If set, CVMSEG is available for loads/stores in
 * kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
-   cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
 
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
-   pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+   pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
 
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38ce5a3d..cdcca60978a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+   mfc0v1, CP0_PRID_REG
+   andiv1, 0xff00

[PATCH v5 net-next,mips 5/7] MIPS: Octeon: Automatically provision CVMSEG space.

[David Daney]

Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.

1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE

New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.

Signed-off-by: David Daney 
Signed-off-by: Carlos Munoz 
---
 arch/mips/cavium-octeon/Kconfig| 27 
 arch/mips/cavium-octeon/setup.c| 16 ++--
 .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +--
 arch/mips/include/asm/mipsregs.h   |  2 ++
 arch/mips/include/asm/octeon/octeon.h  |  2 ++
 arch/mips/include/asm/processor.h  |  2 +-
 arch/mips/kernel/octeon_switch.S   |  2 --
 arch/mips/mm/tlbex.c   | 29 ++
 drivers/staging/octeon/ethernet-defines.h  |  2 +-
 9 files changed, 50 insertions(+), 52 deletions(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index ce469f982134..29c4d81364a6 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -11,21 +11,26 @@ config CAVIUM_CN63XXP1
  non-CN63XXP1 hardware, so it is recommended to select "n"
  unless it is known the workarounds are needed.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-   int "Number of L1 cache lines reserved for CVMSEG memory"
-   range 0 54
-   default 1
-   help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
 
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+   int "Number of extra L1 cache lines reserved for CVMSEG memory"
+   range 0 50
+   default 0
+   help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is.  The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
 config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68bc652..51c4d3c3cada 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
 static unsigned long long max_memory = ULLONG_MAX;
 static unsigned long long reserve_low_mem;
 
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 EXPORT_SYMBOL(octeon_bootbus_sem);
 
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
 
/* R/W If set, CVMSEG is available for loads/stores in
 * kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
-   cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
 
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
-   pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+   pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
 
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38ce5a3d..cdcca60978a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+   mfc0v1, CP0_PRID_REG
+   andiv1, 0xff00
+   li  v0, 0x9500   

[PATCH v5 net-next,mips 0/7] Cavium OCTEON-III network driver.

[David Daney]

We are adding the Cavium OCTEON-III network driver.  But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code.  Aren't SoCs nice in this way?

The first five patches add the SoC support needed by the driver, the
last two add the driver and an entry in MAINTAINERS.

Since these touch several subsystems (mips, netdev), I would
propose merging via netdev, but defer to the maintainers if they think
something else would work better.

A separate pull request was recently done by Steven Hill for the
firmware required by the driver.

Changes from v4:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes from v3:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes from v2:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes from v1:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs (in
  the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (5):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  MIPS: Octeon: Enable LMTDMA/LMTST operations.
  MIPS: Octeon: Add a global resource manager.
  MIPS: Octeon: Add Free Pointer Unit (FPA) support.
  netdev: octeon-ethernet: Add Cavium Octeon III support.

David Daney (2):
  MIPS: Octeon: Automatically provision CVMSEG space.
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   61 +
 MAINTAINERS|6 +
 arch/mips/cavium-octeon/Kconfig|   35 +-
 arch/mips/cavium-octeon/Makefile   |2 +
 arch/mips/cavium-octeon/octeon-fpa3.c  |  363 
 arch/mips/cavium-octeon/resource-mgr.c |  351 
 arch/mips/cavium-octeon/setup.c|   22 +-
 .../asm/mach-cavium-octeon/kernel-entry-init.h |   20 +-
 arch/mips/include/asm/mipsregs.h   |2 +
 arch/mips/include/asm/octeon/octeon.h  |   45 +-
 arch/mips/include/asm/processor.h  |2 +-
 arch/mips/kernel/octeon_switch.S   |2 -
 arch/mips/mm/tlbex.c   |   29 +-
 drivers/net/ethernet/cavium/Kconfig|   55 +-
 drivers/net/ethernet/cavium/octeon/Makefile|6 +
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  701 +++
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2015 +++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2069 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  824 
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1688 
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  301 +++
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  418 
 drivers/staging/octeon/ethernet-defines.h  |2 +-
 23 files changed, 8955 insertions(+), 64 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 arch/mips/cavium-octeon/octeon-fpa3.c
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.14.3

[PATCH v5 net-next,mips 3/7] MIPS: Octeon: Add a global resource manager.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/include/asm/octeon/octeon.h  |  18 ++
 3 files changed, 370 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..28c0bb75d1a4 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -10,6 +10,7 @@
 #
 
 obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y += resource-mgr.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..74efda5420ff
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   while (cmpxchg(_mgr_info->rlock, 0, 1))
+   ; /* Loop while not zero */
+   rmb();
+}
+
+static void res_mgr_unlock(void)
+{
+   /* Wait until all resource operations finish before unlocking. */
+   wmb();
+   WRITE_ONCE(res_mgr_info->rlock, 0);
+   /* Force a write buffer flush. */
+   wmb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource() - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source was created successfully.
+ * Returns < 0 for error codes.
+ */
+int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt)
+{
+   struct global_resource_entry *res_entry;
+   u64 size;
+   u64 *res_addr;
+   int res_index, i, rc = 0;
+
+   res_mgr_lock();
+
+   /* Make sure resource doesn't already exist. */
+   res_index = res_mgr_find_resource(tag);
+   if (res_index >= 0) {
+   rc = -EEXIST;
+   goto err;
+   }
+
+   if (res_mgr_info->entry_cnt >= MAX_RESOURCES) {
+   pr_err("Resource max limit reached, not created\n");
+   rc = -ENOSPC;
+   goto err;
+   }
+
+   /*
+* Each instance is kept in an array of u64s. The first array element
+* holds the number of allocated instances.
+*/
+   size = sizeof(u64) * (inst_cnt + 1);
+   res_addr = cvmx_bootmem_alloc_range(size, CVMX_CACHE_LINE_SIZE, 0, 0);
+   if (!res_addr) {
+   pr_err("Failed to allocate resource. not created\n");
+   rc = -ENOMEM;
+   goto err;
+   }
+
+   /* Initialize the newly created resource. */
+   *res_addr = inst_cnt;
+   for (i = 1; i <= inst_cnt; i++)
+   res_addr[i] = INST_AVAILABLE;
+
+   res_index = res_mgr_info->entry_cnt;
+   res_entry = _mgr_info->resource_entry[res_index];
+   res_entry->tag = tag;
+   res_entry->phys_addr = virt_to_phys(res_addr);
+   res_entry->size = size;
+   res_mgr_in

[PATCH v5 net-next,mips 0/7] Cavium OCTEON-III network driver.

[David Daney]

We are adding the Cavium OCTEON-III network driver.  But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code.  Aren't SoCs nice in this way?

The first five patches add the SoC support needed by the driver, the
last two add the driver and an entry in MAINTAINERS.

Since these touch several subsystems (mips, netdev), I would
propose merging via netdev, but defer to the maintainers if they think
something else would work better.

A separate pull request was recently done by Steven Hill for the
firmware required by the driver.

Changes from v4:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes from v3:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes from v2:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes from v1:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs (in
  the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (5):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  MIPS: Octeon: Enable LMTDMA/LMTST operations.
  MIPS: Octeon: Add a global resource manager.
  MIPS: Octeon: Add Free Pointer Unit (FPA) support.
  netdev: octeon-ethernet: Add Cavium Octeon III support.

David Daney (2):
  MIPS: Octeon: Automatically provision CVMSEG space.
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   61 +
 MAINTAINERS|6 +
 arch/mips/cavium-octeon/Kconfig|   35 +-
 arch/mips/cavium-octeon/Makefile   |2 +
 arch/mips/cavium-octeon/octeon-fpa3.c  |  363 
 arch/mips/cavium-octeon/resource-mgr.c |  351 
 arch/mips/cavium-octeon/setup.c|   22 +-
 .../asm/mach-cavium-octeon/kernel-entry-init.h |   20 +-
 arch/mips/include/asm/mipsregs.h   |2 +
 arch/mips/include/asm/octeon/octeon.h  |   45 +-
 arch/mips/include/asm/processor.h  |2 +-
 arch/mips/kernel/octeon_switch.S   |2 -
 arch/mips/mm/tlbex.c   |   29 +-
 drivers/net/ethernet/cavium/Kconfig|   55 +-
 drivers/net/ethernet/cavium/octeon/Makefile|6 +
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  701 +++
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2015 +++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2069 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  824 
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1688 
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  301 +++
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  418 
 drivers/staging/octeon/ethernet-defines.h  |2 +-
 23 files changed, 8955 insertions(+), 64 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 arch/mips/cavium-octeon/octeon-fpa3.c
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.14.3

[PATCH v5 net-next,mips 3/7] MIPS: Octeon: Add a global resource manager.

[David Daney]

From: Carlos Munoz 

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/include/asm/octeon/octeon.h  |  18 ++
 3 files changed, 370 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..28c0bb75d1a4 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -10,6 +10,7 @@
 #
 
 obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y += resource-mgr.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..74efda5420ff
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   while (cmpxchg(_mgr_info->rlock, 0, 1))
+   ; /* Loop while not zero */
+   rmb();
+}
+
+static void res_mgr_unlock(void)
+{
+   /* Wait until all resource operations finish before unlocking. */
+   wmb();
+   WRITE_ONCE(res_mgr_info->rlock, 0);
+   /* Force a write buffer flush. */
+   wmb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource() - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source was created successfully.
+ * Returns < 0 for error codes.
+ */
+int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt)
+{
+   struct global_resource_entry *res_entry;
+   u64 size;
+   u64 *res_addr;
+   int res_index, i, rc = 0;
+
+   res_mgr_lock();
+
+   /* Make sure resource doesn't already exist. */
+   res_index = res_mgr_find_resource(tag);
+   if (res_index >= 0) {
+   rc = -EEXIST;
+   goto err;
+   }
+
+   if (res_mgr_info->entry_cnt >= MAX_RESOURCES) {
+   pr_err("Resource max limit reached, not created\n");
+   rc = -ENOSPC;
+   goto err;
+   }
+
+   /*
+* Each instance is kept in an array of u64s. The first array element
+* holds the number of allocated instances.
+*/
+   size = sizeof(u64) * (inst_cnt + 1);
+   res_addr = cvmx_bootmem_alloc_range(size, CVMX_CACHE_LINE_SIZE, 0, 0);
+   if (!res_addr) {
+   pr_err("Failed to allocate resource. not created\n");
+   rc = -ENOMEM;
+   goto err;
+   }
+
+   /* Initialize the newly created resource. */
+   *res_addr = inst_cnt;
+   for (i = 1; i <= inst_cnt; i++)
+   res_addr[i] = INST_AVAILABLE;
+
+   res_index = res_mgr_info->entry_cnt;
+   res_entry = _mgr_info->resource_entry[res_index];
+   res_entry->tag = tag;
+   res_entry->phys_addr = virt_to_phys(res_addr);
+   res_entry->size = size;
+   res_mgr_info->entry_cnt++;
+
+err:
+   res_mgr_unlock();
+
+   return rc;
+}
+EXPORT_SYMBOL(res_mgr_create_resource);
+
+

[PATCH v5 net-next,mips 2/7] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
  (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
  (up to 128) of data to the I/O device and then return a
  variable length (up to 128 bytes) response from the I/O device.

For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.

Reviewed-by: James Hogan <jho...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/setup.c   |  6 ++
 arch/mips/include/asm/octeon/octeon.h | 12 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
 #else
cvmmemctl.s.cvmsegenak = 0;
 #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;
+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
 };
 
-- 
2.14.3

[PATCH v5 net-next,mips 7/7] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[David Daney]

Signed-off-by: David Daney <david.da...@cavium.com>
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 77d819b458a9..5aff6fb41b21 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3249,6 +3249,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M: David Daney <david.da...@cavium.com>
+L: net...@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian <george.cher...@cavium.com>
 L: linux-cry...@vger.kernel.org
-- 
2.14.3

[PATCH v5 net-next,mips 2/7] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

From: Carlos Munoz 

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
  (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
  (up to 128) of data to the I/O device and then return a
  variable length (up to 128 bytes) response from the I/O device.

For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.

Reviewed-by: James Hogan 
Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 arch/mips/cavium-octeon/setup.c   |  6 ++
 arch/mips/include/asm/octeon/octeon.h | 12 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
 #else
cvmmemctl.s.cvmsegenak = 0;
 #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;
+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
 };
 
-- 
2.14.3

[PATCH v5 net-next,mips 7/7] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[David Daney]

Signed-off-by: David Daney 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 77d819b458a9..5aff6fb41b21 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3249,6 +3249,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M: David Daney 
+L: net...@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian 
 L: linux-cry...@vger.kernel.org
-- 
2.14.3

[PATCH v5 net-next,mips 4/7] MIPS: Octeon: Add Free Pointer Unit (FPA) support.

[David Daney]

From: Carlos Munoz <cmu...@cavium.com>

>From the hardware user manual: "The FPA is a unit that maintains
pools of pointers to free L2/DRAM memory. To provide QoS, the pools
are referenced indirectly through 1024 auras. Both core software
and hardware units allocate and free pointers."

Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/Kconfig   |   8 +
 arch/mips/cavium-octeon/Makefile  |   1 +
 arch/mips/cavium-octeon/octeon-fpa3.c | 363 ++
 arch/mips/include/asm/octeon/octeon.h |  13 ++
 4 files changed, 385 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/octeon-fpa3.c

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 204a1670fd9b..ce469f982134 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -87,4 +87,12 @@ config OCTEON_ILM
  To compile this driver as a module, choose M here.  The module
  will be called octeon-ilm
 
+config OCTEON_FPA3
+   tristate "Octeon III fpa driver"
+   help
+ This option enables a Octeon III driver for the Free Pool Unit (FPA).
+ The FPA is a hardware unit that manages pools of pointers to free
+ L2/DRAM memory. This driver provides an interface to reserve,
+ initialize, and fill fpa pools.
+
 endif # CAVIUM_OCTEON_SOC
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 28c0bb75d1a4..9d547c2cd77d 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_MTD)   += flash_setup.o
 obj-$(CONFIG_SMP)+= smp.o
 obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
 obj-$(CONFIG_USB)+= octeon-usb.o
+obj-$(CONFIG_OCTEON_FPA3)+= octeon-fpa3.o
diff --git a/arch/mips/cavium-octeon/octeon-fpa3.c 
b/arch/mips/cavium-octeon/octeon-fpa3.c
new file mode 100644
index ..3f0c10e9d915
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-fpa3.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the Octeon III Free Pool Unit (fpa).
+ *
+ * Copyright (C) 2015-2017 Cavium, Inc.
+ */
+
+#include 
+
+#include 
+
+
+/* Registers are accessed via xkphys */
+#define SET_XKPHYS (1ull << 63)
+#define NODE_OFFSET0x10ull
+#define SET_NODE(node) ((node) * NODE_OFFSET)
+
+#define FPA_BASE   0x12800ull
+#define SET_FPA_BASE(node) (SET_XKPHYS + SET_NODE(node) + FPA_BASE)
+
+#define FPA_GEN_CFG(n) (SET_FPA_BASE(n)   + 0x0050)
+
+#define FPA_POOLX_CFG(n, p)(SET_FPA_BASE(n) + (p<<3)  + 0x1000)
+#define FPA_POOLX_START_ADDR(n, p) (SET_FPA_BASE(n) + (p<<3)  + 0x1050)
+#define FPA_POOLX_END_ADDR(n, p)   (SET_FPA_BASE(n) + (p<<3)  + 0x1060)
+#define FPA_POOLX_STACK_BASE(n, p) (SET_FPA_BASE(n) + (p<<3)  + 0x1070)
+#define FPA_POOLX_STACK_END(n, p)  (SET_FPA_BASE(n) + (p<<3)  + 0x1080)
+#define FPA_POOLX_STACK_ADDR(n, p) (SET_FPA_BASE(n) + (p<<3)  + 0x1090)
+
+#define FPA_AURAX_POOL(n, a)   (SET_FPA_BASE(n) + (a<<3)  + 0x2000)
+#define FPA_AURAX_CFG(n, a)(SET_FPA_BASE(n) + (a<<3)  + 0x2010)
+#define FPA_AURAX_CNT(n, a)(SET_FPA_BASE(n) + (a<<3)  + 0x2020)
+#define FPA_AURAX_CNT_LIMIT(n, a)  (SET_FPA_BASE(n) + (a<<3)  + 0x2040)
+#define FPA_AURAX_CNT_THRESHOLD(n, a)  (SET_FPA_BASE(n) + (a<<3)  + 0x2050)
+#define FPA_AURAX_POOL_LEVELS(n, a)(SET_FPA_BASE(n) + (a<<3)  + 0x2070)
+#define FPA_AURAX_CNT_LEVELS(n, a) (SET_FPA_BASE(n) + (a<<3)  + 0x2080)
+
+static inline u64 oct_csr_read(u64 addr)
+{
+   return __raw_readq((void __iomem *)addr);
+}
+
+static inline void oct_csr_write(u64 data, u64 addr)
+{
+   __raw_writeq(data, (void __iomem *)addr);
+}
+
+static DEFINE_MUTEX(octeon_fpa3_lock);
+
+static int get_num_pools(void)
+{
+   if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+   return 64;
+   if (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))
+   return 32;
+   return 0;
+}
+
+static int get_num_auras(void)
+{
+   if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+   return 1024;
+   if (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))
+   return 512;
+   return 0;
+}
+
+/**
+ * octeon_fpa3_init() - Initialize the fpa to default values.
+ * @node: Node of fpa to initialize.
+ *
+ * Return: 0 if successful.
+ * < 0 for error codes.
+ */
+int octeon_fpa3_init(int node)
+{
+   static bool init_done[2];
+   u64 data;
+   int aura_

[PATCH v5 net-next,mips 4/7] MIPS: Octeon: Add Free Pointer Unit (FPA) support.

[David Daney]

From: Carlos Munoz 

>From the hardware user manual: "The FPA is a unit that maintains
pools of pointers to free L2/DRAM memory. To provide QoS, the pools
are referenced indirectly through 1024 auras. Both core software
and hardware units allocate and free pointers."

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
 arch/mips/cavium-octeon/Kconfig   |   8 +
 arch/mips/cavium-octeon/Makefile  |   1 +
 arch/mips/cavium-octeon/octeon-fpa3.c | 363 ++
 arch/mips/include/asm/octeon/octeon.h |  13 ++
 4 files changed, 385 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/octeon-fpa3.c

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 204a1670fd9b..ce469f982134 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -87,4 +87,12 @@ config OCTEON_ILM
  To compile this driver as a module, choose M here.  The module
  will be called octeon-ilm
 
+config OCTEON_FPA3
+   tristate "Octeon III fpa driver"
+   help
+ This option enables a Octeon III driver for the Free Pool Unit (FPA).
+ The FPA is a hardware unit that manages pools of pointers to free
+ L2/DRAM memory. This driver provides an interface to reserve,
+ initialize, and fill fpa pools.
+
 endif # CAVIUM_OCTEON_SOC
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 28c0bb75d1a4..9d547c2cd77d 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_MTD)   += flash_setup.o
 obj-$(CONFIG_SMP)+= smp.o
 obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
 obj-$(CONFIG_USB)+= octeon-usb.o
+obj-$(CONFIG_OCTEON_FPA3)+= octeon-fpa3.o
diff --git a/arch/mips/cavium-octeon/octeon-fpa3.c 
b/arch/mips/cavium-octeon/octeon-fpa3.c
new file mode 100644
index ..3f0c10e9d915
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-fpa3.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the Octeon III Free Pool Unit (fpa).
+ *
+ * Copyright (C) 2015-2017 Cavium, Inc.
+ */
+
+#include 
+
+#include 
+
+
+/* Registers are accessed via xkphys */
+#define SET_XKPHYS (1ull << 63)
+#define NODE_OFFSET0x10ull
+#define SET_NODE(node) ((node) * NODE_OFFSET)
+
+#define FPA_BASE   0x12800ull
+#define SET_FPA_BASE(node) (SET_XKPHYS + SET_NODE(node) + FPA_BASE)
+
+#define FPA_GEN_CFG(n) (SET_FPA_BASE(n)   + 0x0050)
+
+#define FPA_POOLX_CFG(n, p)(SET_FPA_BASE(n) + (p<<3)  + 0x1000)
+#define FPA_POOLX_START_ADDR(n, p) (SET_FPA_BASE(n) + (p<<3)  + 0x1050)
+#define FPA_POOLX_END_ADDR(n, p)   (SET_FPA_BASE(n) + (p<<3)  + 0x1060)
+#define FPA_POOLX_STACK_BASE(n, p) (SET_FPA_BASE(n) + (p<<3)  + 0x1070)
+#define FPA_POOLX_STACK_END(n, p)  (SET_FPA_BASE(n) + (p<<3)  + 0x1080)
+#define FPA_POOLX_STACK_ADDR(n, p) (SET_FPA_BASE(n) + (p<<3)  + 0x1090)
+
+#define FPA_AURAX_POOL(n, a)   (SET_FPA_BASE(n) + (a<<3)  + 0x2000)
+#define FPA_AURAX_CFG(n, a)(SET_FPA_BASE(n) + (a<<3)  + 0x2010)
+#define FPA_AURAX_CNT(n, a)(SET_FPA_BASE(n) + (a<<3)  + 0x2020)
+#define FPA_AURAX_CNT_LIMIT(n, a)  (SET_FPA_BASE(n) + (a<<3)  + 0x2040)
+#define FPA_AURAX_CNT_THRESHOLD(n, a)  (SET_FPA_BASE(n) + (a<<3)  + 0x2050)
+#define FPA_AURAX_POOL_LEVELS(n, a)(SET_FPA_BASE(n) + (a<<3)  + 0x2070)
+#define FPA_AURAX_CNT_LEVELS(n, a) (SET_FPA_BASE(n) + (a<<3)  + 0x2080)
+
+static inline u64 oct_csr_read(u64 addr)
+{
+   return __raw_readq((void __iomem *)addr);
+}
+
+static inline void oct_csr_write(u64 data, u64 addr)
+{
+   __raw_writeq(data, (void __iomem *)addr);
+}
+
+static DEFINE_MUTEX(octeon_fpa3_lock);
+
+static int get_num_pools(void)
+{
+   if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+   return 64;
+   if (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))
+   return 32;
+   return 0;
+}
+
+static int get_num_auras(void)
+{
+   if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+   return 1024;
+   if (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))
+   return 512;
+   return 0;
+}
+
+/**
+ * octeon_fpa3_init() - Initialize the fpa to default values.
+ * @node: Node of fpa to initialize.
+ *
+ * Return: 0 if successful.
+ * < 0 for error codes.
+ */
+int octeon_fpa3_init(int node)
+{
+   static bool init_done[2];
+   u64 data;
+   int aura_cnt, i;
+
+   mutex_lock(_fpa3_lock);
+
+   if (init_done[node])
+   goto done;
+
+   aur

Re: [PATCH v4 3/8] MIPS: Octeon: Add a global resource manager.

[David Daney]

On 12/01/2017 12:41 PM, Philippe Ombredanne wrote:

David,

On Fri, Dec 1, 2017 at 9:01 PM, David Daney <dda...@caviumnetworks.com> wrote:

On 12/01/2017 11:49 AM, Philippe Ombredanne wrote:


David, Greg,

On Fri, Dec 1, 2017 at 6:42 PM, David Daney <dda...@caviumnetworks.com>
wrote:


On 11/30/2017 11:53 PM, Philippe Ombredanne wrote:


[...]


--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * This file is subject to the terms and conditions of the GNU
General
Public
+ * License.  See the file "COPYING" in the main directory of this
archive
+ * for more details.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */




Since you nicely included an SPDX id, you would not need the
boilerplate anymore. e.g. these can go alright?




They may not be strictly speaking necessary, but I don't think they hurt
anything.  Unless there is a requirement to strip out the license text,
we
would stick with it as is.



I think the requirement is there and that would be much better for
everyone: keeping both is redundant and does not bring any value, does
it? Instead it kinda removes the benefits of having the SPDX id in the
first place IMHO.

Furthermore, as there have been already ~12K+ files cleaned up and
still over 60K files to go, it would really nice if new files could
adopt the new style: this way we will not have to revisit and repatch
them in the future.



I am happy to follow any style Greg would suggest.  There doesn't seem to be
much documentation about how this should be done yet.


Thomas (tglx) has already submitted a first series of doc patches a
few weeks ago. And AFAIK he might be working on posting the updates
soon, whenever his real time clock yields a few cycles away from real
time coding work ;)

See also these discussions with Linus [1][2][3], Thomas[4] and Greg[5]
on this and mostly related topics

[1] https://lkml.org/lkml/2017/11/2/715
[2] https://lkml.org/lkml/2017/11/25/125
[3] https://lkml.org/lkml/2017/11/25/133
[4] https://lkml.org/lkml/2017/11/2/805
[5] https://lkml.org/lkml/2017/10/19/165



OK, you convinced me.

Thanks,
David

Re: [PATCH v4 3/8] MIPS: Octeon: Add a global resource manager.

[David Daney]

On 12/01/2017 12:41 PM, Philippe Ombredanne wrote:

David,

On Fri, Dec 1, 2017 at 9:01 PM, David Daney  wrote:

On 12/01/2017 11:49 AM, Philippe Ombredanne wrote:


David, Greg,

On Fri, Dec 1, 2017 at 6:42 PM, David Daney 
wrote:


On 11/30/2017 11:53 PM, Philippe Ombredanne wrote:


[...]


--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * This file is subject to the terms and conditions of the GNU
General
Public
+ * License.  See the file "COPYING" in the main directory of this
archive
+ * for more details.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */




Since you nicely included an SPDX id, you would not need the
boilerplate anymore. e.g. these can go alright?




They may not be strictly speaking necessary, but I don't think they hurt
anything.  Unless there is a requirement to strip out the license text,
we
would stick with it as is.



I think the requirement is there and that would be much better for
everyone: keeping both is redundant and does not bring any value, does
it? Instead it kinda removes the benefits of having the SPDX id in the
first place IMHO.

Furthermore, as there have been already ~12K+ files cleaned up and
still over 60K files to go, it would really nice if new files could
adopt the new style: this way we will not have to revisit and repatch
them in the future.



I am happy to follow any style Greg would suggest.  There doesn't seem to be
much documentation about how this should be done yet.


Thomas (tglx) has already submitted a first series of doc patches a
few weeks ago. And AFAIK he might be working on posting the updates
soon, whenever his real time clock yields a few cycles away from real
time coding work ;)

See also these discussions with Linus [1][2][3], Thomas[4] and Greg[5]
on this and mostly related topics

[1] https://lkml.org/lkml/2017/11/2/715
[2] https://lkml.org/lkml/2017/11/25/125
[3] https://lkml.org/lkml/2017/11/25/133
[4] https://lkml.org/lkml/2017/11/2/805
[5] https://lkml.org/lkml/2017/10/19/165



OK, you convinced me.

Thanks,
David

Re: [PATCH v4 3/8] MIPS: Octeon: Add a global resource manager.

[David Daney]

On 12/01/2017 11:49 AM, Philippe Ombredanne wrote:

David, Greg,

On Fri, Dec 1, 2017 at 6:42 PM, David Daney <dda...@caviumnetworks.com> wrote:

On 11/30/2017 11:53 PM, Philippe Ombredanne wrote:

[...]

--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * This file is subject to the terms and conditions of the GNU General
Public
+ * License.  See the file "COPYING" in the main directory of this
archive
+ * for more details.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */



Since you nicely included an SPDX id, you would not need the
boilerplate anymore. e.g. these can go alright?



They may not be strictly speaking necessary, but I don't think they hurt
anything.  Unless there is a requirement to strip out the license text, we
would stick with it as is.


I think the requirement is there and that would be much better for
everyone: keeping both is redundant and does not bring any value, does
it? Instead it kinda removes the benefits of having the SPDX id in the
first place IMHO.

Furthermore, as there have been already ~12K+ files cleaned up and
still over 60K files to go, it would really nice if new files could
adopt the new style: this way we will not have to revisit and repatch
them in the future.



I am happy to follow any style Greg would suggest.  There doesn't seem 
to be much documentation about how this should be done yet.


David Daney

Re: [PATCH v4 3/8] MIPS: Octeon: Add a global resource manager.

[David Daney]

On 12/01/2017 11:49 AM, Philippe Ombredanne wrote:

David, Greg,

On Fri, Dec 1, 2017 at 6:42 PM, David Daney  wrote:

On 11/30/2017 11:53 PM, Philippe Ombredanne wrote:

[...]

--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * This file is subject to the terms and conditions of the GNU General
Public
+ * License.  See the file "COPYING" in the main directory of this
archive
+ * for more details.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */



Since you nicely included an SPDX id, you would not need the
boilerplate anymore. e.g. these can go alright?



They may not be strictly speaking necessary, but I don't think they hurt
anything.  Unless there is a requirement to strip out the license text, we
would stick with it as is.


I think the requirement is there and that would be much better for
everyone: keeping both is redundant and does not bring any value, does
it? Instead it kinda removes the benefits of having the SPDX id in the
first place IMHO.

Furthermore, as there have been already ~12K+ files cleaned up and
still over 60K files to go, it would really nice if new files could
adopt the new style: this way we will not have to revisit and repatch
them in the future.



I am happy to follow any style Greg would suggest.  There doesn't seem 
to be much documentation about how this should be done yet.


David Daney

Re: [PATCH v4 3/8] MIPS: Octeon: Add a global resource manager.

[David Daney]

On 11/30/2017 11:53 PM, Philippe Ombredanne wrote:

Carlos,

On Thu, Nov 30, 2017 at 11:53 PM, James Hogan <james.ho...@mips.com> wrote:

On Tue, Nov 28, 2017 at 04:55:35PM -0800, David Daney wrote:

From: Carlos Munoz <cmu...@cavium.com>

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
  arch/mips/cavium-octeon/Makefile   |   3 +-
  arch/mips/cavium-octeon/resource-mgr.c | 371 +
  arch/mips/include/asm/octeon/octeon.h  |  18 ++
  3 files changed, 391 insertions(+), 1 deletion(-)
  create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..0a299ab8719f 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,7 +9,8 @@
  # Copyright (C) 2005-2009 Cavium Networks
  #

-obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o \
+  resource-mgr.o


Maybe put that on a separate line like below.


  obj-y += dma-octeon.o
  obj-y += octeon-memcpy.o
  obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..ca25fa953402
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */


Since you nicely included an SPDX id, you would not need the
boilerplate anymore. e.g. these can go alright?


They may not be strictly speaking necessary, but I don't think they hurt 
anything.  Unless there is a requirement to strip out the license text, 
we would stick with it as is.





+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.

Re: [PATCH v4 3/8] MIPS: Octeon: Add a global resource manager.

[David Daney]

On 11/30/2017 11:53 PM, Philippe Ombredanne wrote:

Carlos,

On Thu, Nov 30, 2017 at 11:53 PM, James Hogan  wrote:

On Tue, Nov 28, 2017 at 04:55:35PM -0800, David Daney wrote:

From: Carlos Munoz 

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
  arch/mips/cavium-octeon/Makefile   |   3 +-
  arch/mips/cavium-octeon/resource-mgr.c | 371 +
  arch/mips/include/asm/octeon/octeon.h  |  18 ++
  3 files changed, 391 insertions(+), 1 deletion(-)
  create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..0a299ab8719f 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,7 +9,8 @@
  # Copyright (C) 2005-2009 Cavium Networks
  #

-obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o \
+  resource-mgr.o


Maybe put that on a separate line like below.


  obj-y += dma-octeon.o
  obj-y += octeon-memcpy.o
  obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..ca25fa953402
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */


Since you nicely included an SPDX id, you would not need the
boilerplate anymore. e.g. these can go alright?


They may not be strictly speaking necessary, but I don't think they hurt 
anything.  Unless there is a requirement to strip out the license text, 
we would stick with it as is.





+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.

Re: [PATCH v2] MIPS: Add nonxstack=on|off kernel parameter

[David Daney]

On 11/30/2017 05:06 AM, Miodrag Dinic wrote:

Hi James,


We do have PT_GNU_STACK flags set correctly, this feature is required to
workaround CPU revisions which do not have RIXI support.


RIXI support can be discovered programatically from CP0_Config3.RXI
(cpu_has_rixi in asm/cpu-features.h), so I don't follow why CPUs without
RIXI would require a kernel parameter.


The following patch introduced change in behavior with regards to
stack & heap execute-ability :
commit 1a770b85c1f1c1ee37afd7cef5237ffc4c970f04
Author: Paul Burton 
Date:   Fri Jul 8 11:06:20 2016 +0100

 MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present
 
 The stack and heap have both been executable by default on MIPS until

 now. This patch changes the default to be non-executable, but only for
 ELF binaries with a non-executable PT_GNU_STACK header present. This
 does apply to both the heap & the stack, despite the name PT_GNU_STACK,
 and this matches the behaviour of other architectures like ARM & x86.
 
 Current MIPS toolchains do not produce the PT_GNU_STACK header, which

 means that we can rely upon this patch not changing the behaviour of
 existing binaries. The new default will only take effect for newly
 compiled binaries once toolchains are updated to support PT_GNU_STACK,
 and since those binaries are newly compiled they can be compiled
 expecting the change in default behaviour. Again this matches the way in
 which the ARM & x86 architectures handled their implementations of
 non-executable memory.
 
 Signed-off-by: Paul Burton 

 Cc: Leonid Yegoshin 
 Cc: Maciej Rozycki 
 Cc: Faraz Shahbazker 
 Cc: Raghu Gandham 
 Cc: Matthew Fortune 
 Cc: linux-m...@linux-mips.org
 Patchwork: https://patchwork.linux-mips.org/patch/13765/
 Signed-off-by: Ralf Baechle 



When kernel is detecting the type of mapping it should apply :

fs/binfmt_elf.c:
...
if (elf_read_implies_exec(loc->elf_ex, executable_stack))
current->personality |= READ_IMPLIES_EXEC;
...

this effectively calls mips_elf_read_implies_exec() which performs a check:
...
if (!cpu_has_rixi) {
/* The CPU doesn't support non-executable memory */
return 1;
}

return 0;
}

This will in turn make stack & heap executable on processors without RIXI, which 
are practically all processors with MIPS ISA R < 6.



All Cavium processors since OCTEON Plus (more than ten years ago) 
support RIXI.



We would like to have an option to override this and force non-executable 
mappings for such systems.


This is what I don't understand.  If a system doesn't support XI, then 
no mapping can possibly be non-executable.


There may be some utility in disabling the use of the RIXI bits on 
systems that do support them.  But no command line can conjure 
functional RIXI on systems that don't support it.


Also, this does nothing for multi-threaded programs where libc sets the 
permissions on the thread stacks.


If you really need something, at a minimum, use the same parameter name 
that x86 uses.

Re: [PATCH v2] MIPS: Add nonxstack=on|off kernel parameter

[David Daney]

On 11/30/2017 05:06 AM, Miodrag Dinic wrote:

Hi James,


We do have PT_GNU_STACK flags set correctly, this feature is required to
workaround CPU revisions which do not have RIXI support.


RIXI support can be discovered programatically from CP0_Config3.RXI
(cpu_has_rixi in asm/cpu-features.h), so I don't follow why CPUs without
RIXI would require a kernel parameter.


The following patch introduced change in behavior with regards to
stack & heap execute-ability :
commit 1a770b85c1f1c1ee37afd7cef5237ffc4c970f04
Author: Paul Burton 
Date:   Fri Jul 8 11:06:20 2016 +0100

 MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present
 
 The stack and heap have both been executable by default on MIPS until

 now. This patch changes the default to be non-executable, but only for
 ELF binaries with a non-executable PT_GNU_STACK header present. This
 does apply to both the heap & the stack, despite the name PT_GNU_STACK,
 and this matches the behaviour of other architectures like ARM & x86.
 
 Current MIPS toolchains do not produce the PT_GNU_STACK header, which

 means that we can rely upon this patch not changing the behaviour of
 existing binaries. The new default will only take effect for newly
 compiled binaries once toolchains are updated to support PT_GNU_STACK,
 and since those binaries are newly compiled they can be compiled
 expecting the change in default behaviour. Again this matches the way in
 which the ARM & x86 architectures handled their implementations of
 non-executable memory.
 
 Signed-off-by: Paul Burton 

 Cc: Leonid Yegoshin 
 Cc: Maciej Rozycki 
 Cc: Faraz Shahbazker 
 Cc: Raghu Gandham 
 Cc: Matthew Fortune 
 Cc: linux-m...@linux-mips.org
 Patchwork: https://patchwork.linux-mips.org/patch/13765/
 Signed-off-by: Ralf Baechle 



When kernel is detecting the type of mapping it should apply :

fs/binfmt_elf.c:
...
if (elf_read_implies_exec(loc->elf_ex, executable_stack))
current->personality |= READ_IMPLIES_EXEC;
...

this effectively calls mips_elf_read_implies_exec() which performs a check:
...
if (!cpu_has_rixi) {
/* The CPU doesn't support non-executable memory */
return 1;
}

return 0;
}

This will in turn make stack & heap executable on processors without RIXI, which 
are practically all processors with MIPS ISA R < 6.



All Cavium processors since OCTEON Plus (more than ten years ago) 
support RIXI.



We would like to have an option to override this and force non-executable 
mappings for such systems.


This is what I don't understand.  If a system doesn't support XI, then 
no mapping can possibly be non-executable.


There may be some utility in disabling the use of the RIXI bits on 
systems that do support them.  But no command line can conjure 
functional RIXI on systems that don't support it.


Also, this does nothing for multi-threaded programs where libc sets the 
permissions on the thread stacks.


If you really need something, at a minimum, use the same parameter name 
that x86 uses.

Re: [PATCH v4 3/8] MIPS: Octeon: Add a global resource manager.

[David Daney]

On 11/30/2017 02:53 PM, James Hogan wrote:

On Tue, Nov 28, 2017 at 04:55:35PM -0800, David Daney wrote:

From: Carlos Munoz <cmu...@cavium.com>

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
  arch/mips/cavium-octeon/Makefile   |   3 +-
  arch/mips/cavium-octeon/resource-mgr.c | 371 +
  arch/mips/include/asm/octeon/octeon.h  |  18 ++
  3 files changed, 391 insertions(+), 1 deletion(-)
  create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..0a299ab8719f 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,7 +9,8 @@
  # Copyright (C) 2005-2009 Cavium Networks
  #
  
-obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o

+obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o \
+resource-mgr.o


Maybe put that on a separate line like below.


OK




  obj-y += dma-octeon.o
  obj-y += octeon-memcpy.o
  obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..ca25fa953402
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   unsigned int tmp;
+   u64 lock = (u64)_mgr_info->rlock;


presumably this could be a u32 *, avoid the cast to u64, and still work
just fine below.


I will rewrite to just use cmpxchg()





+
+   __asm__ __volatile__(
+   ".set noreorder\n"
+   "1: ll   %[tmp], 0(%[addr])\n"
+   "   bnez %[tmp], 1b\n"
+   "   li   %[tmp], 1\n"


I believe the convention for .S files is for instructions in branch
delay slots to be indented an additional space for readability. Maybe
that would be worthwhile here.


+   "   sc   %[tmp], 0(%[addr])\n"
+   "   beqz %[tmp], 1b\n"
+   "   nop\n"


and here also.


+   ".set reorder\n" :


nit: strictly speaking there's no need for \n on the last line.


+   [tmp] "="(tmp) :
+   [addr] "r"(lock) :
+   "memory");


minor style thing: its far more common to have : at the beginning of the
line rather than the end.


+}
+
+static void res_mgr_unlock(void)
+{
+   u64 lock = (u64)_mgr_info->rlock;


same again



Will rewrite to use WRITE_ONCE().


+
+   /* Wait until all resource operations finish before unlocking. */
+   mb();
+   __asm__ __volatile__(
+   "sw $0, 0(%[addr])\n" : :
+   [addr] "r"(lock) :
+   "memory");
+
+   /* Force a write buffer flush. */
+   mb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource - Create a resource.
+ * @tag: 

Re: [PATCH v4 3/8] MIPS: Octeon: Add a global resource manager.

[David Daney]

On 11/30/2017 02:53 PM, James Hogan wrote:

On Tue, Nov 28, 2017 at 04:55:35PM -0800, David Daney wrote:

From: Carlos Munoz 

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
  arch/mips/cavium-octeon/Makefile   |   3 +-
  arch/mips/cavium-octeon/resource-mgr.c | 371 +
  arch/mips/include/asm/octeon/octeon.h  |  18 ++
  3 files changed, 391 insertions(+), 1 deletion(-)
  create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e542959a..0a299ab8719f 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,7 +9,8 @@
  # Copyright (C) 2005-2009 Cavium Networks
  #
  
-obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o

+obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o \
+resource-mgr.o


Maybe put that on a separate line like below.


OK




  obj-y += dma-octeon.o
  obj-y += octeon-memcpy.o
  obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index ..ca25fa953402
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   unsigned int tmp;
+   u64 lock = (u64)_mgr_info->rlock;


presumably this could be a u32 *, avoid the cast to u64, and still work
just fine below.


I will rewrite to just use cmpxchg()





+
+   __asm__ __volatile__(
+   ".set noreorder\n"
+   "1: ll   %[tmp], 0(%[addr])\n"
+   "   bnez %[tmp], 1b\n"
+   "   li   %[tmp], 1\n"


I believe the convention for .S files is for instructions in branch
delay slots to be indented an additional space for readability. Maybe
that would be worthwhile here.


+   "   sc   %[tmp], 0(%[addr])\n"
+   "   beqz %[tmp], 1b\n"
+   "   nop\n"


and here also.


+   ".set reorder\n" :


nit: strictly speaking there's no need for \n on the last line.


+   [tmp] "="(tmp) :
+   [addr] "r"(lock) :
+   "memory");


minor style thing: its far more common to have : at the beginning of the
line rather than the end.


+}
+
+static void res_mgr_unlock(void)
+{
+   u64 lock = (u64)_mgr_info->rlock;


same again



Will rewrite to use WRITE_ONCE().


+
+   /* Wait until all resource operations finish before unlocking. */
+   mb();
+   __asm__ __volatile__(
+   "sw $0, 0(%[addr])\n" : :
+   [addr] "r"(lock) :
+   "memory");
+
+   /* Force a write buffer flush. */
+   mb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source

Re: [PATCH v4 2/8] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

On 11/30/2017 02:56 PM, James Hogan wrote:

On Thu, Nov 30, 2017 at 01:49:43PM -0800, David Daney wrote:

On 11/30/2017 01:36 PM, James Hogan wrote:

On Tue, Nov 28, 2017 at 04:55:34PM -0800, David Daney wrote:

Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
   arch/mips/cavium-octeon/setup.c   |  6 ++
   arch/mips/include/asm/octeon/octeon.h | 12 ++--
   2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
   #else
cvmmemctl.s.cvmsegenak = 0;
   #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;


Out of curiosity, is there significance to the value 2 and associated
virtual address 0x8100, or is it pretty arbitrary?


Yes, there is significance.

CPU local memory starts at 0x8000, each line is 0x80 bytes.
so the 2nd line starts at 0x8100


What I mean is, why is 2 chosen instead of any other value?


That is explained in the change log of patch 5/8:


1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE



Cheers
James

Re: [PATCH v4 2/8] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

On 11/30/2017 02:56 PM, James Hogan wrote:

On Thu, Nov 30, 2017 at 01:49:43PM -0800, David Daney wrote:

On 11/30/2017 01:36 PM, James Hogan wrote:

On Tue, Nov 28, 2017 at 04:55:34PM -0800, David Daney wrote:

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
   arch/mips/cavium-octeon/setup.c   |  6 ++
   arch/mips/include/asm/octeon/octeon.h | 12 ++--
   2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
   #else
cvmmemctl.s.cvmsegenak = 0;
   #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;


Out of curiosity, is there significance to the value 2 and associated
virtual address 0x8100, or is it pretty arbitrary?


Yes, there is significance.

CPU local memory starts at 0x8000, each line is 0x80 bytes.
so the 2nd line starts at 0x8100


What I mean is, why is 2 chosen instead of any other value?


That is explained in the change log of patch 5/8:


1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE



Cheers
James

Re: [PATCH v4 2/8] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

On 11/30/2017 01:36 PM, James Hogan wrote:

On Tue, Nov 28, 2017 at 04:55:34PM -0800, David Daney wrote:

From: Carlos Munoz <cmu...@cavium.com>

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
   (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
   (up to 128) of data to the I/O device and then return a
   variable length (up to 128 bytes) response from the IOI device.


Should that be "I/O"?


Yes, I will fix the changelog.






Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
  arch/mips/cavium-octeon/setup.c   |  6 ++
  arch/mips/include/asm/octeon/octeon.h | 12 ++--
  2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
  #else
cvmmemctl.s.cvmsegenak = 0;
  #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;


Out of curiosity, is there significance to the value 2 and associated
virtual address 0x8100, or is it pretty arbitrary?


Yes, there is significance.

CPU local memory starts at 0x8000, each line is 0x80 bytes. 
so the 2nd line starts at 0x8100






+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
  };


Regardless, the patch looks good to me.

Reviewed-by: James Hogan <jho...@kernel.org>

Cheers
James

Re: [PATCH v4 2/8] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[David Daney]

On 11/30/2017 01:36 PM, James Hogan wrote:

On Tue, Nov 28, 2017 at 04:55:34PM -0800, David Daney wrote:

From: Carlos Munoz 

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
   (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
   (up to 128) of data to the I/O device and then return a
   variable length (up to 128 bytes) response from the IOI device.


Should that be "I/O"?


Yes, I will fix the changelog.






Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
Signed-off-by: David Daney 
---
  arch/mips/cavium-octeon/setup.c   |  6 ++
  arch/mips/include/asm/octeon/octeon.h | 12 ++--
  2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
  #else
cvmmemctl.s.cvmsegenak = 0;
  #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;


Out of curiosity, is there significance to the value 2 and associated
virtual address 0x8100, or is it pretty arbitrary?


Yes, there is significance.

CPU local memory starts at 0x8000, each line is 0x80 bytes. 
so the 2nd line starts at 0x8100






+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
  };


Regardless, the patch looks good to me.

Reviewed-by: James Hogan 

Cheers
James

Re: [PATCH] dt-bindings: Remove leading 0x from bindings notation

[David Daney]

On 11/29/2017 12:55 PM, Mathieu Malaterre wrote:

Improve the binding example by removing all the leading 0x to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have leading "0x"


How does it fix the warnings?  You are not changing the .dts files that 
are compiled.


This may also cause the binding documentation to differ from the reality 
of what the actual device trees contain.




Converted using the following command:

find Documentation/devicetree/bindings -name "*.txt" -exec sed -i -e 's/([^ 
])\@0x([0-9a-f])/$1\@$2/g' {} +

This is a follow up to commit 48c926cd3414

Signed-off-by: Mathieu Malaterre 
---
I've also checked using the original perl command that I did not introduce:

Warning (unit_address_format): Node /XXX unit name should not have leading 0s

  Documentation/devicetree/bindings/arm/ccn.txt|  2 +-
  Documentation/devicetree/bindings/arm/omap/crossbar.txt  |  2 +-
  .../devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt  |  2 +-
  Documentation/devicetree/bindings/clock/axi-clkgen.txt   |  2 +-
  .../devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt |  2 +-
  Documentation/devicetree/bindings/clock/exynos4-clock.txt|  2 +-
  Documentation/devicetree/bindings/clock/exynos5250-clock.txt |  2 +-
  Documentation/devicetree/bindings/clock/exynos5410-clock.txt |  2 +-
  Documentation/devicetree/bindings/clock/exynos5420-clock.txt |  2 +-
  Documentation/devicetree/bindings/clock/exynos5440-clock.txt |  2 +-
  .../devicetree/bindings/clock/ti-keystone-pllctrl.txt|  2 +-
  Documentation/devicetree/bindings/clock/zx296702-clk.txt |  4 ++--
  Documentation/devicetree/bindings/crypto/fsl-sec4.txt|  4 ++--
  .../devicetree/bindings/devfreq/event/rockchip-dfi.txt   |  2 +-
  Documentation/devicetree/bindings/display/atmel,lcdc.txt |  4 ++--
  Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt|  4 ++--
  Documentation/devicetree/bindings/dma/zxdma.txt  |  2 +-
  Documentation/devicetree/bindings/gpio/gpio-altera.txt   |  2 +-
  Documentation/devicetree/bindings/i2c/i2c-jz4780.txt |  2 +-
  Documentation/devicetree/bindings/iio/pressure/hp03.txt  |  2 +-
  .../devicetree/bindings/input/touchscreen/bu21013.txt|  2 +-
  .../devicetree/bindings/interrupt-controller/arm,gic.txt |  4 ++--
  .../bindings/interrupt-controller/img,meta-intc.txt  |  2 +-
  .../bindings/interrupt-controller/img,pdc-intc.txt   |  2 +-
  .../bindings/interrupt-controller/st,spear3xx-shirq.txt  |  2 +-
  Documentation/devicetree/bindings/mailbox/altera-mailbox.txt |  6 +++---
  .../devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt  |  2 +-
  Documentation/devicetree/bindings/media/exynos5-gsc.txt  |  2 +-
  Documentation/devicetree/bindings/media/mediatek-vcodec.txt  |  2 +-
  Documentation/devicetree/bindings/media/rcar_vin.txt |  2 +-
  Documentation/devicetree/bindings/media/samsung-fimc.txt |  2 +-
  Documentation/devicetree/bindings/media/sh_mobile_ceu.txt|  2 +-
  Documentation/devicetree/bindings/media/video-interfaces.txt | 10 +-
  .../devicetree/bindings/memory-controllers/ti/emif.txt   |  2 +-
  .../devicetree/bindings/mfd/ti-keystone-devctrl.txt  |  2 +-
  Documentation/devicetree/bindings/misc/brcm,kona-smc.txt |  2 +-
  Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt|  2 +-
  Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt   |  2 +-
  Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt  |  4 ++--
  Documentation/devicetree/bindings/mtd/gpmc-nor.txt   |  6 +++---
  Documentation/devicetree/bindings/mtd/mtk-nand.txt   |  2 +-
  Documentation/devicetree/bindings/net/altera_tse.txt |  4 ++--
  Documentation/devicetree/bindings/net/mdio.txt   |  2 +-
  Documentation/devicetree/bindings/net/socfpga-dwmac.txt  |  2 +-
  Documentation/devicetree/bindings/nios2/nios2.txt|  2 +-
  Documentation/devicetree/bindings/pci/altera-pcie.txt|  2 +-
  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt |  2 +-
  Documentation/devicetree/bindings/pci/hisilicon-pcie.txt |  2 +-
  Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt  |  2 +-
  .../devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt   |  2 +-
  Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt |  4 ++--
  Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt   |  2 +-
  .../devicetree/bindings/pinctrl/rockchip,pinctrl.txt |  4 ++--
  Documentation/devicetree/bindings/regulator/regulator.txt|  2 +-
  Documentation/devicetree/bindings/serial/efm32-uart.txt  |  2 +-
  .../devicetree/bindings/serio/allwinner,sun4i-ps2.txt|  2 +-
  .../devicetree/bindings/soc/ti/keystone-navigator-qmss.txt   |  2 +-
  Documentation/devicetree/bindings/sound/adi,axi-i2s.txt  |  2 +-
  

Re: [PATCH] dt-bindings: Remove leading 0x from bindings notation

[David Daney]

On 11/29/2017 12:55 PM, Mathieu Malaterre wrote:

Improve the binding example by removing all the leading 0x to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have leading "0x"


How does it fix the warnings?  You are not changing the .dts files that 
are compiled.


This may also cause the binding documentation to differ from the reality 
of what the actual device trees contain.




Converted using the following command:

find Documentation/devicetree/bindings -name "*.txt" -exec sed -i -e 's/([^ 
])\@0x([0-9a-f])/$1\@$2/g' {} +

This is a follow up to commit 48c926cd3414

Signed-off-by: Mathieu Malaterre 
---
I've also checked using the original perl command that I did not introduce:

Warning (unit_address_format): Node /XXX unit name should not have leading 0s

  Documentation/devicetree/bindings/arm/ccn.txt|  2 +-
  Documentation/devicetree/bindings/arm/omap/crossbar.txt  |  2 +-
  .../devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt  |  2 +-
  Documentation/devicetree/bindings/clock/axi-clkgen.txt   |  2 +-
  .../devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt |  2 +-
  Documentation/devicetree/bindings/clock/exynos4-clock.txt|  2 +-
  Documentation/devicetree/bindings/clock/exynos5250-clock.txt |  2 +-
  Documentation/devicetree/bindings/clock/exynos5410-clock.txt |  2 +-
  Documentation/devicetree/bindings/clock/exynos5420-clock.txt |  2 +-
  Documentation/devicetree/bindings/clock/exynos5440-clock.txt |  2 +-
  .../devicetree/bindings/clock/ti-keystone-pllctrl.txt|  2 +-
  Documentation/devicetree/bindings/clock/zx296702-clk.txt |  4 ++--
  Documentation/devicetree/bindings/crypto/fsl-sec4.txt|  4 ++--
  .../devicetree/bindings/devfreq/event/rockchip-dfi.txt   |  2 +-
  Documentation/devicetree/bindings/display/atmel,lcdc.txt |  4 ++--
  Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt|  4 ++--
  Documentation/devicetree/bindings/dma/zxdma.txt  |  2 +-
  Documentation/devicetree/bindings/gpio/gpio-altera.txt   |  2 +-
  Documentation/devicetree/bindings/i2c/i2c-jz4780.txt |  2 +-
  Documentation/devicetree/bindings/iio/pressure/hp03.txt  |  2 +-
  .../devicetree/bindings/input/touchscreen/bu21013.txt|  2 +-
  .../devicetree/bindings/interrupt-controller/arm,gic.txt |  4 ++--
  .../bindings/interrupt-controller/img,meta-intc.txt  |  2 +-
  .../bindings/interrupt-controller/img,pdc-intc.txt   |  2 +-
  .../bindings/interrupt-controller/st,spear3xx-shirq.txt  |  2 +-
  Documentation/devicetree/bindings/mailbox/altera-mailbox.txt |  6 +++---
  .../devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt  |  2 +-
  Documentation/devicetree/bindings/media/exynos5-gsc.txt  |  2 +-
  Documentation/devicetree/bindings/media/mediatek-vcodec.txt  |  2 +-
  Documentation/devicetree/bindings/media/rcar_vin.txt |  2 +-
  Documentation/devicetree/bindings/media/samsung-fimc.txt |  2 +-
  Documentation/devicetree/bindings/media/sh_mobile_ceu.txt|  2 +-
  Documentation/devicetree/bindings/media/video-interfaces.txt | 10 +-
  .../devicetree/bindings/memory-controllers/ti/emif.txt   |  2 +-
  .../devicetree/bindings/mfd/ti-keystone-devctrl.txt  |  2 +-
  Documentation/devicetree/bindings/misc/brcm,kona-smc.txt |  2 +-
  Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt|  2 +-
  Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt   |  2 +-
  Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt  |  4 ++--
  Documentation/devicetree/bindings/mtd/gpmc-nor.txt   |  6 +++---
  Documentation/devicetree/bindings/mtd/mtk-nand.txt   |  2 +-
  Documentation/devicetree/bindings/net/altera_tse.txt |  4 ++--
  Documentation/devicetree/bindings/net/mdio.txt   |  2 +-
  Documentation/devicetree/bindings/net/socfpga-dwmac.txt  |  2 +-
  Documentation/devicetree/bindings/nios2/nios2.txt|  2 +-
  Documentation/devicetree/bindings/pci/altera-pcie.txt|  2 +-
  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt |  2 +-
  Documentation/devicetree/bindings/pci/hisilicon-pcie.txt |  2 +-
  Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt  |  2 +-
  .../devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt   |  2 +-
  Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt |  4 ++--
  Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt   |  2 +-
  .../devicetree/bindings/pinctrl/rockchip,pinctrl.txt |  4 ++--
  Documentation/devicetree/bindings/regulator/regulator.txt|  2 +-
  Documentation/devicetree/bindings/serial/efm32-uart.txt  |  2 +-
  .../devicetree/bindings/serio/allwinner,sun4i-ps2.txt|  2 +-
  .../devicetree/bindings/soc/ti/keystone-navigator-qmss.txt   |  2 +-
  Documentation/devicetree/bindings/sound/adi,axi-i2s.txt  |  2 +-