Re: [PATCH v3] PCI/AER: Enable reporting for ports enumerated after AER driver registration

[Dongdong Liu]

在 2018/10/11 23:57, Keith Busch 写道:

On Thu, Oct 11, 2018 at 08:26:18AM -0700, Bjorn Helgaas wrote:

From: Bjorn Helgaas 

Previously we enabled AER error reporting only for Switch Ports that were
enumerated prior to registering the AER service driver.  Switch Ports
enumerated after AER driver registration were left with error reporting
disabled.

A common order, which works correctly, is that we enumerate devices before
registering portdrv and the AER driver:

  - Enumerate all the devices at boot-time

  - Register portdrv and bind it to all Root Ports and Switch Ports, which
disables error reporting for these Ports

  - Register AER service driver and bind it to all Root Ports, which
enables error reporting for the Root Ports and any Switch Ports below
them

But if we enumerate devices *after* registering portdrv and the AER driver,
e.g., if a host bridge driver is loaded as a module, error reporting is not
enabled correctly:

  - Register portdrv and AER driver (this happens at boot-time)

  - Enumerate a Root Port

  - Bind portdrv to Root Port, disabling its error reporting

  - Bind AER service driver to Root Port, enabling error reporting for it
and its children (there are no children, since we haven't enumerated
them yet)

  - Enumerate Switch Port below the Root Port

  - Bind portdrv to Switch Port, disabling its error reporting

  - AER service driver doesn't bind to Switch Ports, so error reporting
remains disabled

Hot-adding a Switch fails similarly: error reporting is enabled correctly
for the Root Port, but when the Switch is enumerated, the AER service
driver doesn't claim it, so there's nothing to enable error reporting for
the Switch Ports.

Change the AER service driver so it binds to *all* PCIe Ports, including
Switch Upstream and Downstream Ports.  Enable AER error reporting for all
these Ports, but not for any children.

Link: 
https://lore.kernel.org/linux-pci/1536085989-2956-1-git-send-email-jonathan.derr...@intel.com
Based-on-patch-by: Jon Derrick 
Signed-off-by: Bjorn Helgaas 
---
 drivers/pci/pcie/aer.c |   16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 90b53abf621d..c40c6607849b 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -1316,12 +1316,6 @@ static void aer_enable_rootport(struct aer_rpc *rpc)
pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, );
pci_write_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, reg32);

-   /*
-* Enable error reporting for the root port device and downstream port
-* devices.
-*/
-   set_downstream_devices_error_reporting(pdev, true);
-
/* Enable Root Port's interrupt in response to error messages */
pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, );
reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
@@ -1378,10 +1372,17 @@ static void aer_remove(struct pcie_device *dev)
  */
 static int aer_probe(struct pcie_device *dev)
 {
+   struct pci_dev *pdev = dev->port;
+   int type = pci_pcie_type(pdev);
int status;
struct aer_rpc *rpc;
struct device *device = >device;

+   if (type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM) {
+   pci_enable_pcie_error_reporting(pdev);
+   return 0;
+   }


I think we need to either return an error in this case so that the
pcie_device won't be eligable for the .remove() callback, or add a
similiar type check in aer_remove().



It seems aer_root_reset() also will be called for downstream port(err.c 
driver->reset_link(dev)),
but aer_root_reset is only for root port.

static struct pcie_port_service_driver aerdriver = {
.name   = "aer",
.port_type  = PCIE_ANY_PORT,
.service= PCIE_PORT_SERVICE_AER,

.probe  = aer_probe,
.remove = aer_remove,
.reset_link = aer_root_reset,
};

Thanks,
Dongdong

.

Re: [PATCH v3] PCI/AER: Enable reporting for ports enumerated after AER driver registration

[Dongdong Liu]

在 2018/10/11 23:57, Keith Busch 写道:

On Thu, Oct 11, 2018 at 08:26:18AM -0700, Bjorn Helgaas wrote:

From: Bjorn Helgaas 

Previously we enabled AER error reporting only for Switch Ports that were
enumerated prior to registering the AER service driver.  Switch Ports
enumerated after AER driver registration were left with error reporting
disabled.

A common order, which works correctly, is that we enumerate devices before
registering portdrv and the AER driver:

  - Enumerate all the devices at boot-time

  - Register portdrv and bind it to all Root Ports and Switch Ports, which
disables error reporting for these Ports

  - Register AER service driver and bind it to all Root Ports, which
enables error reporting for the Root Ports and any Switch Ports below
them

But if we enumerate devices *after* registering portdrv and the AER driver,
e.g., if a host bridge driver is loaded as a module, error reporting is not
enabled correctly:

  - Register portdrv and AER driver (this happens at boot-time)

  - Enumerate a Root Port

  - Bind portdrv to Root Port, disabling its error reporting

  - Bind AER service driver to Root Port, enabling error reporting for it
and its children (there are no children, since we haven't enumerated
them yet)

  - Enumerate Switch Port below the Root Port

  - Bind portdrv to Switch Port, disabling its error reporting

  - AER service driver doesn't bind to Switch Ports, so error reporting
remains disabled

Hot-adding a Switch fails similarly: error reporting is enabled correctly
for the Root Port, but when the Switch is enumerated, the AER service
driver doesn't claim it, so there's nothing to enable error reporting for
the Switch Ports.

Change the AER service driver so it binds to *all* PCIe Ports, including
Switch Upstream and Downstream Ports.  Enable AER error reporting for all
these Ports, but not for any children.

Link: 
https://lore.kernel.org/linux-pci/1536085989-2956-1-git-send-email-jonathan.derr...@intel.com
Based-on-patch-by: Jon Derrick 
Signed-off-by: Bjorn Helgaas 
---
 drivers/pci/pcie/aer.c |   16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 90b53abf621d..c40c6607849b 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -1316,12 +1316,6 @@ static void aer_enable_rootport(struct aer_rpc *rpc)
pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, );
pci_write_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, reg32);

-   /*
-* Enable error reporting for the root port device and downstream port
-* devices.
-*/
-   set_downstream_devices_error_reporting(pdev, true);
-
/* Enable Root Port's interrupt in response to error messages */
pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, );
reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
@@ -1378,10 +1372,17 @@ static void aer_remove(struct pcie_device *dev)
  */
 static int aer_probe(struct pcie_device *dev)
 {
+   struct pci_dev *pdev = dev->port;
+   int type = pci_pcie_type(pdev);
int status;
struct aer_rpc *rpc;
struct device *device = >device;

+   if (type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM) {
+   pci_enable_pcie_error_reporting(pdev);
+   return 0;
+   }


I think we need to either return an error in this case so that the
pcie_device won't be eligable for the .remove() callback, or add a
similiar type check in aer_remove().



It seems aer_root_reset() also will be called for downstream port(err.c 
driver->reset_link(dev)),
but aer_root_reset is only for root port.

static struct pcie_port_service_driver aerdriver = {
.name   = "aer",
.port_type  = PCIE_ANY_PORT,
.service= PCIE_PORT_SERVICE_AER,

.probe  = aer_probe,
.remove = aer_remove,
.reset_link = aer_root_reset,
};

Thanks,
Dongdong

.

Re: [PATCH] PCI/portdrv: Enable error reporting on managed ports

[Dongdong Liu]

Hi Bjorn


commit 15a6711649915ca3e9d1086dc88ff4b616b99aac
Author: Bjorn Helgaas 
Date:   Tue Oct 9 17:25:25 2018 -0500

PCI/AER: Enable reporting for ports enumerated after AER driver registration

Previously we enabled AER error reporting only for Switch Ports that were
enumerated prior to registering the AER service driver.  Switch Ports
enumerated after AER driver registration were left with error reporting
disabled.

A common order, which works correctly, is that we enumerate devices before
registering portdrv and the AER driver:

  - Enumerate all the devices at boot-time

  - Register portdrv and bind it to all Root Ports and Switch Ports, which
disables error reporting for these Ports

  - Register AER service driver and bind it to all Root Ports, which
enables error reporting for the Root Ports and any Switch Ports below
them

But if we enumerate devices *after* registering portdrv and the AER driver,
e.g., if a host bridge driver is loaded as a module, error reporting is not
enabled correctly:

  - Register portdrv and AER driver (this happens at boot-time)

  - Enumerate a Root Port

  - Bind portdrv to Root Port, disabling its error reporting

  - Bind AER service driver to Root Port, enabling error reporting for it
and its children (none, since we haven't enumerated them yet)

  - Enumerate Switch Port below the Root Port

  - Bind portdrv to Switch Port, disabling its error reporting

  - AER service driver doesn't bind to Switch Ports, so error reporting
remains disabled

Hot-adding a Switch fails similarly: error reporting is enabled correctly
for the Root Port, but when the Switch is enumerated, the AER service
driver doesn't claim it, so there's nothing to enable error reporting for
the Switch Ports.

Change the AER service driver so it binds to *all* PCIe ports, including
Switch Upstream and Downstream Ports.  For Switch Ports, enable AER error
reporting.

Link: 
https://lore.kernel.org/linux-pci/1536085989-2956-1-git-send-email-jonathan.derr...@intel.com
Based-on-patch-by: Jon Derrick 
Signed-off-by: Bjorn Helgaas 

diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 90b53abf621d..fe6c16461367 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -1316,12 +1316,6 @@ static void aer_enable_rootport(struct aer_rpc *rpc)
pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, );
pci_write_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, reg32);

-   /*
-* Enable error reporting for the root port device and downstream port
-* devices.
-*/
-   set_downstream_devices_error_reporting(pdev, true);
-


Delete the code will also disable error reporting for the root port as
the portdrv to Root Port has disabled its error reporting,
so need to enable enable error reporting for the root port.
+pci_enable_pcie_error_reporting(pdev);

The patch looks good to me except this.

Thanks
Dongdong.


/* Enable Root Port's interrupt in response to error messages */
pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, );
reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
@@ -1378,10 +1372,17 @@ static void aer_remove(struct pcie_device *dev)
  */
 static int aer_probe(struct pcie_device *dev)
 {
+   struct pci_dev *pdev = dev->port;
+   int type = pci_pcie_type(pdev);
int status;
struct aer_rpc *rpc;
struct device *device = >device;

+   if (type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM) {
+   pci_enable_pcie_error_reporting(pdev);
+   return 0;
+   }
+
rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
if (!rpc) {
dev_printk(KERN_DEBUG, device, "alloc AER rpc failed\n");
@@ -1439,7 +1440,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev 
*dev)

 static struct pcie_port_service_driver aerdriver = {
.name   = "aer",
-   .port_type  = PCI_EXP_TYPE_ROOT_PORT,
+   .port_type  = PCIE_ANY_PORT,
.service= PCIE_PORT_SERVICE_AER,

.probe  = aer_probe,

.

Re: [PATCH] PCI/portdrv: Enable error reporting on managed ports

[Dongdong Liu]

Hi Bjorn


commit 15a6711649915ca3e9d1086dc88ff4b616b99aac
Author: Bjorn Helgaas 
Date:   Tue Oct 9 17:25:25 2018 -0500

PCI/AER: Enable reporting for ports enumerated after AER driver registration

Previously we enabled AER error reporting only for Switch Ports that were
enumerated prior to registering the AER service driver.  Switch Ports
enumerated after AER driver registration were left with error reporting
disabled.

A common order, which works correctly, is that we enumerate devices before
registering portdrv and the AER driver:

  - Enumerate all the devices at boot-time

  - Register portdrv and bind it to all Root Ports and Switch Ports, which
disables error reporting for these Ports

  - Register AER service driver and bind it to all Root Ports, which
enables error reporting for the Root Ports and any Switch Ports below
them

But if we enumerate devices *after* registering portdrv and the AER driver,
e.g., if a host bridge driver is loaded as a module, error reporting is not
enabled correctly:

  - Register portdrv and AER driver (this happens at boot-time)

  - Enumerate a Root Port

  - Bind portdrv to Root Port, disabling its error reporting

  - Bind AER service driver to Root Port, enabling error reporting for it
and its children (none, since we haven't enumerated them yet)

  - Enumerate Switch Port below the Root Port

  - Bind portdrv to Switch Port, disabling its error reporting

  - AER service driver doesn't bind to Switch Ports, so error reporting
remains disabled

Hot-adding a Switch fails similarly: error reporting is enabled correctly
for the Root Port, but when the Switch is enumerated, the AER service
driver doesn't claim it, so there's nothing to enable error reporting for
the Switch Ports.

Change the AER service driver so it binds to *all* PCIe ports, including
Switch Upstream and Downstream Ports.  For Switch Ports, enable AER error
reporting.

Link: 
https://lore.kernel.org/linux-pci/1536085989-2956-1-git-send-email-jonathan.derr...@intel.com
Based-on-patch-by: Jon Derrick 
Signed-off-by: Bjorn Helgaas 

diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 90b53abf621d..fe6c16461367 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -1316,12 +1316,6 @@ static void aer_enable_rootport(struct aer_rpc *rpc)
pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, );
pci_write_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, reg32);

-   /*
-* Enable error reporting for the root port device and downstream port
-* devices.
-*/
-   set_downstream_devices_error_reporting(pdev, true);
-


Delete the code will also disable error reporting for the root port as
the portdrv to Root Port has disabled its error reporting,
so need to enable enable error reporting for the root port.
+pci_enable_pcie_error_reporting(pdev);

The patch looks good to me except this.

Thanks
Dongdong.


/* Enable Root Port's interrupt in response to error messages */
pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, );
reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
@@ -1378,10 +1372,17 @@ static void aer_remove(struct pcie_device *dev)
  */
 static int aer_probe(struct pcie_device *dev)
 {
+   struct pci_dev *pdev = dev->port;
+   int type = pci_pcie_type(pdev);
int status;
struct aer_rpc *rpc;
struct device *device = >device;

+   if (type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM) {
+   pci_enable_pcie_error_reporting(pdev);
+   return 0;
+   }
+
rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
if (!rpc) {
dev_printk(KERN_DEBUG, device, "alloc AER rpc failed\n");
@@ -1439,7 +1440,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev 
*dev)

 static struct pcie_port_service_driver aerdriver = {
.name   = "aer",
-   .port_type  = PCI_EXP_TYPE_ROOT_PORT,
+   .port_type  = PCIE_ANY_PORT,
.service= PCIE_PORT_SERVICE_AER,

.probe  = aer_probe,

.

Re: [PATCH V3 2/2] acpi: apei: call into AER handling regardless of severity

[Dongdong Liu]

在 2017/11/9 3:13, Tyler Baicar 写道:

Currently the GHES code only calls into the AER driver for
recoverable type errors. This is incorrect because errors of
other severities do not get logged by the AER driver and do not
get exposed to user space via the AER trace event. So, call
into the AER driver for PCIe errors regardless of the severity


It will also call do_recovery() regardless of the severity for AER correctable 
errors.
Correctable errors include those error conditions where hardware can recover 
without any loss of information.
Hardware corrects these errors and software intervention is not required.
So we'd better modify the code as below.
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c 
b/drivers/pci/pcie/aer/aerdrv_core.c
index 7448052..a7f77549 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -633,7 +633,8 @@ static void aer_recover_work_func(struct work_struct *work)
continue;
}
cper_print_aer(pdev, entry.severity, entry.regs);
-   do_recovery(pdev, entry.severity);
+ if(entry.severity != AER_CORRECTABLE)
+ do_recovery(pdev, entry.severity);
pci_dev_put(pdev);
}
 }

Thanks,
Dongdong


Signed-off-by: Tyler Baicar 
---
 drivers/acpi/apei/ghes.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index 839c3d5..bb65fa6 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -458,14 +458,12 @@ static void ghes_handle_memory_failure(struct 
acpi_hest_generic_data *gdata, int
 #endif
 }

-static void ghes_handle_aer(struct acpi_hest_generic_data *gdata, int sev, int 
sec_sev)
+static void ghes_handle_aer(struct acpi_hest_generic_data *gdata)
 {
 #ifdef CONFIG_ACPI_APEI_PCIEAER
struct cper_sec_pcie *pcie_err = acpi_hest_get_payload(gdata);

-   if (sev == GHES_SEV_RECOVERABLE &&
-   sec_sev == GHES_SEV_RECOVERABLE &&
-   pcie_err->validation_bits & CPER_PCIE_VALID_DEVICE_ID &&
+   if (pcie_err->validation_bits & CPER_PCIE_VALID_DEVICE_ID &&
pcie_err->validation_bits & CPER_PCIE_VALID_AER_INFO) {
unsigned int devfn;
int aer_severity;
@@ -519,7 +517,7 @@ static void ghes_do_proc(struct ghes *ghes,
ghes_handle_memory_failure(gdata, sev);
}
else if (guid_equal(sec_type, _SEC_PCIE)) {
-   ghes_handle_aer(gdata, sev, sec_sev);
+   ghes_handle_aer(gdata);
}
else if (guid_equal(sec_type, _SEC_PROC_ARM)) {
struct cper_sec_proc_arm *err = 
acpi_hest_get_payload(gdata);

Re: [PATCH V3 2/2] acpi: apei: call into AER handling regardless of severity

[Dongdong Liu]

在 2017/11/9 3:13, Tyler Baicar 写道:

Currently the GHES code only calls into the AER driver for
recoverable type errors. This is incorrect because errors of
other severities do not get logged by the AER driver and do not
get exposed to user space via the AER trace event. So, call
into the AER driver for PCIe errors regardless of the severity


It will also call do_recovery() regardless of the severity for AER correctable 
errors.
Correctable errors include those error conditions where hardware can recover 
without any loss of information.
Hardware corrects these errors and software intervention is not required.
So we'd better modify the code as below.
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c 
b/drivers/pci/pcie/aer/aerdrv_core.c
index 7448052..a7f77549 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -633,7 +633,8 @@ static void aer_recover_work_func(struct work_struct *work)
continue;
}
cper_print_aer(pdev, entry.severity, entry.regs);
-   do_recovery(pdev, entry.severity);
+ if(entry.severity != AER_CORRECTABLE)
+ do_recovery(pdev, entry.severity);
pci_dev_put(pdev);
}
 }

Thanks,
Dongdong


Signed-off-by: Tyler Baicar 
---
 drivers/acpi/apei/ghes.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index 839c3d5..bb65fa6 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -458,14 +458,12 @@ static void ghes_handle_memory_failure(struct 
acpi_hest_generic_data *gdata, int
 #endif
 }

-static void ghes_handle_aer(struct acpi_hest_generic_data *gdata, int sev, int 
sec_sev)
+static void ghes_handle_aer(struct acpi_hest_generic_data *gdata)
 {
 #ifdef CONFIG_ACPI_APEI_PCIEAER
struct cper_sec_pcie *pcie_err = acpi_hest_get_payload(gdata);

-   if (sev == GHES_SEV_RECOVERABLE &&
-   sec_sev == GHES_SEV_RECOVERABLE &&
-   pcie_err->validation_bits & CPER_PCIE_VALID_DEVICE_ID &&
+   if (pcie_err->validation_bits & CPER_PCIE_VALID_DEVICE_ID &&
pcie_err->validation_bits & CPER_PCIE_VALID_AER_INFO) {
unsigned int devfn;
int aer_severity;
@@ -519,7 +517,7 @@ static void ghes_do_proc(struct ghes *ghes,
ghes_handle_memory_failure(gdata, sev);
}
else if (guid_equal(sec_type, _SEC_PCIE)) {
-   ghes_handle_aer(gdata, sev, sec_sev);
+   ghes_handle_aer(gdata);
}
else if (guid_equal(sec_type, _SEC_PROC_ARM)) {
struct cper_sec_proc_arm *err = 
acpi_hest_get_payload(gdata);

Re: [PATCH v4 00/21] PCI: fix config space memory mappings

[Dongdong Liu]

在 2017/4/27 1:24, Jingoo Han 写道:

On Wednesday, April 26, 2017 6:54 AM, Dongdong Liu wrote;


Tested-by: Dongdong Liu <liudongdo...@huawei.com>

I tested the patchset on HiSilicon ARM64 D05 board.It works ok with 82599
netcard.


Thank you for testing these patches. HiSilicon PCIe may use Designware-based
PCIe controller. In my opinion, other Designware-based PCIe controller will
work properly.

To Dongdong Liu, Khuong Dinh, and other people,
If possible, can you check the output of 'lspci -v'?
If you find something different, please share it with us.
Good luck.


root@(none)$ ./lspci -v
0002:80:00.0 Class 0604: Device 19e5:1610 (rev 01)
Flags: bus master, fast devsel, latency 0
Memory at a9e0 (32-bit, non-prefetchable) [size=64K]
Bus: primary=80, secondary=81, subordinate=82, sec-latency=0
I/O behind bridge: -1fff
Memory behind bridge: a880-a8ff
Prefetchable memory behind bridge: a900-a9df
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/32 Maskable+ 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [158] #19
Capabilities: [178] #17
Kernel driver in use: pcieport

0002:81:00.0 Class 0200: Device 8086:10fb (rev 01)
Flags: bus master, fast devsel, latency 0, IRQ 255
Memory at a900 (64-bit, prefetchable) [size=4M]
I/O ports at 1000 [disabled] [size=32]
Memory at a980 (64-bit, prefetchable) [size=16K]
Expansion ROM at a880 [disabled] [size=4M]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Capabilities: [70] MSI-X: Enable+ Count=64 Masked-
Capabilities: [a0] Express Endpoint, MSI 00
Capabilities: [e0] Vital Product Data
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Device Serial Number 9c-37-f4-ff-ff-7b-5b-a0
Capabilities: [150] Alternative Routing-ID Interpretation (ARI)
Capabilities: [160] Single Root I/O Virtualization (SR-IOV)
Kernel driver in use: ixgbe

0002:81:00.1 Class 0200: Device 8086:10fb (rev 01)
Flags: bus master, fast devsel, latency 0, IRQ 255
Memory at a940 (64-bit, prefetchable) [size=4M]
I/O ports at 1020 [disabled] [size=32]
Memory at a9a04000 (64-bit, prefetchable) [size=16K]
Expansion ROM at a8c0 [disabled] [size=4M]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Capabilities: [70] MSI-X: Enable+ Count=64 Masked-
Capabilities: [a0] Express Endpoint, MSI 00
Capabilities: [e0] Vital Product Data
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Device Serial Number 9c-37-f4-ff-ff-7b-5b-a0
Capabilities: [150] Alternative Routing-ID Interpretation (ARI)
Capabilities: [160] Single Root I/O Virtualization (SR-IOV)
Kernel driver in use: ixgbe

0004:88:00.0 Class 0604: Device 19e5:1610 (rev 01)
Flags: bus master, fast devsel, latency 0
Memory at 8a900 (32-bit, non-prefetchable) [size=64K]
Bus: primary=88, secondary=89, subordinate=89, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/32 Maskable+ 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [158] #19
Capabilities: [178] #17
Kernel driver in use: pcieport

Thanks,
Dongdong


Best regards,
Jingoo Han



Thanks,
Dongdong
在 2017/4/25 14:40, Jon Masters 写道:

On 04/19/2017 12:48 PM, Lorenzo Pieralisi wrote:


On some platforms (ie ARM/ARM64) ioremap fails to comply with the PCI
configuration non-posted write transactions requirement, because it
provides a memory mapping that issues "bufferable" or, in PCI terms
"posted" write transactions. Likewise, the current pci_remap_iospace()
implementation maps the physical address range that the PCI translates
to I/O space cycles to virtual address space through pgprot_device()
attributes that on eg ARM64 provides a memory mapping issuing
posted writes transactions, which is not PCI specifications compliant.


Side note that I've pinged all of the ARM server vendors and asked them
to verify this patch series on their platforms.

Jon.

.



.

Re: [PATCH v4 00/21] PCI: fix config space memory mappings

[Dongdong Liu]

在 2017/4/27 1:24, Jingoo Han 写道:

On Wednesday, April 26, 2017 6:54 AM, Dongdong Liu wrote;


Tested-by: Dongdong Liu 

I tested the patchset on HiSilicon ARM64 D05 board.It works ok with 82599
netcard.


Thank you for testing these patches. HiSilicon PCIe may use Designware-based
PCIe controller. In my opinion, other Designware-based PCIe controller will
work properly.

To Dongdong Liu, Khuong Dinh, and other people,
If possible, can you check the output of 'lspci -v'?
If you find something different, please share it with us.
Good luck.


root@(none)$ ./lspci -v
0002:80:00.0 Class 0604: Device 19e5:1610 (rev 01)
Flags: bus master, fast devsel, latency 0
Memory at a9e0 (32-bit, non-prefetchable) [size=64K]
Bus: primary=80, secondary=81, subordinate=82, sec-latency=0
I/O behind bridge: -1fff
Memory behind bridge: a880-a8ff
Prefetchable memory behind bridge: a900-a9df
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/32 Maskable+ 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [158] #19
Capabilities: [178] #17
Kernel driver in use: pcieport

0002:81:00.0 Class 0200: Device 8086:10fb (rev 01)
Flags: bus master, fast devsel, latency 0, IRQ 255
Memory at a900 (64-bit, prefetchable) [size=4M]
I/O ports at 1000 [disabled] [size=32]
Memory at a980 (64-bit, prefetchable) [size=16K]
Expansion ROM at a880 [disabled] [size=4M]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Capabilities: [70] MSI-X: Enable+ Count=64 Masked-
Capabilities: [a0] Express Endpoint, MSI 00
Capabilities: [e0] Vital Product Data
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Device Serial Number 9c-37-f4-ff-ff-7b-5b-a0
Capabilities: [150] Alternative Routing-ID Interpretation (ARI)
Capabilities: [160] Single Root I/O Virtualization (SR-IOV)
Kernel driver in use: ixgbe

0002:81:00.1 Class 0200: Device 8086:10fb (rev 01)
Flags: bus master, fast devsel, latency 0, IRQ 255
Memory at a940 (64-bit, prefetchable) [size=4M]
I/O ports at 1020 [disabled] [size=32]
Memory at a9a04000 (64-bit, prefetchable) [size=16K]
Expansion ROM at a8c0 [disabled] [size=4M]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Capabilities: [70] MSI-X: Enable+ Count=64 Masked-
Capabilities: [a0] Express Endpoint, MSI 00
Capabilities: [e0] Vital Product Data
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Device Serial Number 9c-37-f4-ff-ff-7b-5b-a0
Capabilities: [150] Alternative Routing-ID Interpretation (ARI)
Capabilities: [160] Single Root I/O Virtualization (SR-IOV)
Kernel driver in use: ixgbe

0004:88:00.0 Class 0604: Device 19e5:1610 (rev 01)
Flags: bus master, fast devsel, latency 0
Memory at 8a900 (32-bit, non-prefetchable) [size=64K]
Bus: primary=88, secondary=89, subordinate=89, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/32 Maskable+ 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [158] #19
Capabilities: [178] #17
Kernel driver in use: pcieport

Thanks,
Dongdong


Best regards,
Jingoo Han



Thanks,
Dongdong
在 2017/4/25 14:40, Jon Masters 写道:

On 04/19/2017 12:48 PM, Lorenzo Pieralisi wrote:


On some platforms (ie ARM/ARM64) ioremap fails to comply with the PCI
configuration non-posted write transactions requirement, because it
provides a memory mapping that issues "bufferable" or, in PCI terms
"posted" write transactions. Likewise, the current pci_remap_iospace()
implementation maps the physical address range that the PCI translates
to I/O space cycles to virtual address space through pgprot_device()
attributes that on eg ARM64 provides a memory mapping issuing
posted writes transactions, which is not PCI specifications compliant.


Side note that I've pinged all of the ARM server vendors and asked them
to verify this patch series on their platforms.

Jon.

.



.

Re: [PATCH v4 00/21] PCI: fix config space memory mappings

[Dongdong Liu]

Tested-by: Dongdong Liu <liudongdo...@huawei.com>

I tested the patchset on HiSilicon ARM64 D05 board.It works ok with 82599 
netcard.

Thanks,
Dongdong
在 2017/4/25 14:40, Jon Masters 写道:

On 04/19/2017 12:48 PM, Lorenzo Pieralisi wrote:


On some platforms (ie ARM/ARM64) ioremap fails to comply with the PCI
configuration non-posted write transactions requirement, because it
provides a memory mapping that issues "bufferable" or, in PCI terms
"posted" write transactions. Likewise, the current pci_remap_iospace()
implementation maps the physical address range that the PCI translates
to I/O space cycles to virtual address space through pgprot_device()
attributes that on eg ARM64 provides a memory mapping issuing
posted writes transactions, which is not PCI specifications compliant.


Side note that I've pinged all of the ARM server vendors and asked them
to verify this patch series on their platforms.

Jon.

.

Re: [PATCH v4 00/21] PCI: fix config space memory mappings

[Dongdong Liu]

Tested-by: Dongdong Liu 

I tested the patchset on HiSilicon ARM64 D05 board.It works ok with 82599 
netcard.

Thanks,
Dongdong
在 2017/4/25 14:40, Jon Masters 写道:

On 04/19/2017 12:48 PM, Lorenzo Pieralisi wrote:


On some platforms (ie ARM/ARM64) ioremap fails to comply with the PCI
configuration non-posted write transactions requirement, because it
provides a memory mapping that issues "bufferable" or, in PCI terms
"posted" write transactions. Likewise, the current pci_remap_iospace()
implementation maps the physical address range that the PCI translates
to I/O space cycles to virtual address space through pgprot_device()
attributes that on eg ARM64 provides a memory mapping issuing
posted writes transactions, which is not PCI specifications compliant.


Side note that I've pinged all of the ARM server vendors and asked them
to verify this patch series on their platforms.

Jon.

.

Re: [PATCH V6 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Ming

The latest patchset is [PATCH v11 00/15] PCI: ARM64 ECAM quirks
You can get them from 
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git (pci/ecam)

Thanks
Dongdong
在 2016/12/22 16:31, Ming Lei 写道:

Hi Dongdong,

On Tue, Nov 22, 2016 at 8:08 PM, Dongdong Liu <liudongdo...@huawei.com> wrote:

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- provides the common function acpi_get_rc_resources() for ARM64
  platform.
- adds the HiSilicon ACPI specific quirks.

This patchset is based on branch pci/ecam-v6
It can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

This patchset has been tested on HiSilicon D03 board.
The dmesg log, /proc/iomem, and ACPI table information can be found:
https://bugzilla.kernel.org/show_bug.cgi?id=187961

v5 -> v6:
- change the config option to CONFIG_PCI_ECAM_QUIRKS.
- fix some commets about acpi_get_rc_resources().


Could you post out v7 for fixing conflicts against current linus tree?

BTW, I tried to fix the conflicts by myself, but still caues the following
build failure:

[tom@linux-2.6-vm]$make -j4 CROSS_COMPILE=aarch64-linux-gnu-
ARCH=arm64 drivers/pci/host/pcie-hisi-acpi.o
  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/timeconst.h
  CHK include/generated/bounds.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CC  drivers/pci/host/pcie-hisi-acpi.o
In file included from drivers/pci/host/pcie-hisi-acpi.c:16:0:
drivers/pci/host/../pci.h:357:18: error: conflicting types for
‘acpi_get_rc_resources’
 struct resource *acpi_get_rc_resources(const char *hid, u16 segment);
  ^
drivers/pci/host/../pci.h:352:5: note: previous declaration of
‘acpi_get_rc_resources’ was here
 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
 ^
scripts/Makefile.build:293: recipe for target
'drivers/pci/host/pcie-hisi-acpi.o' failed
make[1]: *** [drivers/pci/host/pcie-hisi-acpi.o] Error 1
Makefile:1640: recipe for target 'drivers/pci/host/pcie-hisi-acpi.o' failed
make: *** [drivers/pci/host/pcie-hisi-acpi.o] Error 2


Thanks,
Ming



v4 -> v5:
- obtain rc base addresses from PNP0C02 at the root of the ACPI
  namespace (under \_SB) instead of from sub-device under the RC.
- merge the rewrited get rc resources code by Tomasz.
- delete unused code.
- drop the PATCH V4 1/2, will rework late as a separate patch.

v3 -> v4:
- rebase on pci/ecam-v6.
- delete the unnecessary link_up check code.

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset.
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers.

Dongdong Liu (2):
  PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 +
 drivers/pci/host/Kconfig  |   7 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 119 ++
 drivers/pci/pci-acpi.c|  69 ++
 drivers/pci/pci.h |   4 ++
 include/linux/pci-ecam.h  |   5 ++
 8 files changed, 219 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

--
1.9.1

Re: [PATCH V6 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Ming

The latest patchset is [PATCH v11 00/15] PCI: ARM64 ECAM quirks
You can get them from 
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git (pci/ecam)

Thanks
Dongdong
在 2016/12/22 16:31, Ming Lei 写道:

Hi Dongdong,

On Tue, Nov 22, 2016 at 8:08 PM, Dongdong Liu  wrote:

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- provides the common function acpi_get_rc_resources() for ARM64
  platform.
- adds the HiSilicon ACPI specific quirks.

This patchset is based on branch pci/ecam-v6
It can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

This patchset has been tested on HiSilicon D03 board.
The dmesg log, /proc/iomem, and ACPI table information can be found:
https://bugzilla.kernel.org/show_bug.cgi?id=187961

v5 -> v6:
- change the config option to CONFIG_PCI_ECAM_QUIRKS.
- fix some commets about acpi_get_rc_resources().


Could you post out v7 for fixing conflicts against current linus tree?

BTW, I tried to fix the conflicts by myself, but still caues the following
build failure:

[tom@linux-2.6-vm]$make -j4 CROSS_COMPILE=aarch64-linux-gnu-
ARCH=arm64 drivers/pci/host/pcie-hisi-acpi.o
  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/timeconst.h
  CHK include/generated/bounds.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CC  drivers/pci/host/pcie-hisi-acpi.o
In file included from drivers/pci/host/pcie-hisi-acpi.c:16:0:
drivers/pci/host/../pci.h:357:18: error: conflicting types for
‘acpi_get_rc_resources’
 struct resource *acpi_get_rc_resources(const char *hid, u16 segment);
  ^
drivers/pci/host/../pci.h:352:5: note: previous declaration of
‘acpi_get_rc_resources’ was here
 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
 ^
scripts/Makefile.build:293: recipe for target
'drivers/pci/host/pcie-hisi-acpi.o' failed
make[1]: *** [drivers/pci/host/pcie-hisi-acpi.o] Error 1
Makefile:1640: recipe for target 'drivers/pci/host/pcie-hisi-acpi.o' failed
make: *** [drivers/pci/host/pcie-hisi-acpi.o] Error 2


Thanks,
Ming



v4 -> v5:
- obtain rc base addresses from PNP0C02 at the root of the ACPI
  namespace (under \_SB) instead of from sub-device under the RC.
- merge the rewrited get rc resources code by Tomasz.
- delete unused code.
- drop the PATCH V4 1/2, will rework late as a separate patch.

v3 -> v4:
- rebase on pci/ecam-v6.
- delete the unnecessary link_up check code.

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset.
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers.

Dongdong Liu (2):
  PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 +
 drivers/pci/host/Kconfig  |   7 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 119 ++
 drivers/pci/pci-acpi.c|  69 ++
 drivers/pci/pci.h |   4 ++
 include/linux/pci-ecam.h  |   5 ++
 8 files changed, 219 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

--
1.9.1

Re: [PATCH V6 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

Hi Tomasz

在 2016/11/23 9:44, Dongdong Liu 写道:

Hi Tomasz

在 2016/11/22 20:32, Tomasz Nowicki 写道:

Hi Dongdong,

On 22.11.2016 13:08, Dongdong Liu wrote:

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and returns
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Tomasz Nowicki <t...@semihalf.com>
---
 drivers/pci/pci-acpi.c | 69 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 73 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..76fd6f4 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,75 @@
 0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };

+#ifdef CONFIG_ARM64
+static struct resource *acpi_get_rc_addr(struct acpi_device *adev)
+{
+struct resource_entry *entry;
+struct list_head list;
+unsigned long flags;
+int ret;
+struct resource *res;
+
+INIT_LIST_HEAD();
+flags = IORESOURCE_MEM;
+ret = acpi_dev_get_resources(adev, ,
+ acpi_dev_filter_resource_type_cb,
+ (void *) flags);
+if (ret <= 0)
+return NULL;
+
+entry = list_first_entry(, struct resource_entry, node);
+res = entry->res;


You return "res" memory pointer and...


+acpi_dev_free_resource_list();


free it here.


 acpi_dev_free_resource_list
--->resource_list_free
--->resource_list_destroy_entry
--->resource_list_free_entry
--->kfree(entry)
only free entry not free entry->res, so this is ok.


Sorry I am wrong, ignore this.


Thanks
Dongdong



+return res;
+}



We either allocate memory for res here or get it from the caller.


Yes, you are right.I prefer to get if from the caller as PATCH V5 shows.

Thanks
Dongdong


Tomasz

.



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Re: [PATCH V6 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

Hi Tomasz

在 2016/11/23 9:44, Dongdong Liu 写道:

Hi Tomasz

在 2016/11/22 20:32, Tomasz Nowicki 写道:

Hi Dongdong,

On 22.11.2016 13:08, Dongdong Liu wrote:

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and returns
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu 
Signed-off-by: Tomasz Nowicki 
---
 drivers/pci/pci-acpi.c | 69 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 73 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..76fd6f4 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,75 @@
 0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };

+#ifdef CONFIG_ARM64
+static struct resource *acpi_get_rc_addr(struct acpi_device *adev)
+{
+struct resource_entry *entry;
+struct list_head list;
+unsigned long flags;
+int ret;
+struct resource *res;
+
+INIT_LIST_HEAD();
+flags = IORESOURCE_MEM;
+ret = acpi_dev_get_resources(adev, ,
+ acpi_dev_filter_resource_type_cb,
+ (void *) flags);
+if (ret <= 0)
+return NULL;
+
+entry = list_first_entry(, struct resource_entry, node);
+res = entry->res;


You return "res" memory pointer and...


+acpi_dev_free_resource_list();


free it here.


 acpi_dev_free_resource_list
--->resource_list_free
--->resource_list_destroy_entry
--->resource_list_free_entry
--->kfree(entry)
only free entry not free entry->res, so this is ok.


Sorry I am wrong, ignore this.


Thanks
Dongdong



+return res;
+}



We either allocate memory for res here or get it from the caller.


Yes, you are right.I prefer to get if from the caller as PATCH V5 shows.

Thanks
Dongdong


Tomasz

.



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Re: [PATCH V6 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

Hi Tomasz

在 2016/11/22 20:32, Tomasz Nowicki 写道:

Hi Dongdong,

On 22.11.2016 13:08, Dongdong Liu wrote:

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and returns
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Tomasz Nowicki <t...@semihalf.com>
---
 drivers/pci/pci-acpi.c | 69 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 73 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..76fd6f4 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,75 @@
 0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };

+#ifdef CONFIG_ARM64
+static struct resource *acpi_get_rc_addr(struct acpi_device *adev)
+{
+struct resource_entry *entry;
+struct list_head list;
+unsigned long flags;
+int ret;
+struct resource *res;
+
+INIT_LIST_HEAD();
+flags = IORESOURCE_MEM;
+ret = acpi_dev_get_resources(adev, ,
+ acpi_dev_filter_resource_type_cb,
+ (void *) flags);
+if (ret <= 0)
+return NULL;
+
+entry = list_first_entry(, struct resource_entry, node);
+res = entry->res;


You return "res" memory pointer and...


+acpi_dev_free_resource_list();


free it here.


 acpi_dev_free_resource_list
--->resource_list_free
--->resource_list_destroy_entry
--->resource_list_free_entry
--->kfree(entry)
only free entry not free entry->res, so this is ok.

Thanks
Dongdong



+return res;
+}



We either allocate memory for res here or get it from the caller.

Tomasz

.

Re: [PATCH V6 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

Hi Tomasz

在 2016/11/22 20:32, Tomasz Nowicki 写道:

Hi Dongdong,

On 22.11.2016 13:08, Dongdong Liu wrote:

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and returns
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu 
Signed-off-by: Tomasz Nowicki 
---
 drivers/pci/pci-acpi.c | 69 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 73 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..76fd6f4 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,75 @@
 0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };

+#ifdef CONFIG_ARM64
+static struct resource *acpi_get_rc_addr(struct acpi_device *adev)
+{
+struct resource_entry *entry;
+struct list_head list;
+unsigned long flags;
+int ret;
+struct resource *res;
+
+INIT_LIST_HEAD();
+flags = IORESOURCE_MEM;
+ret = acpi_dev_get_resources(adev, ,
+ acpi_dev_filter_resource_type_cb,
+ (void *) flags);
+if (ret <= 0)
+return NULL;
+
+entry = list_first_entry(, struct resource_entry, node);
+res = entry->res;


You return "res" memory pointer and...


+acpi_dev_free_resource_list();


free it here.


 acpi_dev_free_resource_list
--->resource_list_free
--->resource_list_destroy_entry
--->resource_list_free_entry
--->kfree(entry)
only free entry not free entry->res, so this is ok.

Thanks
Dongdong



+return res;
+}



We either allocate memory for res here or get it from the caller.

Tomasz

.

[PATCH V6 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 +
 drivers/pci/host/Kconfig  |   7 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 119 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 146 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..3297c5a 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_ECAM_QUIRKS
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..1fbade5 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -301,4 +301,11 @@ config VMD
  To compile this driver as a module, choose M here: the
  module will be called vmd.
 
+config PCI_ECAM_QUIRKS
+   bool "PCI ECAM quirks for ARM64 platform"
+   depends on PCI_ECAM && ARM64 && ACPI
+   help
+ Say y here to enable your platform-specific config access that
+ is not ECAM compliant.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..15435b4 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_ECAM_QUIRKS) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..8bb43b4
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,119 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+#include "../pci.h"
+
+static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+{
+   struct pci_config_window *cfg = bus->sysdata;
+   int dev = PCI_SLOT(devfn);
+
+   if (bus->number == cfg->busr.start) {
+   /* access only one slot on each root port */
+   if (dev > 0)
+   return PCIBIOS_DEVICE_NOT_FOUND;
+   else
+   retu

[PATCH V6 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- provides the common function acpi_get_rc_resources() for ARM64
  platform.
- adds the HiSilicon ACPI specific quirks.

This patchset is based on branch pci/ecam-v6
It can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

This patchset has been tested on HiSilicon D03 board.
The dmesg log, /proc/iomem, and ACPI table information can be found:
https://bugzilla.kernel.org/show_bug.cgi?id=187961

v5 -> v6:
- change the config option to CONFIG_PCI_ECAM_QUIRKS.
- fix some commets about acpi_get_rc_resources().

v4 -> v5:
- obtain rc base addresses from PNP0C02 at the root of the ACPI
  namespace (under \_SB) instead of from sub-device under the RC.
- merge the rewrited get rc resources code by Tomasz.
- delete unused code. 
- drop the PATCH V4 1/2, will rework late as a separate patch.

v3 -> v4:
- rebase on pci/ecam-v6.
- delete the unnecessary link_up check code. 

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset. 
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers.

Dongdong Liu (2):
  PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 +
 drivers/pci/host/Kconfig  |   7 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 119 ++
 drivers/pci/pci-acpi.c|  69 ++
 drivers/pci/pci.h |   4 ++
 include/linux/pci-ecam.h  |   5 ++
 8 files changed, 219 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

-- 
1.9.1

[PATCH V6 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 +
 drivers/pci/host/Kconfig  |   7 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 119 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 146 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..3297c5a 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_ECAM_QUIRKS
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..1fbade5 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -301,4 +301,11 @@ config VMD
  To compile this driver as a module, choose M here: the
  module will be called vmd.
 
+config PCI_ECAM_QUIRKS
+   bool "PCI ECAM quirks for ARM64 platform"
+   depends on PCI_ECAM && ARM64 && ACPI
+   help
+ Say y here to enable your platform-specific config access that
+ is not ECAM compliant.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..15435b4 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_ECAM_QUIRKS) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..8bb43b4
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,119 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+#include "../pci.h"
+
+static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+{
+   struct pci_config_window *cfg = bus->sysdata;
+   int dev = PCI_SLOT(devfn);
+
+   if (bus->number == cfg->busr.start) {
+   /* access only one slot on each root port */
+   if (dev > 0)
+   return PCIBIOS_DEVICE_NOT_FOUND;
+   else
+   return pci_generic_config_read32(bus, devfn, where,
+size, val);
+   }
+
+   return pci_generic_config

[PATCH V6 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- provides the common function acpi_get_rc_resources() for ARM64
  platform.
- adds the HiSilicon ACPI specific quirks.

This patchset is based on branch pci/ecam-v6
It can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

This patchset has been tested on HiSilicon D03 board.
The dmesg log, /proc/iomem, and ACPI table information can be found:
https://bugzilla.kernel.org/show_bug.cgi?id=187961

v5 -> v6:
- change the config option to CONFIG_PCI_ECAM_QUIRKS.
- fix some commets about acpi_get_rc_resources().

v4 -> v5:
- obtain rc base addresses from PNP0C02 at the root of the ACPI
  namespace (under \_SB) instead of from sub-device under the RC.
- merge the rewrited get rc resources code by Tomasz.
- delete unused code. 
- drop the PATCH V4 1/2, will rework late as a separate patch.

v3 -> v4:
- rebase on pci/ecam-v6.
- delete the unnecessary link_up check code. 

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset. 
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers.

Dongdong Liu (2):
  PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 +
 drivers/pci/host/Kconfig  |   7 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 119 ++
 drivers/pci/pci-acpi.c|  69 ++
 drivers/pci/pci.h |   4 ++
 include/linux/pci-ecam.h  |   5 ++
 8 files changed, 219 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

-- 
1.9.1

[PATCH V6 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and returns
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Tomasz Nowicki <t...@semihalf.com>
---
 drivers/pci/pci-acpi.c | 69 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 73 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..76fd6f4 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,75 @@
0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };
 
+#ifdef CONFIG_ARM64
+static struct resource *acpi_get_rc_addr(struct acpi_device *adev)
+{
+   struct resource_entry *entry;
+   struct list_head list;
+   unsigned long flags;
+   int ret;
+   struct resource *res;
+
+   INIT_LIST_HEAD();
+   flags = IORESOURCE_MEM;
+   ret = acpi_dev_get_resources(adev, ,
+acpi_dev_filter_resource_type_cb,
+(void *) flags);
+   if (ret <= 0)
+   return NULL;
+
+   entry = list_first_entry(, struct resource_entry, node);
+   res = entry->res;
+   acpi_dev_free_resource_list();
+   return res;
+}
+
+static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
+void **retval)
+{
+   u16 *segment = context;
+   unsigned long long uid;
+   acpi_status status;
+
+   status = acpi_evaluate_integer(handle, "_UID", NULL, );
+   if (ACPI_FAILURE(status) || uid != *segment)
+   return AE_CTRL_DEPTH;
+
+   *(acpi_handle *)retval = handle;
+   return AE_CTRL_TERMINATE;
+}
+
+/**
+ * acpi_get_rc_resources() - get the RC address resource.
+ * @hid:   HID to search for.
+ * @segment:   PCI Segment number.
+ *
+ * Get the RC address resource that can not be described in MCFG. It takes
+ * the _HID to look for and returns the RC address resource. Use
+ * _CRS of PNP0C02 devices to describe such RC address resource. Use _UID
+ * to match segment to tell which root bus the PNP0C02 resource belong to.
+ *
+ * Return: RC address resource.
+ */
+struct resource *acpi_get_rc_resources(const char *hid, u16 segment)
+{
+   struct acpi_device *adev;
+   acpi_status status;
+   acpi_handle handle;
+   int ret;
+
+   status = acpi_get_devices(hid, acpi_match_rc, , );
+   if (ACPI_FAILURE(status))
+   return -ENODEV;
+
+   ret = acpi_bus_get_device(handle, );
+   if (ret)
+   return ret;
+
+   return acpi_get_rc_addr(adev);
+}
+#endif
+
 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
 {
acpi_status status = AE_NOT_EXIST;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4518562..bf1dbfe 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -356,4 +356,8 @@ static inline int pci_dev_specific_reset(struct pci_dev 
*dev, int probe)
 }
 #endif
 
+#if defined(CONFIG_ARM64) && defined(CONFIG_ACPI)
+struct resource *acpi_get_rc_resources(const char *hid, u16 segment);
+#endif
+
 #endif /* DRIVERS_PCI_H */
-- 
1.9.1

[PATCH V6 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and returns
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu 
Signed-off-by: Tomasz Nowicki 
---
 drivers/pci/pci-acpi.c | 69 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 73 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..76fd6f4 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,75 @@
0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };
 
+#ifdef CONFIG_ARM64
+static struct resource *acpi_get_rc_addr(struct acpi_device *adev)
+{
+   struct resource_entry *entry;
+   struct list_head list;
+   unsigned long flags;
+   int ret;
+   struct resource *res;
+
+   INIT_LIST_HEAD();
+   flags = IORESOURCE_MEM;
+   ret = acpi_dev_get_resources(adev, ,
+acpi_dev_filter_resource_type_cb,
+(void *) flags);
+   if (ret <= 0)
+   return NULL;
+
+   entry = list_first_entry(, struct resource_entry, node);
+   res = entry->res;
+   acpi_dev_free_resource_list();
+   return res;
+}
+
+static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
+void **retval)
+{
+   u16 *segment = context;
+   unsigned long long uid;
+   acpi_status status;
+
+   status = acpi_evaluate_integer(handle, "_UID", NULL, );
+   if (ACPI_FAILURE(status) || uid != *segment)
+   return AE_CTRL_DEPTH;
+
+   *(acpi_handle *)retval = handle;
+   return AE_CTRL_TERMINATE;
+}
+
+/**
+ * acpi_get_rc_resources() - get the RC address resource.
+ * @hid:   HID to search for.
+ * @segment:   PCI Segment number.
+ *
+ * Get the RC address resource that can not be described in MCFG. It takes
+ * the _HID to look for and returns the RC address resource. Use
+ * _CRS of PNP0C02 devices to describe such RC address resource. Use _UID
+ * to match segment to tell which root bus the PNP0C02 resource belong to.
+ *
+ * Return: RC address resource.
+ */
+struct resource *acpi_get_rc_resources(const char *hid, u16 segment)
+{
+   struct acpi_device *adev;
+   acpi_status status;
+   acpi_handle handle;
+   int ret;
+
+   status = acpi_get_devices(hid, acpi_match_rc, , );
+   if (ACPI_FAILURE(status))
+   return -ENODEV;
+
+   ret = acpi_bus_get_device(handle, );
+   if (ret)
+   return ret;
+
+   return acpi_get_rc_addr(adev);
+}
+#endif
+
 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
 {
acpi_status status = AE_NOT_EXIST;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4518562..bf1dbfe 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -356,4 +356,8 @@ static inline int pci_dev_specific_reset(struct pci_dev 
*dev, int probe)
 }
 #endif
 
+#if defined(CONFIG_ARM64) && defined(CONFIG_ACPI)
+struct resource *acpi_get_rc_resources(const char *hid, u16 segment);
+#endif
+
 #endif /* DRIVERS_PCI_H */
-- 
1.9.1

Re: [PATCH V5 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

Hi Rafael

Many Thanks for your review.

在 2016/11/19 6:00, Rafael J. Wysocki 写道:

On Fri, Nov 18, 2016 at 10:22 AM, Dongdong Liu <liudongdo...@huawei.com> wrote:

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and outputs
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Tomasz Nowicki <t...@semihalf.com>
---
 drivers/pci/pci-acpi.c | 71 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 75 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..3557e3a 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,77 @@
0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };

+#ifdef CONFIG_ARM64
+static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)


Why can't it return a resource pointer?


Yes, it can return a resource pointer.
Good catch. will fix.




+{
+   struct resource_entry *entry;
+   struct list_head list;
+   unsigned long flags;
+   int ret;
+
+   INIT_LIST_HEAD();
+   flags = IORESOURCE_MEM;
+   ret = acpi_dev_get_resources(adev, ,
+acpi_dev_filter_resource_type_cb,
+(void *) flags);
+   if (ret < 0) {
+   dev_err(>dev,


The dev_err() log level is quite excessive here IMO.  Why is the
message useful to users at all?  IOW, what is the user supposed to do
if this message is present in the log?


Ok, this is not really needed, I will delete it.



+   "failed to parse _CRS method, error code %d\n", ret);
+   return ret;
+   } else if (ret == 0) {
+   dev_err(>dev,
+   "no IO and memory resources present in _CRS\n");


Same here.

will delete.



+   return -EINVAL;
+   }
+
+   entry = list_first_entry(, struct resource_entry, node);
+   *res = *entry->res;
+   acpi_dev_free_resource_list();
+   return 0;
+}
+
+static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
+void **retval)
+{
+   u16 *segment = context;
+   unsigned long long uid;
+   acpi_status status;
+
+   status = acpi_evaluate_integer(handle, "_UID", NULL, );
+   if (ACPI_FAILURE(status) || uid != *segment)
+   return AE_CTRL_DEPTH;
+
+   *(acpi_handle *)retval = handle;
+   return AE_CTRL_TERMINATE;
+}
+


Please add a kerneldoc comment describing acpi_get_rc_resources().

OK, will do.



+int acpi_get_rc_resources(const char *hid, u16 segment, struct resource *res)
+{
+   struct acpi_device *adev;
+   acpi_status status;
+   acpi_handle handle;
+   int ret;
+
+   status = acpi_get_devices(hid, acpi_match_rc, , );
+   if (ACPI_FAILURE(status)) {
+   pr_err("Can't find _HID %s device", hid);


Same here.


will delete



+   return -ENODEV;
+   }
+
+   ret = acpi_bus_get_device(handle, );
+   if (ret)
+   return ret;
+
+   ret = acpi_get_rc_addr(adev, res);
+   if (ret) {
+   dev_err(>dev, "can't get RC resource");


Same here.


will delete



+   return ret;
+   }
+
+   return 0;
+}


It looks like this function could return the resource pointer just
fine.  What's the problem with that?

It is ok to return the resource pointer, will fix it.



+#endif
+
 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
 {
acpi_status status = AE_NOT_EXIST;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4518562..17ffa38 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -356,4 +356,8 @@ static inline int pci_dev_specific_reset(struct pci_dev 
*dev, int probe)
 }
 #endif

+#ifdef CONFIG_ARM64
+int acpi_get_rc_resources(const char *hid, u16 segment, struct resource *res);
+#endif


Doesn't that depend on ACPI too?


Yes, that depends on ACPI too.
will fix.

Thanks
Dongdong.



+
 #endif /* DRIVERS_PCI_H */
--


Thanks,
Rafael

.

Re: [PATCH V5 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

Hi Rafael

Many Thanks for your review.

在 2016/11/19 6:00, Rafael J. Wysocki 写道:

On Fri, Nov 18, 2016 at 10:22 AM, Dongdong Liu  wrote:

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and outputs
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu 
Signed-off-by: Tomasz Nowicki 
---
 drivers/pci/pci-acpi.c | 71 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 75 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..3557e3a 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,77 @@
0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };

+#ifdef CONFIG_ARM64
+static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)


Why can't it return a resource pointer?


Yes, it can return a resource pointer.
Good catch. will fix.




+{
+   struct resource_entry *entry;
+   struct list_head list;
+   unsigned long flags;
+   int ret;
+
+   INIT_LIST_HEAD();
+   flags = IORESOURCE_MEM;
+   ret = acpi_dev_get_resources(adev, ,
+acpi_dev_filter_resource_type_cb,
+(void *) flags);
+   if (ret < 0) {
+   dev_err(>dev,


The dev_err() log level is quite excessive here IMO.  Why is the
message useful to users at all?  IOW, what is the user supposed to do
if this message is present in the log?


Ok, this is not really needed, I will delete it.



+   "failed to parse _CRS method, error code %d\n", ret);
+   return ret;
+   } else if (ret == 0) {
+   dev_err(>dev,
+   "no IO and memory resources present in _CRS\n");


Same here.

will delete.



+   return -EINVAL;
+   }
+
+   entry = list_first_entry(, struct resource_entry, node);
+   *res = *entry->res;
+   acpi_dev_free_resource_list();
+   return 0;
+}
+
+static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
+void **retval)
+{
+   u16 *segment = context;
+   unsigned long long uid;
+   acpi_status status;
+
+   status = acpi_evaluate_integer(handle, "_UID", NULL, );
+   if (ACPI_FAILURE(status) || uid != *segment)
+   return AE_CTRL_DEPTH;
+
+   *(acpi_handle *)retval = handle;
+   return AE_CTRL_TERMINATE;
+}
+


Please add a kerneldoc comment describing acpi_get_rc_resources().

OK, will do.



+int acpi_get_rc_resources(const char *hid, u16 segment, struct resource *res)
+{
+   struct acpi_device *adev;
+   acpi_status status;
+   acpi_handle handle;
+   int ret;
+
+   status = acpi_get_devices(hid, acpi_match_rc, , );
+   if (ACPI_FAILURE(status)) {
+   pr_err("Can't find _HID %s device", hid);


Same here.


will delete



+   return -ENODEV;
+   }
+
+   ret = acpi_bus_get_device(handle, );
+   if (ret)
+   return ret;
+
+   ret = acpi_get_rc_addr(adev, res);
+   if (ret) {
+   dev_err(>dev, "can't get RC resource");


Same here.


will delete



+   return ret;
+   }
+
+   return 0;
+}


It looks like this function could return the resource pointer just
fine.  What's the problem with that?

It is ok to return the resource pointer, will fix it.



+#endif
+
 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
 {
acpi_status status = AE_NOT_EXIST;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4518562..17ffa38 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -356,4 +356,8 @@ static inline int pci_dev_specific_reset(struct pci_dev 
*dev, int probe)
 }
 #endif

+#ifdef CONFIG_ARM64
+int acpi_get_rc_resources(const char *hid, u16 segment, struct resource *res);
+#endif


Doesn't that depend on ACPI too?


Yes, that depends on ACPI too.
will fix.

Thanks
Dongdong.



+
 #endif /* DRIVERS_PCI_H */
--


Thanks,
Rafael

.

[PATCH V5 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 124 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 152 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..358c7c9
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,124 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+#include "../pci.h"
+
+static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+{
+   struct pci_config_window *cfg = bus->sysdata;
+   int dev = PCI_SLOT(devfn);
+
+   if (bus->number == cfg->busr.start)

[PATCH V5 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- provides the common function acpi_get_rc_resources() for ARM64
  platform.
- adds the HiSilicon ACPI specific quirks.

This patchset is based on branch pci/ecam-v6
It can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

This patchset has been tested on HiSilicon D03 board.
The dmesg log, /proc/iomem, and ACPI table information can be found:
https://bugzilla.kernel.org/show_bug.cgi?id=187961

v4 -> v5:
- obtain rc base addresses from PNP0C02 at the root of the ACPI
namespace (under \_SB) instead of from sub-device under the RC.
- merge the rewrited get rc resources code by Tomasz.
- delete unused code. 
- drop the PATCH V4 1/2, will rework late as a seperate patch.

v3 -> v4:
- rebase on pci/ecam-v6.
- delete the unnecessary link_up check code. 

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset. 
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers.

Dongdong Liu (2):
  PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 124 ++
 drivers/pci/pci-acpi.c|  71 ++
 drivers/pci/pci.h |   4 ++
 include/linux/pci-ecam.h  |   5 ++
 8 files changed, 227 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

-- 
1.9.1

[PATCH V5 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- provides the common function acpi_get_rc_resources() for ARM64
  platform.
- adds the HiSilicon ACPI specific quirks.

This patchset is based on branch pci/ecam-v6
It can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

This patchset has been tested on HiSilicon D03 board.
The dmesg log, /proc/iomem, and ACPI table information can be found:
https://bugzilla.kernel.org/show_bug.cgi?id=187961

v4 -> v5:
- obtain rc base addresses from PNP0C02 at the root of the ACPI
namespace (under \_SB) instead of from sub-device under the RC.
- merge the rewrited get rc resources code by Tomasz.
- delete unused code. 
- drop the PATCH V4 1/2, will rework late as a seperate patch.

v3 -> v4:
- rebase on pci/ecam-v6.
- delete the unnecessary link_up check code. 

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset. 
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers.

Dongdong Liu (2):
  PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 124 ++
 drivers/pci/pci-acpi.c|  71 ++
 drivers/pci/pci.h |   4 ++
 include/linux/pci-ecam.h  |   5 ++
 8 files changed, 227 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

-- 
1.9.1

[PATCH V5 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 +++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 124 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 152 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..358c7c9
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,124 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+#include "../pci.h"
+
+static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+{
+   struct pci_config_window *cfg = bus->sysdata;
+   int dev = PCI_SLOT(devfn);
+
+   if (bus->number == cfg->busr.start) {
+   /* access only one slot on each root port */
+   if (dev > 0)
+   return PCIBIOS_DEVICE_NOT_FOUND;
+   else
+   return pci_generic_confi

[PATCH V5 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and outputs
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Tomasz Nowicki <t...@semihalf.com>
---
 drivers/pci/pci-acpi.c | 71 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 75 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..3557e3a 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,77 @@
0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };
 
+#ifdef CONFIG_ARM64
+static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)
+{
+   struct resource_entry *entry;
+   struct list_head list;
+   unsigned long flags;
+   int ret;
+
+   INIT_LIST_HEAD();
+   flags = IORESOURCE_MEM;
+   ret = acpi_dev_get_resources(adev, ,
+acpi_dev_filter_resource_type_cb,
+(void *) flags);
+   if (ret < 0) {
+   dev_err(>dev,
+   "failed to parse _CRS method, error code %d\n", ret);
+   return ret;
+   } else if (ret == 0) {
+   dev_err(>dev,
+   "no IO and memory resources present in _CRS\n");
+   return -EINVAL;
+   }
+
+   entry = list_first_entry(, struct resource_entry, node);
+   *res = *entry->res;
+   acpi_dev_free_resource_list();
+   return 0;
+}
+
+static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
+void **retval)
+{
+   u16 *segment = context;
+   unsigned long long uid;
+   acpi_status status;
+
+   status = acpi_evaluate_integer(handle, "_UID", NULL, );
+   if (ACPI_FAILURE(status) || uid != *segment)
+   return AE_CTRL_DEPTH;
+
+   *(acpi_handle *)retval = handle;
+   return AE_CTRL_TERMINATE;
+}
+
+int acpi_get_rc_resources(const char *hid, u16 segment, struct resource *res)
+{
+   struct acpi_device *adev;
+   acpi_status status;
+   acpi_handle handle;
+   int ret;
+
+   status = acpi_get_devices(hid, acpi_match_rc, , );
+   if (ACPI_FAILURE(status)) {
+   pr_err("Can't find _HID %s device", hid);
+   return -ENODEV;
+   }
+
+   ret = acpi_bus_get_device(handle, );
+   if (ret)
+   return ret;
+
+   ret = acpi_get_rc_addr(adev, res);
+   if (ret) {
+   dev_err(>dev, "can't get RC resource");
+   return ret;
+   }
+
+   return 0;
+}
+#endif
+
 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
 {
acpi_status status = AE_NOT_EXIST;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4518562..17ffa38 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -356,4 +356,8 @@ static inline int pci_dev_specific_reset(struct pci_dev 
*dev, int probe)
 }
 #endif
 
+#ifdef CONFIG_ARM64
+int acpi_get_rc_resources(const char *hid, u16 segment, struct resource *res);
+#endif
+
 #endif /* DRIVERS_PCI_H */
-- 
1.9.1

[PATCH V5 1/2] PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform

[Dongdong Liu]

The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID to look for and outputs
the RC address resource. Use PNP0C02 devices to describe such RC address
resource. Use _UID to match segment to tell which root bus the PNP0C02
resource belong to.

Signed-off-by: Dongdong Liu 
Signed-off-by: Tomasz Nowicki 
---
 drivers/pci/pci-acpi.c | 71 ++
 drivers/pci/pci.h  |  4 +++
 2 files changed, 75 insertions(+)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index d966d47..3557e3a 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -29,6 +29,77 @@
0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
 };
 
+#ifdef CONFIG_ARM64
+static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)
+{
+   struct resource_entry *entry;
+   struct list_head list;
+   unsigned long flags;
+   int ret;
+
+   INIT_LIST_HEAD();
+   flags = IORESOURCE_MEM;
+   ret = acpi_dev_get_resources(adev, ,
+acpi_dev_filter_resource_type_cb,
+(void *) flags);
+   if (ret < 0) {
+   dev_err(>dev,
+   "failed to parse _CRS method, error code %d\n", ret);
+   return ret;
+   } else if (ret == 0) {
+   dev_err(>dev,
+   "no IO and memory resources present in _CRS\n");
+   return -EINVAL;
+   }
+
+   entry = list_first_entry(, struct resource_entry, node);
+   *res = *entry->res;
+   acpi_dev_free_resource_list();
+   return 0;
+}
+
+static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
+void **retval)
+{
+   u16 *segment = context;
+   unsigned long long uid;
+   acpi_status status;
+
+   status = acpi_evaluate_integer(handle, "_UID", NULL, );
+   if (ACPI_FAILURE(status) || uid != *segment)
+   return AE_CTRL_DEPTH;
+
+   *(acpi_handle *)retval = handle;
+   return AE_CTRL_TERMINATE;
+}
+
+int acpi_get_rc_resources(const char *hid, u16 segment, struct resource *res)
+{
+   struct acpi_device *adev;
+   acpi_status status;
+   acpi_handle handle;
+   int ret;
+
+   status = acpi_get_devices(hid, acpi_match_rc, , );
+   if (ACPI_FAILURE(status)) {
+   pr_err("Can't find _HID %s device", hid);
+   return -ENODEV;
+   }
+
+   ret = acpi_bus_get_device(handle, );
+   if (ret)
+   return ret;
+
+   ret = acpi_get_rc_addr(adev, res);
+   if (ret) {
+   dev_err(>dev, "can't get RC resource");
+   return ret;
+   }
+
+   return 0;
+}
+#endif
+
 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
 {
acpi_status status = AE_NOT_EXIST;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4518562..17ffa38 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -356,4 +356,8 @@ static inline int pci_dev_specific_reset(struct pci_dev 
*dev, int probe)
 }
 #endif
 
+#ifdef CONFIG_ARM64
+int acpi_get_rc_resources(const char *hid, u16 segment, struct resource *res);
+#endif
+
 #endif /* DRIVERS_PCI_H */
-- 
1.9.1

Re: [PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Tomasz

在 2016/11/17 16:28, Tomasz Nowicki 写道:

Hi Dongdong,

I rewrite your code so that it could be used for ThunderX as well.


The rewrited code looks good to me.


This assumes _UID is the right way of looking up corelated RC.
Of course acpi_get_rc_resources() and its acpi_* helpers should go to 
pci-acpi.c.


I am ok about this.

Thanks
Dongdong


Tomasz

static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)
{
struct resource_entry *entry;
struct list_head list;
unsigned long flags;
int ret;

INIT_LIST_HEAD();
flags = IORESOURCE_MEM;
ret = acpi_dev_get_resources(adev, ,
acpi_dev_filter_resource_type_cb, (void *) flags);
if (ret < 0) {
dev_err(>dev,
"failed to parse _CRS method, error code %d\n",
ret);
return ret;
} else if (ret == 0) {
dev_err(>dev,
"no IO and memory resources present in _CRS\n");
return -EINVAL;
}

entry = list_first_entry(, struct resource_entry, node);
*res = *entry->res;
acpi_dev_free_resource_list();
return 0;
}

static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
 void **retval)
{
u16 *segment = context;
unsigned long long uid;
acpi_status status;

status = acpi_evaluate_integer(handle, "_UID", NULL, );
if (ACPI_FAILURE(status) || uid != *segment)
return AE_CTRL_DEPTH;

*(acpi_handle *)retval = handle;
return AE_CTRL_TERMINATE;
}

static int acpi_get_rc_resources(const char *hid, u16 segment,
 struct resource *res)
{
struct acpi_device *adev;
acpi_status status;
acpi_handle handle;
int ret;

status = acpi_get_devices(hid, acpi_match_rc, , );
if (ACPI_FAILURE(status)) {
pr_err("Can't find _HID %s device", hid);
return -ENODEV;
}

ret = acpi_bus_get_device(handle, );
if (ret)
return ret;

ret = acpi_get_rc_addr(adev, res);
if (ret) {
dev_err(>dev, "can't get RC resource");
return ret;
}

return 0;
}

static int hisi_pcie_init(struct pci_config_window *cfg)
{
struct acpi_device *adev = to_acpi_device(cfg->parent);
struct acpi_pci_root *root = acpi_driver_data(adev);
void __iomem *reg_base;
struct resource *res;
acpi_status status;
acpi_handle handle;
int ret;

res = devm_kzalloc(>dev, sizeof(*res), GFP_KERNEL);
if (!res)
return -ENOMEM;

ret = acpi_get_rc_resources("HISI0081", root->segment, res);
if (ret) {
dev_err(>dev, "can't get rc base address");
return ret;
}

reg_base = devm_ioremap(>dev, res->start, resource_size(res));
if (!reg_base)
return -ENOMEM;

cfg->priv = reg_base;
return 0;
}

On 17.11.2016 04:02, Dongdong Liu wrote:

Hi Bjorn
在 2016/11/17 7:00, Bjorn Helgaas 写道:

On Mon, Nov 14, 2016 at 05:33:20PM -0600, Bjorn Helgaas wrote:

On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 157
++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 185 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S:Maintained
 F:Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F:drivers/pci/host/pcie-hisi.c
+F:drivers/pci/host/pcie-hisi-acpi.c

 PCIE DRIVER FOR ROCKCHIP
 M:Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
 { "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
 { "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
 { "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+#define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+{ "HISI  ", 

Re: [PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Tomasz

在 2016/11/17 16:28, Tomasz Nowicki 写道:

Hi Dongdong,

I rewrite your code so that it could be used for ThunderX as well.


The rewrited code looks good to me.


This assumes _UID is the right way of looking up corelated RC.
Of course acpi_get_rc_resources() and its acpi_* helpers should go to 
pci-acpi.c.


I am ok about this.

Thanks
Dongdong


Tomasz

static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)
{
struct resource_entry *entry;
struct list_head list;
unsigned long flags;
int ret;

INIT_LIST_HEAD();
flags = IORESOURCE_MEM;
ret = acpi_dev_get_resources(adev, ,
acpi_dev_filter_resource_type_cb, (void *) flags);
if (ret < 0) {
dev_err(>dev,
"failed to parse _CRS method, error code %d\n",
ret);
return ret;
} else if (ret == 0) {
dev_err(>dev,
"no IO and memory resources present in _CRS\n");
return -EINVAL;
}

entry = list_first_entry(, struct resource_entry, node);
*res = *entry->res;
acpi_dev_free_resource_list();
return 0;
}

static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
 void **retval)
{
u16 *segment = context;
unsigned long long uid;
acpi_status status;

status = acpi_evaluate_integer(handle, "_UID", NULL, );
if (ACPI_FAILURE(status) || uid != *segment)
return AE_CTRL_DEPTH;

*(acpi_handle *)retval = handle;
return AE_CTRL_TERMINATE;
}

static int acpi_get_rc_resources(const char *hid, u16 segment,
 struct resource *res)
{
struct acpi_device *adev;
acpi_status status;
acpi_handle handle;
int ret;

status = acpi_get_devices(hid, acpi_match_rc, , );
if (ACPI_FAILURE(status)) {
pr_err("Can't find _HID %s device", hid);
return -ENODEV;
}

ret = acpi_bus_get_device(handle, );
if (ret)
return ret;

ret = acpi_get_rc_addr(adev, res);
if (ret) {
dev_err(>dev, "can't get RC resource");
return ret;
}

return 0;
}

static int hisi_pcie_init(struct pci_config_window *cfg)
{
struct acpi_device *adev = to_acpi_device(cfg->parent);
struct acpi_pci_root *root = acpi_driver_data(adev);
void __iomem *reg_base;
struct resource *res;
acpi_status status;
acpi_handle handle;
int ret;

res = devm_kzalloc(>dev, sizeof(*res), GFP_KERNEL);
if (!res)
return -ENOMEM;

ret = acpi_get_rc_resources("HISI0081", root->segment, res);
if (ret) {
dev_err(>dev, "can't get rc base address");
return ret;
}

reg_base = devm_ioremap(>dev, res->start, resource_size(res));
if (!reg_base)
return -ENOMEM;

cfg->priv = reg_base;
return 0;
}

On 17.11.2016 04:02, Dongdong Liu wrote:

Hi Bjorn
在 2016/11/17 7:00, Bjorn Helgaas 写道:

On Mon, Nov 14, 2016 at 05:33:20PM -0600, Bjorn Helgaas wrote:

On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 157
++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 185 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S:Maintained
 F:Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F:drivers/pci/host/pcie-hisi.c
+F:drivers/pci/host/pcie-hisi-acpi.c

 PCIE DRIVER FOR ROCKCHIP
 M:Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
 { "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
 { "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
 { "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+#define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+{ "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+{ "HISI  ", table_id, 0, seg + 1, 

Re: [PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Bjorn
在 2016/11/17 7:00, Bjorn Helgaas 写道:

On Mon, Nov 14, 2016 at 05:33:20PM -0600, Bjorn Helgaas wrote:

On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 157 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 185 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };

 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..aade4b5
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,157 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F


These are now unused.


+static const struct acpi_device_i

Re: [PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Bjorn
在 2016/11/17 7:00, Bjorn Helgaas 写道:

On Mon, Nov 14, 2016 at 05:33:20PM -0600, Bjorn Helgaas wrote:

On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 157 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 185 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };

 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..aade4b5
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,157 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F


These are now unused.


+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+  

Re: [PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Bjorn

在 2016/11/17 3:31, Bjorn Helgaas 写道:

On Wed, Nov 16, 2016 at 07:59:38PM +0800, Dongdong Liu wrote:

Hi Bjorn

Many Thanks for your review

在 2016/11/15 7:33, Bjorn Helgaas 写道:

On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
MAINTAINERS   |   1 +
drivers/acpi/pci_mcfg.c   |  13 
drivers/pci/host/Kconfig  |   8 ++
drivers/pci/host/Makefile |   1 +
drivers/pci/host/pcie-hisi-acpi.c | 157 ++
include/linux/pci-ecam.h  |   5 ++
6 files changed, 185 insertions(+)
create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
S:  Maintained
F:  Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
F:  drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

PCIE DRIVER FOR ROCKCHIP
M:  Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
};

static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..aade4b5
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,157 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F


These are n

Re: [PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Bjorn

在 2016/11/17 3:31, Bjorn Helgaas 写道:

On Wed, Nov 16, 2016 at 07:59:38PM +0800, Dongdong Liu wrote:

Hi Bjorn

Many Thanks for your review

在 2016/11/15 7:33, Bjorn Helgaas 写道:

On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
MAINTAINERS   |   1 +
drivers/acpi/pci_mcfg.c   |  13 
drivers/pci/host/Kconfig  |   8 ++
drivers/pci/host/Makefile |   1 +
drivers/pci/host/pcie-hisi-acpi.c | 157 ++
include/linux/pci-ecam.h  |   5 ++
6 files changed, 185 insertions(+)
create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
S:  Maintained
F:  Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
F:  drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

PCIE DRIVER FOR ROCKCHIP
M:  Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
};

static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..aade4b5
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,157 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F


These are now unused.


Thanks for pointing that, will delete them.




+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   

Re: [PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Bjorn

Many Thanks for your review

在 2016/11/15 7:33, Bjorn Helgaas 写道:

On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 157 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 185 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };

 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..aade4b5
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,157 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F


These are now unused.


Thanks for pointing that, will delete them.




+static const struct acpi_device_i

Re: [PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Bjorn

Many Thanks for your review

在 2016/11/15 7:33, Bjorn Helgaas 写道:

On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 157 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 185 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };

 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..aade4b5
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,157 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F


These are now unused.


Thanks for pointing that, will delete them.




+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_acpi_rd_conf(struct pci_bus *b

[PATCH V4 1/2] PCI: hisi: Add ECAM support for devices that are not RC

[Dongdong Liu]

This patch modifies the current Hip05/Hip06 PCIe host
controller driver to add support for 'almost ECAM'
compliant platforms. Some controllers are ECAM compliant
for all the devices of the hierarchy except the root
complex; this patch adds support for such controllers.

This is needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.

Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 15 +---
 drivers/pci/host/Kconfig   |  4 +-
 drivers/pci/host/pcie-designware.c |  4 +-
 drivers/pci/host/pcie-designware.h |  2 +
 drivers/pci/host/pcie-hisi.c   | 45 ++
 5 files changed, 60 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 59c2f47..87a597a 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -9,10 +9,13 @@ Additional properties are described here:
 
 Required properties
 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
-- reg: Should contain rc_dbi, config registers location and length.
-- reg-names: Must include the following entries:
+- reg: Should contain rc_dbi and  either config or ecam-cfg registers
+   location and length (it depends on the platform BIOS).
+- reg-names: Must include
   "rc_dbi": controller configuration registers;
-  "config": PCIe configuration space registers.
+  and one of the following entries:
+"config": PCIe configuration space registers for non-ECAM platforms.
+"ecam-cfg": PCIe configuration space registers for ECAM platforms
 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
 - port-id: Should be 0, 1, 2 or 3.
 
@@ -23,8 +26,10 @@ Optional properties:
 Hip05 Example (note that Hip06 is the same except compatible):
pcie@0xb008 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
-   reg = <0 0xb008 0 0x1>, <0x220 0x 0 0x2000>;
-   reg-names = "rc_dbi", "config";
+   reg = <0 0xb008 0 0x1>,
+ <0x220 0x 0 0x2000>
+   /* or <0x220 0x0010 0 0x0f0> for ecam-cfg*/;
+   reg-names = "rc_dbi", "config" /* or "ecam-cfg" */;
bus-range = <0  15>;
msi-parent = <_pcie>;
#address-cells = <3>;
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d7e7c0a..ae98644 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -219,13 +219,13 @@ config PCIE_ALTERA_MSI
 
 config PCI_HISI
depends on OF && ARM64
-   bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs PCIe controllers"
depends on PCI_MSI_IRQ_DOMAIN
select PCIEPORTBUS
select PCIE_DW
help
  Say Y here if you want PCIe controller support on HiSilicon
- Hip05 and Hip06 SoCs
+ Hip05 and Hip06 and Hip07 SoCs
 
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
diff --git a/drivers/pci/host/pcie-designware.c 
b/drivers/pci/host/pcie-designware.c
index 035f50c..da11644 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -101,8 +101,6 @@
 #define PCIE_PHY_DEBUG_R1_LINK_UP  (0x1 << 4)
 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
 
-static struct pci_ops dw_pcie_ops;
-
 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
 {
if ((uintptr_t)addr & (size - 1)) {
@@ -800,7 +798,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 }
 
-static struct pci_ops dw_pcie_ops = {
+struct pci_ops dw_pcie_ops = {
.read = dw_pcie_rd_conf,
.write = dw_pcie_wr_conf,
 };
diff --git a/drivers/pci/host/pcie-designware.h 
b/drivers/pci/host/pcie-designware.h
index a567ea2..30d228a 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -83,4 +83,6 @@ struct pcie_host_ops {
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+extern struct pci_ops dw_pcie_ops;
+
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 56154

[PATCH V4 1/2] PCI: hisi: Add ECAM support for devices that are not RC

[Dongdong Liu]

This patch modifies the current Hip05/Hip06 PCIe host
controller driver to add support for 'almost ECAM'
compliant platforms. Some controllers are ECAM compliant
for all the devices of the hierarchy except the root
complex; this patch adds support for such controllers.

This is needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.

Signed-off-by: Gabriele Paoloni 
Signed-off-by: Dongdong Liu 
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 15 +---
 drivers/pci/host/Kconfig   |  4 +-
 drivers/pci/host/pcie-designware.c |  4 +-
 drivers/pci/host/pcie-designware.h |  2 +
 drivers/pci/host/pcie-hisi.c   | 45 ++
 5 files changed, 60 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 59c2f47..87a597a 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -9,10 +9,13 @@ Additional properties are described here:
 
 Required properties
 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
-- reg: Should contain rc_dbi, config registers location and length.
-- reg-names: Must include the following entries:
+- reg: Should contain rc_dbi and  either config or ecam-cfg registers
+   location and length (it depends on the platform BIOS).
+- reg-names: Must include
   "rc_dbi": controller configuration registers;
-  "config": PCIe configuration space registers.
+  and one of the following entries:
+"config": PCIe configuration space registers for non-ECAM platforms.
+"ecam-cfg": PCIe configuration space registers for ECAM platforms
 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
 - port-id: Should be 0, 1, 2 or 3.
 
@@ -23,8 +26,10 @@ Optional properties:
 Hip05 Example (note that Hip06 is the same except compatible):
pcie@0xb008 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
-   reg = <0 0xb008 0 0x1>, <0x220 0x 0 0x2000>;
-   reg-names = "rc_dbi", "config";
+   reg = <0 0xb008 0 0x1>,
+ <0x220 0x 0 0x2000>
+   /* or <0x220 0x0010 0 0x0f0> for ecam-cfg*/;
+   reg-names = "rc_dbi", "config" /* or "ecam-cfg" */;
bus-range = <0  15>;
msi-parent = <_pcie>;
#address-cells = <3>;
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d7e7c0a..ae98644 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -219,13 +219,13 @@ config PCIE_ALTERA_MSI
 
 config PCI_HISI
depends on OF && ARM64
-   bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs PCIe controllers"
depends on PCI_MSI_IRQ_DOMAIN
select PCIEPORTBUS
select PCIE_DW
help
  Say Y here if you want PCIe controller support on HiSilicon
- Hip05 and Hip06 SoCs
+ Hip05 and Hip06 and Hip07 SoCs
 
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
diff --git a/drivers/pci/host/pcie-designware.c 
b/drivers/pci/host/pcie-designware.c
index 035f50c..da11644 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -101,8 +101,6 @@
 #define PCIE_PHY_DEBUG_R1_LINK_UP  (0x1 << 4)
 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
 
-static struct pci_ops dw_pcie_ops;
-
 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
 {
if ((uintptr_t)addr & (size - 1)) {
@@ -800,7 +798,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 }
 
-static struct pci_ops dw_pcie_ops = {
+struct pci_ops dw_pcie_ops = {
.read = dw_pcie_rd_conf,
.write = dw_pcie_wr_conf,
 };
diff --git a/drivers/pci/host/pcie-designware.h 
b/drivers/pci/host/pcie-designware.h
index a567ea2..30d228a 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -83,4 +83,6 @@ struct pcie_host_ops {
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+extern struct pci_ops dw_pcie_ops;
+
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 56154c2..555c964 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers

[PATCH V4 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- rework the current HiSilicon driver to add support for ECAM
  platforms(not RC).
- adds the HiSilicon ACPI specific quirks.

This patchset is based on branch pci/ecam-v6
It can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

v3 -> v4:
- rebase on pci/ecam-v6.
- delete the unnecessary link_up check code. 

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset. 
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers

Dongdong Liu (2):
  PCI: hisi: Add ECAM support for devices that are not RC
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 .../devicetree/bindings/pci/hisilicon-pcie.txt |  15 +-
 MAINTAINERS|   1 +
 drivers/acpi/pci_mcfg.c|  13 ++
 drivers/pci/host/Kconfig   |  12 +-
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-designware.c |   4 +-
 drivers/pci/host/pcie-designware.h |   2 +
 drivers/pci/host/pcie-hisi-acpi.c  | 157 +
 drivers/pci/host/pcie-hisi.c   |  45 ++
 include/linux/pci-ecam.h   |   5 +
 10 files changed, 245 insertions(+), 10 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

-- 
1.9.1

[PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 157 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 185 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..aade4b5
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,157 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F
+
+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ in

[PATCH V4 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- rework the current HiSilicon driver to add support for ECAM
  platforms(not RC).
- adds the HiSilicon ACPI specific quirks.

This patchset is based on branch pci/ecam-v6
It can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

v3 -> v4:
- rebase on pci/ecam-v6.
- delete the unnecessary link_up check code. 

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset. 
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers

Dongdong Liu (2):
  PCI: hisi: Add ECAM support for devices that are not RC
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 .../devicetree/bindings/pci/hisilicon-pcie.txt |  15 +-
 MAINTAINERS|   1 +
 drivers/acpi/pci_mcfg.c|  13 ++
 drivers/pci/host/Kconfig   |  12 +-
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-designware.c |   4 +-
 drivers/pci/host/pcie-designware.h |   2 +
 drivers/pci/host/pcie-hisi-acpi.c  | 157 +
 drivers/pci/host/pcie-hisi.c   |  45 ++
 include/linux/pci-ecam.h   |   5 +
 10 files changed, 245 insertions(+), 10 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

-- 
1.9.1

[PATCH V4 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  13 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 157 ++
 include/linux/pci-ecam.h  |   5 ++
 6 files changed, 185 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ac21db3..b1b6fc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -57,6 +57,19 @@ struct mcfg_fixup {
{ "QCOM  ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, _32b_ops },
{ "QCOM  ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, _32b_ops },
+#ifdef CONFIG_PCI_HISI_ACPI
+   #define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..aade4b5
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,157 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F
+
+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+{
+   struct pci_config_window *cfg = bus->sysdata;
+   int dev = PCI_SLOT(devfn);
+
+   if (bus->numbe

Re: [PATCH V3 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Bjorn

Thanks for your review.

在 2016/11/3 7:40, Bjorn Helgaas 写道:

On Thu, Oct 20, 2016 at 11:10:34AM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  15 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 170 ++
 include/linux/pci-ecam.h  |   4 +
 6 files changed, 199 insertions(+)
 create mode 100755 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index bb2c508..135a9b4 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -96,6 +96,21 @@ struct mcfg_fixup {
THUNDER_ECAM_MCFG(2, 12),
THUNDER_ECAM_MCFG(2, 13),
 #endif
+#define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+
+#ifdef CONFIG_PCI_HISI_ACPI
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
+
 };

 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100755
index 000..5650d91
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,170 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F
+
+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_link_up_acpi(struct pci_config_window *cfg)
+{
+   u32 val;
+   void __iomem *reg_base = cfg->priv;
+
+   val = readl

Re: [PATCH V3 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Bjorn

Thanks for your review.

在 2016/11/3 7:40, Bjorn Helgaas 写道:

On Thu, Oct 20, 2016 at 11:10:34AM +0800, Dongdong Liu wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  15 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 170 ++
 include/linux/pci-ecam.h  |   4 +
 6 files changed, 199 insertions(+)
 create mode 100755 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index bb2c508..135a9b4 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -96,6 +96,21 @@ struct mcfg_fixup {
THUNDER_ECAM_MCFG(2, 12),
THUNDER_ECAM_MCFG(2, 13),
 #endif
+#define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+
+#ifdef CONFIG_PCI_HISI_ACPI
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
+
 };

 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100755
index 000..5650d91
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,170 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F
+
+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_link_up_acpi(struct pci_config_window *cfg)
+{
+   u32 val;
+   void __iomem *reg_base = cfg->priv;
+
+   val = readl(reg_base + DEBUG0);
+   return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+}


Maybe reorder this so hisi_pcie_link_up_acpi() i

Re: [PATCH V3 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Lorenzo

Many thanks for your review.
在 2016/10/22 0:08, Lorenzo Pieralisi 写道:

On Fri, Oct 21, 2016 at 02:12:44PM +0800, Dongdong Liu wrote:

[...]


+static int hisi_pcie_init(struct pci_config_window *cfg)
+{
+   int ret;
+   struct acpi_device *adev = to_acpi_device(cfg->parent);


Why is this expected to be struct acpi_device?


I use this acpi device(Device (PCI2)) to get it's child acpi device(Device 
(RES2)), then
obtain rc base addresses from PNP0C02 as subdevice of PNP0A03.

The procedure to get the value of cfg->parent is as the below.
arch/arm64/kernel/pci.c
pci_acpi_scan_root(struct acpi_pci_root *root)
--->pci_acpi_setup_ecam_mapping(root, ri);
--->pci_ecam_create(>device->dev, , bus_res, 
ecam_ops);
--->cfg->parent = dev
;
PCIe DSDT table defines as below.
Device (PCI2)
{
Name (_HID, "PNP0A08") // PCI Express Root Bridge
Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
..
Device (RES2)
{
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa00a , 0x1)
})
..
}


Shouldn't it be a "physical" device whose companion is an ACPI device object?


Sorry, I don't understand.  What do you mean ?


I think Rafael meant the physical node (that in this case is the pci
bridge device) that is associated with the acpi device (the struct
pci_config_window.parent pointer points at the PNP0A03/PNP0A08 acpi
device object though, not the RES2 acpi device that's what you need).

Have a look at:

Documentation/acpi/enumeration.txt
Documentation/acpi/namespace.txt


Thanks for explaining this.




It should be a "physical" device. but I have not saw about
ACPI_COMPANION_SET() of this device.


The PNP0A08 acpi_device (that is what is pointed at by
struct acpi_device = to_acpi_device(pci_config_window.parent)
is the respective pci bridge device companion.

arch/arm64/kernel/pci.c (pcibios_root_bridge_prepare()).

Now for something completely different :), your RES2 pseudo-device.

IIUC platform device (physical node) is created by the ACPI enumeration
code for your RES2 pseudo-device and its resources are already
initialized (by parsing its _CRS) in acpi_create_platform_device().


This is not right. About RES2 pseudo-device,it's _CID is PNP0C02,
this will attach acpi_pnp_attach() (drivers/acpi/acpi_pnp.c) .
acpi_pnp_attach() return 1;ret = acpi_scan_attach_handler() will return 1.
So this will not call acpi_default_enumeration(),
this also will not call acpi_create_platform_device().

drivers/acpi/scan.c
static void acpi_bus_attach(struct acpi_device *device)
{
..
ret = acpi_scan_attach_handler(device);
if (ret < 0)
return;

device->flags.match_driver = true;
if (!ret) {
ret = device_attach(>dev);
if (ret < 0)
return;

if (!ret && device->pnp.type.platform_id)
acpi_default_enumeration(device);
}
..
}

Dongdong
Thanks


This means that by the time you match the PNP0A03/PNP0A08 child with an
acpi_device with _HID == "HISI0081", you can get its associated
physical node and get its resources IOMEM through the physical
node (ie platform device and related resources) instead of re-parsing
the _CRS if I am not mistaken (and that's an IF because I did not
test it).


As above said this does not re-parse the _CRS for RES2 pseudo-device.

Dongdong
Thanks


Regardless, I am not entirely sure there are kernel drivers/control
paths already using this mechanism to handle child devices (keeping in
mind that RES2 is not a real device at all, it is there to represent
PNP0A03 sub-address space for PCI quirks), so it would be good to get
Rafael's agreement on this approach to prevent abusing the current ACPI
platform devices glue code assumptions.

It would also be good to agree on the whole approach soundness.

Thanks,
Lorenzo

.

Re: [PATCH V3 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Lorenzo

Many thanks for your review.
在 2016/10/22 0:08, Lorenzo Pieralisi 写道:

On Fri, Oct 21, 2016 at 02:12:44PM +0800, Dongdong Liu wrote:

[...]


+static int hisi_pcie_init(struct pci_config_window *cfg)
+{
+   int ret;
+   struct acpi_device *adev = to_acpi_device(cfg->parent);


Why is this expected to be struct acpi_device?


I use this acpi device(Device (PCI2)) to get it's child acpi device(Device 
(RES2)), then
obtain rc base addresses from PNP0C02 as subdevice of PNP0A03.

The procedure to get the value of cfg->parent is as the below.
arch/arm64/kernel/pci.c
pci_acpi_scan_root(struct acpi_pci_root *root)
--->pci_acpi_setup_ecam_mapping(root, ri);
--->pci_ecam_create(>device->dev, , bus_res, 
ecam_ops);
--->cfg->parent = dev
;
PCIe DSDT table defines as below.
Device (PCI2)
{
Name (_HID, "PNP0A08") // PCI Express Root Bridge
Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
..
Device (RES2)
{
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa00a , 0x1)
})
..
}


Shouldn't it be a "physical" device whose companion is an ACPI device object?


Sorry, I don't understand.  What do you mean ?


I think Rafael meant the physical node (that in this case is the pci
bridge device) that is associated with the acpi device (the struct
pci_config_window.parent pointer points at the PNP0A03/PNP0A08 acpi
device object though, not the RES2 acpi device that's what you need).

Have a look at:

Documentation/acpi/enumeration.txt
Documentation/acpi/namespace.txt


Thanks for explaining this.




It should be a "physical" device. but I have not saw about
ACPI_COMPANION_SET() of this device.


The PNP0A08 acpi_device (that is what is pointed at by
struct acpi_device = to_acpi_device(pci_config_window.parent)
is the respective pci bridge device companion.

arch/arm64/kernel/pci.c (pcibios_root_bridge_prepare()).

Now for something completely different :), your RES2 pseudo-device.

IIUC platform device (physical node) is created by the ACPI enumeration
code for your RES2 pseudo-device and its resources are already
initialized (by parsing its _CRS) in acpi_create_platform_device().


This is not right. About RES2 pseudo-device,it's _CID is PNP0C02,
this will attach acpi_pnp_attach() (drivers/acpi/acpi_pnp.c) .
acpi_pnp_attach() return 1;ret = acpi_scan_attach_handler() will return 1.
So this will not call acpi_default_enumeration(),
this also will not call acpi_create_platform_device().

drivers/acpi/scan.c
static void acpi_bus_attach(struct acpi_device *device)
{
..
ret = acpi_scan_attach_handler(device);
if (ret < 0)
return;

device->flags.match_driver = true;
if (!ret) {
ret = device_attach(>dev);
if (ret < 0)
return;

if (!ret && device->pnp.type.platform_id)
acpi_default_enumeration(device);
}
..
}

Dongdong
Thanks


This means that by the time you match the PNP0A03/PNP0A08 child with an
acpi_device with _HID == "HISI0081", you can get its associated
physical node and get its resources IOMEM through the physical
node (ie platform device and related resources) instead of re-parsing
the _CRS if I am not mistaken (and that's an IF because I did not
test it).


As above said this does not re-parse the _CRS for RES2 pseudo-device.

Dongdong
Thanks


Regardless, I am not entirely sure there are kernel drivers/control
paths already using this mechanism to handle child devices (keeping in
mind that RES2 is not a real device at all, it is there to represent
PNP0A03 sub-address space for PCI quirks), so it would be good to get
Rafael's agreement on this approach to prevent abusing the current ACPI
platform devices glue code assumptions.

It would also be good to agree on the whole approach soundness.

Thanks,
Lorenzo

.

Re: [PATCH V3 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Rafael

Thanks for your review.

在 2016/10/20 20:27, Rafael J. Wysocki 写道:

On Thu, Oct 20, 2016 at 5:10 AM, Dongdong Liu <liudongdo...@huawei.com> wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
  MAINTAINERS   |   1 +
  drivers/acpi/pci_mcfg.c   |  15 
  drivers/pci/host/Kconfig  |   8 ++
  drivers/pci/host/Makefile |   1 +
  drivers/pci/host/pcie-hisi-acpi.c | 170 ++
  include/linux/pci-ecam.h  |   4 +
  6 files changed, 199 insertions(+)
  create mode 100755 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
  S: Maintained
  F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
  F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

  PCIE DRIVER FOR ROCKCHIP
  M: Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index bb2c508..135a9b4 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -96,6 +96,21 @@ struct mcfg_fixup {
 THUNDER_ECAM_MCFG(2, 12),
 THUNDER_ECAM_MCFG(2, 13),
  #endif
+#define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+
+#ifdef CONFIG_PCI_HISI_ACPI
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
+
  };

  static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
   Say Y here if you want PCIe controller support on HiSilicon
   Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
  config PCIE_QCOM
 bool "Qualcomm PCIe controller"
 depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
  obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
  obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
  obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
  obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
  obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
  obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100755
index 000..5650d91
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,170 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F
+
+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_link_up_acpi(struct pci_config_window *cfg)
+{
+   u32 val;
+   void __

Re: [PATCH V3 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Rafael

Thanks for your review.

在 2016/10/20 20:27, Rafael J. Wysocki 写道:

On Thu, Oct 20, 2016 at 5:10 AM, Dongdong Liu  wrote:

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
  MAINTAINERS   |   1 +
  drivers/acpi/pci_mcfg.c   |  15 
  drivers/pci/host/Kconfig  |   8 ++
  drivers/pci/host/Makefile |   1 +
  drivers/pci/host/pcie-hisi-acpi.c | 170 ++
  include/linux/pci-ecam.h  |   4 +
  6 files changed, 199 insertions(+)
  create mode 100755 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
  S: Maintained
  F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
  F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c

  PCIE DRIVER FOR ROCKCHIP
  M: Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index bb2c508..135a9b4 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -96,6 +96,21 @@ struct mcfg_fixup {
 THUNDER_ECAM_MCFG(2, 12),
 THUNDER_ECAM_MCFG(2, 13),
  #endif
+#define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+
+#ifdef CONFIG_PCI_HISI_ACPI
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
+
  };

  static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
   Say Y here if you want PCIe controller support on HiSilicon
   Hip05 and Hip06 and Hip07 SoCs

+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
  config PCIE_QCOM
 bool "Qualcomm PCIe controller"
 depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
  obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
  obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
  obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
  obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
  obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
  obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100755
index 000..5650d91
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,170 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F
+
+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_link_up_acpi(struct pci_config_window *cfg)
+{
+   u32 val;
+   void __iomem *reg_base = cfg->priv;
+
+   val = readl(reg_base + DEBUG0);
+   return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+}
+
+static int hisi_pcie_acpi_rd_conf(st

[PATCH V3 1/2] PCI: hisi: Add ECAM support for devices that are not RC

[Dongdong Liu]

This patch modifies the current Hip05/Hip06 PCIe host
controller driver to add support for 'almost ECAM'
compliant platforms. Some controllers are ECAM compliant
for all the devices of the hierarchy except the root
complex; this patch adds support for such controllers.

This is needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.

Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 15 +---
 drivers/pci/host/Kconfig   |  4 +-
 drivers/pci/host/pcie-designware.c |  4 +-
 drivers/pci/host/pcie-designware.h |  2 +
 drivers/pci/host/pcie-hisi.c   | 45 ++
 5 files changed, 60 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 59c2f47..87a597a 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -9,10 +9,13 @@ Additional properties are described here:
 
 Required properties
 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
-- reg: Should contain rc_dbi, config registers location and length.
-- reg-names: Must include the following entries:
+- reg: Should contain rc_dbi and  either config or ecam-cfg registers
+   location and length (it depends on the platform BIOS).
+- reg-names: Must include
   "rc_dbi": controller configuration registers;
-  "config": PCIe configuration space registers.
+  and one of the following entries:
+"config": PCIe configuration space registers for non-ECAM platforms.
+"ecam-cfg": PCIe configuration space registers for ECAM platforms
 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
 - port-id: Should be 0, 1, 2 or 3.
 
@@ -23,8 +26,10 @@ Optional properties:
 Hip05 Example (note that Hip06 is the same except compatible):
pcie@0xb008 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
-   reg = <0 0xb008 0 0x1>, <0x220 0x 0 0x2000>;
-   reg-names = "rc_dbi", "config";
+   reg = <0 0xb008 0 0x1>,
+ <0x220 0x 0 0x2000>
+   /* or <0x220 0x0010 0 0x0f0> for ecam-cfg*/;
+   reg-names = "rc_dbi", "config" /* or "ecam-cfg" */;
bus-range = <0  15>;
msi-parent = <_pcie>;
#address-cells = <3>;
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d7e7c0a..ae98644 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -219,13 +219,13 @@ config PCIE_ALTERA_MSI
 
 config PCI_HISI
depends on OF && ARM64
-   bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs PCIe controllers"
depends on PCI_MSI_IRQ_DOMAIN
select PCIEPORTBUS
select PCIE_DW
help
  Say Y here if you want PCIe controller support on HiSilicon
- Hip05 and Hip06 SoCs
+ Hip05 and Hip06 and Hip07 SoCs
 
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
diff --git a/drivers/pci/host/pcie-designware.c 
b/drivers/pci/host/pcie-designware.c
index 035f50c..da11644 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -101,8 +101,6 @@
 #define PCIE_PHY_DEBUG_R1_LINK_UP  (0x1 << 4)
 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
 
-static struct pci_ops dw_pcie_ops;
-
 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
 {
if ((uintptr_t)addr & (size - 1)) {
@@ -800,7 +798,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 }
 
-static struct pci_ops dw_pcie_ops = {
+struct pci_ops dw_pcie_ops = {
.read = dw_pcie_rd_conf,
.write = dw_pcie_wr_conf,
 };
diff --git a/drivers/pci/host/pcie-designware.h 
b/drivers/pci/host/pcie-designware.h
index a567ea2..30d228a 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -83,4 +83,6 @@ struct pcie_host_ops {
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+extern struct pci_ops dw_pcie_ops;
+
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 56154

[PATCH V3 1/2] PCI: hisi: Add ECAM support for devices that are not RC

[Dongdong Liu]

This patch modifies the current Hip05/Hip06 PCIe host
controller driver to add support for 'almost ECAM'
compliant platforms. Some controllers are ECAM compliant
for all the devices of the hierarchy except the root
complex; this patch adds support for such controllers.

This is needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.

Signed-off-by: Gabriele Paoloni 
Signed-off-by: Dongdong Liu 
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 15 +---
 drivers/pci/host/Kconfig   |  4 +-
 drivers/pci/host/pcie-designware.c |  4 +-
 drivers/pci/host/pcie-designware.h |  2 +
 drivers/pci/host/pcie-hisi.c   | 45 ++
 5 files changed, 60 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 59c2f47..87a597a 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -9,10 +9,13 @@ Additional properties are described here:
 
 Required properties
 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
-- reg: Should contain rc_dbi, config registers location and length.
-- reg-names: Must include the following entries:
+- reg: Should contain rc_dbi and  either config or ecam-cfg registers
+   location and length (it depends on the platform BIOS).
+- reg-names: Must include
   "rc_dbi": controller configuration registers;
-  "config": PCIe configuration space registers.
+  and one of the following entries:
+"config": PCIe configuration space registers for non-ECAM platforms.
+"ecam-cfg": PCIe configuration space registers for ECAM platforms
 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
 - port-id: Should be 0, 1, 2 or 3.
 
@@ -23,8 +26,10 @@ Optional properties:
 Hip05 Example (note that Hip06 is the same except compatible):
pcie@0xb008 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
-   reg = <0 0xb008 0 0x1>, <0x220 0x 0 0x2000>;
-   reg-names = "rc_dbi", "config";
+   reg = <0 0xb008 0 0x1>,
+ <0x220 0x 0 0x2000>
+   /* or <0x220 0x0010 0 0x0f0> for ecam-cfg*/;
+   reg-names = "rc_dbi", "config" /* or "ecam-cfg" */;
bus-range = <0  15>;
msi-parent = <_pcie>;
#address-cells = <3>;
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d7e7c0a..ae98644 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -219,13 +219,13 @@ config PCIE_ALTERA_MSI
 
 config PCI_HISI
depends on OF && ARM64
-   bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs PCIe controllers"
depends on PCI_MSI_IRQ_DOMAIN
select PCIEPORTBUS
select PCIE_DW
help
  Say Y here if you want PCIe controller support on HiSilicon
- Hip05 and Hip06 SoCs
+ Hip05 and Hip06 and Hip07 SoCs
 
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
diff --git a/drivers/pci/host/pcie-designware.c 
b/drivers/pci/host/pcie-designware.c
index 035f50c..da11644 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -101,8 +101,6 @@
 #define PCIE_PHY_DEBUG_R1_LINK_UP  (0x1 << 4)
 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
 
-static struct pci_ops dw_pcie_ops;
-
 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
 {
if ((uintptr_t)addr & (size - 1)) {
@@ -800,7 +798,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 }
 
-static struct pci_ops dw_pcie_ops = {
+struct pci_ops dw_pcie_ops = {
.read = dw_pcie_rd_conf,
.write = dw_pcie_wr_conf,
 };
diff --git a/drivers/pci/host/pcie-designware.h 
b/drivers/pci/host/pcie-designware.h
index a567ea2..30d228a 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -83,4 +83,6 @@ struct pcie_host_ops {
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+extern struct pci_ops dw_pcie_ops;
+
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 56154c2..555c964 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers

[PATCH V3 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- rework the current HiSilicon driver to add support for ECAM
  platforms(not RC).
- adds the HiSilicon ACPI specific quirks.

This patchset is based on 4.9-rc1 and add Tomasz quirks V6 pathcset.
Tomasz quirks V6 patchset can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset. 
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers

Dongdong Liu (2):
  PCI: hisi: Add ECAM support for devices that are not RC
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 .../devicetree/bindings/pci/hisilicon-pcie.txt |  15 +-
 MAINTAINERS|   1 +
 drivers/acpi/pci_mcfg.c|  15 ++
 drivers/pci/host/Kconfig   |  12 +-
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-designware.c |   4 +-
 drivers/pci/host/pcie-designware.h |   2 +
 drivers/pci/host/pcie-hisi-acpi.c  | 170 +
 drivers/pci/host/pcie-hisi.c   |  45 ++
 include/linux/pci-ecam.h   |   4 +
 10 files changed, 259 insertions(+), 10 deletions(-)
 create mode 100755 drivers/pci/host/pcie-hisi-acpi.c

-- 
1.9.1

[PATCH V3 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  15 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 170 ++
 include/linux/pci-ecam.h  |   4 +
 6 files changed, 199 insertions(+)
 create mode 100755 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin <shawn@rock-chips.com>
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index bb2c508..135a9b4 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -96,6 +96,21 @@ struct mcfg_fixup {
THUNDER_ECAM_MCFG(2, 12),
THUNDER_ECAM_MCFG(2, 13),
 #endif
+#define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+
+#ifdef CONFIG_PCI_HISI_ACPI
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
+
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100755
index 000..5650d91
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,170 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F
+
+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_link_up_acpi(struct pci_config_window *cfg)
+{
+   u32 val;
+   void __iomem *reg_base = cfg->priv;
+
+   val = readl(reg_base + DEBUG0);
+   return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+}
+
+static int hisi_pcie_acpi_r

[PATCH V3 0/2] Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC
PCIe controllers.
The two patches respectively:
- rework the current HiSilicon driver to add support for ECAM
  platforms(not RC).
- adds the HiSilicon ACPI specific quirks.

This patchset is based on 4.9-rc1 and add Tomasz quirks V6 pathcset.
Tomasz quirks V6 patchset can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git(pci/ecam-v6)

v2 -> v3:
- rebase against 4.9-rc1 and add Tomasz quirks V6 pathcset. 
- obtain rc base addresses from PNP0C02 as subdevice of PNP0A03 instead of
  hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
  Arnd comments.

v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers

Dongdong Liu (2):
  PCI: hisi: Add ECAM support for devices that are not RC
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 .../devicetree/bindings/pci/hisilicon-pcie.txt |  15 +-
 MAINTAINERS|   1 +
 drivers/acpi/pci_mcfg.c|  15 ++
 drivers/pci/host/Kconfig   |  12 +-
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-designware.c |   4 +-
 drivers/pci/host/pcie-designware.h |   2 +
 drivers/pci/host/pcie-hisi-acpi.c  | 170 +
 drivers/pci/host/pcie-hisi.c   |  45 ++
 include/linux/pci-ecam.h   |   4 +
 10 files changed, 259 insertions(+), 10 deletions(-)
 create mode 100755 drivers/pci/host/pcie-hisi-acpi.c

-- 
1.9.1

[PATCH V3 2/2] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we support ECAM access.
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_init() to obtain rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 MAINTAINERS   |   1 +
 drivers/acpi/pci_mcfg.c   |  15 
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/pcie-hisi-acpi.c | 170 ++
 include/linux/pci-ecam.h  |   4 +
 6 files changed, 199 insertions(+)
 create mode 100755 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7..b224caa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9358,6 +9358,7 @@ L:linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR ROCKCHIP
 M: Shawn Lin 
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index bb2c508..135a9b4 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -96,6 +96,21 @@ struct mcfg_fixup {
THUNDER_ECAM_MCFG(2, 12),
THUNDER_ECAM_MCFG(2, 13),
 #endif
+#define PCI_ACPI_QUIRK_QUAD_DOM(table_id, seg, ops) \
+   { "HISI  ", table_id, 0, seg + 0, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 1, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 2, MCFG_BUS_ANY, ops }, \
+   { "HISI  ", table_id, 0, seg + 3, MCFG_BUS_ANY, ops }
+
+#ifdef CONFIG_PCI_HISI_ACPI
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP05   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP06   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 0, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 4, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 8, _pcie_ops),
+   PCI_ACPI_QUIRK_QUAD_DOM("HIP07   ", 12, _pcie_ops),
+#endif
+
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index ae98644..9ff2bcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 and Hip07 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 and Hip07 SoCs ACPI PCIe controllers"
+   select PNP
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 and Hip07 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 084cb49..9402858 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100755
index 000..5650d91
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,170 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#define DEBUG0 0x728
+#define PCIE_LTSSM_LINKUP_STATE0x11
+#define PCIE_LTSSM_STATE_MASK  0x3F
+
+static const struct acpi_device_id hisi_pcie_rc_res_ids[] = {
+   {"HISI0081", 0},
+   {"", 0},
+};
+
+static int hisi_pcie_link_up_acpi(struct pci_config_window *cfg)
+{
+   u32 val;
+   void __iomem *reg_base = cfg->priv;
+
+   val = readl(reg_base + DEBUG0);
+   return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+}
+
+static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+{
+   struct pci_config_window *cfg = bus->sysdata;
+

Re: [PATCH V6 2/5] PCI/ACPI: Check platform specific ECAM quirks

[Dongdong Liu]

Hi Tomasz

在 2016/9/13 14:32, Tomasz Nowicki 写道:

Hi Liu,

On 13.09.2016 04:36, Dongdong Liu wrote:

Hi Tomasz

在 2016/9/10 3:24, Tomasz Nowicki 写道:

Some platforms may not be fully compliant with generic set of PCI config
accessors. For these cases we implement the way to overwrite CFG
accessors
set and configuration space range.

In first place pci_mcfg_parse() saves machine's IDs and revision number
(these come from MCFG header) in order to match against known quirk
entries.
Then the algorithm traverses available quirk list (static array),
matches against <oem_id, oem_table_id, rev, domain, bus number range> and
returns custom PCI config ops and/or CFG resource structure.

When adding new quirk there are two possibilities:
1. Override default pci_generic_ecam_ops ops but CFG resource comes
from MCFG
{ "OEM_ID", "OEM_TABLE_ID", , , , _ops,
MCFG_RES_EMPTY },
2. Override default pci_generic_ecam_ops ops and CFG resource. For
this case
it is also allowed get CFG resource from quirk entry w/o having it in
MCFG.
{ "OEM_ID", "OEM_TABLE_ID", , , , _ops,
   DEFINE_RES_MEM(START, SIZE) },

pci_generic_ecam_ops and MCFG entries will be used for platforms
free from quirks.

Signed-off-by: Tomasz Nowicki <t...@semihalf.com>
Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
  drivers/acpi/pci_mcfg.c | 80
+
  1 file changed, 74 insertions(+), 6 deletions(-)

diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ffcc651..2b8acc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -32,6 +32,59 @@ struct mcfg_entry {
  u8bus_start;
  u8bus_end;
  };
+struct mcfg_fixup {
+char oem_id[ACPI_OEM_ID_SIZE + 1];
+char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
+u32 oem_revision;
+u16 seg;
+struct resource bus_range;
+struct pci_ecam_ops *ops;
+struct resource cfgres;
+};
+
+#define MCFG_DOM_ANY(-1)
+#define MCFG_BUS_RANGE(start, end)DEFINE_RES_NAMED((start),\
+((end) - (start) + 1),\
+NULL, IORESOURCE_BUS)
+#define MCFG_BUS_ANYMCFG_BUS_RANGE(0x0, 0xff)
+#define MCFG_RES_EMPTYDEFINE_RES_NAMED(0, 0, NULL, 0)
+
+static struct mcfg_fixup mcfg_quirks[] = {
+/*{ OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
+};
+
+static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
+static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
+static u32 mcfg_oem_revision;
+
+static void pci_mcfg_match_quirks(struct acpi_pci_root *root,
+  struct resource *cfgres,
+  struct pci_ecam_ops **ecam_ops)
+{
+struct mcfg_fixup *f;
+int i;
+
+/*
+ * First match against PCI topology  then use OEM ID,
OEM
+ * table ID, and OEM revision from MCFG table standard header.
+ */
+for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++,
f++) {
+if (f->seg == root->segment &&


why not use MCFG_DOM_RANGE, I think MCFG_DOM_RANGE is better.
if drop MCFG_DOM_RANGE, mcfg_quirks[] will be more complex.

static struct mcfg_fixup mcfg_quirks[] = {
/*{ OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
/* SoC pass1.x */
{ "CAVIUM", "THUNDERX", 2, 0, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 1, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 2, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 3, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 10, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 11, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 12, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 13, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
#endif
.
};

As PATCH v5 we only need define mcfg_quirks as below, It looks better.
static struct pci_cfg_fixup mcfg_quirks[] __initconst = {
/*{ OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, pci_ops, init_hook
}, */
#ifdef CONFIG_PCI_HOST_THUNDER_PEM
/* Pass2.0 */
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(4, 9), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(14, 19), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
#endif
#ifdef CONFIG_PCI_HISI_ACPI
{ "HISI  ", "HIP05   ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
  NULL, hisi_pcie_acpi_hip05_in

Re: [PATCH V6 2/5] PCI/ACPI: Check platform specific ECAM quirks

[Dongdong Liu]

Hi Tomasz

在 2016/9/13 14:32, Tomasz Nowicki 写道:

Hi Liu,

On 13.09.2016 04:36, Dongdong Liu wrote:

Hi Tomasz

在 2016/9/10 3:24, Tomasz Nowicki 写道:

Some platforms may not be fully compliant with generic set of PCI config
accessors. For these cases we implement the way to overwrite CFG
accessors
set and configuration space range.

In first place pci_mcfg_parse() saves machine's IDs and revision number
(these come from MCFG header) in order to match against known quirk
entries.
Then the algorithm traverses available quirk list (static array),
matches against  and
returns custom PCI config ops and/or CFG resource structure.

When adding new quirk there are two possibilities:
1. Override default pci_generic_ecam_ops ops but CFG resource comes
from MCFG
{ "OEM_ID", "OEM_TABLE_ID", , , , _ops,
MCFG_RES_EMPTY },
2. Override default pci_generic_ecam_ops ops and CFG resource. For
this case
it is also allowed get CFG resource from quirk entry w/o having it in
MCFG.
{ "OEM_ID", "OEM_TABLE_ID", , , , _ops,
   DEFINE_RES_MEM(START, SIZE) },

pci_generic_ecam_ops and MCFG entries will be used for platforms
free from quirks.

Signed-off-by: Tomasz Nowicki 
Signed-off-by: Dongdong Liu 
Signed-off-by: Christopher Covington 
---
  drivers/acpi/pci_mcfg.c | 80
+
  1 file changed, 74 insertions(+), 6 deletions(-)

diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ffcc651..2b8acc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -32,6 +32,59 @@ struct mcfg_entry {
  u8bus_start;
  u8bus_end;
  };
+struct mcfg_fixup {
+char oem_id[ACPI_OEM_ID_SIZE + 1];
+char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
+u32 oem_revision;
+u16 seg;
+struct resource bus_range;
+struct pci_ecam_ops *ops;
+struct resource cfgres;
+};
+
+#define MCFG_DOM_ANY(-1)
+#define MCFG_BUS_RANGE(start, end)DEFINE_RES_NAMED((start),\
+((end) - (start) + 1),\
+NULL, IORESOURCE_BUS)
+#define MCFG_BUS_ANYMCFG_BUS_RANGE(0x0, 0xff)
+#define MCFG_RES_EMPTYDEFINE_RES_NAMED(0, 0, NULL, 0)
+
+static struct mcfg_fixup mcfg_quirks[] = {
+/*{ OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
+};
+
+static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
+static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
+static u32 mcfg_oem_revision;
+
+static void pci_mcfg_match_quirks(struct acpi_pci_root *root,
+  struct resource *cfgres,
+  struct pci_ecam_ops **ecam_ops)
+{
+struct mcfg_fixup *f;
+int i;
+
+/*
+ * First match against PCI topology  then use OEM ID,
OEM
+ * table ID, and OEM revision from MCFG table standard header.
+ */
+for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++,
f++) {
+if (f->seg == root->segment &&


why not use MCFG_DOM_RANGE, I think MCFG_DOM_RANGE is better.
if drop MCFG_DOM_RANGE, mcfg_quirks[] will be more complex.

static struct mcfg_fixup mcfg_quirks[] = {
/*{ OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
/* SoC pass1.x */
{ "CAVIUM", "THUNDERX", 2, 0, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 1, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 2, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 3, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 10, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 11, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 12, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 13, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
#endif
.
};

As PATCH v5 we only need define mcfg_quirks as below, It looks better.
static struct pci_cfg_fixup mcfg_quirks[] __initconst = {
/*{ OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, pci_ops, init_hook
}, */
#ifdef CONFIG_PCI_HOST_THUNDER_PEM
/* Pass2.0 */
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(4, 9), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(14, 19), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
#endif
#ifdef CONFIG_PCI_HISI_ACPI
{ "HISI  ", "HIP05   ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
  NULL, hisi_pcie_acpi_hip05_init},
{ "HISI  ", "HIP06   ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
  NULL, hisi_pcie_acpi_hip06_init},
{ "HISI  

Re: [PATCH V6 2/5] PCI/ACPI: Check platform specific ECAM quirks

[Dongdong Liu]

Hi Tomasz

在 2016/9/10 3:24, Tomasz Nowicki 写道:

Some platforms may not be fully compliant with generic set of PCI config
accessors. For these cases we implement the way to overwrite CFG accessors
set and configuration space range.

In first place pci_mcfg_parse() saves machine's IDs and revision number
(these come from MCFG header) in order to match against known quirk entries.
Then the algorithm traverses available quirk list (static array),
matches against <oem_id, oem_table_id, rev, domain, bus number range> and
returns custom PCI config ops and/or CFG resource structure.

When adding new quirk there are two possibilities:
1. Override default pci_generic_ecam_ops ops but CFG resource comes from MCFG
{ "OEM_ID", "OEM_TABLE_ID", , , , _ops, MCFG_RES_EMPTY 
},
2. Override default pci_generic_ecam_ops ops and CFG resource. For this case
it is also allowed get CFG resource from quirk entry w/o having it in MCFG.
{ "OEM_ID", "OEM_TABLE_ID", , , , _ops,
   DEFINE_RES_MEM(START, SIZE) },

pci_generic_ecam_ops and MCFG entries will be used for platforms
free from quirks.

Signed-off-by: Tomasz Nowicki <t...@semihalf.com>
Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
  drivers/acpi/pci_mcfg.c | 80 +
  1 file changed, 74 insertions(+), 6 deletions(-)

diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ffcc651..2b8acc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -32,6 +32,59 @@ struct mcfg_entry {
u8  bus_start;
u8  bus_end;
  };
+struct mcfg_fixup {
+   char oem_id[ACPI_OEM_ID_SIZE + 1];
+   char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
+   u32 oem_revision;
+   u16 seg;
+   struct resource bus_range;
+   struct pci_ecam_ops *ops;
+   struct resource cfgres;
+};
+
+#define MCFG_DOM_ANY   (-1)
+#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start),   \
+   ((end) - (start) + 1),  \
+   NULL, IORESOURCE_BUS)
+#define MCFG_BUS_ANY   MCFG_BUS_RANGE(0x0, 0xff)
+#define MCFG_RES_EMPTY DEFINE_RES_NAMED(0, 0, NULL, 0)
+
+static struct mcfg_fixup mcfg_quirks[] = {
+/* { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
+};
+
+static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
+static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
+static u32 mcfg_oem_revision;
+
+static void pci_mcfg_match_quirks(struct acpi_pci_root *root,
+ struct resource *cfgres,
+ struct pci_ecam_ops **ecam_ops)
+{
+   struct mcfg_fixup *f;
+   int i;
+
+   /*
+* First match against PCI topology  then use OEM ID, OEM
+* table ID, and OEM revision from MCFG table standard header.
+*/
+   for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
+   if (f->seg == root->segment &&


why not use MCFG_DOM_RANGE, I think MCFG_DOM_RANGE is better.
if drop MCFG_DOM_RANGE, mcfg_quirks[] will be more complex.

static struct mcfg_fixup mcfg_quirks[] = {
/*  { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
/* SoC pass1.x */
{ "CAVIUM", "THUNDERX", 2, 0, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 1, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 2, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 3, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 10, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 11, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 12, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 13, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
#endif
.
};

As PATCH v5 we only need define mcfg_quirks as below, It looks better.
static struct pci_cfg_fixup mcfg_quirks[] __initconst = {
/*  { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, pci_ops, init_hook }, */
#ifdef CONFIG_PCI_HOST_THUNDER_PEM
/* Pass2.0 */
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(4, 9), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(14, 19), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
#endif
#if

Re: [PATCH V6 2/5] PCI/ACPI: Check platform specific ECAM quirks

[Dongdong Liu]

Hi Tomasz

在 2016/9/10 3:24, Tomasz Nowicki 写道:

Some platforms may not be fully compliant with generic set of PCI config
accessors. For these cases we implement the way to overwrite CFG accessors
set and configuration space range.

In first place pci_mcfg_parse() saves machine's IDs and revision number
(these come from MCFG header) in order to match against known quirk entries.
Then the algorithm traverses available quirk list (static array),
matches against  and
returns custom PCI config ops and/or CFG resource structure.

When adding new quirk there are two possibilities:
1. Override default pci_generic_ecam_ops ops but CFG resource comes from MCFG
{ "OEM_ID", "OEM_TABLE_ID", , , , _ops, MCFG_RES_EMPTY 
},
2. Override default pci_generic_ecam_ops ops and CFG resource. For this case
it is also allowed get CFG resource from quirk entry w/o having it in MCFG.
{ "OEM_ID", "OEM_TABLE_ID", , , , _ops,
   DEFINE_RES_MEM(START, SIZE) },

pci_generic_ecam_ops and MCFG entries will be used for platforms
free from quirks.

Signed-off-by: Tomasz Nowicki 
Signed-off-by: Dongdong Liu 
Signed-off-by: Christopher Covington 
---
  drivers/acpi/pci_mcfg.c | 80 +
  1 file changed, 74 insertions(+), 6 deletions(-)

diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ffcc651..2b8acc7 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -32,6 +32,59 @@ struct mcfg_entry {
u8  bus_start;
u8  bus_end;
  };
+struct mcfg_fixup {
+   char oem_id[ACPI_OEM_ID_SIZE + 1];
+   char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
+   u32 oem_revision;
+   u16 seg;
+   struct resource bus_range;
+   struct pci_ecam_ops *ops;
+   struct resource cfgres;
+};
+
+#define MCFG_DOM_ANY   (-1)
+#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start),   \
+   ((end) - (start) + 1),  \
+   NULL, IORESOURCE_BUS)
+#define MCFG_BUS_ANY   MCFG_BUS_RANGE(0x0, 0xff)
+#define MCFG_RES_EMPTY DEFINE_RES_NAMED(0, 0, NULL, 0)
+
+static struct mcfg_fixup mcfg_quirks[] = {
+/* { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
+};
+
+static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
+static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
+static u32 mcfg_oem_revision;
+
+static void pci_mcfg_match_quirks(struct acpi_pci_root *root,
+ struct resource *cfgres,
+ struct pci_ecam_ops **ecam_ops)
+{
+   struct mcfg_fixup *f;
+   int i;
+
+   /*
+* First match against PCI topology  then use OEM ID, OEM
+* table ID, and OEM revision from MCFG table standard header.
+*/
+   for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
+   if (f->seg == root->segment &&


why not use MCFG_DOM_RANGE, I think MCFG_DOM_RANGE is better.
if drop MCFG_DOM_RANGE, mcfg_quirks[] will be more complex.

static struct mcfg_fixup mcfg_quirks[] = {
/*  { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
/* SoC pass1.x */
{ "CAVIUM", "THUNDERX", 2, 0, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 1, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 2, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 3, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 10, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 11, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 12, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
{ "CAVIUM", "THUNDERX", 2, 13, MCFG_BUS_ANY, _thunder_ecam_ops,
  MCFG_RES_EMPTY},
#endif
.
};

As PATCH v5 we only need define mcfg_quirks as below, It looks better.
static struct pci_cfg_fixup mcfg_quirks[] __initconst = {
/*  { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, pci_ops, init_hook }, */
#ifdef CONFIG_PCI_HOST_THUNDER_PEM
/* Pass2.0 */
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(4, 9), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(14, 19), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
#endif
#ifdef CONFIG_PCI_HISI_ACPI
{ "HISI  ", "HIP05   ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Rafael

在 2016/9/2 7:38, Rafael J. Wysocki 写道:

On Thursday, September 01, 2016 11:23:42 AM Dongdong Liu wrote:


在 2016/9/1 6:56, Rafael J. Wysocki 写道:

On Wednesday, August 31, 2016 07:48:14 PM Dongdong Liu wrote:

Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>


Well, what exactly is the ACPI support you're adding?  Is it the ECAM part only
or is there anything more to it?



Hi Rafael, thanks for replying.

Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

In our case we cannot use the standard MCFG object to pass the RC itself config 
space addresses.
The more discuss information can be found:
https://lkml.org/lkml/2016/2/22/1087
[...]
I have looked into this and in our case we cannot use the
standard MCFG object to pass the RC config space addresses.

The reason is that in our HW we have the config base addresses of the
root complex ports that are less than 0x10 byte distant one from
the other as we only map the first 0x1 bytes.
Now the MCFG acpi framework always fix the MCFG resource size to 0x10
for each bus; therefore if we pass our RC addresses through MCFG we end
up with a resource conflict.
To give you a practical example we are in a situation where we have:

port0: [0xb008 - 0xb008 + 0x1]
port1: [0xb009 - 0xb009 + 0x1]
port2: [0xb00A - 0xb00A + 0x1]
port3: [0xb00B - 0xb00B + 0x1]
So if we pass the base addresses through MCFG the resources
will overlap as MCFG will consider 0x10 size for each base
address of the root complex (only the RC bus uses that address)
So far I do not see many option other than using _DSD to pass
these RC config base addresses.


It still is not entirely clear to me what the "ACPI support" is here.

Do you read any configuration information from the ACPI tables or similar?

If so, where is the format of it documented?



Since Our host bridge is non ECAM only for the RC bus config space,for any 
other bus underneath the root bus we support ECAM access,
we need to override these accessors prior to PCI buses enumeration.

As below is MCFG table configuration.
0x2200400~0x220040f (bus 0x40) addresses are wasted, because Our host 
bridge is non ECAM only for the RC.
We use RC base address(0xb008)+offset to access our RC config space.
0x2200410~0x22007ff addresses are used to aceess EP config space (bus 
0x41~0x7f).This support ECAM access.

MCFG Table
...
{
  0x220,  //Base Address
  0x0001, //Segment Group Number
  0x40,   //Start Bus Number
  0x7f,   //End Bus Number
  0x, //Reserved
},
...

DSDT Table
//PCIe Root bus
Device (PCI1)
{
Name (_HID, "PNP0A08") // PCI Express Root Bridge
Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
Name(_SEG, 1) // Segment of this Root complex
Name(_BBN, 0x40) // Base Bus Number
Name(_CCA, 1)
Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0,// AddressGranularity
0x40, // AddressMinimum - Minimum Bus Number
0x7f, // AddressMaximum - Maximum Bus Number
0,// AddressTranslation - Set to 0
0x40  // RangeLength - Number of Busses
)
...
...
}) // Name(RBUF)
  Return (RBUF)
} // Method(_CRS)
} // Device(PCI1)


As below hisi_pcie_acpi_rd_conf() is our config read implementation.
static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  int size, u32 *val)
{
struct pci_config_window *cfg = bus->sysdata;
void __iomem *reg_base = cfg->priv;

if (hisi_pcie_acpi_valid_config(cfg, bus, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
/* Access RC config space */
if (bus->number == cfg->busr.start)
return hisi_pcie_common_cfg_read(reg_base, where, size, val);

/* Access EP conf

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Hi Rafael

在 2016/9/2 7:38, Rafael J. Wysocki 写道:

On Thursday, September 01, 2016 11:23:42 AM Dongdong Liu wrote:


在 2016/9/1 6:56, Rafael J. Wysocki 写道:

On Wednesday, August 31, 2016 07:48:14 PM Dongdong Liu wrote:

Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 


Well, what exactly is the ACPI support you're adding?  Is it the ECAM part only
or is there anything more to it?



Hi Rafael, thanks for replying.

Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

In our case we cannot use the standard MCFG object to pass the RC itself config 
space addresses.
The more discuss information can be found:
https://lkml.org/lkml/2016/2/22/1087
[...]
I have looked into this and in our case we cannot use the
standard MCFG object to pass the RC config space addresses.

The reason is that in our HW we have the config base addresses of the
root complex ports that are less than 0x10 byte distant one from
the other as we only map the first 0x1 bytes.
Now the MCFG acpi framework always fix the MCFG resource size to 0x10
for each bus; therefore if we pass our RC addresses through MCFG we end
up with a resource conflict.
To give you a practical example we are in a situation where we have:

port0: [0xb008 - 0xb008 + 0x1]
port1: [0xb009 - 0xb009 + 0x1]
port2: [0xb00A - 0xb00A + 0x1]
port3: [0xb00B - 0xb00B + 0x1]
So if we pass the base addresses through MCFG the resources
will overlap as MCFG will consider 0x10 size for each base
address of the root complex (only the RC bus uses that address)
So far I do not see many option other than using _DSD to pass
these RC config base addresses.


It still is not entirely clear to me what the "ACPI support" is here.

Do you read any configuration information from the ACPI tables or similar?

If so, where is the format of it documented?



Since Our host bridge is non ECAM only for the RC bus config space,for any 
other bus underneath the root bus we support ECAM access,
we need to override these accessors prior to PCI buses enumeration.

As below is MCFG table configuration.
0x2200400~0x220040f (bus 0x40) addresses are wasted, because Our host 
bridge is non ECAM only for the RC.
We use RC base address(0xb008)+offset to access our RC config space.
0x2200410~0x22007ff addresses are used to aceess EP config space (bus 
0x41~0x7f).This support ECAM access.

MCFG Table
...
{
  0x220,  //Base Address
  0x0001, //Segment Group Number
  0x40,   //Start Bus Number
  0x7f,   //End Bus Number
  0x, //Reserved
},
...

DSDT Table
//PCIe Root bus
Device (PCI1)
{
Name (_HID, "PNP0A08") // PCI Express Root Bridge
Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
Name(_SEG, 1) // Segment of this Root complex
Name(_BBN, 0x40) // Base Bus Number
Name(_CCA, 1)
Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0,// AddressGranularity
0x40, // AddressMinimum - Minimum Bus Number
0x7f, // AddressMaximum - Maximum Bus Number
0,// AddressTranslation - Set to 0
0x40  // RangeLength - Number of Busses
)
...
...
}) // Name(RBUF)
  Return (RBUF)
} // Method(_CRS)
} // Device(PCI1)


As below hisi_pcie_acpi_rd_conf() is our config read implementation.
static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  int size, u32 *val)
{
struct pci_config_window *cfg = bus->sysdata;
void __iomem *reg_base = cfg->priv;

if (hisi_pcie_acpi_valid_config(cfg, bus, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
/* Access RC config space */
if (bus->number == cfg->busr.start)
return hisi_pcie_common_cfg_read(reg_base, where, size, val);

/* Access EP config space */
return pci_generic_config_read(bus, devfn, whe

Re: [RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

Hi Arnd

在 2016/9/1 22:02, Arnd Bergmann 写道:



2. We need to backward compatible with the old dt way config access as below 
code,
so we have to call hisi_pcie_common_cfg_read() when accessing the RC config 
space.
For this, we have to call hisi_pcie_common_cfg_read().

drivers/pci/host/pcie-hisi.c
static inline int hisi_pcie_cfg_read(struct pcie_port *pp, int where,
int size, u32 *val)
{
struct hisi_pcie *pcie = to_hisi_pcie(pp);

return hisi_pcie_common_cfg_read(pcie->reg_base, where, size, val);
}

static struct pcie_host_ops hisi_pcie_host_ops = {
.rd_own_conf = hisi_pcie_cfg_read,
.wr_own_conf = hisi_pcie_cfg_write,
.link_up = hisi_pcie_link_up,
};


I think this would be easier if you separate the ACPI code from the
DT code and not try to have a common file used for both.

Sharing the config space accessors really isn't worth it when both
variants are fairly simple to do, but they don't fit in a common
model because one is called from the ACPI quirks and the other
is called from the dw-pcie driver with completely different calling
conventions.


I agree, many thanks.

Thanks
Dongdong


ARnd
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To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
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More majordomo info at  http://vger.kernel.org/majordomo-info.html

.

Re: [RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

Hi Arnd

在 2016/9/1 22:02, Arnd Bergmann 写道:



2. We need to backward compatible with the old dt way config access as below 
code,
so we have to call hisi_pcie_common_cfg_read() when accessing the RC config 
space.
For this, we have to call hisi_pcie_common_cfg_read().

drivers/pci/host/pcie-hisi.c
static inline int hisi_pcie_cfg_read(struct pcie_port *pp, int where,
int size, u32 *val)
{
struct hisi_pcie *pcie = to_hisi_pcie(pp);

return hisi_pcie_common_cfg_read(pcie->reg_base, where, size, val);
}

static struct pcie_host_ops hisi_pcie_host_ops = {
.rd_own_conf = hisi_pcie_cfg_read,
.wr_own_conf = hisi_pcie_cfg_write,
.link_up = hisi_pcie_link_up,
};


I think this would be easier if you separate the ACPI code from the
DT code and not try to have a common file used for both.

Sharing the config space accessors really isn't worth it when both
variants are fairly simple to do, but they don't fit in a common
model because one is called from the ACPI quirks and the other
is called from the dw-pcie driver with completely different calling
conventions.


I agree, many thanks.

Thanks
Dongdong


ARnd
--
To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

.

Re: [RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

Hi Arnd

在 2016/9/1 15:41, Arnd Bergmann 写道:

On Thursday, September 1, 2016 10:05:29 AM CEST Dongdong Liu wrote:


在 2016/8/31 19:45, Arnd Bergmann 写道:

On Wednesday, August 31, 2016 7:48:12 PM CEST Dongdong Liu wrote:

+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+   u32 reg;
+   u32 reg_val;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   reg_val = readl(reg_base + reg);
+
+   if (size == 1)
+   *val = *(u8 __force *) walker;
+   else if (size == 2)
+   *val = *(u16 __force *) walker;


What is the __force for?


Hi Arnd, thanks for replying.

__force is used to, well, force a conversion, like casting from or to a bitwise 
type, else the Sparse checker will throw a warning.


I know what it's for in general, but in this case there is no __bitwise
or __iomem or any other annotation on either side of the assignment.


Thanks for you point that.






+   else if (size == 4)
+   *val = reg_val;
+   else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;


It looks like you are reimplementing 
pci_generic_config_read32/pci_generic_config_write32
read here, better use them directly.



For our host bridge, access RC and EP config space are not the same way.
Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

hisi_pcie_common_cfg_read is used to read RC config space, only supports 32-bit 
config access.
hisi_pcie_common_cfg_read/hisi_pcie_common_cfg_write may change as below will 
be better.

/* HipXX PCIe host only supports 32-bit config access */
int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
  u32 *val)
{
void __iomem *addr;

addr = reg_base + (where & ~0x3);
*val = readl(addr);

if (size <= 2)
*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);

return PCIBIOS_SUCCESSFUL;
}


My point was: why not call pci_generic_config_read32() when accessing
the RC config space instead of duplicating the code from it?


I know your point.

1. For our host bridge , ".map_bus = pci_ecam_map_bus" is only suitable for
accessing the EP config space.
pci_generic_config_read32() need to call "addr = bus->ops->map_bus(bus, devfn, where 
& ~0x3);",

drivers/pci/host/pcie-hisi-acpi.c
static struct pci_ops hisi_pcie_ops = {
.map_bus = pci_ecam_map_bus,
.read = hisi_pcie_acpi_rd_conf,
.write = hisi_pcie_acpi_wr_conf,
};

Yes, we can change ".map_bus = pci_ecam_map_bus" to ".map_bus = 
hisi_pci_map_bus", and implentment hisi_pci_map_bus as below,
then we will not need to call hisi_pcie_common_cfg_read().

void __iomem *hisi_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int 
where)
{
struct pci_config_window *cfg = bus->sysdata;
void __iomem *reg_base = cfg->priv;

/* for RC config access*/
if (bus->number == cfg->busr.start)
return reg_base + (where & ~0x3);
else
/* for EP config access */
return pci_ecam_map_bus(bus, devfn, where);
}

and hisi_pcie_acpi_rd_conf() need to change as below.
static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  int size, u32 *val)
{
struct pci_config_window *cfg = bus->sysdata;

if (hisi_pcie_acpi_valid_config(cfg, bus, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;

/* access RC config space */
if (bus->number == cfg->busr.start)
return pci_generic_config_read32(bus, devfn, where, size, val);

/* access EP config space */
return pci_generic_config_read(bus, devfn, where, size, val);
}


2. We need to backward compatible with the old dt way config access as below 
code,
so we have to call hisi_pcie_common_cfg_read() when accessing the RC config 
space.
For this, we have to call hisi_pcie_common_cfg_read().

drivers/pci/host/pcie-hisi.c
static inline int hisi_pcie_cfg_read(struct pcie_port *pp, int where,
int size, u32 *val)
{
struct hisi_pcie *pcie = to_hisi_pcie(pp);

return hisi_pcie_common_cfg_read(pcie->reg_base, where, size, val);
}

static struct pcie_host_ops hisi_pcie_host_ops = {
.rd_own_conf = hisi_pcie_cfg_read,
.wr_own_conf = hisi_pcie_cfg_write,
.link_up = hisi_pcie_link_up,
};

Thanks
Dongdong


Arnd

.

Re: [RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

Hi Arnd

在 2016/9/1 15:41, Arnd Bergmann 写道:

On Thursday, September 1, 2016 10:05:29 AM CEST Dongdong Liu wrote:


在 2016/8/31 19:45, Arnd Bergmann 写道:

On Wednesday, August 31, 2016 7:48:12 PM CEST Dongdong Liu wrote:

+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+   u32 reg;
+   u32 reg_val;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   reg_val = readl(reg_base + reg);
+
+   if (size == 1)
+   *val = *(u8 __force *) walker;
+   else if (size == 2)
+   *val = *(u16 __force *) walker;


What is the __force for?


Hi Arnd, thanks for replying.

__force is used to, well, force a conversion, like casting from or to a bitwise 
type, else the Sparse checker will throw a warning.


I know what it's for in general, but in this case there is no __bitwise
or __iomem or any other annotation on either side of the assignment.


Thanks for you point that.






+   else if (size == 4)
+   *val = reg_val;
+   else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;


It looks like you are reimplementing 
pci_generic_config_read32/pci_generic_config_write32
read here, better use them directly.



For our host bridge, access RC and EP config space are not the same way.
Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

hisi_pcie_common_cfg_read is used to read RC config space, only supports 32-bit 
config access.
hisi_pcie_common_cfg_read/hisi_pcie_common_cfg_write may change as below will 
be better.

/* HipXX PCIe host only supports 32-bit config access */
int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
  u32 *val)
{
void __iomem *addr;

addr = reg_base + (where & ~0x3);
*val = readl(addr);

if (size <= 2)
*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);

return PCIBIOS_SUCCESSFUL;
}


My point was: why not call pci_generic_config_read32() when accessing
the RC config space instead of duplicating the code from it?


I know your point.

1. For our host bridge , ".map_bus = pci_ecam_map_bus" is only suitable for
accessing the EP config space.
pci_generic_config_read32() need to call "addr = bus->ops->map_bus(bus, devfn, where 
& ~0x3);",

drivers/pci/host/pcie-hisi-acpi.c
static struct pci_ops hisi_pcie_ops = {
.map_bus = pci_ecam_map_bus,
.read = hisi_pcie_acpi_rd_conf,
.write = hisi_pcie_acpi_wr_conf,
};

Yes, we can change ".map_bus = pci_ecam_map_bus" to ".map_bus = 
hisi_pci_map_bus", and implentment hisi_pci_map_bus as below,
then we will not need to call hisi_pcie_common_cfg_read().

void __iomem *hisi_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int 
where)
{
struct pci_config_window *cfg = bus->sysdata;
void __iomem *reg_base = cfg->priv;

/* for RC config access*/
if (bus->number == cfg->busr.start)
return reg_base + (where & ~0x3);
else
/* for EP config access */
return pci_ecam_map_bus(bus, devfn, where);
}

and hisi_pcie_acpi_rd_conf() need to change as below.
static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  int size, u32 *val)
{
struct pci_config_window *cfg = bus->sysdata;

if (hisi_pcie_acpi_valid_config(cfg, bus, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;

/* access RC config space */
if (bus->number == cfg->busr.start)
return pci_generic_config_read32(bus, devfn, where, size, val);

/* access EP config space */
return pci_generic_config_read(bus, devfn, where, size, val);
}


2. We need to backward compatible with the old dt way config access as below 
code,
so we have to call hisi_pcie_common_cfg_read() when accessing the RC config 
space.
For this, we have to call hisi_pcie_common_cfg_read().

drivers/pci/host/pcie-hisi.c
static inline int hisi_pcie_cfg_read(struct pcie_port *pp, int where,
int size, u32 *val)
{
struct hisi_pcie *pcie = to_hisi_pcie(pp);

return hisi_pcie_common_cfg_read(pcie->reg_base, where, size, val);
}

static struct pcie_host_ops hisi_pcie_host_ops = {
.rd_own_conf = hisi_pcie_cfg_read,
.wr_own_conf = hisi_pcie_cfg_write,
.link_up = hisi_pcie_link_up,
};

Thanks
Dongdong


Arnd

.

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

在 2016/9/1 6:56, Rafael J. Wysocki 写道:

On Wednesday, August 31, 2016 07:48:14 PM Dongdong Liu wrote:

Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>


Well, what exactly is the ACPI support you're adding?  Is it the ECAM part only
or is there anything more to it?



Hi Rafael, thanks for replying.

Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

In our case we cannot use the standard MCFG object to pass the RC itself config 
space addresses.
The more discuss information can be found:
https://lkml.org/lkml/2016/2/22/1087
[...]
I have looked into this and in our case we cannot use the
standard MCFG object to pass the RC config space addresses.

The reason is that in our HW we have the config base addresses of the
root complex ports that are less than 0x10 byte distant one from
the other as we only map the first 0x1 bytes.
Now the MCFG acpi framework always fix the MCFG resource size to 0x10
for each bus; therefore if we pass our RC addresses through MCFG we end
up with a resource conflict.
To give you a practical example we are in a situation where we have:

port0: [0xb008 - 0xb008 + 0x1]
port1: [0xb009 - 0xb009 + 0x1]
port2: [0xb00A - 0xb00A + 0x1]
port3: [0xb00B - 0xb00B + 0x1]
So if we pass the base addresses through MCFG the resources
will overlap as MCFG will consider 0x10 size for each base
address of the root complex (only the RC bus uses that address)
So far I do not see many option other than using _DSD to pass
these RC config base addresses.

Thanks and Regards

Gab
[...]

and

https://patchwork.kernel.org/patch/9178791/
[...]
Furthermore, I suspect we do not even need a way to pass the
non-ECAM compliant config space resources to the OS (ie we can't
change FW anymore anyway in some platforms) so the quirks hooks
are likely to hardcode the required config space addresses for
the respective MCFG match.

..
Thanks !
Lorenzo
[...]

So we hard code with our RC itself config resource.

Thanks
Dongdong


Thanks,
Rafael


.

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

在 2016/9/1 6:56, Rafael J. Wysocki 写道:

On Wednesday, August 31, 2016 07:48:14 PM Dongdong Liu wrote:

Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 


Well, what exactly is the ACPI support you're adding?  Is it the ECAM part only
or is there anything more to it?



Hi Rafael, thanks for replying.

Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

In our case we cannot use the standard MCFG object to pass the RC itself config 
space addresses.
The more discuss information can be found:
https://lkml.org/lkml/2016/2/22/1087
[...]
I have looked into this and in our case we cannot use the
standard MCFG object to pass the RC config space addresses.

The reason is that in our HW we have the config base addresses of the
root complex ports that are less than 0x10 byte distant one from
the other as we only map the first 0x1 bytes.
Now the MCFG acpi framework always fix the MCFG resource size to 0x10
for each bus; therefore if we pass our RC addresses through MCFG we end
up with a resource conflict.
To give you a practical example we are in a situation where we have:

port0: [0xb008 - 0xb008 + 0x1]
port1: [0xb009 - 0xb009 + 0x1]
port2: [0xb00A - 0xb00A + 0x1]
port3: [0xb00B - 0xb00B + 0x1]
So if we pass the base addresses through MCFG the resources
will overlap as MCFG will consider 0x10 size for each base
address of the root complex (only the RC bus uses that address)
So far I do not see many option other than using _DSD to pass
these RC config base addresses.

Thanks and Regards

Gab
[...]

and

https://patchwork.kernel.org/patch/9178791/
[...]
Furthermore, I suspect we do not even need a way to pass the
non-ECAM compliant config space resources to the OS (ie we can't
change FW anymore anyway in some platforms) so the quirks hooks
are likely to hardcode the required config space addresses for
the respective MCFG match.

..
Thanks !
Lorenzo
[...]

So we hard code with our RC itself config resource.

Thanks
Dongdong


Thanks,
Rafael


.

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

在 2016/8/31 19:48, Arnd Bergmann 写道:

On Wednesday, August 31, 2016 7:48:14 PM CEST Dongdong Liu wrote:

+static struct hisi_rc_res rc_res[] = {
+   {
+   HIP05,
+   {
+   DEFINE_RES_MEM(0xb007, SZ_4K),
+   DEFINE_RES_MEM(0xb008, SZ_4K),
+   DEFINE_RES_MEM(0xb009, SZ_4K),
+   DEFINE_RES_MEM(0xb00a, SZ_4K)
+   }
+   },
+   {
+   HIP06,
+   {
+   DEFINE_RES_MEM(0xa009, SZ_4K),
+   DEFINE_RES_MEM(0xa020, SZ_4K),
+   DEFINE_RES_MEM(0xa00a, SZ_4K),
+   DEFINE_RES_MEM(0xa00b, SZ_4K)
+   }
+   },
+   {
+   HIP07,
+   {
+   DEFINE_RES_MEM(0xa009, SZ_4K),
+   DEFINE_RES_MEM(0xa020, SZ_4K),
+   DEFINE_RES_MEM(0xa00a, SZ_4K),
+   DEFINE_RES_MEM(0xa00b, SZ_4K),
+   DEFINE_RES_MEM(0x8a009UL, SZ_4K),
+   DEFINE_RES_MEM(0x8a020UL, SZ_4K),
+   DEFINE_RES_MEM(0x8a00aUL, SZ_4K),
+   DEFINE_RES_MEM(0x8a00bUL, SZ_4K),
+   DEFINE_RES_MEM(0x600a009UL, SZ_4K),
+   DEFINE_RES_MEM(0x600a020UL, SZ_4K),
+   DEFINE_RES_MEM(0x600a00aUL, SZ_4K),
+   DEFINE_RES_MEM(0x600a00bUL, SZ_4K),
+   DEFINE_RES_MEM(0x700a009UL, SZ_4K),
+   DEFINE_RES_MEM(0x700a020UL, SZ_4K),
+   DEFINE_RES_MEM(0x700a00aUL, SZ_4K),
+   DEFINE_RES_MEM(0x700a00bUL, SZ_4K)
+   }
+   },


I don't know much about ACPI, but I'm pretty sure this is not
the normal way to find MMIO resources. Why not read them from
the ACPI tables?



Hi Arnd

Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

We have not found a comfortable ACPI way to describle RC itself config (not 
ECAM) resource .


Thanks
Dongdong


Arnd

.

Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

在 2016/8/31 19:48, Arnd Bergmann 写道:

On Wednesday, August 31, 2016 7:48:14 PM CEST Dongdong Liu wrote:

+static struct hisi_rc_res rc_res[] = {
+   {
+   HIP05,
+   {
+   DEFINE_RES_MEM(0xb007, SZ_4K),
+   DEFINE_RES_MEM(0xb008, SZ_4K),
+   DEFINE_RES_MEM(0xb009, SZ_4K),
+   DEFINE_RES_MEM(0xb00a, SZ_4K)
+   }
+   },
+   {
+   HIP06,
+   {
+   DEFINE_RES_MEM(0xa009, SZ_4K),
+   DEFINE_RES_MEM(0xa020, SZ_4K),
+   DEFINE_RES_MEM(0xa00a, SZ_4K),
+   DEFINE_RES_MEM(0xa00b, SZ_4K)
+   }
+   },
+   {
+   HIP07,
+   {
+   DEFINE_RES_MEM(0xa009, SZ_4K),
+   DEFINE_RES_MEM(0xa020, SZ_4K),
+   DEFINE_RES_MEM(0xa00a, SZ_4K),
+   DEFINE_RES_MEM(0xa00b, SZ_4K),
+   DEFINE_RES_MEM(0x8a009UL, SZ_4K),
+   DEFINE_RES_MEM(0x8a020UL, SZ_4K),
+   DEFINE_RES_MEM(0x8a00aUL, SZ_4K),
+   DEFINE_RES_MEM(0x8a00bUL, SZ_4K),
+   DEFINE_RES_MEM(0x600a009UL, SZ_4K),
+   DEFINE_RES_MEM(0x600a020UL, SZ_4K),
+   DEFINE_RES_MEM(0x600a00aUL, SZ_4K),
+   DEFINE_RES_MEM(0x600a00bUL, SZ_4K),
+   DEFINE_RES_MEM(0x700a009UL, SZ_4K),
+   DEFINE_RES_MEM(0x700a020UL, SZ_4K),
+   DEFINE_RES_MEM(0x700a00aUL, SZ_4K),
+   DEFINE_RES_MEM(0x700a00bUL, SZ_4K)
+   }
+   },


I don't know much about ACPI, but I'm pretty sure this is not
the normal way to find MMIO resources. Why not read them from
the ACPI tables?



Hi Arnd

Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

We have not found a comfortable ACPI way to describle RC itself config (not 
ECAM) resource .


Thanks
Dongdong


Arnd

.

Re: [RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

在 2016/8/31 19:45, Arnd Bergmann 写道:

On Wednesday, August 31, 2016 7:48:12 PM CEST Dongdong Liu wrote:

+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+   u32 reg;
+   u32 reg_val;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   reg_val = readl(reg_base + reg);
+
+   if (size == 1)
+   *val = *(u8 __force *) walker;
+   else if (size == 2)
+   *val = *(u16 __force *) walker;


What is the __force for?


Hi Arnd, thanks for replying.

__force is used to, well, force a conversion, like casting from or to a bitwise 
type, else the Sparse checker will throw a warning.




+   else if (size == 4)
+   *val = reg_val;
+   else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;


It looks like you are reimplementing 
pci_generic_config_read32/pci_generic_config_write32
read here, better use them directly.



For our host bridge, access RC and EP config space are not the same way.
Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

hisi_pcie_common_cfg_read is used to read RC config space, only supports 32-bit 
config access.
hisi_pcie_common_cfg_read/hisi_pcie_common_cfg_write may change as below will 
be better.

/* HipXX PCIe host only supports 32-bit config access */
int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
  u32 *val)
{
void __iomem *addr;

addr = reg_base + (where & ~0x3);
*val = readl(addr);

if (size <= 2)
*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);

return PCIBIOS_SUCCESSFUL;
}

/* HipXX PCIe host only supports 32-bit config access */
int hisi_pcie_common_cfg_write(void __iomem *reg_base, int where, int  size,
u32 val)
{
void __iomem *addr;
u32 mask, tmp;

addr = reg_base + (where & ~0x3);
if (size == 4) {
writel(val, addr);
return PCIBIOS_SUCCESSFUL;
} else {
mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
}

tmp = readl(addr) & mask;
tmp |= val << ((where & 0x3) * 8);
writel(tmp, addr);

return PCIBIOS_SUCCESSFUL;
}


Thanks
Dongdong


Arnd

.

Re: [RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

在 2016/8/31 19:45, Arnd Bergmann 写道:

On Wednesday, August 31, 2016 7:48:12 PM CEST Dongdong Liu wrote:

+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+   u32 reg;
+   u32 reg_val;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   reg_val = readl(reg_base + reg);
+
+   if (size == 1)
+   *val = *(u8 __force *) walker;
+   else if (size == 2)
+   *val = *(u16 __force *) walker;


What is the __force for?


Hi Arnd, thanks for replying.

__force is used to, well, force a conversion, like casting from or to a bitwise 
type, else the Sparse checker will throw a warning.




+   else if (size == 4)
+   *val = reg_val;
+   else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;


It looks like you are reimplementing 
pci_generic_config_read32/pci_generic_config_write32
read here, better use them directly.



For our host bridge, access RC and EP config space are not the same way.
Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.

hisi_pcie_common_cfg_read is used to read RC config space, only supports 32-bit 
config access.
hisi_pcie_common_cfg_read/hisi_pcie_common_cfg_write may change as below will 
be better.

/* HipXX PCIe host only supports 32-bit config access */
int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
  u32 *val)
{
void __iomem *addr;

addr = reg_base + (where & ~0x3);
*val = readl(addr);

if (size <= 2)
*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);

return PCIBIOS_SUCCESSFUL;
}

/* HipXX PCIe host only supports 32-bit config access */
int hisi_pcie_common_cfg_write(void __iomem *reg_base, int where, int  size,
u32 val)
{
void __iomem *addr;
u32 mask, tmp;

addr = reg_base + (where & ~0x3);
if (size == 4) {
writel(val, addr);
return PCIBIOS_SUCCESSFUL;
} else {
mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
}

tmp = readl(addr) & mask;
tmp |= val << ((where & 0x3) * 8);
writel(tmp, addr);

return PCIBIOS_SUCCESSFUL;
}


Thanks
Dongdong


Arnd

.

[RFC PATCH V2 2/3] PCI: hisi: Add ECAM support for devices that are not RC

[Dongdong Liu]

This patch modifies the current Hip05/Hip06 PCIe host
controller driver to add support for 'almost ECAM'
compliant platforms. Some controllers are ECAM compliant
for all the devices of the hierarchy except the root
complex; this patch adds support for such controllers.

This is needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.

Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 15 +---
 drivers/pci/host/pcie-designware.c |  3 +-
 drivers/pci/host/pcie-designware.h |  2 +
 drivers/pci/host/pcie-hisi.c   | 43 ++
 4 files changed, 56 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 59c2f47..87a597a 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -9,10 +9,13 @@ Additional properties are described here:
 
 Required properties
 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
-- reg: Should contain rc_dbi, config registers location and length.
-- reg-names: Must include the following entries:
+- reg: Should contain rc_dbi and  either config or ecam-cfg registers
+   location and length (it depends on the platform BIOS).
+- reg-names: Must include
   "rc_dbi": controller configuration registers;
-  "config": PCIe configuration space registers.
+  and one of the following entries:
+"config": PCIe configuration space registers for non-ECAM platforms.
+"ecam-cfg": PCIe configuration space registers for ECAM platforms
 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
 - port-id: Should be 0, 1, 2 or 3.
 
@@ -23,8 +26,10 @@ Optional properties:
 Hip05 Example (note that Hip06 is the same except compatible):
pcie@0xb008 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
-   reg = <0 0xb008 0 0x1>, <0x220 0x 0 0x2000>;
-   reg-names = "rc_dbi", "config";
+   reg = <0 0xb008 0 0x1>,
+ <0x220 0x 0 0x2000>
+   /* or <0x220 0x0010 0 0x0f0> for ecam-cfg*/;
+   reg-names = "rc_dbi", "config" /* or "ecam-cfg" */;
bus-range = <0  15>;
msi-parent = <_pcie>;
#address-cells = <3>;
diff --git a/drivers/pci/host/pcie-designware.c 
b/drivers/pci/host/pcie-designware.c
index 12afce1..9f5514c 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -75,7 +75,6 @@
 #define PCIE_PHY_DEBUG_R1  (PLR_OFFSET + 0x2c)
 #define PCIE_PHY_DEBUG_R1_LINK_UP  0x0010
 
-static struct pci_ops dw_pcie_ops;
 
 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
 {
@@ -710,7 +709,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 }
 
-static struct pci_ops dw_pcie_ops = {
+struct pci_ops dw_pcie_ops = {
.read = dw_pcie_rd_conf,
.write = dw_pcie_wr_conf,
 };
diff --git a/drivers/pci/host/pcie-designware.h 
b/drivers/pci/host/pcie-designware.h
index f437f9b..234f360 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -86,4 +86,6 @@ int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+extern struct pci_ops dw_pcie_ops;
+
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 23d74e9..81eeaed 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -43,6 +43,18 @@ struct pcie_soc_ops {
int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
 };
 
+static inline int hisi_rd_ecam_conf(struct pcie_port *pp, struct pci_bus *bus,
+   unsigned int devfn, int where, int size, u32 *value)
+{
+   return pci_generic_config_read(bus, devfn, where, size, value);
+}
+
+static inline int hisi_wr_ecam_conf(struct pcie_port *pp, struct pci_bus *bus,
+   unsigned int devfn, int where, int size, u32 value)
+{
+   return pci_generic_config_write(bus, devfn, where, size, value);
+}
+
 static inline int hisi_pcie_cfg_read(struct pcie_port *pp, int where,
int size, u32 *val)
 {
@@ -72,6 +84,20 @@ static struct pcie_host_ops hisi_pcie

[RFC PATCH V2 2/3] PCI: hisi: Add ECAM support for devices that are not RC

[Dongdong Liu]

This patch modifies the current Hip05/Hip06 PCIe host
controller driver to add support for 'almost ECAM'
compliant platforms. Some controllers are ECAM compliant
for all the devices of the hierarchy except the root
complex; this patch adds support for such controllers.

This is needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.

Signed-off-by: Gabriele Paoloni 
Signed-off-by: Dongdong Liu 
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 15 +---
 drivers/pci/host/pcie-designware.c |  3 +-
 drivers/pci/host/pcie-designware.h |  2 +
 drivers/pci/host/pcie-hisi.c   | 43 ++
 4 files changed, 56 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 59c2f47..87a597a 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -9,10 +9,13 @@ Additional properties are described here:
 
 Required properties
 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
-- reg: Should contain rc_dbi, config registers location and length.
-- reg-names: Must include the following entries:
+- reg: Should contain rc_dbi and  either config or ecam-cfg registers
+   location and length (it depends on the platform BIOS).
+- reg-names: Must include
   "rc_dbi": controller configuration registers;
-  "config": PCIe configuration space registers.
+  and one of the following entries:
+"config": PCIe configuration space registers for non-ECAM platforms.
+"ecam-cfg": PCIe configuration space registers for ECAM platforms
 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
 - port-id: Should be 0, 1, 2 or 3.
 
@@ -23,8 +26,10 @@ Optional properties:
 Hip05 Example (note that Hip06 is the same except compatible):
pcie@0xb008 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
-   reg = <0 0xb008 0 0x1>, <0x220 0x 0 0x2000>;
-   reg-names = "rc_dbi", "config";
+   reg = <0 0xb008 0 0x1>,
+ <0x220 0x 0 0x2000>
+   /* or <0x220 0x0010 0 0x0f0> for ecam-cfg*/;
+   reg-names = "rc_dbi", "config" /* or "ecam-cfg" */;
bus-range = <0  15>;
msi-parent = <_pcie>;
#address-cells = <3>;
diff --git a/drivers/pci/host/pcie-designware.c 
b/drivers/pci/host/pcie-designware.c
index 12afce1..9f5514c 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -75,7 +75,6 @@
 #define PCIE_PHY_DEBUG_R1  (PLR_OFFSET + 0x2c)
 #define PCIE_PHY_DEBUG_R1_LINK_UP  0x0010
 
-static struct pci_ops dw_pcie_ops;
 
 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
 {
@@ -710,7 +709,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 }
 
-static struct pci_ops dw_pcie_ops = {
+struct pci_ops dw_pcie_ops = {
.read = dw_pcie_rd_conf,
.write = dw_pcie_wr_conf,
 };
diff --git a/drivers/pci/host/pcie-designware.h 
b/drivers/pci/host/pcie-designware.h
index f437f9b..234f360 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -86,4 +86,6 @@ int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+extern struct pci_ops dw_pcie_ops;
+
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 23d74e9..81eeaed 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -43,6 +43,18 @@ struct pcie_soc_ops {
int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
 };
 
+static inline int hisi_rd_ecam_conf(struct pcie_port *pp, struct pci_bus *bus,
+   unsigned int devfn, int where, int size, u32 *value)
+{
+   return pci_generic_config_read(bus, devfn, where, size, value);
+}
+
+static inline int hisi_wr_ecam_conf(struct pcie_port *pp, struct pci_bus *bus,
+   unsigned int devfn, int where, int size, u32 value)
+{
+   return pci_generic_config_write(bus, devfn, where, size, value);
+}
+
 static inline int hisi_pcie_cfg_read(struct pcie_port *pp, int where,
int size, u32 *val)
 {
@@ -72,6 +84,20 @@ static struct pcie_host_ops hisi_pcie_host_ops = {
.link_up = hisi_pcie_link_up,
 };
 
+static voi

[RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

re-architect the Hip05/Hip06 host controllers driver to prepare
for the ACPI based driver.
The common functions used also by the ACPI driver have been grouped
into a new "common" file.

Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
---
 MAINTAINERS |   2 +
 drivers/pci/host/Makefile   |   2 +-
 drivers/pci/host/pcie-hisi-common.c |  66 ++
 drivers/pci/host/pcie-hisi.c| 110 ++--
 drivers/pci/host/pcie-hisi.h|  23 
 5 files changed, 123 insertions(+), 80 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-common.c
 create mode 100644 drivers/pci/host/pcie-hisi.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 20bb1d0..cdc1bba 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9081,7 +9081,9 @@ M:Gabriele Paoloni <gabriele.paol...@huawei.com>
 L: linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+F: drivers/pci/host/pcie-hisi.h
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-common.c
 
 PCIE DRIVER FOR QUALCOMM MSM
 M: Stanimir Varbanov <svarba...@mm-sol.com>
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 500cf78..02b498d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
-obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-common.c 
b/drivers/pci/host/pcie-hisi-common.c
new file mode 100644
index 000..5a5f269
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-common.c
@@ -0,0 +1,66 @@
+/*
+ * PCIe host controller common functions for HiSilicon SoCs
+ *
+ * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Zhou Wang <wangzh...@hisilicon.com>
+ * Dacai Zhu <zhuda...@hisilicon.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include "pcie-hisi.h"
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+   u32 reg;
+   u32 reg_val;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   reg_val = readl(reg_base + reg);
+
+   if (size == 1)
+   *val = *(u8 __force *) walker;
+   else if (size == 2)
+   *val = *(u16 __force *) walker;
+   else if (size == 4)
+   *val = reg_val;
+   else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;
+}
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_write(void __iomem *reg_base, int where, int  size,
+   u32 val)
+{
+   u32 reg_val;
+   u32 reg;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   if (size == 4)
+   writel(val, reg_base + reg);
+   else if (size == 2) {
+   reg_val = readl(reg_base + reg);
+   *(u16 __force *) walker = val;
+   writel(reg_val, reg_base + reg);
+   } else if (size == 1) {
+   reg_val = readl(reg_base + reg);
+   *(u8 __force *) walker = val;
+   writel(reg_val, reg_base + reg);
+   } else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;
+}
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 7ee9dfc..23d74e9 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -21,6 +21,7 @@
 #include 
 
 #include "pcie-designware.h"
+#include "pcie-hisi.h"
 
 #define PCIE_LTSSM_LINKUP_STATE0x11
 #define PCIE_LTSSM_STATE_MASK  0x3F
@@ -30,12 +31,6 @@
 
 #define to_hisi_pcie(x)container_of(x, struct hisi_pcie, pp)
 
-struct hisi_pcie;
-
-struct pcie_soc_ops {
-   int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
-};
-
 struct hisi_pcie {
struct regmap *subctrl;
void __iomem *reg_base;
@@ -44,87 +39,24 @@ struct hisi_pcie {
struct pcie_soc_ops *soc_ops;
 };
 
-static in

[RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/mcfg-quirks.c|   8 ++
 drivers/pci/host/mcfg-quirks.h|  11 +++
 drivers/pci/host/pcie-hisi-acpi.c | 189 ++
 drivers/pci/host/pcie-hisi.c  |   2 -
 drivers/pci/host/pcie-hisi.h  |   2 +
 7 files changed, 219 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 9b485d8..f940050 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI
+   bool "HiSilicon Hip05 and Hip06 SoCs ACPI PCIe controllers"
+   select ACPI_PCI_HOST_GENERIC
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 02b498d..bf6bbad 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o pcie-hisi-common.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/mcfg-quirks.c b/drivers/pci/host/mcfg-quirks.c
index 2993a72..772a453 100644
--- a/drivers/pci/host/mcfg-quirks.c
+++ b/drivers/pci/host/mcfg-quirks.c
@@ -51,6 +51,14 @@ static struct pci_cfg_fixup mcfg_quirks[] __initconst = {
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(14, 19), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
 #endif
+#ifdef CONFIG_PCI_HISI_ACPI
+   { "HISI  ", "HIP05   ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip05_init},
+   { "HISI  ", "HIP06   ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip06_init},
+   { "HISI  ", "HIP07   ", 0, MCFG_DOM_RANGE(0, 15), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip07_init},
+#endif
 };
 
 static bool pci_mcfg_fixup_match(struct pci_cfg_fixup *f,
diff --git a/drivers/pci/host/mcfg-quirks.h b/drivers/pci/host/mcfg-quirks.h
index 411c667..e496ddd 100644
--- a/drivers/pci/host/mcfg-quirks.h
+++ b/drivers/pci/host/mcfg-quirks.h
@@ -21,4 +21,15 @@ struct pci_config_window *
 thunder_pem_cfg_init(struct acpi_pci_root *root, struct pci_ops *ops);
 #endif
 
+#ifdef CONFIG_PCI_HISI_ACPI
+struct pci_config_window *
+hisi_pcie_acpi_hip05_init(struct acpi_pci_root *root, struct pci_ops *ops);
+
+struct pci_config_window *
+hisi_pcie_acpi_hip06_init(struct acpi_pci_root *root, struct pci_ops *ops);
+
+struct pci_config_window *
+hisi_pcie_acpi_hip07_init(struct acpi_pci_root *root, struct pci_ops *ops);
+#endif
+
 #endif /* __MCFG_QUIRKS_H__ */
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..68cf297
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,189 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#include "mcfg-quirks.h"
+#include "pcie-hisi.h"
+
+#define DEBUG0  0x728
+#define MAX_RC_NUM 16
+
+enum soc_type {
+   HIP05,
+   HIP06,
+   HIP07,
+};
+
+struct hisi_rc_res {
+   int soc_type;
+   struct resource res[MAX_RC_NUM];
+};
+
+static int hisi_pcie_link_up_acpi(struct pci_config_window *cfg)
+{
+   u32 val;
+   void __iomem *reg_base = cfg->priv;
+
+   val = readl(reg_base + DEBUG0);
+   return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+
+}
+
+static int hi

[RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

re-architect the Hip05/Hip06 host controllers driver to prepare
for the ACPI based driver.
The common functions used also by the ACPI driver have been grouped
into a new "common" file.

Signed-off-by: Gabriele Paoloni 
Signed-off-by: Dongdong Liu 
---
 MAINTAINERS |   2 +
 drivers/pci/host/Makefile   |   2 +-
 drivers/pci/host/pcie-hisi-common.c |  66 ++
 drivers/pci/host/pcie-hisi.c| 110 ++--
 drivers/pci/host/pcie-hisi.h|  23 
 5 files changed, 123 insertions(+), 80 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-common.c
 create mode 100644 drivers/pci/host/pcie-hisi.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 20bb1d0..cdc1bba 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9081,7 +9081,9 @@ M:Gabriele Paoloni 
 L: linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+F: drivers/pci/host/pcie-hisi.h
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-common.c
 
 PCIE DRIVER FOR QUALCOMM MSM
 M: Stanimir Varbanov 
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 500cf78..02b498d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
-obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-common.c 
b/drivers/pci/host/pcie-hisi-common.c
new file mode 100644
index 000..5a5f269
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-common.c
@@ -0,0 +1,66 @@
+/*
+ * PCIe host controller common functions for HiSilicon SoCs
+ *
+ * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Zhou Wang 
+ * Dacai Zhu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include "pcie-hisi.h"
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+   u32 reg;
+   u32 reg_val;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   reg_val = readl(reg_base + reg);
+
+   if (size == 1)
+   *val = *(u8 __force *) walker;
+   else if (size == 2)
+   *val = *(u16 __force *) walker;
+   else if (size == 4)
+   *val = reg_val;
+   else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;
+}
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_write(void __iomem *reg_base, int where, int  size,
+   u32 val)
+{
+   u32 reg_val;
+   u32 reg;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   if (size == 4)
+   writel(val, reg_base + reg);
+   else if (size == 2) {
+   reg_val = readl(reg_base + reg);
+   *(u16 __force *) walker = val;
+   writel(reg_val, reg_base + reg);
+   } else if (size == 1) {
+   reg_val = readl(reg_base + reg);
+   *(u8 __force *) walker = val;
+   writel(reg_val, reg_base + reg);
+   } else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;
+}
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 7ee9dfc..23d74e9 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -21,6 +21,7 @@
 #include 
 
 #include "pcie-designware.h"
+#include "pcie-hisi.h"
 
 #define PCIE_LTSSM_LINKUP_STATE0x11
 #define PCIE_LTSSM_STATE_MASK  0x3F
@@ -30,12 +31,6 @@
 
 #define to_hisi_pcie(x)container_of(x, struct hisi_pcie, pp)
 
-struct hisi_pcie;
-
-struct pcie_soc_ops {
-   int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
-};
-
 struct hisi_pcie {
struct regmap *subctrl;
void __iomem *reg_base;
@@ -44,87 +39,24 @@ struct hisi_pcie {
struct pcie_soc_ops *soc_ops;
 };
 
-static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
-   u32 val, u32 reg)
-{
-   writel(val, pcie->reg_base + reg);
-}
-
-static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *

[RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 drivers/pci/host/Kconfig  |   8 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/mcfg-quirks.c|   8 ++
 drivers/pci/host/mcfg-quirks.h|  11 +++
 drivers/pci/host/pcie-hisi-acpi.c | 189 ++
 drivers/pci/host/pcie-hisi.c  |   2 -
 drivers/pci/host/pcie-hisi.h  |   2 +
 7 files changed, 219 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 9b485d8..f940050 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -227,6 +227,14 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI
+   bool "HiSilicon Hip05 and Hip06 SoCs ACPI PCIe controllers"
+   select ACPI_PCI_HOST_GENERIC
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 02b498d..bf6bbad 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o pcie-hisi-common.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/mcfg-quirks.c b/drivers/pci/host/mcfg-quirks.c
index 2993a72..772a453 100644
--- a/drivers/pci/host/mcfg-quirks.c
+++ b/drivers/pci/host/mcfg-quirks.c
@@ -51,6 +51,14 @@ static struct pci_cfg_fixup mcfg_quirks[] __initconst = {
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(14, 19), MCFG_BUS_ANY, NULL,
  thunder_pem_cfg_init },
 #endif
+#ifdef CONFIG_PCI_HISI_ACPI
+   { "HISI  ", "HIP05   ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip05_init},
+   { "HISI  ", "HIP06   ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip06_init},
+   { "HISI  ", "HIP07   ", 0, MCFG_DOM_RANGE(0, 15), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip07_init},
+#endif
 };
 
 static bool pci_mcfg_fixup_match(struct pci_cfg_fixup *f,
diff --git a/drivers/pci/host/mcfg-quirks.h b/drivers/pci/host/mcfg-quirks.h
index 411c667..e496ddd 100644
--- a/drivers/pci/host/mcfg-quirks.h
+++ b/drivers/pci/host/mcfg-quirks.h
@@ -21,4 +21,15 @@ struct pci_config_window *
 thunder_pem_cfg_init(struct acpi_pci_root *root, struct pci_ops *ops);
 #endif
 
+#ifdef CONFIG_PCI_HISI_ACPI
+struct pci_config_window *
+hisi_pcie_acpi_hip05_init(struct acpi_pci_root *root, struct pci_ops *ops);
+
+struct pci_config_window *
+hisi_pcie_acpi_hip06_init(struct acpi_pci_root *root, struct pci_ops *ops);
+
+struct pci_config_window *
+hisi_pcie_acpi_hip07_init(struct acpi_pci_root *root, struct pci_ops *ops);
+#endif
+
 #endif /* __MCFG_QUIRKS_H__ */
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..68cf297
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,189 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#include "mcfg-quirks.h"
+#include "pcie-hisi.h"
+
+#define DEBUG0  0x728
+#define MAX_RC_NUM 16
+
+enum soc_type {
+   HIP05,
+   HIP06,
+   HIP07,
+};
+
+struct hisi_rc_res {
+   int soc_type;
+   struct resource res[MAX_RC_NUM];
+};
+
+static int hisi_pcie_link_up_acpi(struct pci_config_window *cfg)
+{
+   u32 val;
+   void __iomem *reg_base = cfg->priv;
+
+   val = readl(reg_base + DEBUG0);
+   return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+
+}
+
+static int hisi_pcie_acpi_valid_config(struct pci_config_window *cfg,
+  struct pci_bus *bus, int dev)
+{
+   /* If the

[RFC PATCH V2 0/3] Add ACPI support for Hisilicon PCIe Host Controller

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC PCIe
controllers.
The three patches respectively:
- re-architect the current HiSilicon driver to make it scalable to
  the new ACPI quirks.
- rework the current HiSilicon driver to add support for ECAM
  platforms(not RC).
- adds the HiSilicon ACPI specific quirks.

This patchset is base on Tomasz RFC V5 quirk mechanism:
https://lkml.org/lkml/2016/8/8/273

v1 -> v2
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers 

Dongdong Liu (3):
  PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for
ACPI
  PCI: hisi: Add ECAM support for devices that are not RC
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 .../devicetree/bindings/pci/hisilicon-pcie.txt |  15 +-
 MAINTAINERS|   2 +
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   3 +-
 drivers/pci/host/mcfg-quirks.c |   8 +
 drivers/pci/host/mcfg-quirks.h |  11 ++
 drivers/pci/host/pcie-designware.c |   3 +-
 drivers/pci/host/pcie-designware.h |   2 +
 drivers/pci/host/pcie-hisi-acpi.c  | 189 +
 drivers/pci/host/pcie-hisi-common.c|  66 +++
 drivers/pci/host/pcie-hisi.c   | 143 
 drivers/pci/host/pcie-hisi.h   |  25 +++
 12 files changed, 392 insertions(+), 83 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c
 create mode 100644 drivers/pci/host/pcie-hisi-common.c
 create mode 100644 drivers/pci/host/pcie-hisi.h

-- 
1.9.1

[RFC PATCH V2 0/3] Add ACPI support for Hisilicon PCIe Host Controller

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06/Hip07 SoC PCIe
controllers.
The three patches respectively:
- re-architect the current HiSilicon driver to make it scalable to
  the new ACPI quirks.
- rework the current HiSilicon driver to add support for ECAM
  platforms(not RC).
- adds the HiSilicon ACPI specific quirks.

This patchset is base on Tomasz RFC V5 quirk mechanism:
https://lkml.org/lkml/2016/8/8/273

v1 -> v2
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers 

Dongdong Liu (3):
  PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for
ACPI
  PCI: hisi: Add ECAM support for devices that are not RC
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 .../devicetree/bindings/pci/hisilicon-pcie.txt |  15 +-
 MAINTAINERS|   2 +
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   3 +-
 drivers/pci/host/mcfg-quirks.c |   8 +
 drivers/pci/host/mcfg-quirks.h |  11 ++
 drivers/pci/host/pcie-designware.c |   3 +-
 drivers/pci/host/pcie-designware.h |   2 +
 drivers/pci/host/pcie-hisi-acpi.c  | 189 +
 drivers/pci/host/pcie-hisi-common.c|  66 +++
 drivers/pci/host/pcie-hisi.c   | 143 
 drivers/pci/host/pcie-hisi.h   |  25 +++
 12 files changed, 392 insertions(+), 83 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c
 create mode 100644 drivers/pci/host/pcie-hisi-common.c
 create mode 100644 drivers/pci/host/pcie-hisi.h

-- 
1.9.1

Re: [RFC PATCH V5 0/5] ECAM quirks handling for ARM64 platforms

[Dongdong Liu]

在 2016/8/8 21:05, Tomasz Nowicki 写道:

Quirk handling relies on an idea of matching MCFG OEM ID, TABLE ID and
revision (the ones from standard header of MCFG table).

Static array is used to keep quirk entries. Each entry consists of
mentioned MCFG IDs along with custom pci_ops structure and initialization call.

As an example, the last patch presents quirk handling mechanism usage for
ThunderX PEM driver.

v4 -> v5
- rebase against v4.8-rc1
- rework to exact MCFG OEM ID, TABLE ID, rev match
   - use memcmp instead of strncmp
   - no substring match
- fix typos and dmesg message

Tomasz Nowicki (5):
   PCI: Embed pci_ecam_ops in pci_config_window structure
   PCI/ACPI: Move ACPI ECAM mapping to generic MCFG driver
   PCI: Check platform specific ECAM quirks
   ARM64/PCI: Start using quirks handling for ACPI based PCI host
 controller
   PCI: thunder-pem: Support quirky configuration space access for ACPI
 based PCI host controller

  arch/arm64/kernel/pci.c| 42 +
  drivers/acpi/pci_mcfg.c| 40 
  drivers/pci/ecam.c |  6 +--
  drivers/pci/host/Makefile  |  1 +
  drivers/pci/host/mcfg-quirks.c | 93 
  drivers/pci/host/mcfg-quirks.h | 24 ++
  drivers/pci/host/pci-thunder-pem.c | 96 --
  include/linux/pci-acpi.h   |  5 ++
  include/linux/pci-ecam.h   |  2 +-
  9 files changed, 252 insertions(+), 57 deletions(-)
  create mode 100644 drivers/pci/host/mcfg-quirks.c
  create mode 100644 drivers/pci/host/mcfg-quirks.h



Based on the patchset, tested on HiSilicon D03 board with intel 82599 net card. 
It worked OK.

Tested-by: Dongdong Liu <liudongdo...@huawei.com>

Thanks
Dongdong

Re: [RFC PATCH V5 0/5] ECAM quirks handling for ARM64 platforms

[Dongdong Liu]

在 2016/8/8 21:05, Tomasz Nowicki 写道:

Quirk handling relies on an idea of matching MCFG OEM ID, TABLE ID and
revision (the ones from standard header of MCFG table).

Static array is used to keep quirk entries. Each entry consists of
mentioned MCFG IDs along with custom pci_ops structure and initialization call.

As an example, the last patch presents quirk handling mechanism usage for
ThunderX PEM driver.

v4 -> v5
- rebase against v4.8-rc1
- rework to exact MCFG OEM ID, TABLE ID, rev match
   - use memcmp instead of strncmp
   - no substring match
- fix typos and dmesg message

Tomasz Nowicki (5):
   PCI: Embed pci_ecam_ops in pci_config_window structure
   PCI/ACPI: Move ACPI ECAM mapping to generic MCFG driver
   PCI: Check platform specific ECAM quirks
   ARM64/PCI: Start using quirks handling for ACPI based PCI host
 controller
   PCI: thunder-pem: Support quirky configuration space access for ACPI
 based PCI host controller

  arch/arm64/kernel/pci.c| 42 +
  drivers/acpi/pci_mcfg.c| 40 
  drivers/pci/ecam.c |  6 +--
  drivers/pci/host/Makefile  |  1 +
  drivers/pci/host/mcfg-quirks.c | 93 
  drivers/pci/host/mcfg-quirks.h | 24 ++
  drivers/pci/host/pci-thunder-pem.c | 96 --
  include/linux/pci-acpi.h   |  5 ++
  include/linux/pci-ecam.h   |  2 +-
  9 files changed, 252 insertions(+), 57 deletions(-)
  create mode 100644 drivers/pci/host/mcfg-quirks.c
  create mode 100644 drivers/pci/host/mcfg-quirks.h



Based on the patchset, tested on HiSilicon D03 board with intel 82599 net card. 
It worked OK.

Tested-by: Dongdong Liu 

Thanks
Dongdong

[RFC PATCH 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

re-architect the Hip05/Hip06 host controllers driver to prepare
for the ACPI based driver.
The common functions used also by the ACPI driver have been grouped
into a new "common" file.

Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
---
 MAINTAINERS |   2 +
 drivers/pci/host/Makefile   |   2 +-
 drivers/pci/host/pcie-hisi-common.c |  66 ++
 drivers/pci/host/pcie-hisi.c| 110 ++--
 drivers/pci/host/pcie-hisi.h|  23 
 5 files changed, 123 insertions(+), 80 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-common.c
 create mode 100644 drivers/pci/host/pcie-hisi.h

diff --git a/MAINTAINERS b/MAINTAINERS
index ed42cb6..7e8e2c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8829,7 +8829,9 @@ M:Gabriele Paoloni <gabriele.paol...@huawei.com>
 L: linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+F: drivers/pci/host/pcie-hisi.h
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-common.c
 
 PCIE DRIVER FOR QUALCOMM MSM
 M: Stanimir Varbanov <svarba...@mm-sol.com>
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 5fadfd9..05950f3 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
-obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-common.c 
b/drivers/pci/host/pcie-hisi-common.c
new file mode 100644
index 000..5a5f269
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-common.c
@@ -0,0 +1,66 @@
+/*
+ * PCIe host controller common functions for HiSilicon SoCs
+ *
+ * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Zhou Wang <wangzh...@hisilicon.com>
+ * Dacai Zhu <zhuda...@hisilicon.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include "pcie-hisi.h"
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+   u32 reg;
+   u32 reg_val;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   reg_val = readl(reg_base + reg);
+
+   if (size == 1)
+   *val = *(u8 __force *) walker;
+   else if (size == 2)
+   *val = *(u16 __force *) walker;
+   else if (size == 4)
+   *val = reg_val;
+   else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;
+}
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_write(void __iomem *reg_base, int where, int  size,
+   u32 val)
+{
+   u32 reg_val;
+   u32 reg;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   if (size == 4)
+   writel(val, reg_base + reg);
+   else if (size == 2) {
+   reg_val = readl(reg_base + reg);
+   *(u16 __force *) walker = val;
+   writel(reg_val, reg_base + reg);
+   } else if (size == 1) {
+   reg_val = readl(reg_base + reg);
+   *(u8 __force *) walker = val;
+   writel(reg_val, reg_base + reg);
+   } else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;
+}
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 3e98d4e..086af15 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -21,6 +21,7 @@
 #include 
 
 #include "pcie-designware.h"
+#include "pcie-hisi.h"
 
 #define PCIE_LTSSM_LINKUP_STATE0x11
 #define PCIE_LTSSM_STATE_MASK  0x3F
@@ -30,12 +31,6 @@
 
 #define to_hisi_pcie(x)container_of(x, struct hisi_pcie, pp)
 
-struct hisi_pcie;
-
-struct pcie_soc_ops {
-   int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
-};
-
 struct hisi_pcie {
struct regmap *subctrl;
void __iomem *reg_base;
@@ -44,87 +39,24 @@ struct hisi_pcie {
struct pcie_soc_ops *soc_ops;
 };
 
-static in

[RFC PATCH 2/3] PCI: hisi: Add ECAM support for devices that are not RC

[Dongdong Liu]

This patch modifies the current Hip05/Hip06 PCIe host
controller driver to add support for 'almost ECAM'
compliant platforms. Some controllers are ECAM compliant
for all the devices of the hierarchy except the root
complex; this patch adds support for such controllers.

This is needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.

Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 15 +---
 drivers/pci/host/pcie-designware.c |  3 +-
 drivers/pci/host/pcie-designware.h |  2 +
 drivers/pci/host/pcie-hisi.c   | 43 ++
 4 files changed, 56 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 59c2f47..87a597a 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -9,10 +9,13 @@ Additional properties are described here:
 
 Required properties
 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
-- reg: Should contain rc_dbi, config registers location and length.
-- reg-names: Must include the following entries:
+- reg: Should contain rc_dbi and  either config or ecam-cfg registers
+   location and length (it depends on the platform BIOS).
+- reg-names: Must include
   "rc_dbi": controller configuration registers;
-  "config": PCIe configuration space registers.
+  and one of the following entries:
+"config": PCIe configuration space registers for non-ECAM platforms.
+"ecam-cfg": PCIe configuration space registers for ECAM platforms
 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
 - port-id: Should be 0, 1, 2 or 3.
 
@@ -23,8 +26,10 @@ Optional properties:
 Hip05 Example (note that Hip06 is the same except compatible):
pcie@0xb008 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
-   reg = <0 0xb008 0 0x1>, <0x220 0x 0 0x2000>;
-   reg-names = "rc_dbi", "config";
+   reg = <0 0xb008 0 0x1>,
+ <0x220 0x 0 0x2000>
+   /* or <0x220 0x0010 0 0x0f0> for ecam-cfg*/;
+   reg-names = "rc_dbi", "config" /* or "ecam-cfg" */;
bus-range = <0  15>;
msi-parent = <_pcie>;
#address-cells = <3>;
diff --git a/drivers/pci/host/pcie-designware.c 
b/drivers/pci/host/pcie-designware.c
index aafd766..239eb39 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -75,7 +75,6 @@
 #define PCIE_PHY_DEBUG_R1  (PLR_OFFSET + 0x2c)
 #define PCIE_PHY_DEBUG_R1_LINK_UP  0x0010
 
-static struct pci_ops dw_pcie_ops;
 
 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
 {
@@ -700,7 +699,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 }
 
-static struct pci_ops dw_pcie_ops = {
+struct pci_ops dw_pcie_ops = {
.read = dw_pcie_rd_conf,
.write = dw_pcie_wr_conf,
 };
diff --git a/drivers/pci/host/pcie-designware.h 
b/drivers/pci/host/pcie-designware.h
index f437f9b..234f360 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -86,4 +86,6 @@ int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+extern struct pci_ops dw_pcie_ops;
+
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 086af15..c42ef84 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -43,6 +43,18 @@ struct pcie_soc_ops {
int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
 };
 
+static inline int hisi_rd_ecam_conf(struct pcie_port *pp, struct pci_bus *bus,
+   unsigned int devfn, int where, int size, u32 *value)
+{
+   return pci_generic_config_read(bus, devfn, where, size, value);
+}
+
+static inline int hisi_wr_ecam_conf(struct pcie_port *pp, struct pci_bus *bus,
+   unsigned int devfn, int where, int size, u32 value)
+{
+   return pci_generic_config_write(bus, devfn, where, size, value);
+}
+
 static inline int hisi_pcie_cfg_read(struct pcie_port *pp, int where,
int size, u32 *val)
 {
@@ -72,6 +84,20 @@ static struct pcie_host_ops hisi_pcie

[RFC PATCH 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
 MAINTAINERS   |   1 +
 drivers/pci/host/Kconfig  |   7 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/mcfg-quirks.c|   8 ++
 drivers/pci/host/mcfg-quirks.h|   8 ++
 drivers/pci/host/pcie-hisi-acpi.c | 151 ++
 drivers/pci/host/pcie-hisi.c  |   2 -
 drivers/pci/host/pcie-hisi.h  |   2 +
 8 files changed, 178 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 7e8e2c9..c51c736 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8832,6 +8832,7 @@ F:
Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.h
 F: drivers/pci/host/pcie-hisi.c
 F: drivers/pci/host/pcie-hisi-common.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR QUALCOMM MSM
 M: Stanimir Varbanov <svarba...@mm-sol.com>
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 5d2374e..15b73a6 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -210,6 +210,13 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 SoCs ACPI PCIe controllers"
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 05950f3..4843142 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o pcie-hisi-common.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/mcfg-quirks.c b/drivers/pci/host/mcfg-quirks.c
index a4bb76a..e65cd99 100644
--- a/drivers/pci/host/mcfg-quirks.c
+++ b/drivers/pci/host/mcfg-quirks.c
@@ -51,6 +51,14 @@ static struct pci_cfg_fixup mcfg_qurks[] __initconst = {
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(14, 19), MCFG_BUS_ANY,
  NULL, thunder_pem_cfg_init},
 #endif
+#ifdef CONFIG_PCI_HISI_ACPI
+   { "HISI", "HISI0660", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip05_init},
+   { "HISI", "HISI1610", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip06_init},
+   { "HISI", "HISI1612", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip06_init},
+#endif
 };
 
 static bool pci_mcfg_fixup_match(struct pci_cfg_fixup *f,
diff --git a/drivers/pci/host/mcfg-quirks.h b/drivers/pci/host/mcfg-quirks.h
index 411c667..a2d2aaa 100644
--- a/drivers/pci/host/mcfg-quirks.h
+++ b/drivers/pci/host/mcfg-quirks.h
@@ -21,4 +21,12 @@ struct pci_config_window *
 thunder_pem_cfg_init(struct acpi_pci_root *root, struct pci_ops *ops);
 #endif
 
+#ifdef CONFIG_PCI_HISI_ACPI
+struct pci_config_window *
+hisi_pcie_acpi_hip05_init(struct acpi_pci_root *root, struct pci_ops *ops);
+
+struct pci_config_window *
+hisi_pcie_acpi_hip06_init(struct acpi_pci_root *root, struct pci_ops *ops);
+#endif
+
 #endif /* __MCFG_QUIRKS_H__ */
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..93572d0
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,151 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdo...@huawei.com>
+ * Gabriele Paoloni <gabriele.paol...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#include "mcfg-quirks.h"
+#include "pcie-hisi.h"
+
+#define DEBUG0  0x728
+#define RC_NUM  4
+
+enum soc_type {
+   HIP05,
+   HIP06,
+};
+
+struct hisi_rc_res {
+   int soc_type;
+

[RFC PATCH 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI

[Dongdong Liu]

re-architect the Hip05/Hip06 host controllers driver to prepare
for the ACPI based driver.
The common functions used also by the ACPI driver have been grouped
into a new "common" file.

Signed-off-by: Gabriele Paoloni 
Signed-off-by: Dongdong Liu 
---
 MAINTAINERS |   2 +
 drivers/pci/host/Makefile   |   2 +-
 drivers/pci/host/pcie-hisi-common.c |  66 ++
 drivers/pci/host/pcie-hisi.c| 110 ++--
 drivers/pci/host/pcie-hisi.h|  23 
 5 files changed, 123 insertions(+), 80 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-common.c
 create mode 100644 drivers/pci/host/pcie-hisi.h

diff --git a/MAINTAINERS b/MAINTAINERS
index ed42cb6..7e8e2c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8829,7 +8829,9 @@ M:Gabriele Paoloni 
 L: linux-...@vger.kernel.org
 S: Maintained
 F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+F: drivers/pci/host/pcie-hisi.h
 F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-common.c
 
 PCIE DRIVER FOR QUALCOMM MSM
 M: Stanimir Varbanov 
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 5fadfd9..05950f3 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
-obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/pcie-hisi-common.c 
b/drivers/pci/host/pcie-hisi-common.c
new file mode 100644
index 000..5a5f269
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-common.c
@@ -0,0 +1,66 @@
+/*
+ * PCIe host controller common functions for HiSilicon SoCs
+ *
+ * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Zhou Wang 
+ * Dacai Zhu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include "pcie-hisi.h"
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+   u32 reg;
+   u32 reg_val;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   reg_val = readl(reg_base + reg);
+
+   if (size == 1)
+   *val = *(u8 __force *) walker;
+   else if (size == 2)
+   *val = *(u16 __force *) walker;
+   else if (size == 4)
+   *val = reg_val;
+   else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;
+}
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_write(void __iomem *reg_base, int where, int  size,
+   u32 val)
+{
+   u32 reg_val;
+   u32 reg;
+   void *walker = _val;
+
+   walker += (where & 0x3);
+   reg = where & ~0x3;
+   if (size == 4)
+   writel(val, reg_base + reg);
+   else if (size == 2) {
+   reg_val = readl(reg_base + reg);
+   *(u16 __force *) walker = val;
+   writel(reg_val, reg_base + reg);
+   } else if (size == 1) {
+   reg_val = readl(reg_base + reg);
+   *(u8 __force *) walker = val;
+   writel(reg_val, reg_base + reg);
+   } else
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   return PCIBIOS_SUCCESSFUL;
+}
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 3e98d4e..086af15 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -21,6 +21,7 @@
 #include 
 
 #include "pcie-designware.h"
+#include "pcie-hisi.h"
 
 #define PCIE_LTSSM_LINKUP_STATE0x11
 #define PCIE_LTSSM_STATE_MASK  0x3F
@@ -30,12 +31,6 @@
 
 #define to_hisi_pcie(x)container_of(x, struct hisi_pcie, pp)
 
-struct hisi_pcie;
-
-struct pcie_soc_ops {
-   int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
-};
-
 struct hisi_pcie {
struct regmap *subctrl;
void __iomem *reg_base;
@@ -44,87 +39,24 @@ struct hisi_pcie {
struct pcie_soc_ops *soc_ops;
 };
 
-static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
-   u32 val, u32 reg)
-{
-   writel(val, pcie->reg_base + reg);
-}
-
-static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *

[RFC PATCH 2/3] PCI: hisi: Add ECAM support for devices that are not RC

[Dongdong Liu]

This patch modifies the current Hip05/Hip06 PCIe host
controller driver to add support for 'almost ECAM'
compliant platforms. Some controllers are ECAM compliant
for all the devices of the hierarchy except the root
complex; this patch adds support for such controllers.

This is needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.

Signed-off-by: Gabriele Paoloni 
Signed-off-by: Dongdong Liu 
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 15 +---
 drivers/pci/host/pcie-designware.c |  3 +-
 drivers/pci/host/pcie-designware.h |  2 +
 drivers/pci/host/pcie-hisi.c   | 43 ++
 4 files changed, 56 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 59c2f47..87a597a 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -9,10 +9,13 @@ Additional properties are described here:
 
 Required properties
 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
-- reg: Should contain rc_dbi, config registers location and length.
-- reg-names: Must include the following entries:
+- reg: Should contain rc_dbi and  either config or ecam-cfg registers
+   location and length (it depends on the platform BIOS).
+- reg-names: Must include
   "rc_dbi": controller configuration registers;
-  "config": PCIe configuration space registers.
+  and one of the following entries:
+"config": PCIe configuration space registers for non-ECAM platforms.
+"ecam-cfg": PCIe configuration space registers for ECAM platforms
 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
 - port-id: Should be 0, 1, 2 or 3.
 
@@ -23,8 +26,10 @@ Optional properties:
 Hip05 Example (note that Hip06 is the same except compatible):
pcie@0xb008 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
-   reg = <0 0xb008 0 0x1>, <0x220 0x 0 0x2000>;
-   reg-names = "rc_dbi", "config";
+   reg = <0 0xb008 0 0x1>,
+ <0x220 0x 0 0x2000>
+   /* or <0x220 0x0010 0 0x0f0> for ecam-cfg*/;
+   reg-names = "rc_dbi", "config" /* or "ecam-cfg" */;
bus-range = <0  15>;
msi-parent = <_pcie>;
#address-cells = <3>;
diff --git a/drivers/pci/host/pcie-designware.c 
b/drivers/pci/host/pcie-designware.c
index aafd766..239eb39 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -75,7 +75,6 @@
 #define PCIE_PHY_DEBUG_R1  (PLR_OFFSET + 0x2c)
 #define PCIE_PHY_DEBUG_R1_LINK_UP  0x0010
 
-static struct pci_ops dw_pcie_ops;
 
 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
 {
@@ -700,7 +699,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 }
 
-static struct pci_ops dw_pcie_ops = {
+struct pci_ops dw_pcie_ops = {
.read = dw_pcie_rd_conf,
.write = dw_pcie_wr_conf,
 };
diff --git a/drivers/pci/host/pcie-designware.h 
b/drivers/pci/host/pcie-designware.h
index f437f9b..234f360 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -86,4 +86,6 @@ int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+extern struct pci_ops dw_pcie_ops;
+
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 086af15..c42ef84 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -43,6 +43,18 @@ struct pcie_soc_ops {
int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
 };
 
+static inline int hisi_rd_ecam_conf(struct pcie_port *pp, struct pci_bus *bus,
+   unsigned int devfn, int where, int size, u32 *value)
+{
+   return pci_generic_config_read(bus, devfn, where, size, value);
+}
+
+static inline int hisi_wr_ecam_conf(struct pcie_port *pp, struct pci_bus *bus,
+   unsigned int devfn, int where, int size, u32 value)
+{
+   return pci_generic_config_write(bus, devfn, where, size, value);
+}
+
 static inline int hisi_pcie_cfg_read(struct pcie_port *pp, int where,
int size, u32 *val)
 {
@@ -72,6 +84,20 @@ static struct pcie_host_ops hisi_pcie_host_ops = {
.link_up = hisi_pcie_link_up,
 };
 
+static voi

[RFC PATCH 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

[Dongdong Liu]

Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.

Signed-off-by: Dongdong Liu 
Signed-off-by: Gabriele Paoloni 
---
 MAINTAINERS   |   1 +
 drivers/pci/host/Kconfig  |   7 ++
 drivers/pci/host/Makefile |   1 +
 drivers/pci/host/mcfg-quirks.c|   8 ++
 drivers/pci/host/mcfg-quirks.h|   8 ++
 drivers/pci/host/pcie-hisi-acpi.c | 151 ++
 drivers/pci/host/pcie-hisi.c  |   2 -
 drivers/pci/host/pcie-hisi.h  |   2 +
 8 files changed, 178 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 7e8e2c9..c51c736 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8832,6 +8832,7 @@ F:
Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 F: drivers/pci/host/pcie-hisi.h
 F: drivers/pci/host/pcie-hisi.c
 F: drivers/pci/host/pcie-hisi-common.c
+F: drivers/pci/host/pcie-hisi-acpi.c
 
 PCIE DRIVER FOR QUALCOMM MSM
 M: Stanimir Varbanov 
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 5d2374e..15b73a6 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -210,6 +210,13 @@ config PCI_HISI
  Say Y here if you want PCIe controller support on HiSilicon
  Hip05 and Hip06 SoCs
 
+config PCI_HISI_ACPI
+   depends on ACPI && ARM64
+   bool "HiSilicon Hip05 and Hip06 SoCs ACPI PCIe controllers"
+   help
+ Say Y here if you want ACPI PCIe controller support on HiSilicon
+ Hip05 and Hip06 SoCs
+
 config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 05950f3..4843142 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o pcie-hisi-common.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
 obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
diff --git a/drivers/pci/host/mcfg-quirks.c b/drivers/pci/host/mcfg-quirks.c
index a4bb76a..e65cd99 100644
--- a/drivers/pci/host/mcfg-quirks.c
+++ b/drivers/pci/host/mcfg-quirks.c
@@ -51,6 +51,14 @@ static struct pci_cfg_fixup mcfg_qurks[] __initconst = {
{ "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(14, 19), MCFG_BUS_ANY,
  NULL, thunder_pem_cfg_init},
 #endif
+#ifdef CONFIG_PCI_HISI_ACPI
+   { "HISI", "HISI0660", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip05_init},
+   { "HISI", "HISI1610", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip06_init},
+   { "HISI", "HISI1612", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
+ NULL, hisi_pcie_acpi_hip06_init},
+#endif
 };
 
 static bool pci_mcfg_fixup_match(struct pci_cfg_fixup *f,
diff --git a/drivers/pci/host/mcfg-quirks.h b/drivers/pci/host/mcfg-quirks.h
index 411c667..a2d2aaa 100644
--- a/drivers/pci/host/mcfg-quirks.h
+++ b/drivers/pci/host/mcfg-quirks.h
@@ -21,4 +21,12 @@ struct pci_config_window *
 thunder_pem_cfg_init(struct acpi_pci_root *root, struct pci_ops *ops);
 #endif
 
+#ifdef CONFIG_PCI_HISI_ACPI
+struct pci_config_window *
+hisi_pcie_acpi_hip05_init(struct acpi_pci_root *root, struct pci_ops *ops);
+
+struct pci_config_window *
+hisi_pcie_acpi_hip06_init(struct acpi_pci_root *root, struct pci_ops *ops);
+#endif
+
 #endif /* __MCFG_QUIRKS_H__ */
diff --git a/drivers/pci/host/pcie-hisi-acpi.c 
b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 000..93572d0
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,151 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu 
+ * Gabriele Paoloni 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+
+#include "mcfg-quirks.h"
+#include "pcie-hisi.h"
+
+#define DEBUG0  0x728
+#define RC_NUM  4
+
+enum soc_type {
+   HIP05,
+   HIP06,
+};
+
+struct hisi_rc_res {
+   int soc_type;
+   struct resource res[RC_NUM];
+};
+
+static int hisi_pcie_link_up_acpi(struct pci_config_window *cfg)
+{
+   u32 val;
+   void __iomem *reg_base = cfg->pr

[RFC PATCH 0/3] Add ACPI support for Hisilicon PCIe Host Controller

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06 SoC PCIe
controllers.
The three patches respectively:
- re-architect the current HiSilicon driver to make it scalable to
  the new ACPI quirks.
- rework the current HiSilicon driver to add support for ECAM
  platforms(not RC).
- adds the HiSilicon ACPI specific quirks.

This patchset is base on Tomasz RFC V4 quirk mechanism:
https://lkml.org/lkml/2016/6/28/165

Dongdong Liu (3):
  PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for
ACPI
  PCI: hisi: Add ECAM support for devices that are not RC
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 .../devicetree/bindings/pci/hisilicon-pcie.txt |  15 +-
 MAINTAINERS|   3 +
 drivers/pci/host/Kconfig   |   7 +
 drivers/pci/host/Makefile  |   3 +-
 drivers/pci/host/mcfg-quirks.c |   8 ++
 drivers/pci/host/mcfg-quirks.h |   8 ++
 drivers/pci/host/pcie-designware.c |   3 +-
 drivers/pci/host/pcie-designware.h |   2 +
 drivers/pci/host/pcie-hisi-acpi.c  | 151 +
 drivers/pci/host/pcie-hisi-common.c|  66 +
 drivers/pci/host/pcie-hisi.c   | 143 ++-
 drivers/pci/host/pcie-hisi.h   |  25 
 12 files changed, 351 insertions(+), 83 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c
 create mode 100644 drivers/pci/host/pcie-hisi-common.c
 create mode 100644 drivers/pci/host/pcie-hisi.h

-- 
1.9.1

[RFC PATCH 0/3] Add ACPI support for Hisilicon PCIe Host Controller

[Dongdong Liu]

This patchset adds ACPI support for the HiSilicon Hip05/Hip06 SoC PCIe
controllers.
The three patches respectively:
- re-architect the current HiSilicon driver to make it scalable to
  the new ACPI quirks.
- rework the current HiSilicon driver to add support for ECAM
  platforms(not RC).
- adds the HiSilicon ACPI specific quirks.

This patchset is base on Tomasz RFC V4 quirk mechanism:
https://lkml.org/lkml/2016/6/28/165

Dongdong Liu (3):
  PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for
ACPI
  PCI: hisi: Add ECAM support for devices that are not RC
  PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers

 .../devicetree/bindings/pci/hisilicon-pcie.txt |  15 +-
 MAINTAINERS|   3 +
 drivers/pci/host/Kconfig   |   7 +
 drivers/pci/host/Makefile  |   3 +-
 drivers/pci/host/mcfg-quirks.c |   8 ++
 drivers/pci/host/mcfg-quirks.h |   8 ++
 drivers/pci/host/pcie-designware.c |   3 +-
 drivers/pci/host/pcie-designware.h |   2 +
 drivers/pci/host/pcie-hisi-acpi.c  | 151 +
 drivers/pci/host/pcie-hisi-common.c|  66 +
 drivers/pci/host/pcie-hisi.c   | 143 ++-
 drivers/pci/host/pcie-hisi.h   |  25 
 12 files changed, 351 insertions(+), 83 deletions(-)
 create mode 100644 drivers/pci/host/pcie-hisi-acpi.c
 create mode 100644 drivers/pci/host/pcie-hisi-common.c
 create mode 100644 drivers/pci/host/pcie-hisi.h

-- 
1.9.1

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Dongdong Liu]

Hi Po

在 2016/7/5 11:03, Po Liu 写道:

Hi Dongdong,

The patch were intend to fixup the NXP layerscape serial SOC and were tested ok.
I am not clear what platform are you trying to fix.


My platform is an ARM64 platform, PCIe host controller also use Synopsys 
Designware.


The problem on your board may be as below comments:



  -Original Message-
  From: Dongdong Liu [mailto:liudongdo...@huawei.com]
  Sent: Monday, July 04, 2016 4:44 PM
  To: Po Liu; linux-...@vger.kernel.org; linux-arm-
  ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
  devicet...@vger.kernel.org
  Cc: Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang;
  Mingkai Hu; Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian;
  Murali Karicheri; Linuxarm
  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

  Hi Po

  I found a problem with the similar patch. as the below log.

  [4.287060] pci :80:00.0: quirk_aer_interrupt dev->irq 416
  [4.293778] pcieport :80:00.0: pci_device_probe in
  [4.299605] pcieport :80:00.0: of_irq_parse_pci() failed with
  rc=-22
  [4.307209] pcieport :80:00.0: init_service_irqs  dev->irq 0

  The fucntions are called as below sequence.
  1. quirk_aer_interrupt, get the aer dev->irq 416.


This code quirk_aer_interrupt() should be run at 
pci_fixup_device(pci_fixup_final) which is in the pci_bus_add_devices()


Yes, you are right.




  2. pci_device_probe->of_irq_parse_pci, of_irq_parse_pci() failed, then
  dev->irq changed to 0.


pci_device_probe->of_irq_parse_pci which in the pci_scan_child_bus() run before 
 pci_bus_add_devices(). See dw_pcie_host_init().
Apparently , your quirk_aer_interrupt() is running before the dev->irq 
assignment in the of_irq_parse_pci().

So make sure your configure the quirk_aer_interrupt() run in the FINAL stage in 
the quirk.c OR check your host driver which you are using.


Yes , It is FINAL stage in the quirk. I use DECLARE_PCI_FIXUP_FINAL.
I find it is the below patch affect this. 
(https://patchwork.kernel.org/patch/9170333/),
but the patch will be applied to linux 4.8. So the problem will also be existed.

ARM64: PCI: ACPI support for legacy IRQs parsing and consolidation with DT code
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index d5d3d26..b3b8a2c 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -51,11 +51,16 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
 }

 /*
- * Try to assign the IRQ number from DT when adding a new device
+ * Try to assign the IRQ number when probing a new device
  */
-int pcibios_add_device(struct pci_dev *dev)
+int pcibios_alloc_irq(struct pci_dev *dev)
 {
-   dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+ if (acpi_disabled)
+ dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+#ifdef CONFIG_ACPI
+ else
+ return acpi_pci_irq_enable(dev);
+#endif

return 0;
 }

Thanks
Dongdong





  So this patch could not work with aer.

  Thanks
  Dongdong
  在 2016/6/14 16:24, Po Liu 写道:
  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
  > maybe there is interrupt line for aer pme etc. Search the interrupt
  > number in the fdt file. Then fixup the dev->irq with it.
  >
  > Signed-off-by: Po Liu <po@nxp.com>
  > ---
  > changes for V3:
  >  - Move to quirk;
  >  - Only correct the irq in RC mode;
  >
  >   drivers/pci/quirks.c | 29 +
  >   1 file changed, 29 insertions(+)
  >
  > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
  > ee72ebe..8b39cce 100644
  > --- a/drivers/pci/quirks.c
  > +++ b/drivers/pci/quirks.c
  > @@ -25,6 +25,7 @@
  >   #include 
  >   #include 
  >   #include 
  > +#include 
  >   #include  /* isa_dma_bridge_buggy */
  >   #include "pci.h"
  >
  > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
  pci_dev *pdev)
  >  }
  >   }
  >   DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
  > quirk_intel_qat_vf_cap);
  > +
  > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
  > + * but use standalone irq. Read the device tree for the aer
  > + * interrupt number.
  > + */
  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
  > +int ret;
  > +u8 header_type;
  > +struct device_node *np = NULL;
  > +
  > +/* Only for the RC mode device */
  > +pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
  > +if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
  > +return;
  > +
  > +if (dev->bus->dev.of_node)
  > +np = dev->bus->dev.of_node;
  > +
  > +if (IS_EN

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Dongdong Liu]

Hi Po

在 2016/7/5 11:03, Po Liu 写道:

Hi Dongdong,

The patch were intend to fixup the NXP layerscape serial SOC and were tested ok.
I am not clear what platform are you trying to fix.


My platform is an ARM64 platform, PCIe host controller also use Synopsys 
Designware.


The problem on your board may be as below comments:



  -Original Message-
  From: Dongdong Liu [mailto:liudongdo...@huawei.com]
  Sent: Monday, July 04, 2016 4:44 PM
  To: Po Liu; linux-...@vger.kernel.org; linux-arm-
  ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
  devicet...@vger.kernel.org
  Cc: Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang;
  Mingkai Hu; Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian;
  Murali Karicheri; Linuxarm
  Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

  Hi Po

  I found a problem with the similar patch. as the below log.

  [4.287060] pci :80:00.0: quirk_aer_interrupt dev->irq 416
  [4.293778] pcieport :80:00.0: pci_device_probe in
  [4.299605] pcieport :80:00.0: of_irq_parse_pci() failed with
  rc=-22
  [4.307209] pcieport :80:00.0: init_service_irqs  dev->irq 0

  The fucntions are called as below sequence.
  1. quirk_aer_interrupt, get the aer dev->irq 416.


This code quirk_aer_interrupt() should be run at 
pci_fixup_device(pci_fixup_final) which is in the pci_bus_add_devices()


Yes, you are right.




  2. pci_device_probe->of_irq_parse_pci, of_irq_parse_pci() failed, then
  dev->irq changed to 0.


pci_device_probe->of_irq_parse_pci which in the pci_scan_child_bus() run before 
 pci_bus_add_devices(). See dw_pcie_host_init().
Apparently , your quirk_aer_interrupt() is running before the dev->irq 
assignment in the of_irq_parse_pci().

So make sure your configure the quirk_aer_interrupt() run in the FINAL stage in 
the quirk.c OR check your host driver which you are using.


Yes , It is FINAL stage in the quirk. I use DECLARE_PCI_FIXUP_FINAL.
I find it is the below patch affect this. 
(https://patchwork.kernel.org/patch/9170333/),
but the patch will be applied to linux 4.8. So the problem will also be existed.

ARM64: PCI: ACPI support for legacy IRQs parsing and consolidation with DT code
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index d5d3d26..b3b8a2c 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -51,11 +51,16 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
 }

 /*
- * Try to assign the IRQ number from DT when adding a new device
+ * Try to assign the IRQ number when probing a new device
  */
-int pcibios_add_device(struct pci_dev *dev)
+int pcibios_alloc_irq(struct pci_dev *dev)
 {
-   dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+ if (acpi_disabled)
+ dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+#ifdef CONFIG_ACPI
+ else
+ return acpi_pci_irq_enable(dev);
+#endif

return 0;
 }

Thanks
Dongdong





  So this patch could not work with aer.

  Thanks
  Dongdong
  在 2016/6/14 16:24, Po Liu 写道:
  > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
  > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
  > maybe there is interrupt line for aer pme etc. Search the interrupt
  > number in the fdt file. Then fixup the dev->irq with it.
  >
  > Signed-off-by: Po Liu 
  > ---
  > changes for V3:
  >  - Move to quirk;
  >  - Only correct the irq in RC mode;
  >
  >   drivers/pci/quirks.c | 29 +
  >   1 file changed, 29 insertions(+)
  >
  > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
  > ee72ebe..8b39cce 100644
  > --- a/drivers/pci/quirks.c
  > +++ b/drivers/pci/quirks.c
  > @@ -25,6 +25,7 @@
  >   #include 
  >   #include 
  >   #include 
  > +#include 
  >   #include  /* isa_dma_bridge_buggy */
  >   #include "pci.h"
  >
  > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
  pci_dev *pdev)
  >  }
  >   }
  >   DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
  > quirk_intel_qat_vf_cap);
  > +
  > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
  > + * but use standalone irq. Read the device tree for the aer
  > + * interrupt number.
  > + */
  > +static void quirk_aer_interrupt(struct pci_dev *dev) {
  > +int ret;
  > +u8 header_type;
  > +struct device_node *np = NULL;
  > +
  > +/* Only for the RC mode device */
  > +pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
  > +if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
  > +return;
  > +
  > +if (dev->bus->dev.of_node)
  > +np = dev->bus->dev.of_node;
  > +
  > +if (IS_ENABLED(

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Dongdong Liu]

Hi Po

I found a problem with the similar patch. as the below log.

[4.287060] pci :80:00.0: quirk_aer_interrupt dev->irq 416
[4.293778] pcieport :80:00.0: pci_device_probe in
[4.299605] pcieport :80:00.0: of_irq_parse_pci() failed with rc=-22
[4.307209] pcieport :80:00.0: init_service_irqs  dev->irq 0

The fucntions are called as below sequence.
1. quirk_aer_interrupt, get the aer dev->irq 416.
2. pci_device_probe->of_irq_parse_pci, of_irq_parse_pci() failed, then dev->irq 
changed to 0.

So this patch could not work with aer.

Thanks
Dongdong
在 2016/6/14 16:24, Po Liu 写道:

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.

Signed-off-by: Po Liu 
---
changes for V3:
- Move to quirk;
- Only correct the irq in RC mode;

  drivers/pci/quirks.c | 29 +
  1 file changed, 29 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..8b39cce 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
  #include 
  #include 
  #include 
+#include 
  #include /* isa_dma_bridge_buggy */
  #include "pci.h"

@@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
}
  }
  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+   int ret;
+   u8 header_type;
+   struct device_node *np = NULL;
+
+   /* Only for the RC mode device */
+   pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
+   if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
+   return;
+
+   if (dev->bus->dev.of_node)
+   np = dev->bus->dev.of_node;
+
+   if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+   ret = of_irq_get_byname(np, "aer");
+   if (ret > 0) {
+   dev->no_msi = 1;
+   dev->irq = ret;
+   }
+   }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 
quirk_aer_interrupt);

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Dongdong Liu]

Hi Po

I found a problem with the similar patch. as the below log.

[4.287060] pci :80:00.0: quirk_aer_interrupt dev->irq 416
[4.293778] pcieport :80:00.0: pci_device_probe in
[4.299605] pcieport :80:00.0: of_irq_parse_pci() failed with rc=-22
[4.307209] pcieport :80:00.0: init_service_irqs  dev->irq 0

The fucntions are called as below sequence.
1. quirk_aer_interrupt, get the aer dev->irq 416.
2. pci_device_probe->of_irq_parse_pci, of_irq_parse_pci() failed, then dev->irq 
changed to 0.

So this patch could not work with aer.

Thanks
Dongdong
在 2016/6/14 16:24, Po Liu 写道:

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.

Signed-off-by: Po Liu 
---
changes for V3:
- Move to quirk;
- Only correct the irq in RC mode;

  drivers/pci/quirks.c | 29 +
  1 file changed, 29 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..8b39cce 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
  #include 
  #include 
  #include 
+#include 
  #include /* isa_dma_bridge_buggy */
  #include "pci.h"

@@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
}
  }
  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+   int ret;
+   u8 header_type;
+   struct device_node *np = NULL;
+
+   /* Only for the RC mode device */
+   pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
+   if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
+   return;
+
+   if (dev->bus->dev.of_node)
+   np = dev->bus->dev.of_node;
+
+   if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+   ret = of_irq_get_byname(np, "aer");
+   if (ret > 0) {
+   dev->no_msi = 1;
+   dev->irq = ret;
+   }
+   }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 
quirk_aer_interrupt);

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Dongdong Liu]

在 2016/6/14 16:24, Po Liu 写道:

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.

Signed-off-by: Po Liu 
---
changes for V3:
- Move to quirk;
- Only correct the irq in RC mode;

  drivers/pci/quirks.c | 29 +
  1 file changed, 29 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..8b39cce 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
  #include 
  #include 
  #include 
+#include 
  #include /* isa_dma_bridge_buggy */
  #include "pci.h"

@@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
}
  }
  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+   int ret;
+   u8 header_type;
+   struct device_node *np = NULL;
+
+   /* Only for the RC mode device */
+   pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
+   if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
+   return;


How about that it is changed as below.

/* Only for the RC mode device */
if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
return;

Dongdong
Thanks

+
+   if (dev->bus->dev.of_node)
+   np = dev->bus->dev.of_node;
+
+   if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+   ret = of_irq_get_byname(np, "aer");
+   if (ret > 0) {
+   dev->no_msi = 1;
+   dev->irq = ret;
+   }
+   }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 
quirk_aer_interrupt);

Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk

[Dongdong Liu]

在 2016/6/14 16:24, Po Liu 写道:

On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.

Signed-off-by: Po Liu 
---
changes for V3:
- Move to quirk;
- Only correct the irq in RC mode;

  drivers/pci/quirks.c | 29 +
  1 file changed, 29 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..8b39cce 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
  #include 
  #include 
  #include 
+#include 
  #include /* isa_dma_bridge_buggy */
  #include "pci.h"

@@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
}
  }
  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+   int ret;
+   u8 header_type;
+   struct device_node *np = NULL;
+
+   /* Only for the RC mode device */
+   pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
+   if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
+   return;


How about that it is changed as below.

/* Only for the RC mode device */
if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
return;

Dongdong
Thanks

+
+   if (dev->bus->dev.of_node)
+   np = dev->bus->dev.of_node;
+
+   if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+   ret = of_irq_get_byname(np, "aer");
+   if (ret > 0) {
+   dev->no_msi = 1;
+   dev->irq = ret;
+   }
+   }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 
quirk_aer_interrupt);

Re: [RFC PATCH V2 1/2] ACPI/PCI: Match PCI config space accessors against platfrom specific ECAM quirks

[Dongdong Liu]

Hi Duc

在 2016/6/14 17:00, Duc Dang 写道:

On Mon, Jun 13, 2016 at 10:51 PM, Dongdong Liu <liudongdo...@huawei.com> wrote:

Hi Duc

在 2016/6/14 4:57, Duc Dang 写道:


On Mon, Jun 13, 2016 at 8:47 AM, Christopher Covington
<c...@codeaurora.org> wrote:


Hi Dongdong,

On 06/13/2016 09:02 AM, Dongdong Liu wrote:


diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index d3c3e85..49612b3 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -22,6 +22,10 @@
   #include 
   #include 
   #include 
+#include 
+
+/* Root pointer to the mapped MCFG table */
+static struct acpi_table_mcfg *mcfg_table;

   /* Structure to hold entries from the MCFG table */
   struct mcfg_entry {
@@ -35,6 +39,38 @@ struct mcfg_entry {
   /* List to save mcfg entries */
   static LIST_HEAD(pci_mcfg_list);

+extern struct pci_cfg_fixup __start_acpi_mcfg_fixups[];
+extern struct pci_cfg_fixup __end_acpi_mcfg_fixups[];
+
+struct pci_ecam_ops *pci_mcfg_get_ops(struct acpi_pci_root *root)
+{
+ int bus_num = root->secondary.start;
+ int domain = root->segment;
+ struct pci_cfg_fixup *f;
+
+ if (!mcfg_table)
+ return _generic_ecam_ops;
+
+ /*
+  * Match against platform specific quirks and return corresponding
+  * CAM ops.
+  *
+  * First match against PCI topology  then use OEM ID
and
+  * OEM revision from MCFG table standard header.
+  */
+ for (f = __start_acpi_mcfg_fixups; f < __end_acpi_mcfg_fixups;
f++) {
+ if ((f->domain == domain || f->domain ==
PCI_MCFG_DOMAIN_ANY) &&
+ (f->bus_num == bus_num || f->bus_num ==
PCI_MCFG_BUS_ANY) &&
+ (!strncmp(f->oem_id, mcfg_table->header.oem_id,
+   ACPI_OEM_ID_SIZE)) &&
+ (!strncmp(f->oem_table_id,
mcfg_table->header.oem_table_id,
+   ACPI_OEM_TABLE_ID_SIZE)))



This would just be a small convenience, but if the character count used
here were

min(strlen(f->oem_id), ACPI_OEM_ID_SIZE)

then the parameters to DECLARE_ACPI_MCFG_FIXUP macro could be substrings
and
wouldn't need to be padded out to the full length.


+ return f->ops;
+ }
+ /* No quirks, use ECAM */
+ return _generic_ecam_ops;
+}




diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 7d63a66..088a1da 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -25,6 +25,7 @@ static inline acpi_status
pci_acpi_remove_pm_notifier(struct acpi_device *dev)
   extern phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle);

   extern phys_addr_t pci_mcfg_lookup(u16 domain, struct resource
*bus_res);
+extern struct pci_ecam_ops *pci_mcfg_get_ops(struct acpi_pci_root
*root);

   static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev
*pdev)
   {
@@ -72,6 +73,25 @@ struct acpi_pci_root_ops {
int (*prepare_resources)(struct acpi_pci_root_info *info);
   };

+struct pci_cfg_fixup {
+ struct pci_ecam_ops *ops;
+ char *oem_id;
+ char *oem_table_id;
+ int domain;
+ int bus_num;
+};
+
+#define PCI_MCFG_DOMAIN_ANY  -1
+#define PCI_MCFG_BUS_ANY -1
+
+/* Designate a routine to fix up buggy MCFG */
+#define DECLARE_ACPI_MCFG_FIXUP(ops, oem_id, oem_table_id, dom, bus) \
+ static const struct pci_cfg_fixup   \
+ __mcfg_fixup_##oem_id##oem_table_id##dom##bus   \



I'm not entirely sure that this is the right fix--I'm pretty blindly
following a GCC documentation suggestion [1]--but removing the first two
preprocessor concatenation operators "##" solved the following build
error
for me.

include/linux/pci-acpi.h:90:2: error: pasting "__mcfg_fixup_" and
""QCOM"" does not give a valid preprocessing token
__mcfg_fixup_##oem_id##oem_table_id##dom##bus   \



I think the problem is gcc is not happy with quoted string when
processing these tokens
(""QCOM"", the extra "" are added by gcc). So should we not concat
string tokens and
use the fixup definition in v1 of this RFC:
/* Designate a routine to fix up buggy MCFG */
#define DECLARE_ACPI_MCFG_FIXUP(ops, oem_id, rev, dom, bus) \
  static const struct pci_cfg_fixup
__mcfg_fixup_##system##dom##bus\
   __used __attribute__((__section__(".acpi_fixup_mcfg"), \
  aligned((sizeof(void *) =   \
  { ops, oem_id, rev, dom, bus };



V1 fixup exist the redefinition error when compiling mutiple
DECLARE_ACPI_MCFG_FIXUP
with the same PCI_MCFG_DOMAIN_ANY and PCI_MCFG_BUS_ANY.

#define EFI_ACPI_HISI_OEM_ID "HISI"
#define EFI_ACPI_HISI_D02_OEM_TABLE_ID "HISI-D02"
#define EFI_ACPI_HISI_D03_OEM_TABLE_ID "HISI-D03"

DECLARE_ACPI_MCFG_FIXUP(_pcie_ecam_ops, EFI_ACPI_HISI_OEM_ID,
EFI_ACPI_

Re: [RFC PATCH V2 1/2] ACPI/PCI: Match PCI config space accessors against platfrom specific ECAM quirks

[Dongdong Liu]

Hi Duc

在 2016/6/14 17:00, Duc Dang 写道:

On Mon, Jun 13, 2016 at 10:51 PM, Dongdong Liu  wrote:

Hi Duc

在 2016/6/14 4:57, Duc Dang 写道:


On Mon, Jun 13, 2016 at 8:47 AM, Christopher Covington
 wrote:


Hi Dongdong,

On 06/13/2016 09:02 AM, Dongdong Liu wrote:


diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index d3c3e85..49612b3 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -22,6 +22,10 @@
   #include 
   #include 
   #include 
+#include 
+
+/* Root pointer to the mapped MCFG table */
+static struct acpi_table_mcfg *mcfg_table;

   /* Structure to hold entries from the MCFG table */
   struct mcfg_entry {
@@ -35,6 +39,38 @@ struct mcfg_entry {
   /* List to save mcfg entries */
   static LIST_HEAD(pci_mcfg_list);

+extern struct pci_cfg_fixup __start_acpi_mcfg_fixups[];
+extern struct pci_cfg_fixup __end_acpi_mcfg_fixups[];
+
+struct pci_ecam_ops *pci_mcfg_get_ops(struct acpi_pci_root *root)
+{
+ int bus_num = root->secondary.start;
+ int domain = root->segment;
+ struct pci_cfg_fixup *f;
+
+ if (!mcfg_table)
+ return _generic_ecam_ops;
+
+ /*
+  * Match against platform specific quirks and return corresponding
+  * CAM ops.
+  *
+  * First match against PCI topology  then use OEM ID
and
+  * OEM revision from MCFG table standard header.
+  */
+ for (f = __start_acpi_mcfg_fixups; f < __end_acpi_mcfg_fixups;
f++) {
+ if ((f->domain == domain || f->domain ==
PCI_MCFG_DOMAIN_ANY) &&
+ (f->bus_num == bus_num || f->bus_num ==
PCI_MCFG_BUS_ANY) &&
+ (!strncmp(f->oem_id, mcfg_table->header.oem_id,
+   ACPI_OEM_ID_SIZE)) &&
+ (!strncmp(f->oem_table_id,
mcfg_table->header.oem_table_id,
+   ACPI_OEM_TABLE_ID_SIZE)))



This would just be a small convenience, but if the character count used
here were

min(strlen(f->oem_id), ACPI_OEM_ID_SIZE)

then the parameters to DECLARE_ACPI_MCFG_FIXUP macro could be substrings
and
wouldn't need to be padded out to the full length.


+ return f->ops;
+ }
+ /* No quirks, use ECAM */
+ return _generic_ecam_ops;
+}




diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 7d63a66..088a1da 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -25,6 +25,7 @@ static inline acpi_status
pci_acpi_remove_pm_notifier(struct acpi_device *dev)
   extern phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle);

   extern phys_addr_t pci_mcfg_lookup(u16 domain, struct resource
*bus_res);
+extern struct pci_ecam_ops *pci_mcfg_get_ops(struct acpi_pci_root
*root);

   static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev
*pdev)
   {
@@ -72,6 +73,25 @@ struct acpi_pci_root_ops {
int (*prepare_resources)(struct acpi_pci_root_info *info);
   };

+struct pci_cfg_fixup {
+ struct pci_ecam_ops *ops;
+ char *oem_id;
+ char *oem_table_id;
+ int domain;
+ int bus_num;
+};
+
+#define PCI_MCFG_DOMAIN_ANY  -1
+#define PCI_MCFG_BUS_ANY -1
+
+/* Designate a routine to fix up buggy MCFG */
+#define DECLARE_ACPI_MCFG_FIXUP(ops, oem_id, oem_table_id, dom, bus) \
+ static const struct pci_cfg_fixup   \
+ __mcfg_fixup_##oem_id##oem_table_id##dom##bus   \



I'm not entirely sure that this is the right fix--I'm pretty blindly
following a GCC documentation suggestion [1]--but removing the first two
preprocessor concatenation operators "##" solved the following build
error
for me.

include/linux/pci-acpi.h:90:2: error: pasting "__mcfg_fixup_" and
""QCOM"" does not give a valid preprocessing token
__mcfg_fixup_##oem_id##oem_table_id##dom##bus   \



I think the problem is gcc is not happy with quoted string when
processing these tokens
(""QCOM"", the extra "" are added by gcc). So should we not concat
string tokens and
use the fixup definition in v1 of this RFC:
/* Designate a routine to fix up buggy MCFG */
#define DECLARE_ACPI_MCFG_FIXUP(ops, oem_id, rev, dom, bus) \
  static const struct pci_cfg_fixup
__mcfg_fixup_##system##dom##bus\
   __used __attribute__((__section__(".acpi_fixup_mcfg"), \
  aligned((sizeof(void *) =   \
  { ops, oem_id, rev, dom, bus };



V1 fixup exist the redefinition error when compiling mutiple
DECLARE_ACPI_MCFG_FIXUP
with the same PCI_MCFG_DOMAIN_ANY and PCI_MCFG_BUS_ANY.

#define EFI_ACPI_HISI_OEM_ID "HISI"
#define EFI_ACPI_HISI_D02_OEM_TABLE_ID "HISI-D02"
#define EFI_ACPI_HISI_D03_OEM_TABLE_ID "HISI-D03"

DECLARE_ACPI_MCFG_FIXUP(_pcie_ecam_ops, EFI_ACPI_HISI_OEM_ID,
EFI_ACPI_HISI_D02_OEM_TABLE_ID, PCI_MCFG_DOMAIN_ANY,
PCI_MCFG_BUS_ANY);

DECLARE_

Re: [RFC PATCH V2 1/2] ACPI/PCI: Match PCI config space accessors against platfrom specific ECAM quirks

[Dongdong Liu]

Hi Duc

在 2016/6/14 4:57, Duc Dang 写道:

On Mon, Jun 13, 2016 at 8:47 AM, Christopher Covington
<c...@codeaurora.org> wrote:

Hi Dongdong,

On 06/13/2016 09:02 AM, Dongdong Liu wrote:

diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index d3c3e85..49612b3 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -22,6 +22,10 @@
  #include 
  #include 
  #include 
+#include 
+
+/* Root pointer to the mapped MCFG table */
+static struct acpi_table_mcfg *mcfg_table;

  /* Structure to hold entries from the MCFG table */
  struct mcfg_entry {
@@ -35,6 +39,38 @@ struct mcfg_entry {
  /* List to save mcfg entries */
  static LIST_HEAD(pci_mcfg_list);

+extern struct pci_cfg_fixup __start_acpi_mcfg_fixups[];
+extern struct pci_cfg_fixup __end_acpi_mcfg_fixups[];
+
+struct pci_ecam_ops *pci_mcfg_get_ops(struct acpi_pci_root *root)
+{
+ int bus_num = root->secondary.start;
+ int domain = root->segment;
+ struct pci_cfg_fixup *f;
+
+ if (!mcfg_table)
+ return _generic_ecam_ops;
+
+ /*
+  * Match against platform specific quirks and return corresponding
+  * CAM ops.
+  *
+  * First match against PCI topology  then use OEM ID and
+  * OEM revision from MCFG table standard header.
+  */
+ for (f = __start_acpi_mcfg_fixups; f < __end_acpi_mcfg_fixups; f++) {
+ if ((f->domain == domain || f->domain == PCI_MCFG_DOMAIN_ANY) &&
+ (f->bus_num == bus_num || f->bus_num == PCI_MCFG_BUS_ANY) &&
+ (!strncmp(f->oem_id, mcfg_table->header.oem_id,
+   ACPI_OEM_ID_SIZE)) &&
+ (!strncmp(f->oem_table_id, mcfg_table->header.oem_table_id,
+   ACPI_OEM_TABLE_ID_SIZE)))


This would just be a small convenience, but if the character count used here 
were

min(strlen(f->oem_id), ACPI_OEM_ID_SIZE)

then the parameters to DECLARE_ACPI_MCFG_FIXUP macro could be substrings and
wouldn't need to be padded out to the full length.


+ return f->ops;
+ }
+ /* No quirks, use ECAM */
+ return _generic_ecam_ops;
+}



diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 7d63a66..088a1da 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -25,6 +25,7 @@ static inline acpi_status pci_acpi_remove_pm_notifier(struct 
acpi_device *dev)
  extern phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle);

  extern phys_addr_t pci_mcfg_lookup(u16 domain, struct resource *bus_res);
+extern struct pci_ecam_ops *pci_mcfg_get_ops(struct acpi_pci_root *root);

  static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
  {
@@ -72,6 +73,25 @@ struct acpi_pci_root_ops {
   int (*prepare_resources)(struct acpi_pci_root_info *info);
  };

+struct pci_cfg_fixup {
+ struct pci_ecam_ops *ops;
+ char *oem_id;
+ char *oem_table_id;
+ int domain;
+ int bus_num;
+};
+
+#define PCI_MCFG_DOMAIN_ANY  -1
+#define PCI_MCFG_BUS_ANY -1
+
+/* Designate a routine to fix up buggy MCFG */
+#define DECLARE_ACPI_MCFG_FIXUP(ops, oem_id, oem_table_id, dom, bus) \
+ static const struct pci_cfg_fixup   \
+ __mcfg_fixup_##oem_id##oem_table_id##dom##bus   \


I'm not entirely sure that this is the right fix--I'm pretty blindly
following a GCC documentation suggestion [1]--but removing the first two
preprocessor concatenation operators "##" solved the following build error
for me.

include/linux/pci-acpi.h:90:2: error: pasting "__mcfg_fixup_" and ""QCOM"" does 
not give a valid preprocessing token
   __mcfg_fixup_##oem_id##oem_table_id##dom##bus   \


I think the problem is gcc is not happy with quoted string when
processing these tokens
(""QCOM"", the extra "" are added by gcc). So should we not concat
string tokens and
use the fixup definition in v1 of this RFC:
/* Designate a routine to fix up buggy MCFG */
#define DECLARE_ACPI_MCFG_FIXUP(ops, oem_id, rev, dom, bus) \
 static const struct pci_cfg_fixup __mcfg_fixup_##system##dom##bus\
  __used __attribute__((__section__(".acpi_fixup_mcfg"), \
 aligned((sizeof(void *) =   \
 { ops, oem_id, rev, dom, bus };


V1 fixup exist the redefinition error when compiling mutiple 
DECLARE_ACPI_MCFG_FIXUP
with the same PCI_MCFG_DOMAIN_ANY and PCI_MCFG_BUS_ANY.

#define EFI_ACPI_HISI_OEM_ID "HISI"
#define EFI_ACPI_HISI_D02_OEM_TABLE_ID "HISI-D02"
#define EFI_ACPI_HISI_D03_OEM_TABLE_ID "HISI-D03"

DECLARE_ACPI_MCFG_FIXUP(_pcie_ecam_ops, EFI_ACPI_HISI_OEM_ID,
   EFI_ACPI_HISI_D02_OEM_TABLE_ID, PCI_MCFG_DOMAIN_ANY, PCI_MCFG_BUS_ANY);

DECLARE_ACPI_MCFG_FIXUP(_pcie_ecam_ops, EFI_ACPI_HISI_OEM_ID,
   EFI_ACP

Re: [RFC PATCH V2 1/2] ACPI/PCI: Match PCI config space accessors against platfrom specific ECAM quirks

[Dongdong Liu]

Hi Duc

在 2016/6/14 4:57, Duc Dang 写道:

On Mon, Jun 13, 2016 at 8:47 AM, Christopher Covington
 wrote:

Hi Dongdong,

On 06/13/2016 09:02 AM, Dongdong Liu wrote:

diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index d3c3e85..49612b3 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -22,6 +22,10 @@
  #include 
  #include 
  #include 
+#include 
+
+/* Root pointer to the mapped MCFG table */
+static struct acpi_table_mcfg *mcfg_table;

  /* Structure to hold entries from the MCFG table */
  struct mcfg_entry {
@@ -35,6 +39,38 @@ struct mcfg_entry {
  /* List to save mcfg entries */
  static LIST_HEAD(pci_mcfg_list);

+extern struct pci_cfg_fixup __start_acpi_mcfg_fixups[];
+extern struct pci_cfg_fixup __end_acpi_mcfg_fixups[];
+
+struct pci_ecam_ops *pci_mcfg_get_ops(struct acpi_pci_root *root)
+{
+ int bus_num = root->secondary.start;
+ int domain = root->segment;
+ struct pci_cfg_fixup *f;
+
+ if (!mcfg_table)
+ return _generic_ecam_ops;
+
+ /*
+  * Match against platform specific quirks and return corresponding
+  * CAM ops.
+  *
+  * First match against PCI topology  then use OEM ID and
+  * OEM revision from MCFG table standard header.
+  */
+ for (f = __start_acpi_mcfg_fixups; f < __end_acpi_mcfg_fixups; f++) {
+ if ((f->domain == domain || f->domain == PCI_MCFG_DOMAIN_ANY) &&
+ (f->bus_num == bus_num || f->bus_num == PCI_MCFG_BUS_ANY) &&
+ (!strncmp(f->oem_id, mcfg_table->header.oem_id,
+   ACPI_OEM_ID_SIZE)) &&
+ (!strncmp(f->oem_table_id, mcfg_table->header.oem_table_id,
+   ACPI_OEM_TABLE_ID_SIZE)))


This would just be a small convenience, but if the character count used here 
were

min(strlen(f->oem_id), ACPI_OEM_ID_SIZE)

then the parameters to DECLARE_ACPI_MCFG_FIXUP macro could be substrings and
wouldn't need to be padded out to the full length.


+ return f->ops;
+ }
+ /* No quirks, use ECAM */
+ return _generic_ecam_ops;
+}



diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 7d63a66..088a1da 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -25,6 +25,7 @@ static inline acpi_status pci_acpi_remove_pm_notifier(struct 
acpi_device *dev)
  extern phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle);

  extern phys_addr_t pci_mcfg_lookup(u16 domain, struct resource *bus_res);
+extern struct pci_ecam_ops *pci_mcfg_get_ops(struct acpi_pci_root *root);

  static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
  {
@@ -72,6 +73,25 @@ struct acpi_pci_root_ops {
   int (*prepare_resources)(struct acpi_pci_root_info *info);
  };

+struct pci_cfg_fixup {
+ struct pci_ecam_ops *ops;
+ char *oem_id;
+ char *oem_table_id;
+ int domain;
+ int bus_num;
+};
+
+#define PCI_MCFG_DOMAIN_ANY  -1
+#define PCI_MCFG_BUS_ANY -1
+
+/* Designate a routine to fix up buggy MCFG */
+#define DECLARE_ACPI_MCFG_FIXUP(ops, oem_id, oem_table_id, dom, bus) \
+ static const struct pci_cfg_fixup   \
+ __mcfg_fixup_##oem_id##oem_table_id##dom##bus   \


I'm not entirely sure that this is the right fix--I'm pretty blindly
following a GCC documentation suggestion [1]--but removing the first two
preprocessor concatenation operators "##" solved the following build error
for me.

include/linux/pci-acpi.h:90:2: error: pasting "__mcfg_fixup_" and ""QCOM"" does 
not give a valid preprocessing token
   __mcfg_fixup_##oem_id##oem_table_id##dom##bus   \


I think the problem is gcc is not happy with quoted string when
processing these tokens
(""QCOM"", the extra "" are added by gcc). So should we not concat
string tokens and
use the fixup definition in v1 of this RFC:
/* Designate a routine to fix up buggy MCFG */
#define DECLARE_ACPI_MCFG_FIXUP(ops, oem_id, rev, dom, bus) \
 static const struct pci_cfg_fixup __mcfg_fixup_##system##dom##bus\
  __used __attribute__((__section__(".acpi_fixup_mcfg"), \
 aligned((sizeof(void *) =   \
 { ops, oem_id, rev, dom, bus };


V1 fixup exist the redefinition error when compiling mutiple 
DECLARE_ACPI_MCFG_FIXUP
with the same PCI_MCFG_DOMAIN_ANY and PCI_MCFG_BUS_ANY.

#define EFI_ACPI_HISI_OEM_ID "HISI"
#define EFI_ACPI_HISI_D02_OEM_TABLE_ID "HISI-D02"
#define EFI_ACPI_HISI_D03_OEM_TABLE_ID "HISI-D03"

DECLARE_ACPI_MCFG_FIXUP(_pcie_ecam_ops, EFI_ACPI_HISI_OEM_ID,
   EFI_ACPI_HISI_D02_OEM_TABLE_ID, PCI_MCFG_DOMAIN_ANY, PCI_MCFG_BUS_ANY);

DECLARE_ACPI_MCFG_FIXUP(_pcie_ecam_ops, EFI_ACPI_HISI_OEM_ID,
   EFI_ACPI_HISI