[PATCH v2] arm64: dts: meson-sm1: fix typo in opp table

[Dongjin Kim]

The freqency 151200 should be 15.

Signed-off-by: Dongjin Kim 
---

Change in v2:
  - wrong fix in the previous patch.

https://patchwork.kernel.org/project/linux-amlogic/patch/20201130054221.GA25448@anyang-linuxfactory-or-kr/
 

---
 arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 71317f5aada1..c309517abae3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -130,7 +130,7 @@
opp-microvolt = <79>;
};
 
-   opp-151200 {
+   opp-15 {
opp-hz = /bits/ 64 <15>;
opp-microvolt = <80>;
};
-- 
2.17.1

[PATCH] arm64: dts: meson-sm1: fix typo in opp table

[Dongjin Kim]

The freqency 15 should be 151200 in 'opp-15'

Signed-off-by: Dongjin Kim 
---
 arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 71317f5aada1..aba1214c4d09 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -131,7 +131,7 @@
};
 
opp-151200 {
-   opp-hz = /bits/ 64 <15>;
+   opp-hz = /bits/ 64 <151200>;
opp-microvolt = <80>;
};
 
-- 
2.17.1

Re: [PATCH] hwmon: (pwm-fan) add fan pwm1_enable attribute

[Dongjin Kim]

On Wed, Nov 25, 2020 at 06:05:36PM -0800, Guenter Roeck wrote:
> On Thu, Nov 26, 2020 at 01:32:42AM +0900, Dongjin Kim wrote:
> > This patch adds to new attribute 'pwm1_enable' to change the fan speed
> > control method as documented in 'Documentation/hwmon/sysfs-interface'.
> > 
> > Signed-off-by: Dongjin Kim 
> 
> The new attribute needs to be documented in
> Documentation/hwmon/pwm-fan.rst, with supported values.
> 
> > ---
> >  drivers/hwmon/pwm-fan.c | 52 -
> >  1 file changed, 46 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c
> > index 1f63807c0399..834275309421 100644
> > --- a/drivers/hwmon/pwm-fan.c
> > +++ b/drivers/hwmon/pwm-fan.c
> > @@ -39,6 +39,7 @@ struct pwm_fan_ctx {
> > unsigned int pwm_fan_max_state;
> > unsigned int *pwm_fan_cooling_levels;
> > struct thermal_cooling_device *cdev;
> > +   int enable;
> >  };
> >  
> >  /* This handler assumes self resetting edge triggered interrupt. */
> > @@ -76,6 +77,10 @@ static int  __set_pwm(struct pwm_fan_ctx *ctx, unsigned 
> > long pwm)
> > struct pwm_state state = { };
> >  
> > mutex_lock(>lock);
> > +
> > +   if (ctx->enable == 0)
> > +   pwm = MAX_PWM;
> > +
> > if (ctx->pwm_value == pwm)
> > goto exit_set_pwm_err;
> >  
> > @@ -137,11 +142,42 @@ static ssize_t rpm_show(struct device *dev,
> > return sprintf(buf, "%u\n", ctx->rpm);
> >  }
> >  
> > +static ssize_t enable_store(struct device *dev,
> > +   struct device_attribute *attr,
> > +   const char *buf, size_t count)
> > +{
> > +   struct pwm_fan_ctx *ctx = dev_get_drvdata(dev);
> > +   int err;
> > +   unsigned long val;
> > +
> > +   err = kstrtoul(buf, 10, );
> > +   if (err)
> > +   return err;
> > +
> 
> 'val' must be validated and only accept permitted values.
Sure.
> 
> > +   mutex_lock(>lock);
> > +   ctx->enable = val;
> > +   mutex_unlock(>lock);
> > +
> > +   err = __set_pwm(ctx, ctx->pwm_fan_cooling_levels[ctx->pwm_fan_state]);
> > +
> > +   return err ? err : count;
> > +}
> > +
> > +static ssize_t enable_show(struct device *dev, struct device_attribute 
> > *attr,
> > +  char *buf)
> > +{
> > +   struct pwm_fan_ctx *ctx = dev_get_drvdata(dev);
> > +
> > +   return sprintf(buf, "%u\n", ctx->enable);
> > +}
> > +
> >  static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
> > +static SENSOR_DEVICE_ATTR_RW(pwm1_enable, enable, 0);
> >  static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0);
> >  
> >  static struct attribute *pwm_fan_attrs[] = {
> > _dev_attr_pwm1.dev_attr.attr,
> > +   _dev_attr_pwm1_enable.dev_attr.attr,
> > _dev_attr_fan1_input.dev_attr.attr,
> > NULL,
> >  };
> > @@ -153,7 +189,7 @@ static umode_t pwm_fan_attrs_visible(struct kobject 
> > *kobj, struct attribute *a,
> > struct pwm_fan_ctx *ctx = dev_get_drvdata(dev);
> >  
> > /* Hide fan_input in case no interrupt is available  */
> > -   if (n == 1 && ctx->irq <= 0)
> > +   if (n == 2 && ctx->irq <= 0)
> > return 0;
> >  
> > return a->mode;
> > @@ -200,7 +236,7 @@ static int
> >  pwm_fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long 
> > state)
> >  {
> > struct pwm_fan_ctx *ctx = cdev->devdata;
> > -   int ret;
> > +   int ret = 0;
> >  
> > if (!ctx || (state > ctx->pwm_fan_max_state))
> > return -EINVAL;
> > @@ -208,10 +244,12 @@ pwm_fan_set_cur_state(struct thermal_cooling_device 
> > *cdev, unsigned long state)
> > if (state == ctx->pwm_fan_state)
> > return 0;
> >  
> > -   ret = __set_pwm(ctx, ctx->pwm_fan_cooling_levels[state]);
> > -   if (ret) {
> > -   dev_err(>device, "Cannot set pwm!\n");
> > -   return ret;
> > +   if (ctx->enable >= 2) {
> 
> What is "automatic" here ? I don't see how this driver or the underlying
> pwm controller/chip would support automatic fan speed control. This is
> completely independent of thermal control: thermal device support does _not_
> imply or suggest "automatic" fan speed control from a pwm chip perspective.
> 
My understanding of 'automatic' is to set the fan speed by a thermal device

[PATCH] hwmon: (pwm-fan) add fan pwm1_enable attribute

[Dongjin Kim]

This patch adds to new attribute 'pwm1_enable' to change the fan speed
control method as documented in 'Documentation/hwmon/sysfs-interface'.

Signed-off-by: Dongjin Kim 
---
 drivers/hwmon/pwm-fan.c | 52 -
 1 file changed, 46 insertions(+), 6 deletions(-)

diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c
index 1f63807c0399..834275309421 100644
--- a/drivers/hwmon/pwm-fan.c
+++ b/drivers/hwmon/pwm-fan.c
@@ -39,6 +39,7 @@ struct pwm_fan_ctx {
unsigned int pwm_fan_max_state;
unsigned int *pwm_fan_cooling_levels;
struct thermal_cooling_device *cdev;
+   int enable;
 };
 
 /* This handler assumes self resetting edge triggered interrupt. */
@@ -76,6 +77,10 @@ static int  __set_pwm(struct pwm_fan_ctx *ctx, unsigned long 
pwm)
struct pwm_state state = { };
 
mutex_lock(>lock);
+
+   if (ctx->enable == 0)
+   pwm = MAX_PWM;
+
if (ctx->pwm_value == pwm)
goto exit_set_pwm_err;
 
@@ -137,11 +142,42 @@ static ssize_t rpm_show(struct device *dev,
return sprintf(buf, "%u\n", ctx->rpm);
 }
 
+static ssize_t enable_store(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   struct pwm_fan_ctx *ctx = dev_get_drvdata(dev);
+   int err;
+   unsigned long val;
+
+   err = kstrtoul(buf, 10, );
+   if (err)
+   return err;
+
+   mutex_lock(>lock);
+   ctx->enable = val;
+   mutex_unlock(>lock);
+
+   err = __set_pwm(ctx, ctx->pwm_fan_cooling_levels[ctx->pwm_fan_state]);
+
+   return err ? err : count;
+}
+
+static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
+  char *buf)
+{
+   struct pwm_fan_ctx *ctx = dev_get_drvdata(dev);
+
+   return sprintf(buf, "%u\n", ctx->enable);
+}
+
 static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
+static SENSOR_DEVICE_ATTR_RW(pwm1_enable, enable, 0);
 static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0);
 
 static struct attribute *pwm_fan_attrs[] = {
_dev_attr_pwm1.dev_attr.attr,
+   _dev_attr_pwm1_enable.dev_attr.attr,
_dev_attr_fan1_input.dev_attr.attr,
NULL,
 };
@@ -153,7 +189,7 @@ static umode_t pwm_fan_attrs_visible(struct kobject *kobj, 
struct attribute *a,
struct pwm_fan_ctx *ctx = dev_get_drvdata(dev);
 
/* Hide fan_input in case no interrupt is available  */
-   if (n == 1 && ctx->irq <= 0)
+   if (n == 2 && ctx->irq <= 0)
return 0;
 
return a->mode;
@@ -200,7 +236,7 @@ static int
 pwm_fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
 {
struct pwm_fan_ctx *ctx = cdev->devdata;
-   int ret;
+   int ret = 0;
 
if (!ctx || (state > ctx->pwm_fan_max_state))
return -EINVAL;
@@ -208,10 +244,12 @@ pwm_fan_set_cur_state(struct thermal_cooling_device 
*cdev, unsigned long state)
if (state == ctx->pwm_fan_state)
return 0;
 
-   ret = __set_pwm(ctx, ctx->pwm_fan_cooling_levels[state]);
-   if (ret) {
-   dev_err(>device, "Cannot set pwm!\n");
-   return ret;
+   if (ctx->enable >= 2) {
+   ret = __set_pwm(ctx, ctx->pwm_fan_cooling_levels[state]);
+   if (ret) {
+   dev_err(>device, "Cannot set pwm!\n");
+   return ret;
+   }
}
 
ctx->pwm_fan_state = state;
@@ -298,6 +336,8 @@ static int pwm_fan_probe(struct platform_device *pdev)
if (IS_ERR(ctx->pwm))
return dev_err_probe(dev, PTR_ERR(ctx->pwm), "Could not get 
PWM\n");
 
+   ctx->enable = 2;
+
platform_set_drvdata(pdev, ctx);
 
ctx->irq = platform_get_irq_optional(pdev, 0);
-- 
2.25.1

[PATCH] thermal: amlogic_thermal: Add hwmon support

[Dongjin Kim]

Expose Amlogic thermal as HWMON devices.

$ sensors
cpu_thermal-virtual-0
Adapter: Virtual device
temp1:+32.2 C  (crit = +110.0 C)

ddr_thermal-virtual-0
Adapter: Virtual device
temp1:+33.4 C  (crit = +110.0 C)

Signed-off-by: Dongjin Kim 
---
 drivers/thermal/amlogic_thermal.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/thermal/amlogic_thermal.c 
b/drivers/thermal/amlogic_thermal.c
index ccb1fe18e993..2fce96c32586 100644
--- a/drivers/thermal/amlogic_thermal.c
+++ b/drivers/thermal/amlogic_thermal.c
@@ -29,6 +29,7 @@
 #include 
 
 #include "thermal_core.h"
+#include "thermal_hwmon.h"
 
 #define TSENSOR_CFG_REG1   0x4
#define TSENSOR_CFG_REG1_RSET_VBG   BIT(12)
@@ -291,6 +292,9 @@ static int amlogic_thermal_probe(struct platform_device 
*pdev)
if (ret)
return ret;
 
+   if (devm_thermal_add_hwmon_sysfs(pdata->tzd))
+   dev_warn(>dev, "failed to add hwmon sysfs attributes\n");
+
ret = amlogic_thermal_enable(pdata);
 
return ret;
-- 
2.25.1

Re: [PATCH 3/3] arm64: dts: meson: add support for the ODROID-N2+

[Dongjin Kim]

Can we use "Hardkernel ODROID-N2Plus" instead of "Hardkernel ODROID-N2+"?

Thanks,
Dongjin.



On Tue, Jul 21, 2020 at 5:24 PM Neil Armstrong  wrote:
>
> On 21/07/2020 10:10, Neil Armstrong wrote:
> > On 19/07/2020 16:10, Christian Hewitt wrote:
> >> HardKernel ODROID-N2+ uses an Amlogic S922X rev. C chip capable of higher
> >> clock speeds than the original ODROID-N2. Hardkernel supports the big cpu
> >> cluster at 2.4GHz and the little cpu cluster at 2.0GHz. Opp points and
> >> regulator changess are from the HardKernel Linux kernel sources.
> >>
> >> Suggested-by: Dongjin Kim 
> >> Signed-off-by: Christian Hewitt 
> >> ---
> >>  arch/arm64/boot/dts/amlogic/Makefile  |  1 +
> >>  .../dts/amlogic/meson-g12b-odroid-n2-plus.dts | 53 +++
> >>  2 files changed, 54 insertions(+)
> >>  create mode 100644 
> >> arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
> >>
> >> diff --git a/arch/arm64/boot/dts/amlogic/Makefile 
> >> b/arch/arm64/boot/dts/amlogic/Makefile
> >> index 5cac4d1d487d..6dc508b80133 100644
> >> --- a/arch/arm64/boot/dts/amlogic/Makefile
> >> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> >> @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb
> >>  dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb
> >>  dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb
> >>  dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb
> >> +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb
> >>  dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb
> >>  dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb
> >>  dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts 
> >> b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
> >> new file mode 100644
> >> index ..99e96be509f8
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
> >> @@ -0,0 +1,53 @@
> >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >> +/*
> >> + * Copyright (c) 2019 BayLibre, SAS
> >> + * Author: Neil Armstrong 
> >> + */
> >> +
> >> +/dts-v1/;
> >> +
> >> +#include "meson-g12b-odroid-n2.dtsi"
> >> +
> >> +/ {
> >> +compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", 
> >> "amlogic,g12b";
> >> +model = "Hardkernel ODROID-N2+";
> >> +
> >> +vddcpu_a: regulator-vddcpu-a {
> >> +regulator-min-microvolt = <68>;
> >> +regulator-max-microvolt = <104>;
> >> +
> >> +pwms = <_ab 0 1500 0>;
> >> +};
> >> +
> >> +vddcpu_b: regulator-vddcpu-b {
> >> +regulator-min-microvolt = <68>;
> >> +regulator-max-microvolt = <104>;
> >> +
> >> +pwms = <_AO_cd 1 1500 0>;
> >> +};
> >> +
> >> +cpu_opp_table_0: opp-table-0 {
> >> +opp-190800 {
> >> +opp-hz = /bits/ 64 <190800>;
> >> +opp-microvolt = <103>;
> >> +};
> >> +
> >> +opp-201600 {
> >> +opp-hz = /bits/ 64 <201600>;
> >> +opp-microvolt = <104>;
> >> +};
> >> +};
> >> +
> >> +cpub_opp_table_1: opp-table-1 {
> >> +opp-230400 {
> >> +opp-hz = /bits/ 64 <230400>;
> >> +opp-microvolt = <103>;
> >> +};
> >> +
> >> +opp-24 {
> >> +opp-hz = /bits/ 64 <24>;
> >> +opp-microvolt = <104>;
> >> +};
> >> +};
> >> +};
> >> +
> >>
> > Reviewed-by: Neil Armstrong 
> >
>
> Wait no, it should be:
>
> / {
> compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", 
> "amlogic,g12b";
> model = "Hardkernel ODROID-N2+";
> };
>
> _a {
> regulator-min-microvolt = <68>;
> regulator-max-microvolt = <104>;
>
> pwms = <_ab 0 1500 0>;
> };
>
> _b {
> regulator-min-microvolt = <68>;
> regulator-max-microvolt = <104>;
>
> pwms = <_AO_cd 1 1500 0>;
> };
>
> _opp_table_0 {
> opp-190800 {
> opp-hz = /bits/ 64 <190800>;
> opp-microvolt = <103>;
> };
>
> opp-201600 {
> opp-hz = /bits/ 64 <201600>;
> opp-microvolt = <104>;
> };
> };
>
> _opp_table_1 {
> opp-230400 {
> opp-hz = /bits/ 64 <230400>;
> opp-microvolt = <103>;
> };
>
> opp-24 {
> opp-hz = /bits/ 64 <24>;
> opp-microvolt = <104>;
> };
> };
>
> Neil
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[REBASED PATCH] ARM: dts: exynos: fix property values of LDO15/17 for ODROID-XU3/4

[Dongjin Kim]

Looking at the schematic, LDO15 and LDO17 are tied as a power source of a
builtin network chipset. The voltage on LDO15 is corrected to 3.3V and the
name of LDO17 is corrected to "vdd_ldo17".

Signed-off-by: Dongjin Kim <tobet...@gmail.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi 
b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index a5b8d0f0877e..81cbb77204a8 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -233,8 +233,8 @@
 
ldo15_reg: LDO15 {
regulator-name = "vdd_ldo15";
-   regulator-min-microvolt = <310>;
-   regulator-max-microvolt = <310>;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
regulator-always-on;
};
 
@@ -246,7 +246,7 @@
};
 
ldo17_reg: LDO17 {
-   regulator-name = "tsp_avdd";
+   regulator-name = "vdd_ldo17";
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-always-on;
-- 
2.11.0

[REBASED PATCH] ARM: dts: exynos: fix property values of LDO15/17 for ODROID-XU3/4

[Dongjin Kim]

Looking at the schematic, LDO15 and LDO17 are tied as a power source of a
builtin network chipset. The voltage on LDO15 is corrected to 3.3V and the
name of LDO17 is corrected to "vdd_ldo17".

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi 
b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index a5b8d0f0877e..81cbb77204a8 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -233,8 +233,8 @@
 
ldo15_reg: LDO15 {
regulator-name = "vdd_ldo15";
-   regulator-min-microvolt = <310>;
-   regulator-max-microvolt = <310>;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
regulator-always-on;
};
 
@@ -246,7 +246,7 @@
};
 
ldo17_reg: LDO17 {
-   regulator-name = "tsp_avdd";
+   regulator-name = "vdd_ldo17";
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
regulator-always-on;
-- 
2.11.0

[PATCH] ARM: exynos: add machine description for ODROID-XU3/4

[Dongjin Kim]

This patch is to add the machine descriptions for ODROID-XU3/4 boards
in order to present the hardware name at /proc/cputinfo rather than
"SAMSUNG EXYNOS (Flattened Device Tree)". An embedded open source project,
such as DietPi, reads the hardware name to run different features.

$ cat /proc/cpuinfo | grep Hardware
Hardware: ODROID-XU4

Signed-off-by: Dongjin Kim <tobet...@gmail.com>
---
 arch/arm/mach-exynos/exynos.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c404c15ad07f..6197dbf9f48b 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -241,3 +241,31 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened 
Device Tree)")
.dt_compat  = exynos_dt_compat,
.dt_fixup   = exynos_dt_fixup,
 MACHINE_END
+
+#define ODROID_MACHINE_START(name, compat) \
+   DT_MACHINE_START(EXYNOS5422_ODROID_##name, "ODROID-"#name)  \
+   .l2c_aux_val= 0x3c41,   \
+   .l2c_aux_mask   = 0xc20f,   \
+   .smp= smp_ops(exynos_smp_ops),  \
+   .map_io = exynos_init_io,   \
+   .init_early = exynos_firmware_init, \
+   .init_irq   = exynos_init_irq,  \
+   .init_machine   = exynos_dt_machine_init,   \
+   .init_late  = exynos_init_late, \
+   .dt_compat  = compat,   \
+   .dt_fixup   = exynos_dt_fixup,  \
+   MACHINE_END
+
+static char const *const exynos5422_odroidxu3_dt_compat[] __initconst = {
+   "hardkernel,odroid-xu3",
+   "hardkernel,odroid-xu3-lite",
+   NULL,
+};
+
+static char const *const exynos5422_odroidxu4_dt_compat[] __initconst = {
+   "hardkernel,odroid-xu4",
+   NULL,
+};
+
+ODROID_MACHINE_START(XU3, exynos5422_odroidxu3_dt_compat)
+ODROID_MACHINE_START(XU4, exynos5422_odroidxu4_dt_compat)
-- 
2.11.0

[PATCH] ARM: exynos: add machine description for ODROID-XU3/4

[Dongjin Kim]

This patch is to add the machine descriptions for ODROID-XU3/4 boards
in order to present the hardware name at /proc/cputinfo rather than
"SAMSUNG EXYNOS (Flattened Device Tree)". An embedded open source project,
such as DietPi, reads the hardware name to run different features.

$ cat /proc/cpuinfo | grep Hardware
Hardware: ODROID-XU4

Signed-off-by: Dongjin Kim 
---
 arch/arm/mach-exynos/exynos.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c404c15ad07f..6197dbf9f48b 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -241,3 +241,31 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened 
Device Tree)")
.dt_compat  = exynos_dt_compat,
.dt_fixup   = exynos_dt_fixup,
 MACHINE_END
+
+#define ODROID_MACHINE_START(name, compat) \
+   DT_MACHINE_START(EXYNOS5422_ODROID_##name, "ODROID-"#name)  \
+   .l2c_aux_val= 0x3c41,   \
+   .l2c_aux_mask   = 0xc20f,   \
+   .smp= smp_ops(exynos_smp_ops),  \
+   .map_io = exynos_init_io,   \
+   .init_early = exynos_firmware_init, \
+   .init_irq   = exynos_init_irq,  \
+   .init_machine   = exynos_dt_machine_init,   \
+   .init_late  = exynos_init_late, \
+   .dt_compat  = compat,   \
+   .dt_fixup   = exynos_dt_fixup,  \
+   MACHINE_END
+
+static char const *const exynos5422_odroidxu3_dt_compat[] __initconst = {
+   "hardkernel,odroid-xu3",
+   "hardkernel,odroid-xu3-lite",
+   NULL,
+};
+
+static char const *const exynos5422_odroidxu4_dt_compat[] __initconst = {
+   "hardkernel,odroid-xu4",
+   NULL,
+};
+
+ODROID_MACHINE_START(XU3, exynos5422_odroidxu3_dt_compat)
+ODROID_MACHINE_START(XU4, exynos5422_odroidxu4_dt_compat)
-- 
2.11.0

[PATCH] ARM: dts: add clock provider for mshc in Exynos4412

[Dongjin Kim]

Add clock lookup information for mshc in Exynos4412.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4412.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
b/arch/arm/boot/dts/exynos4412.dtsi
index e743e67..67bef99 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -67,5 +67,7 @@
interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
+   clocks = < 301>, < 149>;
+   clock-names = "biu", "ciu";
};
 };
-- 
1.8.1.2

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[PATCH] ARM: dts: add clock provider for mshc in Exynos4412

[Dongjin Kim]

Add clock lookup information for mshc in Exynos4412.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4412.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
b/arch/arm/boot/dts/exynos4412.dtsi
index e743e67..67bef99 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -67,5 +67,7 @@
interrupts = 0 77 0;
#address-cells = 1;
#size-cells = 0;
+   clocks = clock 301, clock 149;
+   clock-names = biu, ciu;
};
 };
-- 
1.8.1.2

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Re: usb: misc: usb3503: connect and intn mismatch in OF vs variable assignments

[Dongjin Kim]

Hi,

The patch is submitted by Mark Brown a week ago, and might be queued already.

[1] http://www.spinics.net/lists/linux-usb/msg91410.html

Thanks,
Dongjin.

On Fri, Aug 16, 2013 at 5:53 PM, Alban Browaeys  wrote:
> hub->gpio_intn  = of_get_named_gpio(np, "connect-gpios", 0);
> and
> hub->gpio_connect = of_get_named_gpio(np, "intn-gpios", 0);
>
> I guess they should be switched , that is connect-gpios bound to 
> hub->gpio_connect
> and intn-gpios to hub->gpio_int.
>
> Sorry not to provides a patch. I thought that this issue might ends up with 
> dts relying
> on this broken behaviour if not pointed early ...
> Either way if not fixed soon , I will have completed my branch cleanup (I 
> also have other patches
> to this file ie drivers/usb/misc/usb3503.c).
>
> Best regards
> Alban
>
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Re: usb: misc: usb3503: connect and intn mismatch in OF vs variable assignments

[Dongjin Kim]

Hi,

The patch is submitted by Mark Brown a week ago, and might be queued already.

[1] http://www.spinics.net/lists/linux-usb/msg91410.html

Thanks,
Dongjin.

On Fri, Aug 16, 2013 at 5:53 PM, Alban Browaeys pra...@yahoo.com wrote:
 hub-gpio_intn  = of_get_named_gpio(np, connect-gpios, 0);
 and
 hub-gpio_connect = of_get_named_gpio(np, intn-gpios, 0);

 I guess they should be switched , that is connect-gpios bound to 
 hub-gpio_connect
 and intn-gpios to hub-gpio_int.

 Sorry not to provides a patch. I thought that this issue might ends up with 
 dts relying
 on this broken behaviour if not pointed early ...
 Either way if not fixed soon , I will have completed my branch cleanup (I 
 also have other patches
 to this file ie drivers/usb/misc/usb3503.c).

 Best regards
 Alban

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[RESEND PATCH v2] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

This patch adds device nodes for USBPHY to Exynos4x12.

Signed-off-by: Dongjin Kim 
Cc: Tomasz Figa 
Cc: Kyungmin Park 
---
* Changes from v1
  o. 'status = "disabled"' is removed to probe as default

 arch/arm/boot/dts/exynos4x12.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
b/arch/arm/boot/dts/exynos4x12.dtsi
index 01da194..3ee6102 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -73,4 +73,21 @@
clock-names = "sclk_fimg2d", "fimg2d";
status = "disabled";
};
+
+   usbphy@125B0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "samsung,exynos4x12-usb2phy";
+   reg = <0x125B 0x100>;
+   ranges;
+
+   clocks = < 2>, < 305>;
+   clock-names = "xusbxti", "otg";
+
+   usbphy-sys {
+   /* USB device and host PHY_CONTROL registers */
+   reg = <0x10020704 0xc>,
+ <0x1001021c 0x4>;
+   };
+   };
 };
-- 
1.7.9.5

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[RESEND PATCH v2] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

This patch adds device nodes for USBPHY to Exynos4x12.

Signed-off-by: Dongjin Kim tobet...@gmail.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
---
* Changes from v1
  o. 'status = disabled' is removed to probe as default

 arch/arm/boot/dts/exynos4x12.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
b/arch/arm/boot/dts/exynos4x12.dtsi
index 01da194..3ee6102 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -73,4 +73,21 @@
clock-names = sclk_fimg2d, fimg2d;
status = disabled;
};
+
+   usbphy@125B0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = samsung,exynos4x12-usb2phy;
+   reg = 0x125B 0x100;
+   ranges;
+
+   clocks = clock 2, clock 305;
+   clock-names = xusbxti, otg;
+
+   usbphy-sys {
+   /* USB device and host PHY_CONTROL registers */
+   reg = 0x10020704 0xc,
+ 0x1001021c 0x4;
+   };
+   };
 };
-- 
1.7.9.5

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Re: [PATCH RESEND] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

Aha, yes...my misunderstanding.
This node is not only for OTG or HSIC, could miss USB HOST transceiver
if certain board file does not set "okay".

Thanks,
Dongjin.

On Tue, Aug 6, 2013 at 3:09 PM, Sachin Kamat  wrote:
> Hi Dongjin,
>
> On 5 August 2013 23:48, Dongjin Kim  wrote:
>> This patch adds device nodes for USBPHY to Exynos4x12.
>>
>> CC: Sachin Kamat 
>> Signed-off-by: Dongjin Kim 
>> ---
>>  arch/arm/boot/dts/exynos4x12.dtsi |   18 ++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
>> b/arch/arm/boot/dts/exynos4x12.dtsi
>> index 01da194..9c3335b 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -73,4 +73,22 @@
>> clock-names = "sclk_fimg2d", "fimg2d";
>> status = "disabled";
>> };
>> +
>> +   usbphy@125B0 {
>> +   #address-cells = <1>;
>> +   #size-cells = <1>;
>> +   compatible = "samsung,exynos4x12-usb2phy";
>> +   reg = <0x125B 0x100>;
>> +   ranges;
>> +
>> +   clocks = < 2>, < 305>;
>> +   clock-names = "xusbxti", "otg";
>> +   status = "disabled";
>
> I don't think this node has any other board specific dependencies. In
> that case you don't need to disable this.
>
>> +
>> +   usbphy-sys {
>> +   /* USB device and host PHY_CONTROL registers */
>> +   reg = <0x10020704 0xc>,
>> + <0x1001021c 0x4>;
>> +   };
>> +   };
>>  };
>> --
>> 1.7.9.5
>>
>
>
>
> --
> With warm regards,
> Sachin
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Re: [PATCH RESEND] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

Aha, yes...my misunderstanding.
This node is not only for OTG or HSIC, could miss USB HOST transceiver
if certain board file does not set okay.

Thanks,
Dongjin.

On Tue, Aug 6, 2013 at 3:09 PM, Sachin Kamat sachin.ka...@linaro.org wrote:
 Hi Dongjin,

 On 5 August 2013 23:48, Dongjin Kim tobet...@gmail.com wrote:
 This patch adds device nodes for USBPHY to Exynos4x12.

 CC: Sachin Kamat sachin.ka...@linaro.org
 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  arch/arm/boot/dts/exynos4x12.dtsi |   18 ++
  1 file changed, 18 insertions(+)

 diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
 b/arch/arm/boot/dts/exynos4x12.dtsi
 index 01da194..9c3335b 100644
 --- a/arch/arm/boot/dts/exynos4x12.dtsi
 +++ b/arch/arm/boot/dts/exynos4x12.dtsi
 @@ -73,4 +73,22 @@
 clock-names = sclk_fimg2d, fimg2d;
 status = disabled;
 };
 +
 +   usbphy@125B0 {
 +   #address-cells = 1;
 +   #size-cells = 1;
 +   compatible = samsung,exynos4x12-usb2phy;
 +   reg = 0x125B 0x100;
 +   ranges;
 +
 +   clocks = clock 2, clock 305;
 +   clock-names = xusbxti, otg;
 +   status = disabled;

 I don't think this node has any other board specific dependencies. In
 that case you don't need to disable this.

 +
 +   usbphy-sys {
 +   /* USB device and host PHY_CONTROL registers */
 +   reg = 0x10020704 0xc,
 + 0x1001021c 0x4;
 +   };
 +   };
  };
 --
 1.7.9.5




 --
 With warm regards,
 Sachin
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[PATCH RESEND] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

This patch adds device nodes for USBPHY to Exynos4x12.

CC: Sachin Kamat 
Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4x12.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
b/arch/arm/boot/dts/exynos4x12.dtsi
index 01da194..9c3335b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -73,4 +73,22 @@
clock-names = "sclk_fimg2d", "fimg2d";
status = "disabled";
};
+
+   usbphy@125B0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "samsung,exynos4x12-usb2phy";
+   reg = <0x125B 0x100>;
+   ranges;
+
+   clocks = < 2>, < 305>;
+   clock-names = "xusbxti", "otg";
+   status = "disabled";
+
+   usbphy-sys {
+   /* USB device and host PHY_CONTROL registers */
+   reg = <0x10020704 0xc>,
+ <0x1001021c 0x4>;
+   };
+   };
 };
-- 
1.7.9.5

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[PATCH RESEND] ARM: dts: Add USB host node for Exynos4

[Dongjin Kim]

This patch adds EHCI and OHCI host device nodes for Exynos4.

CC: Jingoo Han 
Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3f94fe8..cbe5219 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -155,6 +155,24 @@
status = "disabled";
};
 
+   ehci@1258 {
+   compatible = "samsung,exynos4210-ehci";
+   reg = <0x1258 0x100>;
+   interrupts = <0 70 0>;
+   clocks = < 304>;
+   clock-names = "usbhost";
+   status = "disabled";
+   };
+
+   ohci@1259 {
+   compatible = "samsung,exynos4210-ohci";
+   reg = <0x1259 0x100>;
+   interrupts = <0 70 0>;
+   clocks = < 304>;
+   clock-names = "usbhost";
+   status = "disabled";
+   };
+
mfc: codec@1340 {
compatible = "samsung,mfc-v5";
reg = <0x1340 0x1>;
-- 
1.7.9.5

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[PATCH RESEND] ARM: dts: Add USB host node for Exynos4

[Dongjin Kim]

This patch adds EHCI and OHCI host device nodes for Exynos4.

CC: Jingoo Han jg1@samsung.com
Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3f94fe8..cbe5219 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -155,6 +155,24 @@
status = disabled;
};
 
+   ehci@1258 {
+   compatible = samsung,exynos4210-ehci;
+   reg = 0x1258 0x100;
+   interrupts = 0 70 0;
+   clocks = clock 304;
+   clock-names = usbhost;
+   status = disabled;
+   };
+
+   ohci@1259 {
+   compatible = samsung,exynos4210-ohci;
+   reg = 0x1259 0x100;
+   interrupts = 0 70 0;
+   clocks = clock 304;
+   clock-names = usbhost;
+   status = disabled;
+   };
+
mfc: codec@1340 {
compatible = samsung,mfc-v5;
reg = 0x1340 0x1;
-- 
1.7.9.5

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[PATCH RESEND] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

This patch adds device nodes for USBPHY to Exynos4x12.

CC: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4x12.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
b/arch/arm/boot/dts/exynos4x12.dtsi
index 01da194..9c3335b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -73,4 +73,22 @@
clock-names = sclk_fimg2d, fimg2d;
status = disabled;
};
+
+   usbphy@125B0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = samsung,exynos4x12-usb2phy;
+   reg = 0x125B 0x100;
+   ranges;
+
+   clocks = clock 2, clock 305;
+   clock-names = xusbxti, otg;
+   status = disabled;
+
+   usbphy-sys {
+   /* USB device and host PHY_CONTROL registers */
+   reg = 0x10020704 0xc,
+ 0x1001021c 0x4;
+   };
+   };
 };
-- 
1.7.9.5

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Re: [PATCH 1/2] ARM: dts: Add USB Host nodes to Exynos4210

[Dongjin Kim]

Hi Jingoo,

I had submitted another patch almost similar contents, but my patch
contains both EHCI and OHCI USB host devices node in exynos4.dtsi
since I had tested on Exynos4412 and their register map are same with
Exynos4210.

[1] https://patchwork.kernel.org/patch/2832779

On Wed, May 29, 2013 at 6:47 PM, Jingoo Han  wrote:
> Add device nodes for USB Host EHCI and OHCI controllers to Exynos4210.
>
> Signed-off-by: Jingoo Han 
> ---
> Tested on Exynos4210.
>
>  arch/arm/boot/dts/exynos4210.dtsi |   18 ++
>  1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
> b/arch/arm/boot/dts/exynos4210.dtsi
> index 366795a..3c173c7 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -117,6 +117,24 @@
> status = "disabled";
> };
>
> +   usb@1258 {
> +   compatible = "samsung,exynos4210-ehci";
> +   reg = <0x1258 0x100>;
> +   interrupts = <0 70 0>;
> +
> +   clocks = < 304>;
> +   clock-names = "usbhost";
> +   };
> +
> +   usb@1259 {
> +   compatible = "samsung,exynos4210-ohci";
> +   reg = <0x1259 0x100>;
> +   interrupts = <0 70 0>;
> +
> +   clocks = < 304>;
> +   clock-names = "usbhost";
> +   };
> +
> g2d@1280 {
> compatible = "samsung,s5pv210-g2d";
> reg = <0x1280 0x1000>;
> --
> 1.7.10.4
>
>
>
> ___
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> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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[PATCH v2] ARM: dts: Add USB host node for Exynos4

[Dongjin Kim]

This patch adds EHCI and OHCI host device nodes for Exynos4.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3f94fe8..cbe5219 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -155,6 +155,24 @@
status = "disabled";
};
 
+   ehci@1258 {
+   compatible = "samsung,exynos4210-ehci";
+   reg = <0x1258 0x100>;
+   interrupts = <0 70 0>;
+   clocks = < 304>;
+   clock-names = "usbhost";
+   status = "disabled";
+   };
+
+   ohci@1259 {
+   compatible = "samsung,exynos4210-ohci";
+   reg = <0x1259 0x100>;
+   interrupts = <0 70 0>;
+   clocks = < 304>;
+   clock-names = "usbhost";
+   status = "disabled";
+   };
+
mfc: codec@1340 {
compatible = "samsung,mfc-v5";
reg = <0x1340 0x1>;
-- 
1.7.9.5

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Re: [PATCH] ARM: dts: Add USB host node for Exynos4

[Dongjin Kim]

+Jingoo Han

Sorry, its my bad. Typo problem.

I found another patch same with mine,
https://patchwork.kernel.org/patch/2628451, submitted by Jingoo Han
and tested on Exynos4210. Mine is tested on Exynos4412. Both SoC have
same USB host address space, so I think USB host device nodes can be
placed in exynos4.dtsi.

Regards,
Dongjin.

On Wed, Jul 24, 2013 at 12:38 PM, Sachin Kamat  wrote:
> On 23 July 2013 23:02, Dongjin Kim  wrote:
>> This patch adds EHCI and OHCI host device nodes for Exynos4.
>>
>> Signed-off-by: Dongjin Kim 
>> ---
>>  arch/arm/boot/dts/exynos4.dtsi |   20 
>>  1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
>> index 3f94fe8..1cdbf89 100644
>> --- a/arch/arm/boot/dts/exynos4.dtsi
>> +++ b/arch/arm/boot/dts/exynos4.dtsi
>> @@ -155,6 +155,26 @@
>> status = "disabled";
>> };
>>
>> +   ehci@1258 {
>> +   compatible = "samsung,exynos4210-ehci";
>> +   reg = <0x1258 0x100>;
>> +   interrupts = <0 70 0>;
>> +   status = "disabled";
>> +
>> +   clocks = < 304>;
>> +   clock-names = "usbhost";
>> +   };
>> +
>> +   ohci@1259 {
>> +   compatible = "samsung,exynos4210-ohci";
>> +   reg = <0x1258 0x100>;
>
> Register value and node name do not match. Typo?
>
>
>> +   interrupts = <0 70 0>;
>> +   status = "disabled";
>> +
>> +   clocks = < 304>;
>> +   clock-names = "usbhost";
>> +   };
>> +
>> mfc: codec@1340 {
>> compatible = "samsung,mfc-v5";
>> reg = <0x1340 0x1>;
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" 
>> in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> With warm regards,
> Sachin
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Re: [PATCH] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

Thanks Sachin,

On Wed, Jul 24, 2013 at 2:12 PM, Sachin Kamat  wrote:
> Hi Dongjin,
>
> On 23 July 2013 23:01, Dongjin Kim  wrote:
>> This patch adds device nodes for USBPHY to Exynos4x12.
>>
>> Signed-off-by: Dongjin Kim 
>> ---
>>  arch/arm/boot/dts/exynos4x12.dtsi |   18 ++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
>> b/arch/arm/boot/dts/exynos4x12.dtsi
>> index 01da194..9c3335b 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -73,4 +73,22 @@
>> clock-names = "sclk_fimg2d", "fimg2d";
>> status = "disabled";
>> };
>> +
>> +   usbphy@125B0 {
>
> Extra 0 above.
>
This is my bad, I will fix.

>> +   #address-cells = <1>;
>> +   #size-cells = <1>;
>> +   compatible = "samsung,exynos4x12-usb2phy";
>> +   reg = <0x125B 0x100>;
>> +   ranges;
>> +
>> +   clocks = < 2>, < 305>;
>> +   clock-names = "xusbxti", "otg";
>> +   status = "disabled";
>> +
>> +   usbphy-sys {
>> +   /* USB device and host PHY_CONTROL registers */
>> +   reg = <0x10020704 0xc>,
>> + <0x1001021c 0x4>;
>> +   };
>> +   };
>>  };
>
> Please add this node after tmu node (satisfies alphabetical order as
> well as increasing address value)
No tmu node in exynos4x12.dtsi in mainline v3.11-rc2 yet, even in
Kukjin's branch.

>
>
> --
> With warm regards,
> Sachin
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Re: [PATCH] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

Thanks Sachin,

On Wed, Jul 24, 2013 at 2:12 PM, Sachin Kamat sachin.ka...@linaro.org wrote:
 Hi Dongjin,

 On 23 July 2013 23:01, Dongjin Kim tobet...@gmail.com wrote:
 This patch adds device nodes for USBPHY to Exynos4x12.

 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  arch/arm/boot/dts/exynos4x12.dtsi |   18 ++
  1 file changed, 18 insertions(+)

 diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
 b/arch/arm/boot/dts/exynos4x12.dtsi
 index 01da194..9c3335b 100644
 --- a/arch/arm/boot/dts/exynos4x12.dtsi
 +++ b/arch/arm/boot/dts/exynos4x12.dtsi
 @@ -73,4 +73,22 @@
 clock-names = sclk_fimg2d, fimg2d;
 status = disabled;
 };
 +
 +   usbphy@125B0 {

 Extra 0 above.

This is my bad, I will fix.

 +   #address-cells = 1;
 +   #size-cells = 1;
 +   compatible = samsung,exynos4x12-usb2phy;
 +   reg = 0x125B 0x100;
 +   ranges;
 +
 +   clocks = clock 2, clock 305;
 +   clock-names = xusbxti, otg;
 +   status = disabled;
 +
 +   usbphy-sys {
 +   /* USB device and host PHY_CONTROL registers */
 +   reg = 0x10020704 0xc,
 + 0x1001021c 0x4;
 +   };
 +   };
  };

 Please add this node after tmu node (satisfies alphabetical order as
 well as increasing address value)
No tmu node in exynos4x12.dtsi in mainline v3.11-rc2 yet, even in
Kukjin's branch.



 --
 With warm regards,
 Sachin
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Re: [PATCH] ARM: dts: Add USB host node for Exynos4

[Dongjin Kim]

+Jingoo Han

Sorry, its my bad. Typo problem.

I found another patch same with mine,
https://patchwork.kernel.org/patch/2628451, submitted by Jingoo Han
and tested on Exynos4210. Mine is tested on Exynos4412. Both SoC have
same USB host address space, so I think USB host device nodes can be
placed in exynos4.dtsi.

Regards,
Dongjin.

On Wed, Jul 24, 2013 at 12:38 PM, Sachin Kamat sachin.ka...@linaro.org wrote:
 On 23 July 2013 23:02, Dongjin Kim tobet...@gmail.com wrote:
 This patch adds EHCI and OHCI host device nodes for Exynos4.

 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  arch/arm/boot/dts/exynos4.dtsi |   20 
  1 file changed, 20 insertions(+)

 diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
 index 3f94fe8..1cdbf89 100644
 --- a/arch/arm/boot/dts/exynos4.dtsi
 +++ b/arch/arm/boot/dts/exynos4.dtsi
 @@ -155,6 +155,26 @@
 status = disabled;
 };

 +   ehci@1258 {
 +   compatible = samsung,exynos4210-ehci;
 +   reg = 0x1258 0x100;
 +   interrupts = 0 70 0;
 +   status = disabled;
 +
 +   clocks = clock 304;
 +   clock-names = usbhost;
 +   };
 +
 +   ohci@1259 {
 +   compatible = samsung,exynos4210-ohci;
 +   reg = 0x1258 0x100;

 Register value and node name do not match. Typo?


 +   interrupts = 0 70 0;
 +   status = disabled;
 +
 +   clocks = clock 304;
 +   clock-names = usbhost;
 +   };
 +
 mfc: codec@1340 {
 compatible = samsung,mfc-v5;
 reg = 0x1340 0x1;
 --
 1.7.9.5

 --
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 in
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 --
 With warm regards,
 Sachin
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[PATCH v2] ARM: dts: Add USB host node for Exynos4

[Dongjin Kim]

This patch adds EHCI and OHCI host device nodes for Exynos4.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3f94fe8..cbe5219 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -155,6 +155,24 @@
status = disabled;
};
 
+   ehci@1258 {
+   compatible = samsung,exynos4210-ehci;
+   reg = 0x1258 0x100;
+   interrupts = 0 70 0;
+   clocks = clock 304;
+   clock-names = usbhost;
+   status = disabled;
+   };
+
+   ohci@1259 {
+   compatible = samsung,exynos4210-ohci;
+   reg = 0x1259 0x100;
+   interrupts = 0 70 0;
+   clocks = clock 304;
+   clock-names = usbhost;
+   status = disabled;
+   };
+
mfc: codec@1340 {
compatible = samsung,mfc-v5;
reg = 0x1340 0x1;
-- 
1.7.9.5

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Re: [PATCH 1/2] ARM: dts: Add USB Host nodes to Exynos4210

[Dongjin Kim]

Hi Jingoo,

I had submitted another patch almost similar contents, but my patch
contains both EHCI and OHCI USB host devices node in exynos4.dtsi
since I had tested on Exynos4412 and their register map are same with
Exynos4210.

[1] https://patchwork.kernel.org/patch/2832779

On Wed, May 29, 2013 at 6:47 PM, Jingoo Han jg1@samsung.com wrote:
 Add device nodes for USB Host EHCI and OHCI controllers to Exynos4210.

 Signed-off-by: Jingoo Han jg1@samsung.com
 ---
 Tested on Exynos4210.

  arch/arm/boot/dts/exynos4210.dtsi |   18 ++
  1 file changed, 18 insertions(+)

 diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
 b/arch/arm/boot/dts/exynos4210.dtsi
 index 366795a..3c173c7 100644
 --- a/arch/arm/boot/dts/exynos4210.dtsi
 +++ b/arch/arm/boot/dts/exynos4210.dtsi
 @@ -117,6 +117,24 @@
 status = disabled;
 };

 +   usb@1258 {
 +   compatible = samsung,exynos4210-ehci;
 +   reg = 0x1258 0x100;
 +   interrupts = 0 70 0;
 +
 +   clocks = clock 304;
 +   clock-names = usbhost;
 +   };
 +
 +   usb@1259 {
 +   compatible = samsung,exynos4210-ohci;
 +   reg = 0x1259 0x100;
 +   interrupts = 0 70 0;
 +
 +   clocks = clock 304;
 +   clock-names = usbhost;
 +   };
 +
 g2d@1280 {
 compatible = samsung,s5pv210-g2d;
 reg = 0x1280 0x1000;
 --
 1.7.10.4



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[PATCH] ARM: dts: Add USB host node for Exynos4

[Dongjin Kim]

This patch adds EHCI and OHCI host device nodes for Exynos4.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4.dtsi |   20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3f94fe8..1cdbf89 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -155,6 +155,26 @@
status = "disabled";
};
 
+   ehci@1258 {
+   compatible = "samsung,exynos4210-ehci";
+   reg = <0x1258 0x100>;
+   interrupts = <0 70 0>;
+   status = "disabled";
+
+   clocks = < 304>;
+   clock-names = "usbhost";
+   };
+
+   ohci@1259 {
+   compatible = "samsung,exynos4210-ohci";
+   reg = <0x1258 0x100>;
+   interrupts = <0 70 0>;
+   status = "disabled";
+
+   clocks = < 304>;
+   clock-names = "usbhost";
+   };
+
mfc: codec@1340 {
compatible = "samsung,mfc-v5";
reg = <0x1340 0x1>;
-- 
1.7.9.5

--
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[PATCH] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

This patch adds device nodes for USBPHY to Exynos4x12.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4x12.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
b/arch/arm/boot/dts/exynos4x12.dtsi
index 01da194..9c3335b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -73,4 +73,22 @@
clock-names = "sclk_fimg2d", "fimg2d";
status = "disabled";
};
+
+   usbphy@125B0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "samsung,exynos4x12-usb2phy";
+   reg = <0x125B 0x100>;
+   ranges;
+
+   clocks = < 2>, < 305>;
+   clock-names = "xusbxti", "otg";
+   status = "disabled";
+
+   usbphy-sys {
+   /* USB device and host PHY_CONTROL registers */
+   reg = <0x10020704 0xc>,
+ <0x1001021c 0x4>;
+   };
+   };
 };
-- 
1.7.9.5

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[PATCH] ARM: dts: Add USBPHY nodes to Exynos4x12

[Dongjin Kim]

This patch adds device nodes for USBPHY to Exynos4x12.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4x12.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
b/arch/arm/boot/dts/exynos4x12.dtsi
index 01da194..9c3335b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -73,4 +73,22 @@
clock-names = sclk_fimg2d, fimg2d;
status = disabled;
};
+
+   usbphy@125B0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = samsung,exynos4x12-usb2phy;
+   reg = 0x125B 0x100;
+   ranges;
+
+   clocks = clock 2, clock 305;
+   clock-names = xusbxti, otg;
+   status = disabled;
+
+   usbphy-sys {
+   /* USB device and host PHY_CONTROL registers */
+   reg = 0x10020704 0xc,
+ 0x1001021c 0x4;
+   };
+   };
 };
-- 
1.7.9.5

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[PATCH] ARM: dts: Add USB host node for Exynos4

[Dongjin Kim]

This patch adds EHCI and OHCI host device nodes for Exynos4.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4.dtsi |   20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3f94fe8..1cdbf89 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -155,6 +155,26 @@
status = disabled;
};
 
+   ehci@1258 {
+   compatible = samsung,exynos4210-ehci;
+   reg = 0x1258 0x100;
+   interrupts = 0 70 0;
+   status = disabled;
+
+   clocks = clock 304;
+   clock-names = usbhost;
+   };
+
+   ohci@1259 {
+   compatible = samsung,exynos4210-ohci;
+   reg = 0x1258 0x100;
+   interrupts = 0 70 0;
+   status = disabled;
+
+   clocks = clock 304;
+   clock-names = usbhost;
+   };
+
mfc: codec@1340 {
compatible = samsung,mfc-v5;
reg = 0x1340 0x1;
-- 
1.7.9.5

--
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[PATCH] ARM: dts: add vmmc regulator support for ODROID-X

[Dongjin Kim]

This patch is to add vmmc regulator node at MSHC and SDHCI for ODROID-X
board file.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 1786225..3f3d7c8 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -44,6 +44,7 @@
pinctrl-0 = <_clk _cmd _bus4 _bus8>;
pinctrl-names = "default";
status = "okay";
+   vmmc-supply = <_reg _reg>;
 
num-slots = <1>;
supports-highspeed;
@@ -78,6 +79,7 @@
bus-width = <4>;
pinctrl-0 = <_clk _cmd _cd _bus4>;
pinctrl-names = "default";
+   vmmc-supply = <_reg _reg>;
status = "okay";
};
 
-- 
1.7.9.5

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[PATCH] ARM: dts: add vmmc regulator support for ODROID-X

[Dongjin Kim]

This patch is to add vmmc regulator node at MSHC and SDHCI for ODROID-X
board file.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 1786225..3f3d7c8 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -44,6 +44,7 @@
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
status = okay;
+   vmmc-supply = ldo20_reg buck8_reg;
 
num-slots = 1;
supports-highspeed;
@@ -78,6 +79,7 @@
bus-width = 4;
pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
pinctrl-names = default;
+   vmmc-supply = ldo4_reg ldo21_reg;
status = okay;
};
 
-- 
1.7.9.5

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Re: [PATCH 1/3] usb: misc: usb3503: Fix up whitespace

[Dongjin Kim]

Signed-off-by: Dongjin Kim 

On Sat, Jun 1, 2013 at 10:34 AM, Julius Werner  wrote:
> Remove an erroneous tab that should be a space.
>
> Signed-off-by: Julius Werner 
> ---
>  drivers/usb/misc/usb3503.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
> index d3a1cce..73aeb87 100644
> --- a/drivers/usb/misc/usb3503.c
> +++ b/drivers/usb/misc/usb3503.c
> @@ -208,7 +208,7 @@ static int usb3503_probe(struct i2c_client *i2c, const 
> struct i2c_device_id *id)
> hub->gpio_connect = of_get_named_gpio(np, "intn-gpios", 0);
> if (hub->gpio_connect == -EPROBE_DEFER)
> return -EPROBE_DEFER;
> -   hub->gpio_reset = of_get_named_gpio(np, "reset-gpios", 0);
> +   hub->gpio_reset = of_get_named_gpio(np, "reset-gpios", 0);
> if (hub->gpio_reset == -EPROBE_DEFER)
> return -EPROBE_DEFER;
> of_property_read_u32(np, "initial-mode", );
> --
> 1.7.12.4
>
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Re: [PATCH 3/3] usb: misc: usb3503: Remove 100ms sleep on reset, conform to data sheet

[Dongjin Kim]

Signed-off-by: Dongjin Kim 

On Sat, Jun 1, 2013 at 10:34 AM, Julius Werner  wrote:
> The usb3503 driver sleeps a flat 100ms when resetting the chip, with a
> comment about waiting for the reference clock. This seems to be a
> board-specific detail that should not hold up boot across all platforms.
> This patch reduces the sleep to the 4ms initialization delay that the
> chip itself actually requires (as per its data sheet). If certain boards
> require more time to set up the reference clock, they should change this
> through local patches or add a proper, configurable synchronization
> mechanism.
>
> Signed-off-by: Julius Werner 
> ---
>  drivers/usb/misc/usb3503.c | 6 ++
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
> index a647a2e..a1d509f 100644
> --- a/drivers/usb/misc/usb3503.c
> +++ b/drivers/usb/misc/usb3503.c
> @@ -107,11 +107,9 @@ static int usb3503_reset(int gpio_reset, int state)
> if (gpio_is_valid(gpio_reset))
> gpio_set_value(gpio_reset, state);
>
> -   /* Wait RefClk when RESET_N is released, otherwise Hub will
> -* not transition to Hub Communication Stage.
> -*/
> +   /* Wait T_HUBINIT == 4ms for hub logic to stabilize */
> if (state)
> -   msleep(100);
> +   usleep_range(4000, 1);
>
> return 0;
>  }
> --
> 1.7.12.4
>
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Re: [PATCH 2/3] usb: misc: usb3503: Remove hardcoded disabling of ports 2 and 3

[Dongjin Kim]

Hi,

I have sent two patches for the same issue, these two are merged into
Greg's tree. Please review the patches.

[1] https://patchwork.kernel.org/patch/2599021
[2] https://patchwork.kernel.org/patch/2599031

Many thanks,
Dongjin.

On Sat, Jun 1, 2013 at 10:34 AM, Julius Werner  wrote:
> The usb3503 driver currently disables port 2 and 3 without explaination.
> It doesn't make sense to do this in a mainline Linux driver that should
> support all platforms which use this chip. If specific use cases really
> require ports to be disabled, this should either be done through local
> patches or a configurable mechanism (such as a device tree property).
> Until then, let's keep all ports enabled.
>
> Signed-off-by: Julius Werner 
> ---
>  drivers/usb/misc/usb3503.c | 8 
>  1 file changed, 8 deletions(-)
>
> diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
> index 73aeb87..a647a2e 100644
> --- a/drivers/usb/misc/usb3503.c
> +++ b/drivers/usb/misc/usb3503.c
> @@ -134,14 +134,6 @@ static int usb3503_switch_mode(struct usb3503 *hub, enum 
> usb3503_mode mode)
> goto err_hubmode;
> }
>
> -   /* PDS : Port2,3 Disable For Self Powered Operation */
> -   err = usb3503_set_bits(i2c, USB3503_PDS,
> -   (USB3503_PORT2 | USB3503_PORT3));
> -   if (err < 0) {
> -   dev_err(>dev, "PDS failed (%d)\n", err);
> -   goto err_hubmode;
> -   }
> -
> /* CFG1 : SELF_BUS_PWR -> Self-Powerd operation */
> err = usb3503_set_bits(i2c, USB3503_CFG1, 
> USB3503_SELF_BUS_PWR);
> if (err < 0) {
> --
> 1.7.12.4
>
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Re: [PATCH 2/3] usb: misc: usb3503: Remove hardcoded disabling of ports 2 and 3

[Dongjin Kim]

Hi,

I have sent two patches for the same issue, these two are merged into
Greg's tree. Please review the patches.

[1] https://patchwork.kernel.org/patch/2599021
[2] https://patchwork.kernel.org/patch/2599031

Many thanks,
Dongjin.

On Sat, Jun 1, 2013 at 10:34 AM, Julius Werner jwer...@chromium.org wrote:
 The usb3503 driver currently disables port 2 and 3 without explaination.
 It doesn't make sense to do this in a mainline Linux driver that should
 support all platforms which use this chip. If specific use cases really
 require ports to be disabled, this should either be done through local
 patches or a configurable mechanism (such as a device tree property).
 Until then, let's keep all ports enabled.

 Signed-off-by: Julius Werner jwer...@chromium.org
 ---
  drivers/usb/misc/usb3503.c | 8 
  1 file changed, 8 deletions(-)

 diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
 index 73aeb87..a647a2e 100644
 --- a/drivers/usb/misc/usb3503.c
 +++ b/drivers/usb/misc/usb3503.c
 @@ -134,14 +134,6 @@ static int usb3503_switch_mode(struct usb3503 *hub, enum 
 usb3503_mode mode)
 goto err_hubmode;
 }

 -   /* PDS : Port2,3 Disable For Self Powered Operation */
 -   err = usb3503_set_bits(i2c, USB3503_PDS,
 -   (USB3503_PORT2 | USB3503_PORT3));
 -   if (err  0) {
 -   dev_err(i2c-dev, PDS failed (%d)\n, err);
 -   goto err_hubmode;
 -   }
 -
 /* CFG1 : SELF_BUS_PWR - Self-Powerd operation */
 err = usb3503_set_bits(i2c, USB3503_CFG1, 
 USB3503_SELF_BUS_PWR);
 if (err  0) {
 --
 1.7.12.4

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Re: [PATCH 1/3] usb: misc: usb3503: Fix up whitespace

[Dongjin Kim]

Signed-off-by: Dongjin Kim tobet...@gmail.com

On Sat, Jun 1, 2013 at 10:34 AM, Julius Werner jwer...@chromium.org wrote:
 Remove an erroneous tab that should be a space.

 Signed-off-by: Julius Werner jwer...@chromium.org
 ---
  drivers/usb/misc/usb3503.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
 index d3a1cce..73aeb87 100644
 --- a/drivers/usb/misc/usb3503.c
 +++ b/drivers/usb/misc/usb3503.c
 @@ -208,7 +208,7 @@ static int usb3503_probe(struct i2c_client *i2c, const 
 struct i2c_device_id *id)
 hub-gpio_connect = of_get_named_gpio(np, intn-gpios, 0);
 if (hub-gpio_connect == -EPROBE_DEFER)
 return -EPROBE_DEFER;
 -   hub-gpio_reset = of_get_named_gpio(np, reset-gpios, 0);
 +   hub-gpio_reset = of_get_named_gpio(np, reset-gpios, 0);
 if (hub-gpio_reset == -EPROBE_DEFER)
 return -EPROBE_DEFER;
 of_property_read_u32(np, initial-mode, mode);
 --
 1.7.12.4

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Re: [PATCH 3/3] usb: misc: usb3503: Remove 100ms sleep on reset, conform to data sheet

[Dongjin Kim]

Signed-off-by: Dongjin Kim tobet...@gmail.com

On Sat, Jun 1, 2013 at 10:34 AM, Julius Werner jwer...@chromium.org wrote:
 The usb3503 driver sleeps a flat 100ms when resetting the chip, with a
 comment about waiting for the reference clock. This seems to be a
 board-specific detail that should not hold up boot across all platforms.
 This patch reduces the sleep to the 4ms initialization delay that the
 chip itself actually requires (as per its data sheet). If certain boards
 require more time to set up the reference clock, they should change this
 through local patches or add a proper, configurable synchronization
 mechanism.

 Signed-off-by: Julius Werner jwer...@chromium.org
 ---
  drivers/usb/misc/usb3503.c | 6 ++
  1 file changed, 2 insertions(+), 4 deletions(-)

 diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
 index a647a2e..a1d509f 100644
 --- a/drivers/usb/misc/usb3503.c
 +++ b/drivers/usb/misc/usb3503.c
 @@ -107,11 +107,9 @@ static int usb3503_reset(int gpio_reset, int state)
 if (gpio_is_valid(gpio_reset))
 gpio_set_value(gpio_reset, state);

 -   /* Wait RefClk when RESET_N is released, otherwise Hub will
 -* not transition to Hub Communication Stage.
 -*/
 +   /* Wait T_HUBINIT == 4ms for hub logic to stabilize */
 if (state)
 -   msleep(100);
 +   usleep_range(4000, 1);

 return 0;
  }
 --
 1.7.12.4

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[PATCH 2/2] usb: misc: usb3503: Adding device tree entry 'disabled-ports'

[Dongjin Kim]

This patch is to add a property 'disabled-ports' representing the unused port
of USB3503. USB3503 can support up to 3 USB host port and each ports can be
controlled to be enabled or disabled. Do not describe this property if all
ports must be enabled.

You can represent the ports to disable in the device tree.

usb3503@08{
...
disabled-ports = <2 3>;
...
};

Signed-off-by: Dongjin Kim 
---
 Documentation/devicetree/bindings/usb/usb3503.txt |5 +
 drivers/usb/misc/usb3503.c|   14 ++
 2 files changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt 
b/Documentation/devicetree/bindings/usb/usb3503.txt
index 6813a71..8c5be48 100644
--- a/Documentation/devicetree/bindings/usb/usb3503.txt
+++ b/Documentation/devicetree/bindings/usb/usb3503.txt
@@ -4,6 +4,10 @@ Required properties:
 - compatible: Should be "smsc,usb3503".
 - reg: Specifies the i2c slave address, it should be 0x08.
 - connect-gpios: Should specify GPIO for connect.
+- disabled-ports: Should specify the ports unused.
+   '1' or '2' or '3' are availe for this property to describe the port
+   number. 1~3 property values are possible to be desribed.
+   Do not describe this property if all ports have to be enabled.
 - intn-gpios: Should specify GPIO for interrupt.
 - reset-gpios: Should specify GPIO for reset.
 - initial-mode: Should specify initial mode.
@@ -14,6 +18,7 @@ Examples:
compatible = "smsc,usb3503";
reg = <0x08>;
connect-gpios = < 0 1>;
+   disabled-ports = <2 3>;
intn-gpios = < 4 1>;
reset-gpios = < 5 1>;
initial-mode = <1>;
diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index ab24bb3..1908ec6 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -186,6 +186,8 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
struct usb3503 *hub;
int err = -ENOMEM;
u32 mode = USB3503_MODE_UNKNOWN;
+   const u32 *property;
+   int len;
 
hub = kzalloc(sizeof(struct usb3503), GFP_KERNEL);
if (!hub) {
@@ -203,6 +205,18 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
hub->gpio_reset = pdata->gpio_reset;
hub->mode   = pdata->initial_mode;
} else if (np) {
+   hub->port_off_mask = 0;
+
+   property = of_get_property(np, "disabled-ports", );
+   if (property && (len / sizeof(u32)) > 0) {
+   int i;
+   for (i = 0; i < len / sizeof(u32); i++) {
+   u32 port = be32_to_cpu(property[i]);
+   if ((1 <= port) && (port <= 3))
+   hub->port_off_mask |= (1 << port);
+   }
+   }
+
hub->gpio_intn  = of_get_named_gpio(np, "connect-gpios", 0);
if (hub->gpio_intn == -EPROBE_DEFER)
return -EPROBE_DEFER;
-- 
1.7.9.5

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[PATCH 1/2] usb: misc: usb3503: Add to select the ports to disable

[Dongjin Kim]

This patch is to disable the USB ports unconnected to USB3503. In order to
disable the port, 'port_off_mask' must be set.

* Disable PORT1 only
.port_off_mask = USB3503_OFF_PORT1;

* Disable PORT1 and PORT3 only
.port_off_mask = USB3503_OFF_PORT1 | USB3503_OFF_PORT3;

* Enables all ports
.port_off_mask = 0;

Signed-off-by: Dongjin Kim 
---
 drivers/usb/misc/usb3503.c|   19 ++-
 include/linux/platform_data/usb3503.h |5 +
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index d3a1cce..ab24bb3 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -42,9 +42,6 @@
 #define USB3503_NRD0x09
 
 #define USB3503_PDS0x0a
-#define USB3503_PORT1  (1 << 1)
-#define USB3503_PORT2  (1 << 2)
-#define USB3503_PORT3  (1 << 3)
 
 #define USB3503_SP_ILOCK   0xe7
 #define USB3503_SPILOCK_CONNECT(1 << 1)
@@ -56,6 +53,7 @@
 struct usb3503 {
enum usb3503_mode   mode;
struct i2c_client   *client;
+   u8  port_off_mask;
int gpio_intn;
int gpio_reset;
int gpio_connect;
@@ -134,12 +132,14 @@ static int usb3503_switch_mode(struct usb3503 *hub, enum 
usb3503_mode mode)
goto err_hubmode;
}
 
-   /* PDS : Port2,3 Disable For Self Powered Operation */
-   err = usb3503_set_bits(i2c, USB3503_PDS,
-   (USB3503_PORT2 | USB3503_PORT3));
-   if (err < 0) {
-   dev_err(>dev, "PDS failed (%d)\n", err);
-   goto err_hubmode;
+   /* PDS : Disable For Self Powered Operation */
+   if (hub->port_off_mask) {
+   err = usb3503_set_bits(i2c, USB3503_PDS,
+   hub->port_off_mask);
+   if (err < 0) {
+   dev_err(>dev, "PDS failed (%d)\n", err);
+   goto err_hubmode;
+   }
}
 
/* CFG1 : SELF_BUS_PWR -> Self-Powerd operation */
@@ -197,6 +197,7 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
hub->client = i2c;
 
if (pdata) {
+   hub->port_off_mask  = pdata->port_off_mask;
hub->gpio_intn  = pdata->gpio_intn;
hub->gpio_connect   = pdata->gpio_connect;
hub->gpio_reset = pdata->gpio_reset;
diff --git a/include/linux/platform_data/usb3503.h 
b/include/linux/platform_data/usb3503.h
index 85dcc70..1d1b6ef 100644
--- a/include/linux/platform_data/usb3503.h
+++ b/include/linux/platform_data/usb3503.h
@@ -3,6 +3,10 @@
 
 #define USB3503_I2C_NAME   "usb3503"
 
+#define USB3503_OFF_PORT1  (1 << 1)
+#define USB3503_OFF_PORT2  (1 << 2)
+#define USB3503_OFF_PORT3  (1 << 3)
+
 enum usb3503_mode {
USB3503_MODE_UNKNOWN,
USB3503_MODE_HUB,
@@ -11,6 +15,7 @@ enum usb3503_mode {
 
 struct usb3503_platform_data {
enum usb3503_mode   initial_mode;
+   u8  port_off_mask;
int gpio_intn;
int gpio_connect;
int gpio_reset;
-- 
1.7.9.5

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[PATCH] usb: phy: samsung: Add support HSIC on Exynos4X12

[Dongjin Kim]

This patch adds to enable High Speed Inter Chip on Exynos4X12. Both channels
are controlled by usbphy driver based on the patch series of usbphy driver
submitted by Tomasz Figa.

[1] https://patchwork.kernel.org/patch/2576121
[2] https://patchwork.kernel.org/patch/2576131
[3] https://patchwork.kernel.org/patch/2576141
[4] https://patchwork.kernel.org/patch/2576151
[5] https://patchwork.kernel.org/patch/2576161
[6] https://patchwork.kernel.org/patch/2576171

Signed-off-by: Dongjin Kim 
Cc: Tomasz Figa 
Cc: Kyungmin Park 
---
 drivers/usb/phy/phy-samsung-usb.c  |5 +
 drivers/usb/phy/phy-samsung-usb.h  |   10 ++
 drivers/usb/phy/phy-samsung-usb2.c |   13 +++--
 3 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/phy/phy-samsung-usb.c 
b/drivers/usb/phy/phy-samsung-usb.c
index 7a1ed90..ac025ca 100644
--- a/drivers/usb/phy/phy-samsung-usb.c
+++ b/drivers/usb/phy/phy-samsung-usb.c
@@ -100,6 +100,11 @@ void samsung_usbphy_set_isolation_4210(struct 
samsung_usbphy *sphy, bool on)
reg_val |= en_mask;
 
writel(reg_val, reg);
+
+   if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12) {
+   writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL0);
+   writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL1);
+   }
 }
 EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation_4210);
 
diff --git a/drivers/usb/phy/phy-samsung-usb.h 
b/drivers/usb/phy/phy-samsung-usb.h
index 585d12f..68771bf 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -47,6 +47,16 @@
 #define RSTCON_HLINK_SWRST (0x1 << 1)
 #define RSTCON_SWRST   (0x1 << 0)
 
+/* EXYNOS4X12 */
+#define EXYNOS4X12_PHY_HSIC_CTRL0  (0x04)
+#define EXYNOS4X12_PHY_HSIC_CTRL1  (0x08)
+
+#define PHYPWR_NORMAL_MASK_HSIC1   (0x7 << 12)
+#define PHYPWR_NORMAL_MASK_HSIC0   (0x7 << 9)
+#define PHYPWR_NORMAL_MASK_PHY1(0x7 << 6)
+
+#define RSTCON_HOSTPHY_SWRST   (0xf << 3)
+
 /* EXYNOS5 */
 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
 
diff --git a/drivers/usb/phy/phy-samsung-usb2.c 
b/drivers/usb/phy/phy-samsung-usb2.c
index 03180c0..1011c16 100644
--- a/drivers/usb/phy/phy-samsung-usb2.c
+++ b/drivers/usb/phy/phy-samsung-usb2.c
@@ -176,8 +176,12 @@ static void samsung_usb2phy_enable(struct samsung_usbphy 
*sphy)
phypwr &= ~PHYPWR_NORMAL_MASK;
rstcon |= RSTCON_SWRST;
break;
-   case TYPE_EXYNOS4210:
case TYPE_EXYNOS4X12:
+   phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
+   PHYPWR_NORMAL_MASK_HSIC1 |
+   PHYPWR_NORMAL_MASK_PHY1);
+   rstcon |= RSTCON_HOSTPHY_SWRST;
+   case TYPE_EXYNOS4210:
phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
rstcon |= RSTCON_SWRST;
default:
@@ -190,6 +194,8 @@ static void samsung_usb2phy_enable(struct samsung_usbphy 
*sphy)
/* reset all ports of PHY and Link */
writel(rstcon, regs + SAMSUNG_RSTCON);
udelay(10);
+   if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12)
+   rstcon &= ~RSTCON_HOSTPHY_SWRST;
rstcon &= ~RSTCON_SWRST;
writel(rstcon, regs + SAMSUNG_RSTCON);
 }
@@ -240,8 +246,11 @@ static void samsung_usb2phy_disable(struct samsung_usbphy 
*sphy)
case TYPE_S3C64XX:
phypwr |= PHYPWR_NORMAL_MASK;
break;
-   case TYPE_EXYNOS4210:
case TYPE_EXYNOS4X12:
+   phypwr |= (PHYPWR_NORMAL_MASK_HSIC0 |
+   PHYPWR_NORMAL_MASK_HSIC1 |
+   PHYPWR_NORMAL_MASK_PHY1);
+   case TYPE_EXYNOS4210:
phypwr |= PHYPWR_NORMAL_MASK_PHY0;
default:
break;
-- 
1.7.9.5

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[PATCH] ARM: dts: add max77686 node entry for ODROID-X

[Dongjin Kim]

ODROID-X board have a max77686 PMIC on i2c channel 0. The properties of used
LDO and BUCK are defined according the schematic.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |  195 ++
 1 file changed, 195 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf..1786225 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -108,4 +108,199 @@
clock-frequency = <2400>;
};
};
+
+   i2c@1386 {
+   pinctrl-0 = <_bus>;
+   pinctrl-names = "default";
+   status = "okay";
+
+   max77686: pmic@09 {
+   compatible = "maxim,max77686";
+   reg = <0x09>;
+
+   voltage-regulators {
+   ldo1_reg: LDO1 {
+   regulator-name = "VDD_ALIVE_1.0V";
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <100>;
+   regulator-always-on;
+   };
+
+   ldo2_reg: LDO2 {
+   regulator-name = "VDDQ_M1_2_1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   };
+
+   ldo3_reg: LDO3 {
+   regulator-name = "VDDQ_EXT_1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   };
+
+   ldo4_reg: LDO4 {
+   regulator-name = "VDDQ_MMC2_2.8V";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   ldo5_reg: LDO5 {
+   regulator-name = "VDDQ_MMC1_3_1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   ldo6_reg: LDO6 {
+   regulator-name = "VDD10_MPLL_1.0V";
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <100>;
+   regulator-always-on;
+   };
+
+   ldo7_reg: LDO7 {
+   regulator-name = "VDD10_XPLL_1.0V";
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <100>;
+   regulator-always-on;
+   };
+
+   ldo11_reg: LDO11 {
+   regulator-name = "VDD18_ABB1_1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   };
+
+   ldo12_reg: LDO12 {
+   regulator-name = "VDD33_USB_3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   ldo13_reg: LDO13 {
+   regulator-name = "VDDQ_C2C_W_1.8V";
+   regulator-min-microvolt = <180>;
+   

[PATCH] ARM: dts: add max77686 node entry for ODROID-X

[Dongjin Kim]

ODROID-X board have a max77686 PMIC on i2c channel 0. The properties of used
LDO and BUCK are defined according the schematic.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |  195 ++
 1 file changed, 195 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf..1786225 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -108,4 +108,199 @@
clock-frequency = 2400;
};
};
+
+   i2c@1386 {
+   pinctrl-0 = i2c0_bus;
+   pinctrl-names = default;
+   status = okay;
+
+   max77686: pmic@09 {
+   compatible = maxim,max77686;
+   reg = 0x09;
+
+   voltage-regulators {
+   ldo1_reg: LDO1 {
+   regulator-name = VDD_ALIVE_1.0V;
+   regulator-min-microvolt = 100;
+   regulator-max-microvolt = 100;
+   regulator-always-on;
+   };
+
+   ldo2_reg: LDO2 {
+   regulator-name = VDDQ_M1_2_1.8V;
+   regulator-min-microvolt = 180;
+   regulator-max-microvolt = 180;
+   regulator-always-on;
+   };
+
+   ldo3_reg: LDO3 {
+   regulator-name = VDDQ_EXT_1.8V;
+   regulator-min-microvolt = 180;
+   regulator-max-microvolt = 180;
+   regulator-always-on;
+   };
+
+   ldo4_reg: LDO4 {
+   regulator-name = VDDQ_MMC2_2.8V;
+   regulator-min-microvolt = 280;
+   regulator-max-microvolt = 280;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   ldo5_reg: LDO5 {
+   regulator-name = VDDQ_MMC1_3_1.8V;
+   regulator-min-microvolt = 180;
+   regulator-max-microvolt = 180;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   ldo6_reg: LDO6 {
+   regulator-name = VDD10_MPLL_1.0V;
+   regulator-min-microvolt = 100;
+   regulator-max-microvolt = 100;
+   regulator-always-on;
+   };
+
+   ldo7_reg: LDO7 {
+   regulator-name = VDD10_XPLL_1.0V;
+   regulator-min-microvolt = 100;
+   regulator-max-microvolt = 100;
+   regulator-always-on;
+   };
+
+   ldo11_reg: LDO11 {
+   regulator-name = VDD18_ABB1_1.8V;
+   regulator-min-microvolt = 180;
+   regulator-max-microvolt = 180;
+   regulator-always-on;
+   };
+
+   ldo12_reg: LDO12 {
+   regulator-name = VDD33_USB_3.3V;
+   regulator-min-microvolt = 330;
+   regulator-max-microvolt = 330;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   ldo13_reg: LDO13 {
+   regulator-name = VDDQ_C2C_W_1.8V;
+   regulator-min-microvolt = 180;
+   regulator-max-microvolt = 180;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   ldo14_reg: LDO14 {
+   regulator-name

[PATCH] usb: phy: samsung: Add support HSIC on Exynos4X12

[Dongjin Kim]

This patch adds to enable High Speed Inter Chip on Exynos4X12. Both channels
are controlled by usbphy driver based on the patch series of usbphy driver
submitted by Tomasz Figa.

[1] https://patchwork.kernel.org/patch/2576121
[2] https://patchwork.kernel.org/patch/2576131
[3] https://patchwork.kernel.org/patch/2576141
[4] https://patchwork.kernel.org/patch/2576151
[5] https://patchwork.kernel.org/patch/2576161
[6] https://patchwork.kernel.org/patch/2576171

Signed-off-by: Dongjin Kim tobet...@gmail.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
---
 drivers/usb/phy/phy-samsung-usb.c  |5 +
 drivers/usb/phy/phy-samsung-usb.h  |   10 ++
 drivers/usb/phy/phy-samsung-usb2.c |   13 +++--
 3 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/phy/phy-samsung-usb.c 
b/drivers/usb/phy/phy-samsung-usb.c
index 7a1ed90..ac025ca 100644
--- a/drivers/usb/phy/phy-samsung-usb.c
+++ b/drivers/usb/phy/phy-samsung-usb.c
@@ -100,6 +100,11 @@ void samsung_usbphy_set_isolation_4210(struct 
samsung_usbphy *sphy, bool on)
reg_val |= en_mask;
 
writel(reg_val, reg);
+
+   if (sphy-drv_data-cpu_type == TYPE_EXYNOS4X12) {
+   writel(reg_val, sphy-pmuregs + EXYNOS4X12_PHY_HSIC_CTRL0);
+   writel(reg_val, sphy-pmuregs + EXYNOS4X12_PHY_HSIC_CTRL1);
+   }
 }
 EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation_4210);
 
diff --git a/drivers/usb/phy/phy-samsung-usb.h 
b/drivers/usb/phy/phy-samsung-usb.h
index 585d12f..68771bf 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -47,6 +47,16 @@
 #define RSTCON_HLINK_SWRST (0x1  1)
 #define RSTCON_SWRST   (0x1  0)
 
+/* EXYNOS4X12 */
+#define EXYNOS4X12_PHY_HSIC_CTRL0  (0x04)
+#define EXYNOS4X12_PHY_HSIC_CTRL1  (0x08)
+
+#define PHYPWR_NORMAL_MASK_HSIC1   (0x7  12)
+#define PHYPWR_NORMAL_MASK_HSIC0   (0x7  9)
+#define PHYPWR_NORMAL_MASK_PHY1(0x7  6)
+
+#define RSTCON_HOSTPHY_SWRST   (0xf  3)
+
 /* EXYNOS5 */
 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
 
diff --git a/drivers/usb/phy/phy-samsung-usb2.c 
b/drivers/usb/phy/phy-samsung-usb2.c
index 03180c0..1011c16 100644
--- a/drivers/usb/phy/phy-samsung-usb2.c
+++ b/drivers/usb/phy/phy-samsung-usb2.c
@@ -176,8 +176,12 @@ static void samsung_usb2phy_enable(struct samsung_usbphy 
*sphy)
phypwr = ~PHYPWR_NORMAL_MASK;
rstcon |= RSTCON_SWRST;
break;
-   case TYPE_EXYNOS4210:
case TYPE_EXYNOS4X12:
+   phypwr = ~(PHYPWR_NORMAL_MASK_HSIC0 |
+   PHYPWR_NORMAL_MASK_HSIC1 |
+   PHYPWR_NORMAL_MASK_PHY1);
+   rstcon |= RSTCON_HOSTPHY_SWRST;
+   case TYPE_EXYNOS4210:
phypwr = ~PHYPWR_NORMAL_MASK_PHY0;
rstcon |= RSTCON_SWRST;
default:
@@ -190,6 +194,8 @@ static void samsung_usb2phy_enable(struct samsung_usbphy 
*sphy)
/* reset all ports of PHY and Link */
writel(rstcon, regs + SAMSUNG_RSTCON);
udelay(10);
+   if (sphy-drv_data-cpu_type == TYPE_EXYNOS4X12)
+   rstcon = ~RSTCON_HOSTPHY_SWRST;
rstcon = ~RSTCON_SWRST;
writel(rstcon, regs + SAMSUNG_RSTCON);
 }
@@ -240,8 +246,11 @@ static void samsung_usb2phy_disable(struct samsung_usbphy 
*sphy)
case TYPE_S3C64XX:
phypwr |= PHYPWR_NORMAL_MASK;
break;
-   case TYPE_EXYNOS4210:
case TYPE_EXYNOS4X12:
+   phypwr |= (PHYPWR_NORMAL_MASK_HSIC0 |
+   PHYPWR_NORMAL_MASK_HSIC1 |
+   PHYPWR_NORMAL_MASK_PHY1);
+   case TYPE_EXYNOS4210:
phypwr |= PHYPWR_NORMAL_MASK_PHY0;
default:
break;
-- 
1.7.9.5

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[PATCH 1/2] usb: misc: usb3503: Add to select the ports to disable

[Dongjin Kim]

This patch is to disable the USB ports unconnected to USB3503. In order to
disable the port, 'port_off_mask' must be set.

* Disable PORT1 only
.port_off_mask = USB3503_OFF_PORT1;

* Disable PORT1 and PORT3 only
.port_off_mask = USB3503_OFF_PORT1 | USB3503_OFF_PORT3;

* Enables all ports
.port_off_mask = 0;

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 drivers/usb/misc/usb3503.c|   19 ++-
 include/linux/platform_data/usb3503.h |5 +
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index d3a1cce..ab24bb3 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -42,9 +42,6 @@
 #define USB3503_NRD0x09
 
 #define USB3503_PDS0x0a
-#define USB3503_PORT1  (1  1)
-#define USB3503_PORT2  (1  2)
-#define USB3503_PORT3  (1  3)
 
 #define USB3503_SP_ILOCK   0xe7
 #define USB3503_SPILOCK_CONNECT(1  1)
@@ -56,6 +53,7 @@
 struct usb3503 {
enum usb3503_mode   mode;
struct i2c_client   *client;
+   u8  port_off_mask;
int gpio_intn;
int gpio_reset;
int gpio_connect;
@@ -134,12 +132,14 @@ static int usb3503_switch_mode(struct usb3503 *hub, enum 
usb3503_mode mode)
goto err_hubmode;
}
 
-   /* PDS : Port2,3 Disable For Self Powered Operation */
-   err = usb3503_set_bits(i2c, USB3503_PDS,
-   (USB3503_PORT2 | USB3503_PORT3));
-   if (err  0) {
-   dev_err(i2c-dev, PDS failed (%d)\n, err);
-   goto err_hubmode;
+   /* PDS : Disable For Self Powered Operation */
+   if (hub-port_off_mask) {
+   err = usb3503_set_bits(i2c, USB3503_PDS,
+   hub-port_off_mask);
+   if (err  0) {
+   dev_err(i2c-dev, PDS failed (%d)\n, err);
+   goto err_hubmode;
+   }
}
 
/* CFG1 : SELF_BUS_PWR - Self-Powerd operation */
@@ -197,6 +197,7 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
hub-client = i2c;
 
if (pdata) {
+   hub-port_off_mask  = pdata-port_off_mask;
hub-gpio_intn  = pdata-gpio_intn;
hub-gpio_connect   = pdata-gpio_connect;
hub-gpio_reset = pdata-gpio_reset;
diff --git a/include/linux/platform_data/usb3503.h 
b/include/linux/platform_data/usb3503.h
index 85dcc70..1d1b6ef 100644
--- a/include/linux/platform_data/usb3503.h
+++ b/include/linux/platform_data/usb3503.h
@@ -3,6 +3,10 @@
 
 #define USB3503_I2C_NAME   usb3503
 
+#define USB3503_OFF_PORT1  (1  1)
+#define USB3503_OFF_PORT2  (1  2)
+#define USB3503_OFF_PORT3  (1  3)
+
 enum usb3503_mode {
USB3503_MODE_UNKNOWN,
USB3503_MODE_HUB,
@@ -11,6 +15,7 @@ enum usb3503_mode {
 
 struct usb3503_platform_data {
enum usb3503_mode   initial_mode;
+   u8  port_off_mask;
int gpio_intn;
int gpio_connect;
int gpio_reset;
-- 
1.7.9.5

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[PATCH 2/2] usb: misc: usb3503: Adding device tree entry 'disabled-ports'

[Dongjin Kim]

This patch is to add a property 'disabled-ports' representing the unused port
of USB3503. USB3503 can support up to 3 USB host port and each ports can be
controlled to be enabled or disabled. Do not describe this property if all
ports must be enabled.

You can represent the ports to disable in the device tree.

usb3503@08{
...
disabled-ports = 2 3;
...
};

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 Documentation/devicetree/bindings/usb/usb3503.txt |5 +
 drivers/usb/misc/usb3503.c|   14 ++
 2 files changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt 
b/Documentation/devicetree/bindings/usb/usb3503.txt
index 6813a71..8c5be48 100644
--- a/Documentation/devicetree/bindings/usb/usb3503.txt
+++ b/Documentation/devicetree/bindings/usb/usb3503.txt
@@ -4,6 +4,10 @@ Required properties:
 - compatible: Should be smsc,usb3503.
 - reg: Specifies the i2c slave address, it should be 0x08.
 - connect-gpios: Should specify GPIO for connect.
+- disabled-ports: Should specify the ports unused.
+   '1' or '2' or '3' are availe for this property to describe the port
+   number. 1~3 property values are possible to be desribed.
+   Do not describe this property if all ports have to be enabled.
 - intn-gpios: Should specify GPIO for interrupt.
 - reset-gpios: Should specify GPIO for reset.
 - initial-mode: Should specify initial mode.
@@ -14,6 +18,7 @@ Examples:
compatible = smsc,usb3503;
reg = 0x08;
connect-gpios = gpx3 0 1;
+   disabled-ports = 2 3;
intn-gpios = gpx3 4 1;
reset-gpios = gpx3 5 1;
initial-mode = 1;
diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index ab24bb3..1908ec6 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -186,6 +186,8 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
struct usb3503 *hub;
int err = -ENOMEM;
u32 mode = USB3503_MODE_UNKNOWN;
+   const u32 *property;
+   int len;
 
hub = kzalloc(sizeof(struct usb3503), GFP_KERNEL);
if (!hub) {
@@ -203,6 +205,18 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
hub-gpio_reset = pdata-gpio_reset;
hub-mode   = pdata-initial_mode;
} else if (np) {
+   hub-port_off_mask = 0;
+
+   property = of_get_property(np, disabled-ports, len);
+   if (property  (len / sizeof(u32))  0) {
+   int i;
+   for (i = 0; i  len / sizeof(u32); i++) {
+   u32 port = be32_to_cpu(property[i]);
+   if ((1 = port)  (port = 3))
+   hub-port_off_mask |= (1  port);
+   }
+   }
+
hub-gpio_intn  = of_get_named_gpio(np, connect-gpios, 0);
if (hub-gpio_intn == -EPROBE_DEFER)
return -EPROBE_DEFER;
-- 
1.7.9.5

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[PATCH] usb: phy: samsung: adding usbphy for Exynos4X12

[Dongjin Kim]

This patch adds usb host phy (USB 2.0 PHY) support for Samsung Exynos4X12 SoC.
New functions, samsung_exynos4x12_usb2phy_enable/_disable and selecting
reference clock, for Exynos4X12 are added. Since it has different register
set up with Exynos4210 or Exynos5250, "samsung,exynos4x12-usb2phy" is added.

Signed-off-by: Dongjin Kim 
---
 .../devicetree/bindings/usb/samsung-usbphy.txt |5 ++
 drivers/usb/phy/phy-samsung-usb.c  |   30 ++-
 drivers/usb/phy/phy-samsung-usb.h  |   18 
 drivers/usb/phy/phy-samsung-usb2.c |   90 
 4 files changed, 140 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt 
b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
index 33fd354..f805878 100644
--- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -18,6 +18,11 @@ Exynos4210:
 - clock-names: names of clock correseponding IDs clock property as requested
   by the controller driver.
 
+Exynos4x12:
+- compatible : should be "samsung,exynos4x12-usb2phy"
+- reg : base physical address of the phy registers and length of memory mapped
+   region.
+
 Exynos5250:
 - compatible : should be "samsung,exynos5250-usb2phy"
 - reg : base physical address of the phy registers and length of memory mapped
diff --git a/drivers/usb/phy/phy-samsung-usb.c 
b/drivers/usb/phy/phy-samsung-usb.c
index 7b118ee5..efb26de 100644
--- a/drivers/usb/phy/phy-samsung-usb.c
+++ b/drivers/usb/phy/phy-samsung-usb.c
@@ -91,10 +91,11 @@ void samsung_usbphy_set_isolation(struct samsung_usbphy 
*sphy, bool on)
 */
break;
case TYPE_EXYNOS4210:
+   case TYPE_EXYNOS4X12:
/*
-* Fall through since exynos4210 and exynos5250 have similar
-* register architecture: two separate registers for host and
-* device phy control with enable bit at position 0.
+* Fall through since exynos4210/4x12 and exynos5250 have
+* similar register architecture: two separateregistersfor
+* host and device phy control with enable bit at position 0.
 */
case TYPE_EXYNOS5250:
if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
@@ -210,6 +211,29 @@ int samsung_usbphy_get_refclk_freq(struct samsung_usbphy 
*sphy)
refclk_freq = FSEL_CLKSEL_24M;
break;
}
+   } else if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12) {
+   switch (clk_get_rate(ref_clk)) {
+   case 9600 * KHZ:
+   refclk_freq = FSEL_CLKSEL_9600K;
+   break;
+   case 10 * MHZ:
+   refclk_freq = FSEL_CLKSEL_10M;
+   break;
+   case 12 * MHZ:
+   refclk_freq = FSEL_CLKSEL_12M;
+   break;
+   case 19200 * KHZ:
+   refclk_freq = FSEL_CLKSEL_19200K;
+   break;
+   case 20 * MHZ:
+   refclk_freq = FSEL_CLKSEL_20M;
+   break;
+   case 24 * MHZ:
+   default:
+   /* default reference clock */
+   refclk_freq = FSEL_CLKSEL_24M;
+   break;
+   }
} else {
switch (clk_get_rate(ref_clk)) {
case 12 * MHZ:
diff --git a/drivers/usb/phy/phy-samsung-usb.h 
b/drivers/usb/phy/phy-samsung-usb.h
index 70a9cae..ad86bce 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -47,6 +47,23 @@
 #define RSTCON_HLINK_SWRST (0x1 << 1)
 #define RSTCON_SWRST   (0x1 << 0)
 
+/* For Exynos4x12 */
+#define PHYCLK_COMMON_ON_N_PHY0(0x1 << 4)
+#define PHYCLK_COMMON_ON_N_PHY1(0x1 << 7)
+
+#define PHYPWR_NORMAL_MASK_HSIC1   (0x7 << 12)
+#define PHYPWR_NORMAL_MASK_HSIC0   (0x7 << 9)
+#define PHYPWR_NORMAL_MASK_PHY1(0x7 << 6)
+
+#define PHYPWR_ANALOG_POWERDOWN_PHY1   (0x1 << 7)
+
+#define RSTCON_HLINK_SWRST_MASK(0xf << 7)
+#define RSTCON_PHY1_SWRST_MASK (0xf << 3)
+#define RSTCON_PHY0_SWRST_MASK (0x7 << 0)
+
+#define EXYNOS4X12_PHY_HSIC_CTRL0  (0x04)
+#define EXYNOS4X12_PHY_HSIC_CTRL1  (0x08)
+
 /* EXYNOS5 */
 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
 
@@ -241,6 +258,7 @@
 enum samsung_cpu_type {
TYPE_S3C64XX,
TYPE_EXYNOS4210,
+   TYPE_EXYNOS4X12,
TYPE_EXYNOS5250,
 };
 
diff --git a/drivers/usb/phy/phy-sam

[PATCH] usb: phy: samsung: adding usbphy for Exynos4X12

[Dongjin Kim]

This patch adds usb host phy (USB 2.0 PHY) support for Samsung Exynos4X12 SoC.
New functions, samsung_exynos4x12_usb2phy_enable/_disable and selecting
reference clock, for Exynos4X12 are added. Since it has different register
set up with Exynos4210 or Exynos5250, samsung,exynos4x12-usb2phy is added.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 .../devicetree/bindings/usb/samsung-usbphy.txt |5 ++
 drivers/usb/phy/phy-samsung-usb.c  |   30 ++-
 drivers/usb/phy/phy-samsung-usb.h  |   18 
 drivers/usb/phy/phy-samsung-usb2.c |   90 
 4 files changed, 140 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt 
b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
index 33fd354..f805878 100644
--- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -18,6 +18,11 @@ Exynos4210:
 - clock-names: names of clock correseponding IDs clock property as requested
   by the controller driver.
 
+Exynos4x12:
+- compatible : should be samsung,exynos4x12-usb2phy
+- reg : base physical address of the phy registers and length of memory mapped
+   region.
+
 Exynos5250:
 - compatible : should be samsung,exynos5250-usb2phy
 - reg : base physical address of the phy registers and length of memory mapped
diff --git a/drivers/usb/phy/phy-samsung-usb.c 
b/drivers/usb/phy/phy-samsung-usb.c
index 7b118ee5..efb26de 100644
--- a/drivers/usb/phy/phy-samsung-usb.c
+++ b/drivers/usb/phy/phy-samsung-usb.c
@@ -91,10 +91,11 @@ void samsung_usbphy_set_isolation(struct samsung_usbphy 
*sphy, bool on)
 */
break;
case TYPE_EXYNOS4210:
+   case TYPE_EXYNOS4X12:
/*
-* Fall through since exynos4210 and exynos5250 have similar
-* register architecture: two separate registers for host and
-* device phy control with enable bit at position 0.
+* Fall through since exynos4210/4x12 and exynos5250 have
+* similar register architecture: two separateregistersfor
+* host and device phy control with enable bit at position 0.
 */
case TYPE_EXYNOS5250:
if (sphy-phy_type == USB_PHY_TYPE_DEVICE) {
@@ -210,6 +211,29 @@ int samsung_usbphy_get_refclk_freq(struct samsung_usbphy 
*sphy)
refclk_freq = FSEL_CLKSEL_24M;
break;
}
+   } else if (sphy-drv_data-cpu_type == TYPE_EXYNOS4X12) {
+   switch (clk_get_rate(ref_clk)) {
+   case 9600 * KHZ:
+   refclk_freq = FSEL_CLKSEL_9600K;
+   break;
+   case 10 * MHZ:
+   refclk_freq = FSEL_CLKSEL_10M;
+   break;
+   case 12 * MHZ:
+   refclk_freq = FSEL_CLKSEL_12M;
+   break;
+   case 19200 * KHZ:
+   refclk_freq = FSEL_CLKSEL_19200K;
+   break;
+   case 20 * MHZ:
+   refclk_freq = FSEL_CLKSEL_20M;
+   break;
+   case 24 * MHZ:
+   default:
+   /* default reference clock */
+   refclk_freq = FSEL_CLKSEL_24M;
+   break;
+   }
} else {
switch (clk_get_rate(ref_clk)) {
case 12 * MHZ:
diff --git a/drivers/usb/phy/phy-samsung-usb.h 
b/drivers/usb/phy/phy-samsung-usb.h
index 70a9cae..ad86bce 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -47,6 +47,23 @@
 #define RSTCON_HLINK_SWRST (0x1  1)
 #define RSTCON_SWRST   (0x1  0)
 
+/* For Exynos4x12 */
+#define PHYCLK_COMMON_ON_N_PHY0(0x1  4)
+#define PHYCLK_COMMON_ON_N_PHY1(0x1  7)
+
+#define PHYPWR_NORMAL_MASK_HSIC1   (0x7  12)
+#define PHYPWR_NORMAL_MASK_HSIC0   (0x7  9)
+#define PHYPWR_NORMAL_MASK_PHY1(0x7  6)
+
+#define PHYPWR_ANALOG_POWERDOWN_PHY1   (0x1  7)
+
+#define RSTCON_HLINK_SWRST_MASK(0xf  7)
+#define RSTCON_PHY1_SWRST_MASK (0xf  3)
+#define RSTCON_PHY0_SWRST_MASK (0x7  0)
+
+#define EXYNOS4X12_PHY_HSIC_CTRL0  (0x04)
+#define EXYNOS4X12_PHY_HSIC_CTRL1  (0x08)
+
 /* EXYNOS5 */
 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
 
@@ -241,6 +258,7 @@
 enum samsung_cpu_type {
TYPE_S3C64XX,
TYPE_EXYNOS4210,
+   TYPE_EXYNOS4X12,
TYPE_EXYNOS5250,
 };
 
diff --git a/drivers/usb/phy/phy-samsung-usb2.c 
b/drivers/usb/phy/phy-samsung-usb2.c
index 45ffe03..b95d05d 100644
--- a/drivers/usb/phy/phy-samsung-usb2

[PATCH v4] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

This patch adds the compatible string for MSHC controller of Exynos4412.
And exynos5250_dwmmc_caps is renamed to exynos_dwmmc_caps, since it has the
capablities of common feature supported by Exynos4 and Exynos5.

Cc: Seungwon Jeon 
Cc: Jaehoon Chung 
Cc: Sachin Kamat 
Signed-off-by: Dongjin Kim 
---
 drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 4d50da6..dd8f58c 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
return 0;
 }
 
-/* Exynos5250 controller specific capabilities */
-static unsigned long exynos5250_dwmmc_caps[4] = {
+/* Common capabilities of Exynos4/Exynos5 SoC */
+static unsigned long exynos_dwmmc_caps[4] = {
MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
MMC_CAP_CMD23,
@@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
MMC_CAP_CMD23,
 };
 
-static const struct dw_mci_drv_data exynos5250_drv_data = {
-   .caps   = exynos5250_dwmmc_caps,
+static const struct dw_mci_drv_data exynos_drv_data = {
+   .caps   = exynos_dwmmc_caps,
.init   = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
.prepare_command= dw_mci_exynos_prepare_command,
@@ -219,8 +219,10 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
 };
 
 static const struct of_device_id dw_mci_exynos_match[] = {
+   { .compatible = "samsung,exynos4412-dw-mshc",
+   .data = _drv_data, },
{ .compatible = "samsung,exynos5250-dw-mshc",
-   .data = _drv_data, },
+   .data = _drv_data, },
{},
 };
 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
-- 
1.7.10.4

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[PATCH v4] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

This patch adds the compatible string for MSHC controller of Exynos4412.
And exynos5250_dwmmc_caps is renamed to exynos_dwmmc_caps, since it has the
capablities of common feature supported by Exynos4 and Exynos5.

Cc: Seungwon Jeon tgih@samsung.com
Cc: Jaehoon Chung jh80.ch...@samsung.com
Cc: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 4d50da6..dd8f58c 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
return 0;
 }
 
-/* Exynos5250 controller specific capabilities */
-static unsigned long exynos5250_dwmmc_caps[4] = {
+/* Common capabilities of Exynos4/Exynos5 SoC */
+static unsigned long exynos_dwmmc_caps[4] = {
MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
MMC_CAP_CMD23,
@@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
MMC_CAP_CMD23,
 };
 
-static const struct dw_mci_drv_data exynos5250_drv_data = {
-   .caps   = exynos5250_dwmmc_caps,
+static const struct dw_mci_drv_data exynos_drv_data = {
+   .caps   = exynos_dwmmc_caps,
.init   = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
.prepare_command= dw_mci_exynos_prepare_command,
@@ -219,8 +219,10 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
 };
 
 static const struct of_device_id dw_mci_exynos_match[] = {
+   { .compatible = samsung,exynos4412-dw-mshc,
+   .data = exynos_drv_data, },
{ .compatible = samsung,exynos5250-dw-mshc,
-   .data = exynos5250_drv_data, },
+   .data = exynos_drv_data, },
{},
 };
 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
-- 
1.7.10.4

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Re: [PATCH v3] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

Hello Seungwon,

OK, I will change the commit message. And I also think Alim's idea is
good but need more detail about functional features of Synopsis' IP.
Similar situation would be happened to Exynos4210 which is not
supported by dw_mmc-exynos.c yet.

Regards,
Dongjin.

On Thu, Feb 21, 2013 at 7:53 PM, Seungwon Jeon  wrote:
> On Wednesday, February 20, 2013, Alim Akhtar wrote:
>> Hi,
>>
>> On Tue, Feb 19, 2013 at 6:04 PM, Dongjin Kim  wrote:
>> > Hello Seungwon,
>> >
>> > Thank you for reviewing and I understand what you mean.
>> >
>> > I agree that Exynos5250 and Exynos4412 are not same, no idea how much
>> > they are different because no Exynos5250 spec on my hand. But at least
>> > I assumed that the capabilities below are supported by Exynos4412 in
>> > terms of its datasheet and it does work on my end as expected. :) Also
>> > I assumed it will be separated if one of both become different to add
>> > more capabilities.
>> >
>> > MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
>> >MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
>> >
>> > Maybe my understanding or approach is wrong since I do not have the
>> > information of Exynos5250.
>> > And suggestion do you have?
> At least, these capabilities can be shared because of common feature, not 
> fully same.
> Dongjin, could you modify the commit message and comments of code?
>
> Let me introduce the functional feature of Exynos5250 and capability 
> extension.
> I guess I'll send soon.
>
> Thanks,
> Seungwon Jeon
>
>>
>> Recently Guennadi Liakhovetski has done some work to centralize the
>> mmc capabilities. See [1] and [2].
>> Those patches are pushed to Chris's mmc-next tree.
>> Is  it possible to extend [1] and [2] and add more capabilities (at
>> least all known one) and let these caps being passed from DT instead?
>>
>> Second thought is, let the common minimum caps as a part of .caps
>> field in dw_mmc-exynos.c itself and pass the extra/advance controller
>> caps from DT and parse them via dw_mci_parse_dt() in dw_mmc.c itself.
>>
>> [1] https://patchwork.kernel.org/patch/1991851/
>> [2] https://patchwork.kernel.org/patch/2106531/
>>
>> > Regards,
>> > Dongjin.
>> >
>> > On Tue, Feb 19, 2013 at 7:19 PM, Seungwon Jeon  
>> > wrote:
>> >> On Tuesday, February 19, 2013, Dongjin Kim wrote:
>> >>> This patch adds the compatible string for MSHC controller of Exynos4412, 
>> >>> and
>> >>> share the controller specific properties with Exynos5250 since they have 
>> >>> same
>> >>> features. Its driver data name is changed to exynos_drv_data instead SoC
>> >>> specific name.
>> >>
>> >> It's not actually same.
>> >> Exynos4412 doesn't have forward compatibilities for Exynos5250.
>> >> I agree that functionality of exynos_drv_data is common.
>> >> These functions have been implemented for existing Exynos*.
>> >> But in case of caps, it can't applied completely.
>> >> I'm concerning about this.
>> >>
>> >> Thanks,
>> >> Seungwon Jeon
>> >>>
>> >>> Cc: Jaehoon Chung 
>> >>> Cc: Sachin Kamat 
>> >>> Signed-off-by: Dongjin Kim 
>> >>> ---
>> >>>  drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
>> >>>  1 file changed, 7 insertions(+), 5 deletions(-)
>> >>>
>> >>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> >>> b/drivers/mmc/host/dw_mmc-exynos.c
>> >>> index 4d50da6..38cd03c 100644
>> >>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> >>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> >>> @@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci 
>> >>> *host,
>> >>>   return 0;
>> >>>  }
>> >>>
>> >>> -/* Exynos5250 controller specific capabilities */
>> >>> -static unsigned long exynos5250_dwmmc_caps[4] = {
>> >>> +/* Exynos4412/Exynos5250 controller specific capabilities */
>> >>> +static unsigned long exynos_dwmmc_caps[4] = {
>> >>>   MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
>> >>>   MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
>> >>>   MMC_CAP_CMD23,
>> >>> @@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
>> >>>   MMC_CAP_CMD23,
>> >&

Re: [PATCH v3] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

Hello Seungwon,

OK, I will change the commit message. And I also think Alim's idea is
good but need more detail about functional features of Synopsis' IP.
Similar situation would be happened to Exynos4210 which is not
supported by dw_mmc-exynos.c yet.

Regards,
Dongjin.

On Thu, Feb 21, 2013 at 7:53 PM, Seungwon Jeon tgih@samsung.com wrote:
 On Wednesday, February 20, 2013, Alim Akhtar wrote:
 Hi,

 On Tue, Feb 19, 2013 at 6:04 PM, Dongjin Kim tobet...@gmail.com wrote:
  Hello Seungwon,
 
  Thank you for reviewing and I understand what you mean.
 
  I agree that Exynos5250 and Exynos4412 are not same, no idea how much
  they are different because no Exynos5250 spec on my hand. But at least
  I assumed that the capabilities below are supported by Exynos4412 in
  terms of its datasheet and it does work on my end as expected. :) Also
  I assumed it will be separated if one of both become different to add
  more capabilities.
 
  MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
 MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
 
  Maybe my understanding or approach is wrong since I do not have the
  information of Exynos5250.
  And suggestion do you have?
 At least, these capabilities can be shared because of common feature, not 
 fully same.
 Dongjin, could you modify the commit message and comments of code?

 Let me introduce the functional feature of Exynos5250 and capability 
 extension.
 I guess I'll send soon.

 Thanks,
 Seungwon Jeon


 Recently Guennadi Liakhovetski has done some work to centralize the
 mmc capabilities. See [1] and [2].
 Those patches are pushed to Chris's mmc-next tree.
 Is  it possible to extend [1] and [2] and add more capabilities (at
 least all known one) and let these caps being passed from DT instead?

 Second thought is, let the common minimum caps as a part of .caps
 field in dw_mmc-exynos.c itself and pass the extra/advance controller
 caps from DT and parse them via dw_mci_parse_dt() in dw_mmc.c itself.

 [1] https://patchwork.kernel.org/patch/1991851/
 [2] https://patchwork.kernel.org/patch/2106531/

  Regards,
  Dongjin.
 
  On Tue, Feb 19, 2013 at 7:19 PM, Seungwon Jeon tgih@samsung.com 
  wrote:
  On Tuesday, February 19, 2013, Dongjin Kim wrote:
  This patch adds the compatible string for MSHC controller of Exynos4412, 
  and
  share the controller specific properties with Exynos5250 since they have 
  same
  features. Its driver data name is changed to exynos_drv_data instead SoC
  specific name.
 
  It's not actually same.
  Exynos4412 doesn't have forward compatibilities for Exynos5250.
  I agree that functionality of exynos_drv_data is common.
  These functions have been implemented for existing Exynos*.
  But in case of caps, it can't applied completely.
  I'm concerning about this.
 
  Thanks,
  Seungwon Jeon
 
  Cc: Jaehoon Chung jh80.ch...@samsung.com
  Cc: Sachin Kamat sachin.ka...@linaro.org
  Signed-off-by: Dongjin Kim tobet...@gmail.com
  ---
   drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
   1 file changed, 7 insertions(+), 5 deletions(-)
 
  diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
  b/drivers/mmc/host/dw_mmc-exynos.c
  index 4d50da6..38cd03c 100644
  --- a/drivers/mmc/host/dw_mmc-exynos.c
  +++ b/drivers/mmc/host/dw_mmc-exynos.c
  @@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci 
  *host,
return 0;
   }
 
  -/* Exynos5250 controller specific capabilities */
  -static unsigned long exynos5250_dwmmc_caps[4] = {
  +/* Exynos4412/Exynos5250 controller specific capabilities */
  +static unsigned long exynos_dwmmc_caps[4] = {
MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
MMC_CAP_CMD23,
  @@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
MMC_CAP_CMD23,
   };
 
  -static const struct dw_mci_drv_data exynos5250_drv_data = {
  - .caps   = exynos5250_dwmmc_caps,
  +static const struct dw_mci_drv_data exynos_drv_data = {
  + .caps   = exynos_dwmmc_caps,
.init   = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
.prepare_command= dw_mci_exynos_prepare_command,
  @@ -219,8 +219,10 @@ static const struct dw_mci_drv_data 
  exynos5250_drv_data = {
   };
 
   static const struct of_device_id dw_mci_exynos_match[] = {
  + { .compatible = samsung,exynos4412-dw-mshc,
  + .data = exynos_drv_data, },
{ .compatible = samsung,exynos5250-dw-mshc,
  - .data = exynos5250_drv_data, },
  + .data = exynos_drv_data, },
{},
   };
   MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
  --
  1.7.10.4
 
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Re: [PATCH v3] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

Hello Seungwon,

Thank you for reviewing and I understand what you mean.

I agree that Exynos5250 and Exynos4412 are not same, no idea how much
they are different because no Exynos5250 spec on my hand. But at least
I assumed that the capabilities below are supported by Exynos4412 in
terms of its datasheet and it does work on my end as expected. :) Also
I assumed it will be separated if one of both become different to add
more capabilities.

MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
   MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,

Maybe my understanding or approach is wrong since I do not have the
information of Exynos5250.
And suggestion do you have?

Regards,
Dongjin.

On Tue, Feb 19, 2013 at 7:19 PM, Seungwon Jeon  wrote:
> On Tuesday, February 19, 2013, Dongjin Kim wrote:
>> This patch adds the compatible string for MSHC controller of Exynos4412, and
>> share the controller specific properties with Exynos5250 since they have same
>> features. Its driver data name is changed to exynos_drv_data instead SoC
>> specific name.
>
> It's not actually same.
> Exynos4412 doesn't have forward compatibilities for Exynos5250.
> I agree that functionality of exynos_drv_data is common.
> These functions have been implemented for existing Exynos*.
> But in case of caps, it can't applied completely.
> I'm concerning about this.
>
> Thanks,
> Seungwon Jeon
>>
>> Cc: Jaehoon Chung 
>> Cc: Sachin Kamat 
>> Signed-off-by: Dongjin Kim 
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
>>  1 file changed, 7 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> b/drivers/mmc/host/dw_mmc-exynos.c
>> index 4d50da6..38cd03c 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
>>   return 0;
>>  }
>>
>> -/* Exynos5250 controller specific capabilities */
>> -static unsigned long exynos5250_dwmmc_caps[4] = {
>> +/* Exynos4412/Exynos5250 controller specific capabilities */
>> +static unsigned long exynos_dwmmc_caps[4] = {
>>   MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
>>   MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
>>   MMC_CAP_CMD23,
>> @@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
>>   MMC_CAP_CMD23,
>>  };
>>
>> -static const struct dw_mci_drv_data exynos5250_drv_data = {
>> - .caps   = exynos5250_dwmmc_caps,
>> +static const struct dw_mci_drv_data exynos_drv_data = {
>> + .caps   = exynos_dwmmc_caps,
>>   .init   = dw_mci_exynos_priv_init,
>>   .setup_clock= dw_mci_exynos_setup_clock,
>>   .prepare_command= dw_mci_exynos_prepare_command,
>> @@ -219,8 +219,10 @@ static const struct dw_mci_drv_data exynos5250_drv_data 
>> = {
>>  };
>>
>>  static const struct of_device_id dw_mci_exynos_match[] = {
>> + { .compatible = "samsung,exynos4412-dw-mshc",
>> + .data = _drv_data, },
>>   { .compatible = "samsung,exynos5250-dw-mshc",
>> - .data = _drv_data, },
>> + .data = _drv_data, },
>>   {},
>>  };
>>  MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
>> --
>> 1.7.10.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> the body of a message to majord...@vger.kernel.org
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>
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Re: [PATCH v3] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

Hello Seungwon,

Thank you for reviewing and I understand what you mean.

I agree that Exynos5250 and Exynos4412 are not same, no idea how much
they are different because no Exynos5250 spec on my hand. But at least
I assumed that the capabilities below are supported by Exynos4412 in
terms of its datasheet and it does work on my end as expected. :) Also
I assumed it will be separated if one of both become different to add
more capabilities.

MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
   MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,

Maybe my understanding or approach is wrong since I do not have the
information of Exynos5250.
And suggestion do you have?

Regards,
Dongjin.

On Tue, Feb 19, 2013 at 7:19 PM, Seungwon Jeon tgih@samsung.com wrote:
 On Tuesday, February 19, 2013, Dongjin Kim wrote:
 This patch adds the compatible string for MSHC controller of Exynos4412, and
 share the controller specific properties with Exynos5250 since they have same
 features. Its driver data name is changed to exynos_drv_data instead SoC
 specific name.

 It's not actually same.
 Exynos4412 doesn't have forward compatibilities for Exynos5250.
 I agree that functionality of exynos_drv_data is common.
 These functions have been implemented for existing Exynos*.
 But in case of caps, it can't applied completely.
 I'm concerning about this.

 Thanks,
 Seungwon Jeon

 Cc: Jaehoon Chung jh80.ch...@samsung.com
 Cc: Sachin Kamat sachin.ka...@linaro.org
 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
  1 file changed, 7 insertions(+), 5 deletions(-)

 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index 4d50da6..38cd03c 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
   return 0;
  }

 -/* Exynos5250 controller specific capabilities */
 -static unsigned long exynos5250_dwmmc_caps[4] = {
 +/* Exynos4412/Exynos5250 controller specific capabilities */
 +static unsigned long exynos_dwmmc_caps[4] = {
   MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
   MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
   MMC_CAP_CMD23,
 @@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
   MMC_CAP_CMD23,
  };

 -static const struct dw_mci_drv_data exynos5250_drv_data = {
 - .caps   = exynos5250_dwmmc_caps,
 +static const struct dw_mci_drv_data exynos_drv_data = {
 + .caps   = exynos_dwmmc_caps,
   .init   = dw_mci_exynos_priv_init,
   .setup_clock= dw_mci_exynos_setup_clock,
   .prepare_command= dw_mci_exynos_prepare_command,
 @@ -219,8 +219,10 @@ static const struct dw_mci_drv_data exynos5250_drv_data 
 = {
  };

  static const struct of_device_id dw_mci_exynos_match[] = {
 + { .compatible = samsung,exynos4412-dw-mshc,
 + .data = exynos_drv_data, },
   { .compatible = samsung,exynos5250-dw-mshc,
 - .data = exynos5250_drv_data, },
 + .data = exynos_drv_data, },
   {},
  };
  MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
 --
 1.7.10.4

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[PATCH v3] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

This patch adds the compatible string for MSHC controller of Exynos4412, and
share the controller specific properties with Exynos5250 since they have same
features. Its driver data name is changed to exynos_drv_data instead SoC
specific name.

Cc: Jaehoon Chung 
Cc: Sachin Kamat 
Signed-off-by: Dongjin Kim 
---
 drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 4d50da6..38cd03c 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
return 0;
 }
 
-/* Exynos5250 controller specific capabilities */
-static unsigned long exynos5250_dwmmc_caps[4] = {
+/* Exynos4412/Exynos5250 controller specific capabilities */
+static unsigned long exynos_dwmmc_caps[4] = {
MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
MMC_CAP_CMD23,
@@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
MMC_CAP_CMD23,
 };
 
-static const struct dw_mci_drv_data exynos5250_drv_data = {
-   .caps   = exynos5250_dwmmc_caps,
+static const struct dw_mci_drv_data exynos_drv_data = {
+   .caps   = exynos_dwmmc_caps,
.init   = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
.prepare_command= dw_mci_exynos_prepare_command,
@@ -219,8 +219,10 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
 };
 
 static const struct of_device_id dw_mci_exynos_match[] = {
+   { .compatible = "samsung,exynos4412-dw-mshc",
+   .data = _drv_data, },
{ .compatible = "samsung,exynos5250-dw-mshc",
-   .data = _drv_data, },
+   .data = _drv_data, },
{},
 };
 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
-- 
1.7.10.4

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[PATCH v3] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

This patch adds the compatible string for MSHC controller of Exynos4412, and
share the controller specific properties with Exynos5250 since they have same
features. Its driver data name is changed to exynos_drv_data instead SoC
specific name.

Cc: Jaehoon Chung jh80.ch...@samsung.com
Cc: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 4d50da6..38cd03c 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
return 0;
 }
 
-/* Exynos5250 controller specific capabilities */
-static unsigned long exynos5250_dwmmc_caps[4] = {
+/* Exynos4412/Exynos5250 controller specific capabilities */
+static unsigned long exynos_dwmmc_caps[4] = {
MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
MMC_CAP_CMD23,
@@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
MMC_CAP_CMD23,
 };
 
-static const struct dw_mci_drv_data exynos5250_drv_data = {
-   .caps   = exynos5250_dwmmc_caps,
+static const struct dw_mci_drv_data exynos_drv_data = {
+   .caps   = exynos_dwmmc_caps,
.init   = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
.prepare_command= dw_mci_exynos_prepare_command,
@@ -219,8 +219,10 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
 };
 
 static const struct of_device_id dw_mci_exynos_match[] = {
+   { .compatible = samsung,exynos4412-dw-mshc,
+   .data = exynos_drv_data, },
{ .compatible = samsung,exynos5250-dw-mshc,
-   .data = exynos5250_drv_data, },
+   .data = exynos_drv_data, },
{},
 };
 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
-- 
1.7.10.4

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Re: [PATCH] mmc: dw_mmc: No bus setup if default pinctrl is used

[Dongjin Kim]

Hi Linus,

Thank you for reviewing.

Initially I also considered to use IS_ENABLED(CONFIG_PINCTRL) and
ignore for-block according to its status. But it would make a certain
board failed if gpios is used for pin configuration rather than
default-pinctrl even if CONFIG_PINCTRL is enabled. Also considered to
add a function on pinctrl.c to return if default-pinctrl is used, and
drop down the for-block according to its status. It could replace the
long and complicaed line, IS_ERR(host->dev->pins->default_state), to
simple one as well. :)

The best is obviously to enable CONFIG_PINCTRL and remove the
for-block, it makes the code more simple. I like to have a comment
from Thomas if have to support both cases, gpios and default-pinctrl.

Best regards,
Dongjin.

On Fri, Feb 8, 2013 at 4:03 AM, Linus Walleij  wrote:
> On Thu, Feb 7, 2013 at 7:17 PM, Dongjin Kim  wrote:
>
>> Legacy gpio based bus setup is failed when the bus pins are listed with the
>> property 'pinctrl-0' and 'pinctrl-names', instead of 'gpios'. The default
>> pinctrls are handled by device core before probe, no need to configure the
>> pins again in a device driver.
>
> Aha.
>
>>  {
>> int idx, gpio, ret;
>> +   int nr_pins = NUM_PINS(bus_width);
>>
>> if (!slot_np)
>> return -EINVAL;
>>
>> +#if defined(CONFIG_PINCTRL)
>> +   /* Default pinctrl is used */
>> +   if (!IS_ERR(host->dev->pins->default_state))
>> +   nr_pins = 0;
>> +#endif
>
> Use:
>
> if (IS_ENABLED(CONFIG_PINCTRL))
>nr_pins = 0;
>
> Without ifdefs. Grep kernel for examples.
> Read  for explanations.
>
> Put a comment above this to explain exactly why
> you do this.
>
>> +
>> /* cmd + clock + bus-width pins */
>> -   for (idx = 0; idx < NUM_PINS(bus_width); idx++) {
>> +   for (idx = 0; idx < nr_pins; idx++) {
>> gpio = of_get_gpio(slot_np, idx);
>> if (!gpio_is_valid(gpio)) {
>> dev_err(host->dev, "invalid gpio: %d\n", gpio);
>
> This looks kludgy, is it so that the driver falls back to GPIO
> if it cannot use pinctrl? Can't it just depend on CONFIG_PINCTRL
> in Kconfig or do you absolutely have to support both cases?
>
> I was under the impression that the Exynos requires pinctrl.
>
> Yours,
> Linus Walleij
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[PATCH] mmc: dw_mmc: No bus setup if default pinctrl is used

[Dongjin Kim]

Legacy gpio based bus setup is failed when the bus pins are listed with the
property 'pinctrl-0' and 'pinctrl-names', instead of 'gpios'. The default
pinctrls are handled by device core before probe, no need to configure the
pins again in a device driver.

[1.19] Synopsys Designware Multimedia Card Interface Driver
[1.195000] dwmmc_exynos 1255.mshc: Using PIO mode.
[1.20] dwmmc_exynos 1255.mshc: DW MMC controller at irq 109, 32 bit 
host data width, 128 deep fifo
[1.21] dwmmc_exynos 1255.mshc: invalid gpio: -2
[1.215000] dwmmc_exynos: probe of 1255.mshc failed with error -22

Cc: Thomas Abraham 
Cc: Linus Walleij 
Signed-off-by: Dongjin Kim 
---
 drivers/mmc/host/dw_mmc-exynos.c |9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index aafd485..f568c32 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -156,12 +156,19 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
struct device_node *slot_np, u8 bus_width)
 {
int idx, gpio, ret;
+   int nr_pins = NUM_PINS(bus_width);
 
if (!slot_np)
return -EINVAL;
 
+#if defined(CONFIG_PINCTRL)
+   /* Default pinctrl is used */
+   if (!IS_ERR(host->dev->pins->default_state))
+   nr_pins = 0;
+#endif
+
/* cmd + clock + bus-width pins */
-   for (idx = 0; idx < NUM_PINS(bus_width); idx++) {
+   for (idx = 0; idx < nr_pins; idx++) {
gpio = of_get_gpio(slot_np, idx);
if (!gpio_is_valid(gpio)) {
dev_err(host->dev, "invalid gpio: %d\n", gpio);
-- 
1.7.10.4

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[PATCH] mmc: dw_mmc: No bus setup if default pinctrl is used

[Dongjin Kim]

Legacy gpio based bus setup is failed when the bus pins are listed with the
property 'pinctrl-0' and 'pinctrl-names', instead of 'gpios'. The default
pinctrls are handled by device core before probe, no need to configure the
pins again in a device driver.

[1.19] Synopsys Designware Multimedia Card Interface Driver
[1.195000] dwmmc_exynos 1255.mshc: Using PIO mode.
[1.20] dwmmc_exynos 1255.mshc: DW MMC controller at irq 109, 32 bit 
host data width, 128 deep fifo
[1.21] dwmmc_exynos 1255.mshc: invalid gpio: -2
[1.215000] dwmmc_exynos: probe of 1255.mshc failed with error -22

Cc: Thomas Abraham thomas...@samsung.com
Cc: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 drivers/mmc/host/dw_mmc-exynos.c |9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index aafd485..f568c32 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -156,12 +156,19 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
struct device_node *slot_np, u8 bus_width)
 {
int idx, gpio, ret;
+   int nr_pins = NUM_PINS(bus_width);
 
if (!slot_np)
return -EINVAL;
 
+#if defined(CONFIG_PINCTRL)
+   /* Default pinctrl is used */
+   if (!IS_ERR(host-dev-pins-default_state))
+   nr_pins = 0;
+#endif
+
/* cmd + clock + bus-width pins */
-   for (idx = 0; idx  NUM_PINS(bus_width); idx++) {
+   for (idx = 0; idx  nr_pins; idx++) {
gpio = of_get_gpio(slot_np, idx);
if (!gpio_is_valid(gpio)) {
dev_err(host-dev, invalid gpio: %d\n, gpio);
-- 
1.7.10.4

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Re: [PATCH] mmc: dw_mmc: No bus setup if default pinctrl is used

[Dongjin Kim]

Hi Linus,

Thank you for reviewing.

Initially I also considered to use IS_ENABLED(CONFIG_PINCTRL) and
ignore for-block according to its status. But it would make a certain
board failed if gpios is used for pin configuration rather than
default-pinctrl even if CONFIG_PINCTRL is enabled. Also considered to
add a function on pinctrl.c to return if default-pinctrl is used, and
drop down the for-block according to its status. It could replace the
long and complicaed line, IS_ERR(host-dev-pins-default_state), to
simple one as well. :)

The best is obviously to enable CONFIG_PINCTRL and remove the
for-block, it makes the code more simple. I like to have a comment
from Thomas if have to support both cases, gpios and default-pinctrl.

Best regards,
Dongjin.

On Fri, Feb 8, 2013 at 4:03 AM, Linus Walleij linus.wall...@linaro.org wrote:
 On Thu, Feb 7, 2013 at 7:17 PM, Dongjin Kim tobet...@gmail.com wrote:

 Legacy gpio based bus setup is failed when the bus pins are listed with the
 property 'pinctrl-0' and 'pinctrl-names', instead of 'gpios'. The default
 pinctrls are handled by device core before probe, no need to configure the
 pins again in a device driver.

 Aha.

  {
 int idx, gpio, ret;
 +   int nr_pins = NUM_PINS(bus_width);

 if (!slot_np)
 return -EINVAL;

 +#if defined(CONFIG_PINCTRL)
 +   /* Default pinctrl is used */
 +   if (!IS_ERR(host-dev-pins-default_state))
 +   nr_pins = 0;
 +#endif

 Use:

 if (IS_ENABLED(CONFIG_PINCTRL))
nr_pins = 0;

 Without ifdefs. Grep kernel for examples.
 Read linux/kconfig.h for explanations.

 Put a comment above this to explain exactly why
 you do this.

 +
 /* cmd + clock + bus-width pins */
 -   for (idx = 0; idx  NUM_PINS(bus_width); idx++) {
 +   for (idx = 0; idx  nr_pins; idx++) {
 gpio = of_get_gpio(slot_np, idx);
 if (!gpio_is_valid(gpio)) {
 dev_err(host-dev, invalid gpio: %d\n, gpio);

 This looks kludgy, is it so that the driver falls back to GPIO
 if it cannot use pinctrl? Can't it just depend on CONFIG_PINCTRL
 in Kconfig or do you absolutely have to support both cases?

 I was under the impression that the Exynos requires pinctrl.

 Yours,
 Linus Walleij
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Re: [PATCH 1/2] usb: phy: Add USB host phy support on Exyno4412

[Dongjin Kim]

Hello Praveen,

Thank you for reviewing.
I was also considered to use TYPE_4X12, but in some other thread some
people prefer to use 4412 instead of 4X12 because no 4212 based
hardware yet. :)
Anyway, TYPE_4X12 is also fine to me.

And as you pointed out about PHY0, while testing my patch with my
hardware I also wondered why PHY0 has to be enabled. Unless USBPHY its
status was monitored as "halted" it didn't work at all. Now I find the
reason that the first is power for USB block is wrong (not stable) and
the second is when the hardware is initialized at first, like power
up, URSTCON's initial value is 0x79, which means HSIC0, HSIC1, PHY1
and OTG is in reset state. So it has to be released before USB starts.
So I am finding the good place to initiate URSTCON properly, u-boot or
kernel itself.

Do you have any advice on this?

Thank you again.
Dongjin.

On Tue, Feb 5, 2013 at 11:38 PM, Praveen Paneri  wrote:
>
> Hi,
>
> On Tue, Feb 5, 2013 at 6:55 AM, Dongjin Kim  wrote:
> > This patch adds host phy support for Samsung's Exynos4412 SoC to
> > samsung-usbphy driver. This patch is created upon
> > "http://git.kernel.org/?p=linux/kernel/git/balbi/usb.git;a=commit;h=2564b526b8cf01e6c36285edfd40a438e683c2b8;
> >
> > Cc: Praveen Paneri 
> > Signed-off-by: Dongjin Kim 
> > ---
> >  drivers/usb/phy/samsung-usbphy.c |  156
> > +-
> >  1 file changed, 154 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/usb/phy/samsung-usbphy.c
> > b/drivers/usb/phy/samsung-usbphy.c
> > index 6ea5537..c800fa4 100644
> > --- a/drivers/usb/phy/samsung-usbphy.c
> > +++ b/drivers/usb/phy/samsung-usbphy.c
> > @@ -47,7 +47,7 @@
> >
> >  #define PHYCLK_MODE_USB11  (0x1 << 6)
> >  #define PHYCLK_EXT_OSC (0x1 << 5)
> > -#define PHYCLK_COMMON_ON_N (0x1 << 4)
> > +#define PHYCLK_COMMON_ON_N_PHY0(0x1 << 4)
> >  #define PHYCLK_ID_PULL (0x1 << 2)
> >  #define PHYCLK_CLKSEL_MASK (0x3 << 0)
> >  #define PHYCLK_CLKSEL_48M  (0x0 << 0)
> > @@ -60,6 +60,22 @@
> >  #define RSTCON_HLINK_SWRST (0x1 << 1)
> >  #define RSTCON_SWRST   (0x1 << 0)
> >
> > +/* For Exynos4412 */
> > +#define PHYCLK_COMMON_ON_N_PHY1(0x1 << 7)
> > +
> > +#define PHYPWR_NORMAL_MASK_HSIC1   (0x7 << 12)
> > +#define PHYPWR_NORMAL_MASK_HSIC0   (0x7 << 9)
> > +#define PHYPWR_NORMAL_MASK_PHY1(0x7 << 6)
> > +
> > +#define PHYPWR_ANALOG_POWERDOWN_PHY1   (0x1 << 7)
> > +
> > +#define RSTCON_HLINK_SWRST_MASK(0xf << 7)
> > +#define RSTCON_PHY1_SWRST_MASK (0xf << 3)
> > +#define RSTCON_PHY0_SWRST_MASK (0x7 << 0)
> > +
> > +#define EXYNOS4_PHY_HSIC_CTRL0 (0x04)
> > +#define EXYNOS4_PHY_HSIC_CTRL1 (0x08)
> > +
> >  /* EXYNOS5 */
> >  #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
> >
> > @@ -174,6 +190,7 @@
> >  enum samsung_cpu_type {
> > TYPE_S3C64XX,
> > TYPE_EXYNOS4210,
> > +   TYPE_EXYNOS4412,
> Shouldn't you add it under the TYPE_EXYNOS4X12. We will have to add a
> separate support for 4212 then.
> > TYPE_EXYNOS5250,
> >  };
> >
> > @@ -322,6 +339,17 @@ static void samsung_usbphy_set_isolation(struct
> > samsung_usbphy *sphy, bool on)
> > en_mask = sphy->drv_data->hostphy_en_mask;
> > }
> > break;
> > +   case TYPE_EXYNOS4412:
> > +   if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
> > +   reg = sphy->pmuregs +
> > +   sphy->drv_data->devphy_reg_offset;
> > +   en_mask = sphy->drv_data->devphy_en_mask;
> > +   } else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
> > +   reg = sphy->pmuregs +
> > +   sphy->drv_data->hostphy_reg_offset;
> > +   en_mask = sphy->drv_data->hostphy_en_mask;
> > +   }
> > +   break;
> > default:
> > dev_err(sphy->dev, "Invalid SoC type\n");
> > return;
> > @@ -422,6 +450,29 @@ static int samsung_usb

Re: [PATCH 1/2] usb: phy: Add USB host phy support on Exyno4412

[Dongjin Kim]

Hello Praveen,

Thank you for reviewing.
I was also considered to use TYPE_4X12, but in some other thread some
people prefer to use 4412 instead of 4X12 because no 4212 based
hardware yet. :)
Anyway, TYPE_4X12 is also fine to me.

And as you pointed out about PHY0, while testing my patch with my
hardware I also wondered why PHY0 has to be enabled. Unless USBPHY its
status was monitored as halted it didn't work at all. Now I find the
reason that the first is power for USB block is wrong (not stable) and
the second is when the hardware is initialized at first, like power
up, URSTCON's initial value is 0x79, which means HSIC0, HSIC1, PHY1
and OTG is in reset state. So it has to be released before USB starts.
So I am finding the good place to initiate URSTCON properly, u-boot or
kernel itself.

Do you have any advice on this?

Thank you again.
Dongjin.

On Tue, Feb 5, 2013 at 11:38 PM, Praveen Paneri p.pan...@samsung.com wrote:

 Hi,

 On Tue, Feb 5, 2013 at 6:55 AM, Dongjin Kim tobet...@gmail.com wrote:
  This patch adds host phy support for Samsung's Exynos4412 SoC to
  samsung-usbphy driver. This patch is created upon
  http://git.kernel.org/?p=linux/kernel/git/balbi/usb.git;a=commit;h=2564b526b8cf01e6c36285edfd40a438e683c2b8;
 
  Cc: Praveen Paneri p.pan...@samsung.com
  Signed-off-by: Dongjin Kim tobet...@gmail.com
  ---
   drivers/usb/phy/samsung-usbphy.c |  156
  +-
   1 file changed, 154 insertions(+), 2 deletions(-)
 
  diff --git a/drivers/usb/phy/samsung-usbphy.c
  b/drivers/usb/phy/samsung-usbphy.c
  index 6ea5537..c800fa4 100644
  --- a/drivers/usb/phy/samsung-usbphy.c
  +++ b/drivers/usb/phy/samsung-usbphy.c
  @@ -47,7 +47,7 @@
 
   #define PHYCLK_MODE_USB11  (0x1  6)
   #define PHYCLK_EXT_OSC (0x1  5)
  -#define PHYCLK_COMMON_ON_N (0x1  4)
  +#define PHYCLK_COMMON_ON_N_PHY0(0x1  4)
   #define PHYCLK_ID_PULL (0x1  2)
   #define PHYCLK_CLKSEL_MASK (0x3  0)
   #define PHYCLK_CLKSEL_48M  (0x0  0)
  @@ -60,6 +60,22 @@
   #define RSTCON_HLINK_SWRST (0x1  1)
   #define RSTCON_SWRST   (0x1  0)
 
  +/* For Exynos4412 */
  +#define PHYCLK_COMMON_ON_N_PHY1(0x1  7)
  +
  +#define PHYPWR_NORMAL_MASK_HSIC1   (0x7  12)
  +#define PHYPWR_NORMAL_MASK_HSIC0   (0x7  9)
  +#define PHYPWR_NORMAL_MASK_PHY1(0x7  6)
  +
  +#define PHYPWR_ANALOG_POWERDOWN_PHY1   (0x1  7)
  +
  +#define RSTCON_HLINK_SWRST_MASK(0xf  7)
  +#define RSTCON_PHY1_SWRST_MASK (0xf  3)
  +#define RSTCON_PHY0_SWRST_MASK (0x7  0)
  +
  +#define EXYNOS4_PHY_HSIC_CTRL0 (0x04)
  +#define EXYNOS4_PHY_HSIC_CTRL1 (0x08)
  +
   /* EXYNOS5 */
   #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
 
  @@ -174,6 +190,7 @@
   enum samsung_cpu_type {
  TYPE_S3C64XX,
  TYPE_EXYNOS4210,
  +   TYPE_EXYNOS4412,
 Shouldn't you add it under the TYPE_EXYNOS4X12. We will have to add a
 separate support for 4212 then.
  TYPE_EXYNOS5250,
   };
 
  @@ -322,6 +339,17 @@ static void samsung_usbphy_set_isolation(struct
  samsung_usbphy *sphy, bool on)
  en_mask = sphy-drv_data-hostphy_en_mask;
  }
  break;
  +   case TYPE_EXYNOS4412:
  +   if (sphy-phy_type == USB_PHY_TYPE_DEVICE) {
  +   reg = sphy-pmuregs +
  +   sphy-drv_data-devphy_reg_offset;
  +   en_mask = sphy-drv_data-devphy_en_mask;
  +   } else if (sphy-phy_type == USB_PHY_TYPE_HOST) {
  +   reg = sphy-pmuregs +
  +   sphy-drv_data-hostphy_reg_offset;
  +   en_mask = sphy-drv_data-hostphy_en_mask;
  +   }
  +   break;
  default:
  dev_err(sphy-dev, Invalid SoC type\n);
  return;
  @@ -422,6 +450,29 @@ static int samsung_usbphy_get_refclk_freq(struct
  samsung_usbphy *sphy)
  refclk_freq = FSEL_CLKSEL_24M;
  break;
  }
  +   } else if (sphy-drv_data-cpu_type == TYPE_EXYNOS4412) {
  +   switch (clk_get_rate(ref_clk)) {
  +   case 9600 * KHZ:
  +   refclk_freq = FSEL_CLKSEL_9600K;
  +   break;
  +   case 10 * MHZ:
  +   refclk_freq = FSEL_CLKSEL_10M;
  +   break;
  +   case 12 * MHZ:
  +   refclk_freq = FSEL_CLKSEL_12M;
  +   break;
  +   case 19200 * KHZ:
  +   refclk_freq = FSEL_CLKSEL_19200K;
  +   break;
  +   case

[PATCH 2/2] ARM: dts: Add USBPHY device node for Exynos4412

[Dongjin Kim]

This patch adds USBPHY device node for Samsung's Exynos4412 SoC to
arch/arm/boot/dts/exynos4412.dtsi.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4412.dtsi |   13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
b/arch/arm/boot/dts/exynos4412.dtsi
index 387aa27..c01d841 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -33,4 +33,17 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   usbphy@125B {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "samsung,exynos4412-usbphy";
+   reg = <0x125B 0x100>;
+   status = "disabled";
+   ranges;
+
+   usbphy-sys {
+   reg = <0x10020704 0xc>;
+   };
+   };
 };
-- 
1.7.10.4

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[PATCH 1/2] usb: phy: Add USB host phy support on Exyno4412

[Dongjin Kim]

This patch adds host phy support for Samsung's Exynos4412 SoC to
samsung-usbphy driver. This patch is created upon 
"http://git.kernel.org/?p=linux/kernel/git/balbi/usb.git;a=commit;h=2564b526b8cf01e6c36285edfd40a438e683c2b8;

Cc: Praveen Paneri 
Signed-off-by: Dongjin Kim 
---
 drivers/usb/phy/samsung-usbphy.c |  156 +-
 1 file changed, 154 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
index 6ea5537..c800fa4 100644
--- a/drivers/usb/phy/samsung-usbphy.c
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -47,7 +47,7 @@
 
 #define PHYCLK_MODE_USB11  (0x1 << 6)
 #define PHYCLK_EXT_OSC (0x1 << 5)
-#define PHYCLK_COMMON_ON_N (0x1 << 4)
+#define PHYCLK_COMMON_ON_N_PHY0(0x1 << 4)
 #define PHYCLK_ID_PULL (0x1 << 2)
 #define PHYCLK_CLKSEL_MASK (0x3 << 0)
 #define PHYCLK_CLKSEL_48M  (0x0 << 0)
@@ -60,6 +60,22 @@
 #define RSTCON_HLINK_SWRST (0x1 << 1)
 #define RSTCON_SWRST   (0x1 << 0)
 
+/* For Exynos4412 */
+#define PHYCLK_COMMON_ON_N_PHY1(0x1 << 7)
+
+#define PHYPWR_NORMAL_MASK_HSIC1   (0x7 << 12)
+#define PHYPWR_NORMAL_MASK_HSIC0   (0x7 << 9)
+#define PHYPWR_NORMAL_MASK_PHY1(0x7 << 6)
+
+#define PHYPWR_ANALOG_POWERDOWN_PHY1   (0x1 << 7)
+
+#define RSTCON_HLINK_SWRST_MASK(0xf << 7)
+#define RSTCON_PHY1_SWRST_MASK (0xf << 3)
+#define RSTCON_PHY0_SWRST_MASK (0x7 << 0)
+
+#define EXYNOS4_PHY_HSIC_CTRL0 (0x04)
+#define EXYNOS4_PHY_HSIC_CTRL1 (0x08)
+
 /* EXYNOS5 */
 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
 
@@ -174,6 +190,7 @@
 enum samsung_cpu_type {
TYPE_S3C64XX,
TYPE_EXYNOS4210,
+   TYPE_EXYNOS4412,
TYPE_EXYNOS5250,
 };
 
@@ -322,6 +339,17 @@ static void samsung_usbphy_set_isolation(struct 
samsung_usbphy *sphy, bool on)
en_mask = sphy->drv_data->hostphy_en_mask;
}
break;
+   case TYPE_EXYNOS4412:
+   if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
+   reg = sphy->pmuregs +
+   sphy->drv_data->devphy_reg_offset;
+   en_mask = sphy->drv_data->devphy_en_mask;
+   } else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
+   reg = sphy->pmuregs +
+   sphy->drv_data->hostphy_reg_offset;
+   en_mask = sphy->drv_data->hostphy_en_mask;
+   }
+   break;
default:
dev_err(sphy->dev, "Invalid SoC type\n");
return;
@@ -422,6 +450,29 @@ static int samsung_usbphy_get_refclk_freq(struct 
samsung_usbphy *sphy)
refclk_freq = FSEL_CLKSEL_24M;
break;
}
+   } else if (sphy->drv_data->cpu_type == TYPE_EXYNOS4412) {
+   switch (clk_get_rate(ref_clk)) {
+   case 9600 * KHZ:
+   refclk_freq = FSEL_CLKSEL_9600K;
+   break;
+   case 10 * MHZ:
+   refclk_freq = FSEL_CLKSEL_10M;
+   break;
+   case 12 * MHZ:
+   refclk_freq = FSEL_CLKSEL_12M;
+   break;
+   case 19200 * KHZ:
+   refclk_freq = FSEL_CLKSEL_19200K;
+   break;
+   case 20 * MHZ:
+   refclk_freq = FSEL_CLKSEL_20M;
+   break;
+   case 24 * MHZ:
+   default:
+   /* default reference clock */
+   refclk_freq = FSEL_CLKSEL_24M;
+   break;
+   }
} else {
switch (clk_get_rate(ref_clk)) {
case 12 * MHZ:
@@ -561,6 +612,69 @@ static void samsung_exynos5_usbphy_enable(struct 
samsung_usbphy *sphy)
writel(ohcictrl, regs + EXYNOS5_PHY_HOST_OHCICTRL);
 }
 
+static bool exynos4_phyhost_is_on(void *regs)
+{
+   u32 reg;
+
+   reg = readl(regs + SAMSUNG_PHYPWR);
+
+   return !(reg & PHYPWR_ANALOG_POWERDOWN_PHY1);
+}
+
+static void samsung_exynos4412_usbphy_enable(struct samsung_usbphy *sphy)
+{
+   void __iomem *regs = sphy->regs;
+   u32 phypwr;
+   u32 phyclk;
+   u32 rstcon;
+
+   /*
+* phy_usage helps in keeping usage count for phy
+* so that the first consumer enabling the phy is also
+* the last consumer to disable it.
+

[PATCH] ARM: dts: Fix the timing property of MSHC controller

[Dongjin Kim]

This fixes the property of dw-mshc-sdr-timing and dw-mshc-ddr-timing as per
its current binding, it only has two cells.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index f41a84e..009a9c2 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -49,8 +49,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
-   samsung,dw-mshc-sdr-timing = <2 3 3>;
-   samsung,dw-mshc-ddr-timing = <1 2 3>;
+   samsung,dw-mshc-sdr-timing = <2 3>;
+   samsung,dw-mshc-ddr-timing = <1 2>;
 
slot@0 {
reg = <0>;
-- 
1.7.10.4

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[PATCH] ARM: dts: Adding RTC device node

[Dongjin Kim]

This patch enables RTC device node defined in arch/arm/boot/dts/exynos4.dtsi.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 54fe32f..85c958a 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -83,6 +83,10 @@
regulator-boot-on;
};
 
+   rtc@1007 {
+   status = "okay";
+   };
+
sdhci@1253 {
bus-width = <4>;
pinctrl-0 = <_clk _cmd _cd _bus4>;
-- 
1.7.10.4

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[PATCH] usb: phy: Add USB host phy support on Exyno4412

[Dongjin Kim]

This patch adds host phy support for Samsung's Exynos4412 SoC to
samsung-usbphy driver and its device node.

Cc: Praveen Paneri 
Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4412.dtsi |   13 
 drivers/usb/phy/samsung-usbphy.c  |  156 -
 2 files changed, 167 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
b/arch/arm/boot/dts/exynos4412.dtsi
index 387aa27..c01d841 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -33,4 +33,17 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   usbphy@125B {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "samsung,exynos4412-usbphy";
+   reg = <0x125B 0x100>;
+   status = "disabled";
+   ranges;
+
+   usbphy-sys {
+   reg = <0x10020704 0xc>;
+   };
+   };
 };
diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
index 6ea5537..c800fa4 100644
--- a/drivers/usb/phy/samsung-usbphy.c
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -47,7 +47,7 @@
 
 #define PHYCLK_MODE_USB11  (0x1 << 6)
 #define PHYCLK_EXT_OSC (0x1 << 5)
-#define PHYCLK_COMMON_ON_N (0x1 << 4)
+#define PHYCLK_COMMON_ON_N_PHY0(0x1 << 4)
 #define PHYCLK_ID_PULL (0x1 << 2)
 #define PHYCLK_CLKSEL_MASK (0x3 << 0)
 #define PHYCLK_CLKSEL_48M  (0x0 << 0)
@@ -60,6 +60,22 @@
 #define RSTCON_HLINK_SWRST (0x1 << 1)
 #define RSTCON_SWRST   (0x1 << 0)
 
+/* For Exynos4412 */
+#define PHYCLK_COMMON_ON_N_PHY1(0x1 << 7)
+
+#define PHYPWR_NORMAL_MASK_HSIC1   (0x7 << 12)
+#define PHYPWR_NORMAL_MASK_HSIC0   (0x7 << 9)
+#define PHYPWR_NORMAL_MASK_PHY1(0x7 << 6)
+
+#define PHYPWR_ANALOG_POWERDOWN_PHY1   (0x1 << 7)
+
+#define RSTCON_HLINK_SWRST_MASK(0xf << 7)
+#define RSTCON_PHY1_SWRST_MASK (0xf << 3)
+#define RSTCON_PHY0_SWRST_MASK (0x7 << 0)
+
+#define EXYNOS4_PHY_HSIC_CTRL0 (0x04)
+#define EXYNOS4_PHY_HSIC_CTRL1 (0x08)
+
 /* EXYNOS5 */
 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
 
@@ -174,6 +190,7 @@
 enum samsung_cpu_type {
TYPE_S3C64XX,
TYPE_EXYNOS4210,
+   TYPE_EXYNOS4412,
TYPE_EXYNOS5250,
 };
 
@@ -322,6 +339,17 @@ static void samsung_usbphy_set_isolation(struct 
samsung_usbphy *sphy, bool on)
en_mask = sphy->drv_data->hostphy_en_mask;
}
break;
+   case TYPE_EXYNOS4412:
+   if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
+   reg = sphy->pmuregs +
+   sphy->drv_data->devphy_reg_offset;
+   en_mask = sphy->drv_data->devphy_en_mask;
+   } else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
+   reg = sphy->pmuregs +
+   sphy->drv_data->hostphy_reg_offset;
+   en_mask = sphy->drv_data->hostphy_en_mask;
+   }
+   break;
default:
dev_err(sphy->dev, "Invalid SoC type\n");
return;
@@ -422,6 +450,29 @@ static int samsung_usbphy_get_refclk_freq(struct 
samsung_usbphy *sphy)
refclk_freq = FSEL_CLKSEL_24M;
break;
}
+   } else if (sphy->drv_data->cpu_type == TYPE_EXYNOS4412) {
+   switch (clk_get_rate(ref_clk)) {
+   case 9600 * KHZ:
+   refclk_freq = FSEL_CLKSEL_9600K;
+   break;
+   case 10 * MHZ:
+   refclk_freq = FSEL_CLKSEL_10M;
+   break;
+   case 12 * MHZ:
+   refclk_freq = FSEL_CLKSEL_12M;
+   break;
+   case 19200 * KHZ:
+   refclk_freq = FSEL_CLKSEL_19200K;
+   break;
+   case 20 * MHZ:
+   refclk_freq = FSEL_CLKSEL_20M;
+   break;
+   case 24 * MHZ:
+   default:
+   /* default reference clock */
+   refclk_freq = FSEL_CLKSEL_24M;
+   break;
+   }
} else {
switch (clk_get_rate(ref_clk)) {
case 12 * MHZ:
@@ -561,6 +612,69 @@ static void samsung_exynos5_

[PATCH] usb: phy: Add USB host phy support on Exyno4412

[Dongjin Kim]

This patch adds host phy support for Samsung's Exynos4412 SoC to
samsung-usbphy driver and its device node.

Cc: Praveen Paneri p.pan...@samsung.com
Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4412.dtsi |   13 
 drivers/usb/phy/samsung-usbphy.c  |  156 -
 2 files changed, 167 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
b/arch/arm/boot/dts/exynos4412.dtsi
index 387aa27..c01d841 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -33,4 +33,17 @@
#address-cells = 1;
#size-cells = 0;
};
+
+   usbphy@125B {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = samsung,exynos4412-usbphy;
+   reg = 0x125B 0x100;
+   status = disabled;
+   ranges;
+
+   usbphy-sys {
+   reg = 0x10020704 0xc;
+   };
+   };
 };
diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
index 6ea5537..c800fa4 100644
--- a/drivers/usb/phy/samsung-usbphy.c
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -47,7 +47,7 @@
 
 #define PHYCLK_MODE_USB11  (0x1  6)
 #define PHYCLK_EXT_OSC (0x1  5)
-#define PHYCLK_COMMON_ON_N (0x1  4)
+#define PHYCLK_COMMON_ON_N_PHY0(0x1  4)
 #define PHYCLK_ID_PULL (0x1  2)
 #define PHYCLK_CLKSEL_MASK (0x3  0)
 #define PHYCLK_CLKSEL_48M  (0x0  0)
@@ -60,6 +60,22 @@
 #define RSTCON_HLINK_SWRST (0x1  1)
 #define RSTCON_SWRST   (0x1  0)
 
+/* For Exynos4412 */
+#define PHYCLK_COMMON_ON_N_PHY1(0x1  7)
+
+#define PHYPWR_NORMAL_MASK_HSIC1   (0x7  12)
+#define PHYPWR_NORMAL_MASK_HSIC0   (0x7  9)
+#define PHYPWR_NORMAL_MASK_PHY1(0x7  6)
+
+#define PHYPWR_ANALOG_POWERDOWN_PHY1   (0x1  7)
+
+#define RSTCON_HLINK_SWRST_MASK(0xf  7)
+#define RSTCON_PHY1_SWRST_MASK (0xf  3)
+#define RSTCON_PHY0_SWRST_MASK (0x7  0)
+
+#define EXYNOS4_PHY_HSIC_CTRL0 (0x04)
+#define EXYNOS4_PHY_HSIC_CTRL1 (0x08)
+
 /* EXYNOS5 */
 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
 
@@ -174,6 +190,7 @@
 enum samsung_cpu_type {
TYPE_S3C64XX,
TYPE_EXYNOS4210,
+   TYPE_EXYNOS4412,
TYPE_EXYNOS5250,
 };
 
@@ -322,6 +339,17 @@ static void samsung_usbphy_set_isolation(struct 
samsung_usbphy *sphy, bool on)
en_mask = sphy-drv_data-hostphy_en_mask;
}
break;
+   case TYPE_EXYNOS4412:
+   if (sphy-phy_type == USB_PHY_TYPE_DEVICE) {
+   reg = sphy-pmuregs +
+   sphy-drv_data-devphy_reg_offset;
+   en_mask = sphy-drv_data-devphy_en_mask;
+   } else if (sphy-phy_type == USB_PHY_TYPE_HOST) {
+   reg = sphy-pmuregs +
+   sphy-drv_data-hostphy_reg_offset;
+   en_mask = sphy-drv_data-hostphy_en_mask;
+   }
+   break;
default:
dev_err(sphy-dev, Invalid SoC type\n);
return;
@@ -422,6 +450,29 @@ static int samsung_usbphy_get_refclk_freq(struct 
samsung_usbphy *sphy)
refclk_freq = FSEL_CLKSEL_24M;
break;
}
+   } else if (sphy-drv_data-cpu_type == TYPE_EXYNOS4412) {
+   switch (clk_get_rate(ref_clk)) {
+   case 9600 * KHZ:
+   refclk_freq = FSEL_CLKSEL_9600K;
+   break;
+   case 10 * MHZ:
+   refclk_freq = FSEL_CLKSEL_10M;
+   break;
+   case 12 * MHZ:
+   refclk_freq = FSEL_CLKSEL_12M;
+   break;
+   case 19200 * KHZ:
+   refclk_freq = FSEL_CLKSEL_19200K;
+   break;
+   case 20 * MHZ:
+   refclk_freq = FSEL_CLKSEL_20M;
+   break;
+   case 24 * MHZ:
+   default:
+   /* default reference clock */
+   refclk_freq = FSEL_CLKSEL_24M;
+   break;
+   }
} else {
switch (clk_get_rate(ref_clk)) {
case 12 * MHZ:
@@ -561,6 +612,69 @@ static void samsung_exynos5_usbphy_enable(struct 
samsung_usbphy *sphy)
writel(ohcictrl, regs + EXYNOS5_PHY_HOST_OHCICTRL);
 }
 
+static bool exynos4_phyhost_is_on(void *regs)
+{
+   u32 reg;
+
+   reg = readl(regs + SAMSUNG_PHYPWR);
+
+   return !(reg

[PATCH] ARM: dts: Adding RTC device node

[Dongjin Kim]

This patch enables RTC device node defined in arch/arm/boot/dts/exynos4.dtsi.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 54fe32f..85c958a 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -83,6 +83,10 @@
regulator-boot-on;
};
 
+   rtc@1007 {
+   status = okay;
+   };
+
sdhci@1253 {
bus-width = 4;
pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus4;
-- 
1.7.10.4

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[PATCH] ARM: dts: Fix the timing property of MSHC controller

[Dongjin Kim]

This fixes the property of dw-mshc-sdr-timing and dw-mshc-ddr-timing as per
its current binding, it only has two cells.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index f41a84e..009a9c2 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -49,8 +49,8 @@
fifo-depth = 0x80;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
-   samsung,dw-mshc-sdr-timing = 2 3 3;
-   samsung,dw-mshc-ddr-timing = 1 2 3;
+   samsung,dw-mshc-sdr-timing = 2 3;
+   samsung,dw-mshc-ddr-timing = 1 2;
 
slot@0 {
reg = 0;
-- 
1.7.10.4

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[PATCH 1/2] usb: phy: Add USB host phy support on Exyno4412

[Dongjin Kim]

This patch adds host phy support for Samsung's Exynos4412 SoC to
samsung-usbphy driver. This patch is created upon 
http://git.kernel.org/?p=linux/kernel/git/balbi/usb.git;a=commit;h=2564b526b8cf01e6c36285edfd40a438e683c2b8;

Cc: Praveen Paneri p.pan...@samsung.com
Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 drivers/usb/phy/samsung-usbphy.c |  156 +-
 1 file changed, 154 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
index 6ea5537..c800fa4 100644
--- a/drivers/usb/phy/samsung-usbphy.c
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -47,7 +47,7 @@
 
 #define PHYCLK_MODE_USB11  (0x1  6)
 #define PHYCLK_EXT_OSC (0x1  5)
-#define PHYCLK_COMMON_ON_N (0x1  4)
+#define PHYCLK_COMMON_ON_N_PHY0(0x1  4)
 #define PHYCLK_ID_PULL (0x1  2)
 #define PHYCLK_CLKSEL_MASK (0x3  0)
 #define PHYCLK_CLKSEL_48M  (0x0  0)
@@ -60,6 +60,22 @@
 #define RSTCON_HLINK_SWRST (0x1  1)
 #define RSTCON_SWRST   (0x1  0)
 
+/* For Exynos4412 */
+#define PHYCLK_COMMON_ON_N_PHY1(0x1  7)
+
+#define PHYPWR_NORMAL_MASK_HSIC1   (0x7  12)
+#define PHYPWR_NORMAL_MASK_HSIC0   (0x7  9)
+#define PHYPWR_NORMAL_MASK_PHY1(0x7  6)
+
+#define PHYPWR_ANALOG_POWERDOWN_PHY1   (0x1  7)
+
+#define RSTCON_HLINK_SWRST_MASK(0xf  7)
+#define RSTCON_PHY1_SWRST_MASK (0xf  3)
+#define RSTCON_PHY0_SWRST_MASK (0x7  0)
+
+#define EXYNOS4_PHY_HSIC_CTRL0 (0x04)
+#define EXYNOS4_PHY_HSIC_CTRL1 (0x08)
+
 /* EXYNOS5 */
 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
 
@@ -174,6 +190,7 @@
 enum samsung_cpu_type {
TYPE_S3C64XX,
TYPE_EXYNOS4210,
+   TYPE_EXYNOS4412,
TYPE_EXYNOS5250,
 };
 
@@ -322,6 +339,17 @@ static void samsung_usbphy_set_isolation(struct 
samsung_usbphy *sphy, bool on)
en_mask = sphy-drv_data-hostphy_en_mask;
}
break;
+   case TYPE_EXYNOS4412:
+   if (sphy-phy_type == USB_PHY_TYPE_DEVICE) {
+   reg = sphy-pmuregs +
+   sphy-drv_data-devphy_reg_offset;
+   en_mask = sphy-drv_data-devphy_en_mask;
+   } else if (sphy-phy_type == USB_PHY_TYPE_HOST) {
+   reg = sphy-pmuregs +
+   sphy-drv_data-hostphy_reg_offset;
+   en_mask = sphy-drv_data-hostphy_en_mask;
+   }
+   break;
default:
dev_err(sphy-dev, Invalid SoC type\n);
return;
@@ -422,6 +450,29 @@ static int samsung_usbphy_get_refclk_freq(struct 
samsung_usbphy *sphy)
refclk_freq = FSEL_CLKSEL_24M;
break;
}
+   } else if (sphy-drv_data-cpu_type == TYPE_EXYNOS4412) {
+   switch (clk_get_rate(ref_clk)) {
+   case 9600 * KHZ:
+   refclk_freq = FSEL_CLKSEL_9600K;
+   break;
+   case 10 * MHZ:
+   refclk_freq = FSEL_CLKSEL_10M;
+   break;
+   case 12 * MHZ:
+   refclk_freq = FSEL_CLKSEL_12M;
+   break;
+   case 19200 * KHZ:
+   refclk_freq = FSEL_CLKSEL_19200K;
+   break;
+   case 20 * MHZ:
+   refclk_freq = FSEL_CLKSEL_20M;
+   break;
+   case 24 * MHZ:
+   default:
+   /* default reference clock */
+   refclk_freq = FSEL_CLKSEL_24M;
+   break;
+   }
} else {
switch (clk_get_rate(ref_clk)) {
case 12 * MHZ:
@@ -561,6 +612,69 @@ static void samsung_exynos5_usbphy_enable(struct 
samsung_usbphy *sphy)
writel(ohcictrl, regs + EXYNOS5_PHY_HOST_OHCICTRL);
 }
 
+static bool exynos4_phyhost_is_on(void *regs)
+{
+   u32 reg;
+
+   reg = readl(regs + SAMSUNG_PHYPWR);
+
+   return !(reg  PHYPWR_ANALOG_POWERDOWN_PHY1);
+}
+
+static void samsung_exynos4412_usbphy_enable(struct samsung_usbphy *sphy)
+{
+   void __iomem *regs = sphy-regs;
+   u32 phypwr;
+   u32 phyclk;
+   u32 rstcon;
+
+   /*
+* phy_usage helps in keeping usage count for phy
+* so that the first consumer enabling the phy is also
+* the last consumer to disable it.
+*/
+
+   atomic_inc(sphy-phy_usage);
+
+   if (exynos4_phyhost_is_on(regs)) {
+   dev_info(sphy-dev, Already power on PHY\n);
+   return

[PATCH 2/2] ARM: dts: Add USBPHY device node for Exynos4412

[Dongjin Kim]

This patch adds USBPHY device node for Samsung's Exynos4412 SoC to
arch/arm/boot/dts/exynos4412.dtsi.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4412.dtsi |   13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
b/arch/arm/boot/dts/exynos4412.dtsi
index 387aa27..c01d841 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -33,4 +33,17 @@
#address-cells = 1;
#size-cells = 0;
};
+
+   usbphy@125B {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = samsung,exynos4412-usbphy;
+   reg = 0x125B 0x100;
+   status = disabled;
+   ranges;
+
+   usbphy-sys {
+   reg = 0x10020704 0xc;
+   };
+   };
 };
-- 
1.7.10.4

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Re: [PATCH RESEND] ARM: dts: max77686: Add DTS file for max77686 PMIC

[Dongjin Kim]

Hello Mark,

Yes, this is not ARM-specific chip at all. Just wanted to be reviewed
by you and others if the format is ok before integrating to my board
file. I had sent similar one before,
https://patchwork.kernel.org/patch/1287711, and you advised that was
too board specific. And plan to integrate like OMAP boards have with
twl6030.dtsi and twl6040.dtsi.

If would be nice if somewhere you specify a directory for such device files.

Regards,
Dongjin.

On Sat, Jan 26, 2013 at 2:06 PM, Mark Brown
 wrote:
> On Fri, Jan 25, 2013 at 03:46:08AM +0900, Dongjin Kim wrote:
>
>> ---
>>  arch/arm/boot/dts/max77686.dtsi |  156 
>> +++
>
> Why is this in arch/arm?  This isn't an ARM-specific chip.
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[PATCH] USB: misc: usb3503: Fix compiler warning

[Dongjin Kim]

This patch fixes the compiler warning of uninitialized variable.

drivers/usb/misc/usb3503.c: In function ‘usb3503_probe’:
drivers/usb/misc/usb3503.c:215:13: warning: ‘mode’ may be used uninitialized
in this function [-Wuninitialized]

Signed-off-by: Dongjin Kim 
---
 drivers/usb/misc/usb3503.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index 471218a..f713f6a 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -185,7 +185,7 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
struct device_node *np = i2c->dev.of_node;
struct usb3503 *hub;
int err = -ENOMEM;
-   u32 mode;
+   u32 mode = USB3503_MODE_UNKNOWN;
 
hub = kzalloc(sizeof(struct usb3503), GFP_KERNEL);
if (!hub) {
-- 
1.7.10.4

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[PATCH] USB: misc: usb3503: Fix compiler warning

[Dongjin Kim]

This patch fixes the compiler warning of uninitialized variable.

drivers/usb/misc/usb3503.c: In function ‘usb3503_probe’:
drivers/usb/misc/usb3503.c:215:13: warning: ‘mode’ may be used uninitialized
in this function [-Wuninitialized]

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 drivers/usb/misc/usb3503.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index 471218a..f713f6a 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -185,7 +185,7 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
struct device_node *np = i2c-dev.of_node;
struct usb3503 *hub;
int err = -ENOMEM;
-   u32 mode;
+   u32 mode = USB3503_MODE_UNKNOWN;
 
hub = kzalloc(sizeof(struct usb3503), GFP_KERNEL);
if (!hub) {
-- 
1.7.10.4

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Re: [PATCH RESEND] ARM: dts: max77686: Add DTS file for max77686 PMIC

[Dongjin Kim]

Hello Mark,

Yes, this is not ARM-specific chip at all. Just wanted to be reviewed
by you and others if the format is ok before integrating to my board
file. I had sent similar one before,
https://patchwork.kernel.org/patch/1287711, and you advised that was
too board specific. And plan to integrate like OMAP boards have with
twl6030.dtsi and twl6040.dtsi.

If would be nice if somewhere you specify a directory for such device files.

Regards,
Dongjin.

On Sat, Jan 26, 2013 at 2:06 PM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
 On Fri, Jan 25, 2013 at 03:46:08AM +0900, Dongjin Kim wrote:

 ---
  arch/arm/boot/dts/max77686.dtsi |  156 
 +++

 Why is this in arch/arm?  This isn't an ARM-specific chip.
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[PATCH RESEND] ARM: dts: max77686: Add DTS file for max77686 PMIC

[Dongjin Kim]

This patch adds a dedicated DTS file for max77686 PMIC, supposed to be included
in a board DTS to control the power for certain consumer devices or AP with 9 
BUCKs
and 26 LDOs

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/max77686.dtsi |  156 +++
 1 file changed, 156 insertions(+)
 create mode 100644 arch/arm/boot/dts/max77686.dtsi

diff --git a/arch/arm/boot/dts/max77686.dtsi b/arch/arm/boot/dts/max77686.dtsi
new file mode 100644
index 000..b80baef
--- /dev/null
+++ b/arch/arm/boot/dts/max77686.dtsi
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2013 Dongjin Kim 
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ */
+
+ {
+   compatible = "maxim,max77686";
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   voltage-regulators {
+   buck1: buck@10 {
+   regulator-compatible = "BUCK1";
+   };
+
+   buck2: buck@12 {
+   regulator-compatible = "BUCK2";
+   };
+
+   buck3: buck@1c {
+   regulator-compatible = "BUCK3";
+   };
+
+   buck4: buck@26 {
+   regulator-compatible = "BUCK4";
+   };
+
+   buck5: buck@30 {
+   regulator-compatible = "BUCK5";
+   };
+
+   buck6: buck@32 {
+   regulator-compatible = "BUCK6";
+   };
+
+   buck7: buck@34 {
+   regulator-compatible = "BUCK7";
+   };
+
+   buck8: buck@36 {
+   regulator-compatible = "BUCK8";
+   };
+
+   buck9: buck@38 {
+   regulator-compatible = "BUCK9";
+   };
+
+   ldo1: ldo@40 {
+   regulator-compatible = "LDO1";
+   };
+
+   ldo2: ldo@41 {
+   regulator-compatible = "LDO2";
+   };
+
+   ldo3: ldo@42 {
+   regulator-compatible = "LDO3";
+   };
+
+   ldo4: ldo@43 {
+   regulator-compatible = "LDO4";
+   };
+
+   ldo5: ldo@44 {
+   regulator-compatible = "LDO5";
+   };
+
+   ldo6: ldo@45 {
+   regulator-compatible = "LDO6";
+   };
+
+   ldo7: ldo@46 {
+   regulator-compatible = "LDO7";
+   };
+
+   ldo8: ldo@47 {
+   regulator-compatible = "LDO8";
+   };
+
+   ldo9: ldo@48 {
+   regulator-compatible = "LDO9";
+   };
+
+   ldo10: ldo@49 {
+   regulator-compatible = "LDO10";
+   };
+
+   ldo11: ldo@4a {
+   regulator-compatible = "LDO11";
+   };
+
+   ldo12: ldo@4b {
+   regulator-compatible = "LDO12";
+   };
+
+   ldo13: ldo@4c {
+   regulator-compatible = "LDO13";
+   };
+
+   ldo14: ldo@4d {
+   regulator-compatible = "LDO14";
+   };
+
+   ldo15: ldo@4e {
+   regulator-compatible = "LDO15";
+   };
+
+   ldo16: ldo@4f {
+   regulator-compatible = "LDO16";
+   };
+
+   ldo17: ldo@50 {
+   regulator-compatible = "LDO17";
+   };
+
+   ldo18: ldo@51 {
+   regulator-compatible = "LDO18";
+   };
+
+   ldo19: ldo@52 {
+   regulator-compatible = "LDO19";
+   };
+
+   ldo20: ldo@53 {
+   regulator-compatible = "LDO20";
+   };
+
+   ldo21: ldo@54 {
+   regulator-compatible = "LDO21";
+   };
+
+   ldo22: ldo@55 {
+   regulator-compatible = "LDO22";
+   };
+
+   ldo23: ldo@56 {
+   regulator-compatible = "LDO23";
+   };
+
+   ldo24: ldo@57 {
+   regulator-compatible = "LDO24";
+   };
+
+   ldo25: ldo@58 {
+   regulator-compatible = "LDO25";
+   

[PATCH v2] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

This patch adds the compatible string for MSHC controller of Exynos4412, and
share the controller specific properties with Exynos5250 since they have same
features. Its driver data name is changed to exynos5_drv_data not to use SoC
specific name.

Signed-off-by: Dongjin Kim 
---
 drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 4d50da6..8238a00 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
return 0;
 }
 
-/* Exynos5250 controller specific capabilities */
-static unsigned long exynos5250_dwmmc_caps[4] = {
+/* Exynos4412/Exynos5250 controller specific capabilities */
+static unsigned long exynos5_dwmmc_caps[4] = {
MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
MMC_CAP_CMD23,
@@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
MMC_CAP_CMD23,
 };
 
-static const struct dw_mci_drv_data exynos5250_drv_data = {
-   .caps   = exynos5250_dwmmc_caps,
+static const struct dw_mci_drv_data exynos5_drv_data = {
+   .caps   = exynos5_dwmmc_caps,
.init   = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
.prepare_command= dw_mci_exynos_prepare_command,
@@ -219,8 +219,10 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
 };
 
 static const struct of_device_id dw_mci_exynos_match[] = {
+   { .compatible = "samsung,exynos4412-dw-mshc",
+   .data = _drv_data, },
{ .compatible = "samsung,exynos5250-dw-mshc",
-   .data = _drv_data, },
+   .data = _drv_data, },
{},
 };
 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
-- 
1.7.10.4

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[PATCH v2] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

This patch adds the compatible string for MSHC controller of Exynos4412, and
share the controller specific properties with Exynos5250 since they have same
features. Its driver data name is changed to exynos5_drv_data not to use SoC
specific name.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 drivers/mmc/host/dw_mmc-exynos.c |   12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 4d50da6..8238a00 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -199,8 +199,8 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
return 0;
 }
 
-/* Exynos5250 controller specific capabilities */
-static unsigned long exynos5250_dwmmc_caps[4] = {
+/* Exynos4412/Exynos5250 controller specific capabilities */
+static unsigned long exynos5_dwmmc_caps[4] = {
MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
MMC_CAP_CMD23,
@@ -208,8 +208,8 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
MMC_CAP_CMD23,
 };
 
-static const struct dw_mci_drv_data exynos5250_drv_data = {
-   .caps   = exynos5250_dwmmc_caps,
+static const struct dw_mci_drv_data exynos5_drv_data = {
+   .caps   = exynos5_dwmmc_caps,
.init   = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
.prepare_command= dw_mci_exynos_prepare_command,
@@ -219,8 +219,10 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
 };
 
 static const struct of_device_id dw_mci_exynos_match[] = {
+   { .compatible = samsung,exynos4412-dw-mshc,
+   .data = exynos5_drv_data, },
{ .compatible = samsung,exynos5250-dw-mshc,
-   .data = exynos5250_drv_data, },
+   .data = exynos5_drv_data, },
{},
 };
 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
-- 
1.7.10.4

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[PATCH RESEND] ARM: dts: max77686: Add DTS file for max77686 PMIC

[Dongjin Kim]

This patch adds a dedicated DTS file for max77686 PMIC, supposed to be included
in a board DTS to control the power for certain consumer devices or AP with 9 
BUCKs
and 26 LDOs

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/max77686.dtsi |  156 +++
 1 file changed, 156 insertions(+)
 create mode 100644 arch/arm/boot/dts/max77686.dtsi

diff --git a/arch/arm/boot/dts/max77686.dtsi b/arch/arm/boot/dts/max77686.dtsi
new file mode 100644
index 000..b80baef
--- /dev/null
+++ b/arch/arm/boot/dts/max77686.dtsi
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2013 Dongjin Kim tobet...@gmail.com
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ */
+
+max77686 {
+   compatible = maxim,max77686;
+
+   interrupt-controller;
+   #interrupt-cells = 1;
+
+   voltage-regulators {
+   buck1: buck@10 {
+   regulator-compatible = BUCK1;
+   };
+
+   buck2: buck@12 {
+   regulator-compatible = BUCK2;
+   };
+
+   buck3: buck@1c {
+   regulator-compatible = BUCK3;
+   };
+
+   buck4: buck@26 {
+   regulator-compatible = BUCK4;
+   };
+
+   buck5: buck@30 {
+   regulator-compatible = BUCK5;
+   };
+
+   buck6: buck@32 {
+   regulator-compatible = BUCK6;
+   };
+
+   buck7: buck@34 {
+   regulator-compatible = BUCK7;
+   };
+
+   buck8: buck@36 {
+   regulator-compatible = BUCK8;
+   };
+
+   buck9: buck@38 {
+   regulator-compatible = BUCK9;
+   };
+
+   ldo1: ldo@40 {
+   regulator-compatible = LDO1;
+   };
+
+   ldo2: ldo@41 {
+   regulator-compatible = LDO2;
+   };
+
+   ldo3: ldo@42 {
+   regulator-compatible = LDO3;
+   };
+
+   ldo4: ldo@43 {
+   regulator-compatible = LDO4;
+   };
+
+   ldo5: ldo@44 {
+   regulator-compatible = LDO5;
+   };
+
+   ldo6: ldo@45 {
+   regulator-compatible = LDO6;
+   };
+
+   ldo7: ldo@46 {
+   regulator-compatible = LDO7;
+   };
+
+   ldo8: ldo@47 {
+   regulator-compatible = LDO8;
+   };
+
+   ldo9: ldo@48 {
+   regulator-compatible = LDO9;
+   };
+
+   ldo10: ldo@49 {
+   regulator-compatible = LDO10;
+   };
+
+   ldo11: ldo@4a {
+   regulator-compatible = LDO11;
+   };
+
+   ldo12: ldo@4b {
+   regulator-compatible = LDO12;
+   };
+
+   ldo13: ldo@4c {
+   regulator-compatible = LDO13;
+   };
+
+   ldo14: ldo@4d {
+   regulator-compatible = LDO14;
+   };
+
+   ldo15: ldo@4e {
+   regulator-compatible = LDO15;
+   };
+
+   ldo16: ldo@4f {
+   regulator-compatible = LDO16;
+   };
+
+   ldo17: ldo@50 {
+   regulator-compatible = LDO17;
+   };
+
+   ldo18: ldo@51 {
+   regulator-compatible = LDO18;
+   };
+
+   ldo19: ldo@52 {
+   regulator-compatible = LDO19;
+   };
+
+   ldo20: ldo@53 {
+   regulator-compatible = LDO20;
+   };
+
+   ldo21: ldo@54 {
+   regulator-compatible = LDO21;
+   };
+
+   ldo22: ldo@55 {
+   regulator-compatible = LDO22;
+   };
+
+   ldo23: ldo@56 {
+   regulator-compatible = LDO23;
+   };
+
+   ldo24: ldo@57 {
+   regulator-compatible = LDO24;
+   };
+
+   ldo25: ldo@58 {
+   regulator-compatible = LDO25;
+   };
+
+   ldo26: ldo@59 {
+   regulator-compatible = LDO26;
+   };
+   };
+};
-- 
1.7.10.4

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Re: [PATCH] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

Hi Jaehoon,

Yes, completely agree with you but I wanted to keep "exynos5250_"
before Exynos4210's drv_data is sorted out. Anyway "exynos5_" would be
ok, I think.

Regards,
Dongjin.

On Thu, Jan 24, 2013 at 11:41 AM, Jaehoon Chung  wrote:
> On 01/24/2013 12:24 AM, Dongjin Kim wrote:
>> This patch adds the compatible string for MSHC controller of Exynos4412, and
>> reuse the controller specific properties with Exynos5250 since those have 
>> same
>> features.
>>
>> Signed-off-by: Dongjin Kim 
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> b/drivers/mmc/host/dw_mmc-exynos.c
>> index 0cb9bcb..4f7685f 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -204,6 +204,8 @@ static const struct dw_mci_drv_data exynos5250_drv_data 
>> = {
>>  };
>>
>>  static const struct of_device_id dw_mci_exynos_match[] = {
>> + { .compatible = "samsung,exynos4412-dw-mshc",
>> + .data = _drv_data, },
> If we can use the same drv_data, should be changed to more generic name, not 
> "exynos5250_".
>
> Best Regards,
> Jaehoon Chung
>>   { .compatible = "samsung,exynos5250-dw-mshc",
>>   .data = _drv_data, },
>>   {},
>>
>
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[PATCH] ARM: dts: Add EHCI device tree node for Exynos4

[Dongjin Kim]

This patch adds EHCI device node for Exynos4412

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4412.dtsi |6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
b/arch/arm/boot/dts/exynos4412.dtsi
index 387aa27..0c8f23b 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -33,4 +33,10 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   ehci@1258 {
+   compatible = "samsung,exynos-ehci";
+   reg = <0x1258 0x100>;
+   interrupts = <0 70 0>;
+   };
 };
-- 
1.7.10.4

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[PATCH] USB: misc: usb3503: add dt support

[Dongjin Kim]

Added device tree support for usb3503 driver and add new document with device 
tree binding information.

Signed-off-by: Dongjin Kim 
---
 Documentation/devicetree/bindings/usb/usb3503.txt |   20 +
 drivers/usb/misc/usb3503.c|   31 +
 2 files changed, 46 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/usb3503.txt

diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt 
b/Documentation/devicetree/bindings/usb/usb3503.txt
new file mode 100644
index 000..6813a71
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/usb3503.txt
@@ -0,0 +1,20 @@
+SMSC USB3503 High-Speed Hub Controller
+
+Required properties:
+- compatible: Should be "smsc,usb3503".
+- reg: Specifies the i2c slave address, it should be 0x08.
+- connect-gpios: Should specify GPIO for connect.
+- intn-gpios: Should specify GPIO for interrupt.
+- reset-gpios: Should specify GPIO for reset.
+- initial-mode: Should specify initial mode.
+(1 for HUB mode, 2 for STANDBY mode)
+
+Examples:
+   usb3503@08 {
+   compatible = "smsc,usb3503";
+   reg = <0x08>;
+   connect-gpios = < 0 1>;
+   intn-gpios = < 4 1>;
+   reset-gpios = < 5 1>;
+   initial-mode = <1>;
+   };
diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index dc2c993..471218a 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -181,8 +182,10 @@ err_hubmode:
 static int usb3503_probe(struct i2c_client *i2c, const struct i2c_device_id 
*id)
 {
struct usb3503_platform_data *pdata = i2c->dev.platform_data;
+   struct device_node *np = i2c->dev.of_node;
struct usb3503 *hub;
int err = -ENOMEM;
+   u32 mode;
 
hub = kzalloc(sizeof(struct usb3503), GFP_KERNEL);
if (!hub) {
@@ -193,14 +196,23 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
i2c_set_clientdata(i2c, hub);
hub->client = i2c;
 
-   if (!pdata) {
-   dev_dbg(>dev, "missing platform data\n");
-   goto err_out;
-   } else {
+   if (pdata) {
hub->gpio_intn  = pdata->gpio_intn;
hub->gpio_connect   = pdata->gpio_connect;
hub->gpio_reset = pdata->gpio_reset;
hub->mode   = pdata->initial_mode;
+   } else if (np) {
+   hub->gpio_intn  = of_get_named_gpio(np, "connect-gpios", 0);
+   if (hub->gpio_intn == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   hub->gpio_connect = of_get_named_gpio(np, "intn-gpios", 0);
+   if (hub->gpio_connect == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   hub->gpio_reset = of_get_named_gpio(np, "reset-gpios", 0);
+   if (hub->gpio_reset == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   of_property_read_u32(np, "initial-mode", );
+   hub->mode = mode;
}
 
if (gpio_is_valid(hub->gpio_intn)) {
@@ -236,7 +248,7 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
}
}
 
-   usb3503_switch_mode(hub, pdata->initial_mode);
+   usb3503_switch_mode(hub, hub->mode);
 
dev_info(>dev, "%s: probed on  %s mode\n", __func__,
(hub->mode == USB3503_MODE_HUB) ? "hub" : "standby");
@@ -277,9 +289,18 @@ static const struct i2c_device_id usb3503_id[] = {
 };
 MODULE_DEVICE_TABLE(i2c, usb3503_id);
 
+#ifdef CONFIG_OF
+static const struct of_device_id usb3503_of_match[] = {
+   { .compatible = "smsc,usb3503", },
+   {},
+};
+MODULE_DEVICE_TABLE(of, usb3503_of_match);
+#endif
+
 static struct i2c_driver usb3503_driver = {
.driver = {
.name = USB3503_I2C_NAME,
+   .of_match_table = of_match_ptr(usb3503_of_match),
},
.probe  = usb3503_probe,
.remove = usb3503_remove,
-- 
1.7.10.4

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[PATCH] ARM: dts: Fix MSHC property and add RTC node

[Dongjin Kim]

This fixes the property of dw-mshc-sdr-timing and dw-mshc-ddr-timing as per
its current binding, it only has two cells.
And also RTC node is added new.

Signed-off-by: Dongjin Kim 
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index f41a84e..1c1d5ec 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -49,8 +49,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
-   samsung,dw-mshc-sdr-timing = <2 3 3>;
-   samsung,dw-mshc-ddr-timing = <1 2 3>;
+   samsung,dw-mshc-sdr-timing = <2 3>;
+   samsung,dw-mshc-ddr-timing = <1 2>;
 
slot@0 {
reg = <0>;
@@ -90,4 +90,8 @@
serial@1383 {
status = "okay";
};
+
+   rtc@1007 {
+   status = "okay";
+   };
 };
-- 
1.7.10.4

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[PATCH] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

This patch adds the compatible string for MSHC controller of Exynos4412, and
reuse the controller specific properties with Exynos5250 since those have same
features.

Signed-off-by: Dongjin Kim 
---
 drivers/mmc/host/dw_mmc-exynos.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 0cb9bcb..4f7685f 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -204,6 +204,8 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
 };
 
 static const struct of_device_id dw_mci_exynos_match[] = {
+   { .compatible = "samsung,exynos4412-dw-mshc",
+   .data = _drv_data, },
{ .compatible = "samsung,exynos5250-dw-mshc",
.data = _drv_data, },
{},
-- 
1.7.10.4

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[PATCH] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

This patch adds the compatible string for MSHC controller of Exynos4412, and
reuse the controller specific properties with Exynos5250 since those have same
features.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 drivers/mmc/host/dw_mmc-exynos.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 0cb9bcb..4f7685f 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -204,6 +204,8 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
 };
 
 static const struct of_device_id dw_mci_exynos_match[] = {
+   { .compatible = samsung,exynos4412-dw-mshc,
+   .data = exynos5250_drv_data, },
{ .compatible = samsung,exynos5250-dw-mshc,
.data = exynos5250_drv_data, },
{},
-- 
1.7.10.4

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[PATCH] ARM: dts: Fix MSHC property and add RTC node

[Dongjin Kim]

This fixes the property of dw-mshc-sdr-timing and dw-mshc-ddr-timing as per
its current binding, it only has two cells.
And also RTC node is added new.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts 
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index f41a84e..1c1d5ec 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -49,8 +49,8 @@
fifo-depth = 0x80;
card-detect-delay = 200;
samsung,dw-mshc-ciu-div = 3;
-   samsung,dw-mshc-sdr-timing = 2 3 3;
-   samsung,dw-mshc-ddr-timing = 1 2 3;
+   samsung,dw-mshc-sdr-timing = 2 3;
+   samsung,dw-mshc-ddr-timing = 1 2;
 
slot@0 {
reg = 0;
@@ -90,4 +90,8 @@
serial@1383 {
status = okay;
};
+
+   rtc@1007 {
+   status = okay;
+   };
 };
-- 
1.7.10.4

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[PATCH] USB: misc: usb3503: add dt support

[Dongjin Kim]

Added device tree support for usb3503 driver and add new document with device 
tree binding information.

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 Documentation/devicetree/bindings/usb/usb3503.txt |   20 +
 drivers/usb/misc/usb3503.c|   31 +
 2 files changed, 46 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/usb3503.txt

diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt 
b/Documentation/devicetree/bindings/usb/usb3503.txt
new file mode 100644
index 000..6813a71
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/usb3503.txt
@@ -0,0 +1,20 @@
+SMSC USB3503 High-Speed Hub Controller
+
+Required properties:
+- compatible: Should be smsc,usb3503.
+- reg: Specifies the i2c slave address, it should be 0x08.
+- connect-gpios: Should specify GPIO for connect.
+- intn-gpios: Should specify GPIO for interrupt.
+- reset-gpios: Should specify GPIO for reset.
+- initial-mode: Should specify initial mode.
+(1 for HUB mode, 2 for STANDBY mode)
+
+Examples:
+   usb3503@08 {
+   compatible = smsc,usb3503;
+   reg = 0x08;
+   connect-gpios = gpx3 0 1;
+   intn-gpios = gpx3 4 1;
+   reset-gpios = gpx3 5 1;
+   initial-mode = 1;
+   };
diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index dc2c993..471218a 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -23,6 +23,7 @@
 #include linux/delay.h
 #include linux/slab.h
 #include linux/module.h
+#include linux/of_gpio.h
 #include linux/platform_device.h
 #include linux/platform_data/usb3503.h
 
@@ -181,8 +182,10 @@ err_hubmode:
 static int usb3503_probe(struct i2c_client *i2c, const struct i2c_device_id 
*id)
 {
struct usb3503_platform_data *pdata = i2c-dev.platform_data;
+   struct device_node *np = i2c-dev.of_node;
struct usb3503 *hub;
int err = -ENOMEM;
+   u32 mode;
 
hub = kzalloc(sizeof(struct usb3503), GFP_KERNEL);
if (!hub) {
@@ -193,14 +196,23 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
i2c_set_clientdata(i2c, hub);
hub-client = i2c;
 
-   if (!pdata) {
-   dev_dbg(i2c-dev, missing platform data\n);
-   goto err_out;
-   } else {
+   if (pdata) {
hub-gpio_intn  = pdata-gpio_intn;
hub-gpio_connect   = pdata-gpio_connect;
hub-gpio_reset = pdata-gpio_reset;
hub-mode   = pdata-initial_mode;
+   } else if (np) {
+   hub-gpio_intn  = of_get_named_gpio(np, connect-gpios, 0);
+   if (hub-gpio_intn == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   hub-gpio_connect = of_get_named_gpio(np, intn-gpios, 0);
+   if (hub-gpio_connect == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   hub-gpio_reset = of_get_named_gpio(np, reset-gpios, 0);
+   if (hub-gpio_reset == -EPROBE_DEFER)
+   return -EPROBE_DEFER;
+   of_property_read_u32(np, initial-mode, mode);
+   hub-mode = mode;
}
 
if (gpio_is_valid(hub-gpio_intn)) {
@@ -236,7 +248,7 @@ static int usb3503_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
}
}
 
-   usb3503_switch_mode(hub, pdata-initial_mode);
+   usb3503_switch_mode(hub, hub-mode);
 
dev_info(i2c-dev, %s: probed on  %s mode\n, __func__,
(hub-mode == USB3503_MODE_HUB) ? hub : standby);
@@ -277,9 +289,18 @@ static const struct i2c_device_id usb3503_id[] = {
 };
 MODULE_DEVICE_TABLE(i2c, usb3503_id);
 
+#ifdef CONFIG_OF
+static const struct of_device_id usb3503_of_match[] = {
+   { .compatible = smsc,usb3503, },
+   {},
+};
+MODULE_DEVICE_TABLE(of, usb3503_of_match);
+#endif
+
 static struct i2c_driver usb3503_driver = {
.driver = {
.name = USB3503_I2C_NAME,
+   .of_match_table = of_match_ptr(usb3503_of_match),
},
.probe  = usb3503_probe,
.remove = usb3503_remove,
-- 
1.7.10.4

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[PATCH] ARM: dts: Add EHCI device tree node for Exynos4

[Dongjin Kim]

This patch adds EHCI device node for Exynos4412

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 arch/arm/boot/dts/exynos4412.dtsi |6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
b/arch/arm/boot/dts/exynos4412.dtsi
index 387aa27..0c8f23b 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -33,4 +33,10 @@
#address-cells = 1;
#size-cells = 0;
};
+
+   ehci@1258 {
+   compatible = samsung,exynos-ehci;
+   reg = 0x1258 0x100;
+   interrupts = 0 70 0;
+   };
 };
-- 
1.7.10.4

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Re: [PATCH] mmc: dw_mmc: Add MSHC compatible for Exynos4412

[Dongjin Kim]

Hi Jaehoon,

Yes, completely agree with you but I wanted to keep exynos5250_
before Exynos4210's drv_data is sorted out. Anyway exynos5_ would be
ok, I think.

Regards,
Dongjin.

On Thu, Jan 24, 2013 at 11:41 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
 On 01/24/2013 12:24 AM, Dongjin Kim wrote:
 This patch adds the compatible string for MSHC controller of Exynos4412, and
 reuse the controller specific properties with Exynos5250 since those have 
 same
 features.

 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  drivers/mmc/host/dw_mmc-exynos.c |2 ++
  1 file changed, 2 insertions(+)

 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index 0cb9bcb..4f7685f 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -204,6 +204,8 @@ static const struct dw_mci_drv_data exynos5250_drv_data 
 = {
  };

  static const struct of_device_id dw_mci_exynos_match[] = {
 + { .compatible = samsung,exynos4412-dw-mshc,
 + .data = exynos5250_drv_data, },
 If we can use the same drv_data, should be changed to more generic name, not 
 exynos5250_.

 Best Regards,
 Jaehoon Chung
   { .compatible = samsung,exynos5250-dw-mshc,
   .data = exynos5250_drv_data, },
   {},


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Re: [PATCH] mmc: host: dw_mmc-exynos: Add support for pinctrl

[Dongjin Kim]

Hi Thomas,

I have a question regarding the bus setup when I use the patch
https://patchwork.kernel.org/patch/1870231. It configures buses as
defined in "pinctrl-0 = ...".

But in the function dw_mci_exynos_setup_bus(), it tries again to
configure gpios and probing is failed because there is no "gpios =
<...>" property. So I guess bus setup has to be ignored when the gpios
are configured with pinctrl.

What's your advice?

Thank you in advance.
Dongjin.

On Fri, Jan 4, 2013 at 3:33 AM, Dongjin Kim  wrote:
> Hi Thomas,
>
> Thank you for your reviewing, and
> https://patchwork.kernel.org/patch/1870231 works. So this change is
> needless.
>
> I had tested with below changes on my hardware.
>
> [1] https://patchwork.kernel.org/patch/1904431
> [2] https://patchwork.kernel.org/patch/1920661
>
> Best regards,
> Dongjin.
>
> On Mon, Dec 31, 2012 at 2:57 PM, Thomas Abraham
>  wrote:
>> On 21 December 2012 09:11, Dongjin Kim  wrote:
>>> This patch adds support for pin configuration using pinctrl subsystem to
>>> dw_mmc-exynos driver. The property 'wp-gpios' can be specified for write
>>> protect but 'samsung,cd-pinmux-gpio' and gpios used for clock, command and
>>> data lines will be ignored.
>>>
>>> -. 'pinctrl-0' should specify pin control groups (clock, comand and data
>>> lines) used for this controller.
>>> -. 'pinctrl-names' should contain only one value, 'default'.
>>>
>>> Signed-off-by: Dongjin Kim 
>>> ---
>>>  drivers/mmc/host/dw_mmc-exynos.c |   44 
>>> --
>>>  1 file changed, 28 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>>> b/drivers/mmc/host/dw_mmc-exynos.c
>>> index 4d50da6..d1c9963 100644
>>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>>> @@ -16,6 +16,7 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>
>>>  #include "dw_mmc.h"
>>>  #include "dw_mmc-pltfm.h"
>>> @@ -49,6 +50,7 @@ struct dw_mci_exynos_priv_data {
>>> u8  ciu_div;
>>> u32 sdr_timing;
>>> u32 ddr_timing;
>>> +   struct pinctrl  *pctrl;
>>>  };
>>>
>>>  static struct dw_mci_exynos_compatible {
>>> @@ -84,6 +86,10 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>> priv->ctrl_type = exynos_compat[idx].ctrl_type;
>>> }
>>>
>>> +   priv->pctrl = devm_pinctrl_get_select_default(host->dev);
>>> +   if (IS_ERR(priv->pctrl))
>>> +   dev_dbg(host->dev, "no pinctrl node\n");
>>> +
>>
>> This could have been handled in dw_mci_exynos_setup_bus function. And
>> we also need to check if this patch gets merged.
>> https://patchwork.kernel.org/patch/1870231/. If it gets merged, this
>> change can be avoided.
>>
>>> host->priv = priv;
>>> return 0;
>>>  }
>>> @@ -149,32 +155,19 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
>>> return ret;
>>>
>>> priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
>>> +
>>> return 0;
>>>  }
>>>
>>>  static int dw_mci_exynos_setup_bus(struct dw_mci *host,
>>> struct device_node *slot_np, u8 bus_width)
>>>  {
>>> +   struct dw_mci_exynos_priv_data *priv = host->priv;
>>> int idx, gpio, ret;
>>>
>>> if (!slot_np)
>>> return -EINVAL;
>>>
>>> -   /* cmd + clock + bus-width pins */
>>> -   for (idx = 0; idx < NUM_PINS(bus_width); idx++) {
>>> -   gpio = of_get_gpio(slot_np, idx);
>>> -   if (!gpio_is_valid(gpio)) {
>>> -   dev_err(host->dev, "invalid gpio: %d\n", gpio);
>>> -   return -EINVAL;
>>> -   }
>>> -
>>> -   ret = devm_gpio_request(host->dev, gpio, "dw-mci-bus");
>>> -   if (ret) {
>>> -   dev_err(host->dev, "gpio [%d] request failed\n", 
>>> gpio);
>>> -   return -EBUSY;
>>> -   }
>

Re: [PATCH] mmc: host: dw_mmc-exynos: Add support for pinctrl

[Dongjin Kim]

Hi Thomas,

I have a question regarding the bus setup when I use the patch
https://patchwork.kernel.org/patch/1870231. It configures buses as
defined in pinctrl-0 = 

But in the function dw_mci_exynos_setup_bus(), it tries again to
configure gpios and probing is failed because there is no gpios =
... property. So I guess bus setup has to be ignored when the gpios
are configured with pinctrl.

What's your advice?

Thank you in advance.
Dongjin.

On Fri, Jan 4, 2013 at 3:33 AM, Dongjin Kim tobet...@gmail.com wrote:
 Hi Thomas,

 Thank you for your reviewing, and
 https://patchwork.kernel.org/patch/1870231 works. So this change is
 needless.

 I had tested with below changes on my hardware.

 [1] https://patchwork.kernel.org/patch/1904431
 [2] https://patchwork.kernel.org/patch/1920661

 Best regards,
 Dongjin.

 On Mon, Dec 31, 2012 at 2:57 PM, Thomas Abraham
 thomas.abra...@linaro.org wrote:
 On 21 December 2012 09:11, Dongjin Kim tobet...@gmail.com wrote:
 This patch adds support for pin configuration using pinctrl subsystem to
 dw_mmc-exynos driver. The property 'wp-gpios' can be specified for write
 protect but 'samsung,cd-pinmux-gpio' and gpios used for clock, command and
 data lines will be ignored.

 -. 'pinctrl-0' should specify pin control groups (clock, comand and data
 lines) used for this controller.
 -. 'pinctrl-names' should contain only one value, 'default'.

 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  drivers/mmc/host/dw_mmc-exynos.c |   44 
 --
  1 file changed, 28 insertions(+), 16 deletions(-)

 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index 4d50da6..d1c9963 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -16,6 +16,7 @@
  #include linux/mmc/dw_mmc.h
  #include linux/of.h
  #include linux/of_gpio.h
 +#include linux/pinctrl/consumer.h

  #include dw_mmc.h
  #include dw_mmc-pltfm.h
 @@ -49,6 +50,7 @@ struct dw_mci_exynos_priv_data {
 u8  ciu_div;
 u32 sdr_timing;
 u32 ddr_timing;
 +   struct pinctrl  *pctrl;
  };

  static struct dw_mci_exynos_compatible {
 @@ -84,6 +86,10 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
 priv-ctrl_type = exynos_compat[idx].ctrl_type;
 }

 +   priv-pctrl = devm_pinctrl_get_select_default(host-dev);
 +   if (IS_ERR(priv-pctrl))
 +   dev_dbg(host-dev, no pinctrl node\n);
 +

 This could have been handled in dw_mci_exynos_setup_bus function. And
 we also need to check if this patch gets merged.
 https://patchwork.kernel.org/patch/1870231/. If it gets merged, this
 change can be avoided.

 host-priv = priv;
 return 0;
  }
 @@ -149,32 +155,19 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 return ret;

 priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 +
 return 0;
  }

  static int dw_mci_exynos_setup_bus(struct dw_mci *host,
 struct device_node *slot_np, u8 bus_width)
  {
 +   struct dw_mci_exynos_priv_data *priv = host-priv;
 int idx, gpio, ret;

 if (!slot_np)
 return -EINVAL;

 -   /* cmd + clock + bus-width pins */
 -   for (idx = 0; idx  NUM_PINS(bus_width); idx++) {
 -   gpio = of_get_gpio(slot_np, idx);
 -   if (!gpio_is_valid(gpio)) {
 -   dev_err(host-dev, invalid gpio: %d\n, gpio);
 -   return -EINVAL;
 -   }
 -
 -   ret = devm_gpio_request(host-dev, gpio, dw-mci-bus);
 -   if (ret) {
 -   dev_err(host-dev, gpio [%d] request failed\n, 
 gpio);
 -   return -EBUSY;
 -   }
 -   }
 -
 gpio = of_get_named_gpio(slot_np, wp-gpios, 0);
 if (gpio_is_valid(gpio)) {
 if (devm_gpio_request(host-dev, gpio, dw-mci-wp))
 @@ -185,9 +178,12 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
 host-pdata-quirks |= DW_MCI_QUIRK_NO_WRITE_PROTECT;
 }

 -   if (host-pdata-quirks  DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 +   if (!IS_ERR(priv-pctrl))
 return 0;

 +   if (host-pdata-quirks  DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 +   goto setup_bus;
 +

 Why do the entire bus setup if card detection is broken?

 gpio = of_get_named_gpio(slot_np, samsung,cd-pinmux-gpio, 0);
 if (gpio_is_valid(gpio)) {
 if (devm_gpio_request(host-dev, gpio, dw-mci-cd))
 @@ -196,6 +192,22 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
 dev_info(host-dev, cd gpio not available);
 }

 + setup_bus:
 +   /* cmd + clock + bus-width pins */
 +   for (idx = 0; idx  NUM_PINS(bus_width); idx

[PATCH] USB: misc: fixup smatch WARNING

[Dongjin Kim]

This patch fixes the warning,

6a099c63650e50ebf7d1259b859a3d230aec4207 [4/10] USB: misc: Add USB3503 
High-Speed Hub Controller

drivers/usb/misc/usb3503.c:238 usb3503_probe() error: we previously assumed 
'pdata' could be null (see line 196)

Signed-off-by: Dongjin Kim 
---
 drivers/usb/misc/usb3503.c |9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index 796d58c..7bc2812 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -182,12 +182,12 @@ int usb3503_probe(struct i2c_client *i2c, const struct 
i2c_device_id *id)
 {
struct usb3503_platform_data *pdata = i2c->dev.platform_data;
struct usb3503 *hub;
-   int err;
+   int err = -ENOMEM;
 
hub = kzalloc(sizeof(struct usb3503), GFP_KERNEL);
if (!hub) {
dev_err(>dev, "private data alloc fail\n");
-   return -ENOMEM;
+   return err;
}
 
i2c_set_clientdata(i2c, hub);
@@ -195,6 +195,7 @@ int usb3503_probe(struct i2c_client *i2c, const struct 
i2c_device_id *id)
 
if (!pdata) {
dev_dbg(>dev, "missing platform data\n");
+   goto err_out;
} else {
hub->gpio_intn  = pdata->gpio_intn;
hub->gpio_connect   = pdata->gpio_connect;
@@ -209,7 +210,7 @@ int usb3503_probe(struct i2c_client *i2c, const struct 
i2c_device_id *id)
dev_err(>dev,
"unable to request GPIO %d as connect 
pin (%d)\n",
hub->gpio_intn, err);
-   goto err_gpio_intn;
+   goto err_out;
}
}
 
@@ -248,7 +249,7 @@ err_gpio_reset:
 err_gpio_connect:
if (gpio_is_valid(hub->gpio_intn))
gpio_free(hub->gpio_intn);
-err_gpio_intn:
+err_out:
kfree(hub);
 
return err;
-- 
1.7.9.5

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[PATCH] USB: misc: fixup smatch WARNING

[Dongjin Kim]

This patch fixes the warning,

6a099c63650e50ebf7d1259b859a3d230aec4207 [4/10] USB: misc: Add USB3503 
High-Speed Hub Controller

drivers/usb/misc/usb3503.c:238 usb3503_probe() error: we previously assumed 
'pdata' could be null (see line 196)

Signed-off-by: Dongjin Kim tobet...@gmail.com
---
 drivers/usb/misc/usb3503.c |9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c
index 796d58c..7bc2812 100644
--- a/drivers/usb/misc/usb3503.c
+++ b/drivers/usb/misc/usb3503.c
@@ -182,12 +182,12 @@ int usb3503_probe(struct i2c_client *i2c, const struct 
i2c_device_id *id)
 {
struct usb3503_platform_data *pdata = i2c-dev.platform_data;
struct usb3503 *hub;
-   int err;
+   int err = -ENOMEM;
 
hub = kzalloc(sizeof(struct usb3503), GFP_KERNEL);
if (!hub) {
dev_err(i2c-dev, private data alloc fail\n);
-   return -ENOMEM;
+   return err;
}
 
i2c_set_clientdata(i2c, hub);
@@ -195,6 +195,7 @@ int usb3503_probe(struct i2c_client *i2c, const struct 
i2c_device_id *id)
 
if (!pdata) {
dev_dbg(i2c-dev, missing platform data\n);
+   goto err_out;
} else {
hub-gpio_intn  = pdata-gpio_intn;
hub-gpio_connect   = pdata-gpio_connect;
@@ -209,7 +210,7 @@ int usb3503_probe(struct i2c_client *i2c, const struct 
i2c_device_id *id)
dev_err(i2c-dev,
unable to request GPIO %d as connect 
pin (%d)\n,
hub-gpio_intn, err);
-   goto err_gpio_intn;
+   goto err_out;
}
}
 
@@ -248,7 +249,7 @@ err_gpio_reset:
 err_gpio_connect:
if (gpio_is_valid(hub-gpio_intn))
gpio_free(hub-gpio_intn);
-err_gpio_intn:
+err_out:
kfree(hub);
 
return err;
-- 
1.7.9.5

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Re: [PATCH] mmc: host: dw_mmc-exynos: Add support for pinctrl

[Dongjin Kim]

Hi Thomas,

Thank you for your reviewing, and
https://patchwork.kernel.org/patch/1870231 works. So this change is
needless.

I had tested with below changes on my hardware.

[1] https://patchwork.kernel.org/patch/1904431
[2] https://patchwork.kernel.org/patch/1920661

Best regards,
Dongjin.

On Mon, Dec 31, 2012 at 2:57 PM, Thomas Abraham
 wrote:
> On 21 December 2012 09:11, Dongjin Kim  wrote:
>> This patch adds support for pin configuration using pinctrl subsystem to
>> dw_mmc-exynos driver. The property 'wp-gpios' can be specified for write
>> protect but 'samsung,cd-pinmux-gpio' and gpios used for clock, command and
>> data lines will be ignored.
>>
>> -. 'pinctrl-0' should specify pin control groups (clock, comand and data
>> lines) used for this controller.
>> -. 'pinctrl-names' should contain only one value, 'default'.
>>
>> Signed-off-by: Dongjin Kim 
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |   44 
>> --
>>  1 file changed, 28 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> b/drivers/mmc/host/dw_mmc-exynos.c
>> index 4d50da6..d1c9963 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -16,6 +16,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>
>>  #include "dw_mmc.h"
>>  #include "dw_mmc-pltfm.h"
>> @@ -49,6 +50,7 @@ struct dw_mci_exynos_priv_data {
>> u8  ciu_div;
>> u32 sdr_timing;
>> u32 ddr_timing;
>> +   struct pinctrl  *pctrl;
>>  };
>>
>>  static struct dw_mci_exynos_compatible {
>> @@ -84,6 +86,10 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>> priv->ctrl_type = exynos_compat[idx].ctrl_type;
>> }
>>
>> +   priv->pctrl = devm_pinctrl_get_select_default(host->dev);
>> +   if (IS_ERR(priv->pctrl))
>> +   dev_dbg(host->dev, "no pinctrl node\n");
>> +
>
> This could have been handled in dw_mci_exynos_setup_bus function. And
> we also need to check if this patch gets merged.
> https://patchwork.kernel.org/patch/1870231/. If it gets merged, this
> change can be avoided.
>
>> host->priv = priv;
>> return 0;
>>  }
>> @@ -149,32 +155,19 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
>> return ret;
>>
>> priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
>> +
>> return 0;
>>  }
>>
>>  static int dw_mci_exynos_setup_bus(struct dw_mci *host,
>> struct device_node *slot_np, u8 bus_width)
>>  {
>> +   struct dw_mci_exynos_priv_data *priv = host->priv;
>> int idx, gpio, ret;
>>
>> if (!slot_np)
>> return -EINVAL;
>>
>> -   /* cmd + clock + bus-width pins */
>> -   for (idx = 0; idx < NUM_PINS(bus_width); idx++) {
>> -   gpio = of_get_gpio(slot_np, idx);
>> -   if (!gpio_is_valid(gpio)) {
>> -   dev_err(host->dev, "invalid gpio: %d\n", gpio);
>> -   return -EINVAL;
>> -   }
>> -
>> -   ret = devm_gpio_request(host->dev, gpio, "dw-mci-bus");
>> -   if (ret) {
>> -   dev_err(host->dev, "gpio [%d] request failed\n", 
>> gpio);
>> -   return -EBUSY;
>> -   }
>> -   }
>> -
>> gpio = of_get_named_gpio(slot_np, "wp-gpios", 0);
>> if (gpio_is_valid(gpio)) {
>> if (devm_gpio_request(host->dev, gpio, "dw-mci-wp"))
>> @@ -185,9 +178,12 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
>> host->pdata->quirks |= DW_MCI_QUIRK_NO_WRITE_PROTECT;
>> }
>>
>> -   if (host->pdata->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
>> +   if (!IS_ERR(priv->pctrl))
>> return 0;
>>
>> +   if (host->pdata->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
>> +   goto setup_bus;
>> +
>
> Why do the entire bus setup if card detection is broken?
>
>> gpio = of_get_named_gpio(slot_np, "samsung,cd-pinmux-gpio", 0);
>> if (gpio_is_valid(gpio)

Re: [PATCH] mmc: host: dw_mmc-exynos: Add support for pinctrl

[Dongjin Kim]

Hi Thomas,

Thank you for your reviewing, and
https://patchwork.kernel.org/patch/1870231 works. So this change is
needless.

I had tested with below changes on my hardware.

[1] https://patchwork.kernel.org/patch/1904431
[2] https://patchwork.kernel.org/patch/1920661

Best regards,
Dongjin.

On Mon, Dec 31, 2012 at 2:57 PM, Thomas Abraham
thomas.abra...@linaro.org wrote:
 On 21 December 2012 09:11, Dongjin Kim tobet...@gmail.com wrote:
 This patch adds support for pin configuration using pinctrl subsystem to
 dw_mmc-exynos driver. The property 'wp-gpios' can be specified for write
 protect but 'samsung,cd-pinmux-gpio' and gpios used for clock, command and
 data lines will be ignored.

 -. 'pinctrl-0' should specify pin control groups (clock, comand and data
 lines) used for this controller.
 -. 'pinctrl-names' should contain only one value, 'default'.

 Signed-off-by: Dongjin Kim tobet...@gmail.com
 ---
  drivers/mmc/host/dw_mmc-exynos.c |   44 
 --
  1 file changed, 28 insertions(+), 16 deletions(-)

 diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
 b/drivers/mmc/host/dw_mmc-exynos.c
 index 4d50da6..d1c9963 100644
 --- a/drivers/mmc/host/dw_mmc-exynos.c
 +++ b/drivers/mmc/host/dw_mmc-exynos.c
 @@ -16,6 +16,7 @@
  #include linux/mmc/dw_mmc.h
  #include linux/of.h
  #include linux/of_gpio.h
 +#include linux/pinctrl/consumer.h

  #include dw_mmc.h
  #include dw_mmc-pltfm.h
 @@ -49,6 +50,7 @@ struct dw_mci_exynos_priv_data {
 u8  ciu_div;
 u32 sdr_timing;
 u32 ddr_timing;
 +   struct pinctrl  *pctrl;
  };

  static struct dw_mci_exynos_compatible {
 @@ -84,6 +86,10 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
 priv-ctrl_type = exynos_compat[idx].ctrl_type;
 }

 +   priv-pctrl = devm_pinctrl_get_select_default(host-dev);
 +   if (IS_ERR(priv-pctrl))
 +   dev_dbg(host-dev, no pinctrl node\n);
 +

 This could have been handled in dw_mci_exynos_setup_bus function. And
 we also need to check if this patch gets merged.
 https://patchwork.kernel.org/patch/1870231/. If it gets merged, this
 change can be avoided.

 host-priv = priv;
 return 0;
  }
 @@ -149,32 +155,19 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 return ret;

 priv-ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 +
 return 0;
  }

  static int dw_mci_exynos_setup_bus(struct dw_mci *host,
 struct device_node *slot_np, u8 bus_width)
  {
 +   struct dw_mci_exynos_priv_data *priv = host-priv;
 int idx, gpio, ret;

 if (!slot_np)
 return -EINVAL;

 -   /* cmd + clock + bus-width pins */
 -   for (idx = 0; idx  NUM_PINS(bus_width); idx++) {
 -   gpio = of_get_gpio(slot_np, idx);
 -   if (!gpio_is_valid(gpio)) {
 -   dev_err(host-dev, invalid gpio: %d\n, gpio);
 -   return -EINVAL;
 -   }
 -
 -   ret = devm_gpio_request(host-dev, gpio, dw-mci-bus);
 -   if (ret) {
 -   dev_err(host-dev, gpio [%d] request failed\n, 
 gpio);
 -   return -EBUSY;
 -   }
 -   }
 -
 gpio = of_get_named_gpio(slot_np, wp-gpios, 0);
 if (gpio_is_valid(gpio)) {
 if (devm_gpio_request(host-dev, gpio, dw-mci-wp))
 @@ -185,9 +178,12 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
 host-pdata-quirks |= DW_MCI_QUIRK_NO_WRITE_PROTECT;
 }

 -   if (host-pdata-quirks  DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 +   if (!IS_ERR(priv-pctrl))
 return 0;

 +   if (host-pdata-quirks  DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 +   goto setup_bus;
 +

 Why do the entire bus setup if card detection is broken?

 gpio = of_get_named_gpio(slot_np, samsung,cd-pinmux-gpio, 0);
 if (gpio_is_valid(gpio)) {
 if (devm_gpio_request(host-dev, gpio, dw-mci-cd))
 @@ -196,6 +192,22 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
 dev_info(host-dev, cd gpio not available);
 }

 + setup_bus:
 +   /* cmd + clock + bus-width pins */
 +   for (idx = 0; idx  NUM_PINS(bus_width); idx++) {
 +   gpio = of_get_gpio(slot_np, idx);
 +   if (!gpio_is_valid(gpio)) {
 +   dev_err(host-dev, invalid gpio: %d\n, gpio);
 +   return -EINVAL;
 +   }
 +
 +   ret = devm_gpio_request(host-dev, gpio, dw-mci-bus);
 +   if (ret) {
 +   dev_err(host-dev, gpio [%d] request failed\n, 
 gpio);
 +   return -EBUSY;
 +   }
 +   }

 This change should not have been there. If the mmc bus setup