[PATCH V9 06/12] arm64: dts: mt8192: add dvfsrc related nodes
Enable dvfsrc on mt8192 platform.
Change-Id: I5c5cf1b0b22358034af5b482b6e46553398591e6
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 8252143..dbefc0d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -464,6 +464,12 @@
#clock-cells = <1>;
};
+ ddr_emi: dvfsrc@10012000 {
+ compatible = "mediatek,mt8192-dvfsrc",
+"mediatek,mt6873-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
--
1.9.1
[PATCH V9 08/12] interconnect: mediatek: Add interconnect provider driver
Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver
using the interconnect framework.
ICC provider ICC Nodes
- |CPU | |--- |VPU |
- | |- |
|DRAM |--|DRAM | |
| |--|scheduler|- |GPU | |--- |DISP|
| |--|(EMI)| |
| |--| | - |
- | |- |MMSYS|--|--- |VDEC|
-- |
/|\|
|change DRAM freq |--- |VENC|
-- |
| DVFSR | |
| | |
-- |--- |IMG |
|
|
|--- |CAM |
Signed-off-by: Henry Chen
---
drivers/interconnect/Kconfig| 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 13 ++
drivers/interconnect/mediatek/Makefile | 3 +
drivers/interconnect/mediatek/mtk-emi.c | 331
5 files changed, 349 insertions(+)
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/mtk-emi.c
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
index d637a89..da91f84 100644
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@@ -12,6 +12,7 @@ menuconfig INTERCONNECT
if INTERCONNECT
source "drivers/interconnect/imx/Kconfig"
+source "drivers/interconnect/mediatek/Kconfig"
source "drivers/interconnect/qcom/Kconfig"
source "drivers/interconnect/samsung/Kconfig"
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
index 97d393f..d697500 100644
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@@ -5,5 +5,6 @@ icc-core-objs := core.o bulk.o
obj-$(CONFIG_INTERCONNECT) += icc-core.o
obj-$(CONFIG_INTERCONNECT_IMX) += imx/
+obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/
obj-$(CONFIG_INTERCONNECT_QCOM)+= qcom/
obj-$(CONFIG_INTERCONNECT_SAMSUNG) += samsung/
diff --git a/drivers/interconnect/mediatek/Kconfig
b/drivers/interconnect/mediatek/Kconfig
new file mode 100644
index 000..ec98d6a
--- /dev/null
+++ b/drivers/interconnect/mediatek/Kconfig
@@ -0,0 +1,13 @@
+config INTERCONNECT_MTK
+ bool "Mediatek Network-on-Chip interconnect drivers"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ help
+ Support for Mediatek's Network-on-Chip interconnect hardware.
+
+config INTERCONNECT_MTK_EMI
+ tristate "Mediatek EMI interconnect driver"
+ depends on INTERCONNECT_MTK
+ depends on (MTK_DVFSRC && OF) || COMPILE_TEST
+ help
+ This is a driver for the Mediatek Network-on-Chip on DVFSRC-based
+ platforms.
diff --git a/drivers/interconnect/mediatek/Makefile
b/drivers/interconnect/mediatek/Makefile
new file mode 100644
index 000..353842b
--- /dev/null
+++ b/drivers/interconnect/mediatek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o
\ No newline at end of file
diff --git a/drivers/interconnect/mediatek/mtk-emi.c
b/drivers/interconnect/mediatek/mtk-emi.c
new file mode 100644
index 000..8d650be
--- /dev/null
+++ b/drivers/interconnect/mediatek/mtk-emi.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum mtk_icc_name {
+ SLAVE_DDR_EMI,
+ MASTER_MCUSYS,
+ MASTER_GPUSYS,
+ MASTER_MMSYS,
+ MASTER_MM_VPU,
+ MASTER_MM_DISP,
+ MASTER_MM_VDEC,
+ MASTER_MM_VENC,
+ MASTER_MM_CAM,
+ MASTER_MM_IMG,
+ MASTER_MM_MDP,
+ MASTER_VPUSYS,
+ MASTER_VPU_PORT_0,
+ MASTER_VPU_PORT_1,
+ MASTER_MDLASYS,
+ MASTER_MDLA_PORT_0,
+ MASTER_UFS,
+ MASTER_PCIE,
+ MASTER_USB,
+ MASTER_WIFI,
+ MASTER_BT,
+ MASTER_NETSYS,
+ MASTER_DBGIF,
+
+ SLAVE_HRT_DDR_EMI,
+ MASTER_HRT_MMSYS,
+ MASTER_HRT_MM_DISP,
+ MASTER_HRT_MM_VDEC,
+ MASTER_HRT_MM_VENC,
+ MASTER_HRT_MM_CAM,
+ MASTER_HRT_MM_IMG,
+ MASTER_HRT_MM_MDP,
+ MASTER_HRT_DBGIF,
+};
+
+#define MT8183_MAX_LINKS 1
+
+/**
+ * struct mtk_icc_node - Mediatek specific interconnect nodes
+ * @name: the node name u
[PATCH V9 05/12] arm64: dts: mt8183: add dvfsrc related nodes
Enable dvfsrc on mt8183 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5b782a4..062afe8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -497,6 +497,11 @@
#clock-cells = <1>;
};
+ ddr_emi: dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ };
+
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8183-pwrap";
reg = <0 0x1000d000 0 0x1000>;
--
1.9.1
[PATCH V9 10/12] arm64: dts: mt8192: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index dbefc0d..81d7d05 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include
+#include
#include
#include
#include
@@ -468,6 +469,7 @@
compatible = "mediatek,mt8192-dvfsrc",
"mediatek,mt6873-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
systimer: timer@10017000 {
--
1.9.1
[PATCH V9 11/12] arm64: dts: mt8183: add dvfsrc regulator nodes
Add dvfsrc regulator nodes which is for MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index e862078..9fefc5e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -502,6 +502,12 @@
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
#interconnect-cells = <1>;
+ dvfsrc_vcore: dvfsrc-vcore {
+ regulator-name = "dvfsrc-vcore";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <80>;
+ regulator-always-on;
+ };
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V9 00/13] Add driver for dvfsrc, support for interconnect
This series is based on v5.11-rc1. The patchsets add support for MediaTek hardware module named DVFSRC (dynamic voltage and frequency scaling resource collector). The DVFSRC is a HW module which is used to collect all the requests from both software and hardware and turn into the decision of minimum operating voltage and minimum DRAM frequency to fulfill those requests. So, This series is to implement the dvfsrc driver to collect all the requests of operating voltage or DRAM bandwidth from other device drivers likes GPU/Camera through 3 frameworks basically: 1. interconnect framework: to aggregate the bandwidth requirements from different clients [1] https://patchwork.kernel.org/cover/10766329/ There has a hw module "DRAM scheduler", which used to control the throughput. The DVFSRC will collect forecast data of dram bandwidth from SW consumers(camera/gpu...), and according the forecast to change the DRAM frequency 2. Regualtor framework: to handle the operating voltage requirement from user or cosumer which not belong any power domain Changes in V9: * modify the cnfiguration of dvfsrc.yaml. (Rob) Changes in V8: * Fixed the dt_binding_check error of dvfsrc.yaml. (Rob) * Remove Kconfig dependency of DVFSRC Changes in V7: * Fixed the dt_binding_check error of dvfsrc.yaml. (Rob) * Fixed the checkpatch complains of "Signed-off-by: email name mismatch". (Georgi) * Fixed coding style of interconnect driver. (Georgi) * Upate comment of the years to 2021. (Georgi) Changes in V6: * Remove the performace state support, because the request from consumer can be replaced by using interconnect and regulator framework. * Update the DT patches and convert them to DT schema. (Georgi) * Modify the comment format and coding style. (Mark) Changes in V5: * Support more platform mt6873/mt8192 * Drop the compatible and interconnect provider node and make the parent node an interconnect provider. (Rob/Georgi) * Make modification of interconnect driver from coding suggestion. (Georgi) * Move interconnect diagram into the commit text of patch. (Georgi) * Register the interconnect provider as a platform sub-device. (Georgi) Changes in V4: * Add acked TAG on dt-bindings patches. (Rob) * Declaration of emi_icc_aggregate since the prototype of aggregate function has changed meanwhile. (Georgi) * Used emi_icc_remove instead of icc_provider_del on probe. (Georgi) * Add dvfsrc regulator driver into series. * Bug fixed of mt8183_get_current_level. * Add mutex protection for pstate operation on dvfsrc_set_performance. Changes in V3: * Remove RFC from the subject prefix of the series * Combine dt-binding patch and move interconnect dt-binding document into dvfsrc. (Rob) * Remove unused header, add unit descirption to the bandwidth, rename compatible name on interconnect driver. (Georgi) * Fixed some coding style: check flow, naming, used readx_poll_timeout on dvfsrc driver. (Ryan) * Rename interconnect driver mt8183.c to mtk-emi.c * Rename interconnect header mtk,mt8183.h to mtk,emi.h * mtk-scpsys.c: Add opp table check first to avoid OF runtime parse failed Changes in RFC V2: * Remove the DT property dram_type. (Rob) * Used generic dts property 'opp-level' to get the performace state. (Stephen) * Remove unecessary dependency config on Kconfig. (Stephen) * Remove unused header file, fixed some coding style issue, typo, error handling on dvfsrc driver. (Nicolas/Stephen) * Remove irq handler on dvfsrc driver. (Stephen) * Remove init table on dvfsrc driver, combine hw init on trustzone. * Add interconnect support of mt8183 to aggregate the emi bandwidth. (Georgi) V8: https://patchwork.kernel.org/project/linux-mediatek/list/?series=421713 V7: https://patchwork.kernel.org/project/linux-mediatek/list/?series=411057 V6: https://patchwork.kernel.org/project/linux-mediatek/list/?series=406077 V5: https://patchwork.kernel.org/project/linux-mediatek/list/?series=348065 V4: https://lore.kernel.org/patchwork/cover/1209284/ V3: https://patchwork.kernel.org/cover/8867/ RFC V2: https://lore.kernel.org/patchwork/patch/1068113/ RFC V1: https://lore.kernel.org/patchwork/cover/1028535/
[PATCH V9 03/12] soc: mediatek: add driver for dvfsrc support
Add dvfsrc driver for MT6873/MT8183/MT8192
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/Kconfig| 11 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 421
include/linux/soc/mediatek/mtk_dvfsrc.h | 35 +++
4 files changed, 468 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc0..2dcf023 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -26,6 +26,17 @@ config MTK_DEVAPC
The violation information is logged for further analysis or
countermeasures.
+config MTK_DVFSRC
+ tristate "MediaTek DVFSRC Support"
+ depends on ARCH_MEDIATEK
+ help
+ Say yes here to add support for the MediaTek DVFSRC (dynamic voltage
+ and frequency scaling resource collector) found
+ on different MediaTek SoCs. The DVFSRC is a proprietary
+ hardware which is used to collect all the requests from
+ system and turn into the decision of minimum Vcore voltage
+ and minimum DRAM frequency to fulfill those requests.
+
config MTK_INFRACFG
bool "MediaTek INFRACFG Support"
select REGMAP
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b6908db..4ead103 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
+obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
new file mode 100644
index 000..c0c6d91
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DVFSRC_IDLE 0x00
+#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
+#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x)
+#define kbps_to_mbps(x) ((x) / 1000)
+
+#define POLL_TIMEOUT1000
+#define STARTUP_TIME1
+
+#define MTK_SIP_DVFSRC_INIT0x00
+
+#define DVFSRC_OPP_DESC(_opp_table)\
+{ \
+ .opps = _opp_table, \
+ .num_opp = ARRAY_SIZE(_opp_table), \
+}
+
+struct dvfsrc_opp {
+ u32 vcore_opp;
+ u32 dram_opp;
+};
+
+struct dvfsrc_opp_desc {
+ const struct dvfsrc_opp *opps;
+ u32 num_opp;
+};
+
+struct mtk_dvfsrc;
+struct dvfsrc_soc_data {
+ const int *regs;
+ const struct dvfsrc_opp_desc *opps_desc;
+ int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
+ int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc);
+ void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+};
+
+struct mtk_dvfsrc {
+ struct device *dev;
+ struct platform_device *icc;
+ struct platform_device *regulator;
+ const struct dvfsrc_soc_data *dvd;
+ int dram_type;
+ const struct dvfsrc_opp_desc *curr_opps;
+ void __iomem *regs;
+ spinlock_t req_lock;
+ struct mutex pstate_lock;
+ struct notifier_block scpsys_notifier;
+};
+
+static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
+{
+ return readl(dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
+{
+ writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \
+ dvfsrc_write(dvfs, offset, \
+ (dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val << shift))
+
+enum dvfsrc_regs {
+ DVFSRC_SW_REQ,
+ DVFSRC_SW_REQ2,
+ DVFSRC_LEVEL,
+ DVFSRC_TARGET_LEVEL,
+ DVFSRC_SW_BW,
+ DVFSRC_SW_PEAK_BW,
+ DVFSRC_SW_HRT_BW,
+ DVFSRC_VCORE_REQUEST,
+};
+
+static const int mt8183_regs[] = {
+ [DVFSRC_SW_REQ] = 0x4,
[PATCH V9 09/12] arm64: dts: mt8183: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8192-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 062afe8..e862078 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
#include
@@ -500,6 +501,7 @@
ddr_emi: dvfsrc@10012000 {
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V9 12/12] arm64: dts: mt8192: add dvfsrc regulator nodes
Add dvfsrc regulator nodes which is for MT8192-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 81d7d05..1cf91a4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -470,6 +470,12 @@
"mediatek,mt6873-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
#interconnect-cells = <1>;
+ dvfsrc_vcore: dvfsrc-vcore {
+ regulator-name = "dvfsrc-vcore";
+ regulator-min-microvolt = <575000>;
+ regulator-max-microvolt = <725000>;
+ regulator-always-on;
+ };
};
systimer: timer@10017000 {
--
1.9.1
[PATCH V9 04/12] soc: mediatek: add support for mt6873
add support for mt6873
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/mtk-dvfsrc.c | 114 ++
1 file changed, 114 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
index c0c6d91..a422680 100644
--- a/drivers/soc/mediatek/mtk-dvfsrc.c
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -102,6 +102,16 @@ enum dvfsrc_regs {
[DVFSRC_SW_BW] =0x160,
};
+static const int mt6873_regs[] = {
+ [DVFSRC_SW_REQ] = 0xC,
+ [DVFSRC_LEVEL] =0xD44,
+ [DVFSRC_SW_PEAK_BW] = 0x278,
+ [DVFSRC_SW_BW] =0x26C,
+ [DVFSRC_SW_HRT_BW] =0x290,
+ [DVFSRC_TARGET_LEVEL] = 0xD48,
+ [DVFSRC_VCORE_REQUEST] =0x6C,
+};
+
static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc)
{
int level;
@@ -127,6 +137,78 @@ static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc
*dvfsrc, u32 level)
POLL_TIMEOUT);
}
+static int mt6873_get_target_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return dvfsrc_read(dvfsrc, DVFSRC_TARGET_LEVEL);
+}
+
+static int mt6873_get_current_level(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 curr_level;
+
+ /* HW level 0 is begin from 0x1, and max opp is 0x1*/
+ curr_level = ffs(dvfsrc_read(dvfsrc, DVFSRC_LEVEL));
+ if (curr_level > dvfsrc->curr_opps->num_opp)
+ curr_level = 0;
+ else
+ curr_level = dvfsrc->curr_opps->num_opp - curr_level;
+
+ return curr_level;
+}
+
+static int mt6873_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ const struct dvfsrc_opp *target, *curr;
+
+ target = >curr_opps->opps[level];
+ return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr,
+ curr->dram_opp >= target->dram_opp,
+ STARTUP_TIME, POLL_TIMEOUT);
+}
+
+static u32 mt6873_get_vcore_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ) >> 4) & 0x7;
+}
+
+static u32 mt6873_get_vcp_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return (dvfsrc_read(dvfsrc, DVFSRC_VCORE_REQUEST) >> 12) & 0x7;
+}
+
+static void mt6873_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ bw = div_u64(kbps_to_mbps(bw), 100);
+ bw = min_t(u64, bw, 0xFF);
+ dvfsrc_write(dvfsrc, DVFSRC_SW_BW, bw);
+}
+
+static void mt6873_set_dram_peak_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ bw = div_u64(kbps_to_mbps(bw), 100);
+ bw = min_t(u64, bw, 0xFF);
+ dvfsrc_write(dvfsrc, DVFSRC_SW_PEAK_BW, bw);
+}
+
+static void mt6873_set_dram_hrtbw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ bw = div_u64((kbps_to_mbps(bw) + 29), 30);
+ bw = min_t(u64, bw, 0x3FF);
+ dvfsrc_write(dvfsrc, DVFSRC_SW_HRT_BW, bw);
+}
+
+static void mt6873_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ spin_lock(>req_lock);
+ dvfsrc_rmw(dvfsrc, DVFSRC_SW_REQ, level, 0x7, 4);
+ spin_unlock(>req_lock);
+}
+
+static void mt6873_set_vscp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ dvfsrc_rmw(dvfsrc, DVFSRC_VCORE_REQUEST, level, 0x7, 12);
+}
+
static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
{
const struct dvfsrc_opp *target, *curr;
@@ -377,6 +459,35 @@ static int mtk_dvfsrc_probe(struct platform_device *pdev)
.wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
};
+static const struct dvfsrc_opp dvfsrc_opp_mt6873_lp4[] = {
+ {0, 0}, {1, 0}, {2, 0}, {3, 0},
+ {0, 1}, {1, 1}, {2, 1}, {3, 1},
+ {0, 2}, {1, 2}, {2, 2}, {3, 2},
+ {1, 3}, {2, 3}, {3, 3}, {1, 4},
+ {2, 4}, {3, 4}, {2, 5}, {3, 5},
+ {3, 6},
+};
+
+static const struct dvfsrc_opp_desc dvfsrc_opp_mt6873_desc[] = {
+ DVFSRC_OPP_DESC(dvfsrc_opp_mt6873_lp4),
+};
+
+static const struct dvfsrc_soc_data mt6873_data = {
+ .opps_desc = dvfsrc_opp_mt6873_desc,
+ .regs = mt6873_regs,
+ .get_target_level = mt6873_get_target_level,
+ .get_current_level = mt6873_get_current_level,
+ .get_vcore_level = mt6873_get_vcore_level,
+ .get_vcp_level = mt6873_get_vcp_level,
+ .set_dram_bw = mt6873_set_dram_bw,
+ .set_dram_peak_bw = mt6873_set_dram_peak_bw,
+ .set_dram_hrtbw = mt6873_set_dram_hrtbw,
+ .set_vcore_level = mt6873_set_vcore_level,
+ .set_vscp_level = mt6873_set_vscp_level,
+ .wait_for_opp_level = mt6873_wait_for_opp_level,
+ .wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
+};
+
static int mtk_dvfsrc_remove(struct platform_device *pdev)
{
struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev);
@@ -392,6 +503,9 @@ static int mtk_dvfsrc_remove(struct platform_device *pdev)
.compatible = "mediatek,mt8183-dvfsrc",
.data = _data,
}, {
+ .co
[PATCH V9 07/12] dt-bindings: interconnect: add MT6873 interconnect dt-bindings
Add interconnect provider dt-bindings for MT6873. Signed-off-by: Henry Chen --- include/dt-bindings/interconnect/mtk,mt6873-emi.h | 41 +++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt6873-emi.h diff --git a/include/dt-bindings/interconnect/mtk,mt6873-emi.h b/include/dt-bindings/interconnect/mtk,mt6873-emi.h new file mode 100644 index 000..0b20011 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt6873-emi.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H + +#define MT6873_SLAVE_DDR_EMI 0 +#define MT6873_MASTER_MCUSYS 1 +#define MT6873_MASTER_GPUSYS 2 +#define MT6873_MASTER_MMSYS3 +#define MT6873_MASTER_MM_VPU 4 +#define MT6873_MASTER_MM_DISP 5 +#define MT6873_MASTER_MM_VDEC 6 +#define MT6873_MASTER_MM_VENC 7 +#define MT6873_MASTER_MM_CAM 8 +#define MT6873_MASTER_MM_IMG 9 +#define MT6873_MASTER_MM_MDP 10 +#define MT6873_MASTER_VPUSYS 11 +#define MT6873_MASTER_VPU_012 +#define MT6873_MASTER_VPU_113 +#define MT6873_MASTER_MDLASYS 14 +#define MT6873_MASTER_MDLA_0 15 +#define MT6873_MASTER_UFS 16 +#define MT6873_MASTER_PCIE 17 +#define MT6873_MASTER_USB 18 +#define MT6873_MASTER_DBGIF19 +#define MT6873_SLAVE_HRT_DDR_EMI 20 +#define MT6873_MASTER_HRT_MMSYS21 +#define MT6873_MASTER_HRT_MM_DISP 22 +#define MT6873_MASTER_HRT_MM_VDEC 23 +#define MT6873_MASTER_HRT_MM_VENC 24 +#define MT6873_MASTER_HRT_MM_CAM 25 +#define MT6873_MASTER_HRT_MM_IMG 26 +#define MT6873_MASTER_HRT_MM_MDP 27 +#define MT6873_MASTER_HRT_DBGIF28 +#define MT6873_MASTER_WIFI 29 +#define MT6873_MASTER_BT 30 +#define MT6873_MASTER_NETSYS 31 +#endif -- 1.9.1
[PATCH V9 01/12] dt-bindings: soc: Add dvfsrc driver bindings
Document the binding for enabling dvfsrc on MediaTek SoC.
Signed-off-by: Henry Chen
---
.../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 67 ++
include/dt-bindings/interconnect/mtk,mt8183-emi.h | 21 +++
2 files changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
new file mode 100644
index 000..f2b67b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/mediatek/dvfsrc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: MediaTek dynamic voltage and frequency scaling resource collector
(DVFSRC)
+
+description: |
+ The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
+ HW module which is used to collect all the requests from both software and
+ hardware and turn into the decision of minimum operating voltage and minimum
+ DRAM frequency to fulfill those requests.
+
+maintainers:
+ - henryc.chen
+
+properties:
+ reg:
+maxItems: 1
+description: DVFSRC common register address and length.
+
+ compatible:
+enum:
+ - mediatek,mt6873-dvfsrc
+ - mediatek,mt8183-dvfsrc
+ - mediatek,mt8192-dvfsrc
+
+ '#interconnect-cells':
+const: 1
+
+ dvfsrc-vcore:
+type: object
+description:
+ The DVFSRC regulator is modelled as a subdevice of the DVFSRC.
+ Because DVFSRC can request power directly via register read/write, likes
+ vcore which is a core power of mt8183. As such, the DVFSRC regulator
+ requires that DVFSRC nodes be present.
+$ref: /schemas/regulator/regulator.yaml#
+
+required:
+ - compatible
+ - reg
+ - "#interconnect-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+dvfsrc@10012000 {
+compatible = "mediatek,mt8183-dvfsrc";
+reg = <0 0x10012000 0 0x1000>;
+#interconnect-cells = <1>;
+dvfsrc_vcore: dvfsrc-vcore {
+regulator-name = "dvfsrc-vcore";
+regulator-min-microvolt = <725000>;
+regulator-max-microvolt = <80>;
+regulator-always-on;
+};
+};
+};
diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h
b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
new file mode 100644
index 000..dfd143f
--- /dev/null
+++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
+#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
+
+#define MT8183_SLAVE_DDR_EMI 0
+#define MT8183_MASTER_MCUSYS 1
+#define MT8183_MASTER_GPU 2
+#define MT8183_MASTER_MMSYS3
+#define MT8183_MASTER_MM_VPU 4
+#define MT8183_MASTER_MM_DISP 5
+#define MT8183_MASTER_MM_VDEC 6
+#define MT8183_MASTER_MM_VENC 7
+#define MT8183_MASTER_MM_CAM 8
+#define MT8183_MASTER_MM_IMG 9
+#define MT8183_MASTER_MM_MDP 10
+
+#endif
--
1.9.1
[PATCH V9 02/12] soc: mediatek: add header for mediatek SIP interface
Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Henry Chen Signed-off-by: Arvin Wang --- include/linux/soc/mediatek/mtk_sip_svc.h | 4 1 file changed, 4 insertions(+) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h index 082398e..079bbcb 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,4 +22,8 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) +/* VCOREFS */ +#define MTK_SIP_VCOREFS_CONTROL \ + MTK_SIP_SMC_CMD(0x506) + #endif -- 1.9.1
[PATCH V8 04/12] soc: mediatek: add support for mt6873
add support for mt6873
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/mtk-dvfsrc.c | 114 ++
1 file changed, 114 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
index c0c6d91..a422680 100644
--- a/drivers/soc/mediatek/mtk-dvfsrc.c
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -102,6 +102,16 @@ enum dvfsrc_regs {
[DVFSRC_SW_BW] =0x160,
};
+static const int mt6873_regs[] = {
+ [DVFSRC_SW_REQ] = 0xC,
+ [DVFSRC_LEVEL] =0xD44,
+ [DVFSRC_SW_PEAK_BW] = 0x278,
+ [DVFSRC_SW_BW] =0x26C,
+ [DVFSRC_SW_HRT_BW] =0x290,
+ [DVFSRC_TARGET_LEVEL] = 0xD48,
+ [DVFSRC_VCORE_REQUEST] =0x6C,
+};
+
static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc)
{
int level;
@@ -127,6 +137,78 @@ static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc
*dvfsrc, u32 level)
POLL_TIMEOUT);
}
+static int mt6873_get_target_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return dvfsrc_read(dvfsrc, DVFSRC_TARGET_LEVEL);
+}
+
+static int mt6873_get_current_level(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 curr_level;
+
+ /* HW level 0 is begin from 0x1, and max opp is 0x1*/
+ curr_level = ffs(dvfsrc_read(dvfsrc, DVFSRC_LEVEL));
+ if (curr_level > dvfsrc->curr_opps->num_opp)
+ curr_level = 0;
+ else
+ curr_level = dvfsrc->curr_opps->num_opp - curr_level;
+
+ return curr_level;
+}
+
+static int mt6873_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ const struct dvfsrc_opp *target, *curr;
+
+ target = >curr_opps->opps[level];
+ return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr,
+ curr->dram_opp >= target->dram_opp,
+ STARTUP_TIME, POLL_TIMEOUT);
+}
+
+static u32 mt6873_get_vcore_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ) >> 4) & 0x7;
+}
+
+static u32 mt6873_get_vcp_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return (dvfsrc_read(dvfsrc, DVFSRC_VCORE_REQUEST) >> 12) & 0x7;
+}
+
+static void mt6873_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ bw = div_u64(kbps_to_mbps(bw), 100);
+ bw = min_t(u64, bw, 0xFF);
+ dvfsrc_write(dvfsrc, DVFSRC_SW_BW, bw);
+}
+
+static void mt6873_set_dram_peak_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ bw = div_u64(kbps_to_mbps(bw), 100);
+ bw = min_t(u64, bw, 0xFF);
+ dvfsrc_write(dvfsrc, DVFSRC_SW_PEAK_BW, bw);
+}
+
+static void mt6873_set_dram_hrtbw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ bw = div_u64((kbps_to_mbps(bw) + 29), 30);
+ bw = min_t(u64, bw, 0x3FF);
+ dvfsrc_write(dvfsrc, DVFSRC_SW_HRT_BW, bw);
+}
+
+static void mt6873_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ spin_lock(>req_lock);
+ dvfsrc_rmw(dvfsrc, DVFSRC_SW_REQ, level, 0x7, 4);
+ spin_unlock(>req_lock);
+}
+
+static void mt6873_set_vscp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ dvfsrc_rmw(dvfsrc, DVFSRC_VCORE_REQUEST, level, 0x7, 12);
+}
+
static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
{
const struct dvfsrc_opp *target, *curr;
@@ -377,6 +459,35 @@ static int mtk_dvfsrc_probe(struct platform_device *pdev)
.wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
};
+static const struct dvfsrc_opp dvfsrc_opp_mt6873_lp4[] = {
+ {0, 0}, {1, 0}, {2, 0}, {3, 0},
+ {0, 1}, {1, 1}, {2, 1}, {3, 1},
+ {0, 2}, {1, 2}, {2, 2}, {3, 2},
+ {1, 3}, {2, 3}, {3, 3}, {1, 4},
+ {2, 4}, {3, 4}, {2, 5}, {3, 5},
+ {3, 6},
+};
+
+static const struct dvfsrc_opp_desc dvfsrc_opp_mt6873_desc[] = {
+ DVFSRC_OPP_DESC(dvfsrc_opp_mt6873_lp4),
+};
+
+static const struct dvfsrc_soc_data mt6873_data = {
+ .opps_desc = dvfsrc_opp_mt6873_desc,
+ .regs = mt6873_regs,
+ .get_target_level = mt6873_get_target_level,
+ .get_current_level = mt6873_get_current_level,
+ .get_vcore_level = mt6873_get_vcore_level,
+ .get_vcp_level = mt6873_get_vcp_level,
+ .set_dram_bw = mt6873_set_dram_bw,
+ .set_dram_peak_bw = mt6873_set_dram_peak_bw,
+ .set_dram_hrtbw = mt6873_set_dram_hrtbw,
+ .set_vcore_level = mt6873_set_vcore_level,
+ .set_vscp_level = mt6873_set_vscp_level,
+ .wait_for_opp_level = mt6873_wait_for_opp_level,
+ .wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
+};
+
static int mtk_dvfsrc_remove(struct platform_device *pdev)
{
struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev);
@@ -392,6 +503,9 @@ static int mtk_dvfsrc_remove(struct platform_device *pdev)
.compatible = "mediatek,mt8183-dvfsrc",
.data = _data,
}, {
+ .co
[PATCH V8 11/12] arm64: dts: mt8183: add dvfsrc regulator nodes
Add dvfsrc regulator nodes which is for MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index e862078..9fefc5e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -502,6 +502,12 @@
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
#interconnect-cells = <1>;
+ dvfsrc_vcore: dvfsrc-vcore {
+ regulator-name = "dvfsrc-vcore";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <80>;
+ regulator-always-on;
+ };
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V8 00/13] Add driver for dvfsrc, support for interconnect
This series is based on v5.11-rc1. The patchsets add support for MediaTek hardware module named DVFSRC (dynamic voltage and frequency scaling resource collector). The DVFSRC is a HW module which is used to collect all the requests from both software and hardware and turn into the decision of minimum operating voltage and minimum DRAM frequency to fulfill those requests. So, This series is to implement the dvfsrc driver to collect all the requests of operating voltage or DRAM bandwidth from other device drivers likes GPU/Camera through 3 frameworks basically: 1. interconnect framework: to aggregate the bandwidth requirements from different clients [1] https://patchwork.kernel.org/cover/10766329/ There has a hw module "DRAM scheduler", which used to control the throughput. The DVFSRC will collect forecast data of dram bandwidth from SW consumers(camera/gpu...), and according the forecast to change the DRAM frequency 2. Regualtor framework: to handle the operating voltage requirement from user or cosumer which not belong any power domain Changes in V8: * Fixed the dt_binding_check error of dvfsrc.yaml. (Rob) * Remove Kconfig dependency of DVFSRC Changes in V7: * Fixed the dt_binding_check error of dvfsrc.yaml. (Rob) * Fixed the checkpatch complains of "Signed-off-by: email name mismatch". (Georgi) * Fixed coding style of interconnect driver. (Georgi) * Upate comment of the years to 2021. (Georgi) Changes in V6: * Remove the performace state support, because the request from consumer can be replaced by using interconnect and regulator framework. * Update the DT patches and convert them to DT schema. (Georgi) * Modify the comment format and coding style. (Mark) Changes in V5: * Support more platform mt6873/mt8192 * Drop the compatible and interconnect provider node and make the parent node an interconnect provider. (Rob/Georgi) * Make modification of interconnect driver from coding suggestion. (Georgi) * Move interconnect diagram into the commit text of patch. (Georgi) * Register the interconnect provider as a platform sub-device. (Georgi) Changes in V4: * Add acked TAG on dt-bindings patches. (Rob) * Declaration of emi_icc_aggregate since the prototype of aggregate function has changed meanwhile. (Georgi) * Used emi_icc_remove instead of icc_provider_del on probe. (Georgi) * Add dvfsrc regulator driver into series. * Bug fixed of mt8183_get_current_level. * Add mutex protection for pstate operation on dvfsrc_set_performance. Changes in V3: * Remove RFC from the subject prefix of the series * Combine dt-binding patch and move interconnect dt-binding document into dvfsrc. (Rob) * Remove unused header, add unit descirption to the bandwidth, rename compatible name on interconnect driver. (Georgi) * Fixed some coding style: check flow, naming, used readx_poll_timeout on dvfsrc driver. (Ryan) * Rename interconnect driver mt8183.c to mtk-emi.c * Rename interconnect header mtk,mt8183.h to mtk,emi.h * mtk-scpsys.c: Add opp table check first to avoid OF runtime parse failed Changes in RFC V2: * Remove the DT property dram_type. (Rob) * Used generic dts property 'opp-level' to get the performace state. (Stephen) * Remove unecessary dependency config on Kconfig. (Stephen) * Remove unused header file, fixed some coding style issue, typo, error handling on dvfsrc driver. (Nicolas/Stephen) * Remove irq handler on dvfsrc driver. (Stephen) * Remove init table on dvfsrc driver, combine hw init on trustzone. * Add interconnect support of mt8183 to aggregate the emi bandwidth. (Georgi) V7: https://patchwork.kernel.org/project/linux-mediatek/list/?series=411057 V6: https://patchwork.kernel.org/project/linux-mediatek/list/?series=406077 V5: https://patchwork.kernel.org/project/linux-mediatek/list/?series=348065 V4: https://lore.kernel.org/patchwork/cover/1209284/ V3: https://patchwork.kernel.org/cover/8867/ RFC V2: https://lore.kernel.org/patchwork/patch/1068113/ RFC V1: https://lore.kernel.org/patchwork/cover/1028535/
[PATCH V8 05/12] arm64: dts: mt8183: add dvfsrc related nodes
Enable dvfsrc on mt8183 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5b782a4..062afe8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -497,6 +497,11 @@
#clock-cells = <1>;
};
+ ddr_emi: dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ };
+
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8183-pwrap";
reg = <0 0x1000d000 0 0x1000>;
--
1.9.1
[PATCH V8 12/12] arm64: dts: mt8192: add dvfsrc regulator nodes
Add dvfsrc regulator nodes which is for MT8192-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 81d7d05..1cf91a4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -470,6 +470,12 @@
"mediatek,mt6873-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
#interconnect-cells = <1>;
+ dvfsrc_vcore: dvfsrc-vcore {
+ regulator-name = "dvfsrc-vcore";
+ regulator-min-microvolt = <575000>;
+ regulator-max-microvolt = <725000>;
+ regulator-always-on;
+ };
};
systimer: timer@10017000 {
--
1.9.1
[PATCH V8 02/12] soc: mediatek: add header for mediatek SIP interface
Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Henry Chen Signed-off-by: Arvin Wang --- include/linux/soc/mediatek/mtk_sip_svc.h | 4 1 file changed, 4 insertions(+) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h index 082398e..079bbcb 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,4 +22,8 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) +/* VCOREFS */ +#define MTK_SIP_VCOREFS_CONTROL \ + MTK_SIP_SMC_CMD(0x506) + #endif -- 1.9.1
[PATCH V8 10/12] arm64: dts: mt8192: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index dbefc0d..81d7d05 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include
+#include
#include
#include
#include
@@ -468,6 +469,7 @@
compatible = "mediatek,mt8192-dvfsrc",
"mediatek,mt6873-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
systimer: timer@10017000 {
--
1.9.1
[PATCH V8 01/12] dt-bindings: soc: Add dvfsrc driver bindings
Document the binding for enabling dvfsrc on MediaTek SoC.
Signed-off-by: Henry Chen
---
.../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 67 ++
include/dt-bindings/interconnect/mtk,mt8183-emi.h | 21 +++
2 files changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
new file mode 100644
index 000..0b746a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/mediatek/dvfsrc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: MediaTek dynamic voltage and frequency scaling resource collector
(DVFSRC)
+
+description: |
+ The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
+ HW module which is used to collect all the requests from both software and
+ hardware and turn into the decision of minimum operating voltage and minimum
+ DRAM frequency to fulfill those requests.
+
+maintainers:
+ - henryc.chen
+
+properties:
+ reg:
+description: DVFSRC common register address and length.
+
+ compatible:
+enum:
+ - mediatek,mt6873-dvfsrc
+ - mediatek,mt8183-dvfsrc
+ - mediatek,mt8192-dvfsrc
+
+ '#interconnect-cells':
+const: 1
+
+patternProperties:
+ dvfsrc-vcore:
+type: object
+description:
+ The DVFSRC regulator is modelled as a subdevice of the DVFSRC.
+ Because DVFSRC can request power directly via register read/write, likes
+ vcore which is a core power of mt8183. As such, the DVFSRC regulator
+ requires that DVFSRC nodes be present.
+$ref: /schemas/regulator/regulator.yaml#
+
+required:
+ - compatible
+ - reg
+ - "#interconnect-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+dvfsrc@10012000 {
+compatible = "mediatek,mt8183-dvfsrc";
+reg = <0 0x10012000 0 0x1000>;
+#interconnect-cells = <1>;
+dvfsrc_vcore: dvfsrc-vcore {
+regulator-name = "dvfsrc-vcore";
+regulator-min-microvolt = <725000>;
+regulator-max-microvolt = <80>;
+regulator-always-on;
+};
+};
+};
diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h
b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
new file mode 100644
index 000..dfd143f
--- /dev/null
+++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
+#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
+
+#define MT8183_SLAVE_DDR_EMI 0
+#define MT8183_MASTER_MCUSYS 1
+#define MT8183_MASTER_GPU 2
+#define MT8183_MASTER_MMSYS3
+#define MT8183_MASTER_MM_VPU 4
+#define MT8183_MASTER_MM_DISP 5
+#define MT8183_MASTER_MM_VDEC 6
+#define MT8183_MASTER_MM_VENC 7
+#define MT8183_MASTER_MM_CAM 8
+#define MT8183_MASTER_MM_IMG 9
+#define MT8183_MASTER_MM_MDP 10
+
+#endif
--
1.9.1
[PATCH V8 09/12] arm64: dts: mt8183: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8192-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 062afe8..e862078 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
#include
@@ -500,6 +501,7 @@
ddr_emi: dvfsrc@10012000 {
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V8 06/12] arm64: dts: mt8192: add dvfsrc related nodes
Enable dvfsrc on mt8192 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 8252143..dbefc0d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -464,6 +464,12 @@
#clock-cells = <1>;
};
+ ddr_emi: dvfsrc@10012000 {
+ compatible = "mediatek,mt8192-dvfsrc",
+"mediatek,mt6873-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
--
1.9.1
[PATCH V8 03/12] soc: mediatek: add driver for dvfsrc support
Add dvfsrc driver for MT6873/MT8183/MT8192
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/Kconfig| 11 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 421
include/linux/soc/mediatek/mtk_dvfsrc.h | 35 +++
4 files changed, 468 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc0..2dcf023 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -26,6 +26,17 @@ config MTK_DEVAPC
The violation information is logged for further analysis or
countermeasures.
+config MTK_DVFSRC
+ tristate "MediaTek DVFSRC Support"
+ depends on ARCH_MEDIATEK
+ help
+ Say yes here to add support for the MediaTek DVFSRC (dynamic voltage
+ and frequency scaling resource collector) found
+ on different MediaTek SoCs. The DVFSRC is a proprietary
+ hardware which is used to collect all the requests from
+ system and turn into the decision of minimum Vcore voltage
+ and minimum DRAM frequency to fulfill those requests.
+
config MTK_INFRACFG
bool "MediaTek INFRACFG Support"
select REGMAP
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b6908db..4ead103 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
+obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
new file mode 100644
index 000..c0c6d91
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DVFSRC_IDLE 0x00
+#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
+#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x)
+#define kbps_to_mbps(x) ((x) / 1000)
+
+#define POLL_TIMEOUT1000
+#define STARTUP_TIME1
+
+#define MTK_SIP_DVFSRC_INIT0x00
+
+#define DVFSRC_OPP_DESC(_opp_table)\
+{ \
+ .opps = _opp_table, \
+ .num_opp = ARRAY_SIZE(_opp_table), \
+}
+
+struct dvfsrc_opp {
+ u32 vcore_opp;
+ u32 dram_opp;
+};
+
+struct dvfsrc_opp_desc {
+ const struct dvfsrc_opp *opps;
+ u32 num_opp;
+};
+
+struct mtk_dvfsrc;
+struct dvfsrc_soc_data {
+ const int *regs;
+ const struct dvfsrc_opp_desc *opps_desc;
+ int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
+ int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc);
+ void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+};
+
+struct mtk_dvfsrc {
+ struct device *dev;
+ struct platform_device *icc;
+ struct platform_device *regulator;
+ const struct dvfsrc_soc_data *dvd;
+ int dram_type;
+ const struct dvfsrc_opp_desc *curr_opps;
+ void __iomem *regs;
+ spinlock_t req_lock;
+ struct mutex pstate_lock;
+ struct notifier_block scpsys_notifier;
+};
+
+static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
+{
+ return readl(dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
+{
+ writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \
+ dvfsrc_write(dvfs, offset, \
+ (dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val << shift))
+
+enum dvfsrc_regs {
+ DVFSRC_SW_REQ,
+ DVFSRC_SW_REQ2,
+ DVFSRC_LEVEL,
+ DVFSRC_TARGET_LEVEL,
+ DVFSRC_SW_BW,
+ DVFSRC_SW_PEAK_BW,
+ DVFSRC_SW_HRT_BW,
+ DVFSRC_VCORE_REQUEST,
+};
+
+static const int mt8183_regs[] = {
+ [DVFSRC_SW_REQ] = 0x4,
[PATCH V8 08/12] interconnect: mediatek: Add interconnect provider driver
Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver
using the interconnect framework.
ICC provider ICC Nodes
- |CPU | |--- |VPU |
- | |- |
|DRAM |--|DRAM | |
| |--|scheduler|- |GPU | |--- |DISP|
| |--|(EMI)| |
| |--| | - |
- | |- |MMSYS|--|--- |VDEC|
-- |
/|\|
|change DRAM freq |--- |VENC|
-- |
| DVFSR | |
| | |
-- |--- |IMG |
|
|
|--- |CAM |
Signed-off-by: Henry Chen
---
drivers/interconnect/Kconfig| 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 13 ++
drivers/interconnect/mediatek/Makefile | 3 +
drivers/interconnect/mediatek/mtk-emi.c | 331
5 files changed, 349 insertions(+)
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/mtk-emi.c
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
index d637a89..da91f84 100644
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@@ -12,6 +12,7 @@ menuconfig INTERCONNECT
if INTERCONNECT
source "drivers/interconnect/imx/Kconfig"
+source "drivers/interconnect/mediatek/Kconfig"
source "drivers/interconnect/qcom/Kconfig"
source "drivers/interconnect/samsung/Kconfig"
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
index 97d393f..d697500 100644
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@@ -5,5 +5,6 @@ icc-core-objs := core.o bulk.o
obj-$(CONFIG_INTERCONNECT) += icc-core.o
obj-$(CONFIG_INTERCONNECT_IMX) += imx/
+obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/
obj-$(CONFIG_INTERCONNECT_QCOM)+= qcom/
obj-$(CONFIG_INTERCONNECT_SAMSUNG) += samsung/
diff --git a/drivers/interconnect/mediatek/Kconfig
b/drivers/interconnect/mediatek/Kconfig
new file mode 100644
index 000..ec98d6a
--- /dev/null
+++ b/drivers/interconnect/mediatek/Kconfig
@@ -0,0 +1,13 @@
+config INTERCONNECT_MTK
+ bool "Mediatek Network-on-Chip interconnect drivers"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ help
+ Support for Mediatek's Network-on-Chip interconnect hardware.
+
+config INTERCONNECT_MTK_EMI
+ tristate "Mediatek EMI interconnect driver"
+ depends on INTERCONNECT_MTK
+ depends on (MTK_DVFSRC && OF) || COMPILE_TEST
+ help
+ This is a driver for the Mediatek Network-on-Chip on DVFSRC-based
+ platforms.
diff --git a/drivers/interconnect/mediatek/Makefile
b/drivers/interconnect/mediatek/Makefile
new file mode 100644
index 000..353842b
--- /dev/null
+++ b/drivers/interconnect/mediatek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o
\ No newline at end of file
diff --git a/drivers/interconnect/mediatek/mtk-emi.c
b/drivers/interconnect/mediatek/mtk-emi.c
new file mode 100644
index 000..8d650be
--- /dev/null
+++ b/drivers/interconnect/mediatek/mtk-emi.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum mtk_icc_name {
+ SLAVE_DDR_EMI,
+ MASTER_MCUSYS,
+ MASTER_GPUSYS,
+ MASTER_MMSYS,
+ MASTER_MM_VPU,
+ MASTER_MM_DISP,
+ MASTER_MM_VDEC,
+ MASTER_MM_VENC,
+ MASTER_MM_CAM,
+ MASTER_MM_IMG,
+ MASTER_MM_MDP,
+ MASTER_VPUSYS,
+ MASTER_VPU_PORT_0,
+ MASTER_VPU_PORT_1,
+ MASTER_MDLASYS,
+ MASTER_MDLA_PORT_0,
+ MASTER_UFS,
+ MASTER_PCIE,
+ MASTER_USB,
+ MASTER_WIFI,
+ MASTER_BT,
+ MASTER_NETSYS,
+ MASTER_DBGIF,
+
+ SLAVE_HRT_DDR_EMI,
+ MASTER_HRT_MMSYS,
+ MASTER_HRT_MM_DISP,
+ MASTER_HRT_MM_VDEC,
+ MASTER_HRT_MM_VENC,
+ MASTER_HRT_MM_CAM,
+ MASTER_HRT_MM_IMG,
+ MASTER_HRT_MM_MDP,
+ MASTER_HRT_DBGIF,
+};
+
+#define MT8183_MAX_LINKS 1
+
+/**
+ * struct mtk_icc_node - Mediatek specific interconnect nodes
+ * @name: the n
[PATCH V8 07/12] dt-bindings: interconnect: add MT6873 interconnect dt-bindings
Add interconnect provider dt-bindings for MT6873. Signed-off-by: Henry Chen --- include/dt-bindings/interconnect/mtk,mt6873-emi.h | 41 +++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt6873-emi.h diff --git a/include/dt-bindings/interconnect/mtk,mt6873-emi.h b/include/dt-bindings/interconnect/mtk,mt6873-emi.h new file mode 100644 index 000..0b20011 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt6873-emi.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H + +#define MT6873_SLAVE_DDR_EMI 0 +#define MT6873_MASTER_MCUSYS 1 +#define MT6873_MASTER_GPUSYS 2 +#define MT6873_MASTER_MMSYS3 +#define MT6873_MASTER_MM_VPU 4 +#define MT6873_MASTER_MM_DISP 5 +#define MT6873_MASTER_MM_VDEC 6 +#define MT6873_MASTER_MM_VENC 7 +#define MT6873_MASTER_MM_CAM 8 +#define MT6873_MASTER_MM_IMG 9 +#define MT6873_MASTER_MM_MDP 10 +#define MT6873_MASTER_VPUSYS 11 +#define MT6873_MASTER_VPU_012 +#define MT6873_MASTER_VPU_113 +#define MT6873_MASTER_MDLASYS 14 +#define MT6873_MASTER_MDLA_0 15 +#define MT6873_MASTER_UFS 16 +#define MT6873_MASTER_PCIE 17 +#define MT6873_MASTER_USB 18 +#define MT6873_MASTER_DBGIF19 +#define MT6873_SLAVE_HRT_DDR_EMI 20 +#define MT6873_MASTER_HRT_MMSYS21 +#define MT6873_MASTER_HRT_MM_DISP 22 +#define MT6873_MASTER_HRT_MM_VDEC 23 +#define MT6873_MASTER_HRT_MM_VENC 24 +#define MT6873_MASTER_HRT_MM_CAM 25 +#define MT6873_MASTER_HRT_MM_IMG 26 +#define MT6873_MASTER_HRT_MM_MDP 27 +#define MT6873_MASTER_HRT_DBGIF28 +#define MT6873_MASTER_WIFI 29 +#define MT6873_MASTER_BT 30 +#define MT6873_MASTER_NETSYS 31 +#endif -- 1.9.1
Re: [PATCH V7 01/13] dt-bindings: soc: Add dvfsrc driver bindings
On Mon, 2021-01-11 at 09:42 -0600, Rob Herring wrote: > On Sun, Jan 10, 2021 at 8:52 PM Henry Chen wrote: > > > > Hi Rob, > > > > On Fri, 2021-01-08 at 20:30 -0700, Rob Herring wrote: > > > On Fri, 08 Jan 2021 15:48:03 +0800, Henry Chen wrote: > > > > Document the binding for enabling dvfsrc on MediaTek SoC. > > > > > > > > Signed-off-by: Henry Chen > > > > --- > > > > .../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 67 > > > > ++ > > > > 1 file changed, 67 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml > > > > > > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > > > > > yamllint warnings/errors: > > > > > > dtschema/dtc warnings/errors: > > > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.example.dts:19:18: > > > fatal error: dt-bindings/interconnect/mtk,mt8183-emi.h: No such file or > > > directory > > >19 | #include > > > | ^~~ > > Sorry, because this header file is added on "[V7,07/13] dt-bindings: > > interconnect: add MT8183 interconnect dt-bindings". > > Should I change the order of the patchset (let the yaml pathc behind the > > header) to fixed that ? > > DT headers should be part of the binding schema patch. (Or at least come > first). OK, I will merge DT header and binding schema patch into a single patch. Henry > > Rob
Re: [PATCH V7 01/13] dt-bindings: soc: Add dvfsrc driver bindings
Hi Rob, On Fri, 2021-01-08 at 20:30 -0700, Rob Herring wrote: > On Fri, 08 Jan 2021 15:48:03 +0800, Henry Chen wrote: > > Document the binding for enabling dvfsrc on MediaTek SoC. > > > > Signed-off-by: Henry Chen > > --- > > .../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 67 > > ++ > > 1 file changed, 67 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.example.dts:19:18: > fatal error: dt-bindings/interconnect/mtk,mt8183-emi.h: No such file or > directory >19 | #include > | ^~~ Sorry, because this header file is added on "[V7,07/13] dt-bindings: interconnect: add MT8183 interconnect dt-bindings". Should I change the order of the patchset (let the yaml pathc behind the header) to fixed that ? Thanks, Henry > compilation terminated. > make[1]: *** [scripts/Makefile.lib:344: > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.example.dt.yaml] Error 1 > make: *** [Makefile:1370: dt_binding_check] Error 2 > > See https://patchwork.ozlabs.org/patch/1423679 > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. >
[PATCH V7 01/13] dt-bindings: soc: Add dvfsrc driver bindings
Document the binding for enabling dvfsrc on MediaTek SoC.
Signed-off-by: Henry Chen
---
.../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 67 ++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
new file mode 100644
index 000..0b746a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/mediatek/dvfsrc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: MediaTek dynamic voltage and frequency scaling resource collector
(DVFSRC)
+
+description: |
+ The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
+ HW module which is used to collect all the requests from both software and
+ hardware and turn into the decision of minimum operating voltage and minimum
+ DRAM frequency to fulfill those requests.
+
+maintainers:
+ - henryc.chen
+
+properties:
+ reg:
+description: DVFSRC common register address and length.
+
+ compatible:
+enum:
+ - mediatek,mt6873-dvfsrc
+ - mediatek,mt8183-dvfsrc
+ - mediatek,mt8192-dvfsrc
+
+ '#interconnect-cells':
+const: 1
+
+patternProperties:
+ dvfsrc-vcore:
+type: object
+description:
+ The DVFSRC regulator is modelled as a subdevice of the DVFSRC.
+ Because DVFSRC can request power directly via register read/write, likes
+ vcore which is a core power of mt8183. As such, the DVFSRC regulator
+ requires that DVFSRC nodes be present.
+$ref: /schemas/regulator/regulator.yaml#
+
+required:
+ - compatible
+ - reg
+ - "#interconnect-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+dvfsrc@10012000 {
+compatible = "mediatek,mt8183-dvfsrc";
+reg = <0 0x10012000 0 0x1000>;
+#interconnect-cells = <1>;
+dvfsrc_vcore: dvfsrc-vcore {
+regulator-name = "dvfsrc-vcore";
+regulator-min-microvolt = <725000>;
+regulator-max-microvolt = <80>;
+regulator-always-on;
+};
+};
+};
--
1.9.1
[PATCH V7 09/13] interconnect: mediatek: Add interconnect provider driver
Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver
using the interconnect framework.
ICC provider ICC Nodes
- |CPU | |--- |VPU |
- | |- |
|DRAM |--|DRAM | |
| |--|scheduler|- |GPU | |--- |DISP|
| |--|(EMI)| |
| |--| | - |
- | |- |MMSYS|--|--- |VDEC|
-- |
/|\|
|change DRAM freq |--- |VENC|
-- |
| DVFSR | |
| | |
-- |--- |IMG |
|
|
|--- |CAM |
Signed-off-by: Henry Chen
---
drivers/interconnect/Kconfig| 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 13 ++
drivers/interconnect/mediatek/Makefile | 3 +
drivers/interconnect/mediatek/mtk-emi.c | 331
5 files changed, 349 insertions(+)
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/mtk-emi.c
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
index d637a89..da91f84 100644
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@@ -12,6 +12,7 @@ menuconfig INTERCONNECT
if INTERCONNECT
source "drivers/interconnect/imx/Kconfig"
+source "drivers/interconnect/mediatek/Kconfig"
source "drivers/interconnect/qcom/Kconfig"
source "drivers/interconnect/samsung/Kconfig"
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
index 97d393f..d697500 100644
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@@ -5,5 +5,6 @@ icc-core-objs := core.o bulk.o
obj-$(CONFIG_INTERCONNECT) += icc-core.o
obj-$(CONFIG_INTERCONNECT_IMX) += imx/
+obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/
obj-$(CONFIG_INTERCONNECT_QCOM)+= qcom/
obj-$(CONFIG_INTERCONNECT_SAMSUNG) += samsung/
diff --git a/drivers/interconnect/mediatek/Kconfig
b/drivers/interconnect/mediatek/Kconfig
new file mode 100644
index 000..ec98d6a
--- /dev/null
+++ b/drivers/interconnect/mediatek/Kconfig
@@ -0,0 +1,13 @@
+config INTERCONNECT_MTK
+ bool "Mediatek Network-on-Chip interconnect drivers"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ help
+ Support for Mediatek's Network-on-Chip interconnect hardware.
+
+config INTERCONNECT_MTK_EMI
+ tristate "Mediatek EMI interconnect driver"
+ depends on INTERCONNECT_MTK
+ depends on (MTK_DVFSRC && OF) || COMPILE_TEST
+ help
+ This is a driver for the Mediatek Network-on-Chip on DVFSRC-based
+ platforms.
diff --git a/drivers/interconnect/mediatek/Makefile
b/drivers/interconnect/mediatek/Makefile
new file mode 100644
index 000..353842b
--- /dev/null
+++ b/drivers/interconnect/mediatek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o
\ No newline at end of file
diff --git a/drivers/interconnect/mediatek/mtk-emi.c
b/drivers/interconnect/mediatek/mtk-emi.c
new file mode 100644
index 000..8d650be
--- /dev/null
+++ b/drivers/interconnect/mediatek/mtk-emi.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum mtk_icc_name {
+ SLAVE_DDR_EMI,
+ MASTER_MCUSYS,
+ MASTER_GPUSYS,
+ MASTER_MMSYS,
+ MASTER_MM_VPU,
+ MASTER_MM_DISP,
+ MASTER_MM_VDEC,
+ MASTER_MM_VENC,
+ MASTER_MM_CAM,
+ MASTER_MM_IMG,
+ MASTER_MM_MDP,
+ MASTER_VPUSYS,
+ MASTER_VPU_PORT_0,
+ MASTER_VPU_PORT_1,
+ MASTER_MDLASYS,
+ MASTER_MDLA_PORT_0,
+ MASTER_UFS,
+ MASTER_PCIE,
+ MASTER_USB,
+ MASTER_WIFI,
+ MASTER_BT,
+ MASTER_NETSYS,
+ MASTER_DBGIF,
+
+ SLAVE_HRT_DDR_EMI,
+ MASTER_HRT_MMSYS,
+ MASTER_HRT_MM_DISP,
+ MASTER_HRT_MM_VDEC,
+ MASTER_HRT_MM_VENC,
+ MASTER_HRT_MM_CAM,
+ MASTER_HRT_MM_IMG,
+ MASTER_HRT_MM_MDP,
+ MASTER_HRT_DBGIF,
+};
+
+#define MT8183_MAX_LINKS 1
+
+/**
+ * struct mtk_icc_node - Mediatek specific interconnect nodes
+ * @name: the n
[PATCH V7 07/13] dt-bindings: interconnect: add MT8183 interconnect dt-bindings
Add interconnect provider dt-bindings for MT8183. Signed-off-by: Henry Chen Reviewed-by: Rob Herring --- include/dt-bindings/interconnect/mtk,mt8183-emi.h | 21 + 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h new file mode 100644 index 000..dfd143f --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H + +#define MT8183_SLAVE_DDR_EMI 0 +#define MT8183_MASTER_MCUSYS 1 +#define MT8183_MASTER_GPU 2 +#define MT8183_MASTER_MMSYS3 +#define MT8183_MASTER_MM_VPU 4 +#define MT8183_MASTER_MM_DISP 5 +#define MT8183_MASTER_MM_VDEC 6 +#define MT8183_MASTER_MM_VENC 7 +#define MT8183_MASTER_MM_CAM 8 +#define MT8183_MASTER_MM_IMG 9 +#define MT8183_MASTER_MM_MDP 10 + +#endif -- 1.9.1
[PATCH V7 05/13] arm64: dts: mt8183: add dvfsrc related nodes
Enable dvfsrc on mt8183 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5b782a4..062afe8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -497,6 +497,11 @@
#clock-cells = <1>;
};
+ ddr_emi: dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ };
+
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8183-pwrap";
reg = <0 0x1000d000 0 0x1000>;
--
1.9.1
[PATCH V7 08/13] dt-bindings: interconnect: add MT6873 interconnect dt-bindings
Add interconnect provider dt-bindings for MT6873. Signed-off-by: Henry Chen --- include/dt-bindings/interconnect/mtk,mt6873-emi.h | 41 +++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt6873-emi.h diff --git a/include/dt-bindings/interconnect/mtk,mt6873-emi.h b/include/dt-bindings/interconnect/mtk,mt6873-emi.h new file mode 100644 index 000..0b20011 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt6873-emi.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H + +#define MT6873_SLAVE_DDR_EMI 0 +#define MT6873_MASTER_MCUSYS 1 +#define MT6873_MASTER_GPUSYS 2 +#define MT6873_MASTER_MMSYS3 +#define MT6873_MASTER_MM_VPU 4 +#define MT6873_MASTER_MM_DISP 5 +#define MT6873_MASTER_MM_VDEC 6 +#define MT6873_MASTER_MM_VENC 7 +#define MT6873_MASTER_MM_CAM 8 +#define MT6873_MASTER_MM_IMG 9 +#define MT6873_MASTER_MM_MDP 10 +#define MT6873_MASTER_VPUSYS 11 +#define MT6873_MASTER_VPU_012 +#define MT6873_MASTER_VPU_113 +#define MT6873_MASTER_MDLASYS 14 +#define MT6873_MASTER_MDLA_0 15 +#define MT6873_MASTER_UFS 16 +#define MT6873_MASTER_PCIE 17 +#define MT6873_MASTER_USB 18 +#define MT6873_MASTER_DBGIF19 +#define MT6873_SLAVE_HRT_DDR_EMI 20 +#define MT6873_MASTER_HRT_MMSYS21 +#define MT6873_MASTER_HRT_MM_DISP 22 +#define MT6873_MASTER_HRT_MM_VDEC 23 +#define MT6873_MASTER_HRT_MM_VENC 24 +#define MT6873_MASTER_HRT_MM_CAM 25 +#define MT6873_MASTER_HRT_MM_IMG 26 +#define MT6873_MASTER_HRT_MM_MDP 27 +#define MT6873_MASTER_HRT_DBGIF28 +#define MT6873_MASTER_WIFI 29 +#define MT6873_MASTER_BT 30 +#define MT6873_MASTER_NETSYS 31 +#endif -- 1.9.1
[PATCH V7 04/13] soc: mediatek: add support for mt6873
add support for mt6873
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/mtk-dvfsrc.c | 114 ++
1 file changed, 114 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
index c0c6d91..a422680 100644
--- a/drivers/soc/mediatek/mtk-dvfsrc.c
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -102,6 +102,16 @@ enum dvfsrc_regs {
[DVFSRC_SW_BW] =0x160,
};
+static const int mt6873_regs[] = {
+ [DVFSRC_SW_REQ] = 0xC,
+ [DVFSRC_LEVEL] =0xD44,
+ [DVFSRC_SW_PEAK_BW] = 0x278,
+ [DVFSRC_SW_BW] =0x26C,
+ [DVFSRC_SW_HRT_BW] =0x290,
+ [DVFSRC_TARGET_LEVEL] = 0xD48,
+ [DVFSRC_VCORE_REQUEST] =0x6C,
+};
+
static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc)
{
int level;
@@ -127,6 +137,78 @@ static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc
*dvfsrc, u32 level)
POLL_TIMEOUT);
}
+static int mt6873_get_target_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return dvfsrc_read(dvfsrc, DVFSRC_TARGET_LEVEL);
+}
+
+static int mt6873_get_current_level(struct mtk_dvfsrc *dvfsrc)
+{
+ u32 curr_level;
+
+ /* HW level 0 is begin from 0x1, and max opp is 0x1*/
+ curr_level = ffs(dvfsrc_read(dvfsrc, DVFSRC_LEVEL));
+ if (curr_level > dvfsrc->curr_opps->num_opp)
+ curr_level = 0;
+ else
+ curr_level = dvfsrc->curr_opps->num_opp - curr_level;
+
+ return curr_level;
+}
+
+static int mt6873_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ const struct dvfsrc_opp *target, *curr;
+
+ target = >curr_opps->opps[level];
+ return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr,
+ curr->dram_opp >= target->dram_opp,
+ STARTUP_TIME, POLL_TIMEOUT);
+}
+
+static u32 mt6873_get_vcore_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ) >> 4) & 0x7;
+}
+
+static u32 mt6873_get_vcp_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return (dvfsrc_read(dvfsrc, DVFSRC_VCORE_REQUEST) >> 12) & 0x7;
+}
+
+static void mt6873_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ bw = div_u64(kbps_to_mbps(bw), 100);
+ bw = min_t(u64, bw, 0xFF);
+ dvfsrc_write(dvfsrc, DVFSRC_SW_BW, bw);
+}
+
+static void mt6873_set_dram_peak_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ bw = div_u64(kbps_to_mbps(bw), 100);
+ bw = min_t(u64, bw, 0xFF);
+ dvfsrc_write(dvfsrc, DVFSRC_SW_PEAK_BW, bw);
+}
+
+static void mt6873_set_dram_hrtbw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+ bw = div_u64((kbps_to_mbps(bw) + 29), 30);
+ bw = min_t(u64, bw, 0x3FF);
+ dvfsrc_write(dvfsrc, DVFSRC_SW_HRT_BW, bw);
+}
+
+static void mt6873_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ spin_lock(>req_lock);
+ dvfsrc_rmw(dvfsrc, DVFSRC_SW_REQ, level, 0x7, 4);
+ spin_unlock(>req_lock);
+}
+
+static void mt6873_set_vscp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ dvfsrc_rmw(dvfsrc, DVFSRC_VCORE_REQUEST, level, 0x7, 12);
+}
+
static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
{
const struct dvfsrc_opp *target, *curr;
@@ -377,6 +459,35 @@ static int mtk_dvfsrc_probe(struct platform_device *pdev)
.wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
};
+static const struct dvfsrc_opp dvfsrc_opp_mt6873_lp4[] = {
+ {0, 0}, {1, 0}, {2, 0}, {3, 0},
+ {0, 1}, {1, 1}, {2, 1}, {3, 1},
+ {0, 2}, {1, 2}, {2, 2}, {3, 2},
+ {1, 3}, {2, 3}, {3, 3}, {1, 4},
+ {2, 4}, {3, 4}, {2, 5}, {3, 5},
+ {3, 6},
+};
+
+static const struct dvfsrc_opp_desc dvfsrc_opp_mt6873_desc[] = {
+ DVFSRC_OPP_DESC(dvfsrc_opp_mt6873_lp4),
+};
+
+static const struct dvfsrc_soc_data mt6873_data = {
+ .opps_desc = dvfsrc_opp_mt6873_desc,
+ .regs = mt6873_regs,
+ .get_target_level = mt6873_get_target_level,
+ .get_current_level = mt6873_get_current_level,
+ .get_vcore_level = mt6873_get_vcore_level,
+ .get_vcp_level = mt6873_get_vcp_level,
+ .set_dram_bw = mt6873_set_dram_bw,
+ .set_dram_peak_bw = mt6873_set_dram_peak_bw,
+ .set_dram_hrtbw = mt6873_set_dram_hrtbw,
+ .set_vcore_level = mt6873_set_vcore_level,
+ .set_vscp_level = mt6873_set_vscp_level,
+ .wait_for_opp_level = mt6873_wait_for_opp_level,
+ .wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
+};
+
static int mtk_dvfsrc_remove(struct platform_device *pdev)
{
struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev);
@@ -392,6 +503,9 @@ static int mtk_dvfsrc_remove(struct platform_device *pdev)
.compatible = "mediatek,mt8183-dvfsrc",
.data = _data,
}, {
+ .co
[PATCH V7 02/13] soc: mediatek: add header for mediatek SIP interface
Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Henry Chen Signed-off-by: Arvin Wang --- include/linux/soc/mediatek/mtk_sip_svc.h | 4 1 file changed, 4 insertions(+) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h index 082398e..079bbcb 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,4 +22,8 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) +/* VCOREFS */ +#define MTK_SIP_VCOREFS_CONTROL \ + MTK_SIP_SMC_CMD(0x506) + #endif -- 1.9.1
[PATCH V7 12/13] arm64: dts: mt8183: add dvfsrc regulator nodes
Add dvfsrc regulator nodes which is for MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index e862078..9fefc5e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -502,6 +502,12 @@
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
#interconnect-cells = <1>;
+ dvfsrc_vcore: dvfsrc-vcore {
+ regulator-name = "dvfsrc-vcore";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <80>;
+ regulator-always-on;
+ };
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V7 03/13] soc: mediatek: add driver for dvfsrc support
Add dvfsrc driver for MT6873/MT8183/MT8192
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/Kconfig| 12 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 421
include/linux/soc/mediatek/mtk_dvfsrc.h | 35 +++
4 files changed, 469 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc0..693a0ff 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -26,6 +26,18 @@ config MTK_DEVAPC
The violation information is logged for further analysis or
countermeasures.
+config MTK_DVFSRC
+ tristate "MediaTek DVFSRC Support"
+ depends on ARCH_MEDIATEK
+ depends on MTK_SCPSYS
+ help
+ Say yes here to add support for the MediaTek DVFSRC (dynamic voltage
+ and frequency scaling resource collector) found
+ on different MediaTek SoCs. The DVFSRC is a proprietary
+ hardware which is used to collect all the requests from
+ system and turn into the decision of minimum Vcore voltage
+ and minimum DRAM frequency to fulfill those requests.
+
config MTK_INFRACFG
bool "MediaTek INFRACFG Support"
select REGMAP
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b6908db..4ead103 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
+obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
new file mode 100644
index 000..c0c6d91
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DVFSRC_IDLE 0x00
+#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
+#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x)
+#define kbps_to_mbps(x) ((x) / 1000)
+
+#define POLL_TIMEOUT1000
+#define STARTUP_TIME1
+
+#define MTK_SIP_DVFSRC_INIT0x00
+
+#define DVFSRC_OPP_DESC(_opp_table)\
+{ \
+ .opps = _opp_table, \
+ .num_opp = ARRAY_SIZE(_opp_table), \
+}
+
+struct dvfsrc_opp {
+ u32 vcore_opp;
+ u32 dram_opp;
+};
+
+struct dvfsrc_opp_desc {
+ const struct dvfsrc_opp *opps;
+ u32 num_opp;
+};
+
+struct mtk_dvfsrc;
+struct dvfsrc_soc_data {
+ const int *regs;
+ const struct dvfsrc_opp_desc *opps_desc;
+ int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
+ int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc);
+ void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+};
+
+struct mtk_dvfsrc {
+ struct device *dev;
+ struct platform_device *icc;
+ struct platform_device *regulator;
+ const struct dvfsrc_soc_data *dvd;
+ int dram_type;
+ const struct dvfsrc_opp_desc *curr_opps;
+ void __iomem *regs;
+ spinlock_t req_lock;
+ struct mutex pstate_lock;
+ struct notifier_block scpsys_notifier;
+};
+
+static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
+{
+ return readl(dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
+{
+ writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \
+ dvfsrc_write(dvfs, offset, \
+ (dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val << shift))
+
+enum dvfsrc_regs {
+ DVFSRC_SW_REQ,
+ DVFSRC_SW_REQ2,
+ DVFSRC_LEVEL,
+ DVFSRC_TARGET_LEVEL,
+ DVFSRC_SW_BW,
+ DVFSRC_SW_PEAK_BW,
+ DVFSRC_SW_HRT_BW,
+ DVFSRC_VCORE_REQUEST,
+};
+
+static const int mt8183_regs[] =
[PATCH V7 11/13] arm64: dts: mt8192: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index dbefc0d..81d7d05 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include
+#include
#include
#include
#include
@@ -468,6 +469,7 @@
compatible = "mediatek,mt8192-dvfsrc",
"mediatek,mt6873-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
systimer: timer@10017000 {
--
1.9.1
[PATCH V7 13/13] arm64: dts: mt8192: add dvfsrc regulator nodes
Add dvfsrc regulator nodes which is for MT8192-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 81d7d05..1cf91a4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -470,6 +470,12 @@
"mediatek,mt6873-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
#interconnect-cells = <1>;
+ dvfsrc_vcore: dvfsrc-vcore {
+ regulator-name = "dvfsrc-vcore";
+ regulator-min-microvolt = <575000>;
+ regulator-max-microvolt = <725000>;
+ regulator-always-on;
+ };
};
systimer: timer@10017000 {
--
1.9.1
[PATCH V7 10/13] arm64: dts: mt8183: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8192-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 062afe8..e862078 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
#include
@@ -500,6 +501,7 @@
ddr_emi: dvfsrc@10012000 {
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V7 00/13] Add driver for dvfsrc, support for active state of scpsys
This series is based on v5.11-rc1. The patchsets add support for MediaTek hardware module named DVFSRC (dynamic voltage and frequency scaling resource collector). The DVFSRC is a HW module which is used to collect all the requests from both software and hardware and turn into the decision of minimum operating voltage and minimum DRAM frequency to fulfill those requests. So, This series is to implement the dvfsrc driver to collect all the requests of operating voltage or DRAM bandwidth from other device drivers likes GPU/Camera through 3 frameworks basically: 1. interconnect framework: to aggregate the bandwidth requirements from different clients [1] https://patchwork.kernel.org/cover/10766329/ There has a hw module "DRAM scheduler", which used to control the throughput. The DVFSRC will collect forecast data of dram bandwidth from SW consumers(camera/gpu...), and according the forecast to change the DRAM frequency 2. Regualtor framework: to handle the operating voltage requirement from user or cosumer which not belong any power domain Changes in V7: * Fixed the dt_binding_check error of dvfsrc.yaml. (Rob) * Fixed the checkpatch complains of "Signed-off-by: email name mismatch". (Georgi) * Fixed coding style of interconnect driver. (Georgi) * Upate comment of the years to 2021. (Georgi) Changes in V6: * Remove the performace state support, because the request from consumer can be replaced by using interconnect and regulator framework. * Update the DT patches and convert them to DT schema. (Georgi) * Modify the comment format and coding style. (Mark) Changes in V5: * Support more platform mt6873/mt8192 * Drop the compatible and interconnect provider node and make the parent node an interconnect provider. (Rob/Georgi) * Make modification of interconnect driver from coding suggestion. (Georgi) * Move interconnect diagram into the commit text of patch. (Georgi) * Register the interconnect provider as a platform sub-device. (Georgi) Changes in V4: * Add acked TAG on dt-bindings patches. (Rob) * Declaration of emi_icc_aggregate since the prototype of aggregate function has changed meanwhile. (Georgi) * Used emi_icc_remove instead of icc_provider_del on probe. (Georgi) * Add dvfsrc regulator driver into series. * Bug fixed of mt8183_get_current_level. * Add mutex protection for pstate operation on dvfsrc_set_performance. Changes in V3: * Remove RFC from the subject prefix of the series * Combine dt-binding patch and move interconnect dt-binding document into dvfsrc. (Rob) * Remove unused header, add unit descirption to the bandwidth, rename compatible name on interconnect driver. (Georgi) * Fixed some coding style: check flow, naming, used readx_poll_timeout on dvfsrc driver. (Ryan) * Rename interconnect driver mt8183.c to mtk-emi.c * Rename interconnect header mtk,mt8183.h to mtk,emi.h * mtk-scpsys.c: Add opp table check first to avoid OF runtime parse failed Changes in RFC V2: * Remove the DT property dram_type. (Rob) * Used generic dts property 'opp-level' to get the performace state. (Stephen) * Remove unecessary dependency config on Kconfig. (Stephen) * Remove unused header file, fixed some coding style issue, typo, error handling on dvfsrc driver. (Nicolas/Stephen) * Remove irq handler on dvfsrc driver. (Stephen) * Remove init table on dvfsrc driver, combine hw init on trustzone. * Add interconnect support of mt8183 to aggregate the emi bandwidth. (Georgi) V6: https://patchwork.kernel.org/project/linux-mediatek/list/?series=406077 V5: https://patchwork.kernel.org/project/linux-mediatek/list/?series=348065 V4: https://lore.kernel.org/patchwork/cover/1209284/ V3: https://patchwork.kernel.org/cover/8867/ RFC V2: https://lore.kernel.org/patchwork/patch/1068113/ RFC V1: https://lore.kernel.org/patchwork/cover/1028535/
[PATCH V7 06/13] arm64: dts: mt8192: add dvfsrc related nodes
Enable dvfsrc on mt8192 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 8252143..dbefc0d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -464,6 +464,12 @@
#clock-cells = <1>;
};
+ ddr_emi: dvfsrc@10012000 {
+ compatible = "mediatek,mt8192-dvfsrc",
+"mediatek,mt6873-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
--
1.9.1
Re: [PATCH V6 08/13] interconnect: mediatek: Add interconnect provider driver
On Mon, 2021-01-04 at 20:36 +0200, Georgi Djakov wrote: > On 12/24/20 08:08, Henry Chen wrote: > > Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver > > using the interconnect framework. > > > > ICC provider ICC Nodes > > > > - |CPU | |--- |VPU | > > - | |- | > > |DRAM |--|DRAM | | > > | |--|scheduler|- |GPU | |--- |DISP| > > | |--|(EMI)| | > > | |--| | - | > > - | |- |MMSYS|--|--- |VDEC| > > -- | > > /|\| > > |change DRAM freq |--- |VENC| > > -- | > > | DVFSR | | > > | | | > > -- |--- |IMG | > >| > >| > > |--- |CAM | > > > > > > Signed-off-by: Henry Chen > > --- > > drivers/interconnect/Kconfig| 1 + > > drivers/interconnect/Makefile | 1 + > > drivers/interconnect/mediatek/Kconfig | 13 ++ > > drivers/interconnect/mediatek/Makefile | 3 + > > drivers/interconnect/mediatek/mtk-emi.c | 330 > > > > 5 files changed, 348 insertions(+) > > create mode 100644 drivers/interconnect/mediatek/Kconfig > > create mode 100644 drivers/interconnect/mediatek/Makefile > > create mode 100644 drivers/interconnect/mediatek/mtk-emi.c > > > > diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig > > index 5b7204e..e939f5a 100644 > > --- a/drivers/interconnect/Kconfig > > +++ b/drivers/interconnect/Kconfig > > @@ -13,5 +13,6 @@ if INTERCONNECT > > > > source "drivers/interconnect/imx/Kconfig" > > source "drivers/interconnect/qcom/Kconfig" > > +source "drivers/interconnect/mediatek/Kconfig" > > Sort alphabetically please. Ok > > > > > endif > > diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile > > index d203520..0643a24 100644 > > --- a/drivers/interconnect/Makefile > > +++ b/drivers/interconnect/Makefile > > @@ -6,3 +6,4 @@ icc-core-objs := core.o bulk.o > > obj-$(CONFIG_INTERCONNECT)+= icc-core.o > > obj-$(CONFIG_INTERCONNECT_IMX)+= imx/ > > obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/ > > +obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/ > > Ditto. Ok > > > diff --git a/drivers/interconnect/mediatek/Kconfig > > b/drivers/interconnect/mediatek/Kconfig > > new file mode 100644 > > index 000..972d3bb > > --- /dev/null > > +++ b/drivers/interconnect/mediatek/Kconfig > > @@ -0,0 +1,13 @@ > > +config INTERCONNECT_MTK > > + bool "Mediatek Network-on-Chip interconnect drivers" > > + depends on ARCH_MEDIATEK > > + help > > + Support for Mediatek's Network-on-Chip interconnect hardware. > > + > > +config INTERCONNECT_MTK_EMI > > + tristate "Mediatek EMI interconnect driver" > > + depends on INTERCONNECT_MTK > > + depends on (MTK_DVFSRC && OF) > > Would it be possible to enable COMPILE_TEST? Do you means change to "depends on (MTK_DVFSRC && OF) || COMPILE_TEST" ? > > > + help > > + This is a driver for the Mediatek Network-on-Chip on DVFSRC-based > > + platforms. > > diff --git a/drivers/interconnect/mediatek/Makefile > > b/drivers/interconnect/mediatek/Makefile > > new file mode 100644 > > index 000..353842b > > --- /dev/null > > +++ b/drivers/interconnect/mediatek/Makefile > > @@ -0,0 +1,3 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > + > > +obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o > > \ No newline at end of file > > diff --git a/drivers/interconnect/mediatek/mtk-emi.c > > b/drivers/interconnect/mediatek/mtk-emi.c > > new file mode 100644 > > index 000..9670077 > > --- /dev/null > > +++ b/drivers/interconnect/mediatek/mtk-emi.c > > @@ -0,0 +1,330 @@ > > +// SPDX-
Re: [PATCH V6 03/13] soc: mediatek: add driver for dvfsrc support
On Thu, 2020-12-24 at 22:33 +0800, Chun-Kuang Hu wrote: Hi CK, > Hi, Henry: > > Henry Chen 於 2020年12月24日 週四 下午2:09寫道： > > > > Add dvfsrc driver for MT6873/MT8183/MT8192 > > Separate this patch for each SoC. OK, thanks. Henry > > Regards, > Chun-Kuang. > > > > > Signed-off-by: Henry Chen > > --- > > drivers/soc/mediatek/Kconfig| 12 + > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mtk-dvfsrc.c | 538 > > > > include/linux/soc/mediatek/mtk_dvfsrc.h | 35 +++ > > 4 files changed, 586 insertions(+) > > create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c > > create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h > >
Re: [PATCH V6 01/13] dt-bindings: soc: Add dvfsrc driver bindings
On Thu, 2020-12-24 at 10:01 -0700, Rob Herring wrote: > On Thu, 24 Dec 2020 14:08:42 +0800, Henry Chen wrote: > > Document the binding for enabling dvfsrc on MediaTek SoC. > > > > Signed-off-by: Henry Chen > > --- > > .../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 68 > > ++ > > 1 file changed, 68 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.example.dts:19:18: > fatal error: dt-bindings/soc/mtk,dvfsrc.h: No such file or directory >19 | #include > | ^~ > compilation terminated. > make[1]: *** [scripts/Makefile.lib:342: > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.example.dt.yaml] Error 1 > make: *** [Makefile:1370: dt_binding_check] Error 2 > > See https://patchwork.ozlabs.org/patch/1420382 > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. > Hi Rob, Sorry for the check error, I will re-check and submit again. Thanks, Henry
[PATCH V6 00/13] Add driver for dvfsrc, support for active state of scpsys
This series is based on v5.10-rc1. The patchsets add support for MediaTek hardware module named DVFSRC (dynamic voltage and frequency scaling resource collector). The DVFSRC is a HW module which is used to collect all the requests from both software and hardware and turn into the decision of minimum operating voltage and minimum DRAM frequency to fulfill those requests. So, This series is to implement the dvfsrc driver to collect all the requests of operating voltage or DRAM bandwidth from other device drivers likes GPU/Camera through 3 frameworks basically: 1. interconnect framework: to aggregate the bandwidth requirements from different clients [1] https://patchwork.kernel.org/cover/10766329/ There has a hw module "DRAM scheduler", which used to control the throughput. The DVFSRC will collect forecast data of dram bandwidth from SW consumers(camera/gpu...), and according the forecast to change the DRAM frequency 2. Regualtor framework: to handle the operating voltage requirement from user or cosumer which not belong any power domain Changes in V6: * Remove the performace state support, because the request from consumer can be replaced by using interconnect and regulator framework. * Update the DT patches and convert them to DT schema. (Georgi) * Modify the comment format and coding style. (Mark) Changes in V5: * Support more platform mt6873/mt8192 * Drop the compatible and interconnect provider node and make the parent node an interconnect provider. (Rob/Georgi) * Make modification of interconnect driver from coding suggestion. (Georgi) * Move interconnect diagram into the commit text of patch. (Georgi) * Register the interconnect provider as a platform sub-device. (Georgi) Changes in V4: * Add acked TAG on dt-bindings patches. (Rob) * Declaration of emi_icc_aggregate since the prototype of aggregate function has changed meanwhile. (Georgi) * Used emi_icc_remove instead of icc_provider_del on probe. (Georgi) * Add dvfsrc regulator driver into series. * Bug fixed of mt8183_get_current_level. * Add mutex protection for pstate operation on dvfsrc_set_performance. Changes in V3: * Remove RFC from the subject prefix of the series * Combine dt-binding patch and move interconnect dt-binding document into dvfsrc. (Rob) * Remove unused header, add unit descirption to the bandwidth, rename compatible name on interconnect driver. (Georgi) * Fixed some coding style: check flow, naming, used readx_poll_timeout on dvfsrc driver. (Ryan) * Rename interconnect driver mt8183.c to mtk-emi.c * Rename interconnect header mtk,mt8183.h to mtk,emi.h * mtk-scpsys.c: Add opp table check first to avoid OF runtime parse failed Changes in RFC V2: * Remove the DT property dram_type. (Rob) * Used generic dts property 'opp-level' to get the performace state. (Stephen) * Remove unecessary dependency config on Kconfig. (Stephen) * Remove unused header file, fixed some coding style issue, typo, error handling on dvfsrc driver. (Nicolas/Stephen) * Remove irq handler on dvfsrc driver. (Stephen) * Remove init table on dvfsrc driver, combine hw init on trustzone. * Add interconnect support of mt8183 to aggregate the emi bandwidth. (Georgi) V5: https://patchwork.kernel.org/project/linux-mediatek/list/?series=348065 V4: https://lore.kernel.org/patchwork/cover/1209284/ V3: https://patchwork.kernel.org/cover/8867/ RFC V2: https://lore.kernel.org/patchwork/patch/1068113/ RFC V1: https://lore.kernel.org/patchwork/cover/1028535/
[PATCH V6 04/13] arm64: dts: mt8183: add dvfsrc related nodes
Enable dvfsrc on mt8183 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 9cfd961..06ef8e0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -328,6 +328,11 @@
#clock-cells = <1>;
};
+ ddr_emi: dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ };
+
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8183-pwrap";
reg = <0 0x1000d000 0 0x1000>;
--
1.9.1
[PATCH V6 12/13] arm64: dts: mt8183: add dvfsrc regulator nodes
Add dvfsrc regulator nodes which is for MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 22b3a68..182b851 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -333,6 +333,12 @@
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
#interconnect-cells = <1>;
+ dvfsrc_vcore: dvfsrc-vcore {
+ regulator-name = "dvfsrc-vcore";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <80>;
+ regulator-always-on;
+ };
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V6 10/13] arm64: dts: mt8192: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8192-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 1e5d506..14c521d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
/ {
compatible = "mediatek,mt8192";
@@ -266,6 +267,7 @@
ddr_emi: dvfsrc@10012000 {
compatible = "mediatek,mt8192-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
systimer: timer@10017000 {
--
1.9.1
[PATCH V6 08/13] interconnect: mediatek: Add interconnect provider driver
Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver
using the interconnect framework.
ICC provider ICC Nodes
- |CPU | |--- |VPU |
- | |- |
|DRAM |--|DRAM | |
| |--|scheduler|- |GPU | |--- |DISP|
| |--|(EMI)| |
| |--| | - |
- | |- |MMSYS|--|--- |VDEC|
-- |
/|\|
|change DRAM freq |--- |VENC|
-- |
| DVFSR | |
| | |
-- |--- |IMG |
|
|
|--- |CAM |
Signed-off-by: Henry Chen
---
drivers/interconnect/Kconfig| 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 13 ++
drivers/interconnect/mediatek/Makefile | 3 +
drivers/interconnect/mediatek/mtk-emi.c | 330
5 files changed, 348 insertions(+)
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/mtk-emi.c
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
index 5b7204e..e939f5a 100644
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@@ -13,5 +13,6 @@ if INTERCONNECT
source "drivers/interconnect/imx/Kconfig"
source "drivers/interconnect/qcom/Kconfig"
+source "drivers/interconnect/mediatek/Kconfig"
endif
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
index d203520..0643a24 100644
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@@ -6,3 +6,4 @@ icc-core-objs := core.o bulk.o
obj-$(CONFIG_INTERCONNECT) += icc-core.o
obj-$(CONFIG_INTERCONNECT_IMX) += imx/
obj-$(CONFIG_INTERCONNECT_QCOM)+= qcom/
+obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/
diff --git a/drivers/interconnect/mediatek/Kconfig
b/drivers/interconnect/mediatek/Kconfig
new file mode 100644
index 000..972d3bb
--- /dev/null
+++ b/drivers/interconnect/mediatek/Kconfig
@@ -0,0 +1,13 @@
+config INTERCONNECT_MTK
+ bool "Mediatek Network-on-Chip interconnect drivers"
+ depends on ARCH_MEDIATEK
+ help
+ Support for Mediatek's Network-on-Chip interconnect hardware.
+
+config INTERCONNECT_MTK_EMI
+ tristate "Mediatek EMI interconnect driver"
+ depends on INTERCONNECT_MTK
+ depends on (MTK_DVFSRC && OF)
+ help
+ This is a driver for the Mediatek Network-on-Chip on DVFSRC-based
+ platforms.
diff --git a/drivers/interconnect/mediatek/Makefile
b/drivers/interconnect/mediatek/Makefile
new file mode 100644
index 000..353842b
--- /dev/null
+++ b/drivers/interconnect/mediatek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o
\ No newline at end of file
diff --git a/drivers/interconnect/mediatek/mtk-emi.c
b/drivers/interconnect/mediatek/mtk-emi.c
new file mode 100644
index 000..9670077
--- /dev/null
+++ b/drivers/interconnect/mediatek/mtk-emi.c
@@ -0,0 +1,330 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum mtk_icc_name {
+ SLAVE_DDR_EMI,
+ MASTER_MCUSYS,
+ MASTER_GPUSYS,
+ MASTER_MMSYS,
+ MASTER_MM_VPU,
+ MASTER_MM_DISP,
+ MASTER_MM_VDEC,
+ MASTER_MM_VENC,
+ MASTER_MM_CAM,
+ MASTER_MM_IMG,
+ MASTER_MM_MDP,
+ MASTER_VPUSYS,
+ MASTER_VPU_PORT_0,
+ MASTER_VPU_PORT_1,
+ MASTER_MDLASYS,
+ MASTER_MDLA_PORT_0,
+ MASTER_UFS,
+ MASTER_PCIE,
+ MASTER_USB,
+ MASTER_WIFI,
+ MASTER_BT,
+ MASTER_NETSYS,
+ MASTER_DBGIF,
+
+ SLAVE_HRT_DDR_EMI,
+ MASTER_HRT_MMSYS,
+ MASTER_HRT_MM_DISP,
+ MASTER_HRT_MM_VDEC,
+ MASTER_HRT_MM_VENC,
+ MASTER_HRT_MM_CAM,
+ MASTER_HRT_MM_IMG,
+ MASTER_HRT_MM_MDP,
+ MASTER_HRT_DBGIF,
+};
+
+#define MT8183_MAX_LINKS 1
+
+/**
+ * struct mtk_icc_node - Mediatek specific interconnect nodes
+ * @name: the node name used in debugfs
+ * @ep : the type of this endpoint
+ * @id: a unique node identifier
+ * @links: an array of nodes where we can go next while traversing
+ * @n
[PATCH V6 03/13] soc: mediatek: add driver for dvfsrc support
Add dvfsrc driver for MT6873/MT8183/MT8192
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/Kconfig| 12 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 538
include/linux/soc/mediatek/mtk_dvfsrc.h | 35 +++
4 files changed, 586 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 59a56cd..0150a6b 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -17,6 +17,18 @@ config MTK_CMDQ
time limitation, such as updating display configuration during the
vblank.
+config MTK_DVFSRC
+ tristate "MediaTek DVFSRC Support"
+ depends on ARCH_MEDIATEK
+ depends on MTK_SCPSYS
+ help
+ Say yes here to add support for the MediaTek DVFSRC (dynamic voltage
+ and frequency scaling resource collector) found
+ on different MediaTek SoCs. The DVFSRC is a proprietary
+ hardware which is used to collect all the requests from
+ system and turn into the decision of minimum Vcore voltage
+ and minimum DRAM frequency to fulfill those requests.
+
config MTK_INFRACFG
bool "MediaTek INFRACFG Support"
select REGMAP
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 01f9f87..d55b473 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
+obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
new file mode 100644
index 000..536ced7
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -0,0 +1,538 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DVFSRC_IDLE 0x00
+#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
+#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x)
+#define kbps_to_mbps(x) ((x) / 1000)
+
+#define POLL_TIMEOUT1000
+#define STARTUP_TIME1
+
+#define MTK_SIP_DVFSRC_INIT0x00
+
+#define DVFSRC_OPP_DESC(_opp_table)\
+{ \
+ .opps = _opp_table, \
+ .num_opp = ARRAY_SIZE(_opp_table), \
+}
+
+struct dvfsrc_opp {
+ u32 vcore_opp;
+ u32 dram_opp;
+};
+
+struct dvfsrc_opp_desc {
+ const struct dvfsrc_opp *opps;
+ u32 num_opp;
+};
+
+struct mtk_dvfsrc;
+struct dvfsrc_soc_data {
+ const int *regs;
+ const struct dvfsrc_opp_desc *opps_desc;
+ int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
+ int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc);
+ void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+};
+
+struct mtk_dvfsrc {
+ struct device *dev;
+ struct platform_device *icc;
+ struct platform_device *regulator;
+ const struct dvfsrc_soc_data *dvd;
+ int dram_type;
+ const struct dvfsrc_opp_desc *curr_opps;
+ void __iomem *regs;
+ spinlock_t req_lock;
+ struct mutex pstate_lock;
+ struct notifier_block scpsys_notifier;
+};
+
+static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
+{
+ return readl(dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
+{
+ writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \
+ dvfsrc_write(dvfs, offset, \
+ (dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val << shift))
+
+enum dvfsrc_regs {
+ DVFSRC_SW_REQ,
+ DVFSRC_SW_REQ2,
+ DVFSRC_LEVEL,
+ DVFSRC_TARGET_LEVEL,
+ DVFSRC_SW_BW,
+ DVFSRC_SW_PEAK_BW,
+ DVFSRC_SW_HRT_BW,
+ DVFSRC_VCORE_REQUEST,
+};
+
+static const int mt8183_regs[] = {
+ [DVFSRC_SW_REQ] = 0x4,
+ [DVFSRC_SW_REQ
[PATCH V6 01/13] dt-bindings: soc: Add dvfsrc driver bindings
Document the binding for enabling dvfsrc on MediaTek SoC.
Signed-off-by: Henry Chen
---
.../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 68 ++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
new file mode 100644
index 000..60e0b7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/mediatek/dvfsrc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: MediaTek dynamic voltage and frequency scaling resource collector
(DVFSRC)
+
+description: |
+ The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
+ HW module which is used to collect all the requests from both software and
+ hardware and turn into the decision of minimum operating voltage and minimum
+ DRAM frequency to fulfill those requests.
+
+maintainers:
+ - henryc.chen
+
+properties:
+ reg:
+description: DVFSRC common register address and length.
+
+ compatible:
+enum:
+ - mediatek,mt6873-dvfsrc
+ - mediatek,mt8183-dvfsrc
+ - mediatek,mt8192-dvfsrc
+
+ '#interconnect-cells':
+const: 1
+
+patternProperties:
+ dvfsrc-vcore:
+type: object
+description:
+ The DVFSRC regulator is modelled as a subdevice of the DVFSRC.
+ Because DVFSRC can request power directly via register read/write, likes
+ vcore which is a core power of mt8183. As such, the DVFSRC regulator
+ requires that DVFSRC nodes be present.
+$ref: /schemas/regulator/regulator.yaml#
+
+required:
+ - compatible
+ - reg
+ - "#interconnect-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+dvfsrc@10012000 {
+compatible = "mediatek,mt8183-dvfsrc";
+reg = <0 0x10012000 0 0x1000>;
+#interconnect-cells = <1>;
+dvfsrc_vcore: dvfsrc-vcore {
+regulator-name = "dvfsrc-vcore";
+regulator-min-microvolt = <725000>;
+regulator-max-microvolt = <80>;
+regulator-always-on;
+};
+};
+};
--
1.9.1
[PATCH V6 06/13] dt-bindings: interconnect: add MT8183 interconnect dt-bindings
Add interconnect provider dt-bindings for MT8183. Signed-off-by: Henry Chen --- include/dt-bindings/interconnect/mtk,mt8183-emi.h | 21 + 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h new file mode 100644 index 000..f921961 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H + +#define MT8183_SLAVE_DDR_EMI 0 +#define MT8183_MASTER_MCUSYS 1 +#define MT8183_MASTER_GPU 2 +#define MT8183_MASTER_MMSYS3 +#define MT8183_MASTER_MM_VPU 4 +#define MT8183_MASTER_MM_DISP 5 +#define MT8183_MASTER_MM_VDEC 6 +#define MT8183_MASTER_MM_VENC 7 +#define MT8183_MASTER_MM_CAM 8 +#define MT8183_MASTER_MM_IMG 9 +#define MT8183_MASTER_MM_MDP 10 + +#endif -- 1.9.1
[PATCH V6 09/13] arm64: dts: mt8183: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 06ef8e0..22b3a68 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -11,6 +11,7 @@
#include
#include
#include "mt8183-pinfunc.h"
+#include
/ {
compatible = "mediatek,mt8183";
@@ -331,6 +332,7 @@
ddr_emi: dvfsrc@10012000 {
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V6 02/13] soc: mediatek: add header for mediatek SIP interface
From: Arvin Wang Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Arvin Wang --- include/linux/soc/mediatek/mtk_sip_svc.h | 4 1 file changed, 4 insertions(+) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h index 082398e..079bbcb 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,4 +22,8 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) +/* VCOREFS */ +#define MTK_SIP_VCOREFS_CONTROL \ + MTK_SIP_SMC_CMD(0x506) + #endif -- 1.9.1
[PATCH V5 01/17] dt-bindings: soc: Add dvfsrc driver bindings
Document the binding for enabling dvfsrc on MediaTek SoC.
Signed-off-by: Henry Chen
Reviewed-by: Rob Herring
---
.../devicetree/bindings/soc/mediatek/dvfsrc.txt| 25 ++
include/dt-bindings/soc/mtk,dvfsrc.h | 14
2 files changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
new file mode 100644
index 000..d5a47d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
@@ -0,0 +1,25 @@
+MediaTek DVFSRC
+
+The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
+HW module which is used to collect all the requests from both software and
+hardware and turn into the decision of minimum operating voltage and minimum
+DRAM frequency to fulfill those requests.
+
+Required Properties:
+- compatible: Should be one of the following
+ - "mediatek,mt6873-dvfsrc": For MT6873 SoC
+ - "mediatek,mt8183-dvfsrc": For MT8183 SoC
+ - "mediatek,mt8192-dvfsrc": For MT8192 SoC
+- reg: Address range of the DVFSRC unit
+- clock-names: Must include the following entries:
+ "dvfsrc": DVFSRC module clock
+- clocks: Must contain an entry for each entry in clock-names.
+
+Example:
+
+ dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ clocks = < CLK_INFRA_DVFSRC>;
+ clock-names = "dvfsrc";
+ };
diff --git a/include/dt-bindings/soc/mtk,dvfsrc.h
b/include/dt-bindings/soc/mtk,dvfsrc.h
new file mode 100644
index 000..a522488
--- /dev/null
+++ b/include/dt-bindings/soc/mtk,dvfsrc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MTK_DVFSRC_H
+#define _DT_BINDINGS_POWER_MTK_DVFSRC_H
+
+#define MT8183_DVFSRC_LEVEL_1 1
+#define MT8183_DVFSRC_LEVEL_2 2
+#define MT8183_DVFSRC_LEVEL_3 3
+#define MT8183_DVFSRC_LEVEL_4 4
+
+#endif /* _DT_BINDINGS_POWER_MTK_DVFSRC_H */
--
1.9.1
[PATCH V5 05/17] soc: mediatek: add header for mediatek SIP interface
From: Arvin Wang Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Arvin Wang --- include/linux/soc/mediatek/mtk_sip_svc.h | 4 1 file changed, 4 insertions(+) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h index 082398e..079bbcb 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,4 +22,8 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) +/* VCOREFS */ +#define MTK_SIP_VCOREFS_CONTROL \ + MTK_SIP_SMC_CMD(0x506) + #endif -- 1.9.1
[PATCH V5 13/17] arm64: dts: mt8192: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 1eae441..647c57a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
/ {
compatible = "mediatek,mt8192";
@@ -420,6 +421,7 @@
ddr_emi: dvfsrc@10012000 {
compatible = "mediatek,mt8192-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
systimer: timer@10017000 {
--
1.9.1
[PATCH V5 02/17] dt-bindings: soc: Add opp table on scpsys bindings
Add opp table on scpsys dt-bindings for Mediatek SoC.
Signed-off-by: Henry Chen
Reviewed-by: Rob Herring
---
.../devicetree/bindings/soc/mediatek/scpsys.txt| 38 ++
1 file changed, 38 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 7f322f9..4b96fdc 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -90,6 +90,27 @@ Example:
< CLK_TOP_VENC_SEL>,
< CLK_TOP_VENC_LT_SEL>;
clock-names = "mfg", "mm", "venc", "venc_lt";
+ operating-points-v2 = <_opp_table>;
+
+ dvfsrc_opp_table: opp-table {
+ compatible = "operating-points-v2-level";
+
+ dvfsrc_vol_min: opp1 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_medium: opp2 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_max: opp3 {
+ opp,level = ;
+ };
+
+ dvfsrc_vol_max: opp4 {
+ opp,level = ;
+ };
+ };
};
Example(power domain sub node within power controller):
@@ -151,4 +172,21 @@ Example consumer:
afe: mt8173-afe-pcm@1122 {
compatible = "mediatek,mt8173-afe-pcm";
power-domains = < MT8173_POWER_DOMAIN_AUDIO>;
+ operating-points-v2 = <_opp_table>;
+ };
+
+ aud_opp_table: aud-opp-table {
+ compatible = "operating-points-v2";
+ opp1 {
+ opp-hz = /bits/ 64 <79300>;
+ required-opps = <_vol_min>;
+ };
+ opp2 {
+ opp-hz = /bits/ 64 <91000>;
+ required-opps = <_vol_max>;
+ };
+ opp3 {
+ opp-hz = /bits/ 64 <101400>;
+ required-opps = <_vol_max>;
+ };
};
--
1.9.1
[PATCH V5 11/17] interconnect: mediatek: Add interconnect provider driver
Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver
using the interconnect framework.
ICC provider ICC Nodes
- |CPU | |--- |VPU |
- | |- |
|DRAM |--|DRAM | |
| |--|scheduler|- |GPU | |--- |DISP|
| |--|(EMI)| |
| |--| | - |
- | |- |MMSYS|--|--- |VDEC|
-- |
/|\|
|change DRAM freq |--- |VENC|
-- |
| DVFSR | |
| | |
-- |--- |IMG |
|
|
|--- |CAM |
Signed-off-by: Henry Chen
---
drivers/interconnect/Kconfig| 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 13 ++
drivers/interconnect/mediatek/Makefile | 3 +
drivers/interconnect/mediatek/mtk-emi.c | 330
5 files changed, 348 insertions(+)
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/mtk-emi.c
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
index 5b7204e..e939f5a 100644
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@@ -13,5 +13,6 @@ if INTERCONNECT
source "drivers/interconnect/imx/Kconfig"
source "drivers/interconnect/qcom/Kconfig"
+source "drivers/interconnect/mediatek/Kconfig"
endif
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
index 4825c28..6f4b88a 100644
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@@ -6,3 +6,4 @@ icc-core-objs := core.o
obj-$(CONFIG_INTERCONNECT) += icc-core.o
obj-$(CONFIG_INTERCONNECT_IMX) += imx/
obj-$(CONFIG_INTERCONNECT_QCOM)+= qcom/
+obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/
diff --git a/drivers/interconnect/mediatek/Kconfig
b/drivers/interconnect/mediatek/Kconfig
new file mode 100644
index 000..972d3bb
--- /dev/null
+++ b/drivers/interconnect/mediatek/Kconfig
@@ -0,0 +1,13 @@
+config INTERCONNECT_MTK
+ bool "Mediatek Network-on-Chip interconnect drivers"
+ depends on ARCH_MEDIATEK
+ help
+ Support for Mediatek's Network-on-Chip interconnect hardware.
+
+config INTERCONNECT_MTK_EMI
+ tristate "Mediatek EMI interconnect driver"
+ depends on INTERCONNECT_MTK
+ depends on (MTK_DVFSRC && OF)
+ help
+ This is a driver for the Mediatek Network-on-Chip on DVFSRC-based
+ platforms.
diff --git a/drivers/interconnect/mediatek/Makefile
b/drivers/interconnect/mediatek/Makefile
new file mode 100644
index 000..353842b
--- /dev/null
+++ b/drivers/interconnect/mediatek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o
\ No newline at end of file
diff --git a/drivers/interconnect/mediatek/mtk-emi.c
b/drivers/interconnect/mediatek/mtk-emi.c
new file mode 100644
index 000..9670077
--- /dev/null
+++ b/drivers/interconnect/mediatek/mtk-emi.c
@@ -0,0 +1,330 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum mtk_icc_name {
+ SLAVE_DDR_EMI,
+ MASTER_MCUSYS,
+ MASTER_GPUSYS,
+ MASTER_MMSYS,
+ MASTER_MM_VPU,
+ MASTER_MM_DISP,
+ MASTER_MM_VDEC,
+ MASTER_MM_VENC,
+ MASTER_MM_CAM,
+ MASTER_MM_IMG,
+ MASTER_MM_MDP,
+ MASTER_VPUSYS,
+ MASTER_VPU_PORT_0,
+ MASTER_VPU_PORT_1,
+ MASTER_MDLASYS,
+ MASTER_MDLA_PORT_0,
+ MASTER_UFS,
+ MASTER_PCIE,
+ MASTER_USB,
+ MASTER_WIFI,
+ MASTER_BT,
+ MASTER_NETSYS,
+ MASTER_DBGIF,
+
+ SLAVE_HRT_DDR_EMI,
+ MASTER_HRT_MMSYS,
+ MASTER_HRT_MM_DISP,
+ MASTER_HRT_MM_VDEC,
+ MASTER_HRT_MM_VENC,
+ MASTER_HRT_MM_CAM,
+ MASTER_HRT_MM_IMG,
+ MASTER_HRT_MM_MDP,
+ MASTER_HRT_DBGIF,
+};
+
+#define MT8183_MAX_LINKS 1
+
+/**
+ * struct mtk_icc_node - Mediatek specific interconnect nodes
+ * @name: the node name used in debugfs
+ * @ep : the type of this endpoint
+ * @id: a unique node identifier
+ * @links: an array of nodes where we can go next while traversing
+ * @num_l
[PATCH V5 04/17] arm64: dts: mt8183: add performance state support of scpsys
Add support for performance state of scpsys on mt8183 platform
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index d85bae7..82ca929 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -12,6 +12,7 @@
#include
#include
#include "mt8183-pinfunc.h"
+#include
/ {
compatible = "mediatek,mt8183";
@@ -340,6 +341,27 @@
#address-cells = <1>;
#size-cells = <0>;
+ operating-points-v2 = <_opp_table>;
+ dvfsrc_opp_table: opp-table {
+ compatible = "operating-points-v2-level";
+
+ dvfsrc_vol_min: opp1 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_medium: opp2 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_max: opp3 {
+ opp,level = ;
+ };
+
+ dvfsrc_vol_max: opp4 {
+ opp,level = ;
+ };
+ };
+
audio@MT8183_POWER_DOMAIN_AUDIO {
reg = ;
};
--
1.9.1
[PATCH V5 12/17] arm64: dts: mt8183: add dvfsrc related nodes
Add DDR EMI provider dictating dram interconnect bus performance found on
MT8192-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 4046603..63a4decd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -13,6 +13,7 @@
#include
#include "mt8183-pinfunc.h"
#include
+#include
/ {
compatible = "mediatek,mt8183";
@@ -472,6 +473,7 @@
ddr_emi: dvfsrc@10012000 {
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ #interconnect-cells = <1>;
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V5 06/17] soc: mediatek: add driver for dvfsrc support
Add dvfsrc driver for MT6873/MT8183/MT8192
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/Kconfig| 12 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 618
include/linux/soc/mediatek/mtk_dvfsrc.h | 34 ++
4 files changed, 665 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 3f5e5cb..ac78c47 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -16,6 +16,18 @@ config MTK_CMDQ
time limitation, such as updating display configuration during the
vblank.
+config MTK_DVFSRC
+ tristate "MediaTek DVFSRC Support"
+ depends on ARCH_MEDIATEK
+ depends on MTK_SCPSYS
+ help
+ Say yes here to add support for the MediaTek DVFSRC (dynamic voltage
+ and frequency scaling resource collector) found
+ on different MediaTek SoCs. The DVFSRC is a proprietary
+ hardware which is used to collect all the requests from
+ system and turn into the decision of minimum Vcore voltage
+ and minimum DRAM frequency to fulfill those requests.
+
config MTK_PMIC_WRAP
tristate "MediaTek PMIC Wrapper Support"
depends on RESET_CONTROLLER
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 2afa7b9..65e9597 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
+obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
new file mode 100644
index 000..c539677
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -0,0 +1,618 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mtk-scpsys.h"
+
+#define DVFSRC_IDLE 0x00
+#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
+#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x)
+#define kbps_to_mbps(x) ((x) / 1000)
+
+#define MT8183_DVFSRC_OPP_LP4 0
+#define MT8183_DVFSRC_OPP_LP4X 1
+#define MT8183_DVFSRC_OPP_LP3 2
+
+#define POLL_TIMEOUT1000
+#define STARTUP_TIME1
+
+#define MTK_SIP_DVFSRC_INIT0x00
+
+#define DVFSRC_OPP_DESC(_opp_table)\
+{ \
+ .opps = _opp_table, \
+ .num_opp = ARRAY_SIZE(_opp_table), \
+}
+
+struct dvfsrc_opp {
+ u32 vcore_opp;
+ u32 dram_opp;
+};
+
+struct dvfsrc_domain {
+ u32 id;
+ u32 state;
+};
+
+struct dvfsrc_opp_desc {
+ const struct dvfsrc_opp *opps;
+ u32 num_opp;
+};
+
+struct mtk_dvfsrc;
+struct dvfsrc_soc_data {
+ const int *regs;
+ u32 num_domains;
+ struct dvfsrc_domain *domains;
+ const struct dvfsrc_opp_desc *opps_desc;
+ int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
+ int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
+ u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc);
+ void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+};
+
+struct mtk_dvfsrc {
+ struct device *dev;
+ struct platform_device *icc;
+ struct platform_device *regulator;
+ const struct dvfsrc_soc_data *dvd;
+ int dram_type;
+ const struct dvfsrc_opp_desc *curr_opps;
+ void __iomem *regs;
+ spinlock_t req_lock;
+ struct mutex pstate_lock;
+ struct notifier_block scpsys_notifier;
+};
+
+static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
+{
+ return readl(dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
+{
+ writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \
+ dvfsrc_write(dvfs, offset, \
+ (dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val << shift))
+
+en
[PATCH V5 03/17] soc: mediatek: add support for the performance state
Support power domain performance state, add header file for scp event.
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/mtk-scpsys.c | 58 +++
drivers/soc/mediatek/mtk-scpsys.h | 22 +++
2 files changed, 80 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-scpsys.h
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index 19a0c7e..ad0ca52 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,8 +11,10 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
#include
@@ -22,6 +24,7 @@
#include
#include
#include
+#include "mtk-scpsys.h"
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUTUSEC_PER_SEC
@@ -272,6 +275,18 @@ struct scp_soc_data {
const struct scp_ctrl_reg regs;
};
+static BLOCKING_NOTIFIER_HEAD(scpsys_notifier_list);
+
+int register_scpsys_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(_notifier_list, nb);
+}
+
+int unregister_scpsys_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(_notifier_list, nb);
+}
+
static int scpsys_domain_is_on(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
@@ -294,6 +309,41 @@ static int scpsys_domain_is_on(struct scp_domain *scpd)
return -EINVAL;
}
+static int mtk_pd_set_performance(struct generic_pm_domain *genpd,
+ unsigned int state)
+{
+ int i;
+ struct scp_domain *scpd =
+ container_of(genpd, struct scp_domain, genpd);
+ struct scp_event_data scpe;
+ struct scp *scp = scpd->scp;
+ struct genpd_onecell_data *pd_data = >pd_data;
+
+ for (i = 0; i < pd_data->num_domains; i++) {
+ if (genpd == pd_data->domains[i]) {
+ dev_dbg(scp->dev, "%d. %s = %d\n",
+ i, genpd->name, state);
+ break;
+ }
+ }
+
+ if (i == pd_data->num_domains)
+ return 0;
+
+ scpe.event_type = MTK_SCPSYS_PSTATE;
+ scpe.genpd = genpd;
+ scpe.domain_id = i;
+ blocking_notifier_call_chain(_notifier_list, state, );
+
+ return 0;
+}
+
+static unsigned int mtk_pd_get_performance(struct generic_pm_domain *genpd,
+ struct dev_pm_opp *opp)
+{
+ return dev_pm_opp_get_level(opp);
+}
+
static int scpsys_regulator_enable(struct scp_domain *scpd)
{
if (!scpd->supply)
@@ -800,6 +850,14 @@ static struct scp *init_scp(struct platform_device *pdev,
genpd->power_on = scpsys_power_on;
if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ACTIVE_WAKEUP))
genpd->flags |= GENPD_FLAG_ACTIVE_WAKEUP;
+
+ /* Add opp table check first to avoid OF runtime parse failed */
+ if (of_count_phandle_with_args(pdev->dev.of_node,
+ "operating-points-v2", NULL) > 0) {
+ genpd->set_performance_state = mtk_pd_set_performance;
+ genpd->opp_to_performance_state =
+ mtk_pd_get_performance;
+ }
}
return scp;
diff --git a/drivers/soc/mediatek/mtk-scpsys.h
b/drivers/soc/mediatek/mtk-scpsys.h
new file mode 100644
index 000..c1e8325
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ */
+
+#ifndef __MTK_SCPSYS_H__
+#define __MTK_SCPSYS_H__
+
+struct scp_event_data {
+ int event_type;
+ int domain_id;
+ struct generic_pm_domain *genpd;
+};
+
+enum scp_event_type {
+ MTK_SCPSYS_PSTATE,
+};
+
+int register_scpsys_notifier(struct notifier_block *nb);
+int unregister_scpsys_notifier(struct notifier_block *nb);
+
+#endif /* __MTK_SCPSYS_H__ */
--
1.9.1
[PATCH V5 07/17] arm64: dts: mt8183: add dvfsrc related nodes
Enable dvfsrc on mt8183 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 82ca929..4046603 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -469,6 +469,11 @@
#clock-cells = <1>;
};
+ ddr_emi: dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ };
+
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8183-pwrap";
reg = <0 0x1000d000 0 0x1000>;
--
1.9.1
[PATCH V5 16/17] arm64: dts: mt8183: add dvfsrc regulator nodes
Add dvfsrc regulator nodes which is for MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 63a4decd..26ca0b3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -474,6 +474,12 @@
compatible = "mediatek,mt8183-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
#interconnect-cells = <1>;
+ dvfsrc_vcore: dvfsrc-vcore {
+ regulator-name = "dvfsrc-vcore";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <80>;
+ regulator-always-on;
+ };
};
pwrap: pwrap@1000d000 {
--
1.9.1
[PATCH V5 09/17] dt-bindings: interconnect: add MT8183 interconnect dt-bindings
Add interconnect provider dt-bindings for MT8183. Signed-off-by: Henry Chen --- .../devicetree/bindings/soc/mediatek/dvfsrc.txt| 2 ++ include/dt-bindings/interconnect/mtk,mt8183-emi.h | 18 ++ 2 files changed, 20 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt index d5a47d8..76ca61d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt @@ -14,6 +14,7 @@ Required Properties: - clock-names: Must include the following entries: "dvfsrc": DVFSRC module clock - clocks: Must contain an entry for each entry in clock-names. +- #interconnect-cells : should contain 1 Example: @@ -22,4 +23,5 @@ Example: reg = <0 0x10012000 0 0x1000>; clocks = < CLK_INFRA_DVFSRC>; clock-names = "dvfsrc"; + #interconnect-cells = <1>; }; diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h new file mode 100644 index 000..2a54856 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H + +#define MT8183_SLAVE_DDR_EMI 0 +#define MT8183_MASTER_MCUSYS 1 +#define MT8183_MASTER_GPU 2 +#define MT8183_MASTER_MMSYS3 +#define MT8183_MASTER_MM_VPU 4 +#define MT8183_MASTER_MM_DISP 5 +#define MT8183_MASTER_MM_VDEC 6 +#define MT8183_MASTER_MM_VENC 7 +#define MT8183_MASTER_MM_CAM 8 +#define MT8183_MASTER_MM_IMG 9 +#define MT8183_MASTER_MM_MDP 10 + +#endif -- 1.9.1
[PATCH V5 00/17] Add driver for dvfsrc, support for active state of scpsys
This series is based on v5.9-rc1 and have dependency patches as following, [v17,00/12] Mediatek MT8183 scpsys support https://patchwork.kernel.org/cover/11703253/ [0/3] Mediatek MT8192 scpsys support https://patchwork.kernel.org/cover/11755897/ The patchsets add support for MediaTek hardware module named DVFSRC (dynamic voltage and frequency scaling resource collector). The DVFSRC is a HW module which is used to collect all the requests from both software and hardware and turn into the decision of minimum operating voltage and minimum DRAM frequency to fulfill those requests. So, This series is to implement the dvfsrc driver to collect all the requests of operating voltage or DRAM bandwidth from other device drivers likes GPU/Camera through 3 frameworks basically: 1. interconnect framework: to aggregate the bandwidth requirements from different clients [1] https://patchwork.kernel.org/cover/10766329/ There has a hw module "DRAM scheduler", which used to control the throughput. The DVFSRC will collect forecast data of dram bandwidth from SW consumers(camera/gpu...), and according the forecast to change the DRAM frequency 2. Active state management of power domains[1]: to handle the operating voltage/dram opp requirement from different power domains [2] https://lwn.net/Articles/744047/ 3. Regualtor framework: to handle the operating voltage requirement from user or cosumer which not belong any power domain Changes in V5: * Support more platform mt6873/mt8192 * Drop the compatible and interconnect provider node and make the parent node an interconnect provider. (Rob/Georgi) * Make modification of interconnect driver from coding suggestion. (Georgi) * Move interconnect diagram into the commit text of patch. (Georgi) * Register the interconnect provider as a platform sub-device. (Georgi) Changes in V4: * Add acked TAG on dt-bindings patches. (Rob) * Declaration of emi_icc_aggregate since the prototype of aggregate function has changed meanwhile. (Georgi) * Used emi_icc_remove instead of icc_provider_del on probe. (Georgi) * Add dvfsrc regulator driver into series. * Bug fixed of mt8183_get_current_level. * Add mutex protection for pstate operation on dvfsrc_set_performance. Changes in V3: * Remove RFC from the subject prefix of the series * Combine dt-binding patch and move interconnect dt-binding document into dvfsrc. (Rob) * Remove unused header, add unit descirption to the bandwidth, rename compatible name on interconnect driver. (Georgi) * Fixed some coding style: check flow, naming, used readx_poll_timeout on dvfsrc driver. (Ryan) * Rename interconnect driver mt8183.c to mtk-emi.c * Rename interconnect header mtk,mt8183.h to mtk,emi.h * mtk-scpsys.c: Add opp table check first to avoid OF runtime parse failed Changes in RFC V2: * Remove the DT property dram_type. (Rob) * Used generic dts property 'opp-level' to get the performace state. (Stephen) * Remove unecessary dependency config on Kconfig. (Stephen) * Remove unused header file, fixed some coding style issue, typo, error handling on dvfsrc driver. (Nicolas/Stephen) * Remove irq handler on dvfsrc driver. (Stephen) * Remove init table on dvfsrc driver, combine hw init on trustzone. * Add interconnect support of mt8183 to aggregate the emi bandwidth. (Georgi) V4: https://lore.kernel.org/patchwork/cover/1209284/ V3: https://patchwork.kernel.org/cover/8867/ RFC V2: https://lore.kernel.org/patchwork/patch/1068113/ RFC V1: https://lore.kernel.org/patchwork/cover/1028535/
Re: [PATCH V3 08/10] dt-bindings: interconnect: add MT8183 interconnect dt-bindings
On Mon, 2019-09-02 at 14:38 +0100, Rob Herring wrote:
Hi Rob,
> On Wed, Aug 28, 2019 at 08:28:46PM +0800, Henry Chen wrote:
> > Add interconnect provider dt-bindings for MT8183.
> >
> > Signed-off-by: Henry Chen
> > ---
> > .../devicetree/bindings/soc/mediatek/dvfsrc.txt| 9 +
> > include/dt-bindings/interconnect/mtk,mt8183-emi.h | 18
> > ++
> > 2 files changed, 27 insertions(+)
> > create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h
> >
> > diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
> > b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
> > index 7f43499..da98ec9 100644
> > --- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
> > +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
> > @@ -12,6 +12,11 @@ Required Properties:
> > - clock-names: Must include the following entries:
> > "dvfsrc": DVFSRC module clock
> > - clocks: Must contain an entry for each entry in clock-names.
> > +- #interconnect-cells : should contain 1
> > +- interconnect : interconnect providers support dram bandwidth
> > requirements.
> > + The provider is able to communicate with the DVFSRC and send the dram
> > + bandwidth to it. shall contain only one of the following:
> > + "mediatek,mt8183-emi"
> >
> > Example:
> >
> > @@ -20,4 +25,8 @@ Example:
> > reg = <0 0x10012000 0 0x1000>;
> > clocks = < CLK_INFRA_DVFSRC>;
> > clock-names = "dvfsrc";
> > + ddr_emi: interconnect {
>
> The EMI is a sub-module in the DVFSRC? This is the DDR controller or
> something else?
Yes, EMI is a sub-module in the DVFSRC, the EMI through interconnect
framework to collect DRAM bandwidth from other device drivers and will
send the bandwidth result to DVFSRC driver.
>
>
> > + compatible = "mediatek,mt8183-emi";
> > + #interconnect-cells = <1>;
> > + };
> > };
>
Re: [PATCH V3 01/10] dt-bindings: soc: Add dvfsrc driver bindings
On Thu, 2019-08-29 at 14:16 -0500, Rob Herring wrote: > On Wed, 28 Aug 2019 20:28:39 +0800, Henry Chen wrote: > > Document the binding for enabling dvfsrc on MediaTek SoC. > > > > Signed-off-by: Henry Chen > > --- > > .../devicetree/bindings/soc/mediatek/dvfsrc.txt| 23 > > ++ > > include/dt-bindings/soc/mtk,dvfsrc.h | 14 + > > 2 files changed, 37 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > > create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h > > > > Please add Acked-by/Reviewed-by tags when posting new versions. However, > there's no need to repost patches *only* to add the tags. The upstream > maintainer will do that for acks received on the version they apply. > > If a tag was not added on purpose, please state why and what changed. Hi Rob, I'm sorry for the mistake. I stand corrected, and will add tags on next version. Henry
[PATCH V3 08/10] dt-bindings: interconnect: add MT8183 interconnect dt-bindings
Add interconnect provider dt-bindings for MT8183.
Signed-off-by: Henry Chen
---
.../devicetree/bindings/soc/mediatek/dvfsrc.txt| 9 +
include/dt-bindings/interconnect/mtk,mt8183-emi.h | 18 ++
2 files changed, 27 insertions(+)
create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
index 7f43499..da98ec9 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
@@ -12,6 +12,11 @@ Required Properties:
- clock-names: Must include the following entries:
"dvfsrc": DVFSRC module clock
- clocks: Must contain an entry for each entry in clock-names.
+- #interconnect-cells : should contain 1
+- interconnect : interconnect providers support dram bandwidth requirements.
+ The provider is able to communicate with the DVFSRC and send the dram
+ bandwidth to it. shall contain only one of the following:
+ "mediatek,mt8183-emi"
Example:
@@ -20,4 +25,8 @@ Example:
reg = <0 0x10012000 0 0x1000>;
clocks = < CLK_INFRA_DVFSRC>;
clock-names = "dvfsrc";
+ ddr_emi: interconnect {
+ compatible = "mediatek,mt8183-emi";
+ #interconnect-cells = <1>;
+ };
};
diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h
b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
new file mode 100644
index 000..2a54856
--- /dev/null
+++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
+#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
+
+#define MT8183_SLAVE_DDR_EMI 0
+#define MT8183_MASTER_MCUSYS 1
+#define MT8183_MASTER_GPU 2
+#define MT8183_MASTER_MMSYS3
+#define MT8183_MASTER_MM_VPU 4
+#define MT8183_MASTER_MM_DISP 5
+#define MT8183_MASTER_MM_VDEC 6
+#define MT8183_MASTER_MM_VENC 7
+#define MT8183_MASTER_MM_CAM 8
+#define MT8183_MASTER_MM_IMG 9
+#define MT8183_MASTER_MM_MDP 10
+
+#endif
--
1.9.1
[PATCH V3 02/10] dt-bindings: soc: Add opp table on scpsys bindings
Add opp table on scpsys dt-bindings for Mediatek SoC.
Signed-off-by: Henry Chen
---
.../devicetree/bindings/soc/mediatek/scpsys.txt| 42 ++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 00eab7e..134430a 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -64,6 +64,10 @@ Optional properties:
- mfg_2d-supply: Power supply for the mfg_2d power domain
- mfg-supply: Power supply for the mfg power domain
+- operating-points-v2: Phandle to the OPP table for the Power domain.
+ Refer to Documentation/devicetree/bindings/power/power_domain.txt
+ and Documentation/devicetree/bindings/opp/opp.txt for more details
+
Example:
scpsys: scpsys@10006000 {
@@ -76,6 +80,27 @@ Example:
< CLK_TOP_VENC_SEL>,
< CLK_TOP_VENC_LT_SEL>;
clock-names = "mfg", "mm", "venc", "venc_lt";
+ operating-points-v2 = <_opp_table>;
+
+ dvfsrc_opp_table: opp-table {
+ compatible = "operating-points-v2-level";
+
+ dvfsrc_vol_min: opp1 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_medium: opp2 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_max: opp3 {
+ opp,level = ;
+ };
+
+ dvfsrc_vol_max: opp4 {
+ opp,level = ;
+ };
+ };
};
Example consumer:
@@ -83,4 +108,21 @@ Example consumer:
afe: mt8173-afe-pcm@1122 {
compatible = "mediatek,mt8173-afe-pcm";
power-domains = < MT8173_POWER_DOMAIN_AUDIO>;
+ operating-points-v2 = <_opp_table>;
+ };
+
+ aud_opp_table: aud-opp-table {
+ compatible = "operating-points-v2";
+ opp1 {
+ opp-hz = /bits/ 64 <79300>;
+ required-opps = <_vol_min>;
+ };
+ opp2 {
+ opp-hz = /bits/ 64 <91000>;
+ required-opps = <_vol_max>;
+ };
+ opp3 {
+ opp-hz = /bits/ 64 <101400>;
+ required-opps = <_vol_max>;
+ };
};
--
1.9.1
[PATCH V3 07/10] arm64: dts: mt8183: add dvfsrc related nodes
Enable dvfsrc on mt8183 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index a58999f..7512f84 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -143,6 +143,13 @@
clock-output-names = "clk26m";
};
+ dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ clocks = < CLK_INFRA_DVFSRC>;
+ clock-names = "dvfsrc";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <>;
--
1.9.1
[PATCH V3 09/10] interconnect: mediatek: Add mt8183 interconnect provider driver
Introduce Mediatek MT8183 specific provider driver using the
interconnect framework.
Signed-off-by: Henry Chen
---
drivers/interconnect/Kconfig| 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 13 ++
drivers/interconnect/mediatek/Makefile | 3 +
drivers/interconnect/mediatek/mtk-emi.c | 246
5 files changed, 264 insertions(+)
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/mtk-emi.c
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
index bfa4ca3..dd9ecb6 100644
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@@ -12,5 +12,6 @@ menuconfig INTERCONNECT
if INTERCONNECT
source "drivers/interconnect/qcom/Kconfig"
+source "drivers/interconnect/mediatek/Kconfig"
endif
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
index 28f2ab0..253f24a3 100644
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@@ -4,3 +4,4 @@ icc-core-objs := core.o
obj-$(CONFIG_INTERCONNECT) += icc-core.o
obj-$(CONFIG_INTERCONNECT_QCOM)+= qcom/
+obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/
diff --git a/drivers/interconnect/mediatek/Kconfig
b/drivers/interconnect/mediatek/Kconfig
new file mode 100644
index 000..972d3bb
--- /dev/null
+++ b/drivers/interconnect/mediatek/Kconfig
@@ -0,0 +1,13 @@
+config INTERCONNECT_MTK
+ bool "Mediatek Network-on-Chip interconnect drivers"
+ depends on ARCH_MEDIATEK
+ help
+ Support for Mediatek's Network-on-Chip interconnect hardware.
+
+config INTERCONNECT_MTK_EMI
+ tristate "Mediatek EMI interconnect driver"
+ depends on INTERCONNECT_MTK
+ depends on (MTK_DVFSRC && OF)
+ help
+ This is a driver for the Mediatek Network-on-Chip on DVFSRC-based
+ platforms.
diff --git a/drivers/interconnect/mediatek/Makefile
b/drivers/interconnect/mediatek/Makefile
new file mode 100644
index 000..353842b
--- /dev/null
+++ b/drivers/interconnect/mediatek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o
\ No newline at end of file
diff --git a/drivers/interconnect/mediatek/mtk-emi.c
b/drivers/interconnect/mediatek/mtk-emi.c
new file mode 100644
index 000..22d2777
--- /dev/null
+++ b/drivers/interconnect/mediatek/mtk-emi.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum mtk_icc_name {
+ SLAVE_DDR_EMI,
+ MASTER_MCUSYS,
+ MASTER_GPUSYS,
+ MASTER_MMSYS,
+ MASTER_MM_VPU,
+ MASTER_MM_DISP,
+ MASTER_MM_VDEC,
+ MASTER_MM_VENC,
+ MASTER_MM_CAM,
+ MASTER_MM_IMG,
+ MASTER_MM_MDP,
+};
+
+#define MT8183_MAX_LINKS 6
+
+/**
+ * struct mtk_icc_node - Mediatek specific interconnect nodes
+ * @name: the node name used in debugfs
+ * @ep: true if the node is an end point.
+ * @id: a unique node identifier
+ * @links: an array of nodes where we can go next while traversing
+ * @num_links: the total number of @links
+ * @buswidth: width of the interconnect between a node and the bus
+ * @sum_avg: current sum aggregate value of all avg bw kBps requests
+ * @max_peak: current max aggregate value of all peak bw kBps requests
+ */
+struct mtk_icc_node {
+ unsigned char *name;
+ bool ep;
+ u16 id;
+ u16 links[MT8183_MAX_LINKS];
+ u16 num_links;
+ u16 buswidth;
+ u64 sum_avg;
+ u64 max_peak;
+};
+
+struct mtk_icc_desc {
+ struct mtk_icc_node **nodes;
+ size_t num_nodes;
+};
+
+#define DEFINE_MNODE(_name, _id, _buswidth, _ep, ...) \
+ static struct mtk_icc_node _name = {\
+ .name = #_name, \
+ .id = _id, \
+ .buswidth = _buswidth, \
+ .ep = _ep, \
+ .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
+}
+
+DEFINE_MNODE(ddr_emi, SLAVE_DDR_EMI, 1024, 1, 0);
+DEFINE_MNODE(mcusys, MASTER_MCUSYS, 256, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(gpu, MASTER_GPUSYS, 256, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(mmsys, MASTER_MMSYS, 256, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(mm_vpu, MASTER_MM_VPU, 128, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_disp, MASTER_MM_DISP, 128, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_vdec, MASTER_MM_VDEC, 128, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_venc, MASTER_MM_VENC, 128, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_cam, MASTER_MM_
[PATCH V3 10/10] arm64: dts: mt8183: Add interconnect provider DT nodes
Add DDR EMI provider dictating dram interconnect bus performance
found on MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 7512f84..a3af77d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -11,6 +11,7 @@
#include
#include "mt8183-pinfunc.h"
#include
+#include
/ {
compatible = "mediatek,mt8183";
@@ -148,6 +149,10 @@
reg = <0 0x10012000 0 0x1000>;
clocks = < CLK_INFRA_DVFSRC>;
clock-names = "dvfsrc";
+ ddr_emi: interconnect {
+ compatible = "mediatek,mt8183-emi";
+ #interconnect-cells = <1>;
+ };
};
timer {
--
1.9.1
[PATCH V3 05/10] soc: mediatek: add header for mediatek SIP interface
Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Henry Chen --- include/soc/mediatek/mtk_sip.h | 17 + 1 file changed, 17 insertions(+) create mode 100644 include/soc/mediatek/mtk_sip.h diff --git a/include/soc/mediatek/mtk_sip.h b/include/soc/mediatek/mtk_sip.h new file mode 100644 index 000..945fc72 --- /dev/null +++ b/include/soc/mediatek/mtk_sip.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2018 MediaTek Inc. + */ +#ifndef __SOC_MTK_SIP_H +#define __SOC_MTK_SIP_H + +#ifdef CONFIG_ARM64 +#define MTK_SIP_SMC_AARCH_BIT 0x4000 +#else +#define MTK_SIP_SMC_AARCH_BIT 0x +#endif + +#define MTK_SIP_SPM(0x82000506 | MTK_SIP_SMC_AARCH_BIT) +#define MTK_SIP_SPM_DVFSRC_INIT0x00 + +#endif -- 1.9.1
[PATCH V3 04/10] arm64: dts: mt8183: add performance state support of scpsys
Add support for performance state of scpsys on mt8183 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 66aaa07..a58999f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -10,6 +10,7 @@
#include
#include
#include "mt8183-pinfunc.h"
+#include
/ {
compatible = "mediatek,mt8183";
@@ -293,6 +294,26 @@
"vpu-3", "vpu-4", "vpu-5";
infracfg = <>;
smi_comm = <_common>;
+ operating-points-v2 = <_opp_table>;
+ dvfsrc_opp_table: opp-table {
+ compatible = "operating-points-v2-level";
+
+ dvfsrc_vol_min: opp1 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_medium: opp2 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_max: opp3 {
+ opp,level = ;
+ };
+
+ dvfsrc_vol_max: opp4 {
+ opp,level = ;
+ };
+ };
};
apmixedsys: syscon@1000c000 {
--
1.9.1
[PATCH V3 00/10] Add driver for dvfsrc, support for active state of scpsys
The patchsets add support for MediaTek hardware module named DVFSRC (dynamic voltage and frequency scaling resource collector). The DVFSRC is a HW module which is used to collect all the requests from both software and hardware and turn into the decision of minimum operating voltage and minimum DRAM frequency to fulfill those requests. So, This series is to implement the dvfsrc driver to collect all the requests of operating voltage or DRAM bandwidth from other device drivers likes GPU/Camera through 2 frameworks basically: 1. interconnect framework: to aggregate the bandwidth requirements from different clients [1] https://patchwork.kernel.org/cover/10766329/ Below is the emi bandwidth map of mt8183. There has a hw module "DRAM scheduler" which used to control the throughput. The DVFSRC will collect forecast data of dram bandwidth from SW consumers(camera/gpu...), and according the forecast to change the DRAM frequency ICC provider ICC Nodes - |CPU | |--->|VPU | - | |-> | |DRAM |--|DRAM | | | |--|scheduler|->|GPU | |--->|DISP| | |--|(EMI)| | | |--| | - | - | |->|MMSYS|--|--->|VDEC| -- | /|\| |change DRAM freq |--->|VENC| -- | | DVFSR | | | | | -- |--->|IMG | | | |--->|CAM | 2. Active state management of power domains[1]: to handle the operating voltage opp requirement from different power domains [2] https://lwn.net/Articles/744047/ Changes in RFC V3: * Remove RFC from the subject prefix of the series * Combine dt-binding patch and move interconnect dt-binding document into dvfsrc. (Rob) * Remove unused header, add unit descirption to the bandwidth, rename compatible name on interconnect driver. (Georgi) * Fixed some coding style: check flow, naming, used readx_poll_timeout on dvfsrc driver. (Ryan) * Rename interconnect driver mt8183.c to mtk-emi.c * Rename interconnect header mtk,mt8183.h to mtk,emi.h * mtk-scpsys.c: Add opp table check first to avoid OF runtime parse failed Changes in RFC V2: * Remove the DT property dram_type. (Rob) * Used generic dts property 'opp-level' to get the performace state. (Stephen) * Remove unecessary dependency config on Kconfig. (Stephen) * Remove unused header file, fixed some coding style issue, typo, error handling on dvfsrc driver. (Nicolas/Stephen) * Remove irq handler on dvfsrc driver. (Stephen) * Remove init table on dvfsrc driver, combine hw init on trustzone. * Add interconnect support of mt8183 to aggregate the emi bandwidth. (Georgi) RFC V2: https://lore.kernel.org/patchwork/patch/1068113/ RFC V1: https://lore.kernel.org/patchwork/cover/1028535/ Henry Chen (10): dt-bindings: soc: Add dvfsrc driver bindings dt-bindings: soc: Add opp table on scpsys bindings soc: mediatek: add support for the performance state arm64: dts: mt8183: add performance state support of scpsys soc: mediatek: add header for mediatek SIP interface soc: mediatek: add MT8183 dvfsrc support arm64: dts: mt8183: add dvfsrc related nodes dt-bindings: interconnect: add MT8183 interconnect dt-bindings interconnect: mediatek: Add mt8183 interconnect provider driver arm64: dts: mt8183: Add interconnect provider DT nodes .../devicetree/bindings/soc/mediatek/dvfsrc.txt| 32 ++ .../devicetree/bindings/soc/mediatek/scpsys.txt| 42 +++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 33 ++ drivers/interconnect/Kconfig | 1 + drivers/interconnect/Makefile | 1 + drivers/interconnect/mediatek/Kconfig | 13 + drivers/interconnect/mediatek/Makefile | 3 + drivers/interconnect/mediatek/mtk-emi.c| 246 ++ drivers/soc/mediatek/Kconfig | 15 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-dvfsrc.c | 374 + drivers/soc/mediatek/mtk-scpsys.c | 58 drivers/soc/mediatek/mtk-scpsys.h | 22 ++ include/dt-bindings/interconnect/mtk,mt8183-emi.h | 18 + include/dt-bindings/soc/mtk,dvfsrc.h | 14 + include/soc/mediatek/mtk_dvfsrc.h | 22 ++ include/soc/mediatek/mtk_sip.h | 17 + 17 files changed, 912 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/d
[PATCH V3 03/10] soc: mediatek: add support for the performance state
Support power domain performance state, add header file for scp event.
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/mtk-scpsys.c | 58 +++
drivers/soc/mediatek/mtk-scpsys.h | 22 +++
2 files changed, 80 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-scpsys.h
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index e072810..50bc254 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -10,7 +10,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
@@ -21,6 +23,7 @@
#include
#include
#include
+#include "mtk-scpsys.h"
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUTUSEC_PER_SEC
@@ -187,6 +190,18 @@ struct scp_soc_data {
bool bus_prot_reg_update;
};
+static BLOCKING_NOTIFIER_HEAD(scpsys_notifier_list);
+
+int register_scpsys_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(_notifier_list, nb);
+}
+
+int unregister_scpsys_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(_notifier_list, nb);
+}
+
static int scpsys_domain_is_on(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
@@ -505,6 +520,41 @@ static void init_clks(struct platform_device *pdev, struct
clk **clk)
clk[i] = devm_clk_get(>dev, clk_names[i]);
}
+static int mtk_pd_set_performance(struct generic_pm_domain *genpd,
+ unsigned int state)
+{
+ int i;
+ struct scp_domain *scpd =
+ container_of(genpd, struct scp_domain, genpd);
+ struct scp_event_data scpe;
+ struct scp *scp = scpd->scp;
+ struct genpd_onecell_data *pd_data = >pd_data;
+
+ for (i = 0; i < pd_data->num_domains; i++) {
+ if (genpd == pd_data->domains[i]) {
+ dev_dbg(scp->dev, "%d. %s = %d\n",
+ i, genpd->name, state);
+ break;
+ }
+ }
+
+ if (i == pd_data->num_domains)
+ return 0;
+
+ scpe.event_type = MTK_SCPSYS_PSTATE;
+ scpe.genpd = genpd;
+ scpe.domain_id = i;
+ blocking_notifier_call_chain(_notifier_list, state, );
+
+ return 0;
+}
+
+static unsigned int mtk_pd_get_performance(struct generic_pm_domain *genpd,
+ struct dev_pm_opp *opp)
+{
+ return dev_pm_opp_get_level(opp);
+}
+
static struct scp *init_scp(struct platform_device *pdev,
const struct scp_domain_data *scp_domain_data, int num,
const struct scp_ctrl_reg *scp_ctrl_reg,
@@ -630,6 +680,14 @@ static struct scp *init_scp(struct platform_device *pdev,
genpd->power_on = scpsys_power_on;
if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ACTIVE_WAKEUP))
genpd->flags |= GENPD_FLAG_ACTIVE_WAKEUP;
+
+ /* Add opp table check first to avoid OF runtime parse failed */
+ if (of_count_phandle_with_args(pdev->dev.of_node,
+ "operating-points-v2", NULL) > 0) {
+ genpd->set_performance_state = mtk_pd_set_performance;
+ genpd->opp_to_performance_state =
+ mtk_pd_get_performance;
+ }
}
return scp;
diff --git a/drivers/soc/mediatek/mtk-scpsys.h
b/drivers/soc/mediatek/mtk-scpsys.h
new file mode 100644
index 000..c1e8325
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ */
+
+#ifndef __MTK_SCPSYS_H__
+#define __MTK_SCPSYS_H__
+
+struct scp_event_data {
+ int event_type;
+ int domain_id;
+ struct generic_pm_domain *genpd;
+};
+
+enum scp_event_type {
+ MTK_SCPSYS_PSTATE,
+};
+
+int register_scpsys_notifier(struct notifier_block *nb);
+int unregister_scpsys_notifier(struct notifier_block *nb);
+
+#endif /* __MTK_SCPSYS_H__ */
--
1.9.1
[PATCH V3 06/10] soc: mediatek: add MT8183 dvfsrc support
Add dvfsrc driver for MT8183
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/Kconfig | 15 ++
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 374 ++
include/soc/mediatek/mtk_dvfsrc.h | 22 +++
4 files changed, 412 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 include/soc/mediatek/mtk_dvfsrc.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 2114b56..384cfb5 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -25,6 +25,21 @@ config MTK_INFRACFG
INFRACFG controller contains various infrastructure registers not
directly associated to any device.
+config MTK_DVFSRC
+ bool "MediaTek DVFSRC Support"
+ depends on ARCH_MEDIATEK
+ default ARCH_MEDIATEK
+ select MTK_INFRACFG
+ select PM_GENERIC_DOMAINS if PM
+ depends on MTK_SCPSYS
+ help
+ Say yes here to add support for the MediaTek DVFSRC (dynamic voltage
+ and frequency scaling resource collector) found
+ on different MediaTek SoCs. The DVFSRC is a proprietary
+ hardware which is used to collect all the requests from
+ system and turn into the decision of minimum Vcore voltage
+ and minimum DRAM frequency to fulfill those requests.
+
config MTK_PMIC_WRAP
tristate "MediaTek PMIC Wrapper Support"
depends on RESET_CONTROLLER
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b442be9..f0b09ad 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
+obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
new file mode 100644
index 000..ee2bb12
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mtk-scpsys.h"
+
+#define DVFSRC_IDLE0x00
+#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
+#define DVFSRC_GET_CURRENT_LEVEL(x)(((x) >> 16) & 0x)
+#define kbps_to_mbps(x)(x / 1000)
+
+#define MT8183_DVFSRC_OPP_LP4 0
+#define MT8183_DVFSRC_OPP_LP4X 1
+#define MT8183_DVFSRC_OPP_LP3 2
+
+#define POLL_TIMEOUT 1000
+#define STARTUP_TIME 1
+
+struct dvfsrc_opp {
+ u32 vcore_opp;
+ u32 dram_opp;
+};
+
+struct dvfsrc_domain {
+ u32 id;
+ u32 state;
+};
+
+struct mtk_dvfsrc;
+struct dvfsrc_soc_data {
+ const int *regs;
+ u32 num_opp;
+ u32 num_domains;
+ const struct dvfsrc_opp **opps;
+ struct dvfsrc_domain *domains;
+ int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
+ int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
+ void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+ int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+};
+
+struct mtk_dvfsrc {
+ struct device *dev;
+ struct clk *clk_dvfsrc;
+ const struct dvfsrc_soc_data *dvd;
+ int dram_type;
+ void __iomem *regs;
+ struct mutex lock;
+ struct notifier_block scpsys_notifier;
+};
+
+static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
+{
+ return readl(dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
+{
+ writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+enum dvfsrc_regs {
+ DVFSRC_SW_REQ,
+ DVFSRC_LEVEL,
+ DVFSRC_SW_BW,
+ DVFSRC_LAST,
+};
+
+static const int mt8183_regs[] = {
+ [DVFSRC_SW_REQ] = 0x4,
+ [DVFSRC_LEVEL] =0xDC,
+ [DVFSRC_SW_BW] =0x160,
+ [DVFSRC_LAST] = 0x308,
+};
+
+static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc)
+{
+ int level;
+
+ level = dvfsrc->dvd->get_current_level(dvfsrc);
+ return >dvd->opps[dvfsrc->dram_type][level];
+}
+
+static int dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc)
+{
+ if (!dvfsrc->dvd->get_target_level)
+ return true;
+
+ return dvfsrc->dvd->get_target_level(dvfsrc);
+}
+
+static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+ const struct dvfsrc_opp *target, *curr;
+ int ret;
+
+ target = >d
[PATCH V3 01/10] dt-bindings: soc: Add dvfsrc driver bindings
Document the binding for enabling dvfsrc on MediaTek SoC.
Signed-off-by: Henry Chen
---
.../devicetree/bindings/soc/mediatek/dvfsrc.txt| 23 ++
include/dt-bindings/soc/mtk,dvfsrc.h | 14 +
2 files changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
new file mode 100644
index 000..7f43499
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
@@ -0,0 +1,23 @@
+MediaTek DVFSRC
+
+The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
+HW module which is used to collect all the requests from both software and
+hardware and turn into the decision of minimum operating voltage and minimum
+DRAM frequency to fulfill those requests.
+
+Required Properties:
+- compatible: Should be one of the following
+ - "mediatek,mt8183-dvfsrc": For MT8183 SoC
+- reg: Address range of the DVFSRC unit
+- clock-names: Must include the following entries:
+ "dvfsrc": DVFSRC module clock
+- clocks: Must contain an entry for each entry in clock-names.
+
+Example:
+
+ dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ clocks = < CLK_INFRA_DVFSRC>;
+ clock-names = "dvfsrc";
+ };
diff --git a/include/dt-bindings/soc/mtk,dvfsrc.h
b/include/dt-bindings/soc/mtk,dvfsrc.h
new file mode 100644
index 000..a522488
--- /dev/null
+++ b/include/dt-bindings/soc/mtk,dvfsrc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MTK_DVFSRC_H
+#define _DT_BINDINGS_POWER_MTK_DVFSRC_H
+
+#define MT8183_DVFSRC_LEVEL_1 1
+#define MT8183_DVFSRC_LEVEL_2 2
+#define MT8183_DVFSRC_LEVEL_3 3
+#define MT8183_DVFSRC_LEVEL_4 4
+
+#endif /* _DT_BINDINGS_POWER_MTK_DVFSRC_H */
--
1.9.1
Re: [RFC V2 10/11] interconnect: mediatek: Add mt8183 interconnect provider driver
Hi Georgi,
Sorry for late reply.
On Tue, 2019-05-14 at 09:43 +0300, Georgi Djakov wrote:
> Hi Henry,
>
> On 4/30/19 11:51, Henry Chen wrote:
> > Introduce Mediatek MT8183 specific provider driver using the
> > interconnect framework.
> >
> > Signed-off-by: Henry Chen
> > ---
> > drivers/interconnect/Kconfig | 1 +
> > drivers/interconnect/Makefile | 1 +
> > drivers/interconnect/mediatek/Kconfig | 13 ++
> > drivers/interconnect/mediatek/Makefile | 5 +
> > drivers/interconnect/mediatek/mt8183.c | 223
> > +
> > 5 files changed, 243 insertions(+)
> > create mode 100644 drivers/interconnect/mediatek/Kconfig
> > create mode 100644 drivers/interconnect/mediatek/Makefile
> > create mode 100644 drivers/interconnect/mediatek/mt8183.c
> >
> > diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
> > index 07a8276..ac41ea6 100644
> > --- a/drivers/interconnect/Kconfig
> > +++ b/drivers/interconnect/Kconfig
> > @@ -11,5 +11,6 @@ menuconfig INTERCONNECT
> > if INTERCONNECT
> >
> > source "drivers/interconnect/qcom/Kconfig"
> > +source "drivers/interconnect/mediatek/Kconfig"
> >
> > endif
> > diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
> > index 28f2ab0..253f24a3 100644
> > --- a/drivers/interconnect/Makefile
> > +++ b/drivers/interconnect/Makefile
> > @@ -4,3 +4,4 @@ icc-core-objs := core.o
> >
> > obj-$(CONFIG_INTERCONNECT) += icc-core.o
> > obj-$(CONFIG_INTERCONNECT_QCOM)+= qcom/
> > +obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/
> > diff --git a/drivers/interconnect/mediatek/Kconfig
> > b/drivers/interconnect/mediatek/Kconfig
> > new file mode 100644
> > index 000..0686494
> > --- /dev/null
> > +++ b/drivers/interconnect/mediatek/Kconfig
> > @@ -0,0 +1,13 @@
> > +config INTERCONNECT_MTK
> > + bool "Mediatek Network-on-Chip interconnect drivers"
> > + depends on ARCH_MEDIATEK
> > + help
> > + Support for Mediatek's Network-on-Chip interconnect hardware.
> > +
> > +config INTERCONNECT_MTK_MT8183
> > + tristate "Mediatek MT8183 interconnect driver"
> > + depends on INTERCONNECT_MTK
> > + depends on (MTK_DVFSRC && OF)
> > + help
> > + This is a driver for the Mediatek Network-on-Chip on mt8183-based
> > + platforms.
> > diff --git a/drivers/interconnect/mediatek/Makefile
> > b/drivers/interconnect/mediatek/Makefile
> > new file mode 100644
> > index 000..a39ceee
> > --- /dev/null
> > +++ b/drivers/interconnect/mediatek/Makefile
> > @@ -0,0 +1,5 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +
> > +mtk-mt8183-objs:= mt8183.o
> > +
> > +obj-$(CONFIG_INTERCONNECT_MTK_MT8183) += mtk-mt8183.o
> > \ No newline at end of file
> > diff --git a/drivers/interconnect/mediatek/mt8183.c
> > b/drivers/interconnect/mediatek/mt8183.c
> > new file mode 100644
> > index 000..38ffe0b
> > --- /dev/null
> > +++ b/drivers/interconnect/mediatek/mt8183.c
> > @@ -0,0 +1,223 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> > + *
> > + */
> > +
> > +#include
> > +#include
> > +#include
>
> This is not needed.
ok, thanks.
>
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#define MT8183_MAX_LINKS 6
> > +
> > +/**
> > + * struct mtk_icc_node - Mediatek specific interconnect nodes
> > + * @name: the node name used in debugfs
> > + * @ep: true if the node is an end point.
> > + * @id: a unique node identifier
> > + * @links: an array of nodes where we can go next while traversing
> > + * @num_links: the total number of @links
> > + * @buswidth: width of the interconnect between a node and the bus
>
> Maybe mention the units?
ok, I will add it.
>
> > + * @sum_avg: current sum aggregate value of all avg bw requests
> > + * @max_peak: current max aggregate value of all peak bw requests
>
> units?
>
> > + */
> > +struct mtk_icc_node {
> > + unsigned char *name;
> > + bool ep;
> > + u16 id;
> > + u16 links[MT8183_MAX_LINKS];
> > + u16 num_links;
> > + u16 buswidth;
> > + u64 sum_avg;
> > +
Re: [RFC V2 09/11] dt-bindings: interconnect: Add header for interconnect node
On Wed, 2019-05-01 at 15:28 -0500, Rob Herring wrote: > On Tue, Apr 30, 2019 at 04:51:03PM +0800, Henry Chen wrote: > > Add header file for mt8183 interconnect node that could be shared between > > the interconeect provider driver and Device Tree source files. > > > > Signed-off-by: Henry Chen > > --- > > include/dt-bindings/interconnect/mtk,mt8183.h | 18 ++ > > 1 file changed, 18 insertions(+) > > create mode 100644 include/dt-bindings/interconnect/mtk,mt8183.h > > This goes with the binding patch. ok, will merged into previous patch 08.
Re: [RFC V2 08/11] dt-bindings: interconnect: add MT8183 interconnect dt-bindings
Hi Rob,
Sorry for late reply.
On Wed, 2019-05-01 at 15:27 -0500, Rob Herring wrote:
> On Tue, Apr 30, 2019 at 04:51:02PM +0800, Henry Chen wrote:
> > Add interconnect provider dt-bindings for MT8183.
> >
> > Signed-off-by: Henry Chen
> > ---
> > .../bindings/interconnect/mtk,mt8183.txt | 24
> > ++
> > 1 file changed, 24 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt
> >
> > diff --git a/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt
> > b/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt
> > new file mode 100644
> > index 000..1cf1841
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt
> > @@ -0,0 +1,24 @@
> > +Mediatek MT8183 interconnect binding
>
> This should be part of the dvfsrc binding.
ok, will add these into dvfsrc binding.
>
> > +
> > +MT8183 interconnect providers support dram bandwidth requirements. The
> > provider
> > +is able to communicate with the DVFSRC and send the dram bandwidth to it.
> > +Provider nodes must reside within an DVFSRC device node.
> > +
> > +Required properties :
> > +- compatible : shall contain only one of the following:
> > + "mediatek,mt8183-emi-icc"
> > +- #interconnect-cells : should contain 1
> > +
> > +Examples:
> > +
> > +dvfsrc@10012000 {
> > + compatible = "mediatek,mt8183-dvfsrc";
> > + reg = <0 0x10012000 0 0x1000>;
> > + clocks = < CLK_INFRA_DVFSRC>;
> > + clock-names = "dvfsrc";
> > + ddr_emi: interconnect {
> > + compatible = "mediatek,mt8183-emi-icc";
> > + #interconnect-cells = <1>;
>
> No need for a child node here. Just move #interconnect-cells to the
> parent.
Ihave tried and it cannot work if move "#interconnect-cells" to the
parent.
The provider nodes must reside within an DVFSRC device node.
>
> Rob
Re: [RFC V2 06/11] soc: mediatek: add MT8183 dvfsrc support
On Mon, 2019-06-10 at 14:00 -0700, Ryan Case wrote:
Hi Ryan,
Sorry for late reply.
> Hi Henry,
>
> On Tue, Apr 30, 2019 at 2:45 AM Henry Chen wrote:
> >
> > Add dvfsrc driver for MT8183
> >
> > Signed-off-by: Henry Chen
> > ---
> > drivers/soc/mediatek/Kconfig | 15 ++
> > drivers/soc/mediatek/Makefile | 1 +
> > drivers/soc/mediatek/mtk-dvfsrc.c | 347
> > ++
> > include/soc/mediatek/mtk_dvfsrc.h | 22 +++
> > 4 files changed, 385 insertions(+)
> > create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
> > create mode 100644 include/soc/mediatek/mtk_dvfsrc.h
> >
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index 17bd759..2721fd6 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -24,6 +24,21 @@ config MTK_INFRACFG
> > INFRACFG controller contains various infrastructure registers not
> > directly associated to any device.
> >
> > +config MTK_DVFSRC
> > + bool "MediaTek DVFSRC Support"
> > + depends on ARCH_MEDIATEK
> > + default ARCH_MEDIATEK
> > + select MTK_INFRACFG
> > + select PM_GENERIC_DOMAINS if PM
> > + depends on MTK_SCPSYS
> > + help
> > + Say yes here to add support for the MediaTek DVFSRC (dynamic
> > voltage
> > + and frequency scaling resource collector) found
> > + on different MediaTek SoCs. The DVFSRC is a proprietary
> > + hardware which is used to collect all the requests from
> > + system and turn into the decision of minimum Vcore voltage
> > + and minimum DRAM frequency to fulfill those requests.
> > +
> > config MTK_PMIC_WRAP
> > tristate "MediaTek PMIC Wrapper Support"
> > depends on RESET_CONTROLLER
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index b9dbad6..cd9d63f 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -1,4 +1,5 @@
> > obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> > +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
> > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
> > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
> > b/drivers/soc/mediatek/mtk-dvfsrc.c
> > new file mode 100644
> > index 000..e54a654
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mtk-dvfsrc.c
> > @@ -0,0 +1,347 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2018 MediaTek Inc.
> > + */
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include "mtk-scpsys.h"
> > +
> > +#define DVFSRC_IDLE0x00
> > +#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
> > +#define DVFSRC_GET_CURRENT_LEVEL(x)(((x) >> 16) & 0x)
> > +
> > +#define MT8183_DVFSRC_OPP_LP4 0
> > +#define MT8183_DVFSRC_OPP_LP4X 1
> > +#define MT8183_DVFSRC_OPP_LP3 2
> > +
> > +struct dvfsrc_opp {
> > + u32 vcore_opp;
> > + u32 dram_opp;
> > +};
> > +
> > +struct dvfsrc_domain {
> > + u32 id;
> > + u32 state;
> > +};
> > +
> > +struct mtk_dvfsrc;
> > +struct dvfsrc_soc_data {
> > + const int *regs;
> > + u32 num_opp;
> > + u32 num_domains;
> > + const struct dvfsrc_opp **opps;
> > + struct dvfsrc_domain *domains;
> > + int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
> > + int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
> > + void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
> > + void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
> > +};
> > +
> > +struct mtk_dvfsrc {
> > + struct device *dev;
> > + struct clk *clk_dvfsrc;
> > + const struct dvfsrc_soc_data *dvd;
> > + int dram_type;
> > + void __iomem *regs;
> > + struct mutex lock;
> > + struct notifier_block scpsys_notifier;
> > +};
> > +
> > +static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
> > +{
> > + return readl(dvfs-&g
[RFC V2 07/11] arm64: dts: mt8183: add dvfsrc related nodes
Enable dvfsrc on mt8183 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 665d561..d298013 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -134,6 +134,13 @@
clock-output-names = "clk26m";
};
+ dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ clocks = < CLK_INFRA_DVFSRC>;
+ clock-names = "dvfsrc";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <>;
--
1.9.1
[RFC V2 02/11] dt-bindings: soc: Add opp table on scpsys bindings
Add opp table on scpsys dt-bindings for Mediatek SoC.
Signed-off-by: Henry Chen
---
.../devicetree/bindings/soc/mediatek/scpsys.txt| 42 ++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index b4728ce..33df802 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -63,6 +63,10 @@ Optional properties:
- mfg_2d-supply: Power supply for the mfg_2d power domain
- mfg-supply: Power supply for the mfg power domain
+- operating-points-v2: Phandle to the OPP table for the Power domain.
+ Refer to Documentation/devicetree/bindings/power/power_domain.txt
+ and Documentation/devicetree/bindings/opp/opp.txt for more details
+
Example:
scpsys: scpsys@10006000 {
@@ -75,6 +79,27 @@ Example:
< CLK_TOP_VENC_SEL>,
< CLK_TOP_VENC_LT_SEL>;
clock-names = "mfg", "mm", "venc", "venc_lt";
+ operating-points-v2 = <_opp_table>;
+
+ dvfsrc_opp_table: opp-table {
+ compatible = "operating-points-v2-level";
+
+ dvfsrc_vol_min: opp1 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_medium: opp2 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_max: opp3 {
+ opp,level = ;
+ };
+
+ dvfsrc_vol_max: opp4 {
+ opp,level = ;
+ };
+ };
};
Example consumer:
@@ -82,4 +107,21 @@ Example consumer:
afe: mt8173-afe-pcm@1122 {
compatible = "mediatek,mt8173-afe-pcm";
power-domains = < MT8173_POWER_DOMAIN_AUDIO>;
+ operating-points-v2 = <_opp_table>;
+ };
+
+ aud_opp_table: aud-opp-table {
+ compatible = "operating-points-v2";
+ opp1 {
+ opp-hz = /bits/ 64 <79300>;
+ required-opps = <_vol_min>;
+ };
+ opp2 {
+ opp-hz = /bits/ 64 <91000>;
+ required-opps = <_vol_max>;
+ };
+ opp3 {
+ opp-hz = /bits/ 64 <101400>;
+ required-opps = <_vol_max>;
+ };
};
--
1.9.1
[PATCH RFC V2] Add driver for dvfsrc, support for active state of scpsys
The patchsets add support for MediaTek hardware module named DVFSRC (dynamic voltage and frequency scaling resource collector). The DVFSRC is a HW module which is used to collect all the requests from both software and hardware and turn into the decision of minimum operating voltage and minimum DRAM frequency to fulfill those requests. So, This series is to implement the dvfsrc driver to collect all the requests of operating voltage or DRAM bandwidth from other device drivers likes GPU/Camera through 2 frameworks basically: 1. interconnect framework: to aggregate the bandwidth requirements from different clients [1] https://patchwork.kernel.org/cover/10766329/ Below is the emi bandwidth map of mt8183. There has a hw module "DRAM scheduler" which used to control the throughput. The DVFSRC will collect forecast data of dram bandwidth from SW consumers(camera/gpu...), and according the forecast to change the DRAM frequency ICC provider ICC Nodes - |CPU | |--->|VPU | - | |-> | |DRAM |--|DRAM | | | |--|scheduler|->|GPU | |--->|DISP| | |--|(EMI)| | | |--| | - | - | |->|MMSYS|--|--->|VDEC| -- | /|\| |change DRAM freq |--->|VENC| -- | | DVFSR | | | | | -- |--->|IMG | | | |--->|CAM | 2. Active state management of power domains[1]: to handle the operating voltage opp requirement from different power domains [2] https://lwn.net/Articles/744047/ Changes in RFC V2: * Remove the DT property dram_type. (Rob) * Used generic dts property 'opp-level' to get the performace state. (Stephen) * Remove unecessary dependency config on Kconfig. (Stephen) * Remove unused header file, fixed some coding style issue, typo, error handling on dvfsrc driver. (Nicolas/Stephen) * Remove irq handler on dvfsrc driver. (Stephen) * Remove init table on dvfsrc driver, combine hw init on trustzone. * Add interconnect support of mt8183 to aggregate the emi bandwidth. (Georgi) RFC V1: https://lore.kernel.org/patchwork/cover/1028535/ Henry Chen (11): dt-bindings: soc: Add dvfsrc driver bindings dt-bindings: soc: Add opp table on scpsys bindings soc: mediatek: add support for the performance state arm64: dts: mt8183: add performance state support of scpsys soc: mediatek: add header for mediatek SIP interface soc: mediatek: add MT8183 dvfsrc support arm64: dts: mt8183: add dvfsrc related nodes dt-bindings: interconnect: add MT8183 interconnect dt-bindings dt-bindings: interconnect: Add header for interconnect node interconnect: mediatek: Add mt8183 interconnect provider driver arm64: dts: mt8183: Add interconnect provider DT nodes .../bindings/interconnect/mtk,mt8183.txt | 24 ++ .../devicetree/bindings/soc/mediatek/dvfsrc.txt| 23 ++ .../devicetree/bindings/soc/mediatek/scpsys.txt| 42 +++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 33 ++ drivers/interconnect/Kconfig | 1 + drivers/interconnect/Makefile | 1 + drivers/interconnect/mediatek/Kconfig | 13 + drivers/interconnect/mediatek/Makefile | 5 + drivers/interconnect/mediatek/mt8183.c | 223 + drivers/soc/mediatek/Kconfig | 15 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-dvfsrc.c | 347 + drivers/soc/mediatek/mtk-scpsys.c | 53 drivers/soc/mediatek/mtk-scpsys.h | 22 ++ include/dt-bindings/interconnect/mtk,mt8183.h | 18 ++ include/dt-bindings/soc/mtk,dvfsrc.h | 14 + include/soc/mediatek/mtk_dvfsrc.h | 22 ++ include/soc/mediatek/mtk_sip.h | 17 + 18 files changed, 874 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt create mode 100644 drivers/interconnect/mediatek/Kconfig create mode 100644 drivers/interconnect/mediatek/Makefile create mode 100644 drivers/interconnect/mediatek/mt8183.c create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c create mode 100644 drivers/soc/mediatek/mtk-scpsys.h create mode 100644 include/dt-bindings/interconnect/mtk,mt8183.h create mode 100644 include/dt-bindings/soc/mtk
[RFC V2 08/11] dt-bindings: interconnect: add MT8183 interconnect dt-bindings
Add interconnect provider dt-bindings for MT8183.
Signed-off-by: Henry Chen
---
.../bindings/interconnect/mtk,mt8183.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt
diff --git a/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt
b/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt
new file mode 100644
index 000..1cf1841
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt
@@ -0,0 +1,24 @@
+Mediatek MT8183 interconnect binding
+
+MT8183 interconnect providers support dram bandwidth requirements. The provider
+is able to communicate with the DVFSRC and send the dram bandwidth to it.
+Provider nodes must reside within an DVFSRC device node.
+
+Required properties :
+- compatible : shall contain only one of the following:
+ "mediatek,mt8183-emi-icc"
+- #interconnect-cells : should contain 1
+
+Examples:
+
+dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ clocks = < CLK_INFRA_DVFSRC>;
+ clock-names = "dvfsrc";
+ ddr_emi: interconnect {
+ compatible = "mediatek,mt8183-emi-icc";
+ #interconnect-cells = <1>;
+ };
+};
+
--
1.9.1
[RFC V2 04/11] arm64: dts: mt8183: add performance state support of scpsys
Add support for performance state of scpsys on mt8183 platform.
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 75c4881..665d561 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
/ {
compatible = "mediatek,mt8183";
@@ -251,6 +252,26 @@
"vpu-3", "vpu-4", "vpu-5";
infracfg = <>;
smi_comm = <_common>;
+ operating-points-v2 = <_opp_table>;
+ dvfsrc_opp_table: opp-table {
+ compatible = "operating-points-v2-level";
+
+ dvfsrc_vol_min: opp1 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_medium: opp2 {
+ opp,level = ;
+ };
+
+ dvfsrc_freq_max: opp3 {
+ opp,level = ;
+ };
+
+ dvfsrc_vol_max: opp4 {
+ opp,level = ;
+ };
+ };
};
apmixedsys: syscon@1000c000 {
--
1.9.1
[RFC V2 05/11] soc: mediatek: add header for mediatek SIP interface
Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Henry Chen --- include/soc/mediatek/mtk_sip.h | 17 + 1 file changed, 17 insertions(+) create mode 100644 include/soc/mediatek/mtk_sip.h diff --git a/include/soc/mediatek/mtk_sip.h b/include/soc/mediatek/mtk_sip.h new file mode 100644 index 000..5394ff4 --- /dev/null +++ b/include/soc/mediatek/mtk_sip.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2018 MediaTek Inc. + */ +#ifndef __SOC_MTK_SIP_H +#define __SOC_MTK_SIP_H + +#ifdef CONFIG_ARM64 +#define MTK_SIP_SMC_AARCH_BIT 0x4000 +#else +#define MTK_SIP_SMC_AARCH_BIT 0x +#endif + +#define MTK_SIP_SPM(0x82000220 | MTK_SIP_SMC_AARCH_BIT) +#define MTK_SIP_SPM_DVFSRC_INIT0x00 + +#endif -- 1.9.1
[RFC V2 09/11] dt-bindings: interconnect: Add header for interconnect node
Add header file for mt8183 interconnect node that could be shared between the interconeect provider driver and Device Tree source files. Signed-off-by: Henry Chen --- include/dt-bindings/interconnect/mtk,mt8183.h | 18 ++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt8183.h diff --git a/include/dt-bindings/interconnect/mtk,mt8183.h b/include/dt-bindings/interconnect/mtk,mt8183.h new file mode 100644 index 000..34adbfa --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8183.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_H + +#define SLAVE_DDR_EMI 0 +#define MASTER_MCUSYS 1 +#define MASTER_GPU 2 +#define MASTER_MMSYS 3 +#define MASTER_MM_VPU 4 +#define MASTER_MM_DISP 5 +#define MASTER_MM_VDEC 6 +#define MASTER_MM_VENC 7 +#define MASTER_MM_CAM 8 +#define MASTER_MM_IMG 9 +#define MASTER_MM_MDP 10 + +#endif -- 1.9.1
[RFC V2 11/11] arm64: dts: mt8183: Add interconnect provider DT nodes
Add DDR EMI provider dictating dram interconnect bus performance
found on MT8183-based platforms
Signed-off-by: Henry Chen
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index d298013..ab98adb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
/ {
compatible = "mediatek,mt8183";
@@ -139,6 +140,10 @@
reg = <0 0x10012000 0 0x1000>;
clocks = < CLK_INFRA_DVFSRC>;
clock-names = "dvfsrc";
+ ddr_emi: interconnect {
+ compatible = "mediatek,mt8183-emi-icc";
+ #interconnect-cells = <1>;
+ };
};
timer {
--
1.9.1
[RFC V2 01/11] dt-bindings: soc: Add dvfsrc driver bindings
Document the binding for enabling dvfsrc on MediaTek SoC.
Signed-off-by: Henry Chen
---
.../devicetree/bindings/soc/mediatek/dvfsrc.txt| 23 ++
include/dt-bindings/soc/mtk,dvfsrc.h | 14 +
2 files changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
new file mode 100644
index 000..7f43499
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
@@ -0,0 +1,23 @@
+MediaTek DVFSRC
+
+The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
+HW module which is used to collect all the requests from both software and
+hardware and turn into the decision of minimum operating voltage and minimum
+DRAM frequency to fulfill those requests.
+
+Required Properties:
+- compatible: Should be one of the following
+ - "mediatek,mt8183-dvfsrc": For MT8183 SoC
+- reg: Address range of the DVFSRC unit
+- clock-names: Must include the following entries:
+ "dvfsrc": DVFSRC module clock
+- clocks: Must contain an entry for each entry in clock-names.
+
+Example:
+
+ dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ clocks = < CLK_INFRA_DVFSRC>;
+ clock-names = "dvfsrc";
+ };
diff --git a/include/dt-bindings/soc/mtk,dvfsrc.h
b/include/dt-bindings/soc/mtk,dvfsrc.h
new file mode 100644
index 000..a522488
--- /dev/null
+++ b/include/dt-bindings/soc/mtk,dvfsrc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MTK_DVFSRC_H
+#define _DT_BINDINGS_POWER_MTK_DVFSRC_H
+
+#define MT8183_DVFSRC_LEVEL_1 1
+#define MT8183_DVFSRC_LEVEL_2 2
+#define MT8183_DVFSRC_LEVEL_3 3
+#define MT8183_DVFSRC_LEVEL_4 4
+
+#endif /* _DT_BINDINGS_POWER_MTK_DVFSRC_H */
--
1.9.1
[RFC V2 10/11] interconnect: mediatek: Add mt8183 interconnect provider driver
Introduce Mediatek MT8183 specific provider driver using the
interconnect framework.
Signed-off-by: Henry Chen
---
drivers/interconnect/Kconfig | 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 13 ++
drivers/interconnect/mediatek/Makefile | 5 +
drivers/interconnect/mediatek/mt8183.c | 223 +
5 files changed, 243 insertions(+)
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/mt8183.c
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
index 07a8276..ac41ea6 100644
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@@ -11,5 +11,6 @@ menuconfig INTERCONNECT
if INTERCONNECT
source "drivers/interconnect/qcom/Kconfig"
+source "drivers/interconnect/mediatek/Kconfig"
endif
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
index 28f2ab0..253f24a3 100644
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@@ -4,3 +4,4 @@ icc-core-objs := core.o
obj-$(CONFIG_INTERCONNECT) += icc-core.o
obj-$(CONFIG_INTERCONNECT_QCOM)+= qcom/
+obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/
diff --git a/drivers/interconnect/mediatek/Kconfig
b/drivers/interconnect/mediatek/Kconfig
new file mode 100644
index 000..0686494
--- /dev/null
+++ b/drivers/interconnect/mediatek/Kconfig
@@ -0,0 +1,13 @@
+config INTERCONNECT_MTK
+ bool "Mediatek Network-on-Chip interconnect drivers"
+ depends on ARCH_MEDIATEK
+ help
+ Support for Mediatek's Network-on-Chip interconnect hardware.
+
+config INTERCONNECT_MTK_MT8183
+ tristate "Mediatek MT8183 interconnect driver"
+ depends on INTERCONNECT_MTK
+ depends on (MTK_DVFSRC && OF)
+ help
+ This is a driver for the Mediatek Network-on-Chip on mt8183-based
+ platforms.
diff --git a/drivers/interconnect/mediatek/Makefile
b/drivers/interconnect/mediatek/Makefile
new file mode 100644
index 000..a39ceee
--- /dev/null
+++ b/drivers/interconnect/mediatek/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+mtk-mt8183-objs:= mt8183.o
+
+obj-$(CONFIG_INTERCONNECT_MTK_MT8183) += mtk-mt8183.o
\ No newline at end of file
diff --git a/drivers/interconnect/mediatek/mt8183.c
b/drivers/interconnect/mediatek/mt8183.c
new file mode 100644
index 000..38ffe0b
--- /dev/null
+++ b/drivers/interconnect/mediatek/mt8183.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MT8183_MAX_LINKS 6
+
+/**
+ * struct mtk_icc_node - Mediatek specific interconnect nodes
+ * @name: the node name used in debugfs
+ * @ep: true if the node is an end point.
+ * @id: a unique node identifier
+ * @links: an array of nodes where we can go next while traversing
+ * @num_links: the total number of @links
+ * @buswidth: width of the interconnect between a node and the bus
+ * @sum_avg: current sum aggregate value of all avg bw requests
+ * @max_peak: current max aggregate value of all peak bw requests
+ */
+struct mtk_icc_node {
+ unsigned char *name;
+ bool ep;
+ u16 id;
+ u16 links[MT8183_MAX_LINKS];
+ u16 num_links;
+ u16 buswidth;
+ u64 sum_avg;
+ u64 max_peak;
+};
+
+struct mtk_icc_desc {
+ struct mtk_icc_node **nodes;
+ size_t num_nodes;
+};
+
+#define DEFINE_MNODE(_name, _id, _buswidth, _ep, _numlinks, ...) \
+ static struct mtk_icc_node _name = {\
+ .name = #_name, \
+ .id = _id, \
+ .buswidth = _buswidth, \
+ .ep = _ep, \
+ .num_links = _numlinks, \
+ .links = { __VA_ARGS__ }, \
+}
+
+DEFINE_MNODE(ddr_emi, SLAVE_DDR_EMI, 1024, 1, 0, 0);
+DEFINE_MNODE(mcusys, MASTER_MCUSYS, 256, 0, 1, SLAVE_DDR_EMI);
+DEFINE_MNODE(gpu, MASTER_GPU, 256, 0, 1, SLAVE_DDR_EMI);
+DEFINE_MNODE(mmsys, MASTER_MMSYS, 256, 0, 1, SLAVE_DDR_EMI);
+DEFINE_MNODE(mm_vpu, MASTER_MM_VPU, 128, 0, 1, MASTER_MMSYS);
+DEFINE_MNODE(mm_disp, MASTER_MM_DISP, 128, 0, 1, MASTER_MMSYS);
+DEFINE_MNODE(mm_vdec, MASTER_MM_VDEC, 128, 0, 1, MASTER_MMSYS);
+DEFINE_MNODE(mm_venc, MASTER_MM_VENC, 128, 0, 1, MASTER_MMSYS);
+DEFINE_MNODE(mm_cam, MASTER_MM_CAM, 128, 0, 1, MASTER_MMSYS);
+DEFINE_MNODE(mm_img, MASTER_MM_IMG, 128, 0, 1, MASTER_MMSYS);
+DEFINE_MNODE(mm_mdp, MA
[RFC V2 03/11] soc: mediatek: add support for the performance state
Support power domain performance state, add header file for scp event.
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/mtk-scpsys.c | 53 +++
drivers/soc/mediatek/mtk-scpsys.h | 22
2 files changed, 75 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-scpsys.h
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index f1d82cd..be8c948 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -10,7 +10,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
@@ -21,6 +23,7 @@
#include
#include
#include
+#include "mtk-scpsys.h"
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUTUSEC_PER_SEC
@@ -188,6 +191,18 @@ struct scp_soc_data {
bool bus_prot_reg_update;
};
+static BLOCKING_NOTIFIER_HEAD(scpsys_notifier_list);
+
+int register_scpsys_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(_notifier_list, nb);
+}
+
+int unregister_scpsys_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(_notifier_list, nb);
+}
+
static int scpsys_domain_is_on(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
@@ -519,6 +534,41 @@ static void init_clks(struct platform_device *pdev, struct
clk **clk)
clk[i] = devm_clk_get(>dev, clk_names[i]);
}
+static int mtk_pd_set_performance(struct generic_pm_domain *genpd,
+ unsigned int state)
+{
+ int i;
+ struct scp_domain *scpd =
+ container_of(genpd, struct scp_domain, genpd);
+ struct scp_event_data scpe;
+ struct scp *scp = scpd->scp;
+ struct genpd_onecell_data *pd_data = >pd_data;
+
+ for (i = 0; i < pd_data->num_domains; i++) {
+ if (genpd == pd_data->domains[i]) {
+ dev_dbg(scp->dev, "%d. %s = %d\n",
+ i, genpd->name, state);
+ break;
+ }
+ }
+
+ if (i == pd_data->num_domains)
+ return 0;
+
+ scpe.event_type = MTK_SCPSYS_PSTATE;
+ scpe.genpd = genpd;
+ scpe.domain_id = i;
+ blocking_notifier_call_chain(_notifier_list, state, );
+
+ return 0;
+}
+
+static unsigned int mtk_pd_get_performance(struct generic_pm_domain *genpd,
+ struct dev_pm_opp *opp)
+{
+ return dev_pm_opp_get_level(opp);
+}
+
static struct scp *init_scp(struct platform_device *pdev,
const struct scp_domain_data *scp_domain_data, int num,
const struct scp_ctrl_reg *scp_ctrl_reg,
@@ -642,6 +692,9 @@ static struct scp *init_scp(struct platform_device *pdev,
genpd->power_on = scpsys_power_on;
if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ACTIVE_WAKEUP))
genpd->flags |= GENPD_FLAG_ACTIVE_WAKEUP;
+
+ genpd->set_performance_state = mtk_pd_set_performance;
+ genpd->opp_to_performance_state = mtk_pd_get_performance;
}
return scp;
diff --git a/drivers/soc/mediatek/mtk-scpsys.h
b/drivers/soc/mediatek/mtk-scpsys.h
new file mode 100644
index 000..c1e8325
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ */
+
+#ifndef __MTK_SCPSYS_H__
+#define __MTK_SCPSYS_H__
+
+struct scp_event_data {
+ int event_type;
+ int domain_id;
+ struct generic_pm_domain *genpd;
+};
+
+enum scp_event_type {
+ MTK_SCPSYS_PSTATE,
+};
+
+int register_scpsys_notifier(struct notifier_block *nb);
+int unregister_scpsys_notifier(struct notifier_block *nb);
+
+#endif /* __MTK_SCPSYS_H__ */
--
1.9.1
[RFC V2 06/11] soc: mediatek: add MT8183 dvfsrc support
Add dvfsrc driver for MT8183
Signed-off-by: Henry Chen
---
drivers/soc/mediatek/Kconfig | 15 ++
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 347 ++
include/soc/mediatek/mtk_dvfsrc.h | 22 +++
4 files changed, 385 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 include/soc/mediatek/mtk_dvfsrc.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 17bd759..2721fd6 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -24,6 +24,21 @@ config MTK_INFRACFG
INFRACFG controller contains various infrastructure registers not
directly associated to any device.
+config MTK_DVFSRC
+ bool "MediaTek DVFSRC Support"
+ depends on ARCH_MEDIATEK
+ default ARCH_MEDIATEK
+ select MTK_INFRACFG
+ select PM_GENERIC_DOMAINS if PM
+ depends on MTK_SCPSYS
+ help
+ Say yes here to add support for the MediaTek DVFSRC (dynamic voltage
+ and frequency scaling resource collector) found
+ on different MediaTek SoCs. The DVFSRC is a proprietary
+ hardware which is used to collect all the requests from
+ system and turn into the decision of minimum Vcore voltage
+ and minimum DRAM frequency to fulfill those requests.
+
config MTK_PMIC_WRAP
tristate "MediaTek PMIC Wrapper Support"
depends on RESET_CONTROLLER
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b9dbad6..cd9d63f 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
+obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
b/drivers/soc/mediatek/mtk-dvfsrc.c
new file mode 100644
index 000..e54a654
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mtk-scpsys.h"
+
+#define DVFSRC_IDLE0x00
+#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
+#define DVFSRC_GET_CURRENT_LEVEL(x)(((x) >> 16) & 0x)
+
+#define MT8183_DVFSRC_OPP_LP4 0
+#define MT8183_DVFSRC_OPP_LP4X 1
+#define MT8183_DVFSRC_OPP_LP3 2
+
+struct dvfsrc_opp {
+ u32 vcore_opp;
+ u32 dram_opp;
+};
+
+struct dvfsrc_domain {
+ u32 id;
+ u32 state;
+};
+
+struct mtk_dvfsrc;
+struct dvfsrc_soc_data {
+ const int *regs;
+ u32 num_opp;
+ u32 num_domains;
+ const struct dvfsrc_opp **opps;
+ struct dvfsrc_domain *domains;
+ int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
+ int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
+ void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+ void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+};
+
+struct mtk_dvfsrc {
+ struct device *dev;
+ struct clk *clk_dvfsrc;
+ const struct dvfsrc_soc_data *dvd;
+ int dram_type;
+ void __iomem *regs;
+ struct mutex lock;
+ struct notifier_block scpsys_notifier;
+};
+
+static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
+{
+ return readl(dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
+{
+ writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+enum dvfsrc_regs {
+ DVFSRC_SW_REQ,
+ DVFSRC_LEVEL,
+ DVFSRC_SW_BW_0,
+ DVFSRC_LAST,
+};
+
+static const int mt8183_regs[] = {
+ [DVFSRC_SW_REQ] = 0x4,
+ [DVFSRC_LEVEL] =0xDC,
+ [DVFSRC_SW_BW_0] = 0x160,
+ [DVFSRC_LAST] = 0x308,
+};
+
+static bool dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc)
+{
+ if (!dvfsrc->dvd->get_target_level)
+ return true;
+
+ return dvfsrc->dvd->get_target_level(dvfsrc) == DVFSRC_IDLE;
+}
+
+static int dvfsrc_wait_for_idle(struct mtk_dvfsrc *dvfsrc)
+{
+ unsigned long timeout;
+
+ timeout = jiffies + usecs_to_jiffies(1000);
+
+ do {
+ if (dvfsrc_is_idle(dvfsrc))
+ return 0;
+ } while (!time_after(jiffies, timeout));
+
+ return -ETIMEDOUT;
+}
+
+static int mt8183_get_target_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return DVFSRC_GET_TARGET_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL));
+}
+
+static int mt8183_get_current_level(struct mtk_dvfsrc *dvfsrc)
+{
+ return ffs(DVFSRC_GET_CURRENT_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL)));
+}
+
+static vo
Re: [RFC RESEND PATCH 1/7] dt-bindings: soc: Add DVFSRC driver bindings
Hi Rob,
Sorry for late reply. I missed this mail before.
On Fri, 2019-01-11 at 10:09 -0600, Rob Herring wrote:
> On Wed, Jan 02, 2019 at 10:09:52PM +0800, Henry Chen wrote:
> > Document the binding for enabling DVFSRC on MediaTek SoC.
> >
> > Signed-off-by: Henry Chen
> > ---
> > .../devicetree/bindings/soc/mediatek/dvfsrc.txt| 26
> > ++
> > include/dt-bindings/soc/mtk,dvfsrc.h | 18 +++
> > 2 files changed, 44 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
> > create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h
> >
> > diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
> > b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
> > new file mode 100644
> > index 000..402c885
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
> > @@ -0,0 +1,26 @@
> > +MediaTek DVFSRC Driver
>
> Bindings are for h/w blocks, not drivers.
ok.
>
> > +The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
> > +HW module which is used to collect all the requests from both software and
> > +hardware and turn into the decision of minimum operating voltage and
> > minimum
> > +DRAM frequency to fulfill those requests.
>
> Seems like the OPP table should be a child of this instead of where you
> currently have it?
Do you means the opp table that I put on scpsys likes below?
I think this opp table is used for mapping the performance state of
power domain, so I put it on scpsys device tree document.
dvfsrc_opp_table: opp-table {
compatible = "operating-points-v2-level";
dvfsrc_vol_min: opp1 {
opp,level = ;
};
dvfsrc_freq_medium: opp2 {
opp,level = ;
};
dvfsrc_freq_max: opp3 {
opp,level = ;
};
dvfsrc_vol_max: opp4 {
opp,level = ;
};
};
>
> > +
> > +Required Properties:
> > +- compatible: Should be one of the following
> > + - "mediatek,mt8183-dvfsrc": For MT8183 SoC
> > +- reg: Address range of the DVFSRC unit
> > +- dram_type: Refer to for the
> > + different dram type support.
>
> This information should come from the DDR controller or memory nodes
> probably. And we already have some properties related to DDR type.
Sorry, I don't know that before, could you give some hint or example for
that?
>
> > +- clock-names: Must include the following entries:
> > + "dvfsrc": DVFSRC module clock
> > +- clocks: Must contain an entry for each entry in clock-names.
> > +
> > +Example:
> > +
> > + dvfsrc_top@10012000 {
>
> Drop the '_top'. (Don't use '_' in node and property names)..
ok
>
> > + compatible = "mediatek,mt8183-dvfsrc";
> > + reg = <0 0x10012000 0 0x1000>;
> > + clocks = < CLK_INFRA_DVFSRC>;
> > + clock-names = "dvfsrc";
> > + dram_type = ;
> > + };
> > diff --git a/include/dt-bindings/soc/mtk,dvfsrc.h
> > b/include/dt-bindings/soc/mtk,dvfsrc.h
> > new file mode 100644
> > index 000..60b3497
> > --- /dev/null
> > +++ b/include/dt-bindings/soc/mtk,dvfsrc.h
> > @@ -0,0 +1,18 @@
> > +/* SPDX-License-Identifier: GPL-2.0
> > + *
> > + * Copyright (c) 2018 MediaTek Inc.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_POWER_MTK_DVFSRC_H
> > +#define _DT_BINDINGS_POWER_MTK_DVFSRC_H
> > +
> > +#define MT8183_DVFSRC_OPP_LP4 0
> > +#define MT8183_DVFSRC_OPP_LP4X 1
> > +#define MT8183_DVFSRC_OPP_LP3 2
> > +
> > +#define MT8183_DVFSRC_LEVEL_1 1
> > +#define MT8183_DVFSRC_LEVEL_2 2
> > +#define MT8183_DVFSRC_LEVEL_3 3
> > +#define MT8183_DVFSRC_LEVEL_4 4
> > +
> > +#endif /* _DT_BINDINGS_POWER_MTK_DVFSRC_H */
> > --
> > 1.9.1
> >
>
> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Re: [RFC RESEND PATCH 0/7] Add driver for dvfsrc and add support for active state of scpsys on mt8183
On Mon, 2019-01-07 at 18:34 +0200, Georgi Djakov wrote: > Hi Henry, > > On 1/7/19 13:04, Henry Chen wrote: > > On Thu, 2019-01-03 at 14:53 -0800, Stephen Boyd wrote: > >> Quoting Henry Chen (2019-01-02 06:09:51) > >>> The patchsets add support for MediaTek hardware module named DVFSRC > >>> (dynamic voltage and frequency scaling resource collector). The DVFSRC is > >>> a HW module which is used to collect all the requests from both software > >>> and hardware and turn into the decision of minimum operating voltage and > >>> minimum DRAM frequency to fulfill those requests. > >>> > >>> So, This series is to implement the dvfsrc driver to collect all the > >>> requests of operating voltage or DRAM bandwidth from other device drivers > >>> likes GPU/Camera through 2 frameworks basically: > >>> > >>> 1. PM_QOS_MEMORY_BANDWIDTH from PM QOS: to aggregate the bandwidth > >>>requirements from different clients > >> > >> Have you looked at using the interconnect framework for this instead of > >> using PM_QOS_MEMORY_BANDWIDTH? Qcom is pushing an interconnect framework > >> to do DRAM bandwidth requirement aggregation. > > > > Sorry, I haven't heard that before. Do you mean is following series > > patch? > > https://patchwork.kernel.org/project/linux-arm-msm/list/?series=53775 > > > > Yes, this one. The idea is that consumer drivers like GPU, camera, video > encoder etc. report their bandwidth needs by using the interconnect API. > The framework does the aggregation and configures the hardware. In order > to use it you need to implement a platform-specific dvfsrc interconnect > provider driver that understands the SoC topology and knows how to > configure the hardware. I am not familiar with DVFSRC, but it seems to > me that it can fit as interconnect provider. > Does this HW module support any QoS priority/latency configuration or is > it only bandwidth and voltage? > > Thanks, > Georgi Hi Georgi, Yes, the design is only to support bandwidth and voltage. The one of the function is to collect the memory bandwidth requirement from consumer and select the minimum DRAM frequency to fulfill system performance.It just get the total bandwidth then set it to HW, not involves complex SoC topology. So we choose to use PM QOS to model that DVFSRC driver can receive the bandwidth information from consumer driver via PM_QOS_MEMORY_BANDWIDTH. Do you have a patch that show how consumer driver used interconnect to update their requirement. Thanks, Henry
Re: [RFC RESEND PATCH 6/7] soc: mediatek: add MT8183 dvfsrc support
On Fri, 2019-01-04 at 07:08 +0800, Stephen Boyd wrote:
> Quoting Henry Chen (2019-01-02 06:09:57)
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index a7d0667..f956f03 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -12,6 +12,21 @@ config MTK_INFRACFG
> > INFRACFG controller contains various infrastructure registers not
> > directly associated to any device.
> >
> > +config MTK_DVFSRC
> > + bool "MediaTek DVFSRC Support"
> > + depends on ARCH_MEDIATEK
> > + default ARCH_MEDIATEK
> > + select REGMAP
>
> Why?
Sorry, no need, will remove.
>
> > + select MTK_INFRACFG
> > + select PM_GENERIC_DOMAINS if PM
>
> It doesn't depend on it?
Because MTK_SCPSYS includes MTK_INFRACFG/PM_GENERIC_DOMAINS.Should I
remove these two config?
>
> > + depends on MTK_SCPSYS
> > + help
> > + Say yes here to add support for the MediaTek DVFSRC found
>
> Maybe you can spell out what the DVFSRC acronym means?
ok.
>
> > + on different MediaTek SoCs. The DVFSRC is a proprietary
> > + hardware which is used to collect all the requests from
> > + system and turn into the decision of minimum Vcore voltage
> > + and minimum DRAM frequency to fulfill those requests.
> > +
> > config MTK_PMIC_WRAP
> > tristate "MediaTek PMIC Wrapper Support"
> > depends on RESET_CONTROLLER
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index 9dc6670..5c010b9 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
> > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
> > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
> > b/drivers/soc/mediatek/mtk-dvfsrc.c
> > new file mode 100644
> > index 000..af462a3
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mtk-dvfsrc.c
> > @@ -0,0 +1,473 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2018 MediaTek Inc.
> > + */
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> Presumably both interrupt.h and irq.h aren't needed.
ok
>
> > +#include
> > +#include
>
> Is this used?
No, will remove.
>
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> Is this used?
No, will remove.
>
> > +#include
> > +#include
> > +#include
> > +#include "mtk-scpsys.h"
> > +
> > +#define DVFSRC_IDLE0x00
> > +#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x)
> > +#define DVFSRC_GET_CURRENT_LEVEL(x)(((x) >> 16) & 0x)
> > +
> > +/* macro for irq */
> > +#define DVFSRC_IRQ_TIMEOUT_EN BIT(1)
> > +
> > +struct dvfsrc_opp {
> > + int vcore_opp;
> > + int dram_opp;
> > +};
> > +
> > +struct dvfsrc_domain {
> > + int id;
> > + int state;
>
> Does id or state need to be signed? Perhaps unsigned or u32 is better?
Yes. I think u32 is better.
>
> > +};
> > +
> > +struct mtk_dvfsrc;
> > +struct dvfsrc_soc_data {
> > + const int *regs;
> > + int num_opp;
> > + int num_domains;
> > + int dram_sft;
> > + int vcore_sft;
> > + const struct dvfsrc_opp **opps;
> > + struct dvfsrc_domain *domains;
> > + void (*init_soc)(struct mtk_dvfsrc *dvfsrc);
> > + int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
> > + int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
> > +};
> > +
> > +struct mtk_dvfsrc {
> > + struct device *dev;
> > + struct clk *clk_dvfsrc;
> > + const struct dvfsrc_soc_data *dvd;
> > + int dram_type;
> > + int irq;
> > + void __iomem *regs;
> > + struct mutex lock; /* generic mutex for dvfsrc driver */
>
> That's not a very useful comment. Please make it useful or remove it.
ok
>
> > +
> > + struct notifier_block qos_notifier;
> > + struct notifier_block scpsys_notifier;
> > +};
> > +
> > +static u32 dvfsrc_read(s
