[PATCH v4 2/3] net/phy: micrel: Comment MMD address of extended registers

2015-06-05 Thread Jaeden Amero
There are some defines for a few pad skew related extended registers.
Specify for which MMD Address (dev_addr) they are for.

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 59cc5d4..f23765e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,7 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
-- 
2.1.4

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[PATCH v4 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.

>From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
"Auto-Negotiation Timing":
The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
Standard specifies this timing to be 16ms +/-8ms. Some PHY link
partners need to receive the FLP with 16ms centered timing;
otherwise, there can be intermittent link failures and long
link-up times.

The PHY data sheet recommends configuring the FLP burst registers after
power-up/reset and immediately thereafter restarting auto-negotiation, so
we center the FLP timing at 16ms and then restart auto-negotiation in the
config_init for KSZ9031.

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index f23765e..499185e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO  3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI  4
+
 /* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
@@ -427,6 +431,22 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 }
 
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+   int result;
+
+   /* Center KSZ9031RNX FLP timing at 16ms. */
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+   if (result)
+   return result;
+
+   return genphy_restart_aneg(phydev);
+}
+
 static int ksz9031_config_init(struct phy_device *phydev)
 {
const struct device *dev = >dev;
@@ -462,7 +482,8 @@ static int ksz9031_config_init(struct phy_device *phydev)
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
tx_data_skews, 4);
}
-   return 0;
+
+   return ksz9031_center_flp_timing(phydev);
 }
 
 #define KSZ8873MLL_GLOBAL_CONTROL_40x06
-- 
2.1.4

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[PATCH v4 1/3] net/phy: micrel: Be more const correct

2015-06-05 Thread Jaeden Amero
In a few places in this driver, we weren't using const where we could
have. Use const more.

In addition, change the arrays of strings in ksz9031_config_init() to be
not only const, but also static.

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 29 +++--
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ebdc357..59cc5d4 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -288,9 +288,10 @@ static int kszphy_config_init(struct phy_device *phydev)
 }
 
 static int ksz9021_load_values_from_of(struct phy_device *phydev,
-  struct device_node *of_node, u16 reg,
-  char *field1, char *field2,
-  char *field3, char *field4)
+  const struct device_node *of_node,
+  u16 reg,
+  const char *field1, const char *field2,
+  const char *field3, const char *field4)
 {
int val1 = -1;
int val2 = -2;
@@ -336,8 +337,8 @@ static int ksz9021_load_values_from_of(struct phy_device 
*phydev,
 
 static int ksz9021_config_init(struct phy_device *phydev)
 {
-   struct device *dev = >dev;
-   struct device_node *of_node = dev->of_node;
+   const struct device *dev = >dev;
+   const struct device_node *of_node = dev->of_node;
 
if (!of_node && dev->parent->of_node)
of_node = dev->parent->of_node;
@@ -389,9 +390,9 @@ static int ksz9031_extended_read(struct phy_device *phydev,
 }
 
 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
-  struct device_node *of_node,
+  const struct device_node *of_node,
   u16 reg, size_t field_sz,
-  char *field[], u8 numfields)
+  const char *field[], u8 numfields)
 {
int val[4] = {-1, -2, -3, -4};
int matches = 0;
@@ -427,18 +428,18 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
 
 static int ksz9031_config_init(struct phy_device *phydev)
 {
-   struct device *dev = >dev;
-   struct device_node *of_node = dev->of_node;
-   char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
-   char *rx_data_skews[4] = {
+   const struct device *dev = >dev;
+   const struct device_node *of_node = dev->of_node;
+   static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
+   static const char *rx_data_skews[4] = {
"rxd0-skew-ps", "rxd1-skew-ps",
"rxd2-skew-ps", "rxd3-skew-ps"
};
-   char *tx_data_skews[4] = {
+   static const char *tx_data_skews[4] = {
"txd0-skew-ps", "txd1-skew-ps",
"txd2-skew-ps", "txd3-skew-ps"
};
-   char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
+   static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 
if (!of_node && dev->parent->of_node)
of_node = dev->parent->of_node;
@@ -519,7 +520,7 @@ ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, 
int devnum,
 static int kszphy_probe(struct phy_device *phydev)
 {
const struct kszphy_type *type = phydev->drv->driver_data;
-   struct device_node *np = phydev->dev.of_node;
+   const struct device_node *np = phydev->dev.of_node;
struct kszphy_priv *priv;
struct clk *clk;
int ret;
-- 
2.1.4

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[PATCH v4 0/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
In v2, we add an additional cleanup commit to make an array of strings
static const and to improve const correctness generally. We also no longer
unnecessarily initialize the result variable in
ksz9031_center_flp_timing().

In v3, we remove the unnecessary result variable from ksz9031_config_init()
introduced by a previous version of "net/phy: micrel: Center FLP timing at
16ms".

In v4, we modify the commit message of "net/phy: micrel: Center FLP timing
at 16ms" to replace the awkward quotation of the data sheet's programming
procedure with an explanation of why we program the FLP burst registers and
restart auto-negotiation where we do (config_init).

Jaeden Amero (3):
  net/phy: micrel: Be more const correct
  net/phy: micrel: Comment MMD address of extended registers
  net/phy: micrel: Center FLP timing at 16ms

 drivers/net/phy/micrel.c | 53 ++--
 1 file changed, 38 insertions(+), 15 deletions(-)

-- 
2.1.4

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Re: [PATCH v3 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
On 06/05/2015 05:43 PM, Florian Fainelli wrote:
> On 05/06/15 15:40, Jaeden Amero wrote:
>> Link failures have been observed when using the KSZ9031 with HP 1810-8G
>> and HP 1910-8G network switches. Center the FLP timing at 16ms to help
>> avoid intermittent link failures.
>>
>> From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
>> "Auto-Negotiation Timing":
>>  The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
>>  transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
>>  Standard specifies this timing to be 16ms +/-8ms. Some PHY link
>>  partners need to receive the FLP with 16ms centered timing;
>>  otherwise, there can be intermittent link failures and long
>>  link-up times.
>>
>>  After KSZ9031[RNX or MNX] power-up/reset, program the following
>>  register sequence to set the FLP timing to 16ms
>>
>>  Write Register Dh = 0x // Set up register address for MMD – Device 
>> Address 0h
>>  Write Register Eh = 0x0004 // Select Register 4h of MMD – Device 
>> Address 0h
>>  Write Register Dh = 0x4000 // Select register data for MMD – Device 
>> Address 0h, Register 4h
>>  Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device 
>> Address 0h, Register 4h
>>  Write Register Dh = 0x // Set up register address for MMD – Device 
>> Address 0h
>>  Write Register Eh = 0x0003 // Select Register 3h of MMD – Device 
>> Address 0h
>>  Write Register Dh = 0x4000 // Select register data for MMD – Device 
>> Address 0h, Register 3h
>>  Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device 
>> Address 0h, Register 3h
>>  Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation
> 
> Quoting a portion of the data-sheet on how to do this programming is
> very strange considering that the code is going to be the reference, not
> the commit message.

I included it for lack of something better to quote that explained
which values to set when. I'd be happy to revise the message as this
appears too strange.

> Other than that, this looks reasonable.

Thanks very much for the review.

Cheers,
Jaeden
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[PATCH v3 1/3] net/phy: micrel: Be more const correct

2015-06-05 Thread Jaeden Amero
In a few places in this driver, we weren't using const where we could
have. Use const more.

In addition, change the arrays of strings in ksz9031_config_init() to be
not only const, but also static.

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 29 +++--
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ebdc357..59cc5d4 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -288,9 +288,10 @@ static int kszphy_config_init(struct phy_device *phydev)
 }
 
 static int ksz9021_load_values_from_of(struct phy_device *phydev,
-  struct device_node *of_node, u16 reg,
-  char *field1, char *field2,
-  char *field3, char *field4)
+  const struct device_node *of_node,
+  u16 reg,
+  const char *field1, const char *field2,
+  const char *field3, const char *field4)
 {
int val1 = -1;
int val2 = -2;
@@ -336,8 +337,8 @@ static int ksz9021_load_values_from_of(struct phy_device 
*phydev,
 
 static int ksz9021_config_init(struct phy_device *phydev)
 {
-   struct device *dev = >dev;
-   struct device_node *of_node = dev->of_node;
+   const struct device *dev = >dev;
+   const struct device_node *of_node = dev->of_node;
 
if (!of_node && dev->parent->of_node)
of_node = dev->parent->of_node;
@@ -389,9 +390,9 @@ static int ksz9031_extended_read(struct phy_device *phydev,
 }
 
 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
-  struct device_node *of_node,
+  const struct device_node *of_node,
   u16 reg, size_t field_sz,
-  char *field[], u8 numfields)
+  const char *field[], u8 numfields)
 {
int val[4] = {-1, -2, -3, -4};
int matches = 0;
@@ -427,18 +428,18 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
 
 static int ksz9031_config_init(struct phy_device *phydev)
 {
-   struct device *dev = >dev;
-   struct device_node *of_node = dev->of_node;
-   char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
-   char *rx_data_skews[4] = {
+   const struct device *dev = >dev;
+   const struct device_node *of_node = dev->of_node;
+   static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
+   static const char *rx_data_skews[4] = {
"rxd0-skew-ps", "rxd1-skew-ps",
"rxd2-skew-ps", "rxd3-skew-ps"
};
-   char *tx_data_skews[4] = {
+   static const char *tx_data_skews[4] = {
"txd0-skew-ps", "txd1-skew-ps",
"txd2-skew-ps", "txd3-skew-ps"
};
-   char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
+   static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 
if (!of_node && dev->parent->of_node)
of_node = dev->parent->of_node;
@@ -519,7 +520,7 @@ ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, 
int devnum,
 static int kszphy_probe(struct phy_device *phydev)
 {
const struct kszphy_type *type = phydev->drv->driver_data;
-   struct device_node *np = phydev->dev.of_node;
+   const struct device_node *np = phydev->dev.of_node;
struct kszphy_priv *priv;
struct clk *clk;
int ret;
-- 
2.1.4

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[PATCH v3 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.

>From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
"Auto-Negotiation Timing":
The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
Standard specifies this timing to be 16ms +/-8ms. Some PHY link
partners need to receive the FLP with 16ms centered timing;
otherwise, there can be intermittent link failures and long
link-up times.

After KSZ9031[RNX or MNX] power-up/reset, program the following
register sequence to set the FLP timing to 16ms

Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0004 // Select Register 4h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 4h
Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device 
Address 0h, Register 4h
Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0003 // Select Register 3h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 3h
Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device 
Address 0h, Register 3h
Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index f23765e..499185e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO  3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI  4
+
 /* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
@@ -427,6 +431,22 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 }
 
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+   int result;
+
+   /* Center KSZ9031RNX FLP timing at 16ms. */
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+   if (result)
+   return result;
+
+   return genphy_restart_aneg(phydev);
+}
+
 static int ksz9031_config_init(struct phy_device *phydev)
 {
const struct device *dev = >dev;
@@ -462,7 +482,8 @@ static int ksz9031_config_init(struct phy_device *phydev)
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
tx_data_skews, 4);
}
-   return 0;
+
+   return ksz9031_center_flp_timing(phydev);
 }
 
 #define KSZ8873MLL_GLOBAL_CONTROL_40x06
-- 
2.1.4

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[PATCH v3 2/3] net/phy: micrel: Comment MMD address of extended registers

2015-06-05 Thread Jaeden Amero
There are some defines for a few pad skew related extended registers.
Specify for which MMD Address (dev_addr) they are for.

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 59cc5d4..f23765e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,7 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
-- 
2.1.4

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[PATCH v3 0/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
In v2, we add an additional cleanup commit to make an array of strings
static const and to improve const correctness generally. We also no longer
unnecessarily initialize the result variable in
ksz9031_center_flp_timing().

In v3, we remove the unnecessary result variable from ksz9031_config_init()
introduced by a previous version of "net/phy: micrel: Center FLP timing at
16ms".

Jaeden Amero (3):
  net/phy: micrel: Be more const correct
  net/phy: micrel: Comment MMD address of extended registers
  net/phy: micrel: Center FLP timing at 16ms

 drivers/net/phy/micrel.c | 53 ++--
 1 file changed, 38 insertions(+), 15 deletions(-)

-- 
2.1.4

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Re: [PATCH v2 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
On 06/05/2015 04:09 PM, Sergei Shtylyov wrote:
>> @@ -441,6 +461,7 @@ static int ksz9031_config_init(struct phy_device
>> *phydev)
>>   "txd2-skew-ps", "txd3-skew-ps"
>>   };
>>   static const char *control_skews[2] = {"txen-skew-ps",
>> "rxdv-skew-ps"};
>> +int result;
> 
>You hardly need this variable...
> 
>>
>>   if (!of_node && dev->parent->of_node)
>>   of_node = dev->parent->of_node;
>> @@ -462,7 +483,10 @@ static int ksz9031_config_init(struct phy_device
>> *phydev)
>>   MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
>>   tx_data_skews, 4);
>>   }
>> -return 0;
>> +
>> +result = ksz9031_center_flp_timing(phydev);
>> +
>> +return result;
> 
>Why not just return directly?
> 

Genius.

Thanks for the feedback. I'll post a v3.
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[PATCH v2 1/3] net/phy: micrel: Be more const correct

2015-06-05 Thread Jaeden Amero
In a few places in this driver, we weren't using const where we could
have. Use const more.

In addition, change the arrays of strings in ksz9031_config_init() to be
not only const, but also static.

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 29 +++--
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ebdc357..59cc5d4 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -288,9 +288,10 @@ static int kszphy_config_init(struct phy_device *phydev)
 }
 
 static int ksz9021_load_values_from_of(struct phy_device *phydev,
-  struct device_node *of_node, u16 reg,
-  char *field1, char *field2,
-  char *field3, char *field4)
+  const struct device_node *of_node,
+  u16 reg,
+  const char *field1, const char *field2,
+  const char *field3, const char *field4)
 {
int val1 = -1;
int val2 = -2;
@@ -336,8 +337,8 @@ static int ksz9021_load_values_from_of(struct phy_device 
*phydev,
 
 static int ksz9021_config_init(struct phy_device *phydev)
 {
-   struct device *dev = >dev;
-   struct device_node *of_node = dev->of_node;
+   const struct device *dev = >dev;
+   const struct device_node *of_node = dev->of_node;
 
if (!of_node && dev->parent->of_node)
of_node = dev->parent->of_node;
@@ -389,9 +390,9 @@ static int ksz9031_extended_read(struct phy_device *phydev,
 }
 
 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
-  struct device_node *of_node,
+  const struct device_node *of_node,
   u16 reg, size_t field_sz,
-  char *field[], u8 numfields)
+  const char *field[], u8 numfields)
 {
int val[4] = {-1, -2, -3, -4};
int matches = 0;
@@ -427,18 +428,18 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
 
 static int ksz9031_config_init(struct phy_device *phydev)
 {
-   struct device *dev = >dev;
-   struct device_node *of_node = dev->of_node;
-   char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
-   char *rx_data_skews[4] = {
+   const struct device *dev = >dev;
+   const struct device_node *of_node = dev->of_node;
+   static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
+   static const char *rx_data_skews[4] = {
"rxd0-skew-ps", "rxd1-skew-ps",
"rxd2-skew-ps", "rxd3-skew-ps"
};
-   char *tx_data_skews[4] = {
+   static const char *tx_data_skews[4] = {
"txd0-skew-ps", "txd1-skew-ps",
"txd2-skew-ps", "txd3-skew-ps"
};
-   char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
+   static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 
if (!of_node && dev->parent->of_node)
of_node = dev->parent->of_node;
@@ -519,7 +520,7 @@ ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, 
int devnum,
 static int kszphy_probe(struct phy_device *phydev)
 {
const struct kszphy_type *type = phydev->drv->driver_data;
-   struct device_node *np = phydev->dev.of_node;
+   const struct device_node *np = phydev->dev.of_node;
struct kszphy_priv *priv;
struct clk *clk;
int ret;
-- 
2.1.4

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[PATCH v2 2/3] net/phy: micrel: Comment MMD address of extended registers

2015-06-05 Thread Jaeden Amero
There are some defines for a few pad skew related extended registers.
Specify for which MMD Address (dev_addr) they are for.

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 59cc5d4..f23765e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,7 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
-- 
2.1.4

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[PATCH v2 0/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
In v2, we add an additional cleanup commit to make an array of strings
static const and to improve const correctness generally. We also no longer
unnecessarily initialize the result variable in
ksz9031_center_flp_timing().

Jaeden Amero (3):
  net/phy: micrel: Be more const correct
  net/phy: micrel: Comment MMD address of extended registers
  net/phy: micrel: Center FLP timing at 16ms

 drivers/net/phy/micrel.c | 56 +++-
 1 file changed, 41 insertions(+), 15 deletions(-)

-- 
2.1.4

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[PATCH v2 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.

>From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
"Auto-Negotiation Timing":
The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
Standard specifies this timing to be 16ms +/-8ms. Some PHY link
partners need to receive the FLP with 16ms centered timing;
otherwise, there can be intermittent link failures and long
link-up times.

After KSZ9031[RNX or MNX] power-up/reset, program the following
register sequence to set the FLP timing to 16ms

Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0004 // Select Register 4h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 4h
Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device 
Address 0h, Register 4h
Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0003 // Select Register 3h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 3h
Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device 
Address 0h, Register 3h
Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index f23765e..e156e36 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO  3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI  4
+
 /* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
@@ -427,6 +431,22 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 }
 
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+   int result;
+
+   /* Center KSZ9031RNX FLP timing at 16ms. */
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+   if (result)
+   return result;
+
+   return genphy_restart_aneg(phydev);
+}
+
 static int ksz9031_config_init(struct phy_device *phydev)
 {
const struct device *dev = >dev;
@@ -441,6 +461,7 @@ static int ksz9031_config_init(struct phy_device *phydev)
"txd2-skew-ps", "txd3-skew-ps"
};
static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
+   int result;
 
if (!of_node && dev->parent->of_node)
of_node = dev->parent->of_node;
@@ -462,7 +483,10 @@ static int ksz9031_config_init(struct phy_device *phydev)
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
tx_data_skews, 4);
}
-   return 0;
+
+   result = ksz9031_center_flp_timing(phydev);
+
+   return result;
 }
 
 #define KSZ8873MLL_GLOBAL_CONTROL_40x06
-- 
2.1.4

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Re: [PATCH 2/2] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Please disregard this patch set. I'll post a second version.

Cheers,
Jaeden
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[PATCH 2/2] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.

>From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
"Auto-Negotiation Timing":
The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
Standard specifies this timing to be 16ms +/-8ms. Some PHY link
partners need to receive the FLP with 16ms centered timing;
otherwise, there can be intermittent link failures and long
link-up times.

After KSZ9031[RNX or MNX] power-up/reset, program the following
register sequence to set the FLP timing to 16ms

Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0004 // Select Register 4h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 4h
Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device 
Address 0h, Register 4h
Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0003 // Select Register 3h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 3h
Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device 
Address 0h, Register 3h
Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 41a2e02..47eb5df 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -365,6 +365,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO  3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI  4
+
 /* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
@@ -426,8 +430,25 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 }
 
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+   int result = 0;
+
+   /* Center KSZ9031RNX FLP timing at 16ms. */
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+   if (result)
+   return result;
+
+   return genphy_restart_aneg(phydev);
+}
+
 static int ksz9031_config_init(struct phy_device *phydev)
 {
+   int result;
struct device *dev = >dev;
struct device_node *of_node = dev->of_node;
char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
@@ -461,7 +482,10 @@ static int ksz9031_config_init(struct phy_device *phydev)
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
tx_data_skews, 4);
}
-   return 0;
+
+   result = ksz9031_center_flp_timing(phydev);
+
+   return result;
 }
 
 #define KSZ8873MLL_GLOBAL_CONTROL_40x06
-- 
2.1.4

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[PATCH 1/2] net/phy: micrel: Comment MMD address of extended registers

2015-06-05 Thread Jaeden Amero
There are some defines for a few pad skew related extended registers.
Specify for which MMD Address (dev_addr) they are for.

Signed-off-by: Jaeden Amero 
---
 drivers/net/phy/micrel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ebdc357..41a2e02 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -365,6 +365,7 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
-- 
2.1.4

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[PATCH 2/2] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.

From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
Auto-Negotiation Timing:
The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
Standard specifies this timing to be 16ms +/-8ms. Some PHY link
partners need to receive the FLP with 16ms centered timing;
otherwise, there can be intermittent link failures and long
link-up times.

After KSZ9031[RNX or MNX] power-up/reset, program the following
register sequence to set the FLP timing to 16ms

Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0004 // Select Register 4h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 4h
Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device 
Address 0h, Register 4h
Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0003 // Select Register 3h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 3h
Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device 
Address 0h, Register 3h
Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 41a2e02..47eb5df 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -365,6 +365,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO  3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI  4
+
 /* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
@@ -426,8 +430,25 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 }
 
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+   int result = 0;
+
+   /* Center KSZ9031RNX FLP timing at 16ms. */
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+   if (result)
+   return result;
+
+   return genphy_restart_aneg(phydev);
+}
+
 static int ksz9031_config_init(struct phy_device *phydev)
 {
+   int result;
struct device *dev = phydev-dev;
struct device_node *of_node = dev-of_node;
char *clk_skews[2] = {rxc-skew-ps, txc-skew-ps};
@@ -461,7 +482,10 @@ static int ksz9031_config_init(struct phy_device *phydev)
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
tx_data_skews, 4);
}
-   return 0;
+
+   result = ksz9031_center_flp_timing(phydev);
+
+   return result;
 }
 
 #define KSZ8873MLL_GLOBAL_CONTROL_40x06
-- 
2.1.4

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[PATCH 1/2] net/phy: micrel: Comment MMD address of extended registers

2015-06-05 Thread Jaeden Amero
There are some defines for a few pad skew related extended registers.
Specify for which MMD Address (dev_addr) they are for.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ebdc357..41a2e02 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -365,6 +365,7 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
-- 
2.1.4

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[PATCH v2 2/3] net/phy: micrel: Comment MMD address of extended registers

2015-06-05 Thread Jaeden Amero
There are some defines for a few pad skew related extended registers.
Specify for which MMD Address (dev_addr) they are for.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 59cc5d4..f23765e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,7 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
-- 
2.1.4

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[PATCH v2 1/3] net/phy: micrel: Be more const correct

2015-06-05 Thread Jaeden Amero
In a few places in this driver, we weren't using const where we could
have. Use const more.

In addition, change the arrays of strings in ksz9031_config_init() to be
not only const, but also static.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 29 +++--
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ebdc357..59cc5d4 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -288,9 +288,10 @@ static int kszphy_config_init(struct phy_device *phydev)
 }
 
 static int ksz9021_load_values_from_of(struct phy_device *phydev,
-  struct device_node *of_node, u16 reg,
-  char *field1, char *field2,
-  char *field3, char *field4)
+  const struct device_node *of_node,
+  u16 reg,
+  const char *field1, const char *field2,
+  const char *field3, const char *field4)
 {
int val1 = -1;
int val2 = -2;
@@ -336,8 +337,8 @@ static int ksz9021_load_values_from_of(struct phy_device 
*phydev,
 
 static int ksz9021_config_init(struct phy_device *phydev)
 {
-   struct device *dev = phydev-dev;
-   struct device_node *of_node = dev-of_node;
+   const struct device *dev = phydev-dev;
+   const struct device_node *of_node = dev-of_node;
 
if (!of_node  dev-parent-of_node)
of_node = dev-parent-of_node;
@@ -389,9 +390,9 @@ static int ksz9031_extended_read(struct phy_device *phydev,
 }
 
 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
-  struct device_node *of_node,
+  const struct device_node *of_node,
   u16 reg, size_t field_sz,
-  char *field[], u8 numfields)
+  const char *field[], u8 numfields)
 {
int val[4] = {-1, -2, -3, -4};
int matches = 0;
@@ -427,18 +428,18 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
 
 static int ksz9031_config_init(struct phy_device *phydev)
 {
-   struct device *dev = phydev-dev;
-   struct device_node *of_node = dev-of_node;
-   char *clk_skews[2] = {rxc-skew-ps, txc-skew-ps};
-   char *rx_data_skews[4] = {
+   const struct device *dev = phydev-dev;
+   const struct device_node *of_node = dev-of_node;
+   static const char *clk_skews[2] = {rxc-skew-ps, txc-skew-ps};
+   static const char *rx_data_skews[4] = {
rxd0-skew-ps, rxd1-skew-ps,
rxd2-skew-ps, rxd3-skew-ps
};
-   char *tx_data_skews[4] = {
+   static const char *tx_data_skews[4] = {
txd0-skew-ps, txd1-skew-ps,
txd2-skew-ps, txd3-skew-ps
};
-   char *control_skews[2] = {txen-skew-ps, rxdv-skew-ps};
+   static const char *control_skews[2] = {txen-skew-ps, rxdv-skew-ps};
 
if (!of_node  dev-parent-of_node)
of_node = dev-parent-of_node;
@@ -519,7 +520,7 @@ ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, 
int devnum,
 static int kszphy_probe(struct phy_device *phydev)
 {
const struct kszphy_type *type = phydev-drv-driver_data;
-   struct device_node *np = phydev-dev.of_node;
+   const struct device_node *np = phydev-dev.of_node;
struct kszphy_priv *priv;
struct clk *clk;
int ret;
-- 
2.1.4

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[PATCH v2 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.

From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
Auto-Negotiation Timing:
The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
Standard specifies this timing to be 16ms +/-8ms. Some PHY link
partners need to receive the FLP with 16ms centered timing;
otherwise, there can be intermittent link failures and long
link-up times.

After KSZ9031[RNX or MNX] power-up/reset, program the following
register sequence to set the FLP timing to 16ms

Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0004 // Select Register 4h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 4h
Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device 
Address 0h, Register 4h
Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0003 // Select Register 3h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 3h
Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device 
Address 0h, Register 3h
Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index f23765e..e156e36 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO  3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI  4
+
 /* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
@@ -427,6 +431,22 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 }
 
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+   int result;
+
+   /* Center KSZ9031RNX FLP timing at 16ms. */
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+   if (result)
+   return result;
+
+   return genphy_restart_aneg(phydev);
+}
+
 static int ksz9031_config_init(struct phy_device *phydev)
 {
const struct device *dev = phydev-dev;
@@ -441,6 +461,7 @@ static int ksz9031_config_init(struct phy_device *phydev)
txd2-skew-ps, txd3-skew-ps
};
static const char *control_skews[2] = {txen-skew-ps, rxdv-skew-ps};
+   int result;
 
if (!of_node  dev-parent-of_node)
of_node = dev-parent-of_node;
@@ -462,7 +483,10 @@ static int ksz9031_config_init(struct phy_device *phydev)
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
tx_data_skews, 4);
}
-   return 0;
+
+   result = ksz9031_center_flp_timing(phydev);
+
+   return result;
 }
 
 #define KSZ8873MLL_GLOBAL_CONTROL_40x06
-- 
2.1.4

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[PATCH v2 0/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
In v2, we add an additional cleanup commit to make an array of strings
static const and to improve const correctness generally. We also no longer
unnecessarily initialize the result variable in
ksz9031_center_flp_timing().

Jaeden Amero (3):
  net/phy: micrel: Be more const correct
  net/phy: micrel: Comment MMD address of extended registers
  net/phy: micrel: Center FLP timing at 16ms

 drivers/net/phy/micrel.c | 56 +++-
 1 file changed, 41 insertions(+), 15 deletions(-)

-- 
2.1.4

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Re: [PATCH 2/2] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Please disregard this patch set. I'll post a second version.

Cheers,
Jaeden
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[PATCH v3 1/3] net/phy: micrel: Be more const correct

2015-06-05 Thread Jaeden Amero
In a few places in this driver, we weren't using const where we could
have. Use const more.

In addition, change the arrays of strings in ksz9031_config_init() to be
not only const, but also static.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 29 +++--
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ebdc357..59cc5d4 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -288,9 +288,10 @@ static int kszphy_config_init(struct phy_device *phydev)
 }
 
 static int ksz9021_load_values_from_of(struct phy_device *phydev,
-  struct device_node *of_node, u16 reg,
-  char *field1, char *field2,
-  char *field3, char *field4)
+  const struct device_node *of_node,
+  u16 reg,
+  const char *field1, const char *field2,
+  const char *field3, const char *field4)
 {
int val1 = -1;
int val2 = -2;
@@ -336,8 +337,8 @@ static int ksz9021_load_values_from_of(struct phy_device 
*phydev,
 
 static int ksz9021_config_init(struct phy_device *phydev)
 {
-   struct device *dev = phydev-dev;
-   struct device_node *of_node = dev-of_node;
+   const struct device *dev = phydev-dev;
+   const struct device_node *of_node = dev-of_node;
 
if (!of_node  dev-parent-of_node)
of_node = dev-parent-of_node;
@@ -389,9 +390,9 @@ static int ksz9031_extended_read(struct phy_device *phydev,
 }
 
 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
-  struct device_node *of_node,
+  const struct device_node *of_node,
   u16 reg, size_t field_sz,
-  char *field[], u8 numfields)
+  const char *field[], u8 numfields)
 {
int val[4] = {-1, -2, -3, -4};
int matches = 0;
@@ -427,18 +428,18 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
 
 static int ksz9031_config_init(struct phy_device *phydev)
 {
-   struct device *dev = phydev-dev;
-   struct device_node *of_node = dev-of_node;
-   char *clk_skews[2] = {rxc-skew-ps, txc-skew-ps};
-   char *rx_data_skews[4] = {
+   const struct device *dev = phydev-dev;
+   const struct device_node *of_node = dev-of_node;
+   static const char *clk_skews[2] = {rxc-skew-ps, txc-skew-ps};
+   static const char *rx_data_skews[4] = {
rxd0-skew-ps, rxd1-skew-ps,
rxd2-skew-ps, rxd3-skew-ps
};
-   char *tx_data_skews[4] = {
+   static const char *tx_data_skews[4] = {
txd0-skew-ps, txd1-skew-ps,
txd2-skew-ps, txd3-skew-ps
};
-   char *control_skews[2] = {txen-skew-ps, rxdv-skew-ps};
+   static const char *control_skews[2] = {txen-skew-ps, rxdv-skew-ps};
 
if (!of_node  dev-parent-of_node)
of_node = dev-parent-of_node;
@@ -519,7 +520,7 @@ ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, 
int devnum,
 static int kszphy_probe(struct phy_device *phydev)
 {
const struct kszphy_type *type = phydev-drv-driver_data;
-   struct device_node *np = phydev-dev.of_node;
+   const struct device_node *np = phydev-dev.of_node;
struct kszphy_priv *priv;
struct clk *clk;
int ret;
-- 
2.1.4

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[PATCH v3 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.

From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
Auto-Negotiation Timing:
The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
Standard specifies this timing to be 16ms +/-8ms. Some PHY link
partners need to receive the FLP with 16ms centered timing;
otherwise, there can be intermittent link failures and long
link-up times.

After KSZ9031[RNX or MNX] power-up/reset, program the following
register sequence to set the FLP timing to 16ms

Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0004 // Select Register 4h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 4h
Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device 
Address 0h, Register 4h
Write Register Dh = 0x // Set up register address for MMD – Device 
Address 0h
Write Register Eh = 0x0003 // Select Register 3h of MMD – Device 
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device 
Address 0h, Register 3h
Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device 
Address 0h, Register 3h
Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index f23765e..499185e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO  3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI  4
+
 /* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
@@ -427,6 +431,22 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 }
 
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+   int result;
+
+   /* Center KSZ9031RNX FLP timing at 16ms. */
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+   if (result)
+   return result;
+
+   return genphy_restart_aneg(phydev);
+}
+
 static int ksz9031_config_init(struct phy_device *phydev)
 {
const struct device *dev = phydev-dev;
@@ -462,7 +482,8 @@ static int ksz9031_config_init(struct phy_device *phydev)
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
tx_data_skews, 4);
}
-   return 0;
+
+   return ksz9031_center_flp_timing(phydev);
 }
 
 #define KSZ8873MLL_GLOBAL_CONTROL_40x06
-- 
2.1.4

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[PATCH v3 0/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
In v2, we add an additional cleanup commit to make an array of strings
static const and to improve const correctness generally. We also no longer
unnecessarily initialize the result variable in
ksz9031_center_flp_timing().

In v3, we remove the unnecessary result variable from ksz9031_config_init()
introduced by a previous version of net/phy: micrel: Center FLP timing at
16ms.

Jaeden Amero (3):
  net/phy: micrel: Be more const correct
  net/phy: micrel: Comment MMD address of extended registers
  net/phy: micrel: Center FLP timing at 16ms

 drivers/net/phy/micrel.c | 53 ++--
 1 file changed, 38 insertions(+), 15 deletions(-)

-- 
2.1.4

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[PATCH v3 2/3] net/phy: micrel: Comment MMD address of extended registers

2015-06-05 Thread Jaeden Amero
There are some defines for a few pad skew related extended registers.
Specify for which MMD Address (dev_addr) they are for.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 59cc5d4..f23765e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,7 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
-- 
2.1.4

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[PATCH v4 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.

From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
Auto-Negotiation Timing:
The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
Standard specifies this timing to be 16ms +/-8ms. Some PHY link
partners need to receive the FLP with 16ms centered timing;
otherwise, there can be intermittent link failures and long
link-up times.

The PHY data sheet recommends configuring the FLP burst registers after
power-up/reset and immediately thereafter restarting auto-negotiation, so
we center the FLP timing at 16ms and then restart auto-negotiation in the
config_init for KSZ9031.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index f23765e..499185e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO  3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI  4
+
 /* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
@@ -427,6 +431,22 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 }
 
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+   int result;
+
+   /* Center KSZ9031RNX FLP timing at 16ms. */
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+   result = ksz9031_extended_write(phydev, OP_DATA, 0,
+   MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+   if (result)
+   return result;
+
+   return genphy_restart_aneg(phydev);
+}
+
 static int ksz9031_config_init(struct phy_device *phydev)
 {
const struct device *dev = phydev-dev;
@@ -462,7 +482,8 @@ static int ksz9031_config_init(struct phy_device *phydev)
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
tx_data_skews, 4);
}
-   return 0;
+
+   return ksz9031_center_flp_timing(phydev);
 }
 
 #define KSZ8873MLL_GLOBAL_CONTROL_40x06
-- 
2.1.4

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[PATCH v4 1/3] net/phy: micrel: Be more const correct

2015-06-05 Thread Jaeden Amero
In a few places in this driver, we weren't using const where we could
have. Use const more.

In addition, change the arrays of strings in ksz9031_config_init() to be
not only const, but also static.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 29 +++--
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ebdc357..59cc5d4 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -288,9 +288,10 @@ static int kszphy_config_init(struct phy_device *phydev)
 }
 
 static int ksz9021_load_values_from_of(struct phy_device *phydev,
-  struct device_node *of_node, u16 reg,
-  char *field1, char *field2,
-  char *field3, char *field4)
+  const struct device_node *of_node,
+  u16 reg,
+  const char *field1, const char *field2,
+  const char *field3, const char *field4)
 {
int val1 = -1;
int val2 = -2;
@@ -336,8 +337,8 @@ static int ksz9021_load_values_from_of(struct phy_device 
*phydev,
 
 static int ksz9021_config_init(struct phy_device *phydev)
 {
-   struct device *dev = phydev-dev;
-   struct device_node *of_node = dev-of_node;
+   const struct device *dev = phydev-dev;
+   const struct device_node *of_node = dev-of_node;
 
if (!of_node  dev-parent-of_node)
of_node = dev-parent-of_node;
@@ -389,9 +390,9 @@ static int ksz9031_extended_read(struct phy_device *phydev,
 }
 
 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
-  struct device_node *of_node,
+  const struct device_node *of_node,
   u16 reg, size_t field_sz,
-  char *field[], u8 numfields)
+  const char *field[], u8 numfields)
 {
int val[4] = {-1, -2, -3, -4};
int matches = 0;
@@ -427,18 +428,18 @@ static int ksz9031_of_load_skew_values(struct phy_device 
*phydev,
 
 static int ksz9031_config_init(struct phy_device *phydev)
 {
-   struct device *dev = phydev-dev;
-   struct device_node *of_node = dev-of_node;
-   char *clk_skews[2] = {rxc-skew-ps, txc-skew-ps};
-   char *rx_data_skews[4] = {
+   const struct device *dev = phydev-dev;
+   const struct device_node *of_node = dev-of_node;
+   static const char *clk_skews[2] = {rxc-skew-ps, txc-skew-ps};
+   static const char *rx_data_skews[4] = {
rxd0-skew-ps, rxd1-skew-ps,
rxd2-skew-ps, rxd3-skew-ps
};
-   char *tx_data_skews[4] = {
+   static const char *tx_data_skews[4] = {
txd0-skew-ps, txd1-skew-ps,
txd2-skew-ps, txd3-skew-ps
};
-   char *control_skews[2] = {txen-skew-ps, rxdv-skew-ps};
+   static const char *control_skews[2] = {txen-skew-ps, rxdv-skew-ps};
 
if (!of_node  dev-parent-of_node)
of_node = dev-parent-of_node;
@@ -519,7 +520,7 @@ ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, 
int devnum,
 static int kszphy_probe(struct phy_device *phydev)
 {
const struct kszphy_type *type = phydev-drv-driver_data;
-   struct device_node *np = phydev-dev.of_node;
+   const struct device_node *np = phydev-dev.of_node;
struct kszphy_priv *priv;
struct clk *clk;
int ret;
-- 
2.1.4

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[PATCH v4 0/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
In v2, we add an additional cleanup commit to make an array of strings
static const and to improve const correctness generally. We also no longer
unnecessarily initialize the result variable in
ksz9031_center_flp_timing().

In v3, we remove the unnecessary result variable from ksz9031_config_init()
introduced by a previous version of net/phy: micrel: Center FLP timing at
16ms.

In v4, we modify the commit message of net/phy: micrel: Center FLP timing
at 16ms to replace the awkward quotation of the data sheet's programming
procedure with an explanation of why we program the FLP burst registers and
restart auto-negotiation where we do (config_init).

Jaeden Amero (3):
  net/phy: micrel: Be more const correct
  net/phy: micrel: Comment MMD address of extended registers
  net/phy: micrel: Center FLP timing at 16ms

 drivers/net/phy/micrel.c | 53 ++--
 1 file changed, 38 insertions(+), 15 deletions(-)

-- 
2.1.4

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[PATCH v4 2/3] net/phy: micrel: Comment MMD address of extended registers

2015-06-05 Thread Jaeden Amero
There are some defines for a few pad skew related extended registers.
Specify for which MMD Address (dev_addr) they are for.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/net/phy/micrel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 59cc5d4..f23765e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,7 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG  60
 
 /* Extended registers */
+/* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
-- 
2.1.4

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Re: [PATCH v3 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
On 06/05/2015 05:43 PM, Florian Fainelli wrote:
 On 05/06/15 15:40, Jaeden Amero wrote:
 Link failures have been observed when using the KSZ9031 with HP 1810-8G
 and HP 1910-8G network switches. Center the FLP timing at 16ms to help
 avoid intermittent link failures.

 From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
 Auto-Negotiation Timing:
  The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
  transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
  Standard specifies this timing to be 16ms +/-8ms. Some PHY link
  partners need to receive the FLP with 16ms centered timing;
  otherwise, there can be intermittent link failures and long
  link-up times.

  After KSZ9031[RNX or MNX] power-up/reset, program the following
  register sequence to set the FLP timing to 16ms

  Write Register Dh = 0x // Set up register address for MMD – Device 
 Address 0h
  Write Register Eh = 0x0004 // Select Register 4h of MMD – Device 
 Address 0h
  Write Register Dh = 0x4000 // Select register data for MMD – Device 
 Address 0h, Register 4h
  Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device 
 Address 0h, Register 4h
  Write Register Dh = 0x // Set up register address for MMD – Device 
 Address 0h
  Write Register Eh = 0x0003 // Select Register 3h of MMD – Device 
 Address 0h
  Write Register Dh = 0x4000 // Select register data for MMD – Device 
 Address 0h, Register 3h
  Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device 
 Address 0h, Register 3h
  Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation
 
 Quoting a portion of the data-sheet on how to do this programming is
 very strange considering that the code is going to be the reference, not
 the commit message.

I included it for lack of something better to quote that explained
which values to set when. I'd be happy to revise the message as this
appears too strange.

 Other than that, this looks reasonable.

Thanks very much for the review.

Cheers,
Jaeden
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Re: [PATCH v2 3/3] net/phy: micrel: Center FLP timing at 16ms

2015-06-05 Thread Jaeden Amero
On 06/05/2015 04:09 PM, Sergei Shtylyov wrote:
 @@ -441,6 +461,7 @@ static int ksz9031_config_init(struct phy_device
 *phydev)
   txd2-skew-ps, txd3-skew-ps
   };
   static const char *control_skews[2] = {txen-skew-ps,
 rxdv-skew-ps};
 +int result;
 
You hardly need this variable...
 

   if (!of_node  dev-parent-of_node)
   of_node = dev-parent-of_node;
 @@ -462,7 +483,10 @@ static int ksz9031_config_init(struct phy_device
 *phydev)
   MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
   tx_data_skews, 4);
   }
 -return 0;
 +
 +result = ksz9031_center_flp_timing(phydev);
 +
 +return result;
 
Why not just return directly?
 

Genius.

Thanks for the feedback. I'll post a v3.
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Re: [net-next PATCH v2 2/3] net: macb: Add support for jumbo frames

2015-05-04 Thread Jaeden Amero
On 05/04/2015 02:52 AM, Harini Katakam wrote:
> Check for "cdns,zynqmp-gem" compatible string and enable jumbo frame support
> in NWCFG register, update descriptor length masks and registers accordingly.
> Jumbo max length register should be set according to support in SoC; it is
> set to 10240 for Zynq Ultrascale+ MPSoC.
> 
> Signed-off-by: Harini Katakam 
> Reviewed-by: Punnaiah Choudary Kalluri 
> ---
> 
> On v1, Michal commented that I should use macb_config for jumbo parameters
> instead of defining them by reading the compatible string directly.
> I can use .caps for isjumbo. But jumbo-max-length needs to be defined.
> Can I add this to the structure? Any suggestions on how to handle this?
> 
> v2:
> Add constant definition and update SoC name
> 
> ---
>  drivers/net/ethernet/cadence/macb.c |   21 ++---
>  drivers/net/ethernet/cadence/macb.h |8 
>  2 files changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.c 
> b/drivers/net/ethernet/cadence/macb.c
> index 4104d49..a065283 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -54,6 +54,8 @@
>  #define MACB_MAX_TX_LEN  ((unsigned int)((1 << 
> MACB_TX_FRMLEN_SIZE) - 1))
>  #define GEM_MAX_TX_LEN   ((unsigned int)((1 << 
> GEM_TX_FRMLEN_SIZE) - 1))
>  
> +#define GEM_ZYNQMP_JUMBO_MAX 10240
> +
>  /*
>   * Graceful stop timeouts in us. We should allow up to
>   * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
> @@ -782,7 +784,7 @@ static int gem_rx(struct macb *bp, int budget)
>   }
>   /* now everything is ready for receiving packet */
>   bp->rx_skbuff[entry] = NULL;
> - len = MACB_BFEXT(RX_FRMLEN, ctrl);
> + len = ctrl & bp->rx_frm_len_mask;
>  
>   netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
>  
> @@ -828,7 +830,7 @@ static int macb_rx_frame(struct macb *bp, unsigned int 
> first_frag,
>   struct macb_dma_desc *desc;
>  
>   desc = macb_rx_desc(bp, last_frag);
> - len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
> + len = desc->ctrl & bp->rx_frm_len_mask;
>  
>   netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
>   macb_rx_ring_wrap(first_frag),
> @@ -1633,7 +1635,10 @@ static void macb_init_hw(struct macb *bp)
>   config |= MACB_BF(RBOF, NET_IP_ALIGN);  /* Make eth data aligned */
>   config |= MACB_BIT(PAE);/* PAuse Enable */
>   config |= MACB_BIT(DRFCS);  /* Discard Rx FCS */
> - config |= MACB_BIT(BIG);/* Receive oversized frames */
> + if (bp->isjumbo)
> + config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
> + else
> + config |= MACB_BIT(BIG);/* Receive oversized frames */
>   if (bp->dev->flags & IFF_PROMISC)
>   config |= MACB_BIT(CAF);/* Copy All Frames */
>   else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
> @@ -1642,8 +1647,13 @@ static void macb_init_hw(struct macb *bp)
>   config |= MACB_BIT(NBC);/* No BroadCast */
>   config |= macb_dbw(bp);
>   macb_writel(bp, NCFGR, config);
> + if (bp->isjumbo && bp->jumbo_max_len)
> + gem_writel(bp, JML, bp->jumbo_max_len);
>   bp->speed = SPEED_10;
>   bp->duplex = DUPLEX_HALF;
> + bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
> + if (bp->isjumbo)
> + bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
>  
>   macb_configure_dma(bp);
>  
> @@ -2762,6 +2772,11 @@ static int macb_probe(struct platform_device *pdev)
>   bp->pclk = pclk;
>   bp->hclk = hclk;
>   bp->tx_clk = tx_clk;
> + if (of_device_is_compatible(pdev->dev.of_node, "cdns,zynqmp-gem")) {
> + bp->isjumbo = 1;
> + bp->jumbo_max_len = GEM_ZYNQMP_JUMBO_MAX;

Could you use the bottom 16 bits of DCFG2 instead of GEM_ZYNQMP_JUMBO_MAX?

> + }
> +
>   spin_lock_init(>lock);
>  
>   /* setup capabilities */
> diff --git a/drivers/net/ethernet/cadence/macb.h 
> b/drivers/net/ethernet/cadence/macb.h
> index eb7d76f..e25f77e 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -71,6 +71,7 @@
>  #define GEM_NCFGR0x0004 /* Network Config */
>  #define GEM_USRIO0x000c /* User IO */
>  #define GEM_DMACFG   0x0010 /* DMA Configuration */
> +#define GEM_JML  0x0048 /* Jumbo Max Length */
>  #define GEM_HRB  0x0080 /* Hash Bottom */
>  #define GEM_HRT  0x0084 /* Hash Top */
>  #define GEM_SA1B 0x0088 /* Specific1 Bottom */
> @@ -514,6 +515,9 @@ struct macb_dma_desc {
>  #define MACB_RX_BROADCAST_OFFSET 31
>  #define MACB_RX_BROADCAST_SIZE   1
>  
> +#define MACB_RX_FRMLEN_MASK  0xFFF
> +#define MACB_RX_JFRMLEN_MASK 

Re: [net-next PATCH v2 2/3] net: macb: Add support for jumbo frames

2015-05-04 Thread Jaeden Amero
On 05/04/2015 02:52 AM, Harini Katakam wrote:
 Check for cdns,zynqmp-gem compatible string and enable jumbo frame support
 in NWCFG register, update descriptor length masks and registers accordingly.
 Jumbo max length register should be set according to support in SoC; it is
 set to 10240 for Zynq Ultrascale+ MPSoC.
 
 Signed-off-by: Harini Katakam hari...@xilinx.com
 Reviewed-by: Punnaiah Choudary Kalluri punn...@xilinx.com
 ---
 
 On v1, Michal commented that I should use macb_config for jumbo parameters
 instead of defining them by reading the compatible string directly.
 I can use .caps for isjumbo. But jumbo-max-length needs to be defined.
 Can I add this to the structure? Any suggestions on how to handle this?
 
 v2:
 Add constant definition and update SoC name
 
 ---
  drivers/net/ethernet/cadence/macb.c |   21 ++---
  drivers/net/ethernet/cadence/macb.h |8 
  2 files changed, 26 insertions(+), 3 deletions(-)
 
 diff --git a/drivers/net/ethernet/cadence/macb.c 
 b/drivers/net/ethernet/cadence/macb.c
 index 4104d49..a065283 100644
 --- a/drivers/net/ethernet/cadence/macb.c
 +++ b/drivers/net/ethernet/cadence/macb.c
 @@ -54,6 +54,8 @@
  #define MACB_MAX_TX_LEN  ((unsigned int)((1  
 MACB_TX_FRMLEN_SIZE) - 1))
  #define GEM_MAX_TX_LEN   ((unsigned int)((1  
 GEM_TX_FRMLEN_SIZE) - 1))
  
 +#define GEM_ZYNQMP_JUMBO_MAX 10240
 +
  /*
   * Graceful stop timeouts in us. We should allow up to
   * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
 @@ -782,7 +784,7 @@ static int gem_rx(struct macb *bp, int budget)
   }
   /* now everything is ready for receiving packet */
   bp-rx_skbuff[entry] = NULL;
 - len = MACB_BFEXT(RX_FRMLEN, ctrl);
 + len = ctrl  bp-rx_frm_len_mask;
  
   netdev_vdbg(bp-dev, gem_rx %u (len %u)\n, entry, len);
  
 @@ -828,7 +830,7 @@ static int macb_rx_frame(struct macb *bp, unsigned int 
 first_frag,
   struct macb_dma_desc *desc;
  
   desc = macb_rx_desc(bp, last_frag);
 - len = MACB_BFEXT(RX_FRMLEN, desc-ctrl);
 + len = desc-ctrl  bp-rx_frm_len_mask;
  
   netdev_vdbg(bp-dev, macb_rx_frame frags %u - %u (len %u)\n,
   macb_rx_ring_wrap(first_frag),
 @@ -1633,7 +1635,10 @@ static void macb_init_hw(struct macb *bp)
   config |= MACB_BF(RBOF, NET_IP_ALIGN);  /* Make eth data aligned */
   config |= MACB_BIT(PAE);/* PAuse Enable */
   config |= MACB_BIT(DRFCS);  /* Discard Rx FCS */
 - config |= MACB_BIT(BIG);/* Receive oversized frames */
 + if (bp-isjumbo)
 + config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
 + else
 + config |= MACB_BIT(BIG);/* Receive oversized frames */
   if (bp-dev-flags  IFF_PROMISC)
   config |= MACB_BIT(CAF);/* Copy All Frames */
   else if (macb_is_gem(bp)  bp-dev-features  NETIF_F_RXCSUM)
 @@ -1642,8 +1647,13 @@ static void macb_init_hw(struct macb *bp)
   config |= MACB_BIT(NBC);/* No BroadCast */
   config |= macb_dbw(bp);
   macb_writel(bp, NCFGR, config);
 + if (bp-isjumbo  bp-jumbo_max_len)
 + gem_writel(bp, JML, bp-jumbo_max_len);
   bp-speed = SPEED_10;
   bp-duplex = DUPLEX_HALF;
 + bp-rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
 + if (bp-isjumbo)
 + bp-rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
  
   macb_configure_dma(bp);
  
 @@ -2762,6 +2772,11 @@ static int macb_probe(struct platform_device *pdev)
   bp-pclk = pclk;
   bp-hclk = hclk;
   bp-tx_clk = tx_clk;
 + if (of_device_is_compatible(pdev-dev.of_node, cdns,zynqmp-gem)) {
 + bp-isjumbo = 1;
 + bp-jumbo_max_len = GEM_ZYNQMP_JUMBO_MAX;

Could you use the bottom 16 bits of DCFG2 instead of GEM_ZYNQMP_JUMBO_MAX?

 + }
 +
   spin_lock_init(bp-lock);
  
   /* setup capabilities */
 diff --git a/drivers/net/ethernet/cadence/macb.h 
 b/drivers/net/ethernet/cadence/macb.h
 index eb7d76f..e25f77e 100644
 --- a/drivers/net/ethernet/cadence/macb.h
 +++ b/drivers/net/ethernet/cadence/macb.h
 @@ -71,6 +71,7 @@
  #define GEM_NCFGR0x0004 /* Network Config */
  #define GEM_USRIO0x000c /* User IO */
  #define GEM_DMACFG   0x0010 /* DMA Configuration */
 +#define GEM_JML  0x0048 /* Jumbo Max Length */
  #define GEM_HRB  0x0080 /* Hash Bottom */
  #define GEM_HRT  0x0084 /* Hash Top */
  #define GEM_SA1B 0x0088 /* Specific1 Bottom */
 @@ -514,6 +515,9 @@ struct macb_dma_desc {
  #define MACB_RX_BROADCAST_OFFSET 31
  #define MACB_RX_BROADCAST_SIZE   1
  
 +#define MACB_RX_FRMLEN_MASK  0xFFF
 +#define MACB_RX_JFRMLEN_MASK 0x3FFF
 +
  /* RX checksum offload disabled: bit 24 clear in NCFGR */
  #define GEM_RX_TYPEID_MATCH_OFFSET

Re: [PATCH RFC] net/macb: Fix UDPv4 checksum offload

2015-04-28 Thread Jaeden Amero
On 04/27/2015 09:47 PM, David Miller wrote:
> From: Jaeden Amero 
> Date: Mon, 27 Apr 2015 17:43:30 -0500
>
> A UDP checksum of zero, means "checksum not computed".  And your
> device isn't computing the checksum at all, but rather is leaving it
> at zero.

The "zero" checksum is not what gets sent over the wire. Independent of
the value of the checksum field, hardware generates a correct checksum
for payloads of 3 or more bytes. The bug is that hardware generates an
incorrect checksum for payloads of 2 or less bytes, unless the checksum
field is zeroed.

> You need to handle this properly by computing the checksum in
> software and then setting the TX descriptor bits such that the
> chip leaves the checksum field alone.

Unfortunately, the Cadence MACB doesn't support the enabling or
disabling of checksum generation per descriptor.
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Re: [PATCH RFC] net/macb: Fix UDPv4 checksum offload

2015-04-28 Thread Jaeden Amero
On 04/27/2015 09:47 PM, David Miller wrote:
 From: Jaeden Amero jaeden.am...@ni.com
 Date: Mon, 27 Apr 2015 17:43:30 -0500

 A UDP checksum of zero, means checksum not computed.  And your
 device isn't computing the checksum at all, but rather is leaving it
 at zero.

The zero checksum is not what gets sent over the wire. Independent of
the value of the checksum field, hardware generates a correct checksum
for payloads of 3 or more bytes. The bug is that hardware generates an
incorrect checksum for payloads of 2 or less bytes, unless the checksum
field is zeroed.

 You need to handle this properly by computing the checksum in
 software and then setting the TX descriptor bits such that the
 chip leaves the checksum field alone.

Unfortunately, the Cadence MACB doesn't support the enabling or
disabling of checksum generation per descriptor.
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[PATCH RFC] net/macb: Fix UDPv4 checksum offload

2015-04-27 Thread Jaeden Amero
From: Jeff Westfahl 

Some Cadence MACB hardware generates incorrect UDP checksums for
outgoing UDP packets with a payload of 2 bytes of less. If the UDP data
payload is 0, 1 or 2 bytes, transmit checksum offloading can compute an
incorrect UDPv4 header checksum (e.g. 0x). If we set the checksum
field in the UDP header to 0, the checksum is computed correctly.

Signed-off-by: Jeff Westfahl 
Signed-off-by: Mihai Neagu 
Signed-off-by: Jaeden Amero 
---

Hey Nicolas,

We see this bug on the Zynq 7000 series chips, but it's unclear as to whether
it applies to other MACB hardware implementations.

We've scoped it to only apply to MACB_MID == 0x20118 (which is the MID we see
used on Zynq), but we, unfortunately, do not know how to identify which MACBs
have this bug.


Reproducing the Bug
---
The bug is pretty easy to reproduce with two networked systems (at least one
using a MACB) and netcat.

Here is some captured data that goes out on the wire when sending the string
"a\n" and "ab\n" via netcat (UDP).

Here is a hexdump of what I observed. I underlined the UDP checksum with
"". I censored my MACs and IPs with X.

"a\n"
000        
010        
020  4282 2923 0a00  0a61  

030      

"ab\n"
000        
010        
020  4282 2923 0b00 c4d2 6261 000a 

030      

As you can see, with the two byte payload, the checksum field of the UDP header
is 0x.


This Patch's Workaround
---
Xilinx implements a "fix" for this bug in their out-of-tree xilinx-xemacps
duplicate macb driver here[1].

The workaround is to zero the UDP checksum field in the packet before sending
the packet to the hardware.

What I'm attempting to do in this patch is to implement a real fix in a way
that is suitable for the normal Cadence MACB driver and will work with all
Cadence MACB implementations, not just those used in the Zynq.

Thanks for any feedback you can provide.

Cheers,
Jaeden


[1] 
https://github.com/Xilinx/linux-xlnx/commit/af2c4ebb7ac56cc5a55cbe55db05470d6e91cbe2


 drivers/net/ethernet/cadence/macb.c | 48 +
 drivers/net/ethernet/cadence/macb.h |  7 ++
 2 files changed, 55 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb.c 
b/drivers/net/ethernet/cadence/macb.c
index 9f53872..a9214a6 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -30,6 +30,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "macb.h"
 
@@ -1219,6 +1221,38 @@ dma_error:
return 0;
 }
 
+static void macb_handle_broken_udp_csum(struct sk_buff *skb,
+   struct net_device *dev)
+{
+   /* Transmit checksum offloading can compute an incorrect UDPv4 header
+* checksum if the checksum value is not already zero.
+*/
+   if (dev->features & NETIF_F_HW_CSUM) {
+   /* The Ethernet header is never set. */
+   skb_reset_mac_header(skb);
+   /* If the packet is IP. */
+   if (ntohs(eth_hdr(skb)->h_proto) == ETH_P_IP) {
+   /* Usually the IP header is already set. */
+   if (unlikely(!ip_hdr(skb)))
+   skb_set_network_header(skb, ETH_HLEN);
+   /* If the packet is UDPv4. */
+   if ((ip_hdr(skb)->version == 4) &&
+   (ip_hdr(skb)->protocol == IPPROTO_UDP)) {
+   /* Sometimes the UDP header is set, sometimes
+* not.
+*/
+   if (!udp_hdr(skb))
+   skb_set_transport_header(
+   skb,
+   ETH_HLEN +
+ (ip_hdr(skb)->ihl << 2));
+   /* Clear the checksum field. */
+   udp_hdr(skb)->check = 0;
+   }
+   }
+   }
+}
+
 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
u16 queue_index = skb_get_queue_mapping(skb);
@@ -1258,6 +1292,9 @@ static int macb_start_xmit(struct sk_buff *skb, struct 
net_device *dev)
return NETDEV_TX_BUSY;
}
 
+   if (bp->quirks & MACB_QUIRK_BROKEN_UDP_CSUM_OFFLOAD)
+   macb_handle_broken_udp_csum(skb, dev);
+
/* Map socket buffer for DMA transfer */
if (!macb_tx_map(bp, queue, skb))

[PATCH RFC] net/macb: Fix UDPv4 checksum offload

2015-04-27 Thread Jaeden Amero
From: Jeff Westfahl jeff.westf...@ni.com

Some Cadence MACB hardware generates incorrect UDP checksums for
outgoing UDP packets with a payload of 2 bytes of less. If the UDP data
payload is 0, 1 or 2 bytes, transmit checksum offloading can compute an
incorrect UDPv4 header checksum (e.g. 0x). If we set the checksum
field in the UDP header to 0, the checksum is computed correctly.

Signed-off-by: Jeff Westfahl jeff.westf...@ni.com
Signed-off-by: Mihai Neagu mihai.ne...@ni.com
Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---

Hey Nicolas,

We see this bug on the Zynq 7000 series chips, but it's unclear as to whether
it applies to other MACB hardware implementations.

We've scoped it to only apply to MACB_MID == 0x20118 (which is the MID we see
used on Zynq), but we, unfortunately, do not know how to identify which MACBs
have this bug.


Reproducing the Bug
---
The bug is pretty easy to reproduce with two networked systems (at least one
using a MACB) and netcat.

Here is some captured data that goes out on the wire when sending the string
a\n and ab\n via netcat (UDP).

Here is a hexdump of what I observed. I underlined the UDP checksum with
. I censored my MACs and IPs with X.

a\n
000        
010        
020  4282 2923 0a00  0a61  

030      

ab\n
000        
010        
020  4282 2923 0b00 c4d2 6261 000a 

030      

As you can see, with the two byte payload, the checksum field of the UDP header
is 0x.


This Patch's Workaround
---
Xilinx implements a fix for this bug in their out-of-tree xilinx-xemacps
duplicate macb driver here[1].

The workaround is to zero the UDP checksum field in the packet before sending
the packet to the hardware.

What I'm attempting to do in this patch is to implement a real fix in a way
that is suitable for the normal Cadence MACB driver and will work with all
Cadence MACB implementations, not just those used in the Zynq.

Thanks for any feedback you can provide.

Cheers,
Jaeden


[1] 
https://github.com/Xilinx/linux-xlnx/commit/af2c4ebb7ac56cc5a55cbe55db05470d6e91cbe2


 drivers/net/ethernet/cadence/macb.c | 48 +
 drivers/net/ethernet/cadence/macb.h |  7 ++
 2 files changed, 55 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb.c 
b/drivers/net/ethernet/cadence/macb.c
index 9f53872..a9214a6 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -30,6 +30,8 @@
 #include linux/of_device.h
 #include linux/of_mdio.h
 #include linux/of_net.h
+#include linux/ip.h
+#include linux/udp.h
 
 #include macb.h
 
@@ -1219,6 +1221,38 @@ dma_error:
return 0;
 }
 
+static void macb_handle_broken_udp_csum(struct sk_buff *skb,
+   struct net_device *dev)
+{
+   /* Transmit checksum offloading can compute an incorrect UDPv4 header
+* checksum if the checksum value is not already zero.
+*/
+   if (dev-features  NETIF_F_HW_CSUM) {
+   /* The Ethernet header is never set. */
+   skb_reset_mac_header(skb);
+   /* If the packet is IP. */
+   if (ntohs(eth_hdr(skb)-h_proto) == ETH_P_IP) {
+   /* Usually the IP header is already set. */
+   if (unlikely(!ip_hdr(skb)))
+   skb_set_network_header(skb, ETH_HLEN);
+   /* If the packet is UDPv4. */
+   if ((ip_hdr(skb)-version == 4) 
+   (ip_hdr(skb)-protocol == IPPROTO_UDP)) {
+   /* Sometimes the UDP header is set, sometimes
+* not.
+*/
+   if (!udp_hdr(skb))
+   skb_set_transport_header(
+   skb,
+   ETH_HLEN +
+ (ip_hdr(skb)-ihl  2));
+   /* Clear the checksum field. */
+   udp_hdr(skb)-check = 0;
+   }
+   }
+   }
+}
+
 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
u16 queue_index = skb_get_queue_mapping(skb);
@@ -1258,6 +1292,9 @@ static int macb_start_xmit(struct sk_buff *skb, struct 
net_device *dev)
return NETDEV_TX_BUSY;
}
 
+   if (bp-quirks  MACB_QUIRK_BROKEN_UDP_CSUM_OFFLOAD)
+   macb_handle_broken_udp_csum(skb, dev);
+
/* Map socket buffer for DMA transfer */
if (!macb_tx_map(bp, queue

[PATCH] net/macb: Only adjust tx_clk on link change

2015-03-12 Thread Jaeden Amero
The PHY state machine (in drivers/net/phy/phy.c) will unconditionally
call phydev->adjust_link (macb_handle_link_change) when polling in the
PHY_CHANGELINK state. As currently written, macb always ends up
requesting a new tx_clk frequency in macb_handle_link_change. It is a
waste of time to request a new tx_clk frequency if the link state hasn't
changed, as the tx_clk will already be configured properly.

Let's only request a new tx_clk clock frequency when necessary.

Signed-off-by: Jaeden Amero 
Cc: Josh Cartwright 
Cc: Soren Brinkmann 
---
 drivers/net/ethernet/cadence/macb.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.c 
b/drivers/net/ethernet/cadence/macb.c
index f00be58..a0a04b3 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -293,10 +293,13 @@ static void macb_handle_link_change(struct net_device 
*dev)
 
spin_unlock_irqrestore(>lock, flags);
 
-   macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
-
if (status_change) {
if (phydev->link) {
+   /* Update the TX clock rate if and only if the link is
+* up and there has been a link change.
+*/
+   macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
+
netif_carrier_on(dev);
netdev_info(dev, "link up (%d/%s)\n",
phydev->speed,
-- 
2.1.4

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[PATCH] net/macb: Only adjust tx_clk on link change

2015-03-12 Thread Jaeden Amero
The PHY state machine (in drivers/net/phy/phy.c) will unconditionally
call phydev-adjust_link (macb_handle_link_change) when polling in the
PHY_CHANGELINK state. As currently written, macb always ends up
requesting a new tx_clk frequency in macb_handle_link_change. It is a
waste of time to request a new tx_clk frequency if the link state hasn't
changed, as the tx_clk will already be configured properly.

Let's only request a new tx_clk clock frequency when necessary.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
Cc: Josh Cartwright jo...@ni.com
Cc: Soren Brinkmann soren.brinkm...@xilinx.com
---
 drivers/net/ethernet/cadence/macb.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.c 
b/drivers/net/ethernet/cadence/macb.c
index f00be58..a0a04b3 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -293,10 +293,13 @@ static void macb_handle_link_change(struct net_device 
*dev)
 
spin_unlock_irqrestore(bp-lock, flags);
 
-   macb_set_tx_clk(bp-tx_clk, phydev-speed, dev);
-
if (status_change) {
if (phydev-link) {
+   /* Update the TX clock rate if and only if the link is
+* up and there has been a link change.
+*/
+   macb_set_tx_clk(bp-tx_clk, phydev-speed, dev);
+
netif_carrier_on(dev);
netdev_info(dev, link up (%d/%s)\n,
phydev-speed,
-- 
2.1.4

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[PATCH RESEND RESEND] compat_ioctl: Add RS-485 IOCTLs to the list

2012-09-18 Thread Jaeden Amero
The RS-485 TIOCSRS485 and TIOCGRS485 ioctls are 32-bit compatible, so
in order to call them on 64-bit systems from 32-bit user mode, we add
them to the ioctl pointer list as compatible ioctls.

Signed-off-by: Jaeden Amero 
---
 fs/compat_ioctl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fs/compat_ioctl.c b/fs/compat_ioctl.c
index 
debdfe0fc809edfd01ac4a72a0eaf2753efc993d..85dfebfe6820856dc3154dfd178acb6fca63bbe9
 100644
--- a/fs/compat_ioctl.c
+++ b/fs/compat_ioctl.c
@@ -866,6 +866,8 @@ COMPATIBLE_IOCTL(TIOCGPTN)
 COMPATIBLE_IOCTL(TIOCSPTLCK)
 COMPATIBLE_IOCTL(TIOCSERGETLSR)
 COMPATIBLE_IOCTL(TIOCSIG)
+COMPATIBLE_IOCTL(TIOCSRS485)
+COMPATIBLE_IOCTL(TIOCGRS485)
 #ifdef TCGETS2
 COMPATIBLE_IOCTL(TCGETS2)
 COMPATIBLE_IOCTL(TCSETS2)
-- 
1.7.12

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[PATCH RESEND RESEND] compat_ioctl: Add RS-485 IOCTLs to the list

2012-09-18 Thread Jaeden Amero
The RS-485 TIOCSRS485 and TIOCGRS485 ioctls are 32-bit compatible, so
in order to call them on 64-bit systems from 32-bit user mode, we add
them to the ioctl pointer list as compatible ioctls.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 fs/compat_ioctl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fs/compat_ioctl.c b/fs/compat_ioctl.c
index 
debdfe0fc809edfd01ac4a72a0eaf2753efc993d..85dfebfe6820856dc3154dfd178acb6fca63bbe9
 100644
--- a/fs/compat_ioctl.c
+++ b/fs/compat_ioctl.c
@@ -866,6 +866,8 @@ COMPATIBLE_IOCTL(TIOCGPTN)
 COMPATIBLE_IOCTL(TIOCSPTLCK)
 COMPATIBLE_IOCTL(TIOCSERGETLSR)
 COMPATIBLE_IOCTL(TIOCSIG)
+COMPATIBLE_IOCTL(TIOCSRS485)
+COMPATIBLE_IOCTL(TIOCGRS485)
 #ifdef TCGETS2
 COMPATIBLE_IOCTL(TCGETS2)
 COMPATIBLE_IOCTL(TCSETS2)
-- 
1.7.12

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[PATCH RESEND] compat_ioctl: Add RS-485 IOCTLs to the list

2012-08-21 Thread Jaeden Amero
The RS-485 TIOCSRS485 and TIOCGRS485 ioctls are 32-bit compatible, so
in order to call them on 64-bit systems from 32-bit user mode, we add
them to the ioctl pointer list as compatible ioctls.

Signed-off-by: Jaeden Amero 
---
 fs/compat_ioctl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fs/compat_ioctl.c b/fs/compat_ioctl.c
index 
debdfe0fc809edfd01ac4a72a0eaf2753efc993d..85dfebfe6820856dc3154dfd178acb6fca63bbe9
 100644
--- a/fs/compat_ioctl.c
+++ b/fs/compat_ioctl.c
@@ -866,6 +866,8 @@ COMPATIBLE_IOCTL(TIOCGPTN)
 COMPATIBLE_IOCTL(TIOCSPTLCK)
 COMPATIBLE_IOCTL(TIOCSERGETLSR)
 COMPATIBLE_IOCTL(TIOCSIG)
+COMPATIBLE_IOCTL(TIOCSRS485)
+COMPATIBLE_IOCTL(TIOCGRS485)
 #ifdef TCGETS2
 COMPATIBLE_IOCTL(TCGETS2)
 COMPATIBLE_IOCTL(TCSETS2)
-- 
1.7.12

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[PATCH RESEND] compat_ioctl: Add RS-485 IOCTLs to the list

2012-08-21 Thread Jaeden Amero
The RS-485 TIOCSRS485 and TIOCGRS485 ioctls are 32-bit compatible, so
in order to call them on 64-bit systems from 32-bit user mode, we add
them to the ioctl pointer list as compatible ioctls.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 fs/compat_ioctl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fs/compat_ioctl.c b/fs/compat_ioctl.c
index 
debdfe0fc809edfd01ac4a72a0eaf2753efc993d..85dfebfe6820856dc3154dfd178acb6fca63bbe9
 100644
--- a/fs/compat_ioctl.c
+++ b/fs/compat_ioctl.c
@@ -866,6 +866,8 @@ COMPATIBLE_IOCTL(TIOCGPTN)
 COMPATIBLE_IOCTL(TIOCSPTLCK)
 COMPATIBLE_IOCTL(TIOCSERGETLSR)
 COMPATIBLE_IOCTL(TIOCSIG)
+COMPATIBLE_IOCTL(TIOCSRS485)
+COMPATIBLE_IOCTL(TIOCGRS485)
 #ifdef TCGETS2
 COMPATIBLE_IOCTL(TCGETS2)
 COMPATIBLE_IOCTL(TCSETS2)
-- 
1.7.12

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[PATCH] n_tty: Don't lose characters when PARMRK is enabled

2012-07-27 Thread Jaeden Amero
When PARMRK is set and large transfers of characters that will get
marked are being received, n_tty could drop data silently (i.e.
without reporting any error to the client). This is because
characters have the potential to take up to three bytes in the line
discipline (when they get marked with parity or framing errors), but
the amount of free space reported to tty_buffer flush_to_ldisc (via
tty->receive_room) is based on the pre-marked data size.

With this patch, the n_tty layer will no longer assume that each byte
will only take up one byte in the line discipline. Instead, it will
make an overly conservative estimate that each byte will take up
three bytes in the line discipline when PARMRK is set.

Signed-off-by: Jaeden Amero 
---
 drivers/tty/n_tty.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
index 
101790cea4ae45622c0628bf1833012087f9c7c5..e2473cf26d058d1de7059323fbe7a8f29fe0f74e
 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
@@ -92,10 +92,18 @@ static inline int tty_put_user(struct tty_struct *tty, 
unsigned char x,
 
 static void n_tty_set_room(struct tty_struct *tty)
 {
-   /* tty->read_cnt is not read locked ? */
-   int left = N_TTY_BUF_SIZE - tty->read_cnt - 1;
+   int left;
int old_left;
 
+   /* tty->read_cnt is not read locked ? */
+   if (I_PARMRK(tty)) {
+   /* Multiply read_cnt by 3, since each byte might take up to
+* three times as many spaces when PARMRK is set (depending on
+* its flags, e.g. parity error). */
+   left = N_TTY_BUF_SIZE - tty->read_cnt * 3 - 1;
+   } else
+   left = N_TTY_BUF_SIZE - tty->read_cnt - 1;
+
/*
 * If we are doing input canonicalization, and there are no
 * pending newlines, let characters through without limit, so
-- 
1.7.11.1

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[PATCH] n_tty: Don't lose characters when PARMRK is enabled

2012-07-27 Thread Jaeden Amero
When PARMRK is set and large transfers of characters that will get
marked are being received, n_tty could drop data silently (i.e.
without reporting any error to the client). This is because
characters have the potential to take up to three bytes in the line
discipline (when they get marked with parity or framing errors), but
the amount of free space reported to tty_buffer flush_to_ldisc (via
tty-receive_room) is based on the pre-marked data size.

With this patch, the n_tty layer will no longer assume that each byte
will only take up one byte in the line discipline. Instead, it will
make an overly conservative estimate that each byte will take up
three bytes in the line discipline when PARMRK is set.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/tty/n_tty.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
index 
101790cea4ae45622c0628bf1833012087f9c7c5..e2473cf26d058d1de7059323fbe7a8f29fe0f74e
 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
@@ -92,10 +92,18 @@ static inline int tty_put_user(struct tty_struct *tty, 
unsigned char x,
 
 static void n_tty_set_room(struct tty_struct *tty)
 {
-   /* tty-read_cnt is not read locked ? */
-   int left = N_TTY_BUF_SIZE - tty-read_cnt - 1;
+   int left;
int old_left;
 
+   /* tty-read_cnt is not read locked ? */
+   if (I_PARMRK(tty)) {
+   /* Multiply read_cnt by 3, since each byte might take up to
+* three times as many spaces when PARMRK is set (depending on
+* its flags, e.g. parity error). */
+   left = N_TTY_BUF_SIZE - tty-read_cnt * 3 - 1;
+   } else
+   left = N_TTY_BUF_SIZE - tty-read_cnt - 1;
+
/*
 * If we are doing input canonicalization, and there are no
 * pending newlines, let characters through without limit, so
-- 
1.7.11.1

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[PATCH] n_tty: Don't lose characters when PARMRK is enabled

2012-07-26 Thread Jaeden Amero
When PARMRK is set and large transfers of characters that will get
marked are being received, n_tty could drop data silently (i.e.
without reporting any error to the client). This is because
characters have the potential to take up to three bytes in the line
discipline (when they get marked with parity or framing errors), but
the amount of free space reported to tty_buffer flush_to_ldisc (via
tty->receive_room) is based on the pre-marked data size.

With this patch, the n_tty layer will no longer assume that each byte
will only take up one byte in the line discipline. Instead, it will
make an overly conservative estimate that each byte will take up
three bytes in the line discipline when PARMRK is set.

Signed-off-by: Jaeden Amero 
---
 drivers/tty/n_tty.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
index 101790c..5299cda 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
@@ -92,10 +92,20 @@ static inline int tty_put_user(struct tty_struct *tty, 
unsigned char x,
 
 static void n_tty_set_room(struct tty_struct *tty)
 {
-   /* tty->read_cnt is not read locked ? */
-   int left = N_TTY_BUF_SIZE - tty->read_cnt - 1;
+   int left;
int old_left;
 
+   /* tty->read_cnt is not read locked ? */
+   if (I_PARMRK(tty))
+   {
+   /* Multiply read_cnt by 3, since each byte might take up to
+* three times as many spaces when PARMRK is set (depending on
+* its flags, e.g. parity error). */
+   left = N_TTY_BUF_SIZE - tty->read_cnt * 3 - 1;
+   }
+   else
+   left = N_TTY_BUF_SIZE - tty->read_cnt - 1;
+
/*
 * If we are doing input canonicalization, and there are no
 * pending newlines, let characters through without limit, so
-- 
1.7.11.1

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[PATCH] n_tty: Don't lose characters when PARMRK is enabled

2012-07-26 Thread Jaeden Amero
When PARMRK is set and large transfers of characters that will get
marked are being received, n_tty could drop data silently (i.e.
without reporting any error to the client). This is because
characters have the potential to take up to three bytes in the line
discipline (when they get marked with parity or framing errors), but
the amount of free space reported to tty_buffer flush_to_ldisc (via
tty-receive_room) is based on the pre-marked data size.

With this patch, the n_tty layer will no longer assume that each byte
will only take up one byte in the line discipline. Instead, it will
make an overly conservative estimate that each byte will take up
three bytes in the line discipline when PARMRK is set.

Signed-off-by: Jaeden Amero jaeden.am...@ni.com
---
 drivers/tty/n_tty.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
index 101790c..5299cda 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
@@ -92,10 +92,20 @@ static inline int tty_put_user(struct tty_struct *tty, 
unsigned char x,
 
 static void n_tty_set_room(struct tty_struct *tty)
 {
-   /* tty-read_cnt is not read locked ? */
-   int left = N_TTY_BUF_SIZE - tty-read_cnt - 1;
+   int left;
int old_left;
 
+   /* tty-read_cnt is not read locked ? */
+   if (I_PARMRK(tty))
+   {
+   /* Multiply read_cnt by 3, since each byte might take up to
+* three times as many spaces when PARMRK is set (depending on
+* its flags, e.g. parity error). */
+   left = N_TTY_BUF_SIZE - tty-read_cnt * 3 - 1;
+   }
+   else
+   left = N_TTY_BUF_SIZE - tty-read_cnt - 1;
+
/*
 * If we are doing input canonicalization, and there are no
 * pending newlines, let characters through without limit, so
-- 
1.7.11.1

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