Re: [PATCH v6 00/22] Mediatek MT8192 clock support

[James Liao]

sys.yaml
>  create mode 100644 
> Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
>  create mode 100644 
> Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-aud.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-cam.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-ipe.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-mdp.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-mfg.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-mm.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-scp_adsp.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192-venc.c
>  create mode 100644 drivers/clk/mediatek/clk-mt8192.c
>  create mode 100644 include/dt-bindings/clock/mt8192-clk.h
> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

All patches in this series:

Reviewed-by: James Liao 

[PATCH] arm64: dts: mt8192: Add cpu-idle-states

[James Liao]

Add idle states for cpu-off and cluster-off.

Signed-off-by: James Liao 
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 44 
 1 file changed, 44 insertions(+)

This patch bases on v5.10 and [1], adds idle-states for MT8192 CPUs.

[1] 
https://lore.kernel.org/linux-arm-kernel/20201030092207.26488-2-seiya.w...@mediatek.com/

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024de122..c7f2ec9ea4f1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -39,6 +39,7 @@
reg = <0x000>;
enable-method = "psci";
clock-frequency = <170100>;
+   cpu-idle-states = <_l _l>;
next-level-cache = <_0>;
capacity-dmips-mhz = <530>;
};
@@ -49,6 +50,7 @@
reg = <0x100>;
enable-method = "psci";
clock-frequency = <170100>;
+   cpu-idle-states = <_l _l>;
next-level-cache = <_0>;
capacity-dmips-mhz = <530>;
};
@@ -59,6 +61,7 @@
reg = <0x200>;
enable-method = "psci";
clock-frequency = <170100>;
+   cpu-idle-states = <_l _l>;
next-level-cache = <_0>;
capacity-dmips-mhz = <530>;
};
@@ -69,6 +72,7 @@
reg = <0x300>;
enable-method = "psci";
clock-frequency = <170100>;
+   cpu-idle-states = <_l _l>;
next-level-cache = <_0>;
capacity-dmips-mhz = <530>;
};
@@ -79,6 +83,7 @@
reg = <0x400>;
enable-method = "psci";
clock-frequency = <217100>;
+   cpu-idle-states = <_b _b>;
next-level-cache = <_1>;
capacity-dmips-mhz = <1024>;
};
@@ -89,6 +94,7 @@
reg = <0x500>;
enable-method = "psci";
clock-frequency = <217100>;
+   cpu-idle-states = <_b _b>;
next-level-cache = <_1>;
capacity-dmips-mhz = <1024>;
};
@@ -99,6 +105,7 @@
reg = <0x600>;
enable-method = "psci";
clock-frequency = <217100>;
+   cpu-idle-states = <_b _b>;
next-level-cache = <_1>;
capacity-dmips-mhz = <1024>;
};
@@ -109,6 +116,7 @@
reg = <0x700>;
enable-method = "psci";
clock-frequency = <217100>;
+   cpu-idle-states = <_b _b>;
next-level-cache = <_1>;
capacity-dmips-mhz = <1024>;
};
@@ -158,6 +166,42 @@
l3_0: l3-cache {
compatible = "cache";
};
+
+   idle-states {
+   entry-method = "arm,psci";
+   cpuoff_l: cpuoff_l {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x00010001>;
+   local-timer-stop;
+   entry-latency-us = <55>;
+   exit-latency-us = <140>;
+   min-residency-us = <780>;
+   };
+   cpuoff_b: cpuoff_b {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x00010001>;
+   local-timer-stop;
+   entry-latency-us = <35>;
+   exit-latency-us = <145>;
+   min-residency-us = <720>;
+   };
+   clusteroff_l: clusteroff_l {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x01010002>;
+   local-timer-stop;
+ 

[PATCH] arm64: dts: mt8183: Enable CPU idle-states

[James Liao]

Enable mcdi-cpu and mcdi-cluster on MT8183 CPUs.

Signed-off-by: James Liao 
---
This patch bases on v5.1-rc1 and [1], adds idle-states for MT8183 CPUs.

[1] https://patchwork.kernel.org/patch/10962375/

 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 08274bf..ef4b054 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -56,6 +56,7 @@
compatible = "arm,cortex-a53";
reg = <0x000>;
enable-method = "psci";
+   cpu-idle-states = <_CPU _CLUSTER>;
};
 
cpu1: cpu@1 {
@@ -63,6 +64,7 @@
compatible = "arm,cortex-a53";
reg = <0x001>;
enable-method = "psci";
+   cpu-idle-states = <_CPU _CLUSTER>;
};
 
cpu2: cpu@2 {
@@ -70,6 +72,7 @@
compatible = "arm,cortex-a53";
reg = <0x002>;
enable-method = "psci";
+   cpu-idle-states = <_CPU _CLUSTER>;
};
 
cpu3: cpu@3 {
@@ -77,6 +80,7 @@
compatible = "arm,cortex-a53";
reg = <0x003>;
enable-method = "psci";
+   cpu-idle-states = <_CPU _CLUSTER>;
};
 
cpu4: cpu@100 {
@@ -84,6 +88,7 @@
compatible = "arm,cortex-a73";
reg = <0x100>;
enable-method = "psci";
+   cpu-idle-states = <_CPU _CLUSTER>;
};
 
cpu5: cpu@101 {
@@ -91,6 +96,7 @@
compatible = "arm,cortex-a73";
reg = <0x101>;
enable-method = "psci";
+   cpu-idle-states = <_CPU _CLUSTER>;
};
 
cpu6: cpu@102 {
@@ -98,6 +104,7 @@
compatible = "arm,cortex-a73";
reg = <0x102>;
enable-method = "psci";
+   cpu-idle-states = <_CPU _CLUSTER>;
};
 
cpu7: cpu@103 {
@@ -105,6 +112,29 @@
compatible = "arm,cortex-a73";
reg = <0x103>;
enable-method = "psci";
+   cpu-idle-states = <_CPU _CLUSTER>;
+   };
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   MCDI_CPU: mcdi-cpu {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x00010001>;
+   entry-latency-us = <200>;
+   exit-latency-us = <200>;
+   min-residency-us = <800>;
+   };
+
+   MCDI_CLUSTER: mcdi-cluster {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x01010001>;
+   entry-latency-us = <250>;
+   exit-latency-us = <400>;
+   min-residency-us = <1300>;
+   };
};
};
 
-- 
1.9.1

Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off

[James Liao]

On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: James Liao 
> 
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are off.
> 
> On MT8173 for example, ARMPLL's enable bit can be controlled by
> other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> set ARMPLL's enable bit as 0. In this case, SW may want and can
> still change ARMPLL's rate by changing its pcw and postdiv settings.
> But without this patch, new pcw setting will not be applied because
> its enable bit is 0.
> 
> Signed-off-by: James Liao 
> Acked-by: Michael Turquette 
> Signed-off-by: Weiyi Lu 

Reviewed-by: James Liao 

> ---
>  drivers/clk/mediatek/clk-pll.c | 13 ++---
>  1 file changed, 2 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 65cee1d6c400..8d556fc99fed 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -124,9 +124,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll 
> *pll, u32 pcw,
>   int postdiv)
>  {
>   u32 chg, val;
> - int pll_en;
> -
> - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
>  
>   /* disable tuner */
>   __mtk_pll_tuner_disable(pll);
> @@ -147,12 +144,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll 
> *pll, u32 pcw,
>   pll->data->pcw_shift);
>   val |= pcw << pll->data->pcw_shift;
>   writel(val, pll->pcw_addr);
> -
> - chg = readl(pll->pcw_chg_addr);
> -
> - if (pll_en)
> - chg |= PCW_CHG_MASK;
> -
> + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
>   writel(chg, pll->pcw_chg_addr);
>   if (pll->tuner_addr)
>   writel(val + 1, pll->tuner_addr);
> @@ -160,8 +152,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll 
> *pll, u32 pcw,
>   /* restore tuner_en */
>   __mtk_pll_tuner_enable(pll);
>  
> - if (pll_en)
> - udelay(20);
> + udelay(20);
>  }
>  
>  /*

Re: [PATCH v5 7/9] clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data

[James Liao]

On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> In previous MediaTek PLL design, it assumes the pcw change control
> is always on the CON1 register.
> However, the pcw change bit on MT8183 was moved onto CON0 because
> the the PCW length of audio PLLs are extended to 32-bit.
> Add configurable pcw_chg_reg to set the pcw change control register
> address or using the default control register CON1 if without
> setting in pll data.
> 
> Signed-off-by: Weiyi Lu 

Reviewed-by: James Liao 

> ---
>  drivers/clk/mediatek/clk-mtk.h |  1 +
>  drivers/clk/mediatek/clk-pll.c | 17 +++--
>  2 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 928905496c4b..37ae944548e9 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -221,6 +221,7 @@ struct mtk_pll_data {
>   int pcwibits;
>   uint32_t pcw_reg;
>   int pcw_shift;
> + uint32_t pcw_chg_reg;
>   const struct mtk_pll_div_table *div_table;
>   const char *parent_name;
>  };
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 67aaa3082d9b..65cee1d6c400 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -27,7 +27,7 @@
>  #define CON0_BASE_EN BIT(0)
>  #define CON0_PWR_ON  BIT(0)
>  #define CON0_ISO_EN  BIT(1)
> -#define CON0_PCW_CHG BIT(31)
> +#define PCW_CHG_MASK BIT(31)
>  
>  #define AUDPLL_TUNER_EN  BIT(31)
>  
> @@ -51,6 +51,7 @@ struct mtk_clk_pll {
>   void __iomem*tuner_addr;
>   void __iomem*tuner_en_addr;
>   void __iomem*pcw_addr;
> + void __iomem*pcw_chg_addr;
>   const struct mtk_pll_data *data;
>  };
>  
> @@ -122,7 +123,7 @@ static void __mtk_pll_tuner_disable(struct mtk_clk_pll 
> *pll)
>  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>   int postdiv)
>  {
> - u32 con1, val;
> + u32 chg, val;
>   int pll_en;
>  
>   pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
> @@ -147,14 +148,14 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll 
> *pll, u32 pcw,
>   val |= pcw << pll->data->pcw_shift;
>   writel(val, pll->pcw_addr);
>  
> - con1 = readl(pll->base_addr + REG_CON1);
> + chg = readl(pll->pcw_chg_addr);
>  
>   if (pll_en)
> - con1 |= CON0_PCW_CHG;
> + chg |= PCW_CHG_MASK;
>  
> - writel(con1, pll->base_addr + REG_CON1);
> + writel(chg, pll->pcw_chg_addr);
>   if (pll->tuner_addr)
> - writel(con1 + 1, pll->tuner_addr);
> + writel(val + 1, pll->tuner_addr);
>  
>   /* restore tuner_en */
>   __mtk_pll_tuner_enable(pll);
> @@ -329,6 +330,10 @@ static struct clk *mtk_clk_register_pll(const struct 
> mtk_pll_data *data,
>   pll->pwr_addr = base + data->pwr_reg;
>   pll->pd_addr = base + data->pd_reg;
>   pll->pcw_addr = base + data->pcw_reg;
> + if (data->pcw_chg_reg)
> + pll->pcw_chg_addr = base + data->pcw_chg_reg;
> + else
> + pll->pcw_chg_addr = pll->base_addr + REG_CON1;
>   if (data->tuner_reg)
>   pll->tuner_addr = base + data->tuner_reg;
>   if (data->tuner_en_reg)

Re: [PATCH v5 6/9] clk: mediatek: Add flags support for mtk_gate data

[James Liao]

On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> On some Mediatek platforms, there are critical clocks of
> clock gate type.
> To register clock gate with flags CLK_IS_CRITICAL,
> we need to add the flags field in mtk_gate data and register APIs.
> 
> Signed-off-by: Weiyi Lu 

Reviewed-by: James Liao 

> ---
>  drivers/clk/mediatek/clk-gate.c | 5 +++--
>  drivers/clk/mediatek/clk-gate.h | 3 ++-
>  drivers/clk/mediatek/clk-mtk.c  | 3 ++-
>  drivers/clk/mediatek/clk-mtk.h  | 1 +
>  4 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
> index 934bf0e45e26..85daf826619a 100644
> --- a/drivers/clk/mediatek/clk-gate.c
> +++ b/drivers/clk/mediatek/clk-gate.c
> @@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate(
>   int clr_ofs,
>   int sta_ofs,
>   u8 bit,
> - const struct clk_ops *ops)
> + const struct clk_ops *ops,
> + unsigned long flags)
>  {
>   struct mtk_clk_gate *cg;
>   struct clk *clk;
> @@ -168,7 +169,7 @@ struct clk *mtk_clk_register_gate(
>   return ERR_PTR(-ENOMEM);
>  
>   init.name = name;
> - init.flags = CLK_SET_RATE_PARENT;
> + init.flags = flags | CLK_SET_RATE_PARENT;
>   init.parent_names = parent_name ? _name : NULL;
>   init.num_parents = parent_name ? 1 : 0;
>   init.ops = ops;
> diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
> index 72ef89b3ad7b..9f766dfe1d57 100644
> --- a/drivers/clk/mediatek/clk-gate.h
> +++ b/drivers/clk/mediatek/clk-gate.h
> @@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate(
>   int clr_ofs,
>   int sta_ofs,
>   u8 bit,
> - const struct clk_ops *ops);
> + const struct clk_ops *ops,
> + unsigned long flags);
>  
>  #endif /* __DRV_CLK_GATE_H */
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index 9c0ae4278a94..35359e5397c7 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -130,7 +130,8 @@ int mtk_clk_register_gates(struct device_node *node,
>   gate->regs->set_ofs,
>   gate->regs->clr_ofs,
>   gate->regs->sta_ofs,
> - gate->shift, gate->ops);
> + gate->shift, gate->ops,
> + gate->flags);
>  
>   if (IS_ERR(clk)) {
>   pr_err("Failed to register clk %s: %ld\n",
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 11b5517903d0..928905496c4b 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -158,6 +158,7 @@ struct mtk_gate {
>   const struct mtk_gate_regs *regs;
>   int shift;
>   const struct clk_ops *ops;
> + unsigned long flags;
>  };
>  
>  int mtk_clk_register_gates(struct device_node *node,

Re: [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data

[James Liao]

On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: Owen Chen 
> 
> 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
>add a variable to indicate this change and
>backward-compatible.
> 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
>1.5Ghz, add a variable to indicate platform-dependent.
> 
> Signed-off-by: Owen Chen 
> Signed-off-by: Weiyi Lu 
> Acked-by: Sean Wang 

Reviewed-by: James Liao 

> ---
>  drivers/clk/mediatek/clk-mtk.h |  2 ++
>  drivers/clk/mediatek/clk-pll.c | 15 +++
>  2 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index f83c2bbb677e..11b5517903d0 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -214,8 +214,10 @@ struct mtk_pll_data {
>   unsigned int flags;
>   const struct clk_ops *ops;
>   u32 rst_bar_mask;
> + unsigned long fmin;
>   unsigned long fmax;
>   int pcwbits;
> + int pcwibits;
>   uint32_t pcw_reg;
>   int pcw_shift;
>   const struct mtk_pll_div_table *div_table;
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 18842d660317..67aaa3082d9b 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -32,6 +32,8 @@
>  #define AUDPLL_TUNER_EN  BIT(31)
>  
>  #define POSTDIV_MASK 0x7
> +
> +/* default 7 bits integer, can be overridden with pcwibits. */
>  #define INTEGER_BITS 7
>  
>  /*
> @@ -68,12 +70,15 @@ static unsigned long __mtk_pll_recalc_rate(struct 
> mtk_clk_pll *pll, u32 fin,
>   u32 pcw, int postdiv)
>  {
>   int pcwbits = pll->data->pcwbits;
> - int pcwfbits;
> + int pcwfbits = 0;
> + int ibits;
>   u64 vco;
>   u8 c = 0;
>  
>   /* The fractional part of the PLL divider. */
> - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
> + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
> + if (pcwbits > ibits)
> + pcwfbits = pcwbits - ibits;
>  
>   vco = (u64)fin * pcw;
>  
> @@ -170,9 +175,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll 
> *pll, u32 pcw,
>  static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 
> *postdiv,
>   u32 freq, u32 fin)
>  {
> - unsigned long fmin = 1000 * MHZ;
> + unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
>   const struct mtk_pll_div_table *div_table = pll->data->div_table;
>   u64 _pcw;
> + int ibits;
>   u32 val;
>  
>   if (freq > pll->data->fmax)
> @@ -196,7 +202,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, 
> u32 *pcw, u32 *postdiv,
>   }
>  
>   /* _pcw = freq * postdiv / fin * 2^pcwfbits */
> - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
> + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
> + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
>   do_div(_pcw, fin);
>  
>   *pcw = (u32)_pcw;

Re: [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate

[James Liao]

On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: Owen Chen 
> 
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be restored after new settings applied.
> 
> Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
> Cc: 
> Signed-off-by: Owen Chen 
> Signed-off-by: Weiyi Lu 

Reviewed-by: James Liao 

> ---
>  drivers/clk/mediatek/clk-pll.c | 48 --
>  1 file changed, 34 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index f54e4015b0b1..18842d660317 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct 
> mtk_clk_pll *pll, u32 fin,
>   return ((unsigned long)vco + postdiv - 1) / postdiv;
>  }
>  
> +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
> +{
> + u32 r;
> +
> + if (pll->tuner_en_addr) {
> + r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> + writel(r, pll->tuner_en_addr);
> + } else if (pll->tuner_addr) {
> + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> + writel(r, pll->tuner_addr);
> + }
> +}
> +
> +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
> +{
> + u32 r;
> +
> + if (pll->tuner_en_addr) {
> + r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> + writel(r, pll->tuner_en_addr);
> + } else if (pll->tuner_addr) {
> + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> + writel(r, pll->tuner_addr);
> + }
> +}
> +
>  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>   int postdiv)
>  {
> @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, 
> u32 pcw,
>  
>   pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
>  
> + /* disable tuner */
> + __mtk_pll_tuner_disable(pll);
> +
>   /* set postdiv */
>   val = readl(pll->pd_addr);
>   val &= ~(POSTDIV_MASK << pll->data->pd_shift);
> @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll 
> *pll, u32 pcw,
>   if (pll->tuner_addr)
>   writel(con1 + 1, pll->tuner_addr);
>  
> + /* restore tuner_en */
> + __mtk_pll_tuner_enable(pll);
> +
>   if (pll_en)
>   udelay(20);
>  }
> @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
>   r |= pll->data->en_mask;
>   writel(r, pll->base_addr + REG_CON0);
>  
> - if (pll->tuner_en_addr) {
> - r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> - writel(r, pll->tuner_en_addr);
> - } else if (pll->tuner_addr) {
> - r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> - writel(r, pll->tuner_addr);
> - }
> + __mtk_pll_tuner_enable(pll);
>  
>   udelay(20);
>  
> @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
>   writel(r, pll->base_addr + REG_CON0);
>   }
>  
> - if (pll->tuner_en_addr) {
> - r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> - writel(r, pll->tuner_en_addr);
> - } else if (pll->tuner_addr) {
> - r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> - writel(r, pll->tuner_addr);
> - }
> + __mtk_pll_tuner_disable(pll);
>  
>   r = readl(pll->base_addr + REG_CON0);
>   r &= ~CON0_BASE_EN;

Re: [PATCH v5 2/9] clk: mediatek: Add new clkmux register API

[James Liao]

On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: Owen Chen 
> 
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new API to handle this hw change with
> a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
> 
> Signed-off-by: Owen Chen 
> Signed-off-by: Weiyi Lu 

Reviewed-by: James Liao 

> ---
>  drivers/clk/mediatek/Makefile  |   3 +-
>  drivers/clk/mediatek/clk-mux.c | 223 +
>  drivers/clk/mediatek/clk-mux.h |  89 +
>  3 files changed, 314 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mux.c
>  create mode 100644 drivers/clk/mediatek/clk-mux.h
> 
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index ee4410ff43ab..20cf9eea4171 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -1,5 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o 
> clk-apmixed.o clk-cpumux.o reset.o
> +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o 
> clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
> +
>  obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
>  obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
>  obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
> diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
> new file mode 100644
> index ..877a883fa616
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mux.c
> @@ -0,0 +1,223 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +
> +static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
> +{
> + return container_of(hw, struct mtk_clk_mux, hw);
> +}
> +
> +static int mtk_clk_mux_enable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = BIT(mux->data->gate_shift);
> +
> + return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
> + mask, ~mask);
> +}
> +
> +static void mtk_clk_mux_disable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = BIT(mux->data->gate_shift);
> +
> + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
> +}
> +
> +static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> +
> + return regmap_write(mux->regmap, mux->data->clr_ofs,
> + BIT(mux->data->gate_shift));
> +}
> +
> +static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> +
> + regmap_write(mux->regmap, mux->data->set_ofs,
> + BIT(mux->data->gate_shift));
> +}
> +
> +static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 val;
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, );
> +
> + return (val & BIT(mux->data->gate_shift)) == 0;
> +}
> +
> +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + u32 val;
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, );
> + val = (val >> mux->data->mux_shift) & mask;
> +
> + return val;
> +}
> +
> +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + unsigned long flags;
> +
> + if (mux->lock)
> + spin_lock_irqsave(mux->lock, flags);
> + else
> + __acquire(mux->lock);
> +
> + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
> + index << mux->data->mux_shift);
> +
> + if (mux->lock)
> + spin_unlock_irqrestore(mux->lock, flags);
> + else
> + __release(mux->lock);
> +
> + return 0;
> +}
> +
> +static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
&

[PATCH v2] arm64: dts: mediatek: Add cpuidle support for MT2712

[James Liao]

Add CPU idle state nodes to enable C1/C2 idle states.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
---

changes since v1:
- Rebase to 4.14-rc1.

 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 57d0396..5d4e406 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -39,6 +39,7 @@
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x000>;
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
};
 
cpu1: cpu@1 {
@@ -46,6 +47,7 @@
compatible = "arm,cortex-a35";
reg = <0x001>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
};
 
cpu2: cpu@200 {
@@ -53,6 +55,29 @@
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
+   };
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   entry-latency-us = <100>;
+   exit-latency-us = <80>;
+   min-residency-us = <2000>;
+   arm,psci-suspend-param = <0x001>;
+   };
+
+   CLUSTER_SLEEP_0: cluster-sleep-0 {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   entry-latency-us = <350>;
+   exit-latency-us = <80>;
+   min-residency-us = <3000>;
+   arm,psci-suspend-param = <0x101>;
+   };
};
};
 
-- 
1.9.1

[PATCH v2] arm64: dts: mediatek: Add cpuidle support for MT2712

[James Liao]

Add CPU idle state nodes to enable C1/C2 idle states.

Signed-off-by: James Liao 
---

changes since v1:
- Rebase to 4.14-rc1.

 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 57d0396..5d4e406 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -39,6 +39,7 @@
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x000>;
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
};
 
cpu1: cpu@1 {
@@ -46,6 +47,7 @@
compatible = "arm,cortex-a35";
reg = <0x001>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
};
 
cpu2: cpu@200 {
@@ -53,6 +55,29 @@
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
+   };
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   entry-latency-us = <100>;
+   exit-latency-us = <80>;
+   min-residency-us = <2000>;
+   arm,psci-suspend-param = <0x001>;
+   };
+
+   CLUSTER_SLEEP_0: cluster-sleep-0 {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   entry-latency-us = <350>;
+   exit-latency-us = <80>;
+   min-residency-us = <3000>;
+   arm,psci-suspend-param = <0x101>;
+   };
};
};
 
-- 
1.9.1

[PATCH] arm64: dts: mediatek: Add cpuidle support for MT2712

[James Liao]

Add CPU idle state nodes to enable C1/C2 idle states.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
---
This patch bases on latest Matthias v4.13-next/dts64 branch [1],
add CPU idle states for MT2712.

[1] https://github.com/mbgg/linux-mediatek.git

 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 57d0396..5d4e406 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -39,6 +39,7 @@
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x000>;
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
};
 
cpu1: cpu@1 {
@@ -46,6 +47,7 @@
compatible = "arm,cortex-a35";
reg = <0x001>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
};
 
cpu2: cpu@200 {
@@ -53,6 +55,29 @@
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
+   };
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   entry-latency-us = <100>;
+   exit-latency-us = <80>;
+   min-residency-us = <2000>;
+   arm,psci-suspend-param = <0x001>;
+   };
+
+   CLUSTER_SLEEP_0: cluster-sleep-0 {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   entry-latency-us = <350>;
+   exit-latency-us = <80>;
+   min-residency-us = <3000>;
+   arm,psci-suspend-param = <0x101>;
+   };
};
};
 
-- 
1.9.1

[PATCH] arm64: dts: mediatek: Add cpuidle support for MT2712

[James Liao]

Add CPU idle state nodes to enable C1/C2 idle states.

Signed-off-by: James Liao 
---
This patch bases on latest Matthias v4.13-next/dts64 branch [1],
add CPU idle states for MT2712.

[1] https://github.com/mbgg/linux-mediatek.git

 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 57d0396..5d4e406 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -39,6 +39,7 @@
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x000>;
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
};
 
cpu1: cpu@1 {
@@ -46,6 +47,7 @@
compatible = "arm,cortex-a35";
reg = <0x001>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
};
 
cpu2: cpu@200 {
@@ -53,6 +55,29 @@
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0 _SLEEP_0>;
+   };
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   entry-latency-us = <100>;
+   exit-latency-us = <80>;
+   min-residency-us = <2000>;
+   arm,psci-suspend-param = <0x001>;
+   };
+
+   CLUSTER_SLEEP_0: cluster-sleep-0 {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   entry-latency-us = <350>;
+   exit-latency-us = <80>;
+   min-residency-us = <3000>;
+   arm,psci-suspend-param = <0x101>;
+   };
};
};
 
-- 
1.9.1

Re: [PATCH] clk: Convert to using %pOF instead of full_name

[James Liao]

On Tue, 2017-07-18 at 16:42 -0500, Rob Herring wrote:
> Now that we have a custom printf format specifier, convert users of
> full_name to use %pOF instead. This is preparation to remove storing
> of the full path string for each node.
> 
> ---
>  drivers/clk/mediatek/clk-cpumux.c|  2 +-
>  drivers/clk/mediatek/clk-mtk.c   |  2 +-
>  drivers/clk/mediatek/reset.c |  2 +-

For clk/mediatek:
Acked-by: James Liao <jamesjj.l...@mediatek.com>


Best regards,

James

Re: [PATCH] clk: Convert to using %pOF instead of full_name

[James Liao]

On Tue, 2017-07-18 at 16:42 -0500, Rob Herring wrote:
> Now that we have a custom printf format specifier, convert users of
> full_name to use %pOF instead. This is preparation to remove storing
> of the full path string for each node.
> 
> ---
>  drivers/clk/mediatek/clk-cpumux.c|  2 +-
>  drivers/clk/mediatek/clk-mtk.c   |  2 +-
>  drivers/clk/mediatek/reset.c |  2 +-

For clk/mediatek:
Acked-by: James Liao 


Best regards,

James

[PATCH 1/3] arm: dts: mt2701: Sort DT nodes by register address

[James Liao]

This patch rearrange MT2701 DT nodes to keep them in ascending order.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4..73f4b7c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -96,24 +96,6 @@
 ;
};
 
-   pio: pinctrl@10005000 {
-   compatible = "mediatek,mt2701-pinctrl";
-   reg = <0 0x1000b000 0 0x1000>;
-   mediatek,pctl-regmap = <_pctl_a>;
-   pins-are-numbered;
-   gpio-controller;
-   #gpio-cells = <2>;
-   interrupt-controller;
-   #interrupt-cells = <2>;
-   interrupts = ,
-;
-   };
-
-   syscfg_pctl_a: syscfg@10005000 {
-   compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
-   reg = <0 0x10005000 0 0x1000>;
-   };
-
topckgen: syscon@1000 {
compatible = "mediatek,mt2701-topckgen", "syscon";
reg = <0 0x1000 0 0x1000>;
@@ -134,6 +116,24 @@
#reset-cells = <1>;
};
 
+   pio: pinctrl@10005000 {
+   compatible = "mediatek,mt2701-pinctrl";
+   reg = <0 0x1000b000 0 0x1000>;
+   mediatek,pctl-regmap = <_pctl_a>;
+   pins-are-numbered;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = ,
+;
+   };
+
+   syscfg_pctl_a: syscfg@10005000 {
+   compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
+   reg = <0 0x10005000 0 0x1000>;
+   };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
 "mediatek,mt6589-wdt";
-- 
1.9.1

[PATCH 0/3] Add clock and power domain DT nodes for Mediatek MT2701

[James Liao]

This patch series base on v4.10-rc1, include MT2701 power domain and clock
DT nodes.

An early patch [1] which was not applied in v4.10-rc1 also included in this
patch series.

[1] https://patchwork.kernel.org/patch/9457625/

James Liao (3):
  arm: dts: mt2701: Sort DT nodes by register address
  arm: dts: mt2701: Add subsystem clock controller device nodes
  arm: dts: mt2701: Add power domain controller device node

 arch/arm/boot/dts/mt2701.dtsi | 84 +--
 1 file changed, 66 insertions(+), 18 deletions(-)

--
1.9.1

[PATCH 1/3] arm: dts: mt2701: Sort DT nodes by register address

[James Liao]

This patch rearrange MT2701 DT nodes to keep them in ascending order.

Signed-off-by: James Liao 
---
 arch/arm/boot/dts/mt2701.dtsi | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4..73f4b7c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -96,24 +96,6 @@
 ;
};
 
-   pio: pinctrl@10005000 {
-   compatible = "mediatek,mt2701-pinctrl";
-   reg = <0 0x1000b000 0 0x1000>;
-   mediatek,pctl-regmap = <_pctl_a>;
-   pins-are-numbered;
-   gpio-controller;
-   #gpio-cells = <2>;
-   interrupt-controller;
-   #interrupt-cells = <2>;
-   interrupts = ,
-;
-   };
-
-   syscfg_pctl_a: syscfg@10005000 {
-   compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
-   reg = <0 0x10005000 0 0x1000>;
-   };
-
topckgen: syscon@1000 {
compatible = "mediatek,mt2701-topckgen", "syscon";
reg = <0 0x1000 0 0x1000>;
@@ -134,6 +116,24 @@
#reset-cells = <1>;
};
 
+   pio: pinctrl@10005000 {
+   compatible = "mediatek,mt2701-pinctrl";
+   reg = <0 0x1000b000 0 0x1000>;
+   mediatek,pctl-regmap = <_pctl_a>;
+   pins-are-numbered;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = ,
+;
+   };
+
+   syscfg_pctl_a: syscfg@10005000 {
+   compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
+   reg = <0 0x10005000 0 0x1000>;
+   };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
 "mediatek,mt6589-wdt";
-- 
1.9.1

[PATCH 0/3] Add clock and power domain DT nodes for Mediatek MT2701

[James Liao]

This patch series base on v4.10-rc1, include MT2701 power domain and clock
DT nodes.

An early patch [1] which was not applied in v4.10-rc1 also included in this
patch series.

[1] https://patchwork.kernel.org/patch/9457625/

James Liao (3):
  arm: dts: mt2701: Sort DT nodes by register address
  arm: dts: mt2701: Add subsystem clock controller device nodes
  arm: dts: mt2701: Add power domain controller device node

 arch/arm/boot/dts/mt2701.dtsi | 84 +--
 1 file changed, 66 insertions(+), 18 deletions(-)

--
1.9.1

[PATCH 3/3] arm: dts: mt2701: Add power domain controller device node

[James Liao]

Add power domain controller node (scpsys) for MT2701.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 150c48d..bdf8954 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -13,6 +13,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -134,6 +135,17 @@
reg = <0 0x10005000 0 0x1000>;
};
 
+   scpsys: scpsys@10006000 {
+   compatible = "mediatek,mt2701-scpsys", "syscon";
+   #power-domain-cells = <1>;
+   reg = <0 0x10006000 0 0x1000>;
+   infracfg = <>;
+   clocks = < CLK_TOP_MM_SEL>,
+< CLK_TOP_MFG_SEL>,
+< CLK_TOP_ETHIF_SEL>;
+   clock-names = "mm", "mfg", "ethif";
+   };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
 "mediatek,mt6589-wdt";
-- 
1.9.1

[PATCH 2/3] arm: dts: mt2701: Add subsystem clock controller device nodes

[James Liao]

Add MT2701 subsystem clock controllers, inlcude mmsys, imgsys,
vdecsys, hifsys, ethsys and bdpsys.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 73f4b7c..150c48d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -214,4 +214,40 @@
clock-names = "baud", "bus";
status = "disabled";
};
+
+   mmsys: syscon@1400 {
+   compatible = "mediatek,mt2701-mmsys", "syscon";
+   reg = <0 0x1400 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   imgsys: syscon@1500 {
+   compatible = "mediatek,mt2701-imgsys", "syscon";
+   reg = <0 0x1500 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   vdecsys: syscon@1600 {
+   compatible = "mediatek,mt2701-vdecsys", "syscon";
+   reg = <0 0x1600 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   hifsys: syscon@1a00 {
+   compatible = "mediatek,mt2701-hifsys", "syscon";
+   reg = <0 0x1a00 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   ethsys: syscon@1b00 {
+   compatible = "mediatek,mt2701-ethsys", "syscon";
+   reg = <0 0x1b00 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   bdpsys: syscon@1c00 {
+   compatible = "mediatek,mt2701-bdpsys", "syscon";
+   reg = <0 0x1c00 0 0x1000>;
+   #clock-cells = <1>;
+   };
 };
-- 
1.9.1

[PATCH 3/3] arm: dts: mt2701: Add power domain controller device node

[James Liao]

Add power domain controller node (scpsys) for MT2701.

Signed-off-by: James Liao 
---
 arch/arm/boot/dts/mt2701.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 150c48d..bdf8954 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -13,6 +13,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -134,6 +135,17 @@
reg = <0 0x10005000 0 0x1000>;
};
 
+   scpsys: scpsys@10006000 {
+   compatible = "mediatek,mt2701-scpsys", "syscon";
+   #power-domain-cells = <1>;
+   reg = <0 0x10006000 0 0x1000>;
+   infracfg = <>;
+   clocks = < CLK_TOP_MM_SEL>,
+< CLK_TOP_MFG_SEL>,
+< CLK_TOP_ETHIF_SEL>;
+   clock-names = "mm", "mfg", "ethif";
+   };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
 "mediatek,mt6589-wdt";
-- 
1.9.1

[PATCH 2/3] arm: dts: mt2701: Add subsystem clock controller device nodes

[James Liao]

Add MT2701 subsystem clock controllers, inlcude mmsys, imgsys,
vdecsys, hifsys, ethsys and bdpsys.

Signed-off-by: James Liao 
---
 arch/arm/boot/dts/mt2701.dtsi | 36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 73f4b7c..150c48d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -214,4 +214,40 @@
clock-names = "baud", "bus";
status = "disabled";
};
+
+   mmsys: syscon@1400 {
+   compatible = "mediatek,mt2701-mmsys", "syscon";
+   reg = <0 0x1400 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   imgsys: syscon@1500 {
+   compatible = "mediatek,mt2701-imgsys", "syscon";
+   reg = <0 0x1500 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   vdecsys: syscon@1600 {
+   compatible = "mediatek,mt2701-vdecsys", "syscon";
+   reg = <0 0x1600 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   hifsys: syscon@1a00 {
+   compatible = "mediatek,mt2701-hifsys", "syscon";
+   reg = <0 0x1a00 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   ethsys: syscon@1b00 {
+   compatible = "mediatek,mt2701-ethsys", "syscon";
+   reg = <0 0x1b00 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   bdpsys: syscon@1c00 {
+   compatible = "mediatek,mt2701-bdpsys", "syscon";
+   reg = <0 0x1c00 0 0x1000>;
+   #clock-cells = <1>;
+   };
 };
-- 
1.9.1

[PATCH] arm: dts: mt2701: Sort DT nodes by register address

[James Liao]

This patch rearrange MT2701 DT nodes to keep them in ascending order.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
---
This patch is based on latest v4.9-next/dts branch of [1], to fix MT2701
DT nodes ordering.

[1] https://github.com/mbgg/linux-mediatek/tree/v4.9-next/dts

 arch/arm/boot/dts/mt2701.dtsi | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4..73f4b7c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -96,24 +96,6 @@
 ;
};
 
-   pio: pinctrl@10005000 {
-   compatible = "mediatek,mt2701-pinctrl";
-   reg = <0 0x1000b000 0 0x1000>;
-   mediatek,pctl-regmap = <_pctl_a>;
-   pins-are-numbered;
-   gpio-controller;
-   #gpio-cells = <2>;
-   interrupt-controller;
-   #interrupt-cells = <2>;
-   interrupts = ,
-;
-   };
-
-   syscfg_pctl_a: syscfg@10005000 {
-   compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
-   reg = <0 0x10005000 0 0x1000>;
-   };
-
topckgen: syscon@1000 {
compatible = "mediatek,mt2701-topckgen", "syscon";
reg = <0 0x1000 0 0x1000>;
@@ -134,6 +116,24 @@
#reset-cells = <1>;
};
 
+   pio: pinctrl@10005000 {
+   compatible = "mediatek,mt2701-pinctrl";
+   reg = <0 0x1000b000 0 0x1000>;
+   mediatek,pctl-regmap = <_pctl_a>;
+   pins-are-numbered;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = ,
+;
+   };
+
+   syscfg_pctl_a: syscfg@10005000 {
+   compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
+   reg = <0 0x10005000 0 0x1000>;
+   };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
 "mediatek,mt6589-wdt";
-- 
1.9.1

[PATCH] arm: dts: mt2701: Sort DT nodes by register address

[James Liao]

This patch rearrange MT2701 DT nodes to keep them in ascending order.

Signed-off-by: James Liao 
---
This patch is based on latest v4.9-next/dts branch of [1], to fix MT2701
DT nodes ordering.

[1] https://github.com/mbgg/linux-mediatek/tree/v4.9-next/dts

 arch/arm/boot/dts/mt2701.dtsi | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4..73f4b7c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -96,24 +96,6 @@
 ;
};
 
-   pio: pinctrl@10005000 {
-   compatible = "mediatek,mt2701-pinctrl";
-   reg = <0 0x1000b000 0 0x1000>;
-   mediatek,pctl-regmap = <_pctl_a>;
-   pins-are-numbered;
-   gpio-controller;
-   #gpio-cells = <2>;
-   interrupt-controller;
-   #interrupt-cells = <2>;
-   interrupts = ,
-;
-   };
-
-   syscfg_pctl_a: syscfg@10005000 {
-   compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
-   reg = <0 0x10005000 0 0x1000>;
-   };
-
topckgen: syscon@1000 {
compatible = "mediatek,mt2701-topckgen", "syscon";
reg = <0 0x1000 0 0x1000>;
@@ -134,6 +116,24 @@
#reset-cells = <1>;
};
 
+   pio: pinctrl@10005000 {
+   compatible = "mediatek,mt2701-pinctrl";
+   reg = <0 0x1000b000 0 0x1000>;
+   mediatek,pctl-regmap = <_pctl_a>;
+   pins-are-numbered;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = ,
+;
+   };
+
+   syscfg_pctl_a: syscfg@10005000 {
+   compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
+   reg = <0 0x10005000 0 0x1000>;
+   };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
 "mediatek,mt6589-wdt";
-- 
1.9.1

[PATCH v3] clk: mediatek: Allow changing PLL rate when it is off

[James Liao]

Some modules may need to change its clock rate before turn on it.
So changing PLL's rate when it is off should be allowed.
This patch removes PLL enabled check before set rate, so that
PLLs can set new frequency even if they are off.

On MT8173 for example, ARMPLL's enable bit can be controlled by
other HW. That means ARMPLL may be turned on even if we (CPU / SW)
set ARMPLL's enable bit as 0. In this case, SW may want and can
still change ARMPLL's rate by changing its pcw and postdiv settings.
But without this patch, new pcw setting will not be applied because
its enable bit is 0.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Acked-by: Michael Turquette <mturuqe...@baylibre.com>
---
Please refer to previous comments in [1] and [2].

changes since v2:
- Rebase to v4.9-rc1.

changes since v1:
- Add more explanation in commit messages.

[1] https://patchwork.kernel.org/patch/7983221/
[2] https://patchwork.kernel.org/patch/7998891/

 drivers/clk/mediatek/clk-pll.c | 9 ++---
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 0c2deac..80f57b4 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -91,9 +91,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, 
u32 pcw,
int postdiv)
 {
u32 con1, val;
-   int pll_en;
-
-   pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
 
/* set postdiv */
val = readl(pll->pd_addr);
@@ -114,15 +111,13 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll 
*pll, u32 pcw,
 
con1 = readl(pll->base_addr + REG_CON1);
 
-   if (pll_en)
-   con1 |= CON0_PCW_CHG;
+   con1 |= CON0_PCW_CHG;
 
writel(con1, pll->base_addr + REG_CON1);
if (pll->tuner_addr)
writel(con1 + 1, pll->tuner_addr);
 
-   if (pll_en)
-   udelay(20);
+   udelay(20);
 }
 
 /*
-- 
1.9.1

[PATCH v3] clk: mediatek: Allow changing PLL rate when it is off

[James Liao]

Some modules may need to change its clock rate before turn on it.
So changing PLL's rate when it is off should be allowed.
This patch removes PLL enabled check before set rate, so that
PLLs can set new frequency even if they are off.

On MT8173 for example, ARMPLL's enable bit can be controlled by
other HW. That means ARMPLL may be turned on even if we (CPU / SW)
set ARMPLL's enable bit as 0. In this case, SW may want and can
still change ARMPLL's rate by changing its pcw and postdiv settings.
But without this patch, new pcw setting will not be applied because
its enable bit is 0.

Signed-off-by: James Liao 
Acked-by: Michael Turquette 
---
Please refer to previous comments in [1] and [2].

changes since v2:
- Rebase to v4.9-rc1.

changes since v1:
- Add more explanation in commit messages.

[1] https://patchwork.kernel.org/patch/7983221/
[2] https://patchwork.kernel.org/patch/7998891/

 drivers/clk/mediatek/clk-pll.c | 9 ++---
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 0c2deac..80f57b4 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -91,9 +91,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, 
u32 pcw,
int postdiv)
 {
u32 con1, val;
-   int pll_en;
-
-   pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
 
/* set postdiv */
val = readl(pll->pd_addr);
@@ -114,15 +111,13 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll 
*pll, u32 pcw,
 
con1 = readl(pll->base_addr + REG_CON1);
 
-   if (pll_en)
-   con1 |= CON0_PCW_CHG;
+   con1 |= CON0_PCW_CHG;
 
writel(con1, pll->base_addr + REG_CON1);
if (pll->tuner_addr)
writel(con1 + 1, pll->tuner_addr);
 
-   if (pll_en)
-   udelay(20);
+   udelay(20);
 }
 
 /*
-- 
1.9.1

Re: [PATCH v14 1/4] clk: mediatek: Add MT2701 clock support

[James Liao]

Hi Stephen,

On Mon, 2016-10-31 at 11:06 -0700, Stephen Boyd wrote:
> On 10/31, James Liao wrote:
> > On Thu, 2016-10-27 at 18:17 -0700, Stephen Boyd wrote:
> > > On 10/21, Erin Lo wrote:
> > > > @@ -244,3 +256,31 @@ void mtk_clk_register_composites(const struct 
> > > > mtk_composite *mcs,
> > > > clk_data->clks[mc->id] = clk;
> > > > }
> > > >  }
> > > > +
> > > > +void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
> > > > +   int num, void __iomem *base, spinlock_t *lock,
> > > > +   struct clk_onecell_data *clk_data)
> > > > +{
> > > > +   struct clk *clk;
> > > > +   int i;
> > > > +
> > > > +   for (i = 0; i <  num; i++) {
> > > > +   const struct mtk_clk_divider *mcd = [i];
> > > > +
> > > > +   if (clk_data && 
> > > > !IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
> > > 
> > > NULL is a valid clk. IS_ERR_OR_NULL is usually wrong.
> > 
> > Why NULL is a valid clk?
> 
> Perhaps at some point we'll want to return a NULL pointer to
> clk_get() callers so that they can handle things like optional
> clocks easily without having any storage requirements. I don't
> know if we'll ever do that, but that's just a possibility.
> 
> > 
> > clk_data is designed for multiple initialization from different clock
> > types, such as infra_clk_data in clk-mt2701.c. So it will ignore valid
> > clocks to avoid duplicated clock registration. Here I assume a clock
> > pointer with error code or NULL to be an invalid (not initialized)
> > clock.
> > 
> 
> Ok. Would it be possible to initialize the array with all error
> pointers? That would make things less error prone, but it

Yes. Current mtk_alloc_clk_data() implementation init all elements with
ERR_PTR(-ENOENT). 

> probably doesn't matter at all anyway because this is done during
> registration time. IS_ERR_OR_NULL makes me take a second look
> each time, because it's usually wrong.

I see. Although currently all Mediatek clk drivers use
mtk_alloc_clk_data() to allocate clk_data, I would like to keep the
flexibility to support zero-initialized clk_data such as a static
structure. So I prefer to treat a NULL pointer as an uninitialized
clock.


Best regards,

James

Re: [PATCH v14 1/4] clk: mediatek: Add MT2701 clock support

[James Liao]

Hi Stephen,

On Mon, 2016-10-31 at 11:06 -0700, Stephen Boyd wrote:
> On 10/31, James Liao wrote:
> > On Thu, 2016-10-27 at 18:17 -0700, Stephen Boyd wrote:
> > > On 10/21, Erin Lo wrote:
> > > > @@ -244,3 +256,31 @@ void mtk_clk_register_composites(const struct 
> > > > mtk_composite *mcs,
> > > > clk_data->clks[mc->id] = clk;
> > > > }
> > > >  }
> > > > +
> > > > +void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
> > > > +   int num, void __iomem *base, spinlock_t *lock,
> > > > +   struct clk_onecell_data *clk_data)
> > > > +{
> > > > +   struct clk *clk;
> > > > +   int i;
> > > > +
> > > > +   for (i = 0; i <  num; i++) {
> > > > +   const struct mtk_clk_divider *mcd = [i];
> > > > +
> > > > +   if (clk_data && 
> > > > !IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
> > > 
> > > NULL is a valid clk. IS_ERR_OR_NULL is usually wrong.
> > 
> > Why NULL is a valid clk?
> 
> Perhaps at some point we'll want to return a NULL pointer to
> clk_get() callers so that they can handle things like optional
> clocks easily without having any storage requirements. I don't
> know if we'll ever do that, but that's just a possibility.
> 
> > 
> > clk_data is designed for multiple initialization from different clock
> > types, such as infra_clk_data in clk-mt2701.c. So it will ignore valid
> > clocks to avoid duplicated clock registration. Here I assume a clock
> > pointer with error code or NULL to be an invalid (not initialized)
> > clock.
> > 
> 
> Ok. Would it be possible to initialize the array with all error
> pointers? That would make things less error prone, but it

Yes. Current mtk_alloc_clk_data() implementation init all elements with
ERR_PTR(-ENOENT). 

> probably doesn't matter at all anyway because this is done during
> registration time. IS_ERR_OR_NULL makes me take a second look
> each time, because it's usually wrong.

I see. Although currently all Mediatek clk drivers use
mtk_alloc_clk_data() to allocate clk_data, I would like to keep the
flexibility to support zero-initialized clk_data such as a static
structure. So I prefer to treat a NULL pointer as an uninitialized
clock.


Best regards,

James

Re: [PATCH v14 1/4] clk: mediatek: Add MT2701 clock support

[James Liao]

Hi Stephen,

On Thu, 2016-10-27 at 18:17 -0700, Stephen Boyd wrote:
> On 10/21, Erin Lo wrote:
> > diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c 
> > b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > new file mode 100644
> > index 000..dbf6ab2
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > @@ -0,0 +1,148 @@
> > +
> > +static int mtk_bdpsys_init(struct platform_device *pdev)
> > +{
> > +   struct clk_onecell_data *clk_data;
> > +   int r;
> > +   struct device_node *node = pdev->dev.of_node;
> > +
> > +   clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
> > +
> > +   mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
> > +   clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +
> > +   return r;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt2701_bdp[] = {
> > +   { .compatible = "mediatek,mt2701-bdpsys", },
> > +   {}
> > +};
> > +
> > +static int clk_mt2701_bdp_probe(struct platform_device *pdev)
> > +{
> > +   int r;
> > +
> > +   r = mtk_bdpsys_init(pdev);
> 
> Why not just put the contents of that function here? I don't see
> the point of this.

Because of some historical reasons, we keep mtk_bdpsys_init() for
changing init points between CLK_OF_DECLARE() and probe() more easily. I
can move all contents from mtk_bdpsys_init() here in next patch.

> > +   if (r) {
> > +   dev_err(>dev,
> > +   "could not register clock provider: %s: %d\n",
> > +   pdev->name, r);
> > +   }
> > +
> > +   return r;
> > +}
> > +
> > +static struct platform_driver clk_mt2701_bdp_drv = {
> > +   .probe = clk_mt2701_bdp_probe,
> > +   .driver = {
> > +   .name = "clk-mt2701-bdp",
> > +   .of_match_table = of_match_clk_mt2701_bdp,
> > +   },
> > +};
> > +
> > +builtin_platform_driver(clk_mt2701_bdp_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c 
> > b/drivers/clk/mediatek/clk-mt2701-eth.c
> > new file mode 100644
> > index 000..b2a71a4
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701-eth.c
> > @@ -0,0 +1,90 @@
> > +/*
> > + * Copyright (c) 2014 MediaTek Inc.
> > + * Author: Shunli Wang 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include 
> > +
> > +static const struct mtk_gate_regs eth_cg_regs = {
> > +   .sta_ofs = 0x0030,
> > +};
> > +
> > +#define GATE_ETH(_id, _name, _parent, _shift) {\
> > +   .id = _id,  \
> > +   .name = _name,  \
> > +   .parent_name = _parent, \
> > +   .regs = _cg_regs,   \
> > +   .shift = _shift,\
> > +   .ops = _clk_gate_ops_no_setclr_inv, \
> > +   }
> > +
> > +static const struct mtk_gate eth_clks[] = {
> > +   GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
> > +   GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
> > +   GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
> > +   GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
> > +   GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
> > +   GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
> > +   GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
> > +   GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
> > +};
> > +
> > +static int mtk_ethsys_init(struct platform_device *pdev)
> > +{
> > +   struct clk_onecell_data *clk_data;
> > +   int r;
> > +   struct device_node *node = pdev->dev.of_node;
> > +
> > +   clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
> > +
> > +   mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
> > +   clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +
> > +   return r;
> 
> Just return of_clk_add_provider() please.

I'll change it in next patch.

> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt2701_eth[] = {
> > +   { .compatible = "mediatek,mt2701-ethsys", },
> > +   {}
> > +};
> > +
> > +static int clk_mt2701_eth_probe(struct platform_device *pdev)
> > +{
> > +   int r;
> > +
> > +   r = mtk_ethsys_init(pdev);
> 
> Same comment.

Okay.

> > +   if (r) {
> > +   dev_err(>dev,
> > +   "could not register clock provider: %s: %d\n",
> > +   pdev->name, r);
> > +   }
> > +
> 

Re: [PATCH v14 1/4] clk: mediatek: Add MT2701 clock support

[James Liao]

Hi Stephen,

On Thu, 2016-10-27 at 18:17 -0700, Stephen Boyd wrote:
> On 10/21, Erin Lo wrote:
> > diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c 
> > b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > new file mode 100644
> > index 000..dbf6ab2
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > @@ -0,0 +1,148 @@
> > +
> > +static int mtk_bdpsys_init(struct platform_device *pdev)
> > +{
> > +   struct clk_onecell_data *clk_data;
> > +   int r;
> > +   struct device_node *node = pdev->dev.of_node;
> > +
> > +   clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
> > +
> > +   mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
> > +   clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +
> > +   return r;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt2701_bdp[] = {
> > +   { .compatible = "mediatek,mt2701-bdpsys", },
> > +   {}
> > +};
> > +
> > +static int clk_mt2701_bdp_probe(struct platform_device *pdev)
> > +{
> > +   int r;
> > +
> > +   r = mtk_bdpsys_init(pdev);
> 
> Why not just put the contents of that function here? I don't see
> the point of this.

Because of some historical reasons, we keep mtk_bdpsys_init() for
changing init points between CLK_OF_DECLARE() and probe() more easily. I
can move all contents from mtk_bdpsys_init() here in next patch.

> > +   if (r) {
> > +   dev_err(>dev,
> > +   "could not register clock provider: %s: %d\n",
> > +   pdev->name, r);
> > +   }
> > +
> > +   return r;
> > +}
> > +
> > +static struct platform_driver clk_mt2701_bdp_drv = {
> > +   .probe = clk_mt2701_bdp_probe,
> > +   .driver = {
> > +   .name = "clk-mt2701-bdp",
> > +   .of_match_table = of_match_clk_mt2701_bdp,
> > +   },
> > +};
> > +
> > +builtin_platform_driver(clk_mt2701_bdp_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c 
> > b/drivers/clk/mediatek/clk-mt2701-eth.c
> > new file mode 100644
> > index 000..b2a71a4
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701-eth.c
> > @@ -0,0 +1,90 @@
> > +/*
> > + * Copyright (c) 2014 MediaTek Inc.
> > + * Author: Shunli Wang 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include 
> > +
> > +static const struct mtk_gate_regs eth_cg_regs = {
> > +   .sta_ofs = 0x0030,
> > +};
> > +
> > +#define GATE_ETH(_id, _name, _parent, _shift) {\
> > +   .id = _id,  \
> > +   .name = _name,  \
> > +   .parent_name = _parent, \
> > +   .regs = _cg_regs,   \
> > +   .shift = _shift,\
> > +   .ops = _clk_gate_ops_no_setclr_inv, \
> > +   }
> > +
> > +static const struct mtk_gate eth_clks[] = {
> > +   GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
> > +   GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
> > +   GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
> > +   GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
> > +   GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
> > +   GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
> > +   GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
> > +   GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
> > +};
> > +
> > +static int mtk_ethsys_init(struct platform_device *pdev)
> > +{
> > +   struct clk_onecell_data *clk_data;
> > +   int r;
> > +   struct device_node *node = pdev->dev.of_node;
> > +
> > +   clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
> > +
> > +   mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
> > +   clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +
> > +   return r;
> 
> Just return of_clk_add_provider() please.

I'll change it in next patch.

> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt2701_eth[] = {
> > +   { .compatible = "mediatek,mt2701-ethsys", },
> > +   {}
> > +};
> > +
> > +static int clk_mt2701_eth_probe(struct platform_device *pdev)
> > +{
> > +   int r;
> > +
> > +   r = mtk_ethsys_init(pdev);
> 
> Same comment.

Okay.

> > +   if (r) {
> > +   dev_err(>dev,
> > +   "could not register clock provider: %s: %d\n",
> > +   pdev->name, r);
> > +   }
> > +
> > +   return r;
> > +}
> 

Re: [PATCH v9 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

On Mon, 2016-10-31 at 01:08 +0100, Matthias Brugger wrote:
> Hi James,
> 
> On 10/20/2016 10:56 AM, James Liao wrote:
> > Some power domain comsumers may init before module_init.
> > So the power domain provider (scpsys) need to be initialized
> > earlier too.
> >
> > Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
> > between IOMMU and multimedia HW. SMI is responsible to
> > enable/disable iommu and help transfer data for each multimedia
> > HW. Both of them have to wait until the power and clocks are
> > enabled.
> >
> > So scpsys driver should be initialized before SMI, and SMI should
> > be initialized before IOMMU, and then init IOMMU consumers
> > (display/vdec/venc/camera etc.).
> >
> > IOMMU is subsys_init by default. So we need to init scpsys driver
> > before subsys_init.
> >
> > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > Reviewed-by: Kevin Hilman <khil...@baylibre.com>
> > ---
> 
> I didn't applied this patch for now.
> I answered you in v7 of this series [1]. I would prefer to see if we can 
> fix that otherwise.
> 
> Would be great if you or Yong could provide some feedback.
> 
> Thanks,
> Matthias
> 
> [1] https://patchwork.kernel.org/patch/9397405/
> 
> >  drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
> >  1 file changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index fa9ee69..dd7a07d 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -613,4 +613,21 @@ static int scpsys_probe(struct platform_device *pdev)
> > .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> > },
> >  };
> > -builtin_platform_driver(scpsys_drv);
> > +
> > +static int __init scpsys_drv_init(void)
> > +{
> > +   return platform_driver_register(_drv);
> > +}
> > +
> > +/*
> > + * There are some Mediatek drivers which depend on the power domain driver 
> > need
> > + * to probe in earlier initcall levels. So scpsys driver also need to probe
> > + * earlier.
> > + *
> > + * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU 
> > and
> > + * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
> > + * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
> > + * IOMMU drivers are initialized during subsys_init by default, so we need 
> > to
> > + * move SMI and scpsys drivers to subsys_init or earlier init levels.
> > + */
> > +subsys_initcall(scpsys_drv_init);
> >

Hi Matthias,

I got it, thanks.


Hi Yong,

Is this patch still needed on latest kernel for IOMMU driver? Or we have
other solutions for IOMMU driver init?


Best regards,

James

Re: [PATCH v9 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

On Mon, 2016-10-31 at 01:08 +0100, Matthias Brugger wrote:
> Hi James,
> 
> On 10/20/2016 10:56 AM, James Liao wrote:
> > Some power domain comsumers may init before module_init.
> > So the power domain provider (scpsys) need to be initialized
> > earlier too.
> >
> > Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
> > between IOMMU and multimedia HW. SMI is responsible to
> > enable/disable iommu and help transfer data for each multimedia
> > HW. Both of them have to wait until the power and clocks are
> > enabled.
> >
> > So scpsys driver should be initialized before SMI, and SMI should
> > be initialized before IOMMU, and then init IOMMU consumers
> > (display/vdec/venc/camera etc.).
> >
> > IOMMU is subsys_init by default. So we need to init scpsys driver
> > before subsys_init.
> >
> > Signed-off-by: James Liao 
> > Reviewed-by: Kevin Hilman 
> > ---
> 
> I didn't applied this patch for now.
> I answered you in v7 of this series [1]. I would prefer to see if we can 
> fix that otherwise.
> 
> Would be great if you or Yong could provide some feedback.
> 
> Thanks,
> Matthias
> 
> [1] https://patchwork.kernel.org/patch/9397405/
> 
> >  drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
> >  1 file changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index fa9ee69..dd7a07d 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -613,4 +613,21 @@ static int scpsys_probe(struct platform_device *pdev)
> > .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> > },
> >  };
> > -builtin_platform_driver(scpsys_drv);
> > +
> > +static int __init scpsys_drv_init(void)
> > +{
> > +   return platform_driver_register(_drv);
> > +}
> > +
> > +/*
> > + * There are some Mediatek drivers which depend on the power domain driver 
> > need
> > + * to probe in earlier initcall levels. So scpsys driver also need to probe
> > + * earlier.
> > + *
> > + * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU 
> > and
> > + * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
> > + * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
> > + * IOMMU drivers are initialized during subsys_init by default, so we need 
> > to
> > + * move SMI and scpsys drivers to subsys_init or earlier init levels.
> > + */
> > +subsys_initcall(scpsys_drv_init);
> >

Hi Matthias,

I got it, thanks.


Hi Yong,

Is this patch still needed on latest kernel for IOMMU driver? Or we have
other solutions for IOMMU driver init?


Best regards,

James

Re: [PATCH v9 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Hi Matthias,

Sorry for late reply due to our email service.

On Tue, 2016-10-25 at 16:04 +0200, Matthias Brugger wrote:
> Hi James,
> 
> On 10/20/2016 10:56 AM, James Liao wrote:
> > -static int scpsys_probe(struct platform_device *pdev)
> > +static void init_clks(struct platform_device *pdev, struct clk 
> > *clk[CLK_MAX])
> 
> I prefer struct clk **clk.

Okay.

> > +{
> > +   int i;
> > +
> > +   for (i = CLK_NONE + 1; i < CLK_MAX; i++)
> > +   clk[i] = devm_clk_get(>dev, clk_names[i]);
> > +}
> > +
> > +static struct scp *init_scp(struct platform_device *pdev,
> > +   const struct scp_domain_data *scp_domain_data, int num)
> >  {
> > struct genpd_onecell_data *pd_data;
> > struct resource *res;
> > -   int i, j, ret;
> > +   int i, j;
> > struct scp *scp;
> > -   struct clk *clk[MT8173_CLK_MAX];
> > +   struct clk *clk[CLK_MAX];
> 
> should be *[CLK_MAX - 1] but I would prefer to define in the enum:
> CLK_MAX = CLK_VENC_LT,

After init_clks() the clk[] will have valid contents between
clk[1]..clk[CLK_MAX-1], so it's necessary to declare clk[] with CLK_MAX
elements.

> If you are ok with it, I can fix both of my comments when applying.

Yes. struct clk **clk can be applied directly. But I think clk[CLK_MAX]
should be kept in current implementation.


Best regards,

James

Re: [PATCH v9 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Hi Matthias,

Sorry for late reply due to our email service.

On Tue, 2016-10-25 at 16:04 +0200, Matthias Brugger wrote:
> Hi James,
> 
> On 10/20/2016 10:56 AM, James Liao wrote:
> > -static int scpsys_probe(struct platform_device *pdev)
> > +static void init_clks(struct platform_device *pdev, struct clk 
> > *clk[CLK_MAX])
> 
> I prefer struct clk **clk.

Okay.

> > +{
> > +   int i;
> > +
> > +   for (i = CLK_NONE + 1; i < CLK_MAX; i++)
> > +   clk[i] = devm_clk_get(>dev, clk_names[i]);
> > +}
> > +
> > +static struct scp *init_scp(struct platform_device *pdev,
> > +   const struct scp_domain_data *scp_domain_data, int num)
> >  {
> > struct genpd_onecell_data *pd_data;
> > struct resource *res;
> > -   int i, j, ret;
> > +   int i, j;
> > struct scp *scp;
> > -   struct clk *clk[MT8173_CLK_MAX];
> > +   struct clk *clk[CLK_MAX];
> 
> should be *[CLK_MAX - 1] but I would prefer to define in the enum:
> CLK_MAX = CLK_VENC_LT,

After init_clks() the clk[] will have valid contents between
clk[1]..clk[CLK_MAX-1], so it's necessary to declare clk[] with CLK_MAX
elements.

> If you are ok with it, I can fix both of my comments when applying.

Yes. struct clk **clk can be applied directly. But I think clk[CLK_MAX]
should be kept in current implementation.


Best regards,

James

[PATCH v9 3/4] soc: mediatek: Add MT2701 power dt-bindings

[James Liao]

From: Shunli Wang <shunli.w...@mediatek.com>

Add power dt-bindings for MT2701.

Signed-off-by: Shunli Wang <shunli.w...@mediatek.com>
Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 .../devicetree/bindings/soc/mediatek/scpsys.txt| 13 +++
 include/dt-bindings/power/mt2701-power.h   | 27 ++
 2 files changed, 35 insertions(+), 5 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 
b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index e8f15e3..16fe94d 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -9,17 +9,20 @@ domain control.
 
 The driver implements the Generic PM domain bindings described in
 power/power_domain.txt. It provides the power domains defined in
-include/dt-bindings/power/mt8173-power.h.
+include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
 
 Required properties:
-- compatible: Must be "mediatek,mt8173-scpsys"
+- compatible: Should be one of:
+   - "mediatek,mt2701-scpsys"
+   - "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
 - infracfg: must contain a phandle to the infracfg controller
 - clock, clock-names: clocks according to the common clock binding.
-  The clocks needed "mm", "mfg", "venc" and "venc_lt".
- These are the clocks which hardware needs to be enabled
- before enabling certain power domains.
+  These are clocks which hardware needs to be
+  enabled before enabling certain power domains.
+   Required clocks for MT2701: "mm", "mfg", "ethif"
+   Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:
 - vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt2701-power.h 
b/include/dt-bindings/power/mt2701-power.h
new file mode 100644
index 000..64cc826
--- /dev/null
+++ b/include/dt-bindings/power/mt2701-power.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
+
+#define MT2701_POWER_DOMAIN_CONN   0
+#define MT2701_POWER_DOMAIN_DISP   1
+#define MT2701_POWER_DOMAIN_MFG2
+#define MT2701_POWER_DOMAIN_VDEC   3
+#define MT2701_POWER_DOMAIN_ISP4
+#define MT2701_POWER_DOMAIN_BDP5
+#define MT2701_POWER_DOMAIN_ETH6
+#define MT2701_POWER_DOMAIN_HIF7
+#define MT2701_POWER_DOMAIN_IFR_MSC8
+
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
-- 
1.9.1

[PATCH v9 3/4] soc: mediatek: Add MT2701 power dt-bindings

[James Liao]

From: Shunli Wang 

Add power dt-bindings for MT2701.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Acked-by: Rob Herring 
Reviewed-by: Kevin Hilman 
---
 .../devicetree/bindings/soc/mediatek/scpsys.txt| 13 +++
 include/dt-bindings/power/mt2701-power.h   | 27 ++
 2 files changed, 35 insertions(+), 5 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 
b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index e8f15e3..16fe94d 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -9,17 +9,20 @@ domain control.
 
 The driver implements the Generic PM domain bindings described in
 power/power_domain.txt. It provides the power domains defined in
-include/dt-bindings/power/mt8173-power.h.
+include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
 
 Required properties:
-- compatible: Must be "mediatek,mt8173-scpsys"
+- compatible: Should be one of:
+   - "mediatek,mt2701-scpsys"
+   - "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
 - infracfg: must contain a phandle to the infracfg controller
 - clock, clock-names: clocks according to the common clock binding.
-  The clocks needed "mm", "mfg", "venc" and "venc_lt".
- These are the clocks which hardware needs to be enabled
- before enabling certain power domains.
+  These are clocks which hardware needs to be
+  enabled before enabling certain power domains.
+   Required clocks for MT2701: "mm", "mfg", "ethif"
+   Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:
 - vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt2701-power.h 
b/include/dt-bindings/power/mt2701-power.h
new file mode 100644
index 000..64cc826
--- /dev/null
+++ b/include/dt-bindings/power/mt2701-power.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
+
+#define MT2701_POWER_DOMAIN_CONN   0
+#define MT2701_POWER_DOMAIN_DISP   1
+#define MT2701_POWER_DOMAIN_MFG2
+#define MT2701_POWER_DOMAIN_VDEC   3
+#define MT2701_POWER_DOMAIN_ISP4
+#define MT2701_POWER_DOMAIN_BDP5
+#define MT2701_POWER_DOMAIN_ETH6
+#define MT2701_POWER_DOMAIN_HIF7
+#define MT2701_POWER_DOMAIN_IFR_MSC8
+
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
-- 
1.9.1

[PATCH v9 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

Some power domain comsumers may init before module_init.
So the power domain provider (scpsys) need to be initialized
earlier too.

Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
between IOMMU and multimedia HW. SMI is responsible to
enable/disable iommu and help transfer data for each multimedia
HW. Both of them have to wait until the power and clocks are
enabled.

So scpsys driver should be initialized before SMI, and SMI should
be initialized before IOMMU, and then init IOMMU consumers
(display/vdec/venc/camera etc.).

IOMMU is subsys_init by default. So we need to init scpsys driver
before subsys_init.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index fa9ee69..dd7a07d 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -613,4 +613,21 @@ static int scpsys_probe(struct platform_device *pdev)
.of_match_table = of_match_ptr(of_scpsys_match_tbl),
},
 };
-builtin_platform_driver(scpsys_drv);
+
+static int __init scpsys_drv_init(void)
+{
+   return platform_driver_register(_drv);
+}
+
+/*
+ * There are some Mediatek drivers which depend on the power domain driver need
+ * to probe in earlier initcall levels. So scpsys driver also need to probe
+ * earlier.
+ *
+ * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU and
+ * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
+ * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
+ * IOMMU drivers are initialized during subsys_init by default, so we need to
+ * move SMI and scpsys drivers to subsys_init or earlier init levels.
+ */
+subsys_initcall(scpsys_drv_init);
-- 
1.9.1

[PATCH v9 4/4] soc: mediatek: Add MT2701 scpsys driver

[James Liao]

From: Shunli Wang <shunli.w...@mediatek.com>

Add scpsys driver for MT2701.

mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
be enabled on both arm64 and arm platforms.

Signed-off-by: Shunli Wang <shunli.w...@mediatek.com>
Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 drivers/soc/mediatek/Kconfig  |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c | 117 +-
 2 files changed, 117 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 0a4ea80..609bb34 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
 config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
-   default ARM64 && ARCH_MEDIATEK
+   default ARCH_MEDIATEK
select REGMAP
select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index dd7a07d..4a1c636 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -27,8 +28,13 @@
 #define SPM_VEN_PWR_CON0x0230
 #define SPM_ISP_PWR_CON0x0238
 #define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON   0x0280
 #define SPM_VEN2_PWR_CON   0x0298
-#define SPM_AUDIO_PWR_CON  0x029c
+#define SPM_AUDIO_PWR_CON  0x029c  /* MT8173 */
+#define SPM_BDP_PWR_CON0x029c  /* MT2701 */
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
@@ -42,10 +48,15 @@
 #define PWR_ON_2ND_BIT BIT(3)
 #define PWR_CLK_DIS_BITBIT(4)
 
+#define PWR_STATUS_CONNBIT(1)
 #define PWR_STATUS_DISPBIT(3)
 #define PWR_STATUS_MFG BIT(4)
 #define PWR_STATUS_ISP BIT(5)
 #define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
 #define PWR_STATUS_VENC_LT BIT(20)
 #define PWR_STATUS_VENCBIT(21)
 #define PWR_STATUS_MFG_2D  BIT(22)
@@ -59,6 +70,7 @@ enum clk_id {
CLK_MFG,
CLK_VENC,
CLK_VENC_LT,
+   CLK_ETHIF,
CLK_MAX,
 };
 
@@ -68,6 +80,7 @@ enum clk_id {
"mfg",
"venc",
"venc_lt",
+   "ethif",
NULL,
 };
 
@@ -455,6 +468,105 @@ static void mtk_register_power_domains(struct 
platform_device *pdev,
 }
 
 /*
+ * MT2701 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt2701[] = {
+   [MT2701_POWER_DOMAIN_CONN] = {
+   .name = "conn",
+   .sta_mask = PWR_STATUS_CONN,
+   .ctl_offs = SPM_CONN_PWR_CON,
+   .bus_prot_mask = 0x0104,
+   .clk_id = {CLK_NONE},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_DISP] = {
+   .name = "disp",
+   .sta_mask = PWR_STATUS_DISP,
+   .ctl_offs = SPM_DIS_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .clk_id = {CLK_MM},
+   .bus_prot_mask = 0x0002,
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_MFG] = {
+   .name = "mfg",
+   .sta_mask = PWR_STATUS_MFG,
+   .ctl_offs = SPM_MFG_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MFG},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_VDEC] = {
+   .name = "vdec",
+   .sta_mask = PWR_STATUS_VDEC,
+   .ctl_offs = SPM_VDE_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MM},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_ISP] = {
+   .name = "isp",
+   .sta_mask = PWR_STATUS_ISP,
+   .ctl_offs = SPM_ISP_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(13, 12),
+

[PATCH v9 0/4] Mediatek MT2701 SCPSYS power domain support

[James Liao]

This series is based on v4.9-rc1 and adds scpsys power domain support
for Mediatek MT2701.

To share the code between MT2701 and MT8173, this patchset also refined
original mtk-scpsys.c to separate common codes and platform codes, so
that mtk-scpsys.c can support new SoCs more easily.

MT8173 and MT2701 scpsys init level are now subsys_init. Please refer to [1]
to see discussion details.

changes since v8:
- Rebase to v4.9-rc1.
- Refine implementation in init_clks() and init_scp().

changes since v7:
- Add clk_id for each scp_domain_data define.
- Minor coding style changes.

changes since v6:
- Minor changes in the dt-binding document.

changes since v5:
- Rebase to v4.6-rc1.
- Add dependent clocks for MFG, ISP, ETH and HIF power domains.
- Add "ethif" as a dependent clock in scpsys dt-binding document.

changes since v4:
- Rebase to v4.5-rc4.
- Remove mtk-scpsys.h and Merge its code into mtk-scpsys.c.
- Add names for every controlling registers and bits.
- Include dt-bindings headers at the beginning of mtk-scpsys.c.
- Sort compatible string in dt-binding documents.

changes since v3:
- Implement MT8173 and MT2701 scpsys drivers in a signle file.
- Remove naming of registers that can't be shared among SoCs.

changes since v2:
- Rebase to mbgg/linux-mediatek v4.4-next/soc [1].
- Remove MTK_SCPSYS_MT8173 and MTK_SCPSYS_MT2701.
- Modify scpsys dt-binding document to support MT2701.

changes since v1:
- Make MTK_SCPSYS in Kconfig invisible from users.
- Add comments for changing scpsys init level to subsys_init.

[1] 
http://lists.infradead.org/pipermail/linux-mediatek/2015-December/003416.html

James Liao (2):
  soc: mediatek: Refine scpsys to support multiple platform
  soc: mediatek: Init MT8173 scpsys driver earlier

Shunli Wang (2):
  soc: mediatek: Add MT2701 power dt-bindings
  soc: mediatek: Add MT2701 scpsys driver

 .../devicetree/bindings/soc/mediatek/scpsys.txt|  13 +-
 drivers/soc/mediatek/Kconfig   |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c  | 484 +++--
 include/dt-bindings/power/mt2701-power.h   |  27 ++
 4 files changed, 380 insertions(+), 146 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

--
1.9.1

[PATCH v9 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Refine scpsys driver common code to support multiple SoC / platform.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 348 +++---
 1 file changed, 210 insertions(+), 138 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 837effe..fa9ee69 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,17 +11,15 @@
  * GNU General Public License for more details.
  */
 #include 
-#include 
+#include 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
+#include 
+
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -34,6 +32,7 @@
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
+
 #define SPM_PWR_STATUS 0x060c
 #define SPM_PWR_STATUS_2ND 0x0610
 
@@ -55,12 +54,21 @@
 #define PWR_STATUS_USB BIT(25)
 
 enum clk_id {
-   MT8173_CLK_NONE,
-   MT8173_CLK_MM,
-   MT8173_CLK_MFG,
-   MT8173_CLK_VENC,
-   MT8173_CLK_VENC_LT,
-   MT8173_CLK_MAX,
+   CLK_NONE,
+   CLK_MM,
+   CLK_MFG,
+   CLK_VENC,
+   CLK_VENC_LT,
+   CLK_MAX,
+};
+
+static const char * const clk_names[] = {
+   NULL,
+   "mm",
+   "mfg",
+   "venc",
+   "venc_lt",
+   NULL,
 };
 
 #define MAX_CLKS   2
@@ -76,98 +84,6 @@ struct scp_domain_data {
bool active_wakeup;
 };
 
-static const struct scp_domain_data scp_domain_data[] = {
-   [MT8173_POWER_DOMAIN_VDEC] = {
-   .name = "vdec",
-   .sta_mask = PWR_STATUS_VDEC,
-   .ctl_offs = SPM_VDE_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_VENC] = {
-   .name = "venc",
-   .sta_mask = PWR_STATUS_VENC,
-   .ctl_offs = SPM_VEN_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
-   },
-   [MT8173_POWER_DOMAIN_ISP] = {
-   .name = "isp",
-   .sta_mask = PWR_STATUS_ISP,
-   .ctl_offs = SPM_ISP_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_MM] = {
-   .name = "mm",
-   .sta_mask = PWR_STATUS_DISP,
-   .ctl_offs = SPM_DIS_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
-   MT8173_TOP_AXI_PROT_EN_MM_M1,
-   },
-   [MT8173_POWER_DOMAIN_VENC_LT] = {
-   .name = "venc_lt",
-   .sta_mask = PWR_STATUS_VENC_LT,
-   .ctl_offs = SPM_VEN2_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
-   },
-   [MT8173_POWER_DOMAIN_AUDIO] = {
-   .name = "audio",
-   .sta_mask = PWR_STATUS_AUDIO,
-   .ctl_offs = SPM_AUDIO_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_USB] = {
-   .name = "usb",
-   .sta_mask = PWR_STATUS_USB,
-   .ctl_offs = SPM_USB_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   .active_wakeup = true,
-   },
-   [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
-   .name = "mfg_async",
-   .sta_mask = PWR_STATUS_MFG_ASYNC,
-   .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = 0,
-   .clk_id = {MT8173_CLK_MFG},
-   },
-   [MT8173_POWER_DOMAIN_MFG_2D] = {
-   .name = "mfg_2d",
-   .sta_mask = PWR_STATUS_MFG_2D,
-   .ctl_offs = SPM_MFG_2D_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_MFG] = {
-   

[PATCH v9 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

Some power domain comsumers may init before module_init.
So the power domain provider (scpsys) need to be initialized
earlier too.

Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
between IOMMU and multimedia HW. SMI is responsible to
enable/disable iommu and help transfer data for each multimedia
HW. Both of them have to wait until the power and clocks are
enabled.

So scpsys driver should be initialized before SMI, and SMI should
be initialized before IOMMU, and then init IOMMU consumers
(display/vdec/venc/camera etc.).

IOMMU is subsys_init by default. So we need to init scpsys driver
before subsys_init.

Signed-off-by: James Liao 
Reviewed-by: Kevin Hilman 
---
 drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index fa9ee69..dd7a07d 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -613,4 +613,21 @@ static int scpsys_probe(struct platform_device *pdev)
.of_match_table = of_match_ptr(of_scpsys_match_tbl),
},
 };
-builtin_platform_driver(scpsys_drv);
+
+static int __init scpsys_drv_init(void)
+{
+   return platform_driver_register(_drv);
+}
+
+/*
+ * There are some Mediatek drivers which depend on the power domain driver need
+ * to probe in earlier initcall levels. So scpsys driver also need to probe
+ * earlier.
+ *
+ * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU and
+ * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
+ * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
+ * IOMMU drivers are initialized during subsys_init by default, so we need to
+ * move SMI and scpsys drivers to subsys_init or earlier init levels.
+ */
+subsys_initcall(scpsys_drv_init);
-- 
1.9.1

[PATCH v9 4/4] soc: mediatek: Add MT2701 scpsys driver

[James Liao]

From: Shunli Wang 

Add scpsys driver for MT2701.

mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
be enabled on both arm64 and arm platforms.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Reviewed-by: Kevin Hilman 
---
 drivers/soc/mediatek/Kconfig  |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c | 117 +-
 2 files changed, 117 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 0a4ea80..609bb34 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
 config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
-   default ARM64 && ARCH_MEDIATEK
+   default ARCH_MEDIATEK
select REGMAP
select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index dd7a07d..4a1c636 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -27,8 +28,13 @@
 #define SPM_VEN_PWR_CON0x0230
 #define SPM_ISP_PWR_CON0x0238
 #define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON   0x0280
 #define SPM_VEN2_PWR_CON   0x0298
-#define SPM_AUDIO_PWR_CON  0x029c
+#define SPM_AUDIO_PWR_CON  0x029c  /* MT8173 */
+#define SPM_BDP_PWR_CON0x029c  /* MT2701 */
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
@@ -42,10 +48,15 @@
 #define PWR_ON_2ND_BIT BIT(3)
 #define PWR_CLK_DIS_BITBIT(4)
 
+#define PWR_STATUS_CONNBIT(1)
 #define PWR_STATUS_DISPBIT(3)
 #define PWR_STATUS_MFG BIT(4)
 #define PWR_STATUS_ISP BIT(5)
 #define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
 #define PWR_STATUS_VENC_LT BIT(20)
 #define PWR_STATUS_VENCBIT(21)
 #define PWR_STATUS_MFG_2D  BIT(22)
@@ -59,6 +70,7 @@ enum clk_id {
CLK_MFG,
CLK_VENC,
CLK_VENC_LT,
+   CLK_ETHIF,
CLK_MAX,
 };
 
@@ -68,6 +80,7 @@ enum clk_id {
"mfg",
"venc",
"venc_lt",
+   "ethif",
NULL,
 };
 
@@ -455,6 +468,105 @@ static void mtk_register_power_domains(struct 
platform_device *pdev,
 }
 
 /*
+ * MT2701 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt2701[] = {
+   [MT2701_POWER_DOMAIN_CONN] = {
+   .name = "conn",
+   .sta_mask = PWR_STATUS_CONN,
+   .ctl_offs = SPM_CONN_PWR_CON,
+   .bus_prot_mask = 0x0104,
+   .clk_id = {CLK_NONE},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_DISP] = {
+   .name = "disp",
+   .sta_mask = PWR_STATUS_DISP,
+   .ctl_offs = SPM_DIS_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .clk_id = {CLK_MM},
+   .bus_prot_mask = 0x0002,
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_MFG] = {
+   .name = "mfg",
+   .sta_mask = PWR_STATUS_MFG,
+   .ctl_offs = SPM_MFG_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MFG},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_VDEC] = {
+   .name = "vdec",
+   .sta_mask = PWR_STATUS_VDEC,
+   .ctl_offs = SPM_VDE_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MM},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_ISP] = {
+   .name = "isp",
+   .sta_mask = PWR_STATUS_ISP,
+   .ctl_offs = SPM_ISP_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(13, 12),
+   .clk_id = {CLK_MM},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_BDP] = {
+ 

[PATCH v9 0/4] Mediatek MT2701 SCPSYS power domain support

[James Liao]

This series is based on v4.9-rc1 and adds scpsys power domain support
for Mediatek MT2701.

To share the code between MT2701 and MT8173, this patchset also refined
original mtk-scpsys.c to separate common codes and platform codes, so
that mtk-scpsys.c can support new SoCs more easily.

MT8173 and MT2701 scpsys init level are now subsys_init. Please refer to [1]
to see discussion details.

changes since v8:
- Rebase to v4.9-rc1.
- Refine implementation in init_clks() and init_scp().

changes since v7:
- Add clk_id for each scp_domain_data define.
- Minor coding style changes.

changes since v6:
- Minor changes in the dt-binding document.

changes since v5:
- Rebase to v4.6-rc1.
- Add dependent clocks for MFG, ISP, ETH and HIF power domains.
- Add "ethif" as a dependent clock in scpsys dt-binding document.

changes since v4:
- Rebase to v4.5-rc4.
- Remove mtk-scpsys.h and Merge its code into mtk-scpsys.c.
- Add names for every controlling registers and bits.
- Include dt-bindings headers at the beginning of mtk-scpsys.c.
- Sort compatible string in dt-binding documents.

changes since v3:
- Implement MT8173 and MT2701 scpsys drivers in a signle file.
- Remove naming of registers that can't be shared among SoCs.

changes since v2:
- Rebase to mbgg/linux-mediatek v4.4-next/soc [1].
- Remove MTK_SCPSYS_MT8173 and MTK_SCPSYS_MT2701.
- Modify scpsys dt-binding document to support MT2701.

changes since v1:
- Make MTK_SCPSYS in Kconfig invisible from users.
- Add comments for changing scpsys init level to subsys_init.

[1] 
http://lists.infradead.org/pipermail/linux-mediatek/2015-December/003416.html

James Liao (2):
  soc: mediatek: Refine scpsys to support multiple platform
  soc: mediatek: Init MT8173 scpsys driver earlier

Shunli Wang (2):
  soc: mediatek: Add MT2701 power dt-bindings
  soc: mediatek: Add MT2701 scpsys driver

 .../devicetree/bindings/soc/mediatek/scpsys.txt|  13 +-
 drivers/soc/mediatek/Kconfig   |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c  | 484 +++--
 include/dt-bindings/power/mt2701-power.h   |  27 ++
 4 files changed, 380 insertions(+), 146 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

--
1.9.1

[PATCH v9 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Refine scpsys driver common code to support multiple SoC / platform.

Signed-off-by: James Liao 
Reviewed-by: Kevin Hilman 
---
 drivers/soc/mediatek/mtk-scpsys.c | 348 +++---
 1 file changed, 210 insertions(+), 138 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 837effe..fa9ee69 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,17 +11,15 @@
  * GNU General Public License for more details.
  */
 #include 
-#include 
+#include 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
+#include 
+
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -34,6 +32,7 @@
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
+
 #define SPM_PWR_STATUS 0x060c
 #define SPM_PWR_STATUS_2ND 0x0610
 
@@ -55,12 +54,21 @@
 #define PWR_STATUS_USB BIT(25)
 
 enum clk_id {
-   MT8173_CLK_NONE,
-   MT8173_CLK_MM,
-   MT8173_CLK_MFG,
-   MT8173_CLK_VENC,
-   MT8173_CLK_VENC_LT,
-   MT8173_CLK_MAX,
+   CLK_NONE,
+   CLK_MM,
+   CLK_MFG,
+   CLK_VENC,
+   CLK_VENC_LT,
+   CLK_MAX,
+};
+
+static const char * const clk_names[] = {
+   NULL,
+   "mm",
+   "mfg",
+   "venc",
+   "venc_lt",
+   NULL,
 };
 
 #define MAX_CLKS   2
@@ -76,98 +84,6 @@ struct scp_domain_data {
bool active_wakeup;
 };
 
-static const struct scp_domain_data scp_domain_data[] = {
-   [MT8173_POWER_DOMAIN_VDEC] = {
-   .name = "vdec",
-   .sta_mask = PWR_STATUS_VDEC,
-   .ctl_offs = SPM_VDE_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_VENC] = {
-   .name = "venc",
-   .sta_mask = PWR_STATUS_VENC,
-   .ctl_offs = SPM_VEN_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
-   },
-   [MT8173_POWER_DOMAIN_ISP] = {
-   .name = "isp",
-   .sta_mask = PWR_STATUS_ISP,
-   .ctl_offs = SPM_ISP_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_MM] = {
-   .name = "mm",
-   .sta_mask = PWR_STATUS_DISP,
-   .ctl_offs = SPM_DIS_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
-   MT8173_TOP_AXI_PROT_EN_MM_M1,
-   },
-   [MT8173_POWER_DOMAIN_VENC_LT] = {
-   .name = "venc_lt",
-   .sta_mask = PWR_STATUS_VENC_LT,
-   .ctl_offs = SPM_VEN2_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
-   },
-   [MT8173_POWER_DOMAIN_AUDIO] = {
-   .name = "audio",
-   .sta_mask = PWR_STATUS_AUDIO,
-   .ctl_offs = SPM_AUDIO_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_USB] = {
-   .name = "usb",
-   .sta_mask = PWR_STATUS_USB,
-   .ctl_offs = SPM_USB_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   .active_wakeup = true,
-   },
-   [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
-   .name = "mfg_async",
-   .sta_mask = PWR_STATUS_MFG_ASYNC,
-   .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = 0,
-   .clk_id = {MT8173_CLK_MFG},
-   },
-   [MT8173_POWER_DOMAIN_MFG_2D] = {
-   .name = "mfg_2d",
-   .sta_mask = PWR_STATUS_MFG_2D,
-   .ctl_offs = SPM_MFG_2D_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_MFG] = {
-   .name = "mfg",
-   .sta_mask = PWR_

Re: [PATCH v8 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

On Wed, 2016-09-21 at 12:25 +0200, Matthias Brugger wrote:
> 
> On 19/07/16 09:04, James Liao wrote:
> > Refine scpsys driver common code to support multiple SoC / platform.
> >
> > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > Reviewed-by: Kevin Hilman <khil...@baylibre.com>
> > ---
> >  drivers/soc/mediatek/mtk-scpsys.c | 363 
> > +++---
> >  1 file changed, 220 insertions(+), 143 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index 837effe..1f3555a 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -11,17 +11,15 @@
> >   * GNU General Public License for more details.
> >   */
> >  #include 
> > -#include 
> > +#include 
> >  #include 
> > -#include 
> >  #include 
> > -#include 
> >  #include 
> >  #include 
> >  #include 
> > -#include 
> > -#include 
> >  #include 
> > +#include 
> > +
> >  #include 
> >
> >  #define SPM_VDE_PWR_CON0x0210
> > @@ -34,6 +32,7 @@
> >  #define SPM_MFG_2D_PWR_CON 0x02c0
> >  #define SPM_MFG_ASYNC_PWR_CON  0x02c4
> >  #define SPM_USB_PWR_CON0x02cc
> > +
> >  #define SPM_PWR_STATUS 0x060c
> >  #define SPM_PWR_STATUS_2ND 0x0610
> >
> > @@ -55,12 +54,12 @@
> >  #define PWR_STATUS_USB BIT(25)
> >
> >  enum clk_id {
> > -   MT8173_CLK_NONE,
> > -   MT8173_CLK_MM,
> > -   MT8173_CLK_MFG,
> > -   MT8173_CLK_VENC,
> > -   MT8173_CLK_VENC_LT,
> > -   MT8173_CLK_MAX,
> > +   CLK_NONE,
> > +   CLK_MM,
> > +   CLK_MFG,
> > +   CLK_VENC,
> > +   CLK_VENC_LT,
> > +   CLK_MAX,
> >  };
> >
> >  #define MAX_CLKS   2
> > @@ -76,98 +75,6 @@ struct scp_domain_data {
> > bool active_wakeup;
> >  };
> >
> > -static const struct scp_domain_data scp_domain_data[] = {
> > -   [MT8173_POWER_DOMAIN_VDEC] = {
> > -   .name = "vdec",
> > -   .sta_mask = PWR_STATUS_VDEC,
> > -   .ctl_offs = SPM_VDE_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(12, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   },
> > -   [MT8173_POWER_DOMAIN_VENC] = {
> > -   .name = "venc",
> > -   .sta_mask = PWR_STATUS_VENC,
> > -   .ctl_offs = SPM_VEN_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
> > -   },
> > -   [MT8173_POWER_DOMAIN_ISP] = {
> > -   .name = "isp",
> > -   .sta_mask = PWR_STATUS_ISP,
> > -   .ctl_offs = SPM_ISP_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(13, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   },
> > -   [MT8173_POWER_DOMAIN_MM] = {
> > -   .name = "mm",
> > -   .sta_mask = PWR_STATUS_DISP,
> > -   .ctl_offs = SPM_DIS_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(12, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> > -   MT8173_TOP_AXI_PROT_EN_MM_M1,
> > -   },
> > -   [MT8173_POWER_DOMAIN_VENC_LT] = {
> > -   .name = "venc_lt",
> > -   .sta_mask = PWR_STATUS_VENC_LT,
> > -   .ctl_offs = SPM_VEN2_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
> > -   },
> > -   [MT8173_POWER_DOMAIN_AUDIO] = {
> > -   .name = "audio",
> > -   .sta_mask = PWR_STATUS_AUDIO,
> > -   .ctl_offs = SPM_AUDIO_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_NONE},
> > -   },
> > -   [MT8173_POWER_DOMAIN_USB] = {
> > -   .name = "usb",
> > -   .sta_mask = PWR_STATUS_USB,
> > -   .ctl_offs = SPM_USB_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > - 

Re: [PATCH v8 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

On Wed, 2016-09-21 at 12:25 +0200, Matthias Brugger wrote:
> 
> On 19/07/16 09:04, James Liao wrote:
> > Refine scpsys driver common code to support multiple SoC / platform.
> >
> > Signed-off-by: James Liao 
> > Reviewed-by: Kevin Hilman 
> > ---
> >  drivers/soc/mediatek/mtk-scpsys.c | 363 
> > +++---
> >  1 file changed, 220 insertions(+), 143 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index 837effe..1f3555a 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -11,17 +11,15 @@
> >   * GNU General Public License for more details.
> >   */
> >  #include 
> > -#include 
> > +#include 
> >  #include 
> > -#include 
> >  #include 
> > -#include 
> >  #include 
> >  #include 
> >  #include 
> > -#include 
> > -#include 
> >  #include 
> > +#include 
> > +
> >  #include 
> >
> >  #define SPM_VDE_PWR_CON0x0210
> > @@ -34,6 +32,7 @@
> >  #define SPM_MFG_2D_PWR_CON 0x02c0
> >  #define SPM_MFG_ASYNC_PWR_CON  0x02c4
> >  #define SPM_USB_PWR_CON0x02cc
> > +
> >  #define SPM_PWR_STATUS 0x060c
> >  #define SPM_PWR_STATUS_2ND 0x0610
> >
> > @@ -55,12 +54,12 @@
> >  #define PWR_STATUS_USB BIT(25)
> >
> >  enum clk_id {
> > -   MT8173_CLK_NONE,
> > -   MT8173_CLK_MM,
> > -   MT8173_CLK_MFG,
> > -   MT8173_CLK_VENC,
> > -   MT8173_CLK_VENC_LT,
> > -   MT8173_CLK_MAX,
> > +   CLK_NONE,
> > +   CLK_MM,
> > +   CLK_MFG,
> > +   CLK_VENC,
> > +   CLK_VENC_LT,
> > +   CLK_MAX,
> >  };
> >
> >  #define MAX_CLKS   2
> > @@ -76,98 +75,6 @@ struct scp_domain_data {
> > bool active_wakeup;
> >  };
> >
> > -static const struct scp_domain_data scp_domain_data[] = {
> > -   [MT8173_POWER_DOMAIN_VDEC] = {
> > -   .name = "vdec",
> > -   .sta_mask = PWR_STATUS_VDEC,
> > -   .ctl_offs = SPM_VDE_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(12, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   },
> > -   [MT8173_POWER_DOMAIN_VENC] = {
> > -   .name = "venc",
> > -   .sta_mask = PWR_STATUS_VENC,
> > -   .ctl_offs = SPM_VEN_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
> > -   },
> > -   [MT8173_POWER_DOMAIN_ISP] = {
> > -   .name = "isp",
> > -   .sta_mask = PWR_STATUS_ISP,
> > -   .ctl_offs = SPM_ISP_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(13, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   },
> > -   [MT8173_POWER_DOMAIN_MM] = {
> > -   .name = "mm",
> > -   .sta_mask = PWR_STATUS_DISP,
> > -   .ctl_offs = SPM_DIS_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(12, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> > -   MT8173_TOP_AXI_PROT_EN_MM_M1,
> > -   },
> > -   [MT8173_POWER_DOMAIN_VENC_LT] = {
> > -   .name = "venc_lt",
> > -   .sta_mask = PWR_STATUS_VENC_LT,
> > -   .ctl_offs = SPM_VEN2_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
> > -   },
> > -   [MT8173_POWER_DOMAIN_AUDIO] = {
> > -   .name = "audio",
> > -   .sta_mask = PWR_STATUS_AUDIO,
> > -   .ctl_offs = SPM_AUDIO_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_NONE},
> > -   },
> > -   [MT8173_POWER_DOMAIN_USB] = {
> > -   .name = "usb",
> > -   .sta_mask = PWR_STATUS_USB,
> > -   .ctl_offs = SPM_USB_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
&g

Re: [PATCH] clk: mediatek: clk-mt8173: Unmap region obtained by of_iomap

[James Liao]

On Tue, 2016-09-20 at 14:00 +0530, Arvind Yadav wrote:
> From: Arvind Yadav <arvind.yadav...@gmail.com>
> 
> Free memory mapping, if init is not successful.
> 
> Signed-off-by: Arvind Yadav <arvind.yadav...@gmail.com>

Reviewed-by: James Liao <jamesjj.l...@mediatek.com>

> ---
>  drivers/clk/mediatek/clk-mt8173.c |4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt8173.c 
> b/drivers/clk/mediatek/clk-mt8173.c
> index 10c9860..0ac3aee 100644
> --- a/drivers/clk/mediatek/clk-mt8173.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -1074,8 +1074,10 @@ static void __init mtk_apmixedsys_init(struct 
> device_node *node)
>   }
>  
>   mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> - if (!clk_data)
> + if (!clk_data) {
> + iounmap(base);
>   return;
> + }
>  
>   mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
>  

Re: [PATCH] clk: mediatek: clk-mt8173: Unmap region obtained by of_iomap

[James Liao]

On Tue, 2016-09-20 at 14:00 +0530, Arvind Yadav wrote:
> From: Arvind Yadav 
> 
> Free memory mapping, if init is not successful.
> 
> Signed-off-by: Arvind Yadav 

Reviewed-by: James Liao 

> ---
>  drivers/clk/mediatek/clk-mt8173.c |4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt8173.c 
> b/drivers/clk/mediatek/clk-mt8173.c
> index 10c9860..0ac3aee 100644
> --- a/drivers/clk/mediatek/clk-mt8173.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -1074,8 +1074,10 @@ static void __init mtk_apmixedsys_init(struct 
> device_node *node)
>   }
>  
>   mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> - if (!clk_data)
> + if (!clk_data) {
> + iounmap(base);
>   return;
> + }
>  
>   mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
>  

Re: [PATCH v12 2/4] reset: mediatek: Add MT2701 reset driver

[James Liao]

On Wed, 2016-08-24 at 10:50 -0700, Stephen Boyd wrote:
> On 08/22, Erin Lo wrote:
> > diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c 
> > b/drivers/clk/mediatek/clk-mt2701-hif.c
> > index 18b4ab5..702fd74 100644
> > --- a/drivers/clk/mediatek/clk-mt2701-hif.c
> > +++ b/drivers/clk/mediatek/clk-mt2701-hif.c
> > @@ -52,11 +52,15 @@ static int mtk_hifsys_init(struct device_node *node)
> > clk_data);
> >  
> > r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > -   if (r)
> > +   if (r) {
> > pr_err("%s(): could not register clock provider: %d\n",
> > __func__, r);
> > +   return r;
> > +   }
> > +
> > +   mtk_register_reset_controller(node, 1, 0x34);
> 
> The cleanup here isn't great. mtk_register_reset_controller()
> should really return an error so that we can properly cleanup if
> needed. Fixing that in a later patch would be a good idea.

Hi Stephen,

I think so. This function returns void because it was invoked in
CLK_OF_DECLARE() in previous SoC's drivers. I'll investigate how to make
it return an error code without breaking backward compatibility.


Best regards,

James

Re: [PATCH v12 2/4] reset: mediatek: Add MT2701 reset driver

[James Liao]

On Wed, 2016-08-24 at 10:50 -0700, Stephen Boyd wrote:
> On 08/22, Erin Lo wrote:
> > diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c 
> > b/drivers/clk/mediatek/clk-mt2701-hif.c
> > index 18b4ab5..702fd74 100644
> > --- a/drivers/clk/mediatek/clk-mt2701-hif.c
> > +++ b/drivers/clk/mediatek/clk-mt2701-hif.c
> > @@ -52,11 +52,15 @@ static int mtk_hifsys_init(struct device_node *node)
> > clk_data);
> >  
> > r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > -   if (r)
> > +   if (r) {
> > pr_err("%s(): could not register clock provider: %d\n",
> > __func__, r);
> > +   return r;
> > +   }
> > +
> > +   mtk_register_reset_controller(node, 1, 0x34);
> 
> The cleanup here isn't great. mtk_register_reset_controller()
> should really return an error so that we can properly cleanup if
> needed. Fixing that in a later patch would be a good idea.

Hi Stephen,

I think so. This function returns void because it was invoked in
CLK_OF_DECLARE() in previous SoC's drivers. I'll investigate how to make
it return an error code without breaking backward compatibility.


Best regards,

James

Re: [PATCH v12 1/4] clk: mediatek: Add MT2701 clock support

[James Liao]

Hi Stephen,

On Wed, 2016-08-24 at 10:49 -0700, Stephen Boyd wrote:
> On 08/22, Erin Lo wrote:
> > +
> > +static void __init mtk_infrasys_init_early(struct device_node *node)
> > +{
> > +   int r, i;
> > +
> > +   if (!infra_clk_data) {
> > +   infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > +
> > +   for (i = 0; i < CLK_INFRA_NR; i++)
> > +   infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
> > +   }
> > +
> > +   mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> > +   infra_clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
> > +   if (r)
> > +   pr_err("%s(): could not register clock provider: %d\n",
> > +   __func__, r);
> > +}
> > +CLK_OF_DECLARE(mtk_infra, "mediatek,mt2701-infracfg", 
> > mtk_infrasys_init_early);
> 
> This should use CLK_OF_DECLARE_DRIVER? Has this been tested on
> latest clk-next? Some recent patches make it so that
> CLK_OF_DECLARE() prevents platform devices from being created for
> the associated DT nodes that match during of_clk_init().

Oops, you are right. Clocks in infra_clks are gone on clk-next, but they
are good on v4.8-rc1.

I register clk13m in infra_fixed_divs through CLK_OF_DECLARE() so that
it can be registered as early as possible because it will be referred by
the timer driver. Is there a formal way to separate clock registrations
on the same clock provider? Or should I move infra_clks registration
into CLK_OF_DECLARE()?

> > +
> > +static int mtk_infrasys_init(struct device_node *node)
> > +{
> > +   int r, i;
> > +
> > +   if (!infra_clk_data) {
> > +   infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > +   } else {
> > +   for (i = 0; i < CLK_INFRA_NR; i++) {
> > +   if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
> > +   infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
> > +   }
> > +   }
> > +
> > +   mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
> > +   infra_clk_data);
> > +   mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> > +   infra_clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
> > +   if (r)
> > +   pr_err("%s(): could not register clock provider: %d\n",
> > +   __func__, r);
> > +
> > +   return r;
> > +}
> > +
> > +static const struct mtk_gate_regs peri0_cg_regs = {
> > +   .set_ofs = 0x0008,
> > +   .clr_ofs = 0x0010,
> > +   .sta_ofs = 0x0018,
> > +};
> > +
> > +static const struct mtk_gate_regs peri1_cg_regs = {
> > +   .set_ofs = 0x000c,
> > +   .clr_ofs = 0x0014,
> > +   .sta_ofs = 0x001c,
> > +};
> > +
> > +#define GATE_PERI0(_id, _name, _parent, _shift) {  \
> > +   .id = _id,  \
> > +   .name = _name,  \
> > +   .parent_name = _parent, \
> > +   .regs = _cg_regs, \
> > +   .shift = _shift,\
> > +   .ops = _clk_gate_ops_setclr,\
> > +   }
> > +
> > +#define GATE_PERI1(_id, _name, _parent, _shift) {  \
> > +   .id = _id,  \
> > +   .name = _name,  \
> > +   .parent_name = _parent, \
> > +   .regs = _cg_regs, \
> > +   .shift = _shift,\
> > +   .ops = _clk_gate_ops_setclr,\
> > +   }
> > +
> > +static const struct mtk_gate peri_clks[] = {
> > +   GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
> > +   GATE_PERI1(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
> > +   GATE_PERI1(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
> > +   GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
> > +   GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
> > +   GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
> > +   GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
> > +   GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
> > +   GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
> > +   GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
> > +   GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
> > +   GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
> > +   GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
> > +   GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
> > +   GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
> > +   GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
> > +   GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
> > +   GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
> > +   GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
> > +   GATE_PERI0(CLK_PERI_AP_DMA, 

Re: [PATCH v12 1/4] clk: mediatek: Add MT2701 clock support

[James Liao]

Hi Stephen,

On Wed, 2016-08-24 at 10:49 -0700, Stephen Boyd wrote:
> On 08/22, Erin Lo wrote:
> > +
> > +static void __init mtk_infrasys_init_early(struct device_node *node)
> > +{
> > +   int r, i;
> > +
> > +   if (!infra_clk_data) {
> > +   infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > +
> > +   for (i = 0; i < CLK_INFRA_NR; i++)
> > +   infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
> > +   }
> > +
> > +   mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> > +   infra_clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
> > +   if (r)
> > +   pr_err("%s(): could not register clock provider: %d\n",
> > +   __func__, r);
> > +}
> > +CLK_OF_DECLARE(mtk_infra, "mediatek,mt2701-infracfg", 
> > mtk_infrasys_init_early);
> 
> This should use CLK_OF_DECLARE_DRIVER? Has this been tested on
> latest clk-next? Some recent patches make it so that
> CLK_OF_DECLARE() prevents platform devices from being created for
> the associated DT nodes that match during of_clk_init().

Oops, you are right. Clocks in infra_clks are gone on clk-next, but they
are good on v4.8-rc1.

I register clk13m in infra_fixed_divs through CLK_OF_DECLARE() so that
it can be registered as early as possible because it will be referred by
the timer driver. Is there a formal way to separate clock registrations
on the same clock provider? Or should I move infra_clks registration
into CLK_OF_DECLARE()?

> > +
> > +static int mtk_infrasys_init(struct device_node *node)
> > +{
> > +   int r, i;
> > +
> > +   if (!infra_clk_data) {
> > +   infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > +   } else {
> > +   for (i = 0; i < CLK_INFRA_NR; i++) {
> > +   if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
> > +   infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
> > +   }
> > +   }
> > +
> > +   mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
> > +   infra_clk_data);
> > +   mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> > +   infra_clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
> > +   if (r)
> > +   pr_err("%s(): could not register clock provider: %d\n",
> > +   __func__, r);
> > +
> > +   return r;
> > +}
> > +
> > +static const struct mtk_gate_regs peri0_cg_regs = {
> > +   .set_ofs = 0x0008,
> > +   .clr_ofs = 0x0010,
> > +   .sta_ofs = 0x0018,
> > +};
> > +
> > +static const struct mtk_gate_regs peri1_cg_regs = {
> > +   .set_ofs = 0x000c,
> > +   .clr_ofs = 0x0014,
> > +   .sta_ofs = 0x001c,
> > +};
> > +
> > +#define GATE_PERI0(_id, _name, _parent, _shift) {  \
> > +   .id = _id,  \
> > +   .name = _name,  \
> > +   .parent_name = _parent, \
> > +   .regs = _cg_regs, \
> > +   .shift = _shift,\
> > +   .ops = _clk_gate_ops_setclr,\
> > +   }
> > +
> > +#define GATE_PERI1(_id, _name, _parent, _shift) {  \
> > +   .id = _id,  \
> > +   .name = _name,  \
> > +   .parent_name = _parent, \
> > +   .regs = _cg_regs, \
> > +   .shift = _shift,\
> > +   .ops = _clk_gate_ops_setclr,\
> > +   }
> > +
> > +static const struct mtk_gate peri_clks[] = {
> > +   GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
> > +   GATE_PERI1(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
> > +   GATE_PERI1(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
> > +   GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
> > +   GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
> > +   GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
> > +   GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
> > +   GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
> > +   GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
> > +   GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
> > +   GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
> > +   GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
> > +   GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
> > +   GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
> > +   GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
> > +   GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
> > +   GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
> > +   GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
> > +   GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
> > +   GATE_PERI0(CLK_PERI_AP_DMA, 

Re: [PATCH v10 8/9] arm: dts: mt2701: Add clock controller device nodes

[James Liao]

On Thu, 2016-08-18 at 17:18 -0700, Stephen Boyd wrote:
> On 08/16, Erin Lo wrote:
> > From: James Liao <jamesjj.l...@mediatek.com>
> > 
> > Add clock controller nodes for MT2701, include topckgen, infracfg,
> > pericfg, apmixedsys, mmsys, imgsys, vdecsys, hifsys, ethsys and
> > bdpsys. This patch also add two oscillators that provide clocks for
> > MT2701.
> > 
> > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > Signed-off-by: Erin Lo <erin...@mediatek.com>
> > ---
> 
> This should go through arm-soc tree, so do you need a stable
> branch in clk tree to pull through arm-soc, or are we going to
> wait a release cycle on the dts patches?

Hi Stephen,

I prefer to wait a release cycle. We may merge clk driver first, then
merge dts patches in next kernel release.


Best regards,

James

Re: [PATCH v10 8/9] arm: dts: mt2701: Add clock controller device nodes

[James Liao]

On Thu, 2016-08-18 at 17:18 -0700, Stephen Boyd wrote:
> On 08/16, Erin Lo wrote:
> > From: James Liao 
> > 
> > Add clock controller nodes for MT2701, include topckgen, infracfg,
> > pericfg, apmixedsys, mmsys, imgsys, vdecsys, hifsys, ethsys and
> > bdpsys. This patch also add two oscillators that provide clocks for
> > MT2701.
> > 
> > Signed-off-by: James Liao 
> > Signed-off-by: Erin Lo 
> > ---
> 
> This should go through arm-soc tree, so do you need a stable
> branch in clk tree to pull through arm-soc, or are we going to
> wait a release cycle on the dts patches?

Hi Stephen,

I prefer to wait a release cycle. We may merge clk driver first, then
merge dts patches in next kernel release.


Best regards,

James

Re: [PATCH v9 06/10] clk: mediatek: Add MT2701 clock support

[James Liao]

Hi Stephen,

On Fri, 2016-08-12 at 17:44 -0700, Stephen Boyd wrote:
> On 06/22, Erin Lo wrote:
> > diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c 
> > b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > new file mode 100644
> > index 000..81f628c
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > @@ -0,0 +1,140 @@
> > +/*
> > + * Copyright (c) 2014 MediaTek Inc.
> > + * Author: Shunli Wang 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> 
> Is this include used? I would expect clk-provider.h instead.

Yes, it can be replaced with clk-provider.h. I'll change it in next
patch series.

> > +#include 
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include 
> > +
> [..]
> > +
> > +static void mtk_bdpsys_init(struct device_node *node)
> > +{
> > +   struct clk_onecell_data *clk_data;
> > +   int r;
> > +
> > +   clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
> > +
> > +   mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
> > +   clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> 
> Is it possible to move to of_clk_add_hw_provider()? It can be
> done later if that would mean changing all
> mtk_clk_register_gates() users.

I would like to keep current implementation due to test/integration
effort. I prefer to apply clk_hw related APIs on new clk drivers instead
of modify existing drivers.


Best regards,

James

Re: [PATCH v9 06/10] clk: mediatek: Add MT2701 clock support

[James Liao]

Hi Stephen,

On Fri, 2016-08-12 at 17:44 -0700, Stephen Boyd wrote:
> On 06/22, Erin Lo wrote:
> > diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c 
> > b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > new file mode 100644
> > index 000..81f628c
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > @@ -0,0 +1,140 @@
> > +/*
> > + * Copyright (c) 2014 MediaTek Inc.
> > + * Author: Shunli Wang 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> 
> Is this include used? I would expect clk-provider.h instead.

Yes, it can be replaced with clk-provider.h. I'll change it in next
patch series.

> > +#include 
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include 
> > +
> [..]
> > +
> > +static void mtk_bdpsys_init(struct device_node *node)
> > +{
> > +   struct clk_onecell_data *clk_data;
> > +   int r;
> > +
> > +   clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
> > +
> > +   mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
> > +   clk_data);
> > +
> > +   r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> 
> Is it possible to move to of_clk_add_hw_provider()? It can be
> done later if that would mean changing all
> mtk_clk_register_gates() users.

I would like to keep current implementation due to test/integration
effort. I prefer to apply clk_hw related APIs on new clk drivers instead
of modify existing drivers.


Best regards,

James

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

Hi Stephen,

On Fri, 2016-08-12 at 17:39 -0700, Stephen Boyd wrote:
> On 08/12, James Liao wrote:
> > On Wed, 2016-08-10 at 14:09 -0700, Stephen Boyd wrote:
> > > (Including lists)
> > > 
> > > On 08/09, James Liao wrote:
> > > > On Wed, 2016-08-03 at 13:46 +0800, James Liao wrote:
> > > >>
> > > >> Hi Mike,
> > > >>
> > > >> Do you have new patches to fix new clock parents? If not, I think we 
> > > >> can
> > > >> use my patch first. Is it okay?
> > > >>
> > > >
> > > > Hi Stephen,
> > > >
> > > > Do you have comments for the bug fixing? I prefer to use my patch (clk:
> > > > fix initial state of critical clock's parents). How do you think?
> > > >
> > > 
> > > How about we recalc accuracies and rates in addition to the patch
> > > from Mike? That will fix everything?
> > 
> > Hi Stephen,
> > 
> > It works!
> > 
> > I'll send a new series of MT2701 clock support in few days. Should I
> > include this patch in my series? Or you'll merge it into clk-next
> > directly?
> > 
> 
> Thanks. I can take that as a tested-by? I can merge it into

Yes, please feel free to add:

Tested-by: James Liao <jamesjj.l...@mediatek.com>

> clk-next directly, but do we need to put the mt2701 patches on a
> separate branch to merge into arm-soc? If so we'll need to put
> this patch first to avoid bisection failures.

I prefer to merge clk driver into mainline first. Patches that depend on
mt2701 clks such as dtsi can base on next kernel release.


Best regards,

James

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

Hi Stephen,

On Fri, 2016-08-12 at 17:39 -0700, Stephen Boyd wrote:
> On 08/12, James Liao wrote:
> > On Wed, 2016-08-10 at 14:09 -0700, Stephen Boyd wrote:
> > > (Including lists)
> > > 
> > > On 08/09, James Liao wrote:
> > > > On Wed, 2016-08-03 at 13:46 +0800, James Liao wrote:
> > > >>
> > > >> Hi Mike,
> > > >>
> > > >> Do you have new patches to fix new clock parents? If not, I think we 
> > > >> can
> > > >> use my patch first. Is it okay?
> > > >>
> > > >
> > > > Hi Stephen,
> > > >
> > > > Do you have comments for the bug fixing? I prefer to use my patch (clk:
> > > > fix initial state of critical clock's parents). How do you think?
> > > >
> > > 
> > > How about we recalc accuracies and rates in addition to the patch
> > > from Mike? That will fix everything?
> > 
> > Hi Stephen,
> > 
> > It works!
> > 
> > I'll send a new series of MT2701 clock support in few days. Should I
> > include this patch in my series? Or you'll merge it into clk-next
> > directly?
> > 
> 
> Thanks. I can take that as a tested-by? I can merge it into

Yes, please feel free to add:

Tested-by: James Liao 

> clk-next directly, but do we need to put the mt2701 patches on a
> separate branch to merge into arm-soc? If so we'll need to put
> this patch first to avoid bisection failures.

I prefer to merge clk driver into mainline first. Patches that depend on
mt2701 clks such as dtsi can base on next kernel release.


Best regards,

James

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

On Wed, 2016-08-10 at 14:09 -0700, Stephen Boyd wrote:
> (Including lists)
> 
> On 08/09, James Liao wrote:
> > On Wed, 2016-08-03 at 13:46 +0800, James Liao wrote:
> >>
> >> Hi Mike,
> >>
> >> Do you have new patches to fix new clock parents? If not, I think we can
> >> use my patch first. Is it okay?
> >>
> >
> > Hi Stephen,
> >
> > Do you have comments for the bug fixing? I prefer to use my patch (clk:
> > fix initial state of critical clock's parents). How do you think?
> >
> 
> How about we recalc accuracies and rates in addition to the patch
> from Mike? That will fix everything?

Hi Stephen,

It works!

I'll send a new series of MT2701 clock support in few days. Should I
include this patch in my series? Or you'll merge it into clk-next
directly?


Best regards,

James

> ---8<
> From: Michael Turquette <mturque...@baylibre.com>
> Subject: [PATCH] clk: migrate ref counts when orphans are reunited
> 
> It's always nice to see families reunited, and this is equally true when
> talking about parent clocks and their children. However, if the orphan
> clk had a positive prepare_count or enable_count, then we would not
> migrate those counts up the parent chain correctly.
> 
> This has manifested with the recent critical clocks feature, which often
> enables clocks very early, before their parents have been registered.
> 
> Fixed by replacing the call to clk_core_reparent with calls to
> __clk_set_parent_{before,after}.
> 
> Cc: James Liao <jamesjj.l...@mediatek.com>
> Cc: Erin Lo <erin...@mediatek.com>
> Signed-off-by: Michael Turquette <mturque...@baylibre.com>
> [sb...@codeaurora.org: Recalc accuracies and rates too]
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
> ---
>  drivers/clk/clk.c | 12 ++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 820a939fb6bb..dc3fff2bf839 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -2449,8 +2449,16 @@ static int __clk_core_init(struct clk_core *core)
>   hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, child_node) {
>   struct clk_core *parent = __clk_init_parent(orphan);
>  
> - if (parent)
> - clk_core_reparent(orphan, parent);
> + /*
> +  * we could call __clk_set_parent, but that would result in a
> +  * reducant call to the .set_rate op, if it exists
> +  */
> + if (parent) {
> + __clk_set_parent_before(orphan, parent);
> + __clk_set_parent_after(orphan, parent, NULL);
> + __clk_recalc_accuracies(orphan);
> + __clk_recalc_rates(orphan, 0);
> + }
>   }
>  
>   /*

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

On Wed, 2016-08-10 at 14:09 -0700, Stephen Boyd wrote:
> (Including lists)
> 
> On 08/09, James Liao wrote:
> > On Wed, 2016-08-03 at 13:46 +0800, James Liao wrote:
> >>
> >> Hi Mike,
> >>
> >> Do you have new patches to fix new clock parents? If not, I think we can
> >> use my patch first. Is it okay?
> >>
> >
> > Hi Stephen,
> >
> > Do you have comments for the bug fixing? I prefer to use my patch (clk:
> > fix initial state of critical clock's parents). How do you think?
> >
> 
> How about we recalc accuracies and rates in addition to the patch
> from Mike? That will fix everything?

Hi Stephen,

It works!

I'll send a new series of MT2701 clock support in few days. Should I
include this patch in my series? Or you'll merge it into clk-next
directly?


Best regards,

James

> ---8<
> From: Michael Turquette 
> Subject: [PATCH] clk: migrate ref counts when orphans are reunited
> 
> It's always nice to see families reunited, and this is equally true when
> talking about parent clocks and their children. However, if the orphan
> clk had a positive prepare_count or enable_count, then we would not
> migrate those counts up the parent chain correctly.
> 
> This has manifested with the recent critical clocks feature, which often
> enables clocks very early, before their parents have been registered.
> 
> Fixed by replacing the call to clk_core_reparent with calls to
> __clk_set_parent_{before,after}.
> 
> Cc: James Liao 
> Cc: Erin Lo 
> Signed-off-by: Michael Turquette 
> [sb...@codeaurora.org: Recalc accuracies and rates too]
> Signed-off-by: Stephen Boyd 
> ---
>  drivers/clk/clk.c | 12 ++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 820a939fb6bb..dc3fff2bf839 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -2449,8 +2449,16 @@ static int __clk_core_init(struct clk_core *core)
>   hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, child_node) {
>   struct clk_core *parent = __clk_init_parent(orphan);
>  
> - if (parent)
> - clk_core_reparent(orphan, parent);
> + /*
> +  * we could call __clk_set_parent, but that would result in a
> +  * reducant call to the .set_rate op, if it exists
> +  */
> + if (parent) {
> + __clk_set_parent_before(orphan, parent);
> + __clk_set_parent_after(orphan, parent, NULL);
> + __clk_recalc_accuracies(orphan);
> + __clk_recalc_rates(orphan, 0);
> + }
>   }
>  
>   /*

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

On Wed, 2016-08-03 at 13:46 +0800, James Liao wrote:
> On Mon, 2016-07-11 at 16:24 +0800, James Liao wrote:
> > Hi Mike,
> > 
> > On Fri, 2016-07-08 at 16:32 -0700, Michael Turquette wrote:
> > > Hi James,
> > > 
> > > Quoting James Liao (2016-07-03 20:51:48)
> > > > On Fri, 2016-07-01 at 18:21 -0700, Stephen Boyd wrote:
> > > > > (Resending to everyone)
> > > > > 
> > > > > On 06/22, Erin Lo wrote:
> > > > > > From: James Liao <jamesjj.l...@mediatek.com>
> > > > > > 
> > > > > > This patch fixed wrong state of parent clocks if they are registered
> > > > > > after critical clocks.
> > > > > > 
> > > > > > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > > > > > Signed-off-by: Erin Lo <erin...@mediatek.com>
> > > > > 
> > > > > It would be nice if you included the information about the
> > > > > problem from James' previous mail. This says what it does, but
> > > > > doesn't explain what the problem is and how it is fixing it.
> > > > > 
> > > > > > ---
> > > > > >  drivers/clk/clk.c | 9 -
> > > > > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > > > > 
> > > > > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > > > > > index d584004..e9f5f89 100644
> > > > > > --- a/drivers/clk/clk.c
> > > > > > +++ b/drivers/clk/clk.c
> > > > > > @@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core 
> > > > > > *core)
> > > > > > hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, 
> > > > > > child_node) {
> > > > > > struct clk_core *parent = __clk_init_parent(orphan);
> > > > > >  
> > > > > > -   if (parent)
> > > > > > +   if (parent) {
> > > > > > clk_core_reparent(orphan, parent);
> > > > > > +
> > > > > > +   if (orphan->prepare_count)
> > > > > > +   clk_core_prepare(parent);
> > > > > > +
> > > > > > +   if (orphan->enable_count)
> > > > > > +   clk_core_enable(parent);
> > > > > > +   }
> > > > > > }
> > > > > 
> > > > > I'm pretty sure I pointed this problem out to Mike when the
> > > > > critical clk patches were being pushed. I can't recall what the
> > > > > plan was though to fix the problem. I'm pretty sure he said that
> > > > > clk_core_reparent() would take care of it, but obviously it is
> > > > > not doing that. Or perhaps it was that clk handoff should figure
> > > > > out that the parents of a critical clk are also on and thus keep
> > > > > them on.
> > > > 
> > > > Hi Mike
> > > > 
> > > > Is there any other patch to fix this issue? Or did I misuse critical
> > > > clock flag?
> > > 
> > > There is no fix yes. Your fix is basically correct. I was mistaken back
> > > when I told you and Stephen that the framework already took care of
> > > this.
> > > 
> > > However, instead of "open coding" this solution, I would rather re-use
> > > the __clk_set_parent_{before,after} helpers instead. Can you review/test
> > > the following patch and let me know what you think?
> > > 
> > > Thanks,
> > > Mike
> > > 
> > > 
> > > 
> > > From c0163b3f719b1e219b28ad425f94f9ef54a25a8f Mon Sep 17 00:00:00 2001
> > > From: Michael Turquette <mturque...@baylibre.com>
> > > Date: Fri, 8 Jul 2016 16:05:22 -0700
> > > Subject: [PATCH] clk: migrate ref counts when orphans are reunited
> > > 
> > > It's always nice to see families reunited, and this is equally true when
> > > talking about parent clocks and their children. However, if the orphan
> > > clk had a positive prepare_count or enable_count, then we would not
> > > migrate those counts up the parent chain correctly.
> > > 
> > > This has manifested with the recent critical clocks feature, which often
> > > enables clocks very early, before their parents have been registered.
> > > 

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

On Wed, 2016-08-03 at 13:46 +0800, James Liao wrote:
> On Mon, 2016-07-11 at 16:24 +0800, James Liao wrote:
> > Hi Mike,
> > 
> > On Fri, 2016-07-08 at 16:32 -0700, Michael Turquette wrote:
> > > Hi James,
> > > 
> > > Quoting James Liao (2016-07-03 20:51:48)
> > > > On Fri, 2016-07-01 at 18:21 -0700, Stephen Boyd wrote:
> > > > > (Resending to everyone)
> > > > > 
> > > > > On 06/22, Erin Lo wrote:
> > > > > > From: James Liao 
> > > > > > 
> > > > > > This patch fixed wrong state of parent clocks if they are registered
> > > > > > after critical clocks.
> > > > > > 
> > > > > > Signed-off-by: James Liao 
> > > > > > Signed-off-by: Erin Lo 
> > > > > 
> > > > > It would be nice if you included the information about the
> > > > > problem from James' previous mail. This says what it does, but
> > > > > doesn't explain what the problem is and how it is fixing it.
> > > > > 
> > > > > > ---
> > > > > >  drivers/clk/clk.c | 9 -
> > > > > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > > > > 
> > > > > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > > > > > index d584004..e9f5f89 100644
> > > > > > --- a/drivers/clk/clk.c
> > > > > > +++ b/drivers/clk/clk.c
> > > > > > @@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core 
> > > > > > *core)
> > > > > > hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, 
> > > > > > child_node) {
> > > > > > struct clk_core *parent = __clk_init_parent(orphan);
> > > > > >  
> > > > > > -   if (parent)
> > > > > > +   if (parent) {
> > > > > > clk_core_reparent(orphan, parent);
> > > > > > +
> > > > > > +   if (orphan->prepare_count)
> > > > > > +   clk_core_prepare(parent);
> > > > > > +
> > > > > > +   if (orphan->enable_count)
> > > > > > +   clk_core_enable(parent);
> > > > > > +   }
> > > > > > }
> > > > > 
> > > > > I'm pretty sure I pointed this problem out to Mike when the
> > > > > critical clk patches were being pushed. I can't recall what the
> > > > > plan was though to fix the problem. I'm pretty sure he said that
> > > > > clk_core_reparent() would take care of it, but obviously it is
> > > > > not doing that. Or perhaps it was that clk handoff should figure
> > > > > out that the parents of a critical clk are also on and thus keep
> > > > > them on.
> > > > 
> > > > Hi Mike
> > > > 
> > > > Is there any other patch to fix this issue? Or did I misuse critical
> > > > clock flag?
> > > 
> > > There is no fix yes. Your fix is basically correct. I was mistaken back
> > > when I told you and Stephen that the framework already took care of
> > > this.
> > > 
> > > However, instead of "open coding" this solution, I would rather re-use
> > > the __clk_set_parent_{before,after} helpers instead. Can you review/test
> > > the following patch and let me know what you think?
> > > 
> > > Thanks,
> > > Mike
> > > 
> > > 
> > > 
> > > From c0163b3f719b1e219b28ad425f94f9ef54a25a8f Mon Sep 17 00:00:00 2001
> > > From: Michael Turquette 
> > > Date: Fri, 8 Jul 2016 16:05:22 -0700
> > > Subject: [PATCH] clk: migrate ref counts when orphans are reunited
> > > 
> > > It's always nice to see families reunited, and this is equally true when
> > > talking about parent clocks and their children. However, if the orphan
> > > clk had a positive prepare_count or enable_count, then we would not
> > > migrate those counts up the parent chain correctly.
> > > 
> > > This has manifested with the recent critical clocks feature, which often
> > > enables clocks very early, before their parents have been registered.
> > > 
> > > Fixed by replacing the call to clk_core_reparent with calls to
> > > __clk_set_parent_{before,afte

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

On Mon, 2016-07-11 at 16:24 +0800, James Liao wrote:
> Hi Mike,
> 
> On Fri, 2016-07-08 at 16:32 -0700, Michael Turquette wrote:
> > Hi James,
> > 
> > Quoting James Liao (2016-07-03 20:51:48)
> > > On Fri, 2016-07-01 at 18:21 -0700, Stephen Boyd wrote:
> > > > (Resending to everyone)
> > > > 
> > > > On 06/22, Erin Lo wrote:
> > > > > From: James Liao <jamesjj.l...@mediatek.com>
> > > > > 
> > > > > This patch fixed wrong state of parent clocks if they are registered
> > > > > after critical clocks.
> > > > > 
> > > > > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > > > > Signed-off-by: Erin Lo <erin...@mediatek.com>
> > > > 
> > > > It would be nice if you included the information about the
> > > > problem from James' previous mail. This says what it does, but
> > > > doesn't explain what the problem is and how it is fixing it.
> > > > 
> > > > > ---
> > > > >  drivers/clk/clk.c | 9 -
> > > > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > > > > index d584004..e9f5f89 100644
> > > > > --- a/drivers/clk/clk.c
> > > > > +++ b/drivers/clk/clk.c
> > > > > @@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core 
> > > > > *core)
> > > > > hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, 
> > > > > child_node) {
> > > > > struct clk_core *parent = __clk_init_parent(orphan);
> > > > >  
> > > > > -   if (parent)
> > > > > +   if (parent) {
> > > > > clk_core_reparent(orphan, parent);
> > > > > +
> > > > > +   if (orphan->prepare_count)
> > > > > +   clk_core_prepare(parent);
> > > > > +
> > > > > +   if (orphan->enable_count)
> > > > > +   clk_core_enable(parent);
> > > > > +   }
> > > > > }
> > > > 
> > > > I'm pretty sure I pointed this problem out to Mike when the
> > > > critical clk patches were being pushed. I can't recall what the
> > > > plan was though to fix the problem. I'm pretty sure he said that
> > > > clk_core_reparent() would take care of it, but obviously it is
> > > > not doing that. Or perhaps it was that clk handoff should figure
> > > > out that the parents of a critical clk are also on and thus keep
> > > > them on.
> > > 
> > > Hi Mike
> > > 
> > > Is there any other patch to fix this issue? Or did I misuse critical
> > > clock flag?
> > 
> > There is no fix yes. Your fix is basically correct. I was mistaken back
> > when I told you and Stephen that the framework already took care of
> > this.
> > 
> > However, instead of "open coding" this solution, I would rather re-use
> > the __clk_set_parent_{before,after} helpers instead. Can you review/test
> > the following patch and let me know what you think?
> > 
> > Thanks,
> > Mike
> > 
> > 
> > 
> > From c0163b3f719b1e219b28ad425f94f9ef54a25a8f Mon Sep 17 00:00:00 2001
> > From: Michael Turquette <mturque...@baylibre.com>
> > Date: Fri, 8 Jul 2016 16:05:22 -0700
> > Subject: [PATCH] clk: migrate ref counts when orphans are reunited
> > 
> > It's always nice to see families reunited, and this is equally true when
> > talking about parent clocks and their children. However, if the orphan
> > clk had a positive prepare_count or enable_count, then we would not
> > migrate those counts up the parent chain correctly.
> > 
> > This has manifested with the recent critical clocks feature, which often
> > enables clocks very early, before their parents have been registered.
> > 
> > Fixed by replacing the call to clk_core_reparent with calls to
> > __clk_set_parent_{before,after}.
> > 
> > Cc: James Liao <jamesjj.l...@mediatek.com>
> > Cc: Erin Lo <erin...@mediatek.com>
> > Signed-off-by: Michael Turquette <mturque...@baylibre.com>
> > ---
> >  drivers/clk/clk.c | 10 --
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

On Mon, 2016-07-11 at 16:24 +0800, James Liao wrote:
> Hi Mike,
> 
> On Fri, 2016-07-08 at 16:32 -0700, Michael Turquette wrote:
> > Hi James,
> > 
> > Quoting James Liao (2016-07-03 20:51:48)
> > > On Fri, 2016-07-01 at 18:21 -0700, Stephen Boyd wrote:
> > > > (Resending to everyone)
> > > > 
> > > > On 06/22, Erin Lo wrote:
> > > > > From: James Liao 
> > > > > 
> > > > > This patch fixed wrong state of parent clocks if they are registered
> > > > > after critical clocks.
> > > > > 
> > > > > Signed-off-by: James Liao 
> > > > > Signed-off-by: Erin Lo 
> > > > 
> > > > It would be nice if you included the information about the
> > > > problem from James' previous mail. This says what it does, but
> > > > doesn't explain what the problem is and how it is fixing it.
> > > > 
> > > > > ---
> > > > >  drivers/clk/clk.c | 9 -
> > > > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > > > > index d584004..e9f5f89 100644
> > > > > --- a/drivers/clk/clk.c
> > > > > +++ b/drivers/clk/clk.c
> > > > > @@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core 
> > > > > *core)
> > > > > hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, 
> > > > > child_node) {
> > > > > struct clk_core *parent = __clk_init_parent(orphan);
> > > > >  
> > > > > -   if (parent)
> > > > > +   if (parent) {
> > > > > clk_core_reparent(orphan, parent);
> > > > > +
> > > > > +   if (orphan->prepare_count)
> > > > > +   clk_core_prepare(parent);
> > > > > +
> > > > > +   if (orphan->enable_count)
> > > > > +   clk_core_enable(parent);
> > > > > +   }
> > > > > }
> > > > 
> > > > I'm pretty sure I pointed this problem out to Mike when the
> > > > critical clk patches were being pushed. I can't recall what the
> > > > plan was though to fix the problem. I'm pretty sure he said that
> > > > clk_core_reparent() would take care of it, but obviously it is
> > > > not doing that. Or perhaps it was that clk handoff should figure
> > > > out that the parents of a critical clk are also on and thus keep
> > > > them on.
> > > 
> > > Hi Mike
> > > 
> > > Is there any other patch to fix this issue? Or did I misuse critical
> > > clock flag?
> > 
> > There is no fix yes. Your fix is basically correct. I was mistaken back
> > when I told you and Stephen that the framework already took care of
> > this.
> > 
> > However, instead of "open coding" this solution, I would rather re-use
> > the __clk_set_parent_{before,after} helpers instead. Can you review/test
> > the following patch and let me know what you think?
> > 
> > Thanks,
> > Mike
> > 
> > 
> > 
> > From c0163b3f719b1e219b28ad425f94f9ef54a25a8f Mon Sep 17 00:00:00 2001
> > From: Michael Turquette 
> > Date: Fri, 8 Jul 2016 16:05:22 -0700
> > Subject: [PATCH] clk: migrate ref counts when orphans are reunited
> > 
> > It's always nice to see families reunited, and this is equally true when
> > talking about parent clocks and their children. However, if the orphan
> > clk had a positive prepare_count or enable_count, then we would not
> > migrate those counts up the parent chain correctly.
> > 
> > This has manifested with the recent critical clocks feature, which often
> > enables clocks very early, before their parents have been registered.
> > 
> > Fixed by replacing the call to clk_core_reparent with calls to
> > __clk_set_parent_{before,after}.
> > 
> > Cc: James Liao 
> > Cc: Erin Lo 
> > Signed-off-by: Michael Turquette 
> > ---
> >  drivers/clk/clk.c | 10 --
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index 820a939fb6bb..70efe4c4e0cc 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -2449,8 +2449,14 @@ static int __clk_core_in

[PATCH v8 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

Some power domain comsumers may init before module_init.
So the power domain provider (scpsys) need to be initialized
earlier too.

Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
between IOMMU and multimedia HW. SMI is responsible to
enable/disable iommu and help transfer data for each multimedia
HW. Both of them have to wait until the power and clocks are
enabled.

So scpsys driver should be initialized before SMI, and SMI should
be initialized before IOMMU, and then init IOMMU consumers
(display/vdec/venc/camera etc.).

IOMMU is subsys_init by default. So we need to init scpsys driver
before subsys_init.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 1f3555a..e806cb7 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -618,4 +618,21 @@ static struct platform_driver scpsys_drv = {
.of_match_table = of_match_ptr(of_scpsys_match_tbl),
},
 };
-builtin_platform_driver(scpsys_drv);
+
+static int __init scpsys_drv_init(void)
+{
+   return platform_driver_register(_drv);
+}
+
+/*
+ * There are some Mediatek drivers which depend on the power domain driver need
+ * to probe in earlier initcall levels. So scpsys driver also need to probe
+ * earlier.
+ *
+ * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU and
+ * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
+ * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
+ * IOMMU drivers are initialized during subsys_init by default, so we need to
+ * move SMI and scpsys drivers to subsys_init or earlier init levels.
+ */
+subsys_initcall(scpsys_drv_init);
-- 
1.9.1

[PATCH v8 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

Some power domain comsumers may init before module_init.
So the power domain provider (scpsys) need to be initialized
earlier too.

Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
between IOMMU and multimedia HW. SMI is responsible to
enable/disable iommu and help transfer data for each multimedia
HW. Both of them have to wait until the power and clocks are
enabled.

So scpsys driver should be initialized before SMI, and SMI should
be initialized before IOMMU, and then init IOMMU consumers
(display/vdec/venc/camera etc.).

IOMMU is subsys_init by default. So we need to init scpsys driver
before subsys_init.

Signed-off-by: James Liao 
Reviewed-by: Kevin Hilman 
---
 drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 1f3555a..e806cb7 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -618,4 +618,21 @@ static struct platform_driver scpsys_drv = {
.of_match_table = of_match_ptr(of_scpsys_match_tbl),
},
 };
-builtin_platform_driver(scpsys_drv);
+
+static int __init scpsys_drv_init(void)
+{
+   return platform_driver_register(_drv);
+}
+
+/*
+ * There are some Mediatek drivers which depend on the power domain driver need
+ * to probe in earlier initcall levels. So scpsys driver also need to probe
+ * earlier.
+ *
+ * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU and
+ * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
+ * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
+ * IOMMU drivers are initialized during subsys_init by default, so we need to
+ * move SMI and scpsys drivers to subsys_init or earlier init levels.
+ */
+subsys_initcall(scpsys_drv_init);
-- 
1.9.1

[PATCH v8 4/4] soc: mediatek: Add MT2701 scpsys driver

[James Liao]

From: Shunli Wang <shunli.w...@mediatek.com>

Add scpsys driver for MT2701.

mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
be enabled on both arm64 and arm platforms.

Signed-off-by: Shunli Wang <shunli.w...@mediatek.com>
Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 drivers/soc/mediatek/Kconfig  |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c | 120 +-
 2 files changed, 119 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 0a4ea80..609bb34 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
 config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
-   default ARM64 && ARCH_MEDIATEK
+   default ARCH_MEDIATEK
select REGMAP
select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index e806cb7..b94b4e4 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -27,8 +28,13 @@
 #define SPM_VEN_PWR_CON0x0230
 #define SPM_ISP_PWR_CON0x0238
 #define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON   0x0280
 #define SPM_VEN2_PWR_CON   0x0298
-#define SPM_AUDIO_PWR_CON  0x029c
+#define SPM_AUDIO_PWR_CON  0x029c  /* MT8173 */
+#define SPM_BDP_PWR_CON0x029c  /* MT2701 */
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
@@ -42,10 +48,15 @@
 #define PWR_ON_2ND_BIT BIT(3)
 #define PWR_CLK_DIS_BITBIT(4)
 
+#define PWR_STATUS_CONNBIT(1)
 #define PWR_STATUS_DISPBIT(3)
 #define PWR_STATUS_MFG BIT(4)
 #define PWR_STATUS_ISP BIT(5)
 #define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
 #define PWR_STATUS_VENC_LT BIT(20)
 #define PWR_STATUS_VENCBIT(21)
 #define PWR_STATUS_MFG_2D  BIT(22)
@@ -59,6 +70,7 @@ enum clk_id {
CLK_MFG,
CLK_VENC,
CLK_VENC_LT,
+   CLK_ETHIF,
CLK_MAX,
 };
 
@@ -321,7 +333,8 @@ static void init_clks(struct platform_device *pdev, struct 
clk *clk[CLK_MAX])
CLK_MM,
CLK_MFG,
CLK_VENC,
-   CLK_VENC_LT
+   CLK_VENC_LT,
+   CLK_ETHIF
};
 
static const char * const clk_names[] = {
@@ -329,6 +342,7 @@ static void init_clks(struct platform_device *pdev, struct 
clk *clk[CLK_MAX])
"mfg",
"venc",
"venc_lt",
+   "ethif",
};
 
int i;
@@ -460,6 +474,105 @@ static void mtk_register_power_domains(struct 
platform_device *pdev,
 }
 
 /*
+ * MT2701 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt2701[] = {
+   [MT2701_POWER_DOMAIN_CONN] = {
+   .name = "conn",
+   .sta_mask = PWR_STATUS_CONN,
+   .ctl_offs = SPM_CONN_PWR_CON,
+   .bus_prot_mask = 0x0104,
+   .clk_id = {CLK_NONE},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_DISP] = {
+   .name = "disp",
+   .sta_mask = PWR_STATUS_DISP,
+   .ctl_offs = SPM_DIS_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .clk_id = {CLK_MM},
+   .bus_prot_mask = 0x0002,
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_MFG] = {
+   .name = "mfg",
+   .sta_mask = PWR_STATUS_MFG,
+   .ctl_offs = SPM_MFG_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MFG},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_VDEC] = {
+   .name = "vdec",
+   .sta_mask = PWR_STATUS_VDEC,
+   .ctl_offs = SPM_VDE_PWR_CON,
+ 

[PATCH v8 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Refine scpsys driver common code to support multiple SoC / platform.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 363 +++---
 1 file changed, 220 insertions(+), 143 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 837effe..1f3555a 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,17 +11,15 @@
  * GNU General Public License for more details.
  */
 #include 
-#include 
+#include 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
+#include 
+
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -34,6 +32,7 @@
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
+
 #define SPM_PWR_STATUS 0x060c
 #define SPM_PWR_STATUS_2ND 0x0610
 
@@ -55,12 +54,12 @@
 #define PWR_STATUS_USB BIT(25)
 
 enum clk_id {
-   MT8173_CLK_NONE,
-   MT8173_CLK_MM,
-   MT8173_CLK_MFG,
-   MT8173_CLK_VENC,
-   MT8173_CLK_VENC_LT,
-   MT8173_CLK_MAX,
+   CLK_NONE,
+   CLK_MM,
+   CLK_MFG,
+   CLK_VENC,
+   CLK_VENC_LT,
+   CLK_MAX,
 };
 
 #define MAX_CLKS   2
@@ -76,98 +75,6 @@ struct scp_domain_data {
bool active_wakeup;
 };
 
-static const struct scp_domain_data scp_domain_data[] = {
-   [MT8173_POWER_DOMAIN_VDEC] = {
-   .name = "vdec",
-   .sta_mask = PWR_STATUS_VDEC,
-   .ctl_offs = SPM_VDE_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_VENC] = {
-   .name = "venc",
-   .sta_mask = PWR_STATUS_VENC,
-   .ctl_offs = SPM_VEN_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
-   },
-   [MT8173_POWER_DOMAIN_ISP] = {
-   .name = "isp",
-   .sta_mask = PWR_STATUS_ISP,
-   .ctl_offs = SPM_ISP_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_MM] = {
-   .name = "mm",
-   .sta_mask = PWR_STATUS_DISP,
-   .ctl_offs = SPM_DIS_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
-   MT8173_TOP_AXI_PROT_EN_MM_M1,
-   },
-   [MT8173_POWER_DOMAIN_VENC_LT] = {
-   .name = "venc_lt",
-   .sta_mask = PWR_STATUS_VENC_LT,
-   .ctl_offs = SPM_VEN2_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
-   },
-   [MT8173_POWER_DOMAIN_AUDIO] = {
-   .name = "audio",
-   .sta_mask = PWR_STATUS_AUDIO,
-   .ctl_offs = SPM_AUDIO_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_USB] = {
-   .name = "usb",
-   .sta_mask = PWR_STATUS_USB,
-   .ctl_offs = SPM_USB_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   .active_wakeup = true,
-   },
-   [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
-   .name = "mfg_async",
-   .sta_mask = PWR_STATUS_MFG_ASYNC,
-   .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = 0,
-   .clk_id = {MT8173_CLK_MFG},
-   },
-   [MT8173_POWER_DOMAIN_MFG_2D] = {
-   .name = "mfg_2d",
-   .sta_mask = PWR_STATUS_MFG_2D,
-   .ctl_offs = SPM_MFG_2D_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_MFG] = {
-   .name = "mfg",
-   .sta_mask = PWR_STATUS_MFG,
-   .ctl_offs = SPM_MFG_PWR_CON,
-   .sram_pdn_bits = GENMASK(13, 8),
-   .

[PATCH v8 4/4] soc: mediatek: Add MT2701 scpsys driver

[James Liao]

From: Shunli Wang 

Add scpsys driver for MT2701.

mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
be enabled on both arm64 and arm platforms.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Reviewed-by: Kevin Hilman 
---
 drivers/soc/mediatek/Kconfig  |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c | 120 +-
 2 files changed, 119 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 0a4ea80..609bb34 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
 config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
-   default ARM64 && ARCH_MEDIATEK
+   default ARCH_MEDIATEK
select REGMAP
select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index e806cb7..b94b4e4 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -27,8 +28,13 @@
 #define SPM_VEN_PWR_CON0x0230
 #define SPM_ISP_PWR_CON0x0238
 #define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON   0x0280
 #define SPM_VEN2_PWR_CON   0x0298
-#define SPM_AUDIO_PWR_CON  0x029c
+#define SPM_AUDIO_PWR_CON  0x029c  /* MT8173 */
+#define SPM_BDP_PWR_CON0x029c  /* MT2701 */
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
@@ -42,10 +48,15 @@
 #define PWR_ON_2ND_BIT BIT(3)
 #define PWR_CLK_DIS_BITBIT(4)
 
+#define PWR_STATUS_CONNBIT(1)
 #define PWR_STATUS_DISPBIT(3)
 #define PWR_STATUS_MFG BIT(4)
 #define PWR_STATUS_ISP BIT(5)
 #define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
 #define PWR_STATUS_VENC_LT BIT(20)
 #define PWR_STATUS_VENCBIT(21)
 #define PWR_STATUS_MFG_2D  BIT(22)
@@ -59,6 +70,7 @@ enum clk_id {
CLK_MFG,
CLK_VENC,
CLK_VENC_LT,
+   CLK_ETHIF,
CLK_MAX,
 };
 
@@ -321,7 +333,8 @@ static void init_clks(struct platform_device *pdev, struct 
clk *clk[CLK_MAX])
CLK_MM,
CLK_MFG,
CLK_VENC,
-   CLK_VENC_LT
+   CLK_VENC_LT,
+   CLK_ETHIF
};
 
static const char * const clk_names[] = {
@@ -329,6 +342,7 @@ static void init_clks(struct platform_device *pdev, struct 
clk *clk[CLK_MAX])
"mfg",
"venc",
"venc_lt",
+   "ethif",
};
 
int i;
@@ -460,6 +474,105 @@ static void mtk_register_power_domains(struct 
platform_device *pdev,
 }
 
 /*
+ * MT2701 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt2701[] = {
+   [MT2701_POWER_DOMAIN_CONN] = {
+   .name = "conn",
+   .sta_mask = PWR_STATUS_CONN,
+   .ctl_offs = SPM_CONN_PWR_CON,
+   .bus_prot_mask = 0x0104,
+   .clk_id = {CLK_NONE},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_DISP] = {
+   .name = "disp",
+   .sta_mask = PWR_STATUS_DISP,
+   .ctl_offs = SPM_DIS_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .clk_id = {CLK_MM},
+   .bus_prot_mask = 0x0002,
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_MFG] = {
+   .name = "mfg",
+   .sta_mask = PWR_STATUS_MFG,
+   .ctl_offs = SPM_MFG_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MFG},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_VDEC] = {
+   .name = "vdec",
+   .sta_mask = PWR_STATUS_VDEC,
+   .ctl_offs = SPM_VDE_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MM},
+   .a

[PATCH v8 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Refine scpsys driver common code to support multiple SoC / platform.

Signed-off-by: James Liao 
Reviewed-by: Kevin Hilman 
---
 drivers/soc/mediatek/mtk-scpsys.c | 363 +++---
 1 file changed, 220 insertions(+), 143 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 837effe..1f3555a 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,17 +11,15 @@
  * GNU General Public License for more details.
  */
 #include 
-#include 
+#include 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
+#include 
+
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -34,6 +32,7 @@
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
+
 #define SPM_PWR_STATUS 0x060c
 #define SPM_PWR_STATUS_2ND 0x0610
 
@@ -55,12 +54,12 @@
 #define PWR_STATUS_USB BIT(25)
 
 enum clk_id {
-   MT8173_CLK_NONE,
-   MT8173_CLK_MM,
-   MT8173_CLK_MFG,
-   MT8173_CLK_VENC,
-   MT8173_CLK_VENC_LT,
-   MT8173_CLK_MAX,
+   CLK_NONE,
+   CLK_MM,
+   CLK_MFG,
+   CLK_VENC,
+   CLK_VENC_LT,
+   CLK_MAX,
 };
 
 #define MAX_CLKS   2
@@ -76,98 +75,6 @@ struct scp_domain_data {
bool active_wakeup;
 };
 
-static const struct scp_domain_data scp_domain_data[] = {
-   [MT8173_POWER_DOMAIN_VDEC] = {
-   .name = "vdec",
-   .sta_mask = PWR_STATUS_VDEC,
-   .ctl_offs = SPM_VDE_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_VENC] = {
-   .name = "venc",
-   .sta_mask = PWR_STATUS_VENC,
-   .ctl_offs = SPM_VEN_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
-   },
-   [MT8173_POWER_DOMAIN_ISP] = {
-   .name = "isp",
-   .sta_mask = PWR_STATUS_ISP,
-   .ctl_offs = SPM_ISP_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_MM] = {
-   .name = "mm",
-   .sta_mask = PWR_STATUS_DISP,
-   .ctl_offs = SPM_DIS_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
-   MT8173_TOP_AXI_PROT_EN_MM_M1,
-   },
-   [MT8173_POWER_DOMAIN_VENC_LT] = {
-   .name = "venc_lt",
-   .sta_mask = PWR_STATUS_VENC_LT,
-   .ctl_offs = SPM_VEN2_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
-   },
-   [MT8173_POWER_DOMAIN_AUDIO] = {
-   .name = "audio",
-   .sta_mask = PWR_STATUS_AUDIO,
-   .ctl_offs = SPM_AUDIO_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_USB] = {
-   .name = "usb",
-   .sta_mask = PWR_STATUS_USB,
-   .ctl_offs = SPM_USB_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   .active_wakeup = true,
-   },
-   [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
-   .name = "mfg_async",
-   .sta_mask = PWR_STATUS_MFG_ASYNC,
-   .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = 0,
-   .clk_id = {MT8173_CLK_MFG},
-   },
-   [MT8173_POWER_DOMAIN_MFG_2D] = {
-   .name = "mfg_2d",
-   .sta_mask = PWR_STATUS_MFG_2D,
-   .ctl_offs = SPM_MFG_2D_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_MFG] = {
-   .name = "mfg",
-   .sta_mask = PWR_STATUS_MFG,
-   .ctl_offs = SPM_MFG_PWR_CON,
-   .sram_pdn_bits = GENMASK(13, 8),
-   .sram_pdn_ack_bits = GENMASK(21, 16),
- 

[PATCH v8 3/4] soc: mediatek: Add MT2701 power dt-bindings

[James Liao]

From: Shunli Wang <shunli.w...@mediatek.com>

Add power dt-bindings for MT2701.

Signed-off-by: Shunli Wang <shunli.w...@mediatek.com>
Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 .../devicetree/bindings/soc/mediatek/scpsys.txt| 13 +++
 include/dt-bindings/power/mt2701-power.h   | 27 ++
 2 files changed, 35 insertions(+), 5 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 
b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index e8f15e3..16fe94d 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -9,17 +9,20 @@ domain control.
 
 The driver implements the Generic PM domain bindings described in
 power/power_domain.txt. It provides the power domains defined in
-include/dt-bindings/power/mt8173-power.h.
+include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
 
 Required properties:
-- compatible: Must be "mediatek,mt8173-scpsys"
+- compatible: Should be one of:
+   - "mediatek,mt2701-scpsys"
+   - "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
 - infracfg: must contain a phandle to the infracfg controller
 - clock, clock-names: clocks according to the common clock binding.
-  The clocks needed "mm", "mfg", "venc" and "venc_lt".
- These are the clocks which hardware needs to be enabled
- before enabling certain power domains.
+  These are clocks which hardware needs to be
+  enabled before enabling certain power domains.
+   Required clocks for MT2701: "mm", "mfg", "ethif"
+   Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:
 - vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt2701-power.h 
b/include/dt-bindings/power/mt2701-power.h
new file mode 100644
index 000..64cc826
--- /dev/null
+++ b/include/dt-bindings/power/mt2701-power.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
+
+#define MT2701_POWER_DOMAIN_CONN   0
+#define MT2701_POWER_DOMAIN_DISP   1
+#define MT2701_POWER_DOMAIN_MFG2
+#define MT2701_POWER_DOMAIN_VDEC   3
+#define MT2701_POWER_DOMAIN_ISP4
+#define MT2701_POWER_DOMAIN_BDP5
+#define MT2701_POWER_DOMAIN_ETH6
+#define MT2701_POWER_DOMAIN_HIF7
+#define MT2701_POWER_DOMAIN_IFR_MSC8
+
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
-- 
1.9.1

[PATCH v8 0/4] Mediatek MT2701 SCPSYS power domain support

[James Liao]

This series is based on v4.7-rc1 and adds scpsys power domain support
for Mediatek MT2701.

To share the code between MT2701 and MT8173, this patchset also refined
original mtk-scpsys.c to separate common codes and platform codes, so
that mtk-scpsys.c can support new SoCs more easily.

MT8173 and MT2701 scpsys init level are now subsys_init. Please refer to [1]
to see discussion details.

changes since v7:
- Add clk_id for each scp_domain_data define.
- Minor coding style changes.

changes since v6:
- Minor changes in the dt-binding document.

changes since v5:
- Rebase to v4.6-rc1.
- Add dependent clocks for MFG, ISP, ETH and HIF power domains.
- Add "ethif" as a dependent clock in scpsys dt-binding document.

changes since v4:
- Rebase to v4.5-rc4.
- Remove mtk-scpsys.h and Merge its code into mtk-scpsys.c.
- Add names for every controlling registers and bits.
- Include dt-bindings headers at the beginning of mtk-scpsys.c.
- Sort compatible string in dt-binding documents.

changes since v3:
- Implement MT8173 and MT2701 scpsys drivers in a signle file.
- Remove naming of registers that can't be shared among SoCs.

changes since v2:
- Rebase to mbgg/linux-mediatek v4.4-next/soc [1].
- Remove MTK_SCPSYS_MT8173 and MTK_SCPSYS_MT2701.
- Modify scpsys dt-binding document to support MT2701.

changes since v1:
- Make MTK_SCPSYS in Kconfig invisible from users.
- Add comments for changing scpsys init level to subsys_init.

[1] 
http://lists.infradead.org/pipermail/linux-mediatek/2015-December/003416.html

James Liao (2):
  soc: mediatek: Refine scpsys to support multiple platform
  soc: mediatek: Init MT8173 scpsys driver earlier

Shunli Wang (2):
  soc: mediatek: Add MT2701 power dt-bindings
  soc: mediatek: Add MT2701 scpsys driver

 .../devicetree/bindings/soc/mediatek/scpsys.txt|  13 +-
 drivers/soc/mediatek/Kconfig   |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c  | 500 +++--
 include/dt-bindings/power/mt2701-power.h   |  27 ++
 4 files changed, 391 insertions(+), 151 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

--
1.9.1

[PATCH v8 3/4] soc: mediatek: Add MT2701 power dt-bindings

[James Liao]

From: Shunli Wang 

Add power dt-bindings for MT2701.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Acked-by: Rob Herring 
Reviewed-by: Kevin Hilman 
---
 .../devicetree/bindings/soc/mediatek/scpsys.txt| 13 +++
 include/dt-bindings/power/mt2701-power.h   | 27 ++
 2 files changed, 35 insertions(+), 5 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 
b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index e8f15e3..16fe94d 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -9,17 +9,20 @@ domain control.
 
 The driver implements the Generic PM domain bindings described in
 power/power_domain.txt. It provides the power domains defined in
-include/dt-bindings/power/mt8173-power.h.
+include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
 
 Required properties:
-- compatible: Must be "mediatek,mt8173-scpsys"
+- compatible: Should be one of:
+   - "mediatek,mt2701-scpsys"
+   - "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
 - infracfg: must contain a phandle to the infracfg controller
 - clock, clock-names: clocks according to the common clock binding.
-  The clocks needed "mm", "mfg", "venc" and "venc_lt".
- These are the clocks which hardware needs to be enabled
- before enabling certain power domains.
+  These are clocks which hardware needs to be
+  enabled before enabling certain power domains.
+   Required clocks for MT2701: "mm", "mfg", "ethif"
+   Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:
 - vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt2701-power.h 
b/include/dt-bindings/power/mt2701-power.h
new file mode 100644
index 000..64cc826
--- /dev/null
+++ b/include/dt-bindings/power/mt2701-power.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
+
+#define MT2701_POWER_DOMAIN_CONN   0
+#define MT2701_POWER_DOMAIN_DISP   1
+#define MT2701_POWER_DOMAIN_MFG2
+#define MT2701_POWER_DOMAIN_VDEC   3
+#define MT2701_POWER_DOMAIN_ISP4
+#define MT2701_POWER_DOMAIN_BDP5
+#define MT2701_POWER_DOMAIN_ETH6
+#define MT2701_POWER_DOMAIN_HIF7
+#define MT2701_POWER_DOMAIN_IFR_MSC8
+
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
-- 
1.9.1

[PATCH v8 0/4] Mediatek MT2701 SCPSYS power domain support

[James Liao]

This series is based on v4.7-rc1 and adds scpsys power domain support
for Mediatek MT2701.

To share the code between MT2701 and MT8173, this patchset also refined
original mtk-scpsys.c to separate common codes and platform codes, so
that mtk-scpsys.c can support new SoCs more easily.

MT8173 and MT2701 scpsys init level are now subsys_init. Please refer to [1]
to see discussion details.

changes since v7:
- Add clk_id for each scp_domain_data define.
- Minor coding style changes.

changes since v6:
- Minor changes in the dt-binding document.

changes since v5:
- Rebase to v4.6-rc1.
- Add dependent clocks for MFG, ISP, ETH and HIF power domains.
- Add "ethif" as a dependent clock in scpsys dt-binding document.

changes since v4:
- Rebase to v4.5-rc4.
- Remove mtk-scpsys.h and Merge its code into mtk-scpsys.c.
- Add names for every controlling registers and bits.
- Include dt-bindings headers at the beginning of mtk-scpsys.c.
- Sort compatible string in dt-binding documents.

changes since v3:
- Implement MT8173 and MT2701 scpsys drivers in a signle file.
- Remove naming of registers that can't be shared among SoCs.

changes since v2:
- Rebase to mbgg/linux-mediatek v4.4-next/soc [1].
- Remove MTK_SCPSYS_MT8173 and MTK_SCPSYS_MT2701.
- Modify scpsys dt-binding document to support MT2701.

changes since v1:
- Make MTK_SCPSYS in Kconfig invisible from users.
- Add comments for changing scpsys init level to subsys_init.

[1] 
http://lists.infradead.org/pipermail/linux-mediatek/2015-December/003416.html

James Liao (2):
  soc: mediatek: Refine scpsys to support multiple platform
  soc: mediatek: Init MT8173 scpsys driver earlier

Shunli Wang (2):
  soc: mediatek: Add MT2701 power dt-bindings
  soc: mediatek: Add MT2701 scpsys driver

 .../devicetree/bindings/soc/mediatek/scpsys.txt|  13 +-
 drivers/soc/mediatek/Kconfig   |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c  | 500 +++--
 include/dt-bindings/power/mt2701-power.h   |  27 ++
 4 files changed, 391 insertions(+), 151 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

--
1.9.1

Re: [PATCH v7 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Hi Matthias,

On Mon, 2016-07-11 at 15:10 +0200, Matthias Brugger wrote:
> 
> On 11/07/16 10:56, James Liao wrote:
> 
> [...]
> 
> >>>>> @@ -467,28 +386,54 @@ static int scpsys_probe(struct platform_device 
> >>>>> *pdev)
> >>>>> if (PTR_ERR(scpd->supply) == -ENODEV)
> >>>>> scpd->supply = NULL;
> >>>>> else
> >>>>> -   return PTR_ERR(scpd->supply);
> >>>>> +   return ERR_CAST(scpd->supply);
> >>>>> }
> >>>>> }
> >>>>>
> >>>>> -   pd_data->num_domains = NUM_DOMAINS;
> >>>>> +   pd_data->num_domains = num;
> >>>>>
> >>>>> -   for (i = 0; i < NUM_DOMAINS; i++) {
> >>>>> +   init_clks(pdev, clk);
> >>>>> +
> >>>>> +   for (i = 0; i < num; i++) {
> >>>>> struct scp_domain *scpd = >domains[i];
> >>>>> struct generic_pm_domain *genpd = >genpd;
> >>>>> const struct scp_domain_data *data = 
> >>>>> _domain_data[i];
> >>>>>
> >>>>> +   for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
> >>>>> +   struct clk *c = clk[data->clk_id[j]];
> >>>>> +
> >>>>> +   if (IS_ERR(c)) {
> >>>>> +   dev_err(>dev, "%s: clk 
> >>>>> unavailable\n",
> >>>>> +   data->name);
> >>>>> +   return ERR_CAST(c);
> >>>>> +   }
> >>>>> +
> >>>>> +   scpd->clk[j] = c;
> >>>>
> >>>> Put this in the else branch. Apart from that is there any reason you
> >>>
> >>> Do you mean to change like this?
> >>>
> >>>   if (IS_ERR(c)) {
> >>>   ...
> >>>   return ERR_CAST(c);
> >>>   } else {
> >>>   scpd->clk[j] = c;
> >>>   }
> >>>
> >>> checkpatch.pl will warn for above code due to it returns in 'if' branch.
> >>>
> >>
> >> I tried that on top of next-20160706 and it checkpatch didn't throw any
> >> warning. Which kernel version are based on?
> >
> > I don't remember which version of checkpatch warn on this pattern. This
> > patch series develop across several kernel versions.
> 
> We as the kernel community develop against master or linux-next. We only 
> care about older kernel version in the sense that we intent hard not to 
> break any userspace/kernel or firmware/kernel interfaces. Apart from 
> that it's up to every individual to backport patches from mainline 
> kernel to his respective version. But that's nothing the community as a 
> hole can take care of.
> 
> >
> > So do you prefer to put "scpd->clk[j] = c;" into 'else' branch?
> >
> 
> Yes please :)

Yingjoe had tested in the latest checkpatch.pl and it showed checkpatch
warn on the else-branch. He had replied the results in previous email.
 
> >>>> moved the for up in the function? If not, I would prefer not to move it,
> >>>> to make it easier to read the diff.
> >>>
> >>> The new 'for' block are far different from original one. And I think
> >>> it's easy to read if we keep simple assign statements in the same block.
> >>>
> >>
> >> It's different in the sense that it checks if struct clk *c is an error.
> >> I don't see the reason why we need to move it up in the file.
> >> It's not too important but I would prefer not to move it if there is no
> >> reason.
> >
> > I think I may misunderstand your comments. Which 'for' block did you
> > mention for? 'for (i = 0; i < num ...' or 'for (j = 0; j < MAX_CLKS
> > && ...' ?
> >
> > The 'for(i)' exists in original code, this patch just change its counter
> > from 'NUM_DOMAINS' to 'num'. The 'for(j)' is a new for-block, so it was
> > not moved from other blocks.
> >
> 
> for (j = 0; j < MAX_CLKS... is present in the actual scpsys_probe in 
> linux-next (line 485 as of today). This patch moves this for a few lines 
> up, to be precise before executing this code sequence:
> 
> pd_data->domains[i] = genpd;
> scpd->scp = scp;
> 
> scpd->data = data;
> 
> 
> AFAIK there is no reason to do so. It adds unnecessary complexity to the 
> patch. So please fix this together with the other comments you got.

I see. So you prefer to put the for(j < MAX_CLKS) after 'scpd->data =
data' right? I can change it in next patch.


Best regards,

James

Re: [PATCH v7 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Hi Matthias,

On Mon, 2016-07-11 at 15:10 +0200, Matthias Brugger wrote:
> 
> On 11/07/16 10:56, James Liao wrote:
> 
> [...]
> 
> >>>>> @@ -467,28 +386,54 @@ static int scpsys_probe(struct platform_device 
> >>>>> *pdev)
> >>>>> if (PTR_ERR(scpd->supply) == -ENODEV)
> >>>>> scpd->supply = NULL;
> >>>>> else
> >>>>> -   return PTR_ERR(scpd->supply);
> >>>>> +   return ERR_CAST(scpd->supply);
> >>>>> }
> >>>>> }
> >>>>>
> >>>>> -   pd_data->num_domains = NUM_DOMAINS;
> >>>>> +   pd_data->num_domains = num;
> >>>>>
> >>>>> -   for (i = 0; i < NUM_DOMAINS; i++) {
> >>>>> +   init_clks(pdev, clk);
> >>>>> +
> >>>>> +   for (i = 0; i < num; i++) {
> >>>>> struct scp_domain *scpd = >domains[i];
> >>>>> struct generic_pm_domain *genpd = >genpd;
> >>>>> const struct scp_domain_data *data = 
> >>>>> _domain_data[i];
> >>>>>
> >>>>> +   for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
> >>>>> +   struct clk *c = clk[data->clk_id[j]];
> >>>>> +
> >>>>> +   if (IS_ERR(c)) {
> >>>>> +   dev_err(>dev, "%s: clk 
> >>>>> unavailable\n",
> >>>>> +   data->name);
> >>>>> +   return ERR_CAST(c);
> >>>>> +   }
> >>>>> +
> >>>>> +   scpd->clk[j] = c;
> >>>>
> >>>> Put this in the else branch. Apart from that is there any reason you
> >>>
> >>> Do you mean to change like this?
> >>>
> >>>   if (IS_ERR(c)) {
> >>>   ...
> >>>   return ERR_CAST(c);
> >>>   } else {
> >>>   scpd->clk[j] = c;
> >>>   }
> >>>
> >>> checkpatch.pl will warn for above code due to it returns in 'if' branch.
> >>>
> >>
> >> I tried that on top of next-20160706 and it checkpatch didn't throw any
> >> warning. Which kernel version are based on?
> >
> > I don't remember which version of checkpatch warn on this pattern. This
> > patch series develop across several kernel versions.
> 
> We as the kernel community develop against master or linux-next. We only 
> care about older kernel version in the sense that we intent hard not to 
> break any userspace/kernel or firmware/kernel interfaces. Apart from 
> that it's up to every individual to backport patches from mainline 
> kernel to his respective version. But that's nothing the community as a 
> hole can take care of.
> 
> >
> > So do you prefer to put "scpd->clk[j] = c;" into 'else' branch?
> >
> 
> Yes please :)

Yingjoe had tested in the latest checkpatch.pl and it showed checkpatch
warn on the else-branch. He had replied the results in previous email.
 
> >>>> moved the for up in the function? If not, I would prefer not to move it,
> >>>> to make it easier to read the diff.
> >>>
> >>> The new 'for' block are far different from original one. And I think
> >>> it's easy to read if we keep simple assign statements in the same block.
> >>>
> >>
> >> It's different in the sense that it checks if struct clk *c is an error.
> >> I don't see the reason why we need to move it up in the file.
> >> It's not too important but I would prefer not to move it if there is no
> >> reason.
> >
> > I think I may misunderstand your comments. Which 'for' block did you
> > mention for? 'for (i = 0; i < num ...' or 'for (j = 0; j < MAX_CLKS
> > && ...' ?
> >
> > The 'for(i)' exists in original code, this patch just change its counter
> > from 'NUM_DOMAINS' to 'num'. The 'for(j)' is a new for-block, so it was
> > not moved from other blocks.
> >
> 
> for (j = 0; j < MAX_CLKS... is present in the actual scpsys_probe in 
> linux-next (line 485 as of today). This patch moves this for a few lines 
> up, to be precise before executing this code sequence:
> 
> pd_data->domains[i] = genpd;
> scpd->scp = scp;
> 
> scpd->data = data;
> 
> 
> AFAIK there is no reason to do so. It adds unnecessary complexity to the 
> patch. So please fix this together with the other comments you got.

I see. So you prefer to put the for(j < MAX_CLKS) after 'scpd->data =
data' right? I can change it in next patch.


Best regards,

James

Re: [PATCH v7 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Hi Matthias,

On Thu, 2016-07-07 at 13:20 +0200, Matthias Brugger wrote:
> 
> On 06/07/16 07:39, James Liao wrote:
> > Hi Matthias,
> >
> > On Sat, 2016-07-02 at 18:33 +0200, Matthias Brugger wrote:
> >>
> >> On 05/16/2016 11:28 AM, James Liao wrote:
> >>> Refine scpsys driver common code to support multiple SoC / platform.
> >>>
> >>> Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> >>> Reviewed-by: Kevin Hilman <khil...@baylibre.com>
> >>> ---
> >>>   drivers/soc/mediatek/mtk-scpsys.c | 363 
> >>> +++---
> >>>   1 file changed, 220 insertions(+), 143 deletions(-)
> >>>
> >>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> >>> b/drivers/soc/mediatek/mtk-scpsys.c
> >>> index 57e781c..5870a24 100644
> >>> --- a/drivers/soc/mediatek/mtk-scpsys.c
> >>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> >>> @@ -11,17 +11,15 @@
> >>>* GNU General Public License for more details.
> >>>*/
> >>>   #include 
> >>> -#include 
> >>> +#include 
> >>>   #include 
> >>> -#include 
> >>>   #include 
> >>> -#include 
> >>>   #include 
> >>>   #include 
> >>>   #include 
> >>> -#include 
> >>> -#include 
> >>>   #include 
> >>> +#include 
> >>> +
> >>>   #include 
> >>>
> >>>   #define SPM_VDE_PWR_CON 0x0210
> >>> @@ -34,6 +32,7 @@
> >>>   #define SPM_MFG_2D_PWR_CON  0x02c0
> >>>   #define SPM_MFG_ASYNC_PWR_CON   0x02c4
> >>>   #define SPM_USB_PWR_CON 0x02cc
> >>> +
> >>>   #define SPM_PWR_STATUS  0x060c
> >>>   #define SPM_PWR_STATUS_2ND  0x0610
> >>>
> >>> @@ -55,12 +54,12 @@
> >>>   #define PWR_STATUS_USB  BIT(25)
> >>>
> >>>   enum clk_id {
> >>> - MT8173_CLK_NONE,
> >>> - MT8173_CLK_MM,
> >>> - MT8173_CLK_MFG,
> >>> - MT8173_CLK_VENC,
> >>> - MT8173_CLK_VENC_LT,
> >>> - MT8173_CLK_MAX,
> >>> + CLK_NONE,
> >>> + CLK_MM,
> >>> + CLK_MFG,
> >>> + CLK_VENC,
> >>> + CLK_VENC_LT,
> >>> + CLK_MAX,
> >>>   };
> >>>
> >>>   #define MAX_CLKS2
> >>> @@ -76,98 +75,6 @@ struct scp_domain_data {
> >>>   bool active_wakeup;
> >>>   };
> >>>
> >>> -static const struct scp_domain_data scp_domain_data[] = {
> >>> - [MT8173_POWER_DOMAIN_VDEC] = {
> >>> - .name = "vdec",
> >>> - .sta_mask = PWR_STATUS_VDEC,
> >>> - .ctl_offs = SPM_VDE_PWR_CON,
> >>> - .sram_pdn_bits = GENMASK(11, 8),
> >>> - .sram_pdn_ack_bits = GENMASK(12, 12),
> >>> - .clk_id = {MT8173_CLK_MM},
> >>> - },
> >>> - [MT8173_POWER_DOMAIN_VENC] = {
> >>> - .name = "venc",
> >>> - .sta_mask = PWR_STATUS_VENC,
> >>> - .ctl_offs = SPM_VEN_PWR_CON,
> >>> - .sram_pdn_bits = GENMASK(11, 8),
> >>> - .sram_pdn_ack_bits = GENMASK(15, 12),
> >>> - .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
> >>> - },
> >>> - [MT8173_POWER_DOMAIN_ISP] = {
> >>> - .name = "isp",
> >>> - .sta_mask = PWR_STATUS_ISP,
> >>> - .ctl_offs = SPM_ISP_PWR_CON,
> >>> - .sram_pdn_bits = GENMASK(11, 8),
> >>> - .sram_pdn_ack_bits = GENMASK(13, 12),
> >>> - .clk_id = {MT8173_CLK_MM},
> >>> - },
> >>> - [MT8173_POWER_DOMAIN_MM] = {
> >>> - .name = "mm",
> >>> - .sta_mask = PWR_STATUS_DISP,
> >>> - .ctl_offs = SPM_DIS_PWR_CON,
> >>> - .sram_pdn_bits = GENMASK(11, 8),
> >>> - .sram_pdn_ack_bits = GENMASK(12, 12),
> >>> - .clk_id = {MT8173_CLK_MM},
> >>> - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> >>> - MT8173_TOP_AXI_PROT_EN_MM_M1,
> >>> - },
> >>> - [MT8173_POWER_DOMAIN_VENC_LT] = {
> >>> - .name = "venc_lt",
> >&

Re: [PATCH v7 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Hi Matthias,

On Thu, 2016-07-07 at 13:20 +0200, Matthias Brugger wrote:
> 
> On 06/07/16 07:39, James Liao wrote:
> > Hi Matthias,
> >
> > On Sat, 2016-07-02 at 18:33 +0200, Matthias Brugger wrote:
> >>
> >> On 05/16/2016 11:28 AM, James Liao wrote:
> >>> Refine scpsys driver common code to support multiple SoC / platform.
> >>>
> >>> Signed-off-by: James Liao 
> >>> Reviewed-by: Kevin Hilman 
> >>> ---
> >>>   drivers/soc/mediatek/mtk-scpsys.c | 363 
> >>> +++---
> >>>   1 file changed, 220 insertions(+), 143 deletions(-)
> >>>
> >>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> >>> b/drivers/soc/mediatek/mtk-scpsys.c
> >>> index 57e781c..5870a24 100644
> >>> --- a/drivers/soc/mediatek/mtk-scpsys.c
> >>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> >>> @@ -11,17 +11,15 @@
> >>>* GNU General Public License for more details.
> >>>*/
> >>>   #include 
> >>> -#include 
> >>> +#include 
> >>>   #include 
> >>> -#include 
> >>>   #include 
> >>> -#include 
> >>>   #include 
> >>>   #include 
> >>>   #include 
> >>> -#include 
> >>> -#include 
> >>>   #include 
> >>> +#include 
> >>> +
> >>>   #include 
> >>>
> >>>   #define SPM_VDE_PWR_CON 0x0210
> >>> @@ -34,6 +32,7 @@
> >>>   #define SPM_MFG_2D_PWR_CON  0x02c0
> >>>   #define SPM_MFG_ASYNC_PWR_CON   0x02c4
> >>>   #define SPM_USB_PWR_CON 0x02cc
> >>> +
> >>>   #define SPM_PWR_STATUS  0x060c
> >>>   #define SPM_PWR_STATUS_2ND  0x0610
> >>>
> >>> @@ -55,12 +54,12 @@
> >>>   #define PWR_STATUS_USB  BIT(25)
> >>>
> >>>   enum clk_id {
> >>> - MT8173_CLK_NONE,
> >>> - MT8173_CLK_MM,
> >>> - MT8173_CLK_MFG,
> >>> - MT8173_CLK_VENC,
> >>> - MT8173_CLK_VENC_LT,
> >>> - MT8173_CLK_MAX,
> >>> + CLK_NONE,
> >>> + CLK_MM,
> >>> + CLK_MFG,
> >>> + CLK_VENC,
> >>> + CLK_VENC_LT,
> >>> + CLK_MAX,
> >>>   };
> >>>
> >>>   #define MAX_CLKS2
> >>> @@ -76,98 +75,6 @@ struct scp_domain_data {
> >>>   bool active_wakeup;
> >>>   };
> >>>
> >>> -static const struct scp_domain_data scp_domain_data[] = {
> >>> - [MT8173_POWER_DOMAIN_VDEC] = {
> >>> - .name = "vdec",
> >>> - .sta_mask = PWR_STATUS_VDEC,
> >>> - .ctl_offs = SPM_VDE_PWR_CON,
> >>> - .sram_pdn_bits = GENMASK(11, 8),
> >>> - .sram_pdn_ack_bits = GENMASK(12, 12),
> >>> - .clk_id = {MT8173_CLK_MM},
> >>> - },
> >>> - [MT8173_POWER_DOMAIN_VENC] = {
> >>> - .name = "venc",
> >>> - .sta_mask = PWR_STATUS_VENC,
> >>> - .ctl_offs = SPM_VEN_PWR_CON,
> >>> - .sram_pdn_bits = GENMASK(11, 8),
> >>> - .sram_pdn_ack_bits = GENMASK(15, 12),
> >>> - .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
> >>> - },
> >>> - [MT8173_POWER_DOMAIN_ISP] = {
> >>> - .name = "isp",
> >>> - .sta_mask = PWR_STATUS_ISP,
> >>> - .ctl_offs = SPM_ISP_PWR_CON,
> >>> - .sram_pdn_bits = GENMASK(11, 8),
> >>> - .sram_pdn_ack_bits = GENMASK(13, 12),
> >>> - .clk_id = {MT8173_CLK_MM},
> >>> - },
> >>> - [MT8173_POWER_DOMAIN_MM] = {
> >>> - .name = "mm",
> >>> - .sta_mask = PWR_STATUS_DISP,
> >>> - .ctl_offs = SPM_DIS_PWR_CON,
> >>> - .sram_pdn_bits = GENMASK(11, 8),
> >>> - .sram_pdn_ack_bits = GENMASK(12, 12),
> >>> - .clk_id = {MT8173_CLK_MM},
> >>> - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> >>> - MT8173_TOP_AXI_PROT_EN_MM_M1,
> >>> - },
> >>> - [MT8173_POWER_DOMAIN_VENC_LT] = {
> >>> - .name = "venc_lt",
> >>> - .sta_mask = PWR_STATUS_VENC_LT,
> >&

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

Hi Mike,

On Fri, 2016-07-08 at 16:32 -0700, Michael Turquette wrote:
> Hi James,
> 
> Quoting James Liao (2016-07-03 20:51:48)
> > On Fri, 2016-07-01 at 18:21 -0700, Stephen Boyd wrote:
> > > (Resending to everyone)
> > > 
> > > On 06/22, Erin Lo wrote:
> > > > From: James Liao <jamesjj.l...@mediatek.com>
> > > > 
> > > > This patch fixed wrong state of parent clocks if they are registered
> > > > after critical clocks.
> > > > 
> > > > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > > > Signed-off-by: Erin Lo <erin...@mediatek.com>
> > > 
> > > It would be nice if you included the information about the
> > > problem from James' previous mail. This says what it does, but
> > > doesn't explain what the problem is and how it is fixing it.
> > > 
> > > > ---
> > > >  drivers/clk/clk.c | 9 -
> > > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > > > index d584004..e9f5f89 100644
> > > > --- a/drivers/clk/clk.c
> > > > +++ b/drivers/clk/clk.c
> > > > @@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core *core)
> > > > hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, 
> > > > child_node) {
> > > > struct clk_core *parent = __clk_init_parent(orphan);
> > > >  
> > > > -   if (parent)
> > > > +   if (parent) {
> > > > clk_core_reparent(orphan, parent);
> > > > +
> > > > +   if (orphan->prepare_count)
> > > > +   clk_core_prepare(parent);
> > > > +
> > > > +   if (orphan->enable_count)
> > > > +   clk_core_enable(parent);
> > > > +   }
> > > > }
> > > 
> > > I'm pretty sure I pointed this problem out to Mike when the
> > > critical clk patches were being pushed. I can't recall what the
> > > plan was though to fix the problem. I'm pretty sure he said that
> > > clk_core_reparent() would take care of it, but obviously it is
> > > not doing that. Or perhaps it was that clk handoff should figure
> > > out that the parents of a critical clk are also on and thus keep
> > > them on.
> > 
> > Hi Mike
> > 
> > Is there any other patch to fix this issue? Or did I misuse critical
> > clock flag?
> 
> There is no fix yes. Your fix is basically correct. I was mistaken back
> when I told you and Stephen that the framework already took care of
> this.
> 
> However, instead of "open coding" this solution, I would rather re-use
> the __clk_set_parent_{before,after} helpers instead. Can you review/test
> the following patch and let me know what you think?
> 
> Thanks,
> Mike
> 
> 
> 
> From c0163b3f719b1e219b28ad425f94f9ef54a25a8f Mon Sep 17 00:00:00 2001
> From: Michael Turquette <mturque...@baylibre.com>
> Date: Fri, 8 Jul 2016 16:05:22 -0700
> Subject: [PATCH] clk: migrate ref counts when orphans are reunited
> 
> It's always nice to see families reunited, and this is equally true when
> talking about parent clocks and their children. However, if the orphan
> clk had a positive prepare_count or enable_count, then we would not
> migrate those counts up the parent chain correctly.
> 
> This has manifested with the recent critical clocks feature, which often
> enables clocks very early, before their parents have been registered.
> 
> Fixed by replacing the call to clk_core_reparent with calls to
> __clk_set_parent_{before,after}.
> 
> Cc: James Liao <jamesjj.l...@mediatek.com>
> Cc: Erin Lo <erin...@mediatek.com>
> Signed-off-by: Michael Turquette <mturque...@baylibre.com>
> ---
>  drivers/clk/clk.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 820a939fb6bb..70efe4c4e0cc 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -2449,8 +2449,14 @@ static int __clk_core_init(struct clk_core *core)
>   hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, child_node) {
>   struct clk_core *parent = __clk_init_parent(orphan);
>  
> - if (parent)
> - clk_core_reparent(orphan, parent);

Is it correct to remove clk_core_reparent()? It lacks
__clk_recalc_accuracies() and __clk_recalc_rates(), so th

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

Hi Mike,

On Fri, 2016-07-08 at 16:32 -0700, Michael Turquette wrote:
> Hi James,
> 
> Quoting James Liao (2016-07-03 20:51:48)
> > On Fri, 2016-07-01 at 18:21 -0700, Stephen Boyd wrote:
> > > (Resending to everyone)
> > > 
> > > On 06/22, Erin Lo wrote:
> > > > From: James Liao 
> > > > 
> > > > This patch fixed wrong state of parent clocks if they are registered
> > > > after critical clocks.
> > > > 
> > > > Signed-off-by: James Liao 
> > > > Signed-off-by: Erin Lo 
> > > 
> > > It would be nice if you included the information about the
> > > problem from James' previous mail. This says what it does, but
> > > doesn't explain what the problem is and how it is fixing it.
> > > 
> > > > ---
> > > >  drivers/clk/clk.c | 9 -
> > > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > > > index d584004..e9f5f89 100644
> > > > --- a/drivers/clk/clk.c
> > > > +++ b/drivers/clk/clk.c
> > > > @@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core *core)
> > > > hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, 
> > > > child_node) {
> > > > struct clk_core *parent = __clk_init_parent(orphan);
> > > >  
> > > > -   if (parent)
> > > > +   if (parent) {
> > > > clk_core_reparent(orphan, parent);
> > > > +
> > > > +   if (orphan->prepare_count)
> > > > +   clk_core_prepare(parent);
> > > > +
> > > > +   if (orphan->enable_count)
> > > > +   clk_core_enable(parent);
> > > > +   }
> > > > }
> > > 
> > > I'm pretty sure I pointed this problem out to Mike when the
> > > critical clk patches were being pushed. I can't recall what the
> > > plan was though to fix the problem. I'm pretty sure he said that
> > > clk_core_reparent() would take care of it, but obviously it is
> > > not doing that. Or perhaps it was that clk handoff should figure
> > > out that the parents of a critical clk are also on and thus keep
> > > them on.
> > 
> > Hi Mike
> > 
> > Is there any other patch to fix this issue? Or did I misuse critical
> > clock flag?
> 
> There is no fix yes. Your fix is basically correct. I was mistaken back
> when I told you and Stephen that the framework already took care of
> this.
> 
> However, instead of "open coding" this solution, I would rather re-use
> the __clk_set_parent_{before,after} helpers instead. Can you review/test
> the following patch and let me know what you think?
> 
> Thanks,
> Mike
> 
> 
> 
> From c0163b3f719b1e219b28ad425f94f9ef54a25a8f Mon Sep 17 00:00:00 2001
> From: Michael Turquette 
> Date: Fri, 8 Jul 2016 16:05:22 -0700
> Subject: [PATCH] clk: migrate ref counts when orphans are reunited
> 
> It's always nice to see families reunited, and this is equally true when
> talking about parent clocks and their children. However, if the orphan
> clk had a positive prepare_count or enable_count, then we would not
> migrate those counts up the parent chain correctly.
> 
> This has manifested with the recent critical clocks feature, which often
> enables clocks very early, before their parents have been registered.
> 
> Fixed by replacing the call to clk_core_reparent with calls to
> __clk_set_parent_{before,after}.
> 
> Cc: James Liao 
> Cc: Erin Lo 
> Signed-off-by: Michael Turquette 
> ---
>  drivers/clk/clk.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 820a939fb6bb..70efe4c4e0cc 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -2449,8 +2449,14 @@ static int __clk_core_init(struct clk_core *core)
>   hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, child_node) {
>   struct clk_core *parent = __clk_init_parent(orphan);
>  
> - if (parent)
> - clk_core_reparent(orphan, parent);

Is it correct to remove clk_core_reparent()? It lacks
__clk_recalc_accuracies() and __clk_recalc_rates(), so the new parent's
rate will not propagate correctly.

For example, I set vdec_sel as a critical clock. Without your patch, the
result was:

vdecpll 00   33800
   vdecpll_ck   11   33800
  vdec_sel  11   33800

With your patch, it became:

vdecpll 11   33800
   vdecpll_ck   11   0
  vdec_sel  11   0

The prepare_count and enable_count are correct with your patch, but the
rates of vdecpll_ck and vdec_sel become incorrect.


Best regards,

James

> + /*
> +  * we could call __clk_set_parent, but that would result in a
> +  * reducant call to the .set_rate op, if it exists
> +  */
> + if (parent) {
> + __clk_set_parent_before(orphan, parent);
> + __clk_set_parent_after(orphan, parent, NULL);
> + }
>   }
>  
>   /*

Re: [PATCH v7 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Hi Matthias,

On Sat, 2016-07-02 at 18:33 +0200, Matthias Brugger wrote:
> 
> On 05/16/2016 11:28 AM, James Liao wrote:
> > Refine scpsys driver common code to support multiple SoC / platform.
> >
> > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > Reviewed-by: Kevin Hilman <khil...@baylibre.com>
> > ---
> >  drivers/soc/mediatek/mtk-scpsys.c | 363 
> > +++---
> >  1 file changed, 220 insertions(+), 143 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index 57e781c..5870a24 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -11,17 +11,15 @@
> >   * GNU General Public License for more details.
> >   */
> >  #include 
> > -#include 
> > +#include 
> >  #include 
> > -#include 
> >  #include 
> > -#include 
> >  #include 
> >  #include 
> >  #include 
> > -#include 
> > -#include 
> >  #include 
> > +#include 
> > +
> >  #include 
> >
> >  #define SPM_VDE_PWR_CON0x0210
> > @@ -34,6 +32,7 @@
> >  #define SPM_MFG_2D_PWR_CON 0x02c0
> >  #define SPM_MFG_ASYNC_PWR_CON  0x02c4
> >  #define SPM_USB_PWR_CON0x02cc
> > +
> >  #define SPM_PWR_STATUS 0x060c
> >  #define SPM_PWR_STATUS_2ND 0x0610
> >
> > @@ -55,12 +54,12 @@
> >  #define PWR_STATUS_USB BIT(25)
> >
> >  enum clk_id {
> > -   MT8173_CLK_NONE,
> > -   MT8173_CLK_MM,
> > -   MT8173_CLK_MFG,
> > -   MT8173_CLK_VENC,
> > -   MT8173_CLK_VENC_LT,
> > -   MT8173_CLK_MAX,
> > +   CLK_NONE,
> > +   CLK_MM,
> > +   CLK_MFG,
> > +   CLK_VENC,
> > +   CLK_VENC_LT,
> > +   CLK_MAX,
> >  };
> >
> >  #define MAX_CLKS   2
> > @@ -76,98 +75,6 @@ struct scp_domain_data {
> > bool active_wakeup;
> >  };
> >
> > -static const struct scp_domain_data scp_domain_data[] = {
> > -   [MT8173_POWER_DOMAIN_VDEC] = {
> > -   .name = "vdec",
> > -   .sta_mask = PWR_STATUS_VDEC,
> > -   .ctl_offs = SPM_VDE_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(12, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   },
> > -   [MT8173_POWER_DOMAIN_VENC] = {
> > -   .name = "venc",
> > -   .sta_mask = PWR_STATUS_VENC,
> > -   .ctl_offs = SPM_VEN_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
> > -   },
> > -   [MT8173_POWER_DOMAIN_ISP] = {
> > -   .name = "isp",
> > -   .sta_mask = PWR_STATUS_ISP,
> > -   .ctl_offs = SPM_ISP_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(13, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   },
> > -   [MT8173_POWER_DOMAIN_MM] = {
> > -   .name = "mm",
> > -   .sta_mask = PWR_STATUS_DISP,
> > -   .ctl_offs = SPM_DIS_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(12, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> > -   MT8173_TOP_AXI_PROT_EN_MM_M1,
> > -   },
> > -   [MT8173_POWER_DOMAIN_VENC_LT] = {
> > -   .name = "venc_lt",
> > -   .sta_mask = PWR_STATUS_VENC_LT,
> > -   .ctl_offs = SPM_VEN2_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
> > -   },
> > -   [MT8173_POWER_DOMAIN_AUDIO] = {
> > -   .name = "audio",
> > -   .sta_mask = PWR_STATUS_AUDIO,
> > -   .ctl_offs = SPM_AUDIO_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_NONE},
> > -   },
> > -   [MT8173_POWER_DOMAIN_USB] = {
> > -   .name = "usb",
> > -   .sta_mask = PWR_STATUS_USB,
> > -   .ctl_offs = SPM_USB_PWR_CON,
> > -   .sr

Re: [PATCH v7 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Hi Matthias,

On Sat, 2016-07-02 at 18:33 +0200, Matthias Brugger wrote:
> 
> On 05/16/2016 11:28 AM, James Liao wrote:
> > Refine scpsys driver common code to support multiple SoC / platform.
> >
> > Signed-off-by: James Liao 
> > Reviewed-by: Kevin Hilman 
> > ---
> >  drivers/soc/mediatek/mtk-scpsys.c | 363 
> > +++---
> >  1 file changed, 220 insertions(+), 143 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index 57e781c..5870a24 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -11,17 +11,15 @@
> >   * GNU General Public License for more details.
> >   */
> >  #include 
> > -#include 
> > +#include 
> >  #include 
> > -#include 
> >  #include 
> > -#include 
> >  #include 
> >  #include 
> >  #include 
> > -#include 
> > -#include 
> >  #include 
> > +#include 
> > +
> >  #include 
> >
> >  #define SPM_VDE_PWR_CON0x0210
> > @@ -34,6 +32,7 @@
> >  #define SPM_MFG_2D_PWR_CON 0x02c0
> >  #define SPM_MFG_ASYNC_PWR_CON  0x02c4
> >  #define SPM_USB_PWR_CON0x02cc
> > +
> >  #define SPM_PWR_STATUS 0x060c
> >  #define SPM_PWR_STATUS_2ND 0x0610
> >
> > @@ -55,12 +54,12 @@
> >  #define PWR_STATUS_USB BIT(25)
> >
> >  enum clk_id {
> > -   MT8173_CLK_NONE,
> > -   MT8173_CLK_MM,
> > -   MT8173_CLK_MFG,
> > -   MT8173_CLK_VENC,
> > -   MT8173_CLK_VENC_LT,
> > -   MT8173_CLK_MAX,
> > +   CLK_NONE,
> > +   CLK_MM,
> > +   CLK_MFG,
> > +   CLK_VENC,
> > +   CLK_VENC_LT,
> > +   CLK_MAX,
> >  };
> >
> >  #define MAX_CLKS   2
> > @@ -76,98 +75,6 @@ struct scp_domain_data {
> > bool active_wakeup;
> >  };
> >
> > -static const struct scp_domain_data scp_domain_data[] = {
> > -   [MT8173_POWER_DOMAIN_VDEC] = {
> > -   .name = "vdec",
> > -   .sta_mask = PWR_STATUS_VDEC,
> > -   .ctl_offs = SPM_VDE_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(12, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   },
> > -   [MT8173_POWER_DOMAIN_VENC] = {
> > -   .name = "venc",
> > -   .sta_mask = PWR_STATUS_VENC,
> > -   .ctl_offs = SPM_VEN_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
> > -   },
> > -   [MT8173_POWER_DOMAIN_ISP] = {
> > -   .name = "isp",
> > -   .sta_mask = PWR_STATUS_ISP,
> > -   .ctl_offs = SPM_ISP_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(13, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   },
> > -   [MT8173_POWER_DOMAIN_MM] = {
> > -   .name = "mm",
> > -   .sta_mask = PWR_STATUS_DISP,
> > -   .ctl_offs = SPM_DIS_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(12, 12),
> > -   .clk_id = {MT8173_CLK_MM},
> > -   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> > -   MT8173_TOP_AXI_PROT_EN_MM_M1,
> > -   },
> > -   [MT8173_POWER_DOMAIN_VENC_LT] = {
> > -   .name = "venc_lt",
> > -   .sta_mask = PWR_STATUS_VENC_LT,
> > -   .ctl_offs = SPM_VEN2_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
> > -   },
> > -   [MT8173_POWER_DOMAIN_AUDIO] = {
> > -   .name = "audio",
> > -   .sta_mask = PWR_STATUS_AUDIO,
> > -   .ctl_offs = SPM_AUDIO_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
> > -   .clk_id = {MT8173_CLK_NONE},
> > -   },
> > -   [MT8173_POWER_DOMAIN_USB] = {
> > -   .name = "usb",
> > -   .sta_mask = PWR_STATUS_USB,
> > -   .ctl_offs = SPM_USB_PWR_CON,
> > -   .sram_pdn_bits = GENMASK(11, 8),
> > -   .sram_pdn_ack_bits = GENMASK(15, 12),
&g

Re: [PATCH v7 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

On Sat, 2016-07-02 at 18:35 +0200, Matthias Brugger wrote:
> 
> On 05/16/2016 11:28 AM, James Liao wrote:
> > Some power domain comsumers may init before module_init.
> > So the power domain provider (scpsys) need to be initialized
> > earlier too.
> >
> > Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
> > between IOMMU and multimedia HW. SMI is responsible to
> > enable/disable iommu and help transfer data for each multimedia
> > HW. Both of them have to wait until the power and clocks are
> > enabled.
> >
> > So scpsys driver should be initialized before SMI, and SMI should
> > be initialized before IOMMU, and then init IOMMU consumers
> > (display/vdec/venc/camera etc.).
> >
> > IOMMU is subsys_init by default. So we need to init scpsys driver
> > before subsys_init.
> >
> > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > Reviewed-by: Kevin Hilman <khil...@baylibre.com>
> > ---
> >  drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
> >  1 file changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index 5870a24..00c0adb 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -617,4 +617,21 @@ static struct platform_driver scpsys_drv = {
> > .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> > },
> >  };
> > -builtin_platform_driver(scpsys_drv);
> > +
> > +static int __init scpsys_drv_init(void)
> > +{
> > +   return platform_driver_register(_drv);
> > +}
> > +
> > +/*
> > + * There are some Mediatek drivers which depend on the power domain driver 
> > need
> > + * to probe in earlier initcall levels. So scpsys driver also need to probe
> > + * earlier.
> > + *
> > + * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU 
> > and
> > + * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
> > + * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
> > + * IOMMU drivers are initialized during subsys_init by default, so we need 
> > to
> > + * move SMI and scpsys drivers to subsys_init or earlier init levels.
> > + */
> > +subsys_initcall(scpsys_drv_init);
> >
> 
> Can't we achieve this with probe deferring? I'm not really keen on 
> coding the order of the different drivers like this.

Hi Matthias,

Some drivers such as IOMMU don't support probe deferring. So scpsys need
to init before them by changing init level.


Best regards,

James

Re: [PATCH v7 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

On Sat, 2016-07-02 at 18:35 +0200, Matthias Brugger wrote:
> 
> On 05/16/2016 11:28 AM, James Liao wrote:
> > Some power domain comsumers may init before module_init.
> > So the power domain provider (scpsys) need to be initialized
> > earlier too.
> >
> > Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
> > between IOMMU and multimedia HW. SMI is responsible to
> > enable/disable iommu and help transfer data for each multimedia
> > HW. Both of them have to wait until the power and clocks are
> > enabled.
> >
> > So scpsys driver should be initialized before SMI, and SMI should
> > be initialized before IOMMU, and then init IOMMU consumers
> > (display/vdec/venc/camera etc.).
> >
> > IOMMU is subsys_init by default. So we need to init scpsys driver
> > before subsys_init.
> >
> > Signed-off-by: James Liao 
> > Reviewed-by: Kevin Hilman 
> > ---
> >  drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
> >  1 file changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index 5870a24..00c0adb 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -617,4 +617,21 @@ static struct platform_driver scpsys_drv = {
> > .of_match_table = of_match_ptr(of_scpsys_match_tbl),
> > },
> >  };
> > -builtin_platform_driver(scpsys_drv);
> > +
> > +static int __init scpsys_drv_init(void)
> > +{
> > +   return platform_driver_register(_drv);
> > +}
> > +
> > +/*
> > + * There are some Mediatek drivers which depend on the power domain driver 
> > need
> > + * to probe in earlier initcall levels. So scpsys driver also need to probe
> > + * earlier.
> > + *
> > + * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU 
> > and
> > + * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
> > + * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
> > + * IOMMU drivers are initialized during subsys_init by default, so we need 
> > to
> > + * move SMI and scpsys drivers to subsys_init or earlier init levels.
> > + */
> > +subsys_initcall(scpsys_drv_init);
> >
> 
> Can't we achieve this with probe deferring? I'm not really keen on 
> coding the order of the different drivers like this.

Hi Matthias,

Some drivers such as IOMMU don't support probe deferring. So scpsys need
to init before them by changing init level.


Best regards,

James

Re: [PATCH v7 4/4] soc: mediatek: Add MT2701 scpsys driver

[James Liao]

On Sat, 2016-07-02 at 18:41 +0200, Matthias Brugger wrote:
> 
> On 05/16/2016 11:28 AM, James Liao wrote:
> > From: Shunli Wang <shunli.w...@mediatek.com>
> >
> > Add scpsys driver for MT2701.
> >
> > mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
> > be enabled on both arm64 and arm platforms.
> >
> > Signed-off-by: Shunli Wang <shunli.w...@mediatek.com>
> > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > Reviewed-by: Kevin Hilman <khil...@baylibre.com>
> > ---
> >  drivers/soc/mediatek/Kconfig  |   2 +-
> >  drivers/soc/mediatek/mtk-scpsys.c | 117 
> > +-
> >  2 files changed, 116 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index 0a4ea80..609bb34 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
> >  config MTK_SCPSYS
> > bool "MediaTek SCPSYS Support"
> > depends on ARCH_MEDIATEK || COMPILE_TEST
> > -   default ARM64 && ARCH_MEDIATEK
> > +   default ARCH_MEDIATEK
> > select REGMAP
> > select MTK_INFRACFG
> > select PM_GENERIC_DOMAINS if PM
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index 00c0adb..f4d1230 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -20,6 +20,7 @@
> >  #include 
> >  #include 
> >
> > +#include 
> >  #include 
> >
> >  #define SPM_VDE_PWR_CON0x0210
> > @@ -27,8 +28,13 @@
> >  #define SPM_VEN_PWR_CON0x0230
> >  #define SPM_ISP_PWR_CON0x0238
> >  #define SPM_DIS_PWR_CON0x023c
> > +#define SPM_CONN_PWR_CON   0x0280
> >  #define SPM_VEN2_PWR_CON   0x0298
> > -#define SPM_AUDIO_PWR_CON  0x029c
> > +#define SPM_AUDIO_PWR_CON  0x029c  /* MT8173 */
> > +#define SPM_BDP_PWR_CON0x029c  /* MT2701 */
> > +#define SPM_ETH_PWR_CON0x02a0
> > +#define SPM_HIF_PWR_CON0x02a4
> > +#define SPM_IFR_MSC_PWR_CON0x02a8
> >  #define SPM_MFG_2D_PWR_CON 0x02c0
> >  #define SPM_MFG_ASYNC_PWR_CON  0x02c4
> >  #define SPM_USB_PWR_CON0x02cc
> > @@ -42,10 +48,15 @@
> >  #define PWR_ON_2ND_BIT BIT(3)
> >  #define PWR_CLK_DIS_BITBIT(4)
> >
> > +#define PWR_STATUS_CONNBIT(1)
> >  #define PWR_STATUS_DISPBIT(3)
> >  #define PWR_STATUS_MFG BIT(4)
> >  #define PWR_STATUS_ISP BIT(5)
> >  #define PWR_STATUS_VDECBIT(7)
> > +#define PWR_STATUS_BDP BIT(14)
> > +#define PWR_STATUS_ETH BIT(15)
> > +#define PWR_STATUS_HIF BIT(16)
> > +#define PWR_STATUS_IFR_MSC BIT(17)
> >  #define PWR_STATUS_VENC_LT BIT(20)
> >  #define PWR_STATUS_VENCBIT(21)
> >  #define PWR_STATUS_MFG_2D  BIT(22)
> > @@ -59,6 +70,7 @@ enum clk_id {
> > CLK_MFG,
> > CLK_VENC,
> > CLK_VENC_LT,
> > +   CLK_ETHIF,
> > CLK_MAX,
> >  };
> >
> > @@ -321,7 +333,8 @@ static void init_clks(struct platform_device *pdev, 
> > struct clk *clk[CLK_MAX])
> > CLK_MM,
> > CLK_MFG,
> > CLK_VENC,
> > -   CLK_VENC_LT
> > +   CLK_VENC_LT,
> > +   CLK_ETHIF
> > };
> >
> > static const char * const clk_names[] = {
> > @@ -329,6 +342,7 @@ static void init_clks(struct platform_device *pdev, 
> > struct clk *clk[CLK_MAX])
> > "mfg",
> > "venc",
> > "venc_lt",
> > +   "ethif",
> > };
> >
> > int i;
> > @@ -459,6 +473,102 @@ static void mtk_register_power_domains(struct 
> > platform_device *pdev,
> >  }
> >
> >  /*
> > + * MT2701 power domain support
> > + */
> > +
> > +static const struct scp_domain_data scp_domain_data_mt2701[] = {
> > +   [MT2701_POWER_DOMAIN_CONN] = {
> > +   .name = "conn",
> > +   .sta_mask = PWR_STATUS_CONN,
> > +   .

Re: [PATCH v7 4/4] soc: mediatek: Add MT2701 scpsys driver

[James Liao]

On Sat, 2016-07-02 at 18:41 +0200, Matthias Brugger wrote:
> 
> On 05/16/2016 11:28 AM, James Liao wrote:
> > From: Shunli Wang 
> >
> > Add scpsys driver for MT2701.
> >
> > mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
> > be enabled on both arm64 and arm platforms.
> >
> > Signed-off-by: Shunli Wang 
> > Signed-off-by: James Liao 
> > Reviewed-by: Kevin Hilman 
> > ---
> >  drivers/soc/mediatek/Kconfig  |   2 +-
> >  drivers/soc/mediatek/mtk-scpsys.c | 117 
> > +-
> >  2 files changed, 116 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index 0a4ea80..609bb34 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
> >  config MTK_SCPSYS
> > bool "MediaTek SCPSYS Support"
> > depends on ARCH_MEDIATEK || COMPILE_TEST
> > -   default ARM64 && ARCH_MEDIATEK
> > +   default ARCH_MEDIATEK
> > select REGMAP
> > select MTK_INFRACFG
> > select PM_GENERIC_DOMAINS if PM
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index 00c0adb..f4d1230 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -20,6 +20,7 @@
> >  #include 
> >  #include 
> >
> > +#include 
> >  #include 
> >
> >  #define SPM_VDE_PWR_CON0x0210
> > @@ -27,8 +28,13 @@
> >  #define SPM_VEN_PWR_CON0x0230
> >  #define SPM_ISP_PWR_CON0x0238
> >  #define SPM_DIS_PWR_CON0x023c
> > +#define SPM_CONN_PWR_CON   0x0280
> >  #define SPM_VEN2_PWR_CON   0x0298
> > -#define SPM_AUDIO_PWR_CON  0x029c
> > +#define SPM_AUDIO_PWR_CON  0x029c  /* MT8173 */
> > +#define SPM_BDP_PWR_CON0x029c  /* MT2701 */
> > +#define SPM_ETH_PWR_CON0x02a0
> > +#define SPM_HIF_PWR_CON0x02a4
> > +#define SPM_IFR_MSC_PWR_CON0x02a8
> >  #define SPM_MFG_2D_PWR_CON 0x02c0
> >  #define SPM_MFG_ASYNC_PWR_CON  0x02c4
> >  #define SPM_USB_PWR_CON0x02cc
> > @@ -42,10 +48,15 @@
> >  #define PWR_ON_2ND_BIT BIT(3)
> >  #define PWR_CLK_DIS_BITBIT(4)
> >
> > +#define PWR_STATUS_CONNBIT(1)
> >  #define PWR_STATUS_DISPBIT(3)
> >  #define PWR_STATUS_MFG BIT(4)
> >  #define PWR_STATUS_ISP BIT(5)
> >  #define PWR_STATUS_VDECBIT(7)
> > +#define PWR_STATUS_BDP BIT(14)
> > +#define PWR_STATUS_ETH BIT(15)
> > +#define PWR_STATUS_HIF BIT(16)
> > +#define PWR_STATUS_IFR_MSC BIT(17)
> >  #define PWR_STATUS_VENC_LT BIT(20)
> >  #define PWR_STATUS_VENCBIT(21)
> >  #define PWR_STATUS_MFG_2D  BIT(22)
> > @@ -59,6 +70,7 @@ enum clk_id {
> > CLK_MFG,
> > CLK_VENC,
> > CLK_VENC_LT,
> > +   CLK_ETHIF,
> > CLK_MAX,
> >  };
> >
> > @@ -321,7 +333,8 @@ static void init_clks(struct platform_device *pdev, 
> > struct clk *clk[CLK_MAX])
> > CLK_MM,
> > CLK_MFG,
> > CLK_VENC,
> > -   CLK_VENC_LT
> > +   CLK_VENC_LT,
> > +   CLK_ETHIF
> > };
> >
> > static const char * const clk_names[] = {
> > @@ -329,6 +342,7 @@ static void init_clks(struct platform_device *pdev, 
> > struct clk *clk[CLK_MAX])
> > "mfg",
> > "venc",
> > "venc_lt",
> > +   "ethif",
> > };
> >
> > int i;
> > @@ -459,6 +473,102 @@ static void mtk_register_power_domains(struct 
> > platform_device *pdev,
> >  }
> >
> >  /*
> > + * MT2701 power domain support
> > + */
> > +
> > +static const struct scp_domain_data scp_domain_data_mt2701[] = {
> > +   [MT2701_POWER_DOMAIN_CONN] = {
> > +   .name = "conn",
> > +   .sta_mask = PWR_STATUS_CONN,
> > +   .ctl_offs = SPM_CONN_PWR_CON,
> > +   .bus_prot_mask = 0x0104,
> > +   .active_wakeup = true,
> 
> .clk_

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

On Fri, 2016-07-01 at 18:21 -0700, Stephen Boyd wrote:
> (Resending to everyone)
> 
> On 06/22, Erin Lo wrote:
> > From: James Liao <jamesjj.l...@mediatek.com>
> > 
> > This patch fixed wrong state of parent clocks if they are registered
> > after critical clocks.
> > 
> > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > Signed-off-by: Erin Lo <erin...@mediatek.com>
> 
> It would be nice if you included the information about the
> problem from James' previous mail. This says what it does, but
> doesn't explain what the problem is and how it is fixing it.
> 
> > ---
> >  drivers/clk/clk.c | 9 -
> >  1 file changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index d584004..e9f5f89 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core *core)
> > hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, child_node) {
> > struct clk_core *parent = __clk_init_parent(orphan);
> >  
> > -   if (parent)
> > +   if (parent) {
> > clk_core_reparent(orphan, parent);
> > +
> > +   if (orphan->prepare_count)
> > +   clk_core_prepare(parent);
> > +
> > +   if (orphan->enable_count)
> > +   clk_core_enable(parent);
> > +   }
> > }
> 
> I'm pretty sure I pointed this problem out to Mike when the
> critical clk patches were being pushed. I can't recall what the
> plan was though to fix the problem. I'm pretty sure he said that
> clk_core_reparent() would take care of it, but obviously it is
> not doing that. Or perhaps it was that clk handoff should figure
> out that the parents of a critical clk are also on and thus keep
> them on.

Hi Mike

Is there any other patch to fix this issue? Or did I misuse critical
clock flag?


Best regards,

James

Re: [PATCH v9 01/10] clk: fix initial state of critical clock's parents

[James Liao]

On Fri, 2016-07-01 at 18:21 -0700, Stephen Boyd wrote:
> (Resending to everyone)
> 
> On 06/22, Erin Lo wrote:
> > From: James Liao 
> > 
> > This patch fixed wrong state of parent clocks if they are registered
> > after critical clocks.
> > 
> > Signed-off-by: James Liao 
> > Signed-off-by: Erin Lo 
> 
> It would be nice if you included the information about the
> problem from James' previous mail. This says what it does, but
> doesn't explain what the problem is and how it is fixing it.
> 
> > ---
> >  drivers/clk/clk.c | 9 -
> >  1 file changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index d584004..e9f5f89 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core *core)
> > hlist_for_each_entry_safe(orphan, tmp2, _orphan_list, child_node) {
> > struct clk_core *parent = __clk_init_parent(orphan);
> >  
> > -   if (parent)
> > +   if (parent) {
> > clk_core_reparent(orphan, parent);
> > +
> > +   if (orphan->prepare_count)
> > +   clk_core_prepare(parent);
> > +
> > +   if (orphan->enable_count)
> > +   clk_core_enable(parent);
> > +   }
> > }
> 
> I'm pretty sure I pointed this problem out to Mike when the
> critical clk patches were being pushed. I can't recall what the
> plan was though to fix the problem. I'm pretty sure he said that
> clk_core_reparent() would take care of it, but obviously it is
> not doing that. Or perhaps it was that clk handoff should figure
> out that the parents of a critical clk are also on and thus keep
> them on.

Hi Mike

Is there any other patch to fix this issue? Or did I misuse critical
clock flag?


Best regards,

James

[PATCH v7 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

Some power domain comsumers may init before module_init.
So the power domain provider (scpsys) need to be initialized
earlier too.

Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
between IOMMU and multimedia HW. SMI is responsible to
enable/disable iommu and help transfer data for each multimedia
HW. Both of them have to wait until the power and clocks are
enabled.

So scpsys driver should be initialized before SMI, and SMI should
be initialized before IOMMU, and then init IOMMU consumers
(display/vdec/venc/camera etc.).

IOMMU is subsys_init by default. So we need to init scpsys driver
before subsys_init.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 5870a24..00c0adb 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -617,4 +617,21 @@ static struct platform_driver scpsys_drv = {
.of_match_table = of_match_ptr(of_scpsys_match_tbl),
},
 };
-builtin_platform_driver(scpsys_drv);
+
+static int __init scpsys_drv_init(void)
+{
+   return platform_driver_register(_drv);
+}
+
+/*
+ * There are some Mediatek drivers which depend on the power domain driver need
+ * to probe in earlier initcall levels. So scpsys driver also need to probe
+ * earlier.
+ *
+ * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU and
+ * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
+ * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
+ * IOMMU drivers are initialized during subsys_init by default, so we need to
+ * move SMI and scpsys drivers to subsys_init or earlier init levels.
+ */
+subsys_initcall(scpsys_drv_init);
-- 
1.9.1

[PATCH v7 2/4] soc: mediatek: Init MT8173 scpsys driver earlier

[James Liao]

Some power domain comsumers may init before module_init.
So the power domain provider (scpsys) need to be initialized
earlier too.

Take an example for our IOMMU (M4U) and SMI. SMI is a bridge
between IOMMU and multimedia HW. SMI is responsible to
enable/disable iommu and help transfer data for each multimedia
HW. Both of them have to wait until the power and clocks are
enabled.

So scpsys driver should be initialized before SMI, and SMI should
be initialized before IOMMU, and then init IOMMU consumers
(display/vdec/venc/camera etc.).

IOMMU is subsys_init by default. So we need to init scpsys driver
before subsys_init.

Signed-off-by: James Liao 
Reviewed-by: Kevin Hilman 
---
 drivers/soc/mediatek/mtk-scpsys.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 5870a24..00c0adb 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -617,4 +617,21 @@ static struct platform_driver scpsys_drv = {
.of_match_table = of_match_ptr(of_scpsys_match_tbl),
},
 };
-builtin_platform_driver(scpsys_drv);
+
+static int __init scpsys_drv_init(void)
+{
+   return platform_driver_register(_drv);
+}
+
+/*
+ * There are some Mediatek drivers which depend on the power domain driver need
+ * to probe in earlier initcall levels. So scpsys driver also need to probe
+ * earlier.
+ *
+ * IOMMU(M4U) and SMI drivers for example. SMI is a bridge between IOMMU and
+ * multimedia HW. IOMMU depends on SMI, and SMI is a power domain consumer,
+ * so the proper probe sequence should be scpsys -> SMI -> IOMMU driver.
+ * IOMMU drivers are initialized during subsys_init by default, so we need to
+ * move SMI and scpsys drivers to subsys_init or earlier init levels.
+ */
+subsys_initcall(scpsys_drv_init);
-- 
1.9.1

[PATCH v7 4/4] soc: mediatek: Add MT2701 scpsys driver

[James Liao]

From: Shunli Wang <shunli.w...@mediatek.com>

Add scpsys driver for MT2701.

mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
be enabled on both arm64 and arm platforms.

Signed-off-by: Shunli Wang <shunli.w...@mediatek.com>
Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 drivers/soc/mediatek/Kconfig  |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c | 117 +-
 2 files changed, 116 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 0a4ea80..609bb34 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
 config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
-   default ARM64 && ARCH_MEDIATEK
+   default ARCH_MEDIATEK
select REGMAP
select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 00c0adb..f4d1230 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -27,8 +28,13 @@
 #define SPM_VEN_PWR_CON0x0230
 #define SPM_ISP_PWR_CON0x0238
 #define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON   0x0280
 #define SPM_VEN2_PWR_CON   0x0298
-#define SPM_AUDIO_PWR_CON  0x029c
+#define SPM_AUDIO_PWR_CON  0x029c  /* MT8173 */
+#define SPM_BDP_PWR_CON0x029c  /* MT2701 */
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
@@ -42,10 +48,15 @@
 #define PWR_ON_2ND_BIT BIT(3)
 #define PWR_CLK_DIS_BITBIT(4)
 
+#define PWR_STATUS_CONNBIT(1)
 #define PWR_STATUS_DISPBIT(3)
 #define PWR_STATUS_MFG BIT(4)
 #define PWR_STATUS_ISP BIT(5)
 #define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
 #define PWR_STATUS_VENC_LT BIT(20)
 #define PWR_STATUS_VENCBIT(21)
 #define PWR_STATUS_MFG_2D  BIT(22)
@@ -59,6 +70,7 @@ enum clk_id {
CLK_MFG,
CLK_VENC,
CLK_VENC_LT,
+   CLK_ETHIF,
CLK_MAX,
 };
 
@@ -321,7 +333,8 @@ static void init_clks(struct platform_device *pdev, struct 
clk *clk[CLK_MAX])
CLK_MM,
CLK_MFG,
CLK_VENC,
-   CLK_VENC_LT
+   CLK_VENC_LT,
+   CLK_ETHIF
};
 
static const char * const clk_names[] = {
@@ -329,6 +342,7 @@ static void init_clks(struct platform_device *pdev, struct 
clk *clk[CLK_MAX])
"mfg",
"venc",
"venc_lt",
+   "ethif",
};
 
int i;
@@ -459,6 +473,102 @@ static void mtk_register_power_domains(struct 
platform_device *pdev,
 }
 
 /*
+ * MT2701 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt2701[] = {
+   [MT2701_POWER_DOMAIN_CONN] = {
+   .name = "conn",
+   .sta_mask = PWR_STATUS_CONN,
+   .ctl_offs = SPM_CONN_PWR_CON,
+   .bus_prot_mask = 0x0104,
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_DISP] = {
+   .name = "disp",
+   .sta_mask = PWR_STATUS_DISP,
+   .ctl_offs = SPM_DIS_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .clk_id = {CLK_MM},
+   .bus_prot_mask = 0x0002,
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_MFG] = {
+   .name = "mfg",
+   .sta_mask = PWR_STATUS_MFG,
+   .ctl_offs = SPM_MFG_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MFG},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_VDEC] = {
+   .name = "vdec",
+   .sta_mask = PWR_STATUS_VDEC,
+   .ctl_offs = SPM_VDE_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+

[PATCH v7 0/4] Mediatek MT2701 SCPSYS power domain support

[James Liao]

This series is based on v4.6-rc1 and adds scpsys power domain support
for Mediatek MT2701.

To share the code between MT2701 and MT8173, this patchset also refined
original mtk-scpsys.c to separate common codes and platform codes, so
that mtk-scpsys.c can support new SoCs more easily.

MT8173 and MT2701 scpsys init level are now subsys_init. Please refer to [1]
to see discussion details.

changes since v6:
- Minor changes in the dt-binding document.

changes since v5:
- Rebase to v4.6-rc1.
- Add dependent clocks for MFG, ISP, ETH and HIF power domains.
- Add "ethif" as a dependent clock in scpsys dt-binding document.

changes since v4:
- Rebase to v4.5-rc4.
- Remove mtk-scpsys.h and Merge its code into mtk-scpsys.c.
- Add names for every controlling registers and bits.
- Include dt-bindings headers at the beginning of mtk-scpsys.c.
- Sort compatible string in dt-binding documents.

changes since v3:
- Implement MT8173 and MT2701 scpsys drivers in a signle file.
- Remove naming of registers that can't be shared among SoCs.

changes since v2:
- Rebase to mbgg/linux-mediatek v4.4-next/soc [1].
- Remove MTK_SCPSYS_MT8173 and MTK_SCPSYS_MT2701.
- Modify scpsys dt-binding document to support MT2701.

changes since v1:
- Make MTK_SCPSYS in Kconfig invisible from users.
- Add comments for changing scpsys init level to subsys_init.

[1] 
http://lists.infradead.org/pipermail/linux-mediatek/2015-December/003416.html

James Liao (2):
  soc: mediatek: Refine scpsys to support multiple platform
  soc: mediatek: Init MT8173 scpsys driver earlier

Shunli Wang (2):
  soc: mediatek: Add MT2701 power dt-bindings
  soc: mediatek: Add MT2701 scpsys driver

 .../devicetree/bindings/soc/mediatek/scpsys.txt|  13 +-
 drivers/soc/mediatek/Kconfig   |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c  | 497 +++--
 include/dt-bindings/power/mt2701-power.h   |  27 ++
 4 files changed, 388 insertions(+), 151 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

--
1.9.1

[PATCH v7 4/4] soc: mediatek: Add MT2701 scpsys driver

[James Liao]

From: Shunli Wang 

Add scpsys driver for MT2701.

mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
be enabled on both arm64 and arm platforms.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Reviewed-by: Kevin Hilman 
---
 drivers/soc/mediatek/Kconfig  |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c | 117 +-
 2 files changed, 116 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 0a4ea80..609bb34 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
 config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
-   default ARM64 && ARCH_MEDIATEK
+   default ARCH_MEDIATEK
select REGMAP
select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 00c0adb..f4d1230 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -27,8 +28,13 @@
 #define SPM_VEN_PWR_CON0x0230
 #define SPM_ISP_PWR_CON0x0238
 #define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON   0x0280
 #define SPM_VEN2_PWR_CON   0x0298
-#define SPM_AUDIO_PWR_CON  0x029c
+#define SPM_AUDIO_PWR_CON  0x029c  /* MT8173 */
+#define SPM_BDP_PWR_CON0x029c  /* MT2701 */
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
@@ -42,10 +48,15 @@
 #define PWR_ON_2ND_BIT BIT(3)
 #define PWR_CLK_DIS_BITBIT(4)
 
+#define PWR_STATUS_CONNBIT(1)
 #define PWR_STATUS_DISPBIT(3)
 #define PWR_STATUS_MFG BIT(4)
 #define PWR_STATUS_ISP BIT(5)
 #define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
 #define PWR_STATUS_VENC_LT BIT(20)
 #define PWR_STATUS_VENCBIT(21)
 #define PWR_STATUS_MFG_2D  BIT(22)
@@ -59,6 +70,7 @@ enum clk_id {
CLK_MFG,
CLK_VENC,
CLK_VENC_LT,
+   CLK_ETHIF,
CLK_MAX,
 };
 
@@ -321,7 +333,8 @@ static void init_clks(struct platform_device *pdev, struct 
clk *clk[CLK_MAX])
CLK_MM,
CLK_MFG,
CLK_VENC,
-   CLK_VENC_LT
+   CLK_VENC_LT,
+   CLK_ETHIF
};
 
static const char * const clk_names[] = {
@@ -329,6 +342,7 @@ static void init_clks(struct platform_device *pdev, struct 
clk *clk[CLK_MAX])
"mfg",
"venc",
"venc_lt",
+   "ethif",
};
 
int i;
@@ -459,6 +473,102 @@ static void mtk_register_power_domains(struct 
platform_device *pdev,
 }
 
 /*
+ * MT2701 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt2701[] = {
+   [MT2701_POWER_DOMAIN_CONN] = {
+   .name = "conn",
+   .sta_mask = PWR_STATUS_CONN,
+   .ctl_offs = SPM_CONN_PWR_CON,
+   .bus_prot_mask = 0x0104,
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_DISP] = {
+   .name = "disp",
+   .sta_mask = PWR_STATUS_DISP,
+   .ctl_offs = SPM_DIS_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .clk_id = {CLK_MM},
+   .bus_prot_mask = 0x0002,
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_MFG] = {
+   .name = "mfg",
+   .sta_mask = PWR_STATUS_MFG,
+   .ctl_offs = SPM_MFG_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MFG},
+   .active_wakeup = true,
+   },
+   [MT2701_POWER_DOMAIN_VDEC] = {
+   .name = "vdec",
+   .sta_mask = PWR_STATUS_VDEC,
+   .ctl_offs = SPM_VDE_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .clk_id = {CLK_MM},
+   .active_wakeup = true,
+   },
+   [MT27

[PATCH v7 0/4] Mediatek MT2701 SCPSYS power domain support

[James Liao]

This series is based on v4.6-rc1 and adds scpsys power domain support
for Mediatek MT2701.

To share the code between MT2701 and MT8173, this patchset also refined
original mtk-scpsys.c to separate common codes and platform codes, so
that mtk-scpsys.c can support new SoCs more easily.

MT8173 and MT2701 scpsys init level are now subsys_init. Please refer to [1]
to see discussion details.

changes since v6:
- Minor changes in the dt-binding document.

changes since v5:
- Rebase to v4.6-rc1.
- Add dependent clocks for MFG, ISP, ETH and HIF power domains.
- Add "ethif" as a dependent clock in scpsys dt-binding document.

changes since v4:
- Rebase to v4.5-rc4.
- Remove mtk-scpsys.h and Merge its code into mtk-scpsys.c.
- Add names for every controlling registers and bits.
- Include dt-bindings headers at the beginning of mtk-scpsys.c.
- Sort compatible string in dt-binding documents.

changes since v3:
- Implement MT8173 and MT2701 scpsys drivers in a signle file.
- Remove naming of registers that can't be shared among SoCs.

changes since v2:
- Rebase to mbgg/linux-mediatek v4.4-next/soc [1].
- Remove MTK_SCPSYS_MT8173 and MTK_SCPSYS_MT2701.
- Modify scpsys dt-binding document to support MT2701.

changes since v1:
- Make MTK_SCPSYS in Kconfig invisible from users.
- Add comments for changing scpsys init level to subsys_init.

[1] 
http://lists.infradead.org/pipermail/linux-mediatek/2015-December/003416.html

James Liao (2):
  soc: mediatek: Refine scpsys to support multiple platform
  soc: mediatek: Init MT8173 scpsys driver earlier

Shunli Wang (2):
  soc: mediatek: Add MT2701 power dt-bindings
  soc: mediatek: Add MT2701 scpsys driver

 .../devicetree/bindings/soc/mediatek/scpsys.txt|  13 +-
 drivers/soc/mediatek/Kconfig   |   2 +-
 drivers/soc/mediatek/mtk-scpsys.c  | 497 +++--
 include/dt-bindings/power/mt2701-power.h   |  27 ++
 4 files changed, 388 insertions(+), 151 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

--
1.9.1

[PATCH v7 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Refine scpsys driver common code to support multiple SoC / platform.

Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 363 +++---
 1 file changed, 220 insertions(+), 143 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 57e781c..5870a24 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,17 +11,15 @@
  * GNU General Public License for more details.
  */
 #include 
-#include 
+#include 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
+#include 
+
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -34,6 +32,7 @@
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
+
 #define SPM_PWR_STATUS 0x060c
 #define SPM_PWR_STATUS_2ND 0x0610
 
@@ -55,12 +54,12 @@
 #define PWR_STATUS_USB BIT(25)
 
 enum clk_id {
-   MT8173_CLK_NONE,
-   MT8173_CLK_MM,
-   MT8173_CLK_MFG,
-   MT8173_CLK_VENC,
-   MT8173_CLK_VENC_LT,
-   MT8173_CLK_MAX,
+   CLK_NONE,
+   CLK_MM,
+   CLK_MFG,
+   CLK_VENC,
+   CLK_VENC_LT,
+   CLK_MAX,
 };
 
 #define MAX_CLKS   2
@@ -76,98 +75,6 @@ struct scp_domain_data {
bool active_wakeup;
 };
 
-static const struct scp_domain_data scp_domain_data[] = {
-   [MT8173_POWER_DOMAIN_VDEC] = {
-   .name = "vdec",
-   .sta_mask = PWR_STATUS_VDEC,
-   .ctl_offs = SPM_VDE_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_VENC] = {
-   .name = "venc",
-   .sta_mask = PWR_STATUS_VENC,
-   .ctl_offs = SPM_VEN_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
-   },
-   [MT8173_POWER_DOMAIN_ISP] = {
-   .name = "isp",
-   .sta_mask = PWR_STATUS_ISP,
-   .ctl_offs = SPM_ISP_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_MM] = {
-   .name = "mm",
-   .sta_mask = PWR_STATUS_DISP,
-   .ctl_offs = SPM_DIS_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
-   MT8173_TOP_AXI_PROT_EN_MM_M1,
-   },
-   [MT8173_POWER_DOMAIN_VENC_LT] = {
-   .name = "venc_lt",
-   .sta_mask = PWR_STATUS_VENC_LT,
-   .ctl_offs = SPM_VEN2_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
-   },
-   [MT8173_POWER_DOMAIN_AUDIO] = {
-   .name = "audio",
-   .sta_mask = PWR_STATUS_AUDIO,
-   .ctl_offs = SPM_AUDIO_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_USB] = {
-   .name = "usb",
-   .sta_mask = PWR_STATUS_USB,
-   .ctl_offs = SPM_USB_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   .active_wakeup = true,
-   },
-   [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
-   .name = "mfg_async",
-   .sta_mask = PWR_STATUS_MFG_ASYNC,
-   .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = 0,
-   .clk_id = {MT8173_CLK_MFG},
-   },
-   [MT8173_POWER_DOMAIN_MFG_2D] = {
-   .name = "mfg_2d",
-   .sta_mask = PWR_STATUS_MFG_2D,
-   .ctl_offs = SPM_MFG_2D_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_MFG] = {
-   .name = "mfg",
-   .sta_mask = PWR_STATUS_MFG,
-   .ctl_offs = SPM_MFG_PWR_CON,
-   .sram_pdn_bits = GENMASK(13, 8),
-   .

[PATCH v7 1/4] soc: mediatek: Refine scpsys to support multiple platform

[James Liao]

Refine scpsys driver common code to support multiple SoC / platform.

Signed-off-by: James Liao 
Reviewed-by: Kevin Hilman 
---
 drivers/soc/mediatek/mtk-scpsys.c | 363 +++---
 1 file changed, 220 insertions(+), 143 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index 57e781c..5870a24 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,17 +11,15 @@
  * GNU General Public License for more details.
  */
 #include 
-#include 
+#include 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
+#include 
+
 #include 
 
 #define SPM_VDE_PWR_CON0x0210
@@ -34,6 +32,7 @@
 #define SPM_MFG_2D_PWR_CON 0x02c0
 #define SPM_MFG_ASYNC_PWR_CON  0x02c4
 #define SPM_USB_PWR_CON0x02cc
+
 #define SPM_PWR_STATUS 0x060c
 #define SPM_PWR_STATUS_2ND 0x0610
 
@@ -55,12 +54,12 @@
 #define PWR_STATUS_USB BIT(25)
 
 enum clk_id {
-   MT8173_CLK_NONE,
-   MT8173_CLK_MM,
-   MT8173_CLK_MFG,
-   MT8173_CLK_VENC,
-   MT8173_CLK_VENC_LT,
-   MT8173_CLK_MAX,
+   CLK_NONE,
+   CLK_MM,
+   CLK_MFG,
+   CLK_VENC,
+   CLK_VENC_LT,
+   CLK_MAX,
 };
 
 #define MAX_CLKS   2
@@ -76,98 +75,6 @@ struct scp_domain_data {
bool active_wakeup;
 };
 
-static const struct scp_domain_data scp_domain_data[] = {
-   [MT8173_POWER_DOMAIN_VDEC] = {
-   .name = "vdec",
-   .sta_mask = PWR_STATUS_VDEC,
-   .ctl_offs = SPM_VDE_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_VENC] = {
-   .name = "venc",
-   .sta_mask = PWR_STATUS_VENC,
-   .ctl_offs = SPM_VEN_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
-   },
-   [MT8173_POWER_DOMAIN_ISP] = {
-   .name = "isp",
-   .sta_mask = PWR_STATUS_ISP,
-   .ctl_offs = SPM_ISP_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_MM},
-   },
-   [MT8173_POWER_DOMAIN_MM] = {
-   .name = "mm",
-   .sta_mask = PWR_STATUS_DISP,
-   .ctl_offs = SPM_DIS_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(12, 12),
-   .clk_id = {MT8173_CLK_MM},
-   .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
-   MT8173_TOP_AXI_PROT_EN_MM_M1,
-   },
-   [MT8173_POWER_DOMAIN_VENC_LT] = {
-   .name = "venc_lt",
-   .sta_mask = PWR_STATUS_VENC_LT,
-   .ctl_offs = SPM_VEN2_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
-   },
-   [MT8173_POWER_DOMAIN_AUDIO] = {
-   .name = "audio",
-   .sta_mask = PWR_STATUS_AUDIO,
-   .ctl_offs = SPM_AUDIO_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_USB] = {
-   .name = "usb",
-   .sta_mask = PWR_STATUS_USB,
-   .ctl_offs = SPM_USB_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(15, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   .active_wakeup = true,
-   },
-   [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
-   .name = "mfg_async",
-   .sta_mask = PWR_STATUS_MFG_ASYNC,
-   .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = 0,
-   .clk_id = {MT8173_CLK_MFG},
-   },
-   [MT8173_POWER_DOMAIN_MFG_2D] = {
-   .name = "mfg_2d",
-   .sta_mask = PWR_STATUS_MFG_2D,
-   .ctl_offs = SPM_MFG_2D_PWR_CON,
-   .sram_pdn_bits = GENMASK(11, 8),
-   .sram_pdn_ack_bits = GENMASK(13, 12),
-   .clk_id = {MT8173_CLK_NONE},
-   },
-   [MT8173_POWER_DOMAIN_MFG] = {
-   .name = "mfg",
-   .sta_mask = PWR_STATUS_MFG,
-   .ctl_offs = SPM_MFG_PWR_CON,
-   .sram_pdn_bits = GENMASK(13, 8),
-   .sram_pdn_ack_bits = GENMASK(21, 16),
- 

[PATCH v7 3/4] soc: mediatek: Add MT2701 power dt-bindings

[James Liao]

From: Shunli Wang <shunli.w...@mediatek.com>

Add power dt-bindings for MT2701.

Signed-off-by: Shunli Wang <shunli.w...@mediatek.com>
Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
Reviewed-by: Kevin Hilman <khil...@baylibre.com>
---
 .../devicetree/bindings/soc/mediatek/scpsys.txt| 13 +++
 include/dt-bindings/power/mt2701-power.h   | 27 ++
 2 files changed, 35 insertions(+), 5 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 
b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index e8f15e3..16fe94d 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -9,17 +9,20 @@ domain control.
 
 The driver implements the Generic PM domain bindings described in
 power/power_domain.txt. It provides the power domains defined in
-include/dt-bindings/power/mt8173-power.h.
+include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
 
 Required properties:
-- compatible: Must be "mediatek,mt8173-scpsys"
+- compatible: Should be one of:
+   - "mediatek,mt2701-scpsys"
+   - "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
 - infracfg: must contain a phandle to the infracfg controller
 - clock, clock-names: clocks according to the common clock binding.
-  The clocks needed "mm", "mfg", "venc" and "venc_lt".
- These are the clocks which hardware needs to be enabled
- before enabling certain power domains.
+  These are clocks which hardware needs to be
+  enabled before enabling certain power domains.
+   Required clocks for MT2701: "mm", "mfg", "ethif"
+   Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:
 - vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt2701-power.h 
b/include/dt-bindings/power/mt2701-power.h
new file mode 100644
index 000..64cc826
--- /dev/null
+++ b/include/dt-bindings/power/mt2701-power.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
+
+#define MT2701_POWER_DOMAIN_CONN   0
+#define MT2701_POWER_DOMAIN_DISP   1
+#define MT2701_POWER_DOMAIN_MFG2
+#define MT2701_POWER_DOMAIN_VDEC   3
+#define MT2701_POWER_DOMAIN_ISP4
+#define MT2701_POWER_DOMAIN_BDP5
+#define MT2701_POWER_DOMAIN_ETH6
+#define MT2701_POWER_DOMAIN_HIF7
+#define MT2701_POWER_DOMAIN_IFR_MSC8
+
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
-- 
1.9.1

[PATCH v7 3/4] soc: mediatek: Add MT2701 power dt-bindings

[James Liao]

From: Shunli Wang 

Add power dt-bindings for MT2701.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Acked-by: Rob Herring 
Reviewed-by: Kevin Hilman 
---
 .../devicetree/bindings/soc/mediatek/scpsys.txt| 13 +++
 include/dt-bindings/power/mt2701-power.h   | 27 ++
 2 files changed, 35 insertions(+), 5 deletions(-)
 create mode 100644 include/dt-bindings/power/mt2701-power.h

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 
b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index e8f15e3..16fe94d 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -9,17 +9,20 @@ domain control.
 
 The driver implements the Generic PM domain bindings described in
 power/power_domain.txt. It provides the power domains defined in
-include/dt-bindings/power/mt8173-power.h.
+include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
 
 Required properties:
-- compatible: Must be "mediatek,mt8173-scpsys"
+- compatible: Should be one of:
+   - "mediatek,mt2701-scpsys"
+   - "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
 - infracfg: must contain a phandle to the infracfg controller
 - clock, clock-names: clocks according to the common clock binding.
-  The clocks needed "mm", "mfg", "venc" and "venc_lt".
- These are the clocks which hardware needs to be enabled
- before enabling certain power domains.
+  These are clocks which hardware needs to be
+  enabled before enabling certain power domains.
+   Required clocks for MT2701: "mm", "mfg", "ethif"
+   Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:
 - vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt2701-power.h 
b/include/dt-bindings/power/mt2701-power.h
new file mode 100644
index 000..64cc826
--- /dev/null
+++ b/include/dt-bindings/power/mt2701-power.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
+
+#define MT2701_POWER_DOMAIN_CONN   0
+#define MT2701_POWER_DOMAIN_DISP   1
+#define MT2701_POWER_DOMAIN_MFG2
+#define MT2701_POWER_DOMAIN_VDEC   3
+#define MT2701_POWER_DOMAIN_ISP4
+#define MT2701_POWER_DOMAIN_BDP5
+#define MT2701_POWER_DOMAIN_ETH6
+#define MT2701_POWER_DOMAIN_HIF7
+#define MT2701_POWER_DOMAIN_IFR_MSC8
+
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
-- 
1.9.1

Re: [PATCH v7 7/9] clk: mediatek: Enable critical clocks for MT2701

[James Liao]

Hi Stephen, Mike, Lee,

On Mon, 2016-05-09 at 15:13 -0700, Stephen Boyd wrote:
> On 05/09, James Liao wrote:
> > Hi Stephen,
> > 
> > On Fri, 2016-05-06 at 16:12 -0700, Stephen Boyd wrote:
> > > On 04/14, James Liao wrote:
> > > > Some system clocks should be turned on by default on MT2701.
> > > > This patch enable these clocks when related clocks have
> > > > been registered.
> > > > 
> > > > Signed-off-by: James Liao <jamesjj.l...@mediatek.com>
> > > > ---
> > > 
> > > critical clks got merged now (sorry I'm slowly getting back to
> > > looking at patches). Please use that flag.
> > 
> > I don't see critical clock support in v4.6-rc7. Is there a repo/branch
> > that has critical clocks merged?
> > 
> 
> Right, it's in clk-next in the clk tree.

I got the latest code from clk-next and tried to use CLK_IS_CRITICAL fro
critical clocks. But There is something wrong with CLK_IS_CRITICAL. For
example, if we set vdec_sel as a critical clock, we'll get the following
result:

vdecpll   00
   vdecpll_ck 11
  vdec_sel11

vdec_sel and vdecpll_ck are TOPCKGEN clocks. vdecpll is a APMIXEDSYS
PLL, which will be registered after TOPCKGEN clocks. The prepare and
enable count are incorrect in this case.

We may need to prepare/enable a parent clock if an enabled orphan clock
re-parent to it. I tried the following modification and it can resolve
this issue. But I'm not sure it's a correct place to enable parent
clcoks. May I have your comment on this?


diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index ce39add..db1bc3a 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2388,8 +2388,15 @@ static int __clk_core_init(struct clk_core *core)
hlist_for_each_entry_safe(orphan, tmp2, _orphan_list,
child_node) {
struct clk_core *parent = __clk_init_parent(orphan);

-   if (parent)
+   if (parent) {
clk_core_reparent(orphan, parent);
+
+   if (orphan->prepare_count)
+   clk_core_prepare(parent);
+
+   if (orphan->enable_count )
+   clk_core_enable(parent);
+   }
}

/*



Best regards,

James