Re: [PATCH v2 1/3] dt-bindings: clock: meson: add A1 clock controller bindings
Hi, Jerome
Thanks for your review.
On 2019/10/21 18:43, Jerome Brunet wrote:
On Fri 18 Oct 2019 at 09:14, Jian Hu wrote:
Add the documentation to support Amlogic A1 clock driver,
and add A1 clock controller bindings.
Signed-off-by: Jian Hu
---
.../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 143
+
Those are 2 different controllers, not variants.
One description (one file) per controller please
OK, I will describe for periphs and PLLs controller separately.
include/dt-bindings/clock/a1-clkc.h| 98 ++
include/dt-bindings/clock/a1-pll-clkc.h| 16 +++
3 files changed, 257 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 000..b382eebe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson A/C serials Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong
+ - Jerome Brunet
+ - Jian Hu
+
+description: |+
+ The clock controller node should be the child of a syscon node with the
+ required property:
+
+ - compatible: Should be one of the following:
+"amlogic,meson-a-analog-sysctrl", "syscon",
"simple-mfd"
+"amlogic,meson-a-periphs-sysctrl", "syscon",
"simple-mfd"
+
+ Refer to the the bindings described in
+ Documentation/devicetree/bindings/mfd/syscon.txt
+
+properties:
+ "#clock-cells":
+const: 1
+ compatible:
+- enum:
+- amlogic,a1-periphs-clkc
+- amlogic,a1-pll-clkc
+
+ reg:
+maxItems: 1
+
+ clocks:
+minItems: 2
+maxItems: 6
+
+ clock-names:
+minItems: 2
+maxItems: 6
+
+required:
+ - "#clock-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+if:
+ properties:
+compatible:
+ enum:
+- amlogic,a1-periphs-clkc
+
+then:
+ properties:
+clocks:
+ minItems: 2
+ maxItems: 2
+items:
+ - description: fixed pll gate clock
+ - description: hifi pll gate clock
+
+clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+- const: xtal_fixpll
+- const: xtal_hifipll
+
+else:
+ if:
+properties:
+ compatible:
+const: amlogic,a1-pll-clkc
+
+ then:
+properties:
+ clocks:
+minItems: 6
+maxItems: 6
+items:
+ - description: Input fixed pll div2
+ - description: Input fixed pll div3
+ - description: Input fixed pll div5
+ - description: Input fixed pll div7
+ - description: Periph Hifi pll
+ - description: Input Oscillator (usually at 24MHz)
+
+ clock-names:
+minItems: 6
+maxItems: 6
+items:
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: fclk_div5
+ - const: fclk_div7
+ - const: hifi_pll
+ - const: xtal
+
+
+additionalProperties: false
+
+examples:
+ - |
+analog: system-controller@0 {
+compatible = "amlogic,meson-a-analog-sysctrl",
+ "simple-mfd", "syscon";
+reg = <0 0x7c00 0 0x21c>;
+
+clkc_pll: pll-clock-controller {
+compatible = "amlogic,a1-pll-clkc";
+#clock-cells = <1>;
+clocks = <_periphs CLKID_XTAL_FIXPLL>,
+ <_periphs CLKID_XTAL_HIFIPLL>;
+clock-names = "xtal_fixpll", "xtal_hifipll";
+};
+};
+
+ - |
+periphs: system-controller@1 {
+compatible = "amlogic,meson-a-periphs-sysctrl",
+ "simple-mfd", "syscon";
+reg = <0 0x800 0 0x104>;
+
+clkc_periphs: periphs-clock-controller {
+compatible = "amlogic,a1-periphs-clkc";
+#clock-cells = <1>;
+clocks = <_pll CLKID_FCLK_DIV2>,
+<_pll CLKID_FCLK_DIV3>,
+<_pll CLKID_FCLK_DIV5>,
+<_pll CLKID_FCLK_DIV7>,
+<_pll CLKID_HIFI_PLL>,
+<>;
+clock-names = "fclk_div2", "fclk_div3", "fclk_div5",
+
[PATCH v2 1/3] dt-bindings: clock: meson: add A1 clock controller bindings
Add the documentation to support Amlogic A1 clock driver,
and add A1 clock controller bindings.
Signed-off-by: Jian Hu
---
.../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 143 +
include/dt-bindings/clock/a1-clkc.h| 98 ++
include/dt-bindings/clock/a1-pll-clkc.h| 16 +++
3 files changed, 257 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 000..b382eebe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson A/C serials Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong
+ - Jerome Brunet
+ - Jian Hu
+
+description: |+
+ The clock controller node should be the child of a syscon node with the
+ required property:
+
+ - compatible: Should be one of the following:
+"amlogic,meson-a-analog-sysctrl", "syscon",
"simple-mfd"
+"amlogic,meson-a-periphs-sysctrl", "syscon",
"simple-mfd"
+
+ Refer to the the bindings described in
+ Documentation/devicetree/bindings/mfd/syscon.txt
+
+properties:
+ "#clock-cells":
+const: 1
+ compatible:
+- enum:
+- amlogic,a1-periphs-clkc
+- amlogic,a1-pll-clkc
+
+ reg:
+maxItems: 1
+
+ clocks:
+minItems: 2
+maxItems: 6
+
+ clock-names:
+minItems: 2
+maxItems: 6
+
+required:
+ - "#clock-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+if:
+ properties:
+compatible:
+ enum:
+- amlogic,a1-periphs-clkc
+
+then:
+ properties:
+clocks:
+ minItems: 2
+ maxItems: 2
+items:
+ - description: fixed pll gate clock
+ - description: hifi pll gate clock
+
+clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+- const: xtal_fixpll
+- const: xtal_hifipll
+
+else:
+ if:
+properties:
+ compatible:
+const: amlogic,a1-pll-clkc
+
+ then:
+properties:
+ clocks:
+minItems: 6
+maxItems: 6
+items:
+ - description: Input fixed pll div2
+ - description: Input fixed pll div3
+ - description: Input fixed pll div5
+ - description: Input fixed pll div7
+ - description: Periph Hifi pll
+ - description: Input Oscillator (usually at 24MHz)
+
+ clock-names:
+minItems: 6
+maxItems: 6
+items:
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: fclk_div5
+ - const: fclk_div7
+ - const: hifi_pll
+ - const: xtal
+
+
+additionalProperties: false
+
+examples:
+ - |
+analog: system-controller@0 {
+compatible = "amlogic,meson-a-analog-sysctrl",
+ "simple-mfd", "syscon";
+reg = <0 0x7c00 0 0x21c>;
+
+clkc_pll: pll-clock-controller {
+compatible = "amlogic,a1-pll-clkc";
+#clock-cells = <1>;
+clocks = <_periphs CLKID_XTAL_FIXPLL>,
+ <_periphs CLKID_XTAL_HIFIPLL>;
+clock-names = "xtal_fixpll", "xtal_hifipll";
+};
+};
+
+ - |
+periphs: system-controller@1 {
+compatible = "amlogic,meson-a-periphs-sysctrl",
+ "simple-mfd", "syscon";
+reg = <0 0x800 0 0x104>;
+
+clkc_periphs: periphs-clock-controller {
+compatible = "amlogic,a1-periphs-clkc";
+#clock-cells = <1>;
+clocks = <_pll CLKID_FCLK_DIV2>,
+<_pll CLKID_FCLK_DIV3>,
+<_pll CLKID_FCLK_DIV5>,
+<_pll CLKID_FCLK_DIV7>,
+<_pll CLKID_HIFI_PLL>,
+<>;
+clock-names = "fclk_div2", "fclk_div3", "fclk_div5",
+ "fclk_div7", "hifi_pll", "xtal";
+};
+};
diff --git a/include/dt-bindings/clock/a1-clkc.h
b/include/dt-bindings/clock/a1-clkc.h
new file mode 100644
index 000..1ba0112
--- /dev/null
+++ b/include/dt-bindings/clock/a1-clkc.h
@@ -0,0
[PATCH v2 2/3] clk: meson: add support for A1 PLL clock ops
The A1 PLL design is different with previous SoCs. The PLL
internal analog modules Power-on sequence is different
with previous, and thus requires a strict register sequence to
enable the PLL. Unlike the previous series, the maximum frequency
is 6G in G12A, for A1 the maximum is 1536M.
Signed-off-by: Jian Hu
---
drivers/clk/meson/clk-pll.c | 66 -
drivers/clk/meson/clk-pll.h | 1 +
2 files changed, 61 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index ddb1e56..b440e62 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -349,6 +349,56 @@ static void meson_clk_pll_disable(struct clk_hw *hw)
meson_parm_write(clk->map, >en, 0);
}
+/*
+ * The A1 design is different with previous SoCs.The PLL
+ * internal analog modules Power-on sequence is different with
+ * previous, different PLL has the different sequence, and
+ * thus requires a strict register sequence to enable the PLL.
+ * When set a new target frequency, the sequence should keep
+ * the same with the initial sequence. Unlike the previous series,
+ * the maximum frequency is 6G in G12A, for A1 the maximum
+ * is 1536M.
+ */
+static void meson_params_update_with_init_seq(struct clk_regmap *clk,
+ struct meson_clk_pll_data *pll,
+ unsigned int m, unsigned int n,
+ unsigned int frac)
+{
+ struct parm *pm = >m;
+ struct parm *pn = >n;
+ struct parm *pfrac = >frac;
+ const struct reg_sequence *init_regs = pll->init_regs;
+ unsigned int i, val;
+
+ for (i = 0; i < pll->init_count; i++) {
+ if (pn->reg_off == init_regs[i].reg) {
+ /* Clear M N bits and Update M N value */
+ val = init_regs[i].def;
+ val &= CLRPMASK(pn->width, pn->shift);
+ val &= CLRPMASK(pm->width, pm->shift);
+ val |= n << pn->shift;
+ val |= m << pm->shift;
+ regmap_write(clk->map, pn->reg_off, val);
+ } else if (MESON_PARM_APPLICABLE(>frac) &&
+ (pfrac->reg_off == init_regs[i].reg)) {
+ /* Clear Frac bits and Update Frac value */
+ val = init_regs[i].def;
+ val &= CLRPMASK(pfrac->width, pfrac->shift);
+ val |= frac << pfrac->shift;
+ regmap_write(clk->map, pfrac->reg_off, val);
+ } else {
+ /*
+* According to the PLL hardware constraint,
+* the left registers should be setted again.
+*/
+ val = init_regs[i].def;
+ regmap_write(clk->map, init_regs[i].reg, val);
+ }
+ if (init_regs[i].delay_us)
+ udelay(init_regs[i].delay_us);
+ }
+}
+
static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -366,16 +416,20 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw,
unsigned long rate,
if (ret)
return ret;
+ if (MESON_PARM_APPLICABLE(>frac))
+ frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);
+
enabled = meson_parm_read(clk->map, >en);
if (enabled)
meson_clk_pll_disable(hw);
- meson_parm_write(clk->map, >n, n);
- meson_parm_write(clk->map, >m, m);
-
- if (MESON_PARM_APPLICABLE(>frac)) {
- frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);
- meson_parm_write(clk->map, >frac, frac);
+ if (pll->strict_sequence)
+ meson_params_update_with_init_seq(clk, pll, m, n, frac);
+ else {
+ meson_parm_write(clk->map, >n, n);
+ meson_parm_write(clk->map, >m, m);
+ if (MESON_PARM_APPLICABLE(>frac))
+ meson_parm_write(clk->map, >frac, frac);
}
/* If the pll is stopped, bail out now */
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 367efd0..d5789cef 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -41,6 +41,7 @@ struct meson_clk_pll_data {
const struct pll_params_table *table;
const struct pll_mult_range *range;
u8 flags;
+ bool strict_sequence;
};
extern const struct clk_ops meson_clk_pll_ro_ops;
--
1.9.1
[PATCH v2 3/3] clk: meson: a1: add support for Amlogic A1 clock driver
The Amlogic A1 clock includes three drivers:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
---
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/a1-pll.c | 345 +++
drivers/clk/meson/a1-pll.h | 56 ++
drivers/clk/meson/a1.c | 2264
drivers/clk/meson/a1.h | 120 +++
6 files changed, 2796 insertions(+)
create mode 100644 drivers/clk/meson/a1-pll.c
create mode 100644 drivers/clk/meson/a1-pll.h
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index dabeb43..c2809b2 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -93,6 +93,16 @@ config COMMON_CLK_AXG_AUDIO
Support for the audio clock controller on AmLogic A113D devices,
aka axg, Say Y if you want audio subsystem to work.
+config COMMON_CLK_A1
+ bool
+ depends on ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_DUALDIV
+ select COMMON_CLK_MESON_PLL
+ help
+ Support for the clock controller on Amlogic A113L device,
+ aka a1. Say Y if you want peripherals to work.
+
config COMMON_CLK_G12A
bool
depends on ARCH_MESON
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 3939f21..28cbae1 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_A1) += a1-pll.o a1.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
new file mode 100644
index 000..486d964
--- /dev/null
+++ b/drivers/clk/meson/a1-pll.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu
+ */
+
+#include
+#include "clk-pll.h"
+#include "meson-eeclk.h"
+#include "a1-pll.h"
+
+static struct clk_regmap a1_fixed_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_FIXPLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll_dco",
+ .ops = _clk_pll_ro_ops,
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xtal_fixpll",
+ .name = "xtal_fixpll",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_fixed_pll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .bit_idx = 20,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fixed_pll",
+ .ops = _regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ _fixed_pll_dco.hw
+ },
+ .num_parents = 1,
+ /*
+* This clock is fclk_div2/3/4's parent,
+* However, fclk_div2/3/5 feeds AXI/APB/DDR.
+* It is required by the platform to operate correctly.
+* Until the following condition are met, we need this clock to
+* be marked as critical:
+* a) Mark the clock used by a firmware resource, if possible
+* b) CCF has a clock hand-off mechanism to make the sure the
+*clo
[PATCH v2 0/3] add Amlogic A1 clock controller driver
add support for Amlogic A1 clock driver, the clock includes three parts: peripheral clocks, pll clocks, CPU clocks. sys pll and CPU clocks will be sent in next patch. Changes since v1 at [1]: -place A1 config alphabetically -add actual reason for RO ops, CLK_IS_CRITICAL, CLK_IGNORE_UNUSED -separate the driver into two driver: peripheral and pll driver -delete CLK_IGNORE_UNUSED flag for pwm b/c/d/e/f clock, dsp clock -delete the change in Kconfig.platforms, address to Kevin alone -remove the useless comments -modify the meson pll driver to support A1 PLLs [1] https://lkml.kernel.org/r/1569411888-98116-1-git-send-email-jian...@amlogic.com Jian Hu (3): dt-bindings: clock: meson: add A1 clock controller bindings clk: meson: add support for A1 PLL clock ops clk: meson: a1: add support for Amlogic A1 clock driver .../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 143 ++ drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile |1 + drivers/clk/meson/a1-pll.c | 345 +++ drivers/clk/meson/a1-pll.h | 56 + drivers/clk/meson/a1.c | 2264 drivers/clk/meson/a1.h | 120 ++ drivers/clk/meson/clk-pll.c| 66 +- drivers/clk/meson/clk-pll.h|1 + include/dt-bindings/clock/a1-clkc.h| 98 + include/dt-bindings/clock/a1-pll-clkc.h| 16 + 11 files changed, 3114 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml create mode 100644 drivers/clk/meson/a1-pll.c create mode 100644 drivers/clk/meson/a1-pll.h create mode 100644 drivers/clk/meson/a1.c create mode 100644 drivers/clk/meson/a1.h create mode 100644 include/dt-bindings/clock/a1-clkc.h create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h -- 1.9.1
Re: [PATCH 2/2] clk: meson: a1: add support for Amlogic A1 clock driver
Hi, jerome
On 2019/10/14 22:55, Jerome Brunet wrote:
On Mon 14 Oct 2019 at 15:42, Jian Hu wrote:
if peripheral clocks probe first, it will fail to get
fixed_pll clocks. A lot of peripheral clocks parent are fclk_div2/3/5/7.
and we can not get fclk_div2/3/5/7 clocks.
What does "fail" mean ?
I intended to get clock using devm_clk_get API in each driver, In this
scene，it will get failed because of the clock not being reigstered. In
fact, we could not use devm_clk_get.
Unless I missed somthing, I don't see why you would need to call
devm_clk_get(). This is now handled directly by the framework.
Just my wrong idea，I had not noticed the CCF would do it.
I can think of two solutions:
1) Do not describe xtal_fixpll, xtal_hifipll.
that is to say, do not decribe the SYS_OSCIN_CTRL register.
2) Put peripheral and pll clock driver in one driver.
Those are work arounds. Actually fixing the problem is usually
preferable.
So if rephrase your problem:
* We have 2 clock controllers (A and B)
* Clock are passed between the controllers using DT
* We have a PLL in controller B which is used by clocks in
controller A.
* the PLL parent clock is in controller A.
Yeah, it is the scene.
=> So if I understand correctly you are saying that it will "fail"
because there is a circular dependency between controller A and B, right
?
Do you have evidence that your problem comes from this circular
dependency ?
I have realized the peripheral driver and PLL drivers,
PLL driver probes first, Peripheral clock driver is the second.
It should work regarless of the order.
In addition，for A1 SoC， it will not work using meson_clk_pll_ops,
it needs strictly sequence，so maybe another ops is required.hifi pll will
be sent with sys pll and CPU clock driver.
The PCie PLL has a good reason to have a single frequency, only one is needed
That's the case the case of the HIFI PLL which, as explained in previous
mails, needs to provide more that the single frenquency you have described.
If the pll driver needs to extended with new ops that's fine. Please
explain this "strict sequence" you are refering too.
What is part of the initial settings, what needs to be done each time ?
The inital settings is the PLL internal analog modules Power-on
sequence, and it is provided by the VLSI colleague.
For A1 PLL, the pll lock monitor block will initialise again in each
time. It is the internal principle.It should keep the strict sequence
when set one target frequency.
AFAIK, CCF will orphan the clock and continue if the parent is not
available. Later, when the parent comes up, the orphan will be
reparented.
IOW, the problem you are reporting should already be covered by CCF.
And which sulution is better above two?
Neither, I'm afraid
Or maybe other good ideas for it?
My bet would be that an important clocks (maybe more than 1) is being
gated during the init process.
Maybe you should try the command line parameter "clk_ignore_unused"
until you get things running with your 2 controllers.
On 2019/9/29 17:38, Jian Hu wrote:
On 2019/9/27 21:32, Jerome Brunet wrote:
On Fri 27 Sep 2019 at 11:52, Jian Hu wrote:
Hi, Jerome
Thank you for review.
On 2019/9/25 23:09, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
arch/arm64/Kconfig.platforms |1 +
drivers/clk/meson/Kconfig| 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/a1.c | 2617
++
drivers/clk/meson/a1.h | 172 +++
5 files changed, 2801 insertions(+)
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
[...]
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 000..26edae0f
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,2617 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "meson-eeclk.h"
+#include "a1.h"
+
+/* PLLs clock in gates, its parent is xtal */
+static struct clk_regmap a1_xtal_clktree = {
+.data = &(struct clk_regmap_gate_data){
+.offset = SYS_OSCIN_CTRL,
+.bit_idx = 0,
+},
+.hw.init = &(struct clk_init_data) {
+.name = "xtal_clktree",
+.ops = _regmap_gate_ops,
+.parent_data = &(const struct clk_parent_d
Re: [PATCH 2/2] clk: meson: a1: add support for Amlogic A1 clock driver
Hi, Jerome
sorry, it's my problem.
I did not discribe clearly the issue.
On 2019/10/11 15:39, Jerome Brunet wrote:
On Tue 08 Oct 2019 at 10:03, Jian Hu wrote:
Hi, Jerome
PLL clocks and peripheral clocks rely on each other.
for fixed_pll, we can describe its parent like this:
xtal-->xtal_fixpll-->fixed_dco-->fixed_pll
xtal fixpll is belong to peripheral region.
fixed_pll/fclk_div2/fclk_div3 is belong to PLL region.
if PLL clocks probe first, it will fail to get xtal_fixpll.
we can not get fixed_dco's parent clock.
if peripheral clocks probe first, it will fail to get
fixed_pll clocks. A lot of peripheral clocks parent are fclk_div2/3/5/7.
and we can not get fclk_div2/3/5/7 clocks.
What does "fail" mean ?
I intended to get clock using devm_clk_get API in each driver, In this
scene，it will get failed because of the clock not being reigstered. In
fact, we could not use devm_clk_get.
I can think of two solutions:
1) Do not describe xtal_fixpll, xtal_hifipll.
that is to say, do not decribe the SYS_OSCIN_CTRL register.
2) Put peripheral and pll clock driver in one driver.
Those are work arounds. Actually fixing the problem is usually
preferable.
So if rephrase your problem:
* We have 2 clock controllers (A and B)
* Clock are passed between the controllers using DT
* We have a PLL in controller B which is used by clocks in
controller A.
* the PLL parent clock is in controller A.
Yeah, it is the scene.
=> So if I understand correctly you are saying that it will "fail"
because there is a circular dependency between controller A and B, right
?
Do you have evidence that your problem comes from this circular
dependency ?
I have realized the peripheral driver and PLL drivers,
PLL driver probes first, Peripheral clock driver is the second.
In addition，for A1 SoC， it will not work using meson_clk_pll_ops,
it needs strictly sequence，so maybe another ops is required.hifi pll
will be sent with sys pll and CPU clock driver.
AFAIK, CCF will orphan the clock and continue if the parent is not
available. Later, when the parent comes up, the orphan will be
reparented.
IOW, the problem you are reporting should already be covered by CCF.
And which sulution is better above two?
Neither, I'm afraid
Or maybe other good ideas for it?
My bet would be that an important clocks (maybe more than 1) is being
gated during the init process.
Maybe you should try the command line parameter "clk_ignore_unused"
until you get things running with your 2 controllers.
On 2019/9/29 17:38, Jian Hu wrote:
On 2019/9/27 21:32, Jerome Brunet wrote:
On Fri 27 Sep 2019 at 11:52, Jian Hu wrote:
Hi, Jerome
Thank you for review.
On 2019/9/25 23:09, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
arch/arm64/Kconfig.platforms |1 +
drivers/clk/meson/Kconfig| 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/a1.c | 2617
++
drivers/clk/meson/a1.h | 172 +++
5 files changed, 2801 insertions(+)
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
[...]
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 000..26edae0f
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,2617 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "meson-eeclk.h"
+#include "a1.h"
+
+/* PLLs clock in gates, its parent is xtal */
+static struct clk_regmap a1_xtal_clktree = {
+.data = &(struct clk_regmap_gate_data){
+.offset = SYS_OSCIN_CTRL,
+.bit_idx = 0,
+},
+.hw.init = &(struct clk_init_data) {
+.name = "xtal_clktree",
+.ops = _regmap_gate_ops,
+.parent_data = &(const struct clk_parent_data) {
+.fw_name = "xtal",
+},
+.num_parents = 1,
+.flags = CLK_IS_CRITICAL,
Is CCF even expected to touch this ever ? what about RO ops ?
Please review your other clocks with this in mind
the clock should not be changed at runtime.clk_regmap_gate_ro_ops
is a good idea. Set RO ops and remove the CLK_IS_CRITICAL flag.
+},
+};
+
+static struct clk_regmap a1_xtal_fixpll = {
+.data = &(struct clk_regmap_gate_data){
+.offset = SYS_OSCIN_CTRL,
+.bit_idx = 1,
Re: [PATCH 2/2] clk: meson: a1: add support for Amlogic A1 clock driver
Hi, Jerome
PLL clocks and peripheral clocks rely on each other.
for fixed_pll, we can describe its parent like this:
xtal-->xtal_fixpll-->fixed_dco-->fixed_pll
xtal fixpll is belong to peripheral region.
fixed_pll/fclk_div2/fclk_div3 is belong to PLL region.
if PLL clocks probe first, it will fail to get xtal_fixpll.
we can not get fixed_dco's parent clock.
if peripheral clocks probe first, it will fail to get
fixed_pll clocks. A lot of peripheral clocks parent are fclk_div2/3/5/7.
and we can not get fclk_div2/3/5/7 clocks.
I can think of two solutions:
1) Do not describe xtal_fixpll, xtal_hifipll.
that is to say, do not decribe the SYS_OSCIN_CTRL register.
2) Put peripheral and pll clock driver in one driver.
And which sulution is better above two?
Or maybe other good ideas for it?
On 2019/9/29 17:38, Jian Hu wrote:
On 2019/9/27 21:32, Jerome Brunet wrote:
On Fri 27 Sep 2019 at 11:52, Jian Hu wrote:
Hi, Jerome
Thank you for review.
On 2019/9/25 23:09, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
arch/arm64/Kconfig.platforms | 1 +
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/a1.c | 2617
++
drivers/clk/meson/a1.h | 172 +++
5 files changed, 2801 insertions(+)
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
[...]
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 000..26edae0f
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,2617 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "meson-eeclk.h"
+#include "a1.h"
+
+/* PLLs clock in gates, its parent is xtal */
+static struct clk_regmap a1_xtal_clktree = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_clktree",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
Is CCF even expected to touch this ever ? what about RO ops ?
Please review your other clocks with this in mind
the clock should not be changed at runtime.clk_regmap_gate_ro_ops
is a good idea. Set RO ops and remove the CLK_IS_CRITICAL flag.
+ },
+};
+
+static struct clk_regmap a1_xtal_fixpll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_fixpll",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_regmap a1_xtal_usb_phy = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_usb_phy",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
How is an USB clock critical to the system ?
Please review your other clocks with comment in mind ...
the usb clock does not affect the system,
remove the CLK_IS_CRITICAL flag
+ },
+};
+
+static struct clk_regmap a1_xtal_usb_ctrl = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 3,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_usb_ctrl",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
the usb clock does not affect the system,
remove the CLK_IS_CRITICAL flag
+
+static struct clk_regmap a1_xtal_hifipll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 4,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name
Re: [PATCH 2/2] clk: meson: a1: add support for Amlogic A1 clock driver
On 2019/9/27 21:32, Jerome Brunet wrote:
On Fri 27 Sep 2019 at 11:52, Jian Hu wrote:
Hi, Jerome
Thank you for review.
On 2019/9/25 23:09, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
arch/arm64/Kconfig.platforms |1 +
drivers/clk/meson/Kconfig| 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/a1.c | 2617
++
drivers/clk/meson/a1.h | 172 +++
5 files changed, 2801 insertions(+)
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 16d7614..a48f67d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -138,6 +138,7 @@ config ARCH_MESON
select COMMON_CLK_AXG
select COMMON_CLK_G12A
select MESON_IRQ_GPIO
+ select COMMON_CLK_A1
This need to be separate patch addressed to Kevin once your driver is merged
ok, I will remove it in PATCH V2. And send it again after the driver is
merged.
help
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index dabeb43..e6cb4c3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -107,3 +107,13 @@ config COMMON_CLK_G12A
help
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
devices, aka g12a. Say Y if you want peripherals to work.
+
+config COMMON_CLK_A1
+ bool
+ depends on ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_DUALDIV
+ select COMMON_CLK_MESON_PLL
+ help
+ Support for the clock controller on Amlogic A113L device,
+ aka a1. Say Y if you want peripherals to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 3939f21..6be3a8f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
+obj-$(CONFIG_COMMON_CLK_A1) += a1.o
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 000..26edae0f
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,2617 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "meson-eeclk.h"
+#include "a1.h"
+
+/* PLLs clock in gates, its parent is xtal */
+static struct clk_regmap a1_xtal_clktree = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_clktree",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
Is CCF even expected to touch this ever ? what about RO ops ?
Please review your other clocks with this in mind
the clock should not be changed at runtime.clk_regmap_gate_ro_ops
is a good idea. Set RO ops and remove the CLK_IS_CRITICAL flag.
+ },
+};
+
+static struct clk_regmap a1_xtal_fixpll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_fixpll",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_regmap a1_xtal_usb_phy = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_usb_phy",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+
Re: [PATCH 2/2] clk: meson: a1: add support for Amlogic A1 clock driver
On 2019/9/27 20:56, Jerome Brunet wrote:
On Fri 27 Sep 2019 at 05:11, Jian Hu wrote:
Hi, Stephen
Thank you for review
On 2019/9/25 21:12, Stephen Boyd wrote:
Quoting Jian Hu (2019-09-25 04:44:48)
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
This second name didn't send the patch. Please follow the signoff
procedures documented in Documentation/process/submitting-patches.rst
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 16d7614..a48f67d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -138,6 +138,7 @@ config ARCH_MESON
select COMMON_CLK_AXG
select COMMON_CLK_G12A
select MESON_IRQ_GPIO
+ select COMMON_CLK_A1
Sort?
ok, I will put it behind COMMON_CLK_AXG
help
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index dabeb43..e6cb4c3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -107,3 +107,13 @@ config COMMON_CLK_G12A
help
Support for the clock controller on Amlogic S905D2, S905X2 and
S905Y2
devices, aka g12a. Say Y if you want peripherals to work.
+
+config COMMON_CLK_A1
Probably should be placed somewhere alphabetically in this file?
ok, I will put it behind COMMON_CLK_AXG_AUDIO
+ bool
+ depends on ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_DUALDIV
+ select COMMON_CLK_MESON_PLL
+ help
+ Support for the clock controller on Amlogic A113L device,
+ aka a1. Say Y if you want peripherals to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 3939f21..6be3a8f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
+obj-$(CONFIG_COMMON_CLK_A1) += a1.o
I would guess this should be sorted on Kconfig name in this file?
ok, I will put it behind COMMON_CLK_AXG_AUDIO
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 000..26edae0f
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,2617 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "meson-eeclk.h"
+#include "a1.h"
+
[...]
+
+/*
+ * The Meson A1 HIFI PLL is 614.4M, it requires
+ * a strict register sequence to enable the PLL.
+ * set meson_clk_pcie_pll_ops as its ops
Please remove this last line as it's obvious from the code what ops are
used.
ok, I will remove it.
+ */
+static struct clk_regmap a1_hifi_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = ANACTRL_HIFIPLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .table = a1_hifi_pll_params_table,
+ .init_regs = a1_hifi_init_regs,
+ .init_count = ARRAY_SIZE(a1_hifi_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hifi_pll",
+ .ops = _clk_pcie_pll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ _xtal_hifipll.hw
+ },
+ .num_parents = 1,
+ },
+};
+
[..]
+
+static struct clk_regmap a1_fclk_div2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .bit_idx = 2
Re: [PATCH 2/2] clk: meson: a1: add support for Amlogic A1 clock driver
Hi, Jerome
Thank you for review.
On 2019/9/25 23:09, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
arch/arm64/Kconfig.platforms |1 +
drivers/clk/meson/Kconfig| 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/a1.c | 2617 ++
drivers/clk/meson/a1.h | 172 +++
5 files changed, 2801 insertions(+)
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 16d7614..a48f67d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -138,6 +138,7 @@ config ARCH_MESON
select COMMON_CLK_AXG
select COMMON_CLK_G12A
select MESON_IRQ_GPIO
+ select COMMON_CLK_A1
This need to be separate patch addressed to Kevin once your driver is merged
ok, I will remove it in PATCH V2. And send it again after the driver is
merged.
help
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index dabeb43..e6cb4c3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -107,3 +107,13 @@ config COMMON_CLK_G12A
help
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
devices, aka g12a. Say Y if you want peripherals to work.
+
+config COMMON_CLK_A1
+ bool
+ depends on ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_DUALDIV
+ select COMMON_CLK_MESON_PLL
+ help
+ Support for the clock controller on Amlogic A113L device,
+ aka a1. Say Y if you want peripherals to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 3939f21..6be3a8f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
+obj-$(CONFIG_COMMON_CLK_A1) += a1.o
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 000..26edae0f
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,2617 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "meson-eeclk.h"
+#include "a1.h"
+
+/* PLLs clock in gates, its parent is xtal */
+static struct clk_regmap a1_xtal_clktree = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_clktree",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
Is CCF even expected to touch this ever ? what about RO ops ?
Please review your other clocks with this in mind
the clock should not be changed at runtime.clk_regmap_gate_ro_ops
is a good idea. Set RO ops and remove the CLK_IS_CRITICAL flag.
+ },
+};
+
+static struct clk_regmap a1_xtal_fixpll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_fixpll",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_regmap a1_xtal_usb_phy = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_usb_phy",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+
Re: [PATCH 1/2] dt-bindings: clock: meson: add A1 clock controller bindings
Hi, Jerome
Thank you for review.
On 2019/9/25 22:29, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
In addition to the comment expressed by Stephen on patch 2
got it.
Add the documentation to support Amlogic A1 clock driver,
and add A1 clock controller bindings.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 65 +
include/dt-bindings/clock/a1-clkc.h| 102 +
2 files changed, 167 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 000..f012eb2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson A1 Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong
+ - Jerome Brunet
+ - Jian Hu
+
+properties:
+ compatible:
+- enum:
+- amlogic,a1-clkc
+
+ reg:
+minItems: 1
+maxItems: 3
+items:
+ - description: peripheral registers
+ - description: cpu registers
+ - description: pll registers
+
+ reg-names:
+items:
+ - const: peripheral
+ - const: pll
+ - const: cpu
+
+ clocks:
+maxItems: 1
+items:
+ - description: Input Oscillator (usually at 24MHz)
+
+ clock-names:
+maxItems: 1
+items:
+ - const: xtal
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+examples:
+ - |
+clkc: clock-controller {
+compatible = "amlogic,a1-clkc";
+reg = <0x0 0xfe000800 0x0 0x100>,
+ <0x0 0xfe007c00 0x0 0x21c>,
+ <0x0 0xfd80 0x0 0x20>;
+reg-names = "peripheral", "pll", "cpu";
I'm sorry but I don't agree with this. You are trying to regroup several
controllers into one with this, and it is not OK
By the looks of it there are 3 different controllers, including one you
did not implement in the driver.
Yes, In A1, the clock registers include three regions.
I agree with your opinion. I will implement the two clock drivers of
peripheral and plls first in PATCH V2. And CPU clock driver will be sent
after the patches are merged.
+clocks = <
+clock-names = "xtal";
+#clock-cells = <1>;
.
Re: [PATCH 2/2] clk: meson: a1: add support for Amlogic A1 clock driver
Hi, Stephen
Thank you for review
On 2019/9/25 21:12, Stephen Boyd wrote:
Quoting Jian Hu (2019-09-25 04:44:48)
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
This second name didn't send the patch. Please follow the signoff
procedures documented in Documentation/process/submitting-patches.rst
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 16d7614..a48f67d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -138,6 +138,7 @@ config ARCH_MESON
select COMMON_CLK_AXG
select COMMON_CLK_G12A
select MESON_IRQ_GPIO
+ select COMMON_CLK_A1
Sort?
ok, I will put it behind COMMON_CLK_AXG
help
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index dabeb43..e6cb4c3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -107,3 +107,13 @@ config COMMON_CLK_G12A
help
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
devices, aka g12a. Say Y if you want peripherals to work.
+
+config COMMON_CLK_A1
Probably should be placed somewhere alphabetically in this file?
ok, I will put it behind COMMON_CLK_AXG_AUDIO
+ bool
+ depends on ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_DUALDIV
+ select COMMON_CLK_MESON_PLL
+ help
+ Support for the clock controller on Amlogic A113L device,
+ aka a1. Say Y if you want peripherals to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 3939f21..6be3a8f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
+obj-$(CONFIG_COMMON_CLK_A1) += a1.o
I would guess this should be sorted on Kconfig name in this file?
ok, I will put it behind COMMON_CLK_AXG_AUDIO
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 000..26edae0f
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,2617 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "meson-eeclk.h"
+#include "a1.h"
+
[...]
+
+/*
+ * The Meson A1 HIFI PLL is 614.4M, it requires
+ * a strict register sequence to enable the PLL.
+ * set meson_clk_pcie_pll_ops as its ops
Please remove this last line as it's obvious from the code what ops are
used.
ok, I will remove it.
+ */
+static struct clk_regmap a1_hifi_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = ANACTRL_HIFIPLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .table = a1_hifi_pll_params_table,
+ .init_regs = a1_hifi_init_regs,
+ .init_count = ARRAY_SIZE(a1_hifi_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hifi_pll",
+ .ops = _clk_pcie_pll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ _xtal_hifipll.hw
+ },
+ .num_parents = 1,
+ },
+};
+
[..]
+
+static struct clk_regmap a1_fclk_div2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .bit_idx = 21,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fc
[PATCH 2/2] clk: meson: a1: add support for Amlogic A1 clock driver
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
arch/arm64/Kconfig.platforms |1 +
drivers/clk/meson/Kconfig| 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/a1.c | 2617 ++
drivers/clk/meson/a1.h | 172 +++
5 files changed, 2801 insertions(+)
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 16d7614..a48f67d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -138,6 +138,7 @@ config ARCH_MESON
select COMMON_CLK_AXG
select COMMON_CLK_G12A
select MESON_IRQ_GPIO
+ select COMMON_CLK_A1
help
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index dabeb43..e6cb4c3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -107,3 +107,13 @@ config COMMON_CLK_G12A
help
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
devices, aka g12a. Say Y if you want peripherals to work.
+
+config COMMON_CLK_A1
+ bool
+ depends on ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_DUALDIV
+ select COMMON_CLK_MESON_PLL
+ help
+ Support for the clock controller on Amlogic A113L device,
+ aka a1. Say Y if you want peripherals to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 3939f21..6be3a8f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
+obj-$(CONFIG_COMMON_CLK_A1) += a1.o
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 000..26edae0f
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,2617 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "vid-pll-div.h"
+#include "clk-dualdiv.h"
+#include "meson-eeclk.h"
+#include "a1.h"
+
+/* PLLs clock in gates, its parent is xtal */
+static struct clk_regmap a1_xtal_clktree = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_clktree",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_regmap a1_xtal_fixpll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_fixpll",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_regmap a1_xtal_usb_phy = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_usb_phy",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_regmap a1_xtal_usb_ctrl = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 3,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_usb_ctrl",
+ .ops = _regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents
[PATCH 1/2] dt-bindings: clock: meson: add A1 clock controller bindings
Add the documentation to support Amlogic A1 clock driver,
and add A1 clock controller bindings.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 65 +
include/dt-bindings/clock/a1-clkc.h| 102 +
2 files changed, 167 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 000..f012eb2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson A1 Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong
+ - Jerome Brunet
+ - Jian Hu
+
+properties:
+ compatible:
+- enum:
+- amlogic,a1-clkc
+
+ reg:
+minItems: 1
+maxItems: 3
+items:
+ - description: peripheral registers
+ - description: cpu registers
+ - description: pll registers
+
+ reg-names:
+items:
+ - const: peripheral
+ - const: pll
+ - const: cpu
+
+ clocks:
+maxItems: 1
+items:
+ - description: Input Oscillator (usually at 24MHz)
+
+ clock-names:
+maxItems: 1
+items:
+ - const: xtal
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+examples:
+ - |
+clkc: clock-controller {
+compatible = "amlogic,a1-clkc";
+reg = <0x0 0xfe000800 0x0 0x100>,
+ <0x0 0xfe007c00 0x0 0x21c>,
+ <0x0 0xfd80 0x0 0x20>;
+reg-names = "peripheral", "pll", "cpu";
+clocks = <
+clock-names = "xtal";
+#clock-cells = <1>;
+};
diff --git a/include/dt-bindings/clock/a1-clkc.h
b/include/dt-bindings/clock/a1-clkc.h
new file mode 100644
index 000..69fbf37
--- /dev/null
+++ b/include/dt-bindings/clock/a1-clkc.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_CLKC_H
+#define __A1_CLKC_H
+
+#define CLKID_FIXED_PLL1
+#define CLKID_FCLK_DIV22
+#define CLKID_FCLK_DIV33
+#define CLKID_FCLK_DIV54
+#define CLKID_FCLK_DIV75
+#define CLKID_FCLK_DIV2_DIV6
+#define CLKID_FCLK_DIV3_DIV7
+#define CLKID_FCLK_DIV5_DIV8
+#define CLKID_FCLK_DIV7_DIV9
+#define CLKID_SYS_CLK 16
+#define CLKID_HIFI_PLL 17
+#define CLKID_CLKTREE 25
+#define CLKID_RESET_CTRL 26
+#define CLKID_ANALOG_CTRL 27
+#define CLKID_PWR_CTRL 28
+#define CLKID_PAD_CTRL 29
+#define CLKID_SYS_CTRL 30
+#define CLKID_TEMP_SENSOR 31
+#define CLKID_AM2AXI_DIV 32
+#define CLKID_SPICC_B 33
+#define CLKID_SPICC_A 34
+#define CLKID_CLK_MSR 35
+#define CLKID_AUDIO36
+#define CLKID_JTAG_CTRL37
+#define CLKID_SARADC 38
+#define CLKID_PWM_EF 39
+#define CLKID_PWM_CD 40
+#define CLKID_PWM_AB 41
+#define CLKID_CEC 42
+#define CLKID_I2C_S43
+#define CLKID_IR_CTRL 44
+#define CLKID_I2C_M_D 45
+#define CLKID_I2C_M_C 46
+#define CLKID_I2C_M_B 47
+#define CLKID_I2C_M_A 48
+#define CLKID_ACODEC 49
+#define CLKID_OTP 50
+#define CLKID_SD_EMMC_A51
+#define CLKID_USB_PHY 52
+#define CLKID_USB_CTRL 53
+#define CLKID_SYS_DSPB 54
+#define CLKID_SYS_DSPA 55
+#define CLKID_DMA 56
+#define CLKID_IRQ_CTRL 57
+#define CLKID_NIC 58
+#define CLKID_GIC 59
+#define CLKI
[PATCH 0/2] add Amlogic A1 clock controller driver
add support for Amlogic A1 clock driver, the clock includes three parts: peripheral clocks, pll clocks, CPU clocks. sys pll and CPU clocks will be sent in next patch. Unlike the previous series, there is no EE/AO domain in A1 clock controllers. Jian Hu (2): dt-bindings: clock: meson: add A1 clock controller bindings clk: meson: a1: add support for Amlogic A1 clock driver .../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 65 + arch/arm64/Kconfig.platforms |1 + drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile |1 + drivers/clk/meson/a1.c | 2617 drivers/clk/meson/a1.h | 172 ++ include/dt-bindings/clock/a1-clkc.h| 102 + 7 files changed, 2968 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml create mode 100644 drivers/clk/meson/a1.c create mode 100644 drivers/clk/meson/a1.h create mode 100644 include/dt-bindings/clock/a1-clkc.h -- 1.9.1
Re: [PATCH v5 1/2] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
Hi, Rob I will add it in next version, thanks. On 2018/12/4 7:06, Rob Herring wrote: On Thu, Nov 29, 2018 at 09:41:56PM +0800, Jian Hu wrote: Add new clock controller compatible and dt-bingdings headers for the Everything-Else domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-clkc.txt | 1 + include/dt-bindings/clock/g12a-clkc.h | 93 ++ 2 files changed, 94 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h Please add acks/reviewed-bys when posting new versions. Rob .
Re: [PATCH v5 1/2] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
Hi, Rob I will add it in next version, thanks. On 2018/12/4 7:06, Rob Herring wrote: On Thu, Nov 29, 2018 at 09:41:56PM +0800, Jian Hu wrote: Add new clock controller compatible and dt-bingdings headers for the Everything-Else domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-clkc.txt | 1 + include/dt-bindings/clock/g12a-clkc.h | 93 ++ 2 files changed, 94 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h Please add acks/reviewed-bys when posting new versions. Rob .
[PATCH v5 2/2] clk: meson-g12a: Add EE Clock controller driver
Add a Clock driver for the Everything-Else part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
arch/arm64/Kconfig.platforms |1 +
drivers/clk/meson/Kconfig|8 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/g12a.c | 1185 ++
drivers/clk/meson/g12a.h | 130 +
5 files changed, 1325 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 51bc479..95d824c 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -116,6 +116,7 @@ config ARCH_MESON
select COMMON_CLK_GXBB
select COMMON_CLK_AXG
select MESON_IRQ_GPIO
+ select COMMON_CLK_G12A
help
This enables support for the Amlogic S905 SoCs.
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f..209c2590 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -54,3 +54,11 @@ config COMMON_CLK_AXG_AUDIO
help
Support for the audio clock controller on AmLogic A113D devices,
aka axg, Say Y if you want audio subsystem to work.
+
+config COMMON_CLK_G12A
+ bool
+ select COMMON_CLK_AMLOGIC
+ select MFD_SYSCON
+ help
+ Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
+ devices, aka g12a.Say Y if you want peripherals to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 0234767..7ff278d 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 000..f8380f5
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,1185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai
+ * Author: Jian Hu
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "g12a.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap g12a_fixed_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = HHI_FIX_PLL_CNTL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll_dco",
+ .ops = _clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "g12a_ee_core" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap g12a_fixed_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_FIX_PLL_CNTL0,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = _regmap_divider_ro_ops,
+ .parent_names = (const char *[]){ "fixed_pll_dco" },
+ .num_parents = 1,
+ /*
+* This clock won't ever change at runtime so
+* CLK_SET_RATE_PARENT is not required
+*/
+ },
+};
+
+/*
+ * Internal sys pll emulation configuration parameters
+ */
+static const struct reg_sequence g12a_sys_init_regs[] = {
+ { .reg = HHI_SYS_PLL_CNTL1, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL2, .def = 0x },
[PATCH v5 1/2] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
Add new clock controller compatible and dt-bingdings headers for the Everything-Else domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-clkc.txt | 1 + include/dt-bindings/clock/g12a-clkc.h | 93 ++ 2 files changed, 94 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599..0833006 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,7 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. + "amlogic,g12a-clkc" for G12A SoC. - #clock-cells: should be 1. diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 000..b55e6e1 --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL1 +#define CLKID_FCLK_DIV22 +#define CLKID_FCLK_DIV33 +#define CLKID_FCLK_DIV44 +#define CLKID_FCLK_DIV55 +#define CLKID_FCLK_DIV76 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK8110 +#define CLKID_MPLL011 +#define CLKID_MPLL112 +#define CLKID_MPLL213 +#define CLKID_MPLL314 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL30121 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART028 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A33 +#define CLKID_SD_EMMC_B34 +#define CLKID_SD_EMMC_C35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO37 +#define CLKID_ETH 38 +#define CLKID_DEMUX39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART142 +#define CLKID_G2D 43 +#define CLKID_RESET44 +#define CLKID_PCIE_COMB45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT65654 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART257 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_B_CLK0 60 +#define CLKID_SD_EMMC_C_CLK0 61 +#define CLKID_HIFI_PLL 71 +#define CLKID_VCLK2_VENCI0 77 +#define CLKID_VCLK2_VENCI1 78 +#define CLKID_VCLK2_VENCP0 79 +#define CLKID_VCLK2_VENCP1 80 +#define CLKID_VCLK2_VENCT0 81 +#define CLKID_VCLK2_VENCT1 82 +#define CLKID_VCLK2_OTHER 83 +#define CLKID_VCLK2_ENCI
[PATCH v5 2/2] clk: meson-g12a: Add EE Clock controller driver
Add a Clock driver for the Everything-Else part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
arch/arm64/Kconfig.platforms |1 +
drivers/clk/meson/Kconfig|8 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/g12a.c | 1185 ++
drivers/clk/meson/g12a.h | 130 +
5 files changed, 1325 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 51bc479..95d824c 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -116,6 +116,7 @@ config ARCH_MESON
select COMMON_CLK_GXBB
select COMMON_CLK_AXG
select MESON_IRQ_GPIO
+ select COMMON_CLK_G12A
help
This enables support for the Amlogic S905 SoCs.
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f..209c2590 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -54,3 +54,11 @@ config COMMON_CLK_AXG_AUDIO
help
Support for the audio clock controller on AmLogic A113D devices,
aka axg, Say Y if you want audio subsystem to work.
+
+config COMMON_CLK_G12A
+ bool
+ select COMMON_CLK_AMLOGIC
+ select MFD_SYSCON
+ help
+ Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
+ devices, aka g12a.Say Y if you want peripherals to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 0234767..7ff278d 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 000..f8380f5
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,1185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai
+ * Author: Jian Hu
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "g12a.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap g12a_fixed_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = HHI_FIX_PLL_CNTL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll_dco",
+ .ops = _clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "g12a_ee_core" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap g12a_fixed_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_FIX_PLL_CNTL0,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = _regmap_divider_ro_ops,
+ .parent_names = (const char *[]){ "fixed_pll_dco" },
+ .num_parents = 1,
+ /*
+* This clock won't ever change at runtime so
+* CLK_SET_RATE_PARENT is not required
+*/
+ },
+};
+
+/*
+ * Internal sys pll emulation configuration parameters
+ */
+static const struct reg_sequence g12a_sys_init_regs[] = {
+ { .reg = HHI_SYS_PLL_CNTL1, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL2, .def = 0x },
[PATCH v5 1/2] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
Add new clock controller compatible and dt-bingdings headers for the Everything-Else domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-clkc.txt | 1 + include/dt-bindings/clock/g12a-clkc.h | 93 ++ 2 files changed, 94 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599..0833006 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,7 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. + "amlogic,g12a-clkc" for G12A SoC. - #clock-cells: should be 1. diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 000..b55e6e1 --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL1 +#define CLKID_FCLK_DIV22 +#define CLKID_FCLK_DIV33 +#define CLKID_FCLK_DIV44 +#define CLKID_FCLK_DIV55 +#define CLKID_FCLK_DIV76 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK8110 +#define CLKID_MPLL011 +#define CLKID_MPLL112 +#define CLKID_MPLL213 +#define CLKID_MPLL314 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL30121 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART028 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A33 +#define CLKID_SD_EMMC_B34 +#define CLKID_SD_EMMC_C35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO37 +#define CLKID_ETH 38 +#define CLKID_DEMUX39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART142 +#define CLKID_G2D 43 +#define CLKID_RESET44 +#define CLKID_PCIE_COMB45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT65654 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART257 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_B_CLK0 60 +#define CLKID_SD_EMMC_C_CLK0 61 +#define CLKID_HIFI_PLL 71 +#define CLKID_VCLK2_VENCI0 77 +#define CLKID_VCLK2_VENCI1 78 +#define CLKID_VCLK2_VENCP0 79 +#define CLKID_VCLK2_VENCP1 80 +#define CLKID_VCLK2_VENCT0 81 +#define CLKID_VCLK2_VENCT1 82 +#define CLKID_VCLK2_OTHER 83 +#define CLKID_VCLK2_ENCI
[PATCH v5 0/2] clk: meson-g12a: Add EE clock controller driver
Changes since v4 at[5] -add bypass clock "g12a_ee_core" from DT -fix Kconfig description -change g12a_mpll0_div/g12a_mpll1_div/g12a_mpll2_div/g12a_mpll3_div clock's parent name as fixed_pll_dco -drop CLK_SET_RATE_PARENT flag for pll clock -drop CLK_GET_RATE_NOCACHE flag for pll_dco clock -delete usless note -enable G12A clock driver Changes since v3 at[4] -add fixed clocks clk_regmap definition Changes since v2 at[2] -fix fixed clocks's descriptions -fix alignment -add enable bit for plls base on [3] patches -add fixed clock gate bit Changes since v1 at[1] -fix typo of 'Everything'. -change the word 'AmLogic' to 'Amlogic' -squash patch 1 and 2. -delete usless message of "Trying obsolete regs". -delete the empty line in include/dt-bindings/clock/g12a-clkc.h. -rebase on top of the "next/drivers" branch, and add g12a clock patch. -add CLK_MUX_ROUND_CLOSEST for g12a_sd_emmc_b_clk0_sel and g12a_sd_emmc_c_clk0_sel. [1]https://lkml.kernel.org/r/1531133549-25806-2-git-send-email-jian...@amlogic.com [2]https://lkml.kernel.org/r/1531728707-192230-2-git-send-email-jian...@amlogic.com [3]https://lkml.kernel.org/r/20180717095617.12240-1-jbru...@baylibre.com [4]https://lkml.kernel.org/r/1533890858-113020-1-git-send-email-jian...@amlogic.com [5]https://lkml.kernel.org/r/1541511349-121152-1-git-send-email-jian...@amlogic.com Jian Hu (2): dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings clk: meson-g12a: Add EE Clock controller driver .../bindings/clock/amlogic,gxbb-clkc.txt |1 + arch/arm64/Kconfig.platforms |1 + drivers/clk/meson/Kconfig |8 + drivers/clk/meson/Makefile |1 + drivers/clk/meson/g12a.c | 1185 drivers/clk/meson/g12a.h | 130 +++ include/dt-bindings/clock/g12a-clkc.h | 93 ++ 7 files changed, 1419 insertions(+) create mode 100644 drivers/clk/meson/g12a.c create mode 100644 drivers/clk/meson/g12a.h create mode 100644 include/dt-bindings/clock/g12a-clkc.h -- 1.9.1
[PATCH v5 0/2] clk: meson-g12a: Add EE clock controller driver
Changes since v4 at[5] -add bypass clock "g12a_ee_core" from DT -fix Kconfig description -change g12a_mpll0_div/g12a_mpll1_div/g12a_mpll2_div/g12a_mpll3_div clock's parent name as fixed_pll_dco -drop CLK_SET_RATE_PARENT flag for pll clock -drop CLK_GET_RATE_NOCACHE flag for pll_dco clock -delete usless note -enable G12A clock driver Changes since v3 at[4] -add fixed clocks clk_regmap definition Changes since v2 at[2] -fix fixed clocks's descriptions -fix alignment -add enable bit for plls base on [3] patches -add fixed clock gate bit Changes since v1 at[1] -fix typo of 'Everything'. -change the word 'AmLogic' to 'Amlogic' -squash patch 1 and 2. -delete usless message of "Trying obsolete regs". -delete the empty line in include/dt-bindings/clock/g12a-clkc.h. -rebase on top of the "next/drivers" branch, and add g12a clock patch. -add CLK_MUX_ROUND_CLOSEST for g12a_sd_emmc_b_clk0_sel and g12a_sd_emmc_c_clk0_sel. [1]https://lkml.kernel.org/r/1531133549-25806-2-git-send-email-jian...@amlogic.com [2]https://lkml.kernel.org/r/1531728707-192230-2-git-send-email-jian...@amlogic.com [3]https://lkml.kernel.org/r/20180717095617.12240-1-jbru...@baylibre.com [4]https://lkml.kernel.org/r/1533890858-113020-1-git-send-email-jian...@amlogic.com [5]https://lkml.kernel.org/r/1541511349-121152-1-git-send-email-jian...@amlogic.com Jian Hu (2): dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings clk: meson-g12a: Add EE Clock controller driver .../bindings/clock/amlogic,gxbb-clkc.txt |1 + arch/arm64/Kconfig.platforms |1 + drivers/clk/meson/Kconfig |8 + drivers/clk/meson/Makefile |1 + drivers/clk/meson/g12a.c | 1185 drivers/clk/meson/g12a.h | 130 +++ include/dt-bindings/clock/g12a-clkc.h | 93 ++ 7 files changed, 1419 insertions(+) create mode 100644 drivers/clk/meson/g12a.c create mode 100644 drivers/clk/meson/g12a.h create mode 100644 include/dt-bindings/clock/g12a-clkc.h -- 1.9.1
Re: [PATCH 2/2] i2c: meson: add support for Meson G12A SoC I2C controller
Hi Neil,
On 2018/11/29 19:26, Neil Armstrong wrote:
On 29/11/2018 11:59, Jian Hu wrote:
Add compatible and data for G12A I2C controller.
Signed-off-by: Jian Hu
---
drivers/i2c/busses/i2c-meson.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
index 90f5d04..b86eed7 100644
--- a/drivers/i2c/busses/i2c-meson.c
+++ b/drivers/i2c/busses/i2c-meson.c
@@ -462,10 +462,15 @@ static int meson_i2c_remove(struct platform_device *pdev)
.div_factor = 3,
};
+static const struct meson_i2c_data i2c_g12a_data = {
+ .div_factor = 3,
Especially if the div_factor is the same as AXG.
If you have some other fixes for G12a in the pipe, you will add the new
compatible and meson_i2c_data later,
for the div_factor, simply use the axg struct and compatible.
Neil
For axg and g12a SoC, the div_factor is the same, and I have confirmed
that they share the same IP. I prefer g12a uses axg's compatible and
data if it is reasonable. I will just submit the i2c controller node in
meson-g12a.dtsi.
+};
+
static const struct of_device_id meson_i2c_match[] = {
{ .compatible = "amlogic,meson6-i2c", .data = _meson6_data },
{ .compatible = "amlogic,meson-gxbb-i2c", .data = _gxbb_data },
{ .compatible = "amlogic,meson-axg-i2c", .data = _axg_data },
+ { .compatible = "amlogic,meson-g12a-i2c", .data = _g12a_data },
{},
};
.
Re: [PATCH 2/2] i2c: meson: add support for Meson G12A SoC I2C controller
Hi Neil,
On 2018/11/29 19:26, Neil Armstrong wrote:
On 29/11/2018 11:59, Jian Hu wrote:
Add compatible and data for G12A I2C controller.
Signed-off-by: Jian Hu
---
drivers/i2c/busses/i2c-meson.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
index 90f5d04..b86eed7 100644
--- a/drivers/i2c/busses/i2c-meson.c
+++ b/drivers/i2c/busses/i2c-meson.c
@@ -462,10 +462,15 @@ static int meson_i2c_remove(struct platform_device *pdev)
.div_factor = 3,
};
+static const struct meson_i2c_data i2c_g12a_data = {
+ .div_factor = 3,
Especially if the div_factor is the same as AXG.
If you have some other fixes for G12a in the pipe, you will add the new
compatible and meson_i2c_data later,
for the div_factor, simply use the axg struct and compatible.
Neil
For axg and g12a SoC, the div_factor is the same, and I have confirmed
that they share the same IP. I prefer g12a uses axg's compatible and
data if it is reasonable. I will just submit the i2c controller node in
meson-g12a.dtsi.
+};
+
static const struct of_device_id meson_i2c_match[] = {
{ .compatible = "amlogic,meson6-i2c", .data = _meson6_data },
{ .compatible = "amlogic,meson-gxbb-i2c", .data = _gxbb_data },
{ .compatible = "amlogic,meson-axg-i2c", .data = _axg_data },
+ { .compatible = "amlogic,meson-g12a-i2c", .data = _g12a_data },
{},
};
.
Re: [PATCH 0/2] i2c: meson: add support for Meson G12A SoC i2c controller
On 2018/11/29 19:02, Jerome Brunet wrote:
On Thu, 2018-11-29 at 18:59 +0800, Jian Hu wrote:
1)Add G12A SoC i2c compatible string in dt-bindings.
2)Add compatible and data for G12A I2C controller driver.
Jian Hu (2):
dt-bindings: i2c: meson: add Meson G12A SoC i2c compatible string
i2c: meson: add support for Meson G12A SoC I2C controller
Looks to me that the g12a is compatible with the axg. What is the point of
adding this new compatible string ?
I am okay if it is reasonable below in file
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi. I2c controller node just
uses axg's compatible.
i2c0: i2c@1f000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1f000 0x0 0x20>;
interrupts = ;
clocks = < CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
If it is, I just submit the i2c controller node in meson-g12a.dtsi.
Documentation/devicetree/bindings/i2c/i2c-meson.txt | 1 +
drivers/i2c/busses/i2c-meson.c | 5 +
2 files changed, 6 insertions(+)
.
Re: [PATCH 0/2] i2c: meson: add support for Meson G12A SoC i2c controller
On 2018/11/29 19:02, Jerome Brunet wrote:
On Thu, 2018-11-29 at 18:59 +0800, Jian Hu wrote:
1)Add G12A SoC i2c compatible string in dt-bindings.
2)Add compatible and data for G12A I2C controller driver.
Jian Hu (2):
dt-bindings: i2c: meson: add Meson G12A SoC i2c compatible string
i2c: meson: add support for Meson G12A SoC I2C controller
Looks to me that the g12a is compatible with the axg. What is the point of
adding this new compatible string ?
I am okay if it is reasonable below in file
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi. I2c controller node just
uses axg's compatible.
i2c0: i2c@1f000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1f000 0x0 0x20>;
interrupts = ;
clocks = < CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
If it is, I just submit the i2c controller node in meson-g12a.dtsi.
Documentation/devicetree/bindings/i2c/i2c-meson.txt | 1 +
drivers/i2c/busses/i2c-meson.c | 5 +
2 files changed, 6 insertions(+)
.
[PATCH 0/2] i2c: meson: add support for Meson G12A SoC i2c controller
1)Add G12A SoC i2c compatible string in dt-bindings. 2)Add compatible and data for G12A I2C controller driver. Jian Hu (2): dt-bindings: i2c: meson: add Meson G12A SoC i2c compatible string i2c: meson: add support for Meson G12A SoC I2C controller Documentation/devicetree/bindings/i2c/i2c-meson.txt | 1 + drivers/i2c/busses/i2c-meson.c | 5 + 2 files changed, 6 insertions(+) -- 1.9.1
[PATCH 0/2] i2c: meson: add support for Meson G12A SoC i2c controller
1)Add G12A SoC i2c compatible string in dt-bindings. 2)Add compatible and data for G12A I2C controller driver. Jian Hu (2): dt-bindings: i2c: meson: add Meson G12A SoC i2c compatible string i2c: meson: add support for Meson G12A SoC I2C controller Documentation/devicetree/bindings/i2c/i2c-meson.txt | 1 + drivers/i2c/busses/i2c-meson.c | 5 + 2 files changed, 6 insertions(+) -- 1.9.1
[PATCH 1/2] dt-bindings: i2c: meson: add Meson G12A SoC i2c compatible string
Add Meson G12A SoC i2c controller compatible string Signed-off-by: Jian Hu --- Documentation/devicetree/bindings/i2c/i2c-meson.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-meson.txt b/Documentation/devicetree/bindings/i2c/i2c-meson.txt index 13d410d..795bc12 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-meson.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-meson.txt @@ -5,6 +5,7 @@ Required properties: "amlogic,meson6-i2c" for Meson8 and compatible SoCs "amlogic,meson-gxbb-i2c" for GXBB and compatible SoCs "amlogic,meson-axg-i2c"for AXG and compatible SoCs + "amlogic,meson-g12a-i2c" for G12A and compatible SoCs - reg: physical address and length of the device registers - interrupts: a single interrupt specifier -- 1.9.1
[PATCH 2/2] i2c: meson: add support for Meson G12A SoC I2C controller
Add compatible and data for G12A I2C controller.
Signed-off-by: Jian Hu
---
drivers/i2c/busses/i2c-meson.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
index 90f5d04..b86eed7 100644
--- a/drivers/i2c/busses/i2c-meson.c
+++ b/drivers/i2c/busses/i2c-meson.c
@@ -462,10 +462,15 @@ static int meson_i2c_remove(struct platform_device *pdev)
.div_factor = 3,
};
+static const struct meson_i2c_data i2c_g12a_data = {
+ .div_factor = 3,
+};
+
static const struct of_device_id meson_i2c_match[] = {
{ .compatible = "amlogic,meson6-i2c", .data = _meson6_data },
{ .compatible = "amlogic,meson-gxbb-i2c", .data = _gxbb_data },
{ .compatible = "amlogic,meson-axg-i2c", .data = _axg_data },
+ { .compatible = "amlogic,meson-g12a-i2c", .data = _g12a_data },
{},
};
--
1.9.1
[PATCH 1/2] dt-bindings: i2c: meson: add Meson G12A SoC i2c compatible string
Add Meson G12A SoC i2c controller compatible string Signed-off-by: Jian Hu --- Documentation/devicetree/bindings/i2c/i2c-meson.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-meson.txt b/Documentation/devicetree/bindings/i2c/i2c-meson.txt index 13d410d..795bc12 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-meson.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-meson.txt @@ -5,6 +5,7 @@ Required properties: "amlogic,meson6-i2c" for Meson8 and compatible SoCs "amlogic,meson-gxbb-i2c" for GXBB and compatible SoCs "amlogic,meson-axg-i2c"for AXG and compatible SoCs + "amlogic,meson-g12a-i2c" for G12A and compatible SoCs - reg: physical address and length of the device registers - interrupts: a single interrupt specifier -- 1.9.1
[PATCH 2/2] i2c: meson: add support for Meson G12A SoC I2C controller
Add compatible and data for G12A I2C controller.
Signed-off-by: Jian Hu
---
drivers/i2c/busses/i2c-meson.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
index 90f5d04..b86eed7 100644
--- a/drivers/i2c/busses/i2c-meson.c
+++ b/drivers/i2c/busses/i2c-meson.c
@@ -462,10 +462,15 @@ static int meson_i2c_remove(struct platform_device *pdev)
.div_factor = 3,
};
+static const struct meson_i2c_data i2c_g12a_data = {
+ .div_factor = 3,
+};
+
static const struct of_device_id meson_i2c_match[] = {
{ .compatible = "amlogic,meson6-i2c", .data = _meson6_data },
{ .compatible = "amlogic,meson-gxbb-i2c", .data = _gxbb_data },
{ .compatible = "amlogic,meson-axg-i2c", .data = _axg_data },
+ { .compatible = "amlogic,meson-g12a-i2c", .data = _g12a_data },
{},
};
--
1.9.1
Re: [PATCH v4 0/2] clk: meson-g12a: Add EE clock controller driver
Hi Jerome
On 2018/11/8 21:34, jbru...@baylibre.com wrote:
On Thu, 2018-11-08 at 21:15 +0800, Jian Hu wrote:
Changes since v3 at[4]
-add fixed clocks clk_regmap definition
Jian,
When replying to the v1 of your clk_ao patchset :
https://patchwork.kernel.org/patch/10562563/#22177627
I have explained that I would like to stop taking clock (such as xtal) from
nowhere. Clocks (even the xtal) should be properly claimed through DT.
I have specifically asked this to be taken into account for the EE controller.
If you need an exemple on how to get the input clock from DT to your
controller, please have look at the axg audio clock controller.
This comment does not appear to be addressed in this version.
Please make sure you have addressed all the comments of past reviews before
reposting
Thx
Thanks, I will resolve it, I want make sure for it.
I should take the "periphs_xtal" clock in ee g12a clock controller
driver through DT , And then I can get its clock name "xtal" by property
of clock-output-names. Is that right?
ee g12a clock dts:
hiubus: bus@ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x1c00>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
sysctrl: syscon@0 {
compatible =
"amlogic,meson-g12a-hhi-sysctrl", "simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x400>;
clkc: clock-controller {
compatible = "amlogic,g12a-clkc";
#clock-cells = <1>;
clocks = <>;
clock-name = "periphs_xtal";
};
};
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <2400>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
Changes since v2 at[2]
-fix fixed clocks's descriptions
-fix aligment
-add enable bit for plls base on [3] patches
-add fixed clock gate bit
Changes since v1 at[1]
-fix typo of 'Everything'.
-change the word 'AmLogic' to 'Amlogic'
-squash patch 1 and 2.
-delete usless message of "Trying obsolete regs".
-delete the empty line in include/dt-bindings/clock/g12a-clkc.h.
-rebase on top of the "next/drivers" branch, and add g12a clock patch.
-add CLK_MUX_ROUND_CLOSEST for g12a_sd_emmc_b_clk0_sel and
g12a_sd_emmc_c_clk0_sel.
[1]
https://lkml.kernel.org/r/1531133549-25806-2-git-send-email-jian...@amlogic.com
[2]
https://lkml.kernel.org/r/1531728707-192230-2-git-send-email-jian...@amlogic.com
[3]https://lkml.kernel.org/r/20180717095617.12240-1-jbru...@baylibre.com
[4]
https://lkml.kernel.org/r/1533890858-113020-1-git-send-email-jian...@amlogic.com
Jian Hu (2):
dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
clk: meson-g12a: Add EE Clock controller driver
.../bindings/clock/amlogic,gxbb-clkc.txt |1 +
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/g12a.c | 1134
drivers/clk/meson/g12a.h | 128 +++
include/dt-bindings/clock/g12a-clkc.h | 93 ++
6 files changed, 1367 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
create mode 100644 include/dt-bindings/clock/g12a-clkc.h
.
Re: [PATCH v4 0/2] clk: meson-g12a: Add EE clock controller driver
Hi Jerome
On 2018/11/8 21:34, jbru...@baylibre.com wrote:
On Thu, 2018-11-08 at 21:15 +0800, Jian Hu wrote:
Changes since v3 at[4]
-add fixed clocks clk_regmap definition
Jian,
When replying to the v1 of your clk_ao patchset :
https://patchwork.kernel.org/patch/10562563/#22177627
I have explained that I would like to stop taking clock (such as xtal) from
nowhere. Clocks (even the xtal) should be properly claimed through DT.
I have specifically asked this to be taken into account for the EE controller.
If you need an exemple on how to get the input clock from DT to your
controller, please have look at the axg audio clock controller.
This comment does not appear to be addressed in this version.
Please make sure you have addressed all the comments of past reviews before
reposting
Thx
Thanks, I will resolve it, I want make sure for it.
I should take the "periphs_xtal" clock in ee g12a clock controller
driver through DT , And then I can get its clock name "xtal" by property
of clock-output-names. Is that right?
ee g12a clock dts:
hiubus: bus@ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x1c00>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
sysctrl: syscon@0 {
compatible =
"amlogic,meson-g12a-hhi-sysctrl", "simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x400>;
clkc: clock-controller {
compatible = "amlogic,g12a-clkc";
#clock-cells = <1>;
clocks = <>;
clock-name = "periphs_xtal";
};
};
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <2400>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
Changes since v2 at[2]
-fix fixed clocks's descriptions
-fix aligment
-add enable bit for plls base on [3] patches
-add fixed clock gate bit
Changes since v1 at[1]
-fix typo of 'Everything'.
-change the word 'AmLogic' to 'Amlogic'
-squash patch 1 and 2.
-delete usless message of "Trying obsolete regs".
-delete the empty line in include/dt-bindings/clock/g12a-clkc.h.
-rebase on top of the "next/drivers" branch, and add g12a clock patch.
-add CLK_MUX_ROUND_CLOSEST for g12a_sd_emmc_b_clk0_sel and
g12a_sd_emmc_c_clk0_sel.
[1]
https://lkml.kernel.org/r/1531133549-25806-2-git-send-email-jian...@amlogic.com
[2]
https://lkml.kernel.org/r/1531728707-192230-2-git-send-email-jian...@amlogic.com
[3]https://lkml.kernel.org/r/20180717095617.12240-1-jbru...@baylibre.com
[4]
https://lkml.kernel.org/r/1533890858-113020-1-git-send-email-jian...@amlogic.com
Jian Hu (2):
dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
clk: meson-g12a: Add EE Clock controller driver
.../bindings/clock/amlogic,gxbb-clkc.txt |1 +
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/g12a.c | 1134
drivers/clk/meson/g12a.h | 128 +++
include/dt-bindings/clock/g12a-clkc.h | 93 ++
6 files changed, 1367 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
create mode 100644 include/dt-bindings/clock/g12a-clkc.h
.
[PATCH v4 0/2] clk: meson-g12a: Add EE clock controller driver
Changes since v3 at[4] -add fixed clocks clk_regmap definition Changes since v2 at[2] -fix fixed clocks's descriptions -fix aligment -add enable bit for plls base on [3] patches -add fixed clock gate bit Changes since v1 at[1] -fix typo of 'Everything'. -change the word 'AmLogic' to 'Amlogic' -squash patch 1 and 2. -delete usless message of "Trying obsolete regs". -delete the empty line in include/dt-bindings/clock/g12a-clkc.h. -rebase on top of the "next/drivers" branch, and add g12a clock patch. -add CLK_MUX_ROUND_CLOSEST for g12a_sd_emmc_b_clk0_sel and g12a_sd_emmc_c_clk0_sel. [1]https://lkml.kernel.org/r/1531133549-25806-2-git-send-email-jian...@amlogic.com [2]https://lkml.kernel.org/r/1531728707-192230-2-git-send-email-jian...@amlogic.com [3]https://lkml.kernel.org/r/20180717095617.12240-1-jbru...@baylibre.com [4]https://lkml.kernel.org/r/1533890858-113020-1-git-send-email-jian...@amlogic.com Jian Hu (2): dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings clk: meson-g12a: Add EE Clock controller driver .../bindings/clock/amlogic,gxbb-clkc.txt |1 + drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile |1 + drivers/clk/meson/g12a.c | 1134 drivers/clk/meson/g12a.h | 128 +++ include/dt-bindings/clock/g12a-clkc.h | 93 ++ 6 files changed, 1367 insertions(+) create mode 100644 drivers/clk/meson/g12a.c create mode 100644 drivers/clk/meson/g12a.h create mode 100644 include/dt-bindings/clock/g12a-clkc.h -- 1.9.1
[PATCH v4 1/2] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
Add new clock controller compatible and dt-bingdings headers for the Everything-Else domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-clkc.txt | 1 + include/dt-bindings/clock/g12a-clkc.h | 93 ++ 2 files changed, 94 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599..0833006 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,7 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. + "amlogic,g12a-clkc" for G12A SoC. - #clock-cells: should be 1. diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 000..b55e6e1 --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL1 +#define CLKID_FCLK_DIV22 +#define CLKID_FCLK_DIV33 +#define CLKID_FCLK_DIV44 +#define CLKID_FCLK_DIV55 +#define CLKID_FCLK_DIV76 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK8110 +#define CLKID_MPLL011 +#define CLKID_MPLL112 +#define CLKID_MPLL213 +#define CLKID_MPLL314 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL30121 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART028 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A33 +#define CLKID_SD_EMMC_B34 +#define CLKID_SD_EMMC_C35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO37 +#define CLKID_ETH 38 +#define CLKID_DEMUX39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART142 +#define CLKID_G2D 43 +#define CLKID_RESET44 +#define CLKID_PCIE_COMB45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT65654 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART257 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_B_CLK0 60 +#define CLKID_SD_EMMC_C_CLK0 61 +#define CLKID_HIFI_PLL 71 +#define CLKID_VCLK2_VENCI0 77 +#define CLKID_VCLK2_VENCI1 78 +#define CLKID_VCLK2_VENCP0 79 +#define CLKID_VCLK2_VENCP1 80 +#define CLKID_VCLK2_VENCT0 81 +#define CLKID_VCLK2_VENCT1 82 +#define CLKID_VCLK2_OTHER 83 +#define CLKID_VCLK2_ENCI
[PATCH v4 0/2] clk: meson-g12a: Add EE clock controller driver
Changes since v3 at[4] -add fixed clocks clk_regmap definition Changes since v2 at[2] -fix fixed clocks's descriptions -fix aligment -add enable bit for plls base on [3] patches -add fixed clock gate bit Changes since v1 at[1] -fix typo of 'Everything'. -change the word 'AmLogic' to 'Amlogic' -squash patch 1 and 2. -delete usless message of "Trying obsolete regs". -delete the empty line in include/dt-bindings/clock/g12a-clkc.h. -rebase on top of the "next/drivers" branch, and add g12a clock patch. -add CLK_MUX_ROUND_CLOSEST for g12a_sd_emmc_b_clk0_sel and g12a_sd_emmc_c_clk0_sel. [1]https://lkml.kernel.org/r/1531133549-25806-2-git-send-email-jian...@amlogic.com [2]https://lkml.kernel.org/r/1531728707-192230-2-git-send-email-jian...@amlogic.com [3]https://lkml.kernel.org/r/20180717095617.12240-1-jbru...@baylibre.com [4]https://lkml.kernel.org/r/1533890858-113020-1-git-send-email-jian...@amlogic.com Jian Hu (2): dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings clk: meson-g12a: Add EE Clock controller driver .../bindings/clock/amlogic,gxbb-clkc.txt |1 + drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile |1 + drivers/clk/meson/g12a.c | 1134 drivers/clk/meson/g12a.h | 128 +++ include/dt-bindings/clock/g12a-clkc.h | 93 ++ 6 files changed, 1367 insertions(+) create mode 100644 drivers/clk/meson/g12a.c create mode 100644 drivers/clk/meson/g12a.h create mode 100644 include/dt-bindings/clock/g12a-clkc.h -- 1.9.1
[PATCH v4 1/2] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
Add new clock controller compatible and dt-bingdings headers for the Everything-Else domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-clkc.txt | 1 + include/dt-bindings/clock/g12a-clkc.h | 93 ++ 2 files changed, 94 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599..0833006 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,7 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. + "amlogic,g12a-clkc" for G12A SoC. - #clock-cells: should be 1. diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 000..b55e6e1 --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL1 +#define CLKID_FCLK_DIV22 +#define CLKID_FCLK_DIV33 +#define CLKID_FCLK_DIV44 +#define CLKID_FCLK_DIV55 +#define CLKID_FCLK_DIV76 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK8110 +#define CLKID_MPLL011 +#define CLKID_MPLL112 +#define CLKID_MPLL213 +#define CLKID_MPLL314 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL30121 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART028 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A33 +#define CLKID_SD_EMMC_B34 +#define CLKID_SD_EMMC_C35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO37 +#define CLKID_ETH 38 +#define CLKID_DEMUX39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART142 +#define CLKID_G2D 43 +#define CLKID_RESET44 +#define CLKID_PCIE_COMB45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT65654 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART257 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_B_CLK0 60 +#define CLKID_SD_EMMC_C_CLK0 61 +#define CLKID_HIFI_PLL 71 +#define CLKID_VCLK2_VENCI0 77 +#define CLKID_VCLK2_VENCI1 78 +#define CLKID_VCLK2_VENCP0 79 +#define CLKID_VCLK2_VENCP1 80 +#define CLKID_VCLK2_VENCT0 81 +#define CLKID_VCLK2_VENCT1 82 +#define CLKID_VCLK2_OTHER 83 +#define CLKID_VCLK2_ENCI
[PATCH v4 2/2] clk: meson-g12a: Add EE Clock controller driver
Add a Clock driver for the Everything-Else part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/g12a.c | 1134
drivers/clk/meson/g12a.h | 128 +
4 files changed, 1273 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f..16edad8 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -54,3 +54,13 @@ config COMMON_CLK_AXG_AUDIO
help
Support for the audio clock controller on AmLogic A113D devices,
aka axg, Say Y if you want audio subsystem to work.
+
+config COMMON_CLK_G12A
+ bool
+ depends on COMMON_CLK_AMLOGIC
+ select RESET_CONTROLLER
+ select COMMON_CLK_REGMAP_MESON
+ select MFD_SYSCON
+ help
+ Support for the clock controller on Amlogic S905D2 devices, aka g12a.
+ Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c4..2b1a562 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 000..84df081
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,1134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai
+ * Author: Jian Hu
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "g12a.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap g12a_fixed_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = HHI_FIX_PLL_CNTL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll_dco",
+ .ops = _clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap g12a_fixed_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_FIX_PLL_CNTL0,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = _regmap_divider_ro_ops,
+ .parent_names = (const char *[]){ "fixed_pll_dco" },
+ .num_parents = 1,
+ /*
+* This clock won't ever change at runtime so
+* CLK_SET_RATE_PARENT is not required
+*/
+ },
+};
+
+static const struct reg_sequence g12a_sys_init_regs[] = {
+ { .reg = HHI_SYS_PLL_CNTL1, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL2, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
+ { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
+ { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
+ { .reg = HHI_SYS_PLL_CNTL6, .def = 0x5654 },
+};
+
+static struct clk_regmap g12a_sys_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+ .shift =
[PATCH v4 2/2] clk: meson-g12a: Add EE Clock controller driver
Add a Clock driver for the Everything-Else part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile |1 +
drivers/clk/meson/g12a.c | 1134
drivers/clk/meson/g12a.h | 128 +
4 files changed, 1273 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f..16edad8 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -54,3 +54,13 @@ config COMMON_CLK_AXG_AUDIO
help
Support for the audio clock controller on AmLogic A113D devices,
aka axg, Say Y if you want audio subsystem to work.
+
+config COMMON_CLK_G12A
+ bool
+ depends on COMMON_CLK_AMLOGIC
+ select RESET_CONTROLLER
+ select COMMON_CLK_REGMAP_MESON
+ select MFD_SYSCON
+ help
+ Support for the clock controller on Amlogic S905D2 devices, aka g12a.
+ Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c4..2b1a562 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 000..84df081
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,1134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai
+ * Author: Jian Hu
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "g12a.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap g12a_fixed_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = HHI_FIX_PLL_CNTL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll_dco",
+ .ops = _clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap g12a_fixed_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_FIX_PLL_CNTL0,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = _regmap_divider_ro_ops,
+ .parent_names = (const char *[]){ "fixed_pll_dco" },
+ .num_parents = 1,
+ /*
+* This clock won't ever change at runtime so
+* CLK_SET_RATE_PARENT is not required
+*/
+ },
+};
+
+static const struct reg_sequence g12a_sys_init_regs[] = {
+ { .reg = HHI_SYS_PLL_CNTL1, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL2, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
+ { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
+ { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
+ { .reg = HHI_SYS_PLL_CNTL6, .def = 0x5654 },
+};
+
+static struct clk_regmap g12a_sys_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+ .shift =
Re: [PATCH 2/2] clk: meson-g12a: Add AO Clock controller driver
Hi: Jerome On 2018/8/27 21:07, Jerome Brunet wrote: On Fri, 2018-08-24 at 21:34 +0800, Jian Hu wrote: I am confued about aoclk81's parent clocks. I can not get the example of axg audio clock driver, Could you provide the link? Had it merged into clk-meson.git? Yes and mainline as well : drivers/clk/meson/axg-audio.c Basically this driver is creating bypass input clocks (audio_pclk, mst_in[0-9], etc...) . This allows to collect input clocks from DT (like any consumer should) will keeping constant in the controller clock tree. From what I've seen of your controller drivers, the EE controller should have one input, the AO should have 3. . I still can not get the example meaning in axg audio driver. In 26 page of A113D_Datasheet V0.7 20170725-Baylibre.pdf,We can see the aoclk81 has two parents. clk81 and ao_slow_clk. I can not get 3 parents. clk81|\ ---| \aoclk81 src0 |\ | |--- -| \ ao_slow_clk | | | |-| / -| / |/ src1|/ src0 is from xtal, if can generate 32k clock, but it is never used. src1 is from gpio clock, It is never used. If necessary， the ao_slow_clk maybe described. So why aoclk81 has 3 parents?
Re: [PATCH 2/2] clk: meson-g12a: Add AO Clock controller driver
Hi: Jerome On 2018/8/27 21:07, Jerome Brunet wrote: On Fri, 2018-08-24 at 21:34 +0800, Jian Hu wrote: I am confued about aoclk81's parent clocks. I can not get the example of axg audio clock driver, Could you provide the link? Had it merged into clk-meson.git? Yes and mainline as well : drivers/clk/meson/axg-audio.c Basically this driver is creating bypass input clocks (audio_pclk, mst_in[0-9], etc...) . This allows to collect input clocks from DT (like any consumer should) will keeping constant in the controller clock tree. From what I've seen of your controller drivers, the EE controller should have one input, the AO should have 3. . I still can not get the example meaning in axg audio driver. In 26 page of A113D_Datasheet V0.7 20170725-Baylibre.pdf,We can see the aoclk81 has two parents. clk81 and ao_slow_clk. I can not get 3 parents. clk81|\ ---| \aoclk81 src0 |\ | |--- -| \ ao_slow_clk | | | |-| / -| / |/ src1|/ src0 is from xtal, if can generate 32k clock, but it is never used. src1 is from gpio clock, It is never used. If necessary， the ao_slow_clk maybe described. So why aoclk81 has 3 parents?
Re: [PATCH 2/2] clk: meson-g12a: Add AO Clock controller driver
Hi: Jerome
Please see my commits.
On 2018/8/14 20:40, Jerome Brunet wrote:
On Fri, 2018-08-10 at 17:54 +0800, Jian Hu wrote:
Add a Clock driver for the ALways-On part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/g12a-aoclk.c | 170 +
drivers/clk/meson/g12a-aoclk.h | 36 +
3 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/meson/g12a-aoclk.c
create mode 100644 drivers/clk/meson/g12a-aoclk.h
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 2b1a562..d5c2dcd 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,5 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO)+= axg-audio.o
-obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.c
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
new file mode 100644
index 000..a5cd95c
--- /dev/null
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Jian Hu
+ */
+#include
+#include
+#include
+#include
+#include
+#include "clkc.h"
+#include "g12a-aoclk.h"
+
+#define G12A_AO_GATE0(_name, _bit) \
+static struct clk_regmap _name##_ao = {
\
+ .data = &(struct clk_regmap_gate_data) {\
+ .offset = (AO_CLK_GATE0), \
+ .bit_idx = (_bit), \
+ }, \
+ .hw.init = &(struct clk_init_data) {\
+ .name = #_name "_ao", \
+ .ops = _regmap_gate_ops,\
+ .parent_names = (const char *[]){ "clk81" }, \
+ .num_parents = 1, \
+ }, \
+}
+
+G12A_AO_GATE0(ahb_bus, 0);
+G12A_AO_GATE0(remote, 1);
+G12A_AO_GATE0(i2c_master, 2);
+G12A_AO_GATE0(i2c_slave, 3);
+G12A_AO_GATE0(uart1, 4);
+G12A_AO_GATE0(prod_i2c,5);
+G12A_AO_GATE0(uart2, 6);
+G12A_AO_GATE0(ir_blaster, 7);
+G12A_AO_GATE0(saradc, 8);
+
+static struct clk_regmap ao_clk81 = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = AO_RTI_PWR_CNTL_REG0,
+ .mask = 0x1,
+ .shift = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ao_clk81",
+ .ops = _regmap_mux_ro_ops,
+ .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
I think it is time we stop taking clock input from nowhere.
With the addition of the axg audio clock controller, there is now an example of
how do so.
This clock controller apparently has 3 inputs:
* xtal
* ao_xtal
* clk_81
I'd like to see that appear this DT bindings and the probe function
Same goes for the EE controller which should only take the xtal.
I am confued about aoclk81's parent clocks.
I can not get the example of axg audio clock driver, Could you provide
the link? Had it merged into clk-meson.git?
my local latest commit is:
commit cd2b3132bd7e84dc6a739fef73e5b5c3f2b3a0bb
Author: Jerome Brunet
Date: Wed Aug 1 16:00:53 2018 +0200
clk: meson: clk-pll: drop hard-coded rates from pll tables
Putting hard-coded rates inside the parameter tables assumes that
the parent is known and will never change. That's a big assumption
we should not make.
We have everything we need to recalculate the output rate using
the parent rate and the rest of the parameters. Let's do so and
drop the rates from the tables.
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap g12a_saradc_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = AO_SAR_CLK,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "g12a_saradc_mux",
+ .ops = _regmap_mux_ops,
+ .parent_names = (const char *[]){ "xtal", "ao_clk81" },
+ .
Re: [PATCH 2/2] clk: meson-g12a: Add AO Clock controller driver
Hi: Jerome
Please see my commits.
On 2018/8/14 20:40, Jerome Brunet wrote:
On Fri, 2018-08-10 at 17:54 +0800, Jian Hu wrote:
Add a Clock driver for the ALways-On part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/g12a-aoclk.c | 170 +
drivers/clk/meson/g12a-aoclk.h | 36 +
3 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/meson/g12a-aoclk.c
create mode 100644 drivers/clk/meson/g12a-aoclk.h
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 2b1a562..d5c2dcd 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,5 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO)+= axg-audio.o
-obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.c
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
new file mode 100644
index 000..a5cd95c
--- /dev/null
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Jian Hu
+ */
+#include
+#include
+#include
+#include
+#include
+#include "clkc.h"
+#include "g12a-aoclk.h"
+
+#define G12A_AO_GATE0(_name, _bit) \
+static struct clk_regmap _name##_ao = {
\
+ .data = &(struct clk_regmap_gate_data) {\
+ .offset = (AO_CLK_GATE0), \
+ .bit_idx = (_bit), \
+ }, \
+ .hw.init = &(struct clk_init_data) {\
+ .name = #_name "_ao", \
+ .ops = _regmap_gate_ops,\
+ .parent_names = (const char *[]){ "clk81" }, \
+ .num_parents = 1, \
+ }, \
+}
+
+G12A_AO_GATE0(ahb_bus, 0);
+G12A_AO_GATE0(remote, 1);
+G12A_AO_GATE0(i2c_master, 2);
+G12A_AO_GATE0(i2c_slave, 3);
+G12A_AO_GATE0(uart1, 4);
+G12A_AO_GATE0(prod_i2c,5);
+G12A_AO_GATE0(uart2, 6);
+G12A_AO_GATE0(ir_blaster, 7);
+G12A_AO_GATE0(saradc, 8);
+
+static struct clk_regmap ao_clk81 = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = AO_RTI_PWR_CNTL_REG0,
+ .mask = 0x1,
+ .shift = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ao_clk81",
+ .ops = _regmap_mux_ro_ops,
+ .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
I think it is time we stop taking clock input from nowhere.
With the addition of the axg audio clock controller, there is now an example of
how do so.
This clock controller apparently has 3 inputs:
* xtal
* ao_xtal
* clk_81
I'd like to see that appear this DT bindings and the probe function
Same goes for the EE controller which should only take the xtal.
I am confued about aoclk81's parent clocks.
I can not get the example of axg audio clock driver, Could you provide
the link? Had it merged into clk-meson.git?
my local latest commit is:
commit cd2b3132bd7e84dc6a739fef73e5b5c3f2b3a0bb
Author: Jerome Brunet
Date: Wed Aug 1 16:00:53 2018 +0200
clk: meson: clk-pll: drop hard-coded rates from pll tables
Putting hard-coded rates inside the parameter tables assumes that
the parent is known and will never change. That's a big assumption
we should not make.
We have everything we need to recalculate the output rate using
the parent rate and the rest of the parameters. Let's do so and
drop the rates from the tables.
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap g12a_saradc_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = AO_SAR_CLK,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "g12a_saradc_mux",
+ .ops = _regmap_mux_ops,
+ .parent_names = (const char *[]){ "xtal", "ao_clk81" },
+ .
Re: [PATCH 1/2] dt-bindings: clk: meson-g12a: Add G12A AO Clock Bindings
On 2018/8/15 4:48, Rob Herring wrote: On Fri, Aug 10, 2018 at 05:54:27PM +0800, Jian Hu wrote: Add new clock controller compatible and dt-bingdings headers for the Always-On domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + include/dt-bindings/clock/g12a-aoclkc.h| 28 ++ 2 files changed, 29 insertions(+) create mode 100755 include/dt-bindings/clock/g12a-aoclkc.h checkpatch says wrong mode. Yes, I have checked the g12a-aoclk.h file,It is wrong mode. I will chmod a-x for it.Thank you for review. diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 3a88052..6f02288 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -10,6 +10,7 @@ Required Properties: - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" + - G12A (S905D2, S905X2) : "amlogic,g12a-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" - #clock-cells: should be 1. diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h new file mode 100755 index 000..6b3f921 --- /dev/null +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Jian Hu + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK + +#define CLKID_AO_AHB_BUS 0 +#define CLKID_AO_REMOTE1 +#define CLKID_AO_I2C_MASTER2 +#define CLKID_AO_I2C_SLAVE 3 +#define CLKID_AO_UART1 4 +#define CLKID_AO_PROD_I2C 5 +#define CLKID_AO_UART2 6 +#define CLKID_AO_IR_BLASTER7 +#define CLKID_AO_SAR_ADC 8 +#define CLKID_AO_CLK81 9 +#define CLKID_AO_SAR_ADC_SEL 10 +#define CLKID_AO_SAR_ADC_DIV 11 +#define CLKID_AO_SAR_ADC_CLK 12 +#define CLKID_AO_ALT_XTAL 13 + +#endif -- 1.9.1 .
Re: [PATCH 1/2] dt-bindings: clk: meson-g12a: Add G12A AO Clock Bindings
On 2018/8/15 4:48, Rob Herring wrote: On Fri, Aug 10, 2018 at 05:54:27PM +0800, Jian Hu wrote: Add new clock controller compatible and dt-bingdings headers for the Always-On domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + include/dt-bindings/clock/g12a-aoclkc.h| 28 ++ 2 files changed, 29 insertions(+) create mode 100755 include/dt-bindings/clock/g12a-aoclkc.h checkpatch says wrong mode. Yes, I have checked the g12a-aoclk.h file,It is wrong mode. I will chmod a-x for it.Thank you for review. diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 3a88052..6f02288 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -10,6 +10,7 @@ Required Properties: - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" + - G12A (S905D2, S905X2) : "amlogic,g12a-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" - #clock-cells: should be 1. diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h new file mode 100755 index 000..6b3f921 --- /dev/null +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Jian Hu + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK + +#define CLKID_AO_AHB_BUS 0 +#define CLKID_AO_REMOTE1 +#define CLKID_AO_I2C_MASTER2 +#define CLKID_AO_I2C_SLAVE 3 +#define CLKID_AO_UART1 4 +#define CLKID_AO_PROD_I2C 5 +#define CLKID_AO_UART2 6 +#define CLKID_AO_IR_BLASTER7 +#define CLKID_AO_SAR_ADC 8 +#define CLKID_AO_CLK81 9 +#define CLKID_AO_SAR_ADC_SEL 10 +#define CLKID_AO_SAR_ADC_DIV 11 +#define CLKID_AO_SAR_ADC_CLK 12 +#define CLKID_AO_ALT_XTAL 13 + +#endif -- 1.9.1 .
[PATCH 0/2] clk: meson-g12a: Add AO clock controller driver
Add a Clock driver for Always-On part of the Amlogic Meson-G12A SoC. -The patch depends on "clk: meson-g12a: Add EE clock controller driver" patch [1] the parent clock of ao_clk81 is clk81 clock which provided in EE controller driver; the file of Makefile modify based on EE controller driver patch. [1]https://lkml.kernel.org/r/1533890858-113020-3-git-send-email-jian...@amlogic.com Jian Hu (2): dt-bindings: clk: meson-g12a: Add G12A AO Clock Bindings clk: meson-g12a: Add AO Clock controller driver .../bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/g12a-aoclk.c | 170 + drivers/clk/meson/g12a-aoclk.h | 36 + include/dt-bindings/clock/g12a-aoclkc.h| 28 5 files changed, 236 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/g12a-aoclk.c create mode 100644 drivers/clk/meson/g12a-aoclk.h create mode 100755 include/dt-bindings/clock/g12a-aoclkc.h -- 1.9.1
[PATCH 0/2] clk: meson-g12a: Add AO clock controller driver
Add a Clock driver for Always-On part of the Amlogic Meson-G12A SoC. -The patch depends on "clk: meson-g12a: Add EE clock controller driver" patch [1] the parent clock of ao_clk81 is clk81 clock which provided in EE controller driver; the file of Makefile modify based on EE controller driver patch. [1]https://lkml.kernel.org/r/1533890858-113020-3-git-send-email-jian...@amlogic.com Jian Hu (2): dt-bindings: clk: meson-g12a: Add G12A AO Clock Bindings clk: meson-g12a: Add AO Clock controller driver .../bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/g12a-aoclk.c | 170 + drivers/clk/meson/g12a-aoclk.h | 36 + include/dt-bindings/clock/g12a-aoclkc.h| 28 5 files changed, 236 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/g12a-aoclk.c create mode 100644 drivers/clk/meson/g12a-aoclk.h create mode 100755 include/dt-bindings/clock/g12a-aoclkc.h -- 1.9.1
[PATCH 2/2] clk: meson-g12a: Add AO Clock controller driver
Add a Clock driver for the ALways-On part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/g12a-aoclk.c | 170 +
drivers/clk/meson/g12a-aoclk.h | 36 +
3 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/meson/g12a-aoclk.c
create mode 100644 drivers/clk/meson/g12a-aoclk.h
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 2b1a562..d5c2dcd 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,5 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
-obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.c
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
new file mode 100644
index 000..a5cd95c
--- /dev/null
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Jian Hu
+ */
+#include
+#include
+#include
+#include
+#include
+#include "clkc.h"
+#include "g12a-aoclk.h"
+
+#define G12A_AO_GATE0(_name, _bit) \
+static struct clk_regmap _name##_ao = {
\
+ .data = &(struct clk_regmap_gate_data) {\
+ .offset = (AO_CLK_GATE0), \
+ .bit_idx = (_bit), \
+ }, \
+ .hw.init = &(struct clk_init_data) {\
+ .name = #_name "_ao", \
+ .ops = _regmap_gate_ops,\
+ .parent_names = (const char *[]){ "clk81" },\
+ .num_parents = 1, \
+ }, \
+}
+
+G12A_AO_GATE0(ahb_bus, 0);
+G12A_AO_GATE0(remote, 1);
+G12A_AO_GATE0(i2c_master, 2);
+G12A_AO_GATE0(i2c_slave, 3);
+G12A_AO_GATE0(uart1, 4);
+G12A_AO_GATE0(prod_i2c,5);
+G12A_AO_GATE0(uart2, 6);
+G12A_AO_GATE0(ir_blaster, 7);
+G12A_AO_GATE0(saradc, 8);
+
+static struct clk_regmap ao_clk81 = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = AO_RTI_PWR_CNTL_REG0,
+ .mask = 0x1,
+ .shift = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ao_clk81",
+ .ops = _regmap_mux_ro_ops,
+ .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap g12a_saradc_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = AO_SAR_CLK,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "g12a_saradc_mux",
+ .ops = _regmap_mux_ops,
+ .parent_names = (const char *[]){ "xtal", "ao_clk81" },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap g12a_saradc_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = AO_SAR_CLK,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "g12a_saradc_div",
+ .ops = _regmap_divider_ops,
+ .parent_names = (const char *[]){ "g12a_saradc_mux" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap g12a_saradc_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = AO_SAR_CLK,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "g12a_saradc_gate",
+ .ops = _regmap_gate_ops,
+ .parent_names = (const char *[]){ "g12a_saradc_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static unsigned int g12a_aoclk_reset[] = {
+ [RESET_AO_REMOTE] = 16,
+ [RESET_AO_UART1] = 17,
+ [RESET_AO_I2C_MASTER] = 18,
+ [RESET_AO_I2C_SLAVE] = 19,
+ [RESET_AO_SARADC]
[PATCH 2/2] clk: meson-g12a: Add AO Clock controller driver
Add a Clock driver for the ALways-On part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/g12a-aoclk.c | 170 +
drivers/clk/meson/g12a-aoclk.h | 36 +
3 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/meson/g12a-aoclk.c
create mode 100644 drivers/clk/meson/g12a-aoclk.h
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 2b1a562..d5c2dcd 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,5 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
-obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.c
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
new file mode 100644
index 000..a5cd95c
--- /dev/null
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Jian Hu
+ */
+#include
+#include
+#include
+#include
+#include
+#include "clkc.h"
+#include "g12a-aoclk.h"
+
+#define G12A_AO_GATE0(_name, _bit) \
+static struct clk_regmap _name##_ao = {
\
+ .data = &(struct clk_regmap_gate_data) {\
+ .offset = (AO_CLK_GATE0), \
+ .bit_idx = (_bit), \
+ }, \
+ .hw.init = &(struct clk_init_data) {\
+ .name = #_name "_ao", \
+ .ops = _regmap_gate_ops,\
+ .parent_names = (const char *[]){ "clk81" },\
+ .num_parents = 1, \
+ }, \
+}
+
+G12A_AO_GATE0(ahb_bus, 0);
+G12A_AO_GATE0(remote, 1);
+G12A_AO_GATE0(i2c_master, 2);
+G12A_AO_GATE0(i2c_slave, 3);
+G12A_AO_GATE0(uart1, 4);
+G12A_AO_GATE0(prod_i2c,5);
+G12A_AO_GATE0(uart2, 6);
+G12A_AO_GATE0(ir_blaster, 7);
+G12A_AO_GATE0(saradc, 8);
+
+static struct clk_regmap ao_clk81 = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = AO_RTI_PWR_CNTL_REG0,
+ .mask = 0x1,
+ .shift = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ao_clk81",
+ .ops = _regmap_mux_ro_ops,
+ .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap g12a_saradc_mux = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = AO_SAR_CLK,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "g12a_saradc_mux",
+ .ops = _regmap_mux_ops,
+ .parent_names = (const char *[]){ "xtal", "ao_clk81" },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap g12a_saradc_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = AO_SAR_CLK,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "g12a_saradc_div",
+ .ops = _regmap_divider_ops,
+ .parent_names = (const char *[]){ "g12a_saradc_mux" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap g12a_saradc_gate = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = AO_SAR_CLK,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "g12a_saradc_gate",
+ .ops = _regmap_gate_ops,
+ .parent_names = (const char *[]){ "g12a_saradc_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static unsigned int g12a_aoclk_reset[] = {
+ [RESET_AO_REMOTE] = 16,
+ [RESET_AO_UART1] = 17,
+ [RESET_AO_I2C_MASTER] = 18,
+ [RESET_AO_I2C_SLAVE] = 19,
+ [RESET_AO_SARADC]
[PATCH 1/2] dt-bindings: clk: meson-g12a: Add G12A AO Clock Bindings
Add new clock controller compatible and dt-bingdings headers for the Always-On domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + include/dt-bindings/clock/g12a-aoclkc.h| 28 ++ 2 files changed, 29 insertions(+) create mode 100755 include/dt-bindings/clock/g12a-aoclkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 3a88052..6f02288 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -10,6 +10,7 @@ Required Properties: - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" + - G12A (S905D2, S905X2) : "amlogic,g12a-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" - #clock-cells: should be 1. diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h new file mode 100755 index 000..6b3f921 --- /dev/null +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Jian Hu + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK + +#define CLKID_AO_AHB_BUS 0 +#define CLKID_AO_REMOTE1 +#define CLKID_AO_I2C_MASTER2 +#define CLKID_AO_I2C_SLAVE 3 +#define CLKID_AO_UART1 4 +#define CLKID_AO_PROD_I2C 5 +#define CLKID_AO_UART2 6 +#define CLKID_AO_IR_BLASTER7 +#define CLKID_AO_SAR_ADC 8 +#define CLKID_AO_CLK81 9 +#define CLKID_AO_SAR_ADC_SEL 10 +#define CLKID_AO_SAR_ADC_DIV 11 +#define CLKID_AO_SAR_ADC_CLK 12 +#define CLKID_AO_ALT_XTAL 13 + +#endif -- 1.9.1
[PATCH 1/2] dt-bindings: clk: meson-g12a: Add G12A AO Clock Bindings
Add new clock controller compatible and dt-bingdings headers for the Always-On domain of the g12a SoC Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + include/dt-bindings/clock/g12a-aoclkc.h| 28 ++ 2 files changed, 29 insertions(+) create mode 100755 include/dt-bindings/clock/g12a-aoclkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 3a88052..6f02288 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -10,6 +10,7 @@ Required Properties: - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" + - G12A (S905D2, S905X2) : "amlogic,g12a-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" - #clock-cells: should be 1. diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h new file mode 100755 index 000..6b3f921 --- /dev/null +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Jian Hu + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK + +#define CLKID_AO_AHB_BUS 0 +#define CLKID_AO_REMOTE1 +#define CLKID_AO_I2C_MASTER2 +#define CLKID_AO_I2C_SLAVE 3 +#define CLKID_AO_UART1 4 +#define CLKID_AO_PROD_I2C 5 +#define CLKID_AO_UART2 6 +#define CLKID_AO_IR_BLASTER7 +#define CLKID_AO_SAR_ADC 8 +#define CLKID_AO_CLK81 9 +#define CLKID_AO_SAR_ADC_SEL 10 +#define CLKID_AO_SAR_ADC_DIV 11 +#define CLKID_AO_SAR_ADC_CLK 12 +#define CLKID_AO_ALT_XTAL 13 + +#endif -- 1.9.1
Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver
Hi Jerome
On 2018/7/11 21:45, Jerome Brunet wrote:
On Wed, 2018-07-11 at 21:41 +0800, Jian Hu wrote:
+static struct clk_regmap g12a_mpll0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL1,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+ .ops = _regmap_gate_ops,
+ .parent_names = (const char *[]){ "mpll0_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
The previous had a predivider (1 or 2) in front of these mpll. Even if the
predivider is usually set to be a passthrough, it is better to model the tree
correctly.
Is this SoC any different ?
I am not sure the difference, I will confirm with IC design guys.
I suggest that you have a look at the (upstream) axg and gxbb clock driver for
this
Same goes for the fdiv gates.
Last, please trim your replies a bit. It will make easier to see what you are
replying to.
.
I have confirmed with IC design guys, axg and gxbb clock driver have a
prediver in frount of these mpll, according to the Spec, we can get the
prediver function in HHI_MPLL_CNTL5 bit12, the G12A SoC have not the
prediver function.
Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver
Hi Jerome
On 2018/7/11 21:45, Jerome Brunet wrote:
On Wed, 2018-07-11 at 21:41 +0800, Jian Hu wrote:
+static struct clk_regmap g12a_mpll0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MPLL_CNTL1,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+ .ops = _regmap_gate_ops,
+ .parent_names = (const char *[]){ "mpll0_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
The previous had a predivider (1 or 2) in front of these mpll. Even if the
predivider is usually set to be a passthrough, it is better to model the tree
correctly.
Is this SoC any different ?
I am not sure the difference, I will confirm with IC design guys.
I suggest that you have a look at the (upstream) axg and gxbb clock driver for
this
Same goes for the fdiv gates.
Last, please trim your replies a bit. It will make easier to see what you are
replying to.
.
I have confirmed with IC design guys, axg and gxbb clock driver have a
prediver in frount of these mpll, according to the Spec, we can get the
prediver function in HHI_MPLL_CNTL5 bit12, the G12A SoC have not the
prediver function.
Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver
On 2018/7/10 17:54, Jerome Brunet wrote:
On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
HI Martin
On 07/10/18 05:53, Martin Blumenstingl wrote:
On Mon, Jul 9, 2018 at 1:14 PM Jian Hu wrote:
Add a Clock driver for the Everyting-Else part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
This patch does not apply against g...@github.com:BayLibre/clk-meson.git
Please rebase on top of the "next/drivers" branch.
Also please review the Kconfig part as changes have happened there.
Ok， I have gotted the code.
---
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/g12a.c | 992 +
drivers/clk/meson/g12a.h | 123 ++
4 files changed, 1126 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec5..94a82f73 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -36,3 +36,13 @@ config COMMON_CLK_AXG
help
Support for the clock controller on AmLogic A113D devices, aka axg.
Say Y if you want peripherals and CPU frequency scaling to work.
+
+config COMMON_CLK_G12A
+ bool
+ depends on COMMON_CLK_AMLOGIC
+ select RESET_CONTROLLER
+ select COMMON_CLK_REGMAP_MESON
+ select MFD_SYSCON
+ help
+ Support for the clock controller on AmLogic U400 devices, aka g12a.
I suppose U400 is the designation of the ref design board, not the SoC, right ?
If this is case, please provide the SoC reference instead.
U400 is the development board name.G12A is the SoC series name，the same
with GXL/GXL/AXG
+ Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index fa6d1e3..45d107c 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o
clk-audio-divider.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o meson-aoclk.o gxbb-aoclk.o
gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o meson-aoclk.o axg-aoclk.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 000..3675697
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,992 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AmLogic Meson-G12A Clock Controller Driver
I thought you guys stopped writing amlogic with this camel case.
Please be consistent about it
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Jian Hu
+ * Author: Qiufang Dai
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "g12a.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap g12a_fixed_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .m = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 16,
+ .width = 2,
+ },
+ .frac = {
+ .reg_off = HHI_FIX_PLL_CNTL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = _clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ },
+};
+
+static const struct reg_sequence g12a_sys_init_regs[] = {
+ { .reg = HHI_SYS_PLL_CNTL1, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL2, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
+ { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
+ { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
+ { .reg = HHI_SYS_PLL_CNTL6, .def = 0x5654 },
+};
+
+static struct clk_regmap g12a_sys_pll = {
+
Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver
On 2018/7/10 17:54, Jerome Brunet wrote:
On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
HI Martin
On 07/10/18 05:53, Martin Blumenstingl wrote:
On Mon, Jul 9, 2018 at 1:14 PM Jian Hu wrote:
Add a Clock driver for the Everyting-Else part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
This patch does not apply against g...@github.com:BayLibre/clk-meson.git
Please rebase on top of the "next/drivers" branch.
Also please review the Kconfig part as changes have happened there.
Ok， I have gotted the code.
---
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/g12a.c | 992 +
drivers/clk/meson/g12a.h | 123 ++
4 files changed, 1126 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec5..94a82f73 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -36,3 +36,13 @@ config COMMON_CLK_AXG
help
Support for the clock controller on AmLogic A113D devices, aka axg.
Say Y if you want peripherals and CPU frequency scaling to work.
+
+config COMMON_CLK_G12A
+ bool
+ depends on COMMON_CLK_AMLOGIC
+ select RESET_CONTROLLER
+ select COMMON_CLK_REGMAP_MESON
+ select MFD_SYSCON
+ help
+ Support for the clock controller on AmLogic U400 devices, aka g12a.
I suppose U400 is the designation of the ref design board, not the SoC, right ?
If this is case, please provide the SoC reference instead.
U400 is the development board name.G12A is the SoC series name，the same
with GXL/GXL/AXG
+ Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index fa6d1e3..45d107c 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o
clk-audio-divider.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o meson-aoclk.o gxbb-aoclk.o
gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o meson-aoclk.o axg-aoclk.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 000..3675697
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,992 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AmLogic Meson-G12A Clock Controller Driver
I thought you guys stopped writing amlogic with this camel case.
Please be consistent about it
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Jian Hu
+ * Author: Qiufang Dai
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "g12a.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap g12a_fixed_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .m = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 16,
+ .width = 2,
+ },
+ .frac = {
+ .reg_off = HHI_FIX_PLL_CNTL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = _clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ },
+};
+
+static const struct reg_sequence g12a_sys_init_regs[] = {
+ { .reg = HHI_SYS_PLL_CNTL1, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL2, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
+ { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
+ { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
+ { .reg = HHI_SYS_PLL_CNTL6, .def = 0x5654 },
+};
+
+static struct clk_regmap g12a_sys_pll = {
+
Re: [PATCH 2/3] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
On 2018/7/10 17:26, Jerome Brunet wrote: On Tue, 2018-07-10 at 00:13 +0200, Martin Blumenstingl wrote: On Mon, Jul 9, 2018 at 1:13 PM Jian Hu wrote: Add dt-bindings headers for the Meson-G12A's Everything-Else part clock controller. I wonder if this should be folded into patch #1 along with an update to Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt so it's clear which header has to be used for G12A Yes, please squash patch 1 and 2. I have squashed patch 1 and 2. Signed-off-by: Jian Hu --- include/dt-bindings/clock/g12a-clkc.h | 93 +++ 1 file changed, 93 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 000..1473225 --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL1 +#define CLKID_FCLK_DIV22 +#define CLKID_FCLK_DIV33 +#define CLKID_FCLK_DIV44 +#define CLKID_FCLK_DIV55 +#define CLKID_FCLK_DIV76 +#define CLKID_GP0_PLL 7 Please fix the alignement. +#define CLKID_CLK8110 +#define CLKID_MPLL011 +#define CLKID_MPLL112 +#define CLKID_MPLL213 +#define CLKID_MPLL314 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL30121 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART028 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A33 +#define CLKID_SD_EMMC_B34 +#define CLKID_SD_EMMC_C35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO37 +#define CLKID_ETH 38 +#define CLKID_DEMUX39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART142 +#define CLKID_G2D 43 +#define CLKID_RESET44 +#define CLKID_PCIE_COMB45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT65654 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART257 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_B_CLK0 60 +#define CLKID_SD_EMMC_C_CLK0 61 +#define CLKID_HIFI_PLL 71 + is this empty line here on purpose? a comment would be great if there's a reason behind it (there's already a gap in the numbering between CLKID_GP0_PLL and CLKID_CLK81, but there's no empty line there - either way is fine, please just keep it consistent) Please drop the empty line. Otherwise, looks good. I have dropped it ,and I will push another email later.Thanks. Regards Martin .
Re: [PATCH 2/3] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
On 2018/7/10 17:26, Jerome Brunet wrote: On Tue, 2018-07-10 at 00:13 +0200, Martin Blumenstingl wrote: On Mon, Jul 9, 2018 at 1:13 PM Jian Hu wrote: Add dt-bindings headers for the Meson-G12A's Everything-Else part clock controller. I wonder if this should be folded into patch #1 along with an update to Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt so it's clear which header has to be used for G12A Yes, please squash patch 1 and 2. I have squashed patch 1 and 2. Signed-off-by: Jian Hu --- include/dt-bindings/clock/g12a-clkc.h | 93 +++ 1 file changed, 93 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 000..1473225 --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL1 +#define CLKID_FCLK_DIV22 +#define CLKID_FCLK_DIV33 +#define CLKID_FCLK_DIV44 +#define CLKID_FCLK_DIV55 +#define CLKID_FCLK_DIV76 +#define CLKID_GP0_PLL 7 Please fix the alignement. +#define CLKID_CLK8110 +#define CLKID_MPLL011 +#define CLKID_MPLL112 +#define CLKID_MPLL213 +#define CLKID_MPLL314 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL30121 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART028 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A33 +#define CLKID_SD_EMMC_B34 +#define CLKID_SD_EMMC_C35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO37 +#define CLKID_ETH 38 +#define CLKID_DEMUX39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART142 +#define CLKID_G2D 43 +#define CLKID_RESET44 +#define CLKID_PCIE_COMB45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT65654 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART257 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_B_CLK0 60 +#define CLKID_SD_EMMC_C_CLK0 61 +#define CLKID_HIFI_PLL 71 + is this empty line here on purpose? a comment would be great if there's a reason behind it (there's already a gap in the numbering between CLKID_GP0_PLL and CLKID_CLK81, but there's no empty line there - either way is fine, please just keep it consistent) Please drop the empty line. Otherwise, looks good. I have dropped it ,and I will push another email later.Thanks. Regards Martin .
Re: [PATCH 2/3] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
On 2018/7/10 6:13, Martin Blumenstingl wrote: On Mon, Jul 9, 2018 at 1:13 PM Jian Hu wrote: Add dt-bindings headers for the Meson-G12A's Everything-Else part clock controller. I wonder if this should be folded into patch #1 along with an update to Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt so it's clear which header has to be used for G12A As your suggestions, I will squash patch 1 and 2. Signed-off-by: Jian Hu --- include/dt-bindings/clock/g12a-clkc.h | 93 +++ 1 file changed, 93 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 000..1473225 --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL1 +#define CLKID_FCLK_DIV22 +#define CLKID_FCLK_DIV33 +#define CLKID_FCLK_DIV44 +#define CLKID_FCLK_DIV55 +#define CLKID_FCLK_DIV76 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK8110 +#define CLKID_MPLL011 +#define CLKID_MPLL112 +#define CLKID_MPLL213 +#define CLKID_MPLL314 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL30121 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART028 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A33 +#define CLKID_SD_EMMC_B34 +#define CLKID_SD_EMMC_C35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO37 +#define CLKID_ETH 38 +#define CLKID_DEMUX39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART142 +#define CLKID_G2D 43 +#define CLKID_RESET44 +#define CLKID_PCIE_COMB45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT65654 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART257 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_B_CLK0 60 +#define CLKID_SD_EMMC_C_CLK0 61 +#define CLKID_HIFI_PLL 71 + is this empty line here on purpose? a comment would be great if there's a reason behind it (there's already a gap in the numbering between CLKID_GP0_PLL and CLKID_CLK81, but there's no empty line there - either way is fine, please just keep it consistent) I will drop the empty line, The gaps have define in drivers/clk/meson/g12a.h file. Regards Martin .
Re: [PATCH 2/3] dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings
On 2018/7/10 6:13, Martin Blumenstingl wrote: On Mon, Jul 9, 2018 at 1:13 PM Jian Hu wrote: Add dt-bindings headers for the Meson-G12A's Everything-Else part clock controller. I wonder if this should be folded into patch #1 along with an update to Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt so it's clear which header has to be used for G12A As your suggestions, I will squash patch 1 and 2. Signed-off-by: Jian Hu --- include/dt-bindings/clock/g12a-clkc.h | 93 +++ 1 file changed, 93 insertions(+) create mode 100644 include/dt-bindings/clock/g12a-clkc.h diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 000..1473225 --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL1 +#define CLKID_FCLK_DIV22 +#define CLKID_FCLK_DIV33 +#define CLKID_FCLK_DIV44 +#define CLKID_FCLK_DIV55 +#define CLKID_FCLK_DIV76 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK8110 +#define CLKID_MPLL011 +#define CLKID_MPLL112 +#define CLKID_MPLL213 +#define CLKID_MPLL314 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL30121 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART028 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A33 +#define CLKID_SD_EMMC_B34 +#define CLKID_SD_EMMC_C35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO37 +#define CLKID_ETH 38 +#define CLKID_DEMUX39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART142 +#define CLKID_G2D 43 +#define CLKID_RESET44 +#define CLKID_PCIE_COMB45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT65654 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART257 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_B_CLK0 60 +#define CLKID_SD_EMMC_C_CLK0 61 +#define CLKID_HIFI_PLL 71 + is this empty line here on purpose? a comment would be great if there's a reason behind it (there's already a gap in the numbering between CLKID_GP0_PLL and CLKID_CLK81, but there's no empty line there - either way is fine, please just keep it consistent) I will drop the empty line, The gaps have define in drivers/clk/meson/g12a.h file. Regards Martin .
Re: [PATCH 1/3] dt-bindings: clk: g12a: New binding for Meson-G12A SoC
On 2018/7/10 5:57, Martin Blumenstingl wrote: adding Rob Herring so it doesn't get lost on the devicetree mailing list On Mon, Jul 9, 2018 at 1:13 PM Jian Hu wrote: Add new binding for Meson-G12A SoC Everything-Else part Signed-off-by: Jian Hu --- Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599..0833006 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,7 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. + "amlogic,g12a-clkc" for G12A SoC. should this be "amlogic,meson-g12a-clkc" instead? that would make it consistent with virtually all other bindings which use the schema "amlogic,meson-" (where chip is 8, 8b, 8m2, -gxbb, -gxl, ...) see also: $ grep -R "amlogic," Documentation/devicetree/bindings/ Which type should we choose,have a discussion? .compatible = "amlogic,g12a-clkc or .compatible = "amlogic,meson-g12a-clkc - #clock-cells: should be 1. -- 1.9.1 ___ linux-amlogic mailing list linux-amlo...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic .
Re: [PATCH 1/3] dt-bindings: clk: g12a: New binding for Meson-G12A SoC
On 2018/7/10 5:57, Martin Blumenstingl wrote: adding Rob Herring so it doesn't get lost on the devicetree mailing list On Mon, Jul 9, 2018 at 1:13 PM Jian Hu wrote: Add new binding for Meson-G12A SoC Everything-Else part Signed-off-by: Jian Hu --- Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599..0833006 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,7 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. + "amlogic,g12a-clkc" for G12A SoC. should this be "amlogic,meson-g12a-clkc" instead? that would make it consistent with virtually all other bindings which use the schema "amlogic,meson-" (where chip is 8, 8b, 8m2, -gxbb, -gxl, ...) see also: $ grep -R "amlogic," Documentation/devicetree/bindings/ Which type should we choose,have a discussion? .compatible = "amlogic,g12a-clkc or .compatible = "amlogic,meson-g12a-clkc - #clock-cells: should be 1. -- 1.9.1 ___ linux-amlogic mailing list linux-amlo...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic .
Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver
On 2018/7/10 5:53, Martin Blumenstingl wrote:
On Mon, Jul 9, 2018 at 1:14 PM Jian Hu wrote:
Add a Clock driver for the Everyting-Else part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/g12a.c | 992 +
drivers/clk/meson/g12a.h | 123 ++
4 files changed, 1126 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec5..94a82f73 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -36,3 +36,13 @@ config COMMON_CLK_AXG
help
Support for the clock controller on AmLogic A113D devices, aka axg.
Say Y if you want peripherals and CPU frequency scaling to work.
+
+config COMMON_CLK_G12A
+ bool
+ depends on COMMON_CLK_AMLOGIC
+ select RESET_CONTROLLER
+ select COMMON_CLK_REGMAP_MESON
+ select MFD_SYSCON
+ help
+ Support for the clock controller on AmLogic U400 devices, aka g12a.
+ Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index fa6d1e3..45d107c 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o
clk-audio-divider.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o meson-aoclk.o gxbb-aoclk.o
gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o meson-aoclk.o axg-aoclk.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 000..3675697
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,992 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AmLogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Jian Hu
+ * Author: Qiufang Dai
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "g12a.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap g12a_fixed_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .m = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 16,
+ .width = 2,
+ },
+ .frac = {
+ .reg_off = HHI_FIX_PLL_CNTL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = _clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ },
+};
+
+static const struct reg_sequence g12a_sys_init_regs[] = {
+ { .reg = HHI_SYS_PLL_CNTL1, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL2, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
+ { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
+ { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
+ { .reg = HHI_SYS_PLL_CNTL6, .def = 0x5654 },
+};
+
+static struct clk_regmap g12a_sys_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .m = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+ .shift = 16,
+ .width = 3,
+ },
+ .l = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+
Re: [PATCH 3/3] clk: meson-g12a: Add EE Clock controller driver
On 2018/7/10 5:53, Martin Blumenstingl wrote:
On Mon, Jul 9, 2018 at 1:14 PM Jian Hu wrote:
Add a Clock driver for the Everyting-Else part
of the Amlogic Meson-G12A SoC.
Signed-off-by: Jian Hu
---
drivers/clk/meson/Kconfig | 10 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/g12a.c | 992 +
drivers/clk/meson/g12a.h | 123 ++
4 files changed, 1126 insertions(+)
create mode 100644 drivers/clk/meson/g12a.c
create mode 100644 drivers/clk/meson/g12a.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec5..94a82f73 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -36,3 +36,13 @@ config COMMON_CLK_AXG
help
Support for the clock controller on AmLogic A113D devices, aka axg.
Say Y if you want peripherals and CPU frequency scaling to work.
+
+config COMMON_CLK_G12A
+ bool
+ depends on COMMON_CLK_AMLOGIC
+ select RESET_CONTROLLER
+ select COMMON_CLK_REGMAP_MESON
+ select MFD_SYSCON
+ help
+ Support for the clock controller on AmLogic U400 devices, aka g12a.
+ Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index fa6d1e3..45d107c 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o
clk-audio-divider.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o meson-aoclk.o gxbb-aoclk.o
gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o meson-aoclk.o axg-aoclk.o
+obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
new file mode 100644
index 000..3675697
--- /dev/null
+++ b/drivers/clk/meson/g12a.c
@@ -0,0 +1,992 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AmLogic Meson-G12A Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Jian Hu
+ * Author: Qiufang Dai
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "g12a.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap g12a_fixed_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .m = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 16,
+ .width = 2,
+ },
+ .frac = {
+ .reg_off = HHI_FIX_PLL_CNTL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_FIX_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = _clk_pll_ro_ops,
+ .parent_names = (const char *[]){ "xtal" },
+ .num_parents = 1,
+ },
+};
+
+static const struct reg_sequence g12a_sys_init_regs[] = {
+ { .reg = HHI_SYS_PLL_CNTL1, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL2, .def = 0x },
+ { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
+ { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
+ { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
+ { .reg = HHI_SYS_PLL_CNTL6, .def = 0x5654 },
+};
+
+static struct clk_regmap g12a_sys_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .m = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .od = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+ .shift = 16,
+ .width = 3,
+ },
+ .l = {
+ .reg_off = HHI_SYS_PLL_CNTL0,
+
