Re: [PATCH] mmc: fix mmc dma operation
Hi Neil, Thanks for the review, I will update the subject and commit message in the next version. On 2019/10/21 15:57, Neil Armstrong wrote: > Hi, > > Thanks for the fix. > > First, you should add "mmc: meson-gx:" in the subject. > > On 21/10/2019 07:59, Jianxin Pan wrote: >> From: Nan Li >> >> In MMC dma transfer, the region requested by dma_map_sg() may be released >> by dma_unmap_sg() before the transfer is completed. >> >> Put the unmap operation in front of mmc_request_done() to avoid this. > > > You should add a "Fixes:" tag so it can be backported on stable kernels. > >> >> Signed-off-by: Nan Li >> Signed-off-by: Jianxin Pan >> --- >> drivers/mmc/host/meson-gx-mmc.c | 15 --- >> 1 file changed, 8 insertions(+), 7 deletions(-) >> [...] >> } >> >> static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command >> *cmd) >> > Neil > > . >
[PATCH] mmc: fix mmc dma operation
From: Nan Li
In MMC dma transfer, the region requested by dma_map_sg() may be released
by dma_unmap_sg() before the transfer is completed.
Put the unmap operation in front of mmc_request_done() to avoid this.
Signed-off-by: Nan Li
Signed-off-by: Jianxin Pan
---
drivers/mmc/host/meson-gx-mmc.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index e712315..7667e8a 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -173,6 +173,7 @@ struct meson_host {
int irq;
bool vqmmc_enabled;
+ bool needs_pre_post_req;
};
#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
@@ -654,6 +655,8 @@ static void meson_mmc_request_done(struct mmc_host *mmc,
struct meson_host *host = mmc_priv(mmc);
host->cmd = NULL;
+ if (host->needs_pre_post_req)
+ meson_mmc_post_req(mmc, mrq, 0);
mmc_request_done(host->mmc, mrq);
}
@@ -803,25 +806,23 @@ static void meson_mmc_start_cmd(struct mmc_host *mmc,
struct mmc_command *cmd)
static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
struct meson_host *host = mmc_priv(mmc);
- bool needs_pre_post_req = mrq->data &&
+
+ host->needs_pre_post_req = mrq->data &&
!(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
- if (needs_pre_post_req) {
+ if (host->needs_pre_post_req) {
meson_mmc_get_transfer_mode(mmc, mrq);
if (!meson_mmc_desc_chain_mode(mrq->data))
- needs_pre_post_req = false;
+ host->needs_pre_post_req = false;
}
- if (needs_pre_post_req)
+ if (host->needs_pre_post_req)
meson_mmc_pre_req(mmc, mrq);
/* Stop execution */
writel(0, host->regs + SD_EMMC_START);
meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
-
- if (needs_pre_post_req)
- meson_mmc_post_req(mmc, mrq, 0);
}
static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
--
2.7.4
[PATCH v3 2/4] firmware: meson_sm: Add secure power domain support
The Amlogic Meson A1/C1 Secure Monitor implements calls to control power
domain.
Signed-off-by: Jianxin Pan
---
drivers/firmware/meson/meson_sm.c | 2 ++
include/linux/firmware/meson/meson_sm.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/firmware/meson/meson_sm.c
b/drivers/firmware/meson/meson_sm.c
index 1d5b4d7..7ec09f5 100644
--- a/drivers/firmware/meson/meson_sm.c
+++ b/drivers/firmware/meson/meson_sm.c
@@ -44,6 +44,8 @@ static const struct meson_sm_chip gxbb_chip = {
CMD(SM_EFUSE_WRITE, 0x8231),
CMD(SM_EFUSE_USER_MAX, 0x8233),
CMD(SM_GET_CHIP_ID, 0x8244),
+ CMD(SM_PWRC_SET,0x8293),
+ CMD(SM_PWRC_GET,0x8295),
{ /* sentinel */ },
},
};
diff --git a/include/linux/firmware/meson/meson_sm.h
b/include/linux/firmware/meson/meson_sm.h
index 6669e2a..4ed3989 100644
--- a/include/linux/firmware/meson/meson_sm.h
+++ b/include/linux/firmware/meson/meson_sm.h
@@ -12,6 +12,8 @@ enum {
SM_EFUSE_WRITE,
SM_EFUSE_USER_MAX,
SM_GET_CHIP_ID,
+ SM_PWRC_SET,
+ SM_PWRC_GET,
};
struct meson_sm_firmware;
--
2.7.4
[PATCH v3 3/4] soc: amlogic: Add support for Secure power domains controller
Add support for the Amlogic Secure Power controller. In A1/C1 series, power
control registers are in secure domain, and should be accessed by smc.
Signed-off-by: Jianxin Pan
---
drivers/soc/amlogic/Kconfig | 13 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc/amlogic/meson-secure-pwrc.c | 204
3 files changed, 218 insertions(+)
create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c
diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
index bc2c912..6cb06e7 100644
--- a/drivers/soc/amlogic/Kconfig
+++ b/drivers/soc/amlogic/Kconfig
@@ -48,6 +48,19 @@ config MESON_EE_PM_DOMAINS
Say yes to expose Amlogic Meson Everything-Else Power Domains as
Generic Power Domains.
+config MESON_SECURE_PM_DOMAINS
+ bool "Amlogic Meson Secure Power Domains driver"
+ depends on ARCH_MESON || COMPILE_TEST
+ depends on PM && OF
+ depends on HAVE_ARM_SMCCC
+ default ARCH_MESON
+ select PM_GENERIC_DOMAINS
+ select PM_GENERIC_DOMAINS_OF
+ help
+ Support for the power controller on Amlogic A1/C1 series.
+ Say yes to expose Amlogic Meson Secure Power Domains as Generic
+ Power Domains.
+
config MESON_MX_SOCINFO
bool "Amlogic Meson MX SoC Information driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
index de79d044..7b8c5d3 100644
--- a/drivers/soc/amlogic/Makefile
+++ b/drivers/soc/amlogic/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
obj-$(CONFIG_MESON_EE_PM_DOMAINS) += meson-ee-pwrc.o
+obj-$(CONFIG_MESON_SECURE_PM_DOMAINS) += meson-secure-pwrc.o
diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c
b/drivers/soc/amlogic/meson-secure-pwrc.c
new file mode 100644
index ..181b066
--- /dev/null
+++ b/drivers/soc/amlogic/meson-secure-pwrc.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc.
+ * Author: Jianxin Pan
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PWRC_ON1
+#define PWRC_OFF 0
+
+struct meson_secure_pwrc_domain {
+ struct generic_pm_domain base;
+ unsigned int index;
+ struct meson_secure_pwrc *pwrc;
+};
+
+struct meson_secure_pwrc {
+ struct meson_secure_pwrc_domain *domains;
+ struct genpd_onecell_data xlate;
+ struct meson_sm_firmware *fw;
+};
+
+struct meson_secure_pwrc_domain_desc {
+ unsigned int index;
+ unsigned int flags;
+ char *name;
+ bool (*is_off)(struct meson_secure_pwrc_domain *pwrc_domain);
+};
+
+struct meson_secure_pwrc_domain_data {
+ unsigned int count;
+ struct meson_secure_pwrc_domain_desc *domains;
+};
+
+static bool pwrc_secure_is_off(struct meson_secure_pwrc_domain *pwrc_domain)
+{
+ int sts = 1;
+
+ if (meson_sm_call(pwrc_domain->pwrc->fw, SM_PWRC_GET, ,
+ pwrc_domain->index, 0, 0, 0, 0) < 0)
+ pr_err("failed to get power domain status\n");
+
+ return !!sts;
+}
+
+static int meson_secure_pwrc_off(struct generic_pm_domain *domain)
+{
+ int sts = 0;
+ struct meson_secure_pwrc_domain *pwrc_domain =
+ container_of(domain, struct meson_secure_pwrc_domain, base);
+
+ if (meson_sm_call(pwrc_domain->pwrc->fw, SM_PWRC_SET, NULL,
+ pwrc_domain->index, PWRC_OFF, 0, 0, 0) < 0) {
+ pr_err("failed to set power domain off\n");
+ sts = -EINVAL;
+ }
+
+ return sts;
+}
+
+static int meson_secure_pwrc_on(struct generic_pm_domain *domain)
+{
+ int sts = 0;
+ struct meson_secure_pwrc_domain *pwrc_domain =
+ container_of(domain, struct meson_secure_pwrc_domain, base);
+
+ if (meson_sm_call(pwrc_domain->pwrc->fw, SM_PWRC_SET, NULL,
+ pwrc_domain->index, PWRC_ON, 0, 0, 0) < 0) {
+ pr_err("failed to set power domain on\n");
+ sts = -EINVAL;
+ }
+
+ return sts;
+}
+
+#define SEC_PD(__name, __flag) \
+[PWRC_##__name##_ID] = \
+{ \
+ .name = #__name,\
+ .index = PWRC_##__name##_ID,\
+ .is_off = pwrc_secure_is_off, \
+ .flags = __flag,\
+}
+
+static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
+ SEC_PD(DSPA,0),
+ SEC_PD(DSPB,0),
+ /* UART should keep working in ATF after suspend and before resume */
+ SEC_PD(UART,GENPD_FLAG_
[PATCH v3 1/4] dt-bindings: power: add Amlogic secure power domains bindings
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.
The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
power domain registers are in secure world.
Signed-off-by: Jianxin Pan
---
.../bindings/power/amlogic,meson-sec-pwrc.yaml | 42 ++
include/dt-bindings/power/meson-a1-power.h | 32 +
2 files changed, 74 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
create mode 100644 include/dt-bindings/power/meson-a1-power.h
diff --git
a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
new file mode 100644
index ..88d8261
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+# Copyright (c) 2019 Amlogic, Inc
+# Author: Jianxin Pan
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson Secure Power Domains
+
+maintainers:
+ - Jianxin Pan
+
+description: |+
+ Meson Secure Power Domains used in A1/C1 SoCs.
+
+properties:
+ compatible:
+enum:
+ - amlogic,meson-a1-pwrc
+
+ "#power-domain-cells":
+const: 1
+
+ secure-monitor:
+description: phandle to the secure-monitor node
+$ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - "#power-domain-cells"
+ - secure-monitor
+
+examples:
+ - |
+pwrc: power-controller {
+ compatible = "amlogic,meson-a1-pwrc";
+ #power-domain-cells = <1>;
+ secure-monitor = <>;
+};
+
+
diff --git a/include/dt-bindings/power/meson-a1-power.h
b/include/dt-bindings/power/meson-a1-power.h
new file mode 100644
index ..6cf50bf
--- /dev/null
+++ b/include/dt-bindings/power/meson-a1-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc.
+ * Author: Jianxin Pan
+ */
+
+#ifndef _DT_BINDINGS_MESON_A1_POWER_H
+#define _DT_BINDINGS_MESON_A1_POWER_H
+
+#define PWRC_DSPA_ID 8
+#define PWRC_DSPB_ID 9
+#define PWRC_UART_ID 10
+#define PWRC_DMC_ID11
+#define PWRC_I2C_ID12
+#define PWRC_PSRAM_ID 13
+#define PWRC_ACODEC_ID 14
+#define PWRC_AUDIO_ID 15
+#define PWRC_OTP_ID16
+#define PWRC_DMA_ID17
+#define PWRC_SD_EMMC_ID18
+#define PWRC_RAMA_ID 19
+#define PWRC_RAMB_ID 20
+#define PWRC_IR_ID 21
+#define PWRC_SPICC_ID 22
+#define PWRC_SPIFC_ID 23
+#define PWRC_USB_ID24
+#define PWRC_NIC_ID25
+#define PWRC_PDMIN_ID 26
+#define PWRC_RSA_ID27
+#define PWRC_MAX_ID28
+
+#endif
--
2.7.4
[PATCH RESEND v3 0/4] arm64: meson: add support for A1 Power Domains
This patchset introduces a "Secure Power Doamin Controller". In A1/C1, power controller registers such as PWRCTRL_FOCRSTN, PWRCTRL_PWR_OFF, PWRCTRL_MEM_PD and PWRCTRL_ISO_EN, are in the secure domain, and should be accessed from ATF by smc. Changes since v1 at [1]: - update domain id - include dt-bindings in dts Changes since v1 at [0]: - use APIs from sm driver - rename pwrc_secure_get_power as Kevin suggested - add comments for always on domains - replace arch_initcall_sync with builtin_platform_driver - fix coding style [0] https://lore.kernel.org/linux-amlogic/1568895064-4116-1-git-send-email-jianxin@amlogic.com [1] https://lore.kernel.org/linux-amlogic/1570695678-42623-1-git-send-email-jianxin@amlogic.com Jianxin Pan (4): dt-bindings: power: add Amlogic secure power domains bindings firmware: meson_sm: Add secure power domain support soc: amlogic: Add support for Secure power domains controller arm64: dts: meson: a1: add secure power domain controller .../bindings/power/amlogic,meson-sec-pwrc.yaml | 42 + arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 8 + drivers/firmware/meson/meson_sm.c | 2 + drivers/soc/amlogic/Kconfig| 13 ++ drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-secure-pwrc.c| 204 + include/dt-bindings/power/meson-a1-power.h | 32 include/linux/firmware/meson/meson_sm.h| 2 + 8 files changed, 304 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c create mode 100644 include/dt-bindings/power/meson-a1-power.h -- 2.7.4
[PATCH v3 4/4] arm64: dts: meson: a1: add secure power domain controller
Enable power domain controller for Meson A1 SoC.
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..081bc31 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -5,6 +5,7 @@
#include
#include
+#include
/ {
compatible = "amlogic,a1";
@@ -93,6 +94,13 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-a1-pwrc";
+ #power-domain-cells = <1>;
+ secure-monitor = <>;
+ status = "okay";
+ };
};
gic: interrupt-controller@ff901000 {
--
2.7.4
Re: [PATCH RESEND v2 1/4] dt-bindings: power: add Amlogic secure power domains bindings
Hi Rob,
On 2019/10/15 1:39, Rob Herring wrote:
> On Thu, Oct 10, 2019 at 04:21:15AM -0400, Jianxin Pan wrote:
>> Add the bindings for the Amlogic Secure power domains, controlling the
>> secure power domains.
>>
>> The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
>> power domain registers are in secure world.
>>
>> Signed-off-by: Jianxin Pan
>> ---
>> .../bindings/power/amlogic,meson-sec-pwrc.yaml | 42
>> ++
>> include/dt-bindings/power/meson-a1-power.h | 32 +
>> 2 files changed, 74 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> +
>> + secure-monitor:
>> +description: phandle to the secure-monitor node
>> +$ref: /schemas/types.yaml#/definitions/phandle
>
> Why not just a child node of this node?
>
Thanks for the review.
I followed the style of the previous series of meson：
46 efuse: efuse {
47 compatible = "amlogic,meson-gxbb-efuse";
48 clocks = < CLKID_EFUSE>;
49 #address-cells = <1>;
50 #size-cells = <1>;
51 read-only;
52 secure-monitor = <>;
53 };
> Rob
>
> .
>
[PATCH RESEND v2 4/4] arm64: dts: meson: a1: add secure power domain controller
Enable power domain controller for Meson A1 SoC.
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..5547913 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -93,6 +93,13 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-a1-pwrc";
+ #power-domain-cells = <1>;
+ secure-monitor = <>;
+ status = "okay";
+ };
};
gic: interrupt-controller@ff901000 {
--
2.7.4
[PATCH RESED v2 2/4] firmware: meson_sm: Add secure power domain support
The Amlogic Meson A1/C1 Secure Monitor implements calls to control power
domain.
Signed-off-by: Jianxin Pan
---
drivers/firmware/meson/meson_sm.c | 2 ++
include/linux/firmware/meson/meson_sm.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/firmware/meson/meson_sm.c
b/drivers/firmware/meson/meson_sm.c
index 1d5b4d7..7ec09f5 100644
--- a/drivers/firmware/meson/meson_sm.c
+++ b/drivers/firmware/meson/meson_sm.c
@@ -44,6 +44,8 @@ static const struct meson_sm_chip gxbb_chip = {
CMD(SM_EFUSE_WRITE, 0x8231),
CMD(SM_EFUSE_USER_MAX, 0x8233),
CMD(SM_GET_CHIP_ID, 0x8244),
+ CMD(SM_PWRC_SET,0x8293),
+ CMD(SM_PWRC_GET,0x8295),
{ /* sentinel */ },
},
};
diff --git a/include/linux/firmware/meson/meson_sm.h
b/include/linux/firmware/meson/meson_sm.h
index 6669e2a..4ed3989 100644
--- a/include/linux/firmware/meson/meson_sm.h
+++ b/include/linux/firmware/meson/meson_sm.h
@@ -12,6 +12,8 @@ enum {
SM_EFUSE_WRITE,
SM_EFUSE_USER_MAX,
SM_GET_CHIP_ID,
+ SM_PWRC_SET,
+ SM_PWRC_GET,
};
struct meson_sm_firmware;
--
2.7.4
[PATCH RESEND v2 1/4] dt-bindings: power: add Amlogic secure power domains bindings
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.
The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
power domain registers are in secure world.
Signed-off-by: Jianxin Pan
---
.../bindings/power/amlogic,meson-sec-pwrc.yaml | 42 ++
include/dt-bindings/power/meson-a1-power.h | 32 +
2 files changed, 74 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
create mode 100644 include/dt-bindings/power/meson-a1-power.h
diff --git
a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
new file mode 100644
index ..88d8261
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+# Copyright (c) 2019 Amlogic, Inc
+# Author: Jianxin Pan
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson Secure Power Domains
+
+maintainers:
+ - Jianxin Pan
+
+description: |+
+ Meson Secure Power Domains used in A1/C1 SoCs.
+
+properties:
+ compatible:
+enum:
+ - amlogic,meson-a1-pwrc
+
+ "#power-domain-cells":
+const: 1
+
+ secure-monitor:
+description: phandle to the secure-monitor node
+$ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - "#power-domain-cells"
+ - secure-monitor
+
+examples:
+ - |
+pwrc: power-controller {
+ compatible = "amlogic,meson-a1-pwrc";
+ #power-domain-cells = <1>;
+ secure-monitor = <>;
+};
+
+
diff --git a/include/dt-bindings/power/meson-a1-power.h
b/include/dt-bindings/power/meson-a1-power.h
new file mode 100644
index ..6cf50bf
--- /dev/null
+++ b/include/dt-bindings/power/meson-a1-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc.
+ * Author: Jianxin Pan
+ */
+
+#ifndef _DT_BINDINGS_MESON_A1_POWER_H
+#define _DT_BINDINGS_MESON_A1_POWER_H
+
+#define PWRC_DSPA_ID 8
+#define PWRC_DSPB_ID 9
+#define PWRC_UART_ID 10
+#define PWRC_DMC_ID11
+#define PWRC_I2C_ID12
+#define PWRC_PSRAM_ID 13
+#define PWRC_ACODEC_ID 14
+#define PWRC_AUDIO_ID 15
+#define PWRC_OTP_ID16
+#define PWRC_DMA_ID17
+#define PWRC_SD_EMMC_ID18
+#define PWRC_RAMA_ID 19
+#define PWRC_RAMB_ID 20
+#define PWRC_IR_ID 21
+#define PWRC_SPICC_ID 22
+#define PWRC_SPIFC_ID 23
+#define PWRC_USB_ID24
+#define PWRC_NIC_ID25
+#define PWRC_PDMIN_ID 26
+#define PWRC_RSA_ID27
+#define PWRC_MAX_ID28
+
+#endif
--
2.7.4
[PATCH RESEND v2 3/4] soc: amlogic: Add support for Secure power domains controller
Add support for the Amlogic Secure Power controller. In A1/C1 series, power
control registers are in secure domain, and should be accessed by smc.
Signed-off-by: Jianxin Pan
---
drivers/soc/amlogic/Kconfig | 13 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc/amlogic/meson-secure-pwrc.c | 203
3 files changed, 217 insertions(+)
create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c
diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
index bc2c912..6cb06e7 100644
--- a/drivers/soc/amlogic/Kconfig
+++ b/drivers/soc/amlogic/Kconfig
@@ -48,6 +48,19 @@ config MESON_EE_PM_DOMAINS
Say yes to expose Amlogic Meson Everything-Else Power Domains as
Generic Power Domains.
+config MESON_SECURE_PM_DOMAINS
+ bool "Amlogic Meson Secure Power Domains driver"
+ depends on ARCH_MESON || COMPILE_TEST
+ depends on PM && OF
+ depends on HAVE_ARM_SMCCC
+ default ARCH_MESON
+ select PM_GENERIC_DOMAINS
+ select PM_GENERIC_DOMAINS_OF
+ help
+ Support for the power controller on Amlogic A1/C1 series.
+ Say yes to expose Amlogic Meson Secure Power Domains as Generic
+ Power Domains.
+
config MESON_MX_SOCINFO
bool "Amlogic Meson MX SoC Information driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
index de79d044..7b8c5d3 100644
--- a/drivers/soc/amlogic/Makefile
+++ b/drivers/soc/amlogic/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
obj-$(CONFIG_MESON_EE_PM_DOMAINS) += meson-ee-pwrc.o
+obj-$(CONFIG_MESON_SECURE_PM_DOMAINS) += meson-secure-pwrc.o
diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c
b/drivers/soc/amlogic/meson-secure-pwrc.c
new file mode 100644
index ..25951cb
--- /dev/null
+++ b/drivers/soc/amlogic/meson-secure-pwrc.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc.
+ * Author: Jianxin Pan
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PWRC_ON1
+#define PWRC_OFF 0
+
+struct meson_secure_pwrc_domain {
+ struct generic_pm_domain base;
+ unsigned int index;
+ struct meson_secure_pwrc *pwrc;
+};
+
+struct meson_secure_pwrc {
+ struct meson_secure_pwrc_domain *domains;
+ struct genpd_onecell_data xlate;
+ struct meson_sm_firmware *fw;
+};
+
+struct meson_secure_pwrc_domain_desc {
+ unsigned int index;
+ unsigned int flags;
+ char *name;
+ bool (*is_off)(struct meson_secure_pwrc_domain *pwrc_domain);
+};
+
+struct meson_secure_pwrc_domain_data {
+ unsigned int count;
+ struct meson_secure_pwrc_domain_desc *domains;
+};
+
+static bool pwrc_secure_is_off(struct meson_secure_pwrc_domain *pwrc_domain)
+{
+ int sts = 1;
+
+ if (meson_sm_call(pwrc_domain->pwrc->fw, SM_PWRC_GET, ,
+ pwrc_domain->index, 0, 0, 0, 0) < 0)
+ pr_err("failed to get power domain status\n");
+
+ return !!sts;
+}
+
+static int meson_secure_pwrc_off(struct generic_pm_domain *domain)
+{
+ int sts = 0;
+ struct meson_secure_pwrc_domain *pwrc_domain =
+ container_of(domain, struct meson_secure_pwrc_domain, base);
+
+ if (meson_sm_call(pwrc_domain->pwrc->fw, SM_PWRC_SET, NULL,
+ pwrc_domain->index, PWRC_OFF, 0, 0, 0) < 0) {
+ pr_err("failed to set power domain off\n");
+ sts = -EINVAL;
+ }
+
+ return sts;
+}
+
+static int meson_secure_pwrc_on(struct generic_pm_domain *domain)
+{
+ int sts = 0;
+ struct meson_secure_pwrc_domain *pwrc_domain =
+ container_of(domain, struct meson_secure_pwrc_domain, base);
+
+ if (meson_sm_call(pwrc_domain->pwrc->fw, SM_PWRC_SET, NULL,
+ pwrc_domain->index, PWRC_ON, 0, 0, 0) < 0) {
+ pr_err("failed to set power domain on\n");
+ sts = -EINVAL;
+ }
+
+ return sts;
+}
+
+#define SEC_PD(__name, __flag) \
+{ \
+ .name = #__name,\
+ .index = PWRC_##__name##_ID,\
+ .is_off = pwrc_secure_is_off, \
+ .flags = __flag,\
+}
+
+static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
+ SEC_PD(DSPA,0),
+ SEC_PD(DSPB,0),
+ /* UART should keep working in ATF after suspend and before resume */
+ SEC_PD(UART,GENPD_FLAG_ALWAYS_ON),
+ /* DMC is for DDR PHY ana/dig and
[PATCH RESEND v2 0/4] arm64: meson: add support for A1 Power Domains
This patchset introduces a "Secure Power Doamin Controller". In A1/C1, power controller registers such as PWRCTRL_FOCRSTN, PWRCTRL_PWR_OFF, PWRCTRL_MEM_PD and PWRCTRL_ISO_EN, are in the secure domain, and should be accessed from ATF by smc. Changes since v1 at [0]: - use APIs from sm driver - rename pwrc_secure_get_power as Kevin suggested - add comments for always on domains - replace arch_initcall_sync with builtin_platform_driver - fix coding style [0] https://lore.kernel.org/linux-amlogic/1568895064-4116-1-git-send-email-jianxin@amlogic.com Jianxin Pan (4): dt-bindings: power: add Amlogic secure power domains bindings firmware: meson_sm: Add secure power domain support soc: amlogic: Add support for Secure power domains controller arm64: dts: meson: a1: add secure power domain controller .../bindings/power/amlogic,meson-sec-pwrc.yaml | 42 + arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 7 + drivers/firmware/meson/meson_sm.c | 2 + drivers/soc/amlogic/Kconfig| 13 ++ drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-secure-pwrc.c| 203 + include/dt-bindings/power/meson-a1-power.h | 32 include/linux/firmware/meson/meson_sm.h| 2 + 8 files changed, 302 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c create mode 100644 include/dt-bindings/power/meson-a1-power.h -- 2.7.4
[PATCH v2 4/4] arm64: dts: meson: a1: add secure power domain controller
Enable power domain controller for Meson A1 SoC.
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..5547913 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -93,6 +93,13 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-a1-pwrc";
+ #power-domain-cells = <1>;
+ secure-monitor = <>;
+ status = "okay";
+ };
};
gic: interrupt-controller@ff901000 {
--
2.7.4
[PATCH v2 0/4] arm64: meson: add support for A1 Power Domains
This patchset introduces a "Secure Power Doamin Controller". In A1/C1, power controller registers such as PWRCTRL_FOCRSTN, PWRCTRL_PWR_OFF, PWRCTRL_MEM_PD and PWRCTRL_ISO_EN, are in the secure domain, and should be accessed from ATF by smc. Changes since v1 at [0]: - use APIs from sm driver - rename pwrc_secure_get_power as Kevin suggested - add comments for always on domains - replace arch_initcall_sync with builtin_platform_driver - fix coding style [0] https://lore.kernel.org/linux-amlogic/1568895064-4116-1-git-send-email-jianxin@amlogic.com Jianxin Pan (4): dt-bindings: power: add Amlogic secure power domains bindings firmware: meson_sm: Add secure power domain support soc: amlogic: Add support for Secure power domains controller arm64: dts: meson: a1: add secure power domain controller .../bindings/power/amlogic,meson-sec-pwrc.yaml | 42 + arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 7 + drivers/firmware/meson/meson_sm.c | 2 + drivers/soc/amlogic/Kconfig| 13 ++ drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-secure-pwrc.c| 203 + include/dt-bindings/power/meson-a1-power.h | 32 include/linux/firmware/meson/meson_sm.h| 2 + 8 files changed, 302 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c create mode 100644 include/dt-bindings/power/meson-a1-power.h -- 2.7.4
[PATCH v2 1/4] dt-bindings: power: add Amlogic secure power domains bindings
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.
The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
power domain registers are in secure world.
Signed-off-by: Jianxin Pan
---
.../bindings/power/amlogic,meson-sec-pwrc.yaml | 42 ++
include/dt-bindings/power/meson-a1-power.h | 32 +
2 files changed, 74 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
create mode 100644 include/dt-bindings/power/meson-a1-power.h
diff --git
a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
new file mode 100644
index ..88d8261
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+# Copyright (c) 2019 Amlogic, Inc
+# Author: Jianxin Pan
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson Secure Power Domains
+
+maintainers:
+ - Jianxin Pan
+
+description: |+
+ Meson Secure Power Domains used in A1/C1 SoCs.
+
+properties:
+ compatible:
+enum:
+ - amlogic,meson-a1-pwrc
+
+ "#power-domain-cells":
+const: 1
+
+ secure-monitor:
+description: phandle to the secure-monitor node
+$ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - "#power-domain-cells"
+ - secure-monitor
+
+examples:
+ - |
+pwrc: power-controller {
+ compatible = "amlogic,meson-a1-pwrc";
+ #power-domain-cells = <1>;
+ secure-monitor = <>;
+};
+
+
diff --git a/include/dt-bindings/power/meson-a1-power.h
b/include/dt-bindings/power/meson-a1-power.h
new file mode 100644
index ..6cf50bf
--- /dev/null
+++ b/include/dt-bindings/power/meson-a1-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc.
+ * Author: Jianxin Pan
+ */
+
+#ifndef _DT_BINDINGS_MESON_A1_POWER_H
+#define _DT_BINDINGS_MESON_A1_POWER_H
+
+#define PWRC_DSPA_ID 8
+#define PWRC_DSPB_ID 9
+#define PWRC_UART_ID 10
+#define PWRC_DMC_ID11
+#define PWRC_I2C_ID12
+#define PWRC_PSRAM_ID 13
+#define PWRC_ACODEC_ID 14
+#define PWRC_AUDIO_ID 15
+#define PWRC_OTP_ID16
+#define PWRC_DMA_ID17
+#define PWRC_SD_EMMC_ID18
+#define PWRC_RAMA_ID 19
+#define PWRC_RAMB_ID 20
+#define PWRC_IR_ID 21
+#define PWRC_SPICC_ID 22
+#define PWRC_SPIFC_ID 23
+#define PWRC_USB_ID24
+#define PWRC_NIC_ID25
+#define PWRC_PDMIN_ID 26
+#define PWRC_RSA_ID27
+#define PWRC_MAX_ID28
+
+#endif
--
2.7.4
[PATCH v2 3/4] soc: amlogic: Add support for Secure power domains controller
Add support for the Amlogic Secure Power controller. In A1/C1 series, power
control registers are in secure domain, and should be accessed by smc.
Signed-off-by: Jianxin Pan
---
drivers/soc/amlogic/Kconfig | 13 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc/amlogic/meson-secure-pwrc.c | 203
3 files changed, 217 insertions(+)
create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c
diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
index bc2c912..6cb06e7 100644
--- a/drivers/soc/amlogic/Kconfig
+++ b/drivers/soc/amlogic/Kconfig
@@ -48,6 +48,19 @@ config MESON_EE_PM_DOMAINS
Say yes to expose Amlogic Meson Everything-Else Power Domains as
Generic Power Domains.
+config MESON_SECURE_PM_DOMAINS
+ bool "Amlogic Meson Secure Power Domains driver"
+ depends on ARCH_MESON || COMPILE_TEST
+ depends on PM && OF
+ depends on HAVE_ARM_SMCCC
+ default ARCH_MESON
+ select PM_GENERIC_DOMAINS
+ select PM_GENERIC_DOMAINS_OF
+ help
+ Support for the power controller on Amlogic A1/C1 series.
+ Say yes to expose Amlogic Meson Secure Power Domains as Generic
+ Power Domains.
+
config MESON_MX_SOCINFO
bool "Amlogic Meson MX SoC Information driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
index de79d044..7b8c5d3 100644
--- a/drivers/soc/amlogic/Makefile
+++ b/drivers/soc/amlogic/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
obj-$(CONFIG_MESON_EE_PM_DOMAINS) += meson-ee-pwrc.o
+obj-$(CONFIG_MESON_SECURE_PM_DOMAINS) += meson-secure-pwrc.o
diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c
b/drivers/soc/amlogic/meson-secure-pwrc.c
new file mode 100644
index ..25951cb
--- /dev/null
+++ b/drivers/soc/amlogic/meson-secure-pwrc.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc.
+ * Author: Jianxin Pan
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PWRC_ON1
+#define PWRC_OFF 0
+
+struct meson_secure_pwrc_domain {
+ struct generic_pm_domain base;
+ unsigned int index;
+ struct meson_secure_pwrc *pwrc;
+};
+
+struct meson_secure_pwrc {
+ struct meson_secure_pwrc_domain *domains;
+ struct genpd_onecell_data xlate;
+ struct meson_sm_firmware *fw;
+};
+
+struct meson_secure_pwrc_domain_desc {
+ unsigned int index;
+ unsigned int flags;
+ char *name;
+ bool (*is_off)(struct meson_secure_pwrc_domain *pwrc_domain);
+};
+
+struct meson_secure_pwrc_domain_data {
+ unsigned int count;
+ struct meson_secure_pwrc_domain_desc *domains;
+};
+
+static bool pwrc_secure_is_off(struct meson_secure_pwrc_domain *pwrc_domain)
+{
+ int sts = 1;
+
+ if (meson_sm_call(pwrc_domain->pwrc->fw, SM_PWRC_GET, ,
+ pwrc_domain->index, 0, 0, 0, 0) < 0)
+ pr_err("failed to get power domain status\n");
+
+ return !!sts;
+}
+
+static int meson_secure_pwrc_off(struct generic_pm_domain *domain)
+{
+ int sts = 0;
+ struct meson_secure_pwrc_domain *pwrc_domain =
+ container_of(domain, struct meson_secure_pwrc_domain, base);
+
+ if (meson_sm_call(pwrc_domain->pwrc->fw, SM_PWRC_SET, NULL,
+ pwrc_domain->index, PWRC_OFF, 0, 0, 0) < 0) {
+ pr_err("failed to set power domain off\n");
+ sts = -EINVAL;
+ }
+
+ return sts;
+}
+
+static int meson_secure_pwrc_on(struct generic_pm_domain *domain)
+{
+ int sts = 0;
+ struct meson_secure_pwrc_domain *pwrc_domain =
+ container_of(domain, struct meson_secure_pwrc_domain, base);
+
+ if (meson_sm_call(pwrc_domain->pwrc->fw, SM_PWRC_SET, NULL,
+ pwrc_domain->index, PWRC_ON, 0, 0, 0) < 0) {
+ pr_err("failed to set power domain on\n");
+ sts = -EINVAL;
+ }
+
+ return sts;
+}
+
+#define SEC_PD(__name, __flag) \
+{ \
+ .name = #__name,\
+ .index = PWRC_##__name##_ID,\
+ .is_off = pwrc_secure_is_off, \
+ .flags = __flag,\
+}
+
+static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
+ SEC_PD(DSPA,0),
+ SEC_PD(DSPB,0),
+ /* UART should keep working in ATF after suspend and before resume */
+ SEC_PD(UART,GENPD_FLAG_ALWAYS_ON),
+ /* DMC is for DDR PHY ana/dig and
[PATCH v2 2/4] firmware: meson_sm: Add secure power domain support
The Amlogic Meson A1/C1 Secure Monitor implements calls to control power
domain.
Signed-off-by: Jianxin Pan
---
drivers/firmware/meson/meson_sm.c | 2 ++
include/linux/firmware/meson/meson_sm.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/firmware/meson/meson_sm.c
b/drivers/firmware/meson/meson_sm.c
index 1d5b4d7..7ec09f5 100644
--- a/drivers/firmware/meson/meson_sm.c
+++ b/drivers/firmware/meson/meson_sm.c
@@ -44,6 +44,8 @@ static const struct meson_sm_chip gxbb_chip = {
CMD(SM_EFUSE_WRITE, 0x8231),
CMD(SM_EFUSE_USER_MAX, 0x8233),
CMD(SM_GET_CHIP_ID, 0x8244),
+ CMD(SM_PWRC_SET,0x8293),
+ CMD(SM_PWRC_GET,0x8295),
{ /* sentinel */ },
},
};
diff --git a/include/linux/firmware/meson/meson_sm.h
b/include/linux/firmware/meson/meson_sm.h
index 6669e2a..4ed3989 100644
--- a/include/linux/firmware/meson/meson_sm.h
+++ b/include/linux/firmware/meson/meson_sm.h
@@ -12,6 +12,8 @@ enum {
SM_EFUSE_WRITE,
SM_EFUSE_USER_MAX,
SM_GET_CHIP_ID,
+ SM_PWRC_SET,
+ SM_PWRC_GET,
};
struct meson_sm_firmware;
--
2.7.4
Re: [PATCH 1/3] dt-bindings: power: add Amlogic secure power domains bindings
Hi Rob，
Thanks for your review.
I'm sorry to reply so late, for I've been on vacation in the last week.
On 2019/10/2 6:09, Rob Herring wrote:
> On Thu, Sep 19, 2019 at 08:11:02AM -0400, Jianxin Pan wrote:
>> Add the bindings for the Amlogic Secure power domains, controlling the
>> secure power domains.
>>
>> The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
>> power domain registers are in secure world.
>>
>> Signed-off-by: Jianxin Pan
>> Signed-off-by: Zhiqiang Liang
>> ---
>> .../bindings/power/amlogic,meson-sec-pwrc.yaml | 32
>> ++
>> include/dt-bindings/power/meson-a1-power.h | 32
>> ++
>> 2 files changed, 64 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> create mode 100644 include/dt-bindings/power/meson-a1-power.h
>>
>> diff --git
>> a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> new file mode 100644
>> index ..327e0d9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> @@ -0,0 +1,32 @@
>> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +# Copyright (c) 2019 Amlogic, Inc
>> +# Author: Jianxin Pan
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#;
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
>> +
>> +title: Amlogic Meson Secure Power Domains
>> +
>> +maintainers:
>> + - Jianxin Pan
>> +
>> +description: |+
>> + A1/C1 series The Secure Power Domains node should be the child of a syscon
>> + node with the required property.
>
> 'a syscon node' is not specific enough. It must be a specific node.
>
I will fix this.
In A1/C1, power control is in secure domain, and syscon parent is not needed.
>> +
>> +properties:
>> + compatible:
>> +enum:
>> + - amlogic,meson-a1-pwrc
>> +
>> +required:
>> + - compatible
>> +
>> +examples:
>> + - |
>> +pwrc: power-controller {
>> + compatible = "amlogic,meson-a1-pwrc";
>
> But why do you need this node? It has no resources.
>
> #power-domain-cells needed?
I will add #power-domain-cells and secure-monitor here.
Thank you for the review.
>
>> +};
>> +
>> +
>> diff --git a/include/dt-bindings/power/meson-a1-power.h
>> b/include/dt-bindings/power/meson-a1-power.h
>> new file mode 100644
>> index ..6cf50bf
>> --- /dev/null
>> +++ b/include/dt-bindings/power/meson-a1-power.h
>> @@ -0,0 +1,32 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
>> +/*
>> + * Copyright (c) 2019 Amlogic, Inc.
>> + * Author: Jianxin Pan
>> + */
>> +
>> +#ifndef _DT_BINDINGS_MESON_A1_POWER_H
>> +#define _DT_BINDINGS_MESON_A1_POWER_H
>> +
>> +#define PWRC_DSPA_ID8
>> +#define PWRC_DSPB_ID9
>> +#define PWRC_UART_ID10
>> +#define PWRC_DMC_ID 11
>> +#define PWRC_I2C_ID 12
>> +#define PWRC_PSRAM_ID 13
>> +#define PWRC_ACODEC_ID 14
>> +#define PWRC_AUDIO_ID 15
>> +#define PWRC_OTP_ID 16
>> +#define PWRC_DMA_ID 17
>> +#define PWRC_SD_EMMC_ID 18
>> +#define PWRC_RAMA_ID19
>> +#define PWRC_RAMB_ID20
>> +#define PWRC_IR_ID 21
>> +#define PWRC_SPICC_ID 22
>> +#define PWRC_SPIFC_ID 23
>> +#define PWRC_USB_ID 24
>> +#define PWRC_NIC_ID 25
>> +#define PWRC_PDMIN_ID 26
>> +#define PWRC_RSA_ID 27
>> +#define PWRC_MAX_ID 28
>> +
>> +#endif
>> --
>> 2.7.4
>>
>
> .
>
Re: [PATCH 2/3] soc: amlogic: Add support for Secure power domains controller
Hi Kevin,
Thanks for your review. Please see my comments below.
On 2019/9/26 6:41, Kevin Hilman wrote:
> Hi Jianxin,
>
> Jianxin Pan writes:
>
>> Add support for the Amlogic Secure Power controller. In A1/C1 series, power
>> control registers are in secure domain, and should be accessed by smc.
>>
>> Signed-off-by: Jianxin Pan
>> Signed-off-by: Zhiqiang Liang
>
> Thanks for the new power domain driver.
>
>> ---
>> drivers/soc/amlogic/Kconfig | 13 +++
>> drivers/soc/amlogic/Makefile| 1 +
>> drivers/soc/amlogic/meson-secure-pwrc.c | 182
>>
>> 3 files changed, 196 insertions(+)
>> create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c
>>
>> diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
>> index bc2c912..6cb06e7 100644
>> --- a/drivers/soc/amlogic/Kconfig
>> +++ b/drivers/soc/amlogic/Kconfig
>> @@ -48,6 +48,19 @@ config MESON_EE_PM_DOMAINS
>>Say yes to expose Amlogic Meson Everything-Else Power Domains as
>>Generic Power Domains.
>>
>> +config MESON_SECURE_PM_DOMAINS
>> +bool "Amlogic Meson Secure Power Domains driver"
>> +depends on ARCH_MESON || COMPILE_TEST
>> +depends on PM && OF
>> +depends on HAVE_ARM_SMCCC
>> +default ARCH_MESON
>> +select PM_GENERIC_DOMAINS
>> +select PM_GENERIC_DOMAINS_OF
>> +help
>> + Support for the power controller on Amlogic A1/C1 series.
>> + Say yes to expose Amlogic Meson Secure Power Domains as Generic
>> + Power Domains.
>> +
>> config MESON_MX_SOCINFO
>> bool "Amlogic Meson MX SoC Information driver"
>> depends on ARCH_MESON || COMPILE_TEST
>> diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
>> index de79d044..7b8c5d3 100644
>> --- a/drivers/soc/amlogic/Makefile
>> +++ b/drivers/soc/amlogic/Makefile
>> @@ -5,3 +5,4 @@ obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
>> obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
>> obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
>> obj-$(CONFIG_MESON_EE_PM_DOMAINS) += meson-ee-pwrc.o
>> +obj-$(CONFIG_MESON_SECURE_PM_DOMAINS) += meson-secure-pwrc.o
>> diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c
>> b/drivers/soc/amlogic/meson-secure-pwrc.c
>> new file mode 100644
>> index ..00c7232
>> --- /dev/null
>> +++ b/drivers/soc/amlogic/meson-secure-pwrc.c
>> @@ -0,0 +1,182 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
[...]
>> +
>> +static bool pwrc_secure_get_power(struct meson_secure_pwrc_domain
>> *pwrc_domain)
>> +{
>> +struct arm_smccc_res res;
>> +
>> +arm_smccc_smc(SMC_PWRC_GET, pwrc_domain->index, 0,
>> + 0, 0, 0, 0, 0, );
>> +
>> +return res.a0 & 0x1;
>
> Please use a #define with a readable name for this mask.
> The return type of this smc is bool. I will remove 0x1 mask in next version.
Another question about smc:
In this driver, no share memory is needed, and I use arm_smccc_smc() directly.
Should I add secure-monitor = <> in dtb and use meson_sm_call() from sm
driver instead?
>> +}
>
> What does the return value for this function mean? Does true mean
> "powered off" or "powered on">
The return vaule for SMC_PWRC_GET :
0 -> power on
1 -> power off> See the rename I just did on the ee-pwrc driver:
> https://lore.kernel.org/linux-amlogic/20190925213528.21515-2-khil...@kernel.org/
> I will follow and rename to _is_off() in the next verson.
>> +static int meson_secure_pwrc_off(struct generic_pm_domain *domain)
>> +{
>> +struct arm_smccc_res res;
>> +struct meson_secure_pwrc_domain *pwrc_domain =
[...]
>> +
>> +#define SEC_PD(__name, __flag) \
>> +{ \
>> +.name = #__name,\
>> +.index = PWRC_##__name##_ID,\
>> +.get_power = pwrc_secure_get_power, \
>> +.flags = __flag,\
>> +}
>> +
>> +static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
>> +SEC_PD(DSPA,0),
>> +SEC_PD(DSPB,0),
>> +SEC_PD(UART,GENPD_FLAG_ALWAYS_ON),
>
> This flag should only be used for domains where there are no linux
> drivers.
>
> Rather than using this flag, you need to add a 'power-domain' property
> to the uart driver in DT, and then update the meson_uart driver to use
> the ru
Re: [PATCH 2/3] soc: amlogic: Add support for Secure power domains controller
Hi Martin,
On 2019/9/20 4:03, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> I added three comments below from a quick glance at this driver (I
> didn't have time for a complete review)
>
> On Thu, Sep 19, 2019 at 2:11 PM Jianxin Pan wrote:
> [...]
>> + pm_genpd_init(>base, NULL,
>> + (match->domains[i].get_power ?
>> + match->domains[i].get_power(dom) : true));
> .get_power is never NULL in this driver so the ": true" part is
> effectively a no-op
>
OK, I will remove it. Thanks for your time.
> [...]
>> +static const struct of_device_id meson_secure_pwrc_match_table[] = {
>> + {
>> + .compatible = "amlogic,meson-a1-pwrc",
>> + .data = _secure_a1_pwrc_data,
>> + },
>> + { }
> many drivers use a /* sentinel */ comment inside { }
>
OK, I will add this comment line.
> [...]
>> +arch_initcall_sync(meson_secure_pwrc_init);
> why arch_initcall_sync instead of builtin_platform_driver?
> $ grep -R arch_initcall_sync drivers/soc/
> $
>
>
> Martin
>
The power-domain is depended by many other drivers, arch_initcall_sync is used
to make power-domain probe earlier.
Maybe I need to switch back to builtin_platform_driver when use APIs from
meson_sm.c.
> .
>
Re: [PATCH 1/3] dt-bindings: power: add Amlogic secure power domains bindings
Hi Martin,
On 2019/9/20 4:06, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> On Thu, Sep 19, 2019 at 2:11 PM Jianxin Pan wrote:
>>
>> Add the bindings for the Amlogic Secure power domains, controlling the
>> secure power domains.
>>
>> The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
>> power domain registers are in secure world.
>>
>> Signed-off-by: Jianxin Pan
>> Signed-off-by: Zhiqiang Liang
>> ---
>> .../bindings/power/amlogic,meson-sec-pwrc.yaml | 32
>> ++
>> include/dt-bindings/power/meson-a1-power.h | 32
>> ++
>> 2 files changed, 64 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> create mode 100644 include/dt-bindings/power/meson-a1-power.h
>>
>> diff --git
>> a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> new file mode 100644
>> index ..327e0d9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> @@ -0,0 +1,32 @@
>> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
[...]>> +examples:
>> + - |
>> +pwrc: power-controller {
>> + compatible = "amlogic,meson-a1-pwrc";
>> +};
> not a comment about this binding but about the secure monitor in general:
> there's a recent discussion about the secure monitor in the nvmem bindings:
> [0]
>
>
> Martin
>
>
> [0] https://www.spinics.net/lists/arm-kernel/msg750010.html
>
Thanks for your remind,I will update and send the second version after Rework
of secure-monitor driver is applied.
> .
>
[PATCH 3/3] arm64: dts: meson: a1: add secure power domain controller
Enable power domain controller for Meson A1 SoC.
Signed-off-by: Jianxin Pan
Signed-off-by: Zhiqiang Liang
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..d689e5c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -93,6 +93,12 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-a1-pwrc";
+ #power-domain-cells = <1>;
+ status = "okay";
+ };
};
gic: interrupt-controller@ff901000 {
--
2.7.4
[PATCH 1/3] dt-bindings: power: add Amlogic secure power domains bindings
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.
The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
power domain registers are in secure world.
Signed-off-by: Jianxin Pan
Signed-off-by: Zhiqiang Liang
---
.../bindings/power/amlogic,meson-sec-pwrc.yaml | 32 ++
include/dt-bindings/power/meson-a1-power.h | 32 ++
2 files changed, 64 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
create mode 100644 include/dt-bindings/power/meson-a1-power.h
diff --git
a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
new file mode 100644
index ..327e0d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+# Copyright (c) 2019 Amlogic, Inc
+# Author: Jianxin Pan
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson Secure Power Domains
+
+maintainers:
+ - Jianxin Pan
+
+description: |+
+ A1/C1 series The Secure Power Domains node should be the child of a syscon
+ node with the required property.
+
+properties:
+ compatible:
+enum:
+ - amlogic,meson-a1-pwrc
+
+required:
+ - compatible
+
+examples:
+ - |
+pwrc: power-controller {
+ compatible = "amlogic,meson-a1-pwrc";
+};
+
+
diff --git a/include/dt-bindings/power/meson-a1-power.h
b/include/dt-bindings/power/meson-a1-power.h
new file mode 100644
index ..6cf50bf
--- /dev/null
+++ b/include/dt-bindings/power/meson-a1-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc.
+ * Author: Jianxin Pan
+ */
+
+#ifndef _DT_BINDINGS_MESON_A1_POWER_H
+#define _DT_BINDINGS_MESON_A1_POWER_H
+
+#define PWRC_DSPA_ID 8
+#define PWRC_DSPB_ID 9
+#define PWRC_UART_ID 10
+#define PWRC_DMC_ID11
+#define PWRC_I2C_ID12
+#define PWRC_PSRAM_ID 13
+#define PWRC_ACODEC_ID 14
+#define PWRC_AUDIO_ID 15
+#define PWRC_OTP_ID16
+#define PWRC_DMA_ID17
+#define PWRC_SD_EMMC_ID18
+#define PWRC_RAMA_ID 19
+#define PWRC_RAMB_ID 20
+#define PWRC_IR_ID 21
+#define PWRC_SPICC_ID 22
+#define PWRC_SPIFC_ID 23
+#define PWRC_USB_ID24
+#define PWRC_NIC_ID25
+#define PWRC_PDMIN_ID 26
+#define PWRC_RSA_ID27
+#define PWRC_MAX_ID28
+
+#endif
--
2.7.4
[PATCH 2/3] soc: amlogic: Add support for Secure power domains controller
Add support for the Amlogic Secure Power controller. In A1/C1 series, power
control registers are in secure domain, and should be accessed by smc.
Signed-off-by: Jianxin Pan
Signed-off-by: Zhiqiang Liang
---
drivers/soc/amlogic/Kconfig | 13 +++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc/amlogic/meson-secure-pwrc.c | 182
3 files changed, 196 insertions(+)
create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c
diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
index bc2c912..6cb06e7 100644
--- a/drivers/soc/amlogic/Kconfig
+++ b/drivers/soc/amlogic/Kconfig
@@ -48,6 +48,19 @@ config MESON_EE_PM_DOMAINS
Say yes to expose Amlogic Meson Everything-Else Power Domains as
Generic Power Domains.
+config MESON_SECURE_PM_DOMAINS
+ bool "Amlogic Meson Secure Power Domains driver"
+ depends on ARCH_MESON || COMPILE_TEST
+ depends on PM && OF
+ depends on HAVE_ARM_SMCCC
+ default ARCH_MESON
+ select PM_GENERIC_DOMAINS
+ select PM_GENERIC_DOMAINS_OF
+ help
+ Support for the power controller on Amlogic A1/C1 series.
+ Say yes to expose Amlogic Meson Secure Power Domains as Generic
+ Power Domains.
+
config MESON_MX_SOCINFO
bool "Amlogic Meson MX SoC Information driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
index de79d044..7b8c5d3 100644
--- a/drivers/soc/amlogic/Makefile
+++ b/drivers/soc/amlogic/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
obj-$(CONFIG_MESON_EE_PM_DOMAINS) += meson-ee-pwrc.o
+obj-$(CONFIG_MESON_SECURE_PM_DOMAINS) += meson-secure-pwrc.o
diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c
b/drivers/soc/amlogic/meson-secure-pwrc.c
new file mode 100644
index ..00c7232
--- /dev/null
+++ b/drivers/soc/amlogic/meson-secure-pwrc.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc.
+ * Author: Jianxin Pan
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PWRC_ON1
+#define PWRC_OFF 0
+#define SMC_PWRC_SET 0x8293
+#define SMC_PWRC_GET 0x8295
+
+struct meson_secure_pwrc_domain {
+ struct generic_pm_domain base;
+ unsigned int index;
+};
+
+struct meson_secure_pwrc {
+ struct meson_secure_pwrc_domain *domains;
+ struct genpd_onecell_data xlate;
+};
+
+struct meson_secure_pwrc_domain_desc {
+ unsigned int index;
+ unsigned int flags;
+ char *name;
+ bool (*get_power)(struct meson_secure_pwrc_domain *pwrc_domain);
+};
+
+struct meson_secure_pwrc_domain_data {
+ unsigned int count;
+ struct meson_secure_pwrc_domain_desc *domains;
+};
+
+static bool pwrc_secure_get_power(struct meson_secure_pwrc_domain *pwrc_domain)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SMC_PWRC_GET, pwrc_domain->index, 0,
+ 0, 0, 0, 0, 0, );
+
+ return res.a0 & 0x1;
+}
+
+static int meson_secure_pwrc_off(struct generic_pm_domain *domain)
+{
+ struct arm_smccc_res res;
+ struct meson_secure_pwrc_domain *pwrc_domain =
+ container_of(domain, struct meson_secure_pwrc_domain, base);
+
+ arm_smccc_smc(SMC_PWRC_SET, pwrc_domain->index, PWRC_OFF,
+ 0, 0, 0, 0, 0, );
+
+ return 0;
+}
+
+static int meson_secure_pwrc_on(struct generic_pm_domain *domain)
+{
+ struct arm_smccc_res res;
+ struct meson_secure_pwrc_domain *pwrc_domain =
+ container_of(domain, struct meson_secure_pwrc_domain, base);
+
+ arm_smccc_smc(SMC_PWRC_SET, pwrc_domain->index, PWRC_ON,
+ 0, 0, 0, 0, 0, );
+
+ return 0;
+}
+
+#define SEC_PD(__name, __flag) \
+{ \
+ .name = #__name,\
+ .index = PWRC_##__name##_ID,\
+ .get_power = pwrc_secure_get_power, \
+ .flags = __flag,\
+}
+
+static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
+ SEC_PD(DSPA,0),
+ SEC_PD(DSPB,0),
+ SEC_PD(UART,GENPD_FLAG_ALWAYS_ON),
+ SEC_PD(DMC, GENPD_FLAG_ALWAYS_ON),
+ SEC_PD(I2C, 0),
+ SEC_PD(PSRAM, 0),
+ SEC_PD(ACODEC, 0),
+ SEC_PD(AUDIO, 0),
+ SEC_PD(OTP, 0),
+ SEC_PD(DMA, 0),
+ SEC_PD(SD_EMMC, 0),
+ SEC_PD(RAMA,0),
+ SEC_PD(RAMB,GENPD_FLAG_ALWAYS_ON),
+ SEC_PD(IR, 0),
+ SEC_PD(SPICC, 0),
+ SEC_PD(SPIFC, 0),
+ SEC_PD(USB, 0),
+ SEC_PD(NIC, GENPD_FLAG_ALWAYS_ON),
+ SEC_PD(PDMIN, 0),
[PATCH 0/3] arm64: meson: add support for A1 Power Domains
This patchset introduces a "Secure Power Doamin Controller". In A1/C1, power controller registers such as PWRCTRL_FOCRSTN, PWRCTRL_PWR_OFF, PWRCTRL_MEM_PD and PWRCTRL_ISO_EN, are in the secure domain, and should be accessed from ATF by smc. This patchset is based on A1 DTB series at [0]. [0] https://lore.kernel.org/linux-amlogic/1568276370-54181-1-git-send-email-jianxin@amlogic.com Jianxin Pan (3): dt-bindings: power: add Amlogic secure power domains bindings soc: amlogic: Add support for Secure power domains controller arm64: dts: meson: a1: add secure power domain controller .../bindings/power/amlogic,meson-sec-pwrc.yaml | 32 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 + drivers/soc/amlogic/Kconfig| 13 ++ drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-secure-pwrc.c| 182 + include/dt-bindings/power/meson-a1-power.h | 32 6 files changed, 266 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c create mode 100644 include/dt-bindings/power/meson-a1-power.h -- 2.7.4
Re: [PATCH v3 4/4] arm64: dts: add support for A1 based Amlogic AD401
Hi Neil,
On 2019/9/11 23:54, Neil Armstrong wrote:
> On 11/09/2019 17:38, Jianxin Pan wrote:
>> Add basic support for the Amlogic A1 based Amlogic AD401 board:
>> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
>> Timer, UART. It's capable of booting up into the serial console.
>>
>> Signed-off-by: Jianxin Pan
>> Reviewed-by: Jerome Brunet
>> ---
>> arch/arm64/boot/dts/amlogic/Makefile | 1 +
>> arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 ++
>> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 131
>> +
>> 3 files changed, 162 insertions(+)
[...]
>> +
>> +sm: secure-monitor {
>> +compatible = "amlogic,meson-gxbb-sm";
>> +};
>> +
>> +soc {
>> +compatible = "simple-bus";
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +ranges;
>> +
>> +
>> +apb: bus@0xfe00 {
>
> Should be bus@fe00
>
Thanks for your review.
I resent a new version and fixed it.
>> +compatible = "simple-bus";
>> +reg = <0x0 0xfe00 0x0 0x100>;
>> +#address-cells = <2>;
>> +#size-cells = <2>;
[...]
>> +xtal: xtal-clk {
>> +compatible = "fixed-clock";
>> +clock-frequency = <2400>;
>> +clock-output-names = "xtal";
>> +#clock-cells = <0>;
>> +};
>> +};
>>
>
> With that fixed:
> Reviewed-by: Neil Armstrong
>
> Neil
>
> .
>
[PATCH v4 3/4] dt-bindings: arm: amlogic: add Amlogic AD401 bindings
Add the compatible for the Amlogic A1 Based AD401 board. Signed-off-by: Jianxin Pan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 0ef45ac..ee5703c 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -159,5 +159,7 @@ properties: - description: Boards with the Amlogic Meson A1 A113L SoC items: + - enum: + - amlogic,ad401 - const: amlogic,a1 ... -- 2.7.4
[PATCH v4 2/4] dt-bindings: arm: amlogic: add A1 bindings
Add bindings for the new Amlogic A1 SoC family. A1 is an application processor designed for smart audio and IoT applications, with dual core Cortex-A35. Signed-off-by: Jianxin Pan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/amlogic.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 99015ce..0ef45ac 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -156,4 +156,8 @@ properties: - seirobotics,sei610 - khadas,vim3l - const: amlogic,sm1 + + - description: Boards with the Amlogic Meson A1 A113L SoC +items: + - const: amlogic,a1 ... -- 2.7.4
[PATCH v4 0/4] arm64: Add basic support for Amlogic A1 SoC Family
A1 is an application processor designed for smart audio and IoT applications, with Dual core ARM Cortex-A35 CPU. Unlike the previous GXL and G12 series, there is no Cortex-M3 AO CPU in it. This serial add basic support for the Amlogic A1 based Amlogic AD401 board: which describe components as follows: Reserve Memory, CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. The pclk for uart_AO_B need to be fixed once A1 clock driver is merged. In this version, it rely on bootloader to enable the pclk gate Changes since v3 at [2]: - remove 0x in bus Changes since v2 at [1]: - add bus in dts according Martin's suggestion - remove useless comment line Changes since v1 at [0]: - fix coding style - collect Reviewed-by [0] https://lore.kernel.org/linux-amlogic/1567493475-75451-1-git-send-email-jianxin@amlogic.com [1] https://lore.kernel.org/linux-amlogic/1567667251-33466-1-git-send-email-jianxin@amlogic.com [2] https://lore.kernel.org/linux-amlogic/1568216290-84219-1-git-send-email-jianxin@amlogic.com Jianxin Pan (4): soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs dt-bindings: arm: amlogic: add A1 bindings dt-bindings: arm: amlogic: add Amlogic AD401 bindings arm64: dts: add support for A1 based Amlogic AD401 Documentation/devicetree/bindings/arm/amlogic.yaml | 6 + arch/arm64/boot/dts/amlogic/Makefile | 1 + arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 + arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 130 + drivers/soc/amlogic/meson-gx-socinfo.c | 2 + 5 files changed, 169 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi -- 2.7.4
[PATCH v4 1/4] soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs
Add the SoC IDs for the A113L Amlogic A1 SoC.
Signed-off-by: Jianxin Pan
Reviewed-by: Neil Armstrong
---
drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c
b/drivers/soc/amlogic/meson-gx-socinfo.c
index 6d0d04f..3c86d8d 100644
--- a/drivers/soc/amlogic/meson-gx-socinfo.c
+++ b/drivers/soc/amlogic/meson-gx-socinfo.c
@@ -40,6 +40,7 @@ static const struct meson_gx_soc_id {
{ "G12A", 0x28 },
{ "G12B", 0x29 },
{ "SM1", 0x2b },
+ { "A1", 0x2c },
};
static const struct meson_gx_package_id {
@@ -68,6 +69,7 @@ static const struct meson_gx_package_id {
{ "S922X", 0x29, 0x40, 0xf0 },
{ "A311D", 0x29, 0x10, 0xf0 },
{ "S905X3", 0x2b, 0x5, 0xf },
+ { "A113L", 0x2c, 0x0, 0xf8 },
};
static inline unsigned int socinfo_to_major(u32 socinfo)
--
2.7.4
[PATCH v4 4/4] arm64: dts: add support for A1 based Amlogic AD401
Add basic support for the Amlogic A1 based Amlogic AD401 board:
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan
Reviewed-by: Jerome Brunet
Reviewed-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 ++
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 130 +
3 files changed, 161 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/Makefile
b/arch/arm64/boot/dts/amlogic/Makefile
index 84afecb..a90be52 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
new file mode 100644
index ..69c25c6
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-a1.dtsi"
+
+/ {
+ compatible = "amlogic,ad401", "amlogic,a1";
+ model = "Amlogic Meson A1 AD401 Development Board";
+
+ aliases {
+ serial0 = _AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x800>;
+ };
+};
+
+_AO_B {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
new file mode 100644
index ..7210ad0
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "amlogic,a1";
+
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x80>;
+ alignment = <0x0 0x40>;
+ linux,cma-default;
+ };
+ };
+
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gxbb-sm";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ apb: bus@fe00 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe00 0x0 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe00 0x0 0x100>;
+
+ uart_AO: serial@1c00 {
+ compatible = "amlogic,meson-gx-uart",
+"amlogic,meson-ao-uart";
+ reg = <0x0 0x1c00 0x0 0x18>;
+ interrupts = ;
+ clo
[PATCH v3 3/4] dt-bindings: arm: amlogic: add Amlogic AD401 bindings
Add the compatible for the Amlogic A1 Based AD401 board. Signed-off-by: Jianxin Pan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 0ef45ac..ee5703c 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -159,5 +159,7 @@ properties: - description: Boards with the Amlogic Meson A1 A113L SoC items: + - enum: + - amlogic,ad401 - const: amlogic,a1 ... -- 2.7.4
[PATCH v3 2/4] dt-bindings: arm: amlogic: add A1 bindings
Add bindings for the new Amlogic A1 SoC family. A1 is an application processor designed for smart audio and IoT applications, with dual core Cortex-A35. Signed-off-by: Jianxin Pan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/amlogic.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 99015ce..0ef45ac 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -156,4 +156,8 @@ properties: - seirobotics,sei610 - khadas,vim3l - const: amlogic,sm1 + + - description: Boards with the Amlogic Meson A1 A113L SoC +items: + - const: amlogic,a1 ... -- 2.7.4
[PATCH v3 0/4] arm64: Add basic support for Amlogic A1 SoC Family
A1 is an application processor designed for smart audio and IoT applications, with Dual core ARM Cortex-A35 CPU. Unlike the previous GXL and G12 series, there is no Cortex-M3 AO CPU in it. This serial add basic support for the Amlogic A1 based Amlogic AD401 board: which describe components as follows: Reserve Memory, CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. The pclk for uart_AO_B need to be fixed once A1 clock driver is merged. In this version, it rely on bootloader to enable the pclk gate Changes since v2 at [1]: - add bus in dts according Martin's suggestion - remove useless comment line Changes since v1 at [0]: - fix coding style - collect Reviewed-by [0] https://lore.kernel.org/linux-amlogic/1567493475-75451-1-git-send-email-jianxin@amlogic.com/ [1] https://lore.kernel.org/linux-amlogic/1567667251-33466-1-git-send-email-jianxin@amlogic.com Jianxin Pan (4): soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs dt-bindings: arm: amlogic: add A1 bindings dt-bindings: arm: amlogic: add Amlogic AD401 bindings arm64: dts: add support for A1 based Amlogic AD401 Documentation/devicetree/bindings/arm/amlogic.yaml | 6 + arch/arm64/boot/dts/amlogic/Makefile | 1 + arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 + arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 131 + drivers/soc/amlogic/meson-gx-socinfo.c | 2 + 5 files changed, 170 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi -- 2.7.4
[PATCH v3 1/4] soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs
Add the SoC IDs for the A113L Amlogic A1 SoC.
Signed-off-by: Jianxin Pan
Reviewed-by: Neil Armstrong
---
drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c
b/drivers/soc/amlogic/meson-gx-socinfo.c
index 6d0d04f..3c86d8d 100644
--- a/drivers/soc/amlogic/meson-gx-socinfo.c
+++ b/drivers/soc/amlogic/meson-gx-socinfo.c
@@ -40,6 +40,7 @@ static const struct meson_gx_soc_id {
{ "G12A", 0x28 },
{ "G12B", 0x29 },
{ "SM1", 0x2b },
+ { "A1", 0x2c },
};
static const struct meson_gx_package_id {
@@ -68,6 +69,7 @@ static const struct meson_gx_package_id {
{ "S922X", 0x29, 0x40, 0xf0 },
{ "A311D", 0x29, 0x10, 0xf0 },
{ "S905X3", 0x2b, 0x5, 0xf },
+ { "A113L", 0x2c, 0x0, 0xf8 },
};
static inline unsigned int socinfo_to_major(u32 socinfo)
--
2.7.4
[PATCH v3 4/4] arm64: dts: add support for A1 based Amlogic AD401
Add basic support for the Amlogic A1 based Amlogic AD401 board:
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan
Reviewed-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 ++
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 131 +
3 files changed, 162 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/Makefile
b/arch/arm64/boot/dts/amlogic/Makefile
index 84afecb..a90be52 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
new file mode 100644
index ..69c25c6
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-a1.dtsi"
+
+/ {
+ compatible = "amlogic,ad401", "amlogic,a1";
+ model = "Amlogic Meson A1 AD401 Development Board";
+
+ aliases {
+ serial0 = _AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x800>;
+ };
+};
+
+_AO_B {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
new file mode 100644
index ..7da448c
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "amlogic,a1";
+
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x80>;
+ alignment = <0x0 0x40>;
+ linux,cma-default;
+ };
+ };
+
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gxbb-sm";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+
+ apb: bus@0xfe00 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe00 0x0 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe00 0x0 0x100>;
+
+ uart_AO: serial@1c00 {
+ compatible = "amlogic,meson-gx-uart",
+"amlogic,meson-ao-uart";
+ reg = <0x0 0x1c00 0x0 0x18>;
+ interrupts = ;
+ clo
Re: [PATCH v2 4/4] arm64: dts: add support for A1 based Amlogic AD401
Hi Martin, On 2019/9/10 1:24, Martin Blumenstingl wrote: > Hi Jianxin, > > On Mon, Sep 9, 2019 at 2:03 PM Jianxin Pan wrote: >> >> Hi Martin, >> >> On 2019/9/7 23:02, Martin Blumenstingl wrote: >>> Hi Jianxin, >>> >>> On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote: >>> [...] >>>>> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, >>>>> ...) here >>>>> aren't there any busses defined in the A1 SoC implementation or are >>>>> were you planning to add them later? >>>> Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no >>>> AO/EE power domain. >>>> Most of the registers are on the apb_32b bus. aobus, cbus and periphs are >>>> not used in A1. >>> OK, thank you for the explanation >>> since you're going to re-send the patch anyways: can you please >>> include the apb_32b bus? >>> all other upstream Amlogic .dts are using the bus definitions, so that >>> will make A1 consistent with the other SoCs >> In A1 (and the later C1), BUS is not mentioned in the memmap and register >> spec. >> Registers are organized and grouped by functions, and we can not find >> information about buses from the SoC document. > do you know why the busses are not part of the documentation? > >> Maybe it's better to remove bus definitions for these chips. > my understanding is that devicetree describes the hardware > so if there's a bus in hardware (that we know about) then we should > describe it in devicetree > > personally I think busses also make the .dts easier to read: > instead of a huge .dts with all nodes on one level it's split into > multiple smaller sub-nodes - thus making it easier to keep track of > "where am I in this file". > OK, I will add the bus description for A1. Thank you for your suggestion. > > Martin > > . >
Re: [PATCH v2 4/4] arm64: dts: add support for A1 based Amlogic AD401
Hi Jerome, On 2019/9/9 19:36, Jerome Brunet wrote: > > On Sat 07 Sep 2019 at 17:02, Martin Blumenstingl wrote: > >> Hi Jianxin, >> >> On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote: >> [...] >>>> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...) >>>> here >>>> aren't there any busses defined in the A1 SoC implementation or are >>>> were you planning to add them later? >>> Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no >>> AO/EE power domain. >>> Most of the registers are on the apb_32b bus. aobus, cbus and periphs are >>> not used in A1. >> OK, thank you for the explanation >> since you're going to re-send the patch anyways: can you please >> include the apb_32b bus? > > unless there is an 64 bits apb bus as well, I suppose 'apb' would be enough ? > There is no 64bits apb bus in A1, only apb32. Unlike the previous series, For A1 and C1, we can not get bus information for each register from the memmap and datesheet. Do we need to add bus description for them too? If yes, I can add 'apb' . >> all other upstream Amlogic .dts are using the bus definitions, so that >> will make A1 consistent with the other SoCs >> >> >> Martin > > . >
Re: [PATCH v2 4/4] arm64: dts: add support for A1 based Amlogic AD401
Hi Martin, On 2019/9/7 23:02, Martin Blumenstingl wrote: > Hi Jianxin, > > On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote: > [...] >>> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...) >>> here >>> aren't there any busses defined in the A1 SoC implementation or are >>> were you planning to add them later? >> Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no >> AO/EE power domain. >> Most of the registers are on the apb_32b bus. aobus, cbus and periphs are >> not used in A1. > OK, thank you for the explanation > since you're going to re-send the patch anyways: can you please > include the apb_32b bus? > all other upstream Amlogic .dts are using the bus definitions, so that > will make A1 consistent with the other SoCs In A1 (and the later C1), BUS is not mentioned in the memmap and register spec. Registers are organized and grouped by functions, and we can not find information about buses from the SoC document. Maybe it's better to remove bus definitions for these chips. > > > Martin > > . >
Re: [PATCH v2 4/4] arm64: dts: add support for A1 based Amlogic AD401
Hi Martin,
Thanks for the review, we really appreciate your time.
Please see my comments below.
On 2019/9/6 4:15, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> (it's great to see that you and your team are upstreaming this early)
>
> On Thu, Sep 5, 2019 at 9:08 AM Jianxin Pan wrote:
> [...]
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x800>;
>> + /*linux,usable-memory = <0x0 0x0 0x0 0x800>;*/
> why do we need that comment here (I don't understand it - why doesn't
> the "reg" property cover this)?
> I replaced "linux,usable-memory" with reg, but forgot to remove this comment
> line.
I will remove this line in the next version. Thank you.
>> + };
>> +};
>> +
>> +_AO_B {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> new file mode 100644
>> index ..4d476ac
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> @@ -0,0 +1,122 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +/ {
>> + compatible = "amlogic,a1";
>> +
>> + interrupt-parent = <>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <0x2>;
>> + #size-cells = <0x0>;
> only now I notice that all our other .dtsi also use hex values
> (instead of decimal as just a few lines above) here
> do you know if there is a particular reason for this?
>
I just copied from the previous series, and didn't notice the difference
before.> [...]
>> + uart_AO_B: serial@fe002000 {
>> + compatible = "amlogic,meson-gx-uart",
>> +"amlogic,meson-ao-uart";
>> +reg = <0x0 0xfe002000 0x0 0x18>;
> the indentation of the "reg" property is off here
OK, I will fix it.
>
> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...)
> here
> aren't there any busses defined in the A1 SoC implementation or are
> were you planning to add them later?
>Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no
>AO/EE power domain.
Most of the registers are on the apb_32b bus. aobus, cbus and periphs are not
used in A1.
>
> Martin
>
> .
>
[PATCH v2 2/4] dt-bindings: arm: amlogic: add A1 bindings
Add bindings for the new Amlogic A1 SoC family. A1 is an application processor designed for smart audio and IoT applications, with dual core Cortex-A35. Signed-off-by: Jianxin Pan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/amlogic.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 99015ce..0ef45ac 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -156,4 +156,8 @@ properties: - seirobotics,sei610 - khadas,vim3l - const: amlogic,sm1 + + - description: Boards with the Amlogic Meson A1 A113L SoC +items: + - const: amlogic,a1 ... -- 2.7.4
[PATCH v2 3/4] dt-bindings: arm: amlogic: add Amlogic AD401 bindings
Add the compatible for the Amlogic A1 Based AD401 board. Signed-off-by: Jianxin Pan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 0ef45ac..ee5703c 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -159,5 +159,7 @@ properties: - description: Boards with the Amlogic Meson A1 A113L SoC items: + - enum: + - amlogic,ad401 - const: amlogic,a1 ... -- 2.7.4
[PATCH v2 4/4] arm64: dts: add support for A1 based Amlogic AD401
Add basic support for the Amlogic A1 based Amlogic AD401 board:
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan
Reviewed-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 31 +++
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 122 +
3 files changed, 154 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/Makefile
b/arch/arm64/boot/dts/amlogic/Makefile
index 84afecb..a90be52 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
new file mode 100644
index ..190dedf
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-a1.dtsi"
+
+/ {
+ compatible = "amlogic,ad401", "amlogic,a1";
+ model = "Amlogic Meson A1 AD401 Development Board";
+
+ aliases {
+ serial0 = _AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x800>;
+ /*linux,usable-memory = <0x0 0x0 0x0 0x800>;*/
+ };
+};
+
+_AO_B {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
new file mode 100644
index ..4d476ac
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "amlogic,a1";
+
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x80>;
+ alignment = <0x0 0x40>;
+ linux,cma-default;
+ };
+ };
+
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gxbb-sm";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart_AO: serial@fe001c00 {
+ compatible = "amlogic,meson-gx-uart",
+"amlogic,meson-ao-uart";
+ reg = <0x0 0xfe001c00 0x0 0x18>;
+ interrupts = ;
+ clocks = <>, <>, <>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_AO_B: serial@fe002000 {
+ compatible = "amlogic,meson-gx-uart"
[PATCH v2 1/4] soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs
Add the SoC IDs for the A113L Amlogic A1 SoC.
Signed-off-by: Jianxin Pan
Reviewed-by: Neil Armstrong
---
drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c
b/drivers/soc/amlogic/meson-gx-socinfo.c
index 6d0d04f..3c86d8d 100644
--- a/drivers/soc/amlogic/meson-gx-socinfo.c
+++ b/drivers/soc/amlogic/meson-gx-socinfo.c
@@ -40,6 +40,7 @@ static const struct meson_gx_soc_id {
{ "G12A", 0x28 },
{ "G12B", 0x29 },
{ "SM1", 0x2b },
+ { "A1", 0x2c },
};
static const struct meson_gx_package_id {
@@ -68,6 +69,7 @@ static const struct meson_gx_package_id {
{ "S922X", 0x29, 0x40, 0xf0 },
{ "A311D", 0x29, 0x10, 0xf0 },
{ "S905X3", 0x2b, 0x5, 0xf },
+ { "A113L", 0x2c, 0x0, 0xf8 },
};
static inline unsigned int socinfo_to_major(u32 socinfo)
--
2.7.4
[PATCH v2 0/4] arm64: Add basic support for Amlogic A1 SoC Family
A1 is an application processor designed for smart audio and IoT applications, with Dual core ARM Cortex-A35 CPU. Unlike the previous GXL and G12 series, there is no Cortex-M3 AO CPU in it. This serial add basic support for the Amlogic A1 based Amlogic AD401 board: which describe components as follows: Reserve Memory, CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. The pclk for uart_AO_B need to be fixed once A1 clock driver is merged. In this version, it rely on bootloader to enable the pclk gate Changes since v1 [0]: - fix coding style - collect Reviewed-by [0] https://lore.kernel.org/linux-amlogic/1567493475-75451-1-git-send-email-jianxin@amlogic.com/ Jianxin Pan (4): soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs dt-bindings: arm: amlogic: add A1 bindings dt-bindings: arm: amlogic: add Amlogic AD401 bindings arm64: dts: add support for A1 based Amlogic AD401 Documentation/devicetree/bindings/arm/amlogic.yaml | 6 + arch/arm64/boot/dts/amlogic/Makefile | 1 + arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 31 ++ arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 122 + drivers/soc/amlogic/meson-gx-socinfo.c | 2 + 5 files changed, 162 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi -- 2.7.4
Re: [PATCH 4/4] arm64: dts: add support for A1 based Amlogic AD401
Hi Neil,
Thanks for your time.
Please see my comments below.
On 2019/9/3 15:42, Neil Armstrong wrote:
> Hi,
>
> On 03/09/2019 08:51, Jianxin Pan wrote:
>> Add basic support for the Amlogic A1 based Amlogic AD401 board:
>> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
[...]
>> +chosen {
>> +stdout-path = "serial0:115200n8";
>> +};
>> +memory@0 {
>> +device_type = "memory";
>> +linux,usable-memory = <0x0 0x0 0x0 0x800>;
>
> I'll prefer usage of reg, it's handled the same but linux,usable-memory
> is not documented.
>
OK, I will fix it in the next version. Thanks for your review.
>> +};
>> +};
>> +
>> +_AO_B {
>> +status = "okay";
>> +/*pinctrl-0 = <_ao_a_pins>;*/
>> +/*pinctrl-names = "default";*/
>
> Please remove these lines instead of commenting them.
>
OK, I will fix it in the next version.
>> +};
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> new file mode 100644
>> index ..b98d648
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> @@ -0,0 +1,121 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +/ {
[...]
>> +
>> +reserved-memory {
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +ranges;
>
> Isn't there secmon reserved memory ?
>
A1 uses internal SRAM as secmon memory.
And there is no secmon reserved memory in ddr side.
>> +
>> +linux,cma {
>> +compatible = "shared-dma-pool";
>> +reusable;
>> +size = <0x0 0x80>;
[...]
>>
>
> Thanks,
> Neil
>
> .
>
Re: [PATCH 4/4] arm64: dts: add support for A1 based Amlogic AD401
Hi Jerome,
Thanks for your suggestion.
I will fix them in the next version.
On 2019/9/3 15:30, Jerome Brunet wrote:
> On Tue 03 Sep 2019 at 02:51, Jianxin Pan wrote:
>
>> Add basic support for the Amlogic A1 based Amlogic AD401 board:
>> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
>> Timer, UART. It's capable of booting up into the serial console.
>>
>> Signed-off-by: Jianxin Pan
>> ---
>> arch/arm64/boot/dts/amlogic/Makefile | 1 +
>> arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 ++
>> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 121
>> +
>> 3 files changed, 152 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
>> create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
>> b/arch/arm64/boot/dts/amlogic/Makefile
>> index edbf128..1720c45 100644
>> --- a/arch/arm64/boot/dts/amlogic/Makefile
>> +++ b/arch/arm64/boot/dts/amlogic/Makefile
>> @@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
>> +dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
>> b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
>> new file mode 100644
>> index ..3c05cc0
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "meson-a1.dtsi"
>> +
>> +/ {
>> +compatible = "amlogic,ad401", "amlogic,a1";
>> +model = "Amlogic Meson A1 AD401 Development Board";
>> +
>> +aliases {
>> +serial0 = _AO_B;
>> +};
>
> Newline here please
>
>> +chosen {
>> +stdout-path = "serial0:115200n8";
>> +};
>
> same
>
>> +memory@0 {
>> +device_type = "memory";
>> +linux,usable-memory = <0x0 0x0 0x0 0x800>;
>> +};
>> +};
>> +
>> +_AO_B {
>> +status = "okay";
>> +/*pinctrl-0 = <_ao_a_pins>;*/
>> +/*pinctrl-names = "default";*/
>
> Remove the commented code please
>
>> +};
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> new file mode 100644
>> index ..b98d648
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> @@ -0,0 +1,121 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +/ {
>> +compatible = "amlogic,a1";
>> +
>> +interrupt-parent = <>;
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +
>> +cpus {
>> +#address-cells = <0x2>;
>> +#size-cells = <0x0>;
>> +
>> +cpu0: cpu@0 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a35";
>> +reg = <0x0 0x0>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +cpu1: cpu@1 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a35";
>> +reg = <0x0 0x1>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +l2: l2-cache0 {
>> +compatible = "cache";
>> +};
>> +};
>
> New line here please
>
> With this minor comments adressed, looks good.
>
> Reviewed-by: Jerome Brunet
>
>> +psci {
>> +compatible = "arm,psci-1.0";
>> +method = "smc";
>> +};
>> +
>> +reserved-memory {
>> +#address-cells = <2
[PATCH 2/4] dt-bindings: arm: amlogic: add A1 bindings
Add bindings for the new Amlogic A1 SoC family. A1 is an application processor designed for smart audio and IoT applications, with dual core Cortex-A35. Signed-off-by: Jianxin Pan --- Documentation/devicetree/bindings/arm/amlogic.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index b48ea1e..aa07b76 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -155,4 +155,8 @@ properties: - seirobotics,sei610 - khadas,vim3l - const: amlogic,sm1 + + - description: Boards with the Amlogic Meson A1 A113L SoC +items: + - const: amlogic,a1 ... -- 2.7.4
[PATCH 4/4] arm64: dts: add support for A1 based Amlogic AD401
Add basic support for the Amlogic A1 based Amlogic AD401 board:
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 ++
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 121 +
3 files changed, 152 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/Makefile
b/arch/arm64/boot/dts/amlogic/Makefile
index edbf128..1720c45 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
new file mode 100644
index ..3c05cc0
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-a1.dtsi"
+
+/ {
+ compatible = "amlogic,ad401", "amlogic,a1";
+ model = "Amlogic Meson A1 AD401 Development Board";
+
+ aliases {
+ serial0 = _AO_B;
+ };
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+ memory@0 {
+ device_type = "memory";
+ linux,usable-memory = <0x0 0x0 0x0 0x800>;
+ };
+};
+
+_AO_B {
+ status = "okay";
+ /*pinctrl-0 = <_ao_a_pins>;*/
+ /*pinctrl-names = "default";*/
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
new file mode 100644
index ..b98d648
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "amlogic,a1";
+
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x80>;
+ alignment = <0x0 0x40>;
+ linux,cma-default;
+ };
+ };
+
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gxbb-sm";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart_AO: serial@fe001c00 {
+ compatible = "amlogic,meson-gx-uart",
+"amlogic,meson-ao-uart";
+ reg = <0x0 0xfe001c00 0x0 0x18>;
+ interrupts = ;
+ clocks = <>, <>, <>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_AO_B: serial@fe002000 {
+ compatible = "amlogic,meson-gx-
[PATCH 1/4] soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs
Add the SoC IDs for the A113L Amlogic A1 SoC.
Signed-off-by: Jianxin Pan
---
drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c
b/drivers/soc/amlogic/meson-gx-socinfo.c
index 6d0d04f..3c86d8d 100644
--- a/drivers/soc/amlogic/meson-gx-socinfo.c
+++ b/drivers/soc/amlogic/meson-gx-socinfo.c
@@ -40,6 +40,7 @@ static const struct meson_gx_soc_id {
{ "G12A", 0x28 },
{ "G12B", 0x29 },
{ "SM1", 0x2b },
+ { "A1", 0x2c },
};
static const struct meson_gx_package_id {
@@ -68,6 +69,7 @@ static const struct meson_gx_package_id {
{ "S922X", 0x29, 0x40, 0xf0 },
{ "A311D", 0x29, 0x10, 0xf0 },
{ "S905X3", 0x2b, 0x5, 0xf },
+ { "A113L", 0x2c, 0x0, 0xf8 },
};
static inline unsigned int socinfo_to_major(u32 socinfo)
--
2.7.4
[PATCH 3/4] dt-bindings: arm: amlogic: add Amlogic AD401 bindings
Add the compatible for the Amlogic A1 Based AD401 board. Signed-off-by: Jianxin Pan --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index aa07b76..dc4abce 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -158,5 +158,7 @@ properties: - description: Boards with the Amlogic Meson A1 A113L SoC items: + - enum: + - amlogic,ad401 - const: amlogic,a1 ... -- 2.7.4
[PATCH 0/4] arm64: Add basic support for Amlogic A1 SoC Family
A1 is an application processor designed for smart audio and IoT applications, with Dual core ARM Cortex-A35 CPU. Unlike the previous GXL and G12 series, there is no Cortex-M3 AO CPU in it. This serial add basic support for the Amlogic A1 based Amlogic AD401 board: which describe components as follows: Reserve Memory, CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. The pclk for uart_AO_B need to be fixed once A1 clock driver is merged. In this version, it rely on bootloader to enable the pclk gate Jianxin Pan (4): soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs dt-bindings: arm: amlogic: add A1 bindings dt-bindings: arm: amlogic: add Amlogic AD401 bindings arm64: dts: add support for A1 based Amlogic AD401 Documentation/devicetree/bindings/arm/amlogic.yaml | 6 + arch/arm64/boot/dts/amlogic/Makefile | 1 + arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 + arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 121 + drivers/soc/amlogic/meson-gx-socinfo.c | 2 + 5 files changed, 160 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi -- 2.7.4
Re: [PATCH v9 1/4] clk: meson: add one based divider support for sclk divider
Hi Jerome,
On 2019/1/22 17:25, Jerome Brunet wrote:
> On Tue, 2019-01-08 at 21:50 +0800, Jianxin Pan wrote:
>> When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
>> one based divider (div = val), and zero value gates the clock
>>
>> Signed-off-by: Jianxin Pan
>> ---
>> drivers/clk/meson/Makefile | 3 ++-
>> drivers/clk/meson/clkc-audio.h | 8 --
>> drivers/clk/meson/clkc.h | 10 ++-
>> drivers/clk/meson/sclk-div.c | 59 ---
>> ---
>> 4 files changed, 50 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index a849aa8..acd8694 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -4,7 +4,8 @@
>>
>> obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o vid-
>> pll-div.o
>> obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o
>> -obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
>> +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += sclk-div.o
>> +obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o
>> obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>> obj-$(CONFIG_COMMON_CLK_GXBB)+= gxbb.o gxbb-aoclk.o gxbb-aoclk-
>> 32k.o
>> diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
>> index 0a7c157..286ff12 100644
>> --- a/drivers/clk/meson/clkc-audio.h
>> +++ b/drivers/clk/meson/clkc-audio.h
>> @@ -15,14 +15,6 @@ struct meson_clk_triphase_data {
>> struct parm ph2;
>> };
>>
>> -struct meson_sclk_div_data {
>> -struct parm div;
>> -struct parm hi;
>> -unsigned int cached_div;
>> -struct clk_duty cached_duty;
>> -};
>> -
>> extern const struct clk_ops meson_clk_triphase_ops;
>> -extern const struct clk_ops meson_sclk_div_ops;
>>
>> #endif /* __MESON_CLKC_AUDIO_H */
>> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
>> index 6183b22..00b3320 100644
>> --- a/drivers/clk/meson/clkc.h
>> +++ b/drivers/clk/meson/clkc.h
>> @@ -27,6 +27,14 @@ struct parm {
>> u8 width;
>> };
>>
>> +struct meson_sclk_div_data {
>> +struct parm div;
>> +struct parm hi;
>> +unsigned int cached_div;
>> +struct clk_duty cached_duty;
>> +u8 flags;
>> +};
>> +
>> static inline unsigned int meson_parm_read(struct regmap *map, struct parm
>> *p)
>> {
>> unsigned int val;
>> @@ -118,10 +126,10 @@ struct clk_regmap _name = {
>> \
>> extern const struct clk_ops meson_clk_mpll_ops;
>> extern const struct clk_ops meson_clk_phase_ops;
>> extern const struct clk_ops meson_vid_pll_div_ro_ops;
>> +extern const struct clk_ops meson_sclk_div_ops;
>>
>> struct clk_hw *meson_clk_hw_register_input(struct device *dev,
>> const char *of_name,
>> const char *clk_name,
>> unsigned long flags);
>> -
>> #endif /* __CLKC_H */
>> diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c
>> index bc64019..a6c425b 100644
>> --- a/drivers/clk/meson/sclk-div.c
>> +++ b/drivers/clk/meson/sclk-div.c
>> @@ -4,42 +4,60 @@
>> * Author: Jerome Brunet
>> *
>> * Sample clock generator divider:
>> - * This HW divider gates with value 0 but is otherwise a zero based
>> divider:
>> + * This HW divider gates with value 0
>> *
>> * val >= 1
>> - * divider = val + 1
>> + * divider = val + 1 if ONE_BASED is not set, otherwise divider = val.
>> *
>> * The duty cycle may also be set for the LR clock variant. The duty cycle
>> * ratio is:
>> *
>> * hi = [0 - val]
>> - * duty_cycle = (1 + hi) / (1 + val)
>> + * duty_cycle = (1 + hi) / (1 + val) if ONE_BASED is not set, otherwise:
>> + * duty_cycle = hi / (1 + val)
>> */
>>
>> -#include "clkc-audio.h"
>> +#include "clkc.h"
>>
>> -static inline struct meson_sclk_div_data *
>> -meson_sclk_div_data(struct clk_regmap *clk)
>> +static inline int get_reg(int val, unsigned char flag)
>
> s/get_reg/sclk_get_reg
OK, I will rename get_reg and get_value in next version.
Thank you for the review.
>
>> {
>> -return (struct meson_sclk_div_data *)clk->data;
>> +WARN_ON
Re: [PATCH] MAINTAINERS: Add entry for Amlogic NAND controller driver
Hi Miquel, On 2019/1/20 23:06, Miquel Raynal wrote: > Hi Jianxin, > > Jianxin Pan wrote on Sun, 20 Jan 2019 > 01:02:35 +0800: > >> Add entry for Amlogic NAND controller driver and its bindings[0]. >> >> [0] >> https://lore.kernel.org/lkml/1547566684-57472-1-git-send-email-jianxin@amlogic.com/ >> >> Signed-off-by: Liang Yang >> Signed-off-by: Jianxin Pan > > If you are the author of the patch your Signed-off-by should come first. OK. > > Also, why is Liang the Maintainer? Why not you? > Yangliang is Amlogic maintainer for NAND controller. And all patches about amlogic NAND controller are from him. >> --- >> MAINTAINERS | 7 +++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 0abecc5..7d976a1 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -9628,6 +9628,13 @@ F:drivers/media/platform/meson/ao-cec.c >> F: Documentation/devicetree/bindings/media/meson-ao-cec.txt >> T: git git://linuxtv.org/media_tree.git >> >> +MESON NAND CONTROLLER DRIVER FOR AMLOGIC SOCS >> +M: Liang Yang >> +L: linux-...@lists.infradead.org >> +S: Maintained >> +F: drivers/mtd/nand/raw/meson_* >> +F: Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt >> + >> MICROBLAZE ARCHITECTURE >> M: Michal Simek >> W: http://www.monstr.eu/fdt/ > > Thanks, > Miquèl > > . >
[PATCH] MAINTAINERS: Add entry for Amlogic NAND controller driver
Add entry for Amlogic NAND controller driver and its bindings[0]. [0] https://lore.kernel.org/lkml/1547566684-57472-1-git-send-email-jianxin@amlogic.com/ Signed-off-by: Liang Yang Signed-off-by: Jianxin Pan --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0abecc5..7d976a1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9628,6 +9628,13 @@ F: drivers/media/platform/meson/ao-cec.c F: Documentation/devicetree/bindings/media/meson-ao-cec.txt T: git git://linuxtv.org/media_tree.git +MESON NAND CONTROLLER DRIVER FOR AMLOGIC SOCS +M: Liang Yang +L: linux-...@lists.infradead.org +S: Maintained +F: drivers/mtd/nand/raw/meson_* +F: Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt + MICROBLAZE ARCHITECTURE M: Michal Simek W: http://www.monstr.eu/fdt/ -- 1.9.1
Re: [PATCH v9 0/2] mtd: rawnand: meson: add Amlogic NAND driver support
Hi Miquel, On 2019/1/16 0:52, Miquel Raynal wrote: > Hi Jianxin, > > Jianxin Pan wrote on Tue, 15 Jan 2019 > 23:38:02 +0800: > >> These two patches try to add initial NAND driver support for Amlogic Meson >> SoCs, current it has been tested on GXL(p212) and AXG(s400) platform. >> >> Changes since V8 at [9] >> - fix build failre at object_is_on_stack >> - update Kconfig as Martin's suggested > > Thanks for this last version, looks good to me. Could you please send a > patch to add a MAINTAINERS entry? > OK. > Also, can we face any deadly failure if someone compiles this driver > without the MMC clock driver updated? > Without the MMC clock driver 1) This driver can be built successfully. 2) The probe will fail when get clocks defined in MMC clock driver. > Thanks, > Miquèl > > . >
Re: [PATCH] arm64: dts: meson: fix g12a buses
Hi Martin and Jerome, On 2019/1/18 5:20, Martin Blumenstingl wrote: > On Thu, Jan 17, 2019 at 9:39 PM Jerome Brunet wrote: >> >> On Thu, 2019-01-17 at 21:27 +0100, Martin Blumenstingl wrote: >>> OK, but we had incorrect documentation in the past. did you check this >>> with someone from Amlogic? >>> >>> I'm curious because there seem to be two different approaches here: >>> 1) hiubus name and offsets are being fixed within this patch >>> 2) aobus is being dropped here and re-introduced with a different name later >>> on >>> >> >> because hiu exist and aobus does not, for which both the name and size was >> wrong >> >>> approach 1) can also be used for the "rti" region (at least in my >>> opinion, the patch doesn't explain why it can't be done): >> >> THe patch remove aobus (instead of fixing name and size) because, of the >> multiple region documented covered by this 'made region', I did not >> anticipate >> which one will be required and I did not want to add them all. >> >> Better to add them as needed, which is want I done for pinctrl as you pointed >> out >> >>> rename "aobus" to "rti" and change the size to either 0x1000 or 0xb000 >>> (both values can be found in mesong12a.dtsi from >>> buildroot_openlinux_kernel_4.9_fbdev_20180706) >> >> RTI is added here: >> https://lkml.kernel.org/r/20190117103151.3349-1-jbru...@baylibre.com >> >> I don't really understand the problem ? result is the same > the actual problem is "me" as I have conflicting information: > - Amlogic's buildroot kernel (for G12A) uses similar bus definitions > as the GX SoCs (for which there are public datasheets) - this is how > Jianxin added it to meson-g12a.dtsi originally > - this patch does it different - but cannot check if this is correct > (no public datasheet is available for G12A or AXG) nor do I have a > "big picture" of upcoming changes > > Cc'ing Jianxin: can you please review Jerome's patch and give some > more details on the memory map on G12A so further contributions can be > reviewed easier? > 1. "aobus: bus@ff80" describes the following registers: ahb ao_reg reserved980 FF80B000 ahb ao_reg ao_mailbox 4 FF80A000 ahb ao_reg sar_adc 4 FF809000 ahb ao_reg ir_dec 4 FF808000 ahb ao_reg pwm_ab 4 FF807000 ahb ao_reg i2c_s 4 FF806000 ahb ao_reg i2c_m 4 FF805000 ahb ao_reg uart2 4 FF804000 ahb ao_reg uart4 FF803000 ahb ao_reg pwm_cd 4 FF802000 ahb ao_reg reserved4 FF801000 ahb ao_reg rti 4 FF80 2. "cbus: bus@ffd0" describes the following registers: capb3 cbusreserved872 FFD26000FFDF capb3 cbussc 4 FFD25000FFD25FFF capb3 cbusuart0 4 FFD24000FFD24FFF capb3 cbusuart1 4 FFD23000FFD23FFF capb3 cbusuart2 4 FFD22000FFD22FFF capb3 cbusreserved4 FFD21000FFD21FFF capb3 cbusreserved4 FFD2FFD20FFF capb3 cbusi2c_m0 4 FFD1F000FFD1 capb3 cbusi2c_m1 4 FFD1E000FFD1EFFF capb3 cbusi2c_m2 4 FFD1D000FFD1DFFF capb3 cbusi2c_m3 4 FFD1C000FFD1CFFF capb3 cbuspwm_ab 4 FFD1B000FFD1BFFF capb3 cbuspwm_cd 4 FFD1A000FFD1AFFF capb3 cbuspwm_ef 4 FFD19000FFD19FFF capb3 cbusmsr_clk 4 FFD18000FFD18FFF capb3 cbusreserved4 FFD17000FFD17FFF capb3 cbusreserved4 FFD16000FFD16FFF capb3 cbusspicc_1 4 FFD15000FFD15FFF capb3 cbusspifc 4 FFD14000FFD14FFF capb3 cbusspicc_0 4 FFD13000FFD13FFF capb3 cbusreserved4 FFD12000FFD12FFF capb3 cbusreserved4 FFD11000FFD11FFF capb3 cbusreserved4 FFD1FFD10FFF capb3 cbusisa 4 FFD0F000FFD0 capb3 cbusparser 4 FFD0E000FFD0EFFF capb3 cbusreserved4 FFD0D000FFD0DFFF capb3 cbussana4 FFD0C000FFD0CFFF capb3 cbusstream 4 FFD0B000FFD0BFFF capb3 cbusasync_fifo 4 FFD0A000FFD0AFFF capb3 cbusasync_fifo2 4 FFD09000FFD09FFF capb3 cbusassist 4 FFD08000FFD08FFF capb3 cbusmipi_dsi_host 4 FFD07000FFD07FFF capb3 cbusstb 4 FFD06000FFD06FFF capb3 cbusaififo 4 FFD05000FFD05FFF capb3 cbusreserved4 FFD04000
Re: [PATCH v8 4/4] clk: meson: add sub MMC clock controller driver
Hi Stephen,
Thank you for your time.
Please see my comments below.
On 2019/1/10 4:48, Stephen Boyd wrote:
> Quoting Jianxin Pan (2018-12-17 08:24:10)
>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>> new file mode 100644
>> index 000..2582a98
>> --- /dev/null
>> +++ b/drivers/clk/meson/mmc-clkc.c
>> @@ -0,0 +1,304 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Amlogic Meson MMC Sub Clock Controller Driver
>> + *
>> + * Copyright (c) 2017 Baylibre SAS.
>> + * Author: Jerome Brunet
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Yixun Lan
>> + * Author: Jianxin Pan
>> + */
>> +
>> +#include
>
> Do you need this include?
>
Yes, It's also a clock-consumer.
devm_clk_get() gets clock from dts as the parent of mux.
Thank you for your review.
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>
> Is this used?
Yes, syscon_node_to_regmap() is used in mmc_clkc_probe().
>
>> +#include
> [...]
>> + init.num_parents = 1;
>> +
>> + clk = mmc_clkc_register_clk(dev, map, , suffix, data);
>> + if (IS_ERR(clk))
>> + dev_err(dev, "%s clock registration failed\n", suffix);
>> +
>> + return clk;
>> +}
>> +
>> +static int mmc_clkc_probe(struct platform_device *pdev)
>> +{
>> + struct clk_hw_onecell_data *onecell_data;
>> + struct device *dev = >dev;
>> + struct mmc_clkc_data *data;
>> + struct regmap *map;
>> + struct clk_regmap *clk, *core;
>> + struct meson_sclk_div_data *div_data;
>> +
>> + /*cast to drop the const in match->data*/
>> + data = (struct mmc_clkc_data *)of_device_get_match_data(dev);
>
> Is that necessary? Maybe the users of this should take a const argument
> and copy things?
OK, I can alloc two extra memory for PHASE_RX and PHASE_TX data, and then copy
from const data to them.
>
>> + if (!data)
>> + return -ENODEV;
>> +
>> + map = syscon_node_to_regmap(dev->of_node);
>> + if (IS_ERR(map)) {
>> + dev_err(dev, "could not find mmc clock controller\n");
>> + return PTR_ERR(map);
>> + }
>> +
>> + onecell_data = devm_kzalloc(dev, sizeof(*onecell_data) +
>> + sizeof(*onecell_data->hws) *
>> MMC_MAX_CLKS,
>
> struct_size()?
>
OK, I will change it in the next version.
Thank you for your review.
> .
>
[PATCH v9 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller
From: Liang Yang Add initial support for the Amlogic NAND flash controller which foundi in the Meson SoCs. Signed-off-by: Liang Yang Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- drivers/mtd/nand/raw/Kconfig |8 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/meson_nand.c | 1468 + 3 files changed, 1477 insertions(+) create mode 100644 drivers/mtd/nand/raw/meson_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 1a55d3e..2ebbcbf 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -541,4 +541,12 @@ config MTD_NAND_TEGRA is supported. Extra OOB bytes when using HW ECC are currently not supported. +config MTD_NAND_MESON + tristate "Support for NAND controller on Amlogic's Meson SoCs" + depends on ARCH_MESON || COMPILE_TEST + select MFD_SYSCON + help + Enables support for NAND controller on Amlogic's Meson SoCs. + This controller is found on Meson SoCs. + endif # MTD_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 57159b3..a2cc2fe 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o +obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c new file mode 100644 index 000..e858d58 --- /dev/null +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -0,0 +1,1468 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson Nand Flash Controller Driver + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Liang Yang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NFC_REG_CMD0x00 +#define NFC_CMD_IDLE (0xc << 14) +#define NFC_CMD_CLE(0x5 << 14) +#define NFC_CMD_ALE(0x6 << 14) +#define NFC_CMD_ADL((0 << 16) | (3 << 20)) +#define NFC_CMD_ADH((1 << 16) | (3 << 20)) +#define NFC_CMD_AIL((2 << 16) | (3 << 20)) +#define NFC_CMD_AIH((3 << 16) | (3 << 20)) +#define NFC_CMD_SEED ((8 << 16) | (3 << 20)) +#define NFC_CMD_M2N((0 << 17) | (2 << 20)) +#define NFC_CMD_N2M((1 << 17) | (2 << 20)) +#define NFC_CMD_RB BIT(20) +#define NFC_CMD_SCRAMBLER_ENABLE BIT(19) +#define NFC_CMD_SCRAMBLER_DISABLE 0 +#define NFC_CMD_SHORTMODE_DISABLE 0 +#define NFC_CMD_RB_INT BIT(14) + +#define NFC_CMD_GET_SIZE(x)(((x) >> 22) & GENMASK(4, 0)) + +#define NFC_REG_CFG0x04 +#define NFC_REG_DADR 0x08 +#define NFC_REG_IADR 0x0c +#define NFC_REG_BUF0x10 +#define NFC_REG_INFO 0x14 +#define NFC_REG_DC 0x18 +#define NFC_REG_ADR0x1c +#define NFC_REG_DL 0x20 +#define NFC_REG_DH 0x24 +#define NFC_REG_CADR 0x28 +#define NFC_REG_SADR 0x2c +#define NFC_REG_PINS 0x30 +#define NFC_REG_VER0x38 + +#define NFC_RB_IRQ_EN BIT(21) + +#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ + ( \ + (cmd_dir) | \ + ((ran) << 19) | \ + ((bch) << 14) | \ + ((short_mode) << 13)| \ + (((page_size) & 0x7f) << 6) | \ + ((pages) & 0x3f)\ + ) + +#define GENCMDDADDRL(adl, addr)((adl) | ((addr) & 0x)) +#define GENCMDDADDRH(adh, addr)((adh) | (((addr) >> 16) & 0x)) +#define GENCMDIADDRL(ail, addr)((ail) | ((addr) & 0x)) +#define GENCMDIADDRH(aih, addr)((aih) | (((addr) >> 16) & 0x)) + +#define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N) + +#define ECC_CHECK_RETURN_FF(-1) + +#define NAND_CE0 (0xe << 10) +#define NAND_CE1 (0xd << 10) + +#define DMA_BUSY_TIMEOUT 0x10 +#define CMD_FIFO_EMPTY_TIMEOUT 1000 + +#define MAX_CE_N
[PATCH v9 1/2] dt-bindings: nand: meson: add Amlogic NAND controller driver
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
new file mode 100644
index 000..3983c11
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
@@ -0,0 +1,60 @@
+Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
+
+This file documents the properties in addition to those available in
+the MTD NAND bindings.
+
+Required properties:
+- compatible : contains one of:
+ - "amlogic,meson-gxl-nfc"
+ - "amlogic,meson-axg-nfc"
+- clocks :
+ A list of phandle + clock-specifier pairs for the clocks listed
+ in clock-names.
+
+- clock-names: Should contain the following:
+ "core" - NFC module gate clock
+ "device" - device clock from eMMC sub clock controller
+ "rx" - rx clock phase
+ "tx" - tx clock phase
+
+- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC
+ controller port C
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Other properties:
+see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+
+Example demonstrate on AXG SoC:
+
+ sd_emmc_c_clkc: mmc@7000 {
+ compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
+ reg = <0x0 0x7000 0x0 0x800>;
+ };
+
+ nand-controller@7800 {
+ compatible = "amlogic,meson-axg-nfc";
+ reg = <0x0 0x7800 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+
+ clocks = < CLKID_SD_EMMC_C>,
+ <_emmc_c_clkc CLKID_MMC_DIV>,
+ <_emmc_c_clkc CLKID_MMC_PHASE_RX>,
+ <_emmc_c_clkc CLKID_MMC_PHASE_TX>;
+ clock-names = "core", "device", "rx", "tx";
+ amlogic,mmc-syscon = <_emmc_c_clkc>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ };
+ };
--
1.9.1
[PATCH v9 0/2] mtd: rawnand: meson: add Amlogic NAND driver support
These two patches try to add initial NAND driver support for Amlogic Meson SoCs, current it has been tested on GXL(p212) and AXG(s400) platform. Changes since V8 at [9] - fix build failre at object_is_on_stack - update Kconfig as Martin's suggested Changes since V7 at [8] - fix bitflips checking for blank pages - trace the latest commit with nand/next branch - checking the return of meson_nand_op_get_dma_safe_*input/output*_buf - add .detach_chip for free meson_nand.data_buf/info_buf Changes since V6 at [7] - use timings->tBERS_max as the maximum time out, delete NFC_CMD_RB_TIMEOUT - fix nand_rw_cmd and support small block flash and which row address less than 3 - fix coding style - replace readl/writel_* with readl/writel_relaxed* - delete ECC_SET_PROTECTED_OOB_BYTE and ECC_GET_PROTECTED_OOB_BYTE - implement dma access for read_buf and write_buf, more efficient. - delete waiting dma finish in write process and let NAND_CMD_PAGEPROG and RB command go on queuing - add waiting the completed flag of last ecc page be set, for more strict Changes since v5 at [6]: - use instr->delay_ns in exec_op() to caculate the delay cycle - delete struct meson_nfc_info_format and use macros instead - delete "is_scramble" in struct meson_nfc_nand_chip - add WARN_ON_ONCE() for chip > MAX_CE_NUM - drop param *mtd* or struct *nfc* if param *nand exist - substitute set_data_oob and get_data_oob for prase_data_oob and format_data_oob - split timings caculating and setting timings - move info_buf and data_buf to struct meson_nfc_nand_chip Changes since v4 at [5]: - remove the initial default divider(CLK_DIV_MASK) in meson_nfc_clk_init() - dt-bindings: remove staus, add "rx" and "tx" clock, and node rename Changes since v3 at [4]: - remove partition table and some used props from dt-bindings Changes since v2 at [3]: - remove some hardcode time value, like twb - use dev wait R/B instead of nand_soft_waitrdy - implement nfc ecc init by ecc helper - rework nfc buffer init to register the maximun buffer when several chips - free nfc buffer when error and cleanup - add variable to teack all the already assigned CS lines - fix mtd->name use the first cs line only - remove dt "nand-enable-scrambler" and use NAND_NEED_SCRAMBLING instead. - move setuping ECC fileds after the identification phase - use nand_scan() and attach_chip() - check one event to return IRQ_NONE - delete cast when of_device_get_match_data - use nand_controller_init() helper - remove nfc driver complains when calling devm_ioremap_resource - clear irqs before setting up irq handler Changes since v1 at [1]: - adopt property amlogic,nand-enable-scrambler - thanks Martin - drop nand pins in DT - convert clk access to emmc clkc model - fix regiser field definition alignment - drop nand-user-mode - parse cs id from DT - rework n2m, m2n function - explain why insert two "IDLE" command - implement exec_op() - drop meson_nfc_get_nand_chip_dts() - release resource once error occur in meson_nfc_nand_chips_init(), - call nand_cleanup(nand) once mtd_device_register fail Items not addressed ( or confirmed ) in this version: - convert to ECC conf helper() - convert to dma coherent API - how to construct mtd->name [1] https://lkml.kernel.org/r/20180613161314.14894-1-yixun@amlogic.com [2] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180719094612.5833-1-yixun@amlogic.com [4] https://lkml.kernel.org/r/1536317831-58056-1-git-send-email-jianxin@amlogic.com/ [5] https://lore.kernel.org/r/1537433449-65213-2-git-send-email-jianxin@amlogic.com/ [6] https://lore.kernel.org/r/1539839345-14021-1-git-send-email-jianxin@amlogic.com [7] https://lore.kernel.org/r/1541090542-19618-1-git-send-email-jianxin@amlogic.com [8] http://lkml.kernel.org/r/1542386439-30166-1-git-send-email-jianxin@amlogic.com [9] http://lkml.kernel.org/r/1544973463-59523-1-git-send-email-jianxin@amlogic.com Liang Yang (2): dt-bindings: nand: meson: add Amlogic NAND controller driver mtd: rawnand: meson: add support for Amlogic NAND flash controller .../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60 + drivers/mtd/nand/raw/Kconfig |8 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/meson_nand.c | 1468 4 files changed, 1537 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt create mode 100644 drivers/mtd/nand/raw/meson_nand.c -- 1.9.1
Re: [PATCH v8 0/2] mtd: rawnand: meson: add Amlogic NAND driver support
Hi Miquel, On 2019/1/15 16:49, Miquel Raynal wrote: > Hi Jianxin, > > Jianxin Pan wrote on Sun, 16 Dec 2018 > 23:17:41 +0800: > >> These two patches try to add initial NAND driver support for Amlogic Meson >> SoCs, current it has been tested on GXL(p212) and AXG(s400) platform. >> >> Changes since V6 at [8] >> - fix bitflips checking for blank pages >> - trace the latest commit with nand/next branch >> - checking the return of meson_nand_op_get_dma_safe_*input/output*_buf >> - add .detach_chip for free meson_nand.data_buf/info_buf >> > > Can you send a v9 with the build failre (object_is_on_stack pb) fixed > and the Kconfig entry updated (the Meson common clock thing) as > suggested by Martin? I sent v9 just now, object_is_on_stack build fail is fixed and Kconfig is updated as Martin suggested. Thank you for your time. > > > Thanks, > Miquèl > > . >
[PATCH v9 1/4] clk: meson: add one based divider support for sclk divider
When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
one based divider (div = val), and zero value gates the clock
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 3 ++-
drivers/clk/meson/clkc-audio.h | 8 --
drivers/clk/meson/clkc.h | 10 ++-
drivers/clk/meson/sclk-div.c | 59 --
4 files changed, 50 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index a849aa8..acd8694 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,7 +4,8 @@
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o
-obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += sclk-div.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o
obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
index 0a7c157..286ff12 100644
--- a/drivers/clk/meson/clkc-audio.h
+++ b/drivers/clk/meson/clkc-audio.h
@@ -15,14 +15,6 @@ struct meson_clk_triphase_data {
struct parm ph2;
};
-struct meson_sclk_div_data {
- struct parm div;
- struct parm hi;
- unsigned int cached_div;
- struct clk_duty cached_duty;
-};
-
extern const struct clk_ops meson_clk_triphase_ops;
-extern const struct clk_ops meson_sclk_div_ops;
#endif /* __MESON_CLKC_AUDIO_H */
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 6183b22..00b3320 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -27,6 +27,14 @@ struct parm {
u8 width;
};
+struct meson_sclk_div_data {
+ struct parm div;
+ struct parm hi;
+ unsigned int cached_div;
+ struct clk_duty cached_duty;
+ u8 flags;
+};
+
static inline unsigned int meson_parm_read(struct regmap *map, struct parm *p)
{
unsigned int val;
@@ -118,10 +126,10 @@ struct clk_regmap _name = {
\
extern const struct clk_ops meson_clk_mpll_ops;
extern const struct clk_ops meson_clk_phase_ops;
extern const struct clk_ops meson_vid_pll_div_ro_ops;
+extern const struct clk_ops meson_sclk_div_ops;
struct clk_hw *meson_clk_hw_register_input(struct device *dev,
const char *of_name,
const char *clk_name,
unsigned long flags);
-
#endif /* __CLKC_H */
diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c
index bc64019..a6c425b 100644
--- a/drivers/clk/meson/sclk-div.c
+++ b/drivers/clk/meson/sclk-div.c
@@ -4,42 +4,60 @@
* Author: Jerome Brunet
*
* Sample clock generator divider:
- * This HW divider gates with value 0 but is otherwise a zero based divider:
+ * This HW divider gates with value 0
*
* val >= 1
- * divider = val + 1
+ * divider = val + 1 if ONE_BASED is not set, otherwise divider = val.
*
* The duty cycle may also be set for the LR clock variant. The duty cycle
* ratio is:
*
* hi = [0 - val]
- * duty_cycle = (1 + hi) / (1 + val)
+ * duty_cycle = (1 + hi) / (1 + val) if ONE_BASED is not set, otherwise:
+ * duty_cycle = hi / (1 + val)
*/
-#include "clkc-audio.h"
+#include "clkc.h"
-static inline struct meson_sclk_div_data *
-meson_sclk_div_data(struct clk_regmap *clk)
+static inline int get_reg(int val, unsigned char flag)
{
- return (struct meson_sclk_div_data *)clk->data;
+ WARN_ON(val < 1);
+ if ((flag & CLK_DIVIDER_ONE_BASED) || !val)
+ return val;
+ else
+ return val - 1;
+}
+
+static inline int get_value(int reg, unsigned char flag)
+{
+ if (flag & CLK_DIVIDER_ONE_BASED)
+ return reg;
+ else
+ return reg + 1;
}
-static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
+static inline struct meson_sclk_div_data *
+meson_sclk_div_data(struct clk_regmap *clk)
{
- return (1 << sclk->div.width) - 1;
+ return (struct meson_sclk_div_data *)clk->data;
}
static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
{
- return sclk_div_maxval(sclk) + 1;
+ unsigned int reg = clk_div_mask(sclk->div.width);
+
+ return get_value(reg, sclk->flags);
}
static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
unsigned long prate, int maxdiv)
{
int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+ int mindiv = get_value(1, sclk->flags);
- return clamp
[PATCH v9 2/4] clk: meson: add emmc sub clock phase delay driver
From: Yixun Lan
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/clk-phase-delay.c | 73 +
drivers/clk/meson/clkc.h| 7
3 files changed, 81 insertions(+)
create mode 100644 drivers/clk/meson/clk-phase-delay.c
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index acd8694..d59620d 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,6 +3,7 @@
#
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
vid-pll-div.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase-delay.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += sclk-div.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o
diff --git a/drivers/clk/meson/clk-phase-delay.c
b/drivers/clk/meson/clk-phase-delay.c
new file mode 100644
index 000..a6e6600
--- /dev/null
+++ b/drivers/clk/meson/clk-phase-delay.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ * Author: Jianxin Pan
+ */
+
+#include
+#include "clkc.h"
+
+static inline struct meson_clk_phase_delay_data *
+meson_clk_get_phase_delay_data(struct clk_regmap *clk)
+{
+ return clk->data;
+}
+
+static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph;
+ unsigned long period_ps, p, d;
+ int degrees;
+
+ ph = meson_clk_get_phase_delay_data(clk);
+ p = meson_parm_read(clk->map, >phase);
+ degrees = p * 360 / (1 << (ph->phase.width));
+
+ period_ps = DIV_ROUND_UP_ULL(NSEC_PER_SEC * 1000ull,
+clk_hw_get_rate(hw));
+
+ d = meson_parm_read(clk->map, >delay);
+ degrees += d * ph->delay_step_ps * 360 / period_ps;
+ degrees %= 360;
+
+ return degrees;
+}
+
+static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph;
+ unsigned long period_ps, d = 0;
+ unsigned int p;
+
+ ph = meson_clk_get_phase_delay_data(clk);
+ period_ps = DIV_ROUND_UP_ULL(NSEC_PER_SEC * 1000ull,
+clk_hw_get_rate(hw));
+
+ /*
+* First compute the phase index (p), the remainder (r) is the
+* part we'll try to acheive using the delays (d).
+*/
+ p = 360 / 1 << (ph->phase.width);
+ degrees = degrees / p;
+ d = DIV_ROUND_CLOSEST((degrees % p) * period_ps,
+ 360 * ph->delay_step_ps);
+ d = min(d, PMASK(ph->delay.width));
+
+ meson_parm_write(clk->map, >phase, degrees);
+ meson_parm_write(clk->map, >delay, d);
+ return 0;
+}
+
+const struct clk_ops meson_clk_phase_delay_ops = {
+ .get_phase = meson_clk_phase_delay_get_phase,
+ .set_phase = meson_clk_phase_delay_set_phase,
+};
+EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 00b3320..e6f0905 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -118,6 +118,12 @@ struct clk_regmap _name = {
\
}, \
};
+struct meson_clk_phase_delay_data {
+ struct parm phase;
+ struct parm delay;
+ unsigned intdelay_step_ps;
+};
+
/* clk_ops */
extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;
@@ -127,6 +133,7 @@ struct clk_regmap _name = {
\
extern const struct clk_ops meson_clk_phase_ops;
extern const struct clk_ops meson_vid_pll_div_ro_ops;
extern const struct clk_ops meson_sclk_div_ops;
+extern const struct clk_ops meson_clk_phase_delay_ops;
struct clk_hw *meson_clk_hw_register_input(struct device *dev,
const char *of_name,
--
1.9.1
[PATCH v9 3/4] clk: meson: add DT documentation for emmc clock controller
From: Yixun Lan
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 ++
include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
new file mode 100644
index 000..0f518e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
@@ -0,0 +1,39 @@
+* Amlogic MMC Sub Clock Controller Driver
+
+The Amlogic MMC clock controller generates and supplies clock to support
+MMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+ "amlogic,gx-mmc-clkc"
+ "amlogic,axg-mmc-clkc"
+
+- #clock-cells: should be 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names
+ - "clkin0", "clkin1"
+
+- reg: address of emmc sub clock register
+
+Example: Clock controller node:
+
+sd_mmc_c_clkc: clock-controller@7000 {
+ compatible = "amlogic,axg-mmc-clkc", "syscon";
+ reg = <0x0 0x7000 0x0 0x4>;
+ #clock-cells = <1>;
+
+ clock-names = "clkin0", "clkin1";
+ clocks = < CLKID_SD_MMC_C_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
+
+sd_emmc_b_clkc: clock-controller@5000 {
+ compatible = "amlogic,axg-mmc-clkc", "syscon";
+ reg = <0x0 0x5000 0x0 0x4>;
+
+ #clock-cells = <1>;
+ clock-names = "clkin0", "clkin1";
+ clocks = < CLKID_SD_EMMC_B_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h
b/include/dt-bindings/clock/amlogic,mmc-clkc.h
new file mode 100644
index 000..34a3c56
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV 0
+#define CLKID_MMC_PHASE_CORE 1
+#define CLKID_MMC_PHASE_TX 2
+#define CLKID_MMC_PHASE_RX 3
+
+#endif
--
1.9.1
[PATCH v9 4/4] clk: meson: add sub MMC clock controller driver
From: Yixun Lan
The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.
Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Kconfig| 10 ++
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/mmc-clkc.c | 304 +++
3 files changed, 315 insertions(+)
create mode 100644 drivers/clk/meson/mmc-clkc.c
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f..3555f9d 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,16 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
+config COMMON_CLK_MMC_MESON
+ tristate "Meson MMC Sub Clock Controller Driver"
+ depends on ARCH_MESON || COMPILE_TEST
+ select MFD_SYSCON
+ select COMMON_CLK_AMLOGIC
+ help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ which include S905 (GXBB, GXL), A113D/X (AXG) devices.
+ Say Y if you want this clock enabled.
+
config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index d59620d..54416a2 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index 000..2582a98
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ * Author: Jianxin Pan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+
+#define SD_EMMC_CLOCK 0
+#define CLK_DELAY_STEP_PS 200
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS 4
+
+struct mmc_clkc_data {
+ struct meson_clk_phase_delay_data tx;
+ struct meson_clk_phase_delay_data rx;
+};
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+ .offset = SD_EMMC_CLOCK,
+ .mask = 0x3,
+ .shift = 6,
+};
+
+static const struct meson_sclk_div_data mmc_clkc_div_data = {
+ .div = {
+ .reg_off = SD_EMMC_CLOCK,
+ .width = 6,
+ },
+ .flags = CLK_DIVIDER_ONE_BASED,
+};
+
+static struct meson_clk_phase_data mmc_clkc_core_phase = {
+ .ph = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 8,
+ .width = 2,
+ }
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+ .tx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 10,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 16,
+ .width = 4,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+ .rx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 12,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 20,
+ .width = 4,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+};
+
+static const struct mmc_clkc_data mmc_clkc_axg_data = {
+ .tx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 10,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 16,
+ .width = 6,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+ .rx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+
[PATCH RESEND v9 0/4] clk: meson: add a sub EMMC clock controller support
This driver will add a MMC clock controller driver support. The original idea about adding a clock controller is during the discussion in the NAND driver mainline effort[1]. This driver is tested in the S400 board (AXG platform) with NAND driver. Changes since v8 [9] - fix auto build test ERROR with ARCH=i386 Changes since v7 [8] - move meson_clk_get_phase_delay_data() from header to driver - CONFIG sclk-div with COMMON_CLK_AMLOGIC instead of COMMON_CLK_AMLOGIC_AUDIO - remove onecell date and ID for internal MUX clk - use helper for functions for ONE_BASED in sclk-div - add ONE_BASED support for duty cycle Changes since v6 [7]: - add one based support for sclk divier - alloc sclk in probe for multiple instance - fix coding styles Changes since v5 [6]: - remove divider ops with .init and use sclk_div instead - drop CLK_DIVIDER_ROUND_CLOSEST in mux and div - drop the useless type cast Changes since v4 [5]: - use struct parm in phase delay driver - remove 0 delay releted part in phase delay driver - don't rebuild the parent name once again - add divider ops with .init Changes since v3 [4]: - separate clk-phase-delay driver - replace clk_get_rate() with clk_hw_get_rate() - collect Rob's R-Y - drop 'meson-' prefix from compatible string Changes since v2 [3]: - squash dt-binding clock-id patch - update license - fix alignment - construct a clk register helper() function Changes since v1 [2]: - implement phase clock - update compatible name - adjust file name - divider probe() into small functions, and re-use them [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13 [2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com [4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com [5] https://lkml.kernel.org/r/20180809070724.11935-4-yixun@amlogic.com [6] https://lkml.kernel.org/r/1539839245-13793-1-git-send-email-jianxin@amlogic.com [7] https://lkml.kernel.org/r/1541089855-19356-1-git-send-email-jianxin@amlogic.com [8] https://lkml.kernel.org/r/1544457877-51301-1-git-send-email-jianxin@amlogic.com [9] https://lkml.kernel.org/r/1545063850-21504-1-git-send-email-jianxin@amlogic.com Jianxin Pan (1): clk: meson: add one based divider support for sclk divider Yixun Lan (3): clk: meson: add emmc sub clock phase delay driver clk: meson: add DT documentation for emmc clock controller clk: meson: add sub MMC clock controller driver .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 +++ drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 5 +- drivers/clk/meson/clk-phase-delay.c| 73 + drivers/clk/meson/clkc-audio.h | 8 - drivers/clk/meson/clkc.h | 17 +- drivers/clk/meson/mmc-clkc.c | 304 + drivers/clk/meson/sclk-div.c | 59 ++-- include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++ 9 files changed, 502 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt create mode 100644 drivers/clk/meson/clk-phase-delay.c create mode 100644 drivers/clk/meson/mmc-clkc.c create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h -- 1.9.1
[PATCH RESEND v8 0/2] mtd: rawnand: meson: add Amlogic NAND driver support
These two patches try to add initial NAND driver support for Amlogic Meson SoCs, current it has been tested on GXL(p212) and AXG(s400) platform. Changes since V6 at [8] - fix bitflips checking for blank pages - trace the latest commit with nand/next branch - checking the return of meson_nand_op_get_dma_safe_*input/output*_buf - add .detach_chip for free meson_nand.data_buf/info_buf Changes since V6 at [7] - use timings->tBERS_max as the maximum time out, delete NFC_CMD_RB_TIMEOUT - fix nand_rw_cmd and support small block flash and which row address less than 3 - fix coding style - replace readl/writel_* with readl/writel_relaxed* - delete ECC_SET_PROTECTED_OOB_BYTE and ECC_GET_PROTECTED_OOB_BYTE - implement dma access for read_buf and write_buf, more efficient. - delete waiting dma finish in write process and let NAND_CMD_PAGEPROG and RB command go on queuing - add waiting the completed flag of last ecc page be set, for more strict Changes since v5 at [6]: - use instr->delay_ns in exec_op() to caculate the delay cycle - delete struct meson_nfc_info_format and use macros instead - delete "is_scramble" in struct meson_nfc_nand_chip - add WARN_ON_ONCE() for chip > MAX_CE_NUM - drop param *mtd* or struct *nfc* if param *nand exist - substitute set_data_oob and get_data_oob for prase_data_oob and format_data_oob - split timings caculating and setting timings - move info_buf and data_buf to struct meson_nfc_nand_chip Changes since v4 at [5]: - remove the initial default divider(CLK_DIV_MASK) in meson_nfc_clk_init() - dt-bindings: remove staus, add "rx" and "tx" clock, and node rename Changes since v3 at [4]: - remove partition table and some used props from dt-bindings Changes since v2 at [3]: - remove some hardcode time value, like twb - use dev wait R/B instead of nand_soft_waitrdy - implement nfc ecc init by ecc helper - rework nfc buffer init to register the maximun buffer when several chips - free nfc buffer when error and cleanup - add variable to teack all the already assigned CS lines - fix mtd->name use the first cs line only - remove dt "nand-enable-scrambler" and use NAND_NEED_SCRAMBLING instead. - move setuping ECC fileds after the identification phase - use nand_scan() and attach_chip() - check one event to return IRQ_NONE - delete cast when of_device_get_match_data - use nand_controller_init() helper - remove nfc driver complains when calling devm_ioremap_resource - clear irqs before setting up irq handler Changes since v1 at [1]: - adopt property amlogic,nand-enable-scrambler - thanks Martin - drop nand pins in DT - convert clk access to emmc clkc model - fix regiser field definition alignment - drop nand-user-mode - parse cs id from DT - rework n2m, m2n function - explain why insert two "IDLE" command - implement exec_op() - drop meson_nfc_get_nand_chip_dts() - release resource once error occur in meson_nfc_nand_chips_init(), - call nand_cleanup(nand) once mtd_device_register fail Items not addressed ( or confirmed ) in this version: - convert to ECC conf helper() - convert to dma coherent API - how to construct mtd->name [1] https://lkml.kernel.org/r/20180613161314.14894-1-yixun@amlogic.com [2] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180719094612.5833-1-yixun@amlogic.com [4] https://lkml.kernel.org/r/1536317831-58056-1-git-send-email-jianxin@amlogic.com/ [5] https://lore.kernel.org/r/1537433449-65213-2-git-send-email-jianxin@amlogic.com/ [6] https://lore.kernel.org/r/1539839345-14021-1-git-send-email-jianxin@amlogic.com [7] https://lore.kernel.org/r/1541090542-19618-1-git-send-email-jianxin@amlogic.com [8] http://lkml.kernel.org/r/1542386439-30166-1-git-send-email-jianxin@amlogic.com Liang Yang (2): dt-bindings: nand: meson: add Amlogic NAND controller driver mtd: rawnand: meson: add support for Amlogic NAND flash controller .../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60 + drivers/mtd/nand/raw/Kconfig | 10 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/meson_nand.c | 1468 4 files changed, 1539 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt create mode 100644 drivers/mtd/nand/raw/meson_nand.c -- 1.9.1
[PATCH RESEND v8 1/2] dt-bindings: nand: meson: add Amlogic NAND controller driver
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
new file mode 100644
index 000..3983c11
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
@@ -0,0 +1,60 @@
+Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
+
+This file documents the properties in addition to those available in
+the MTD NAND bindings.
+
+Required properties:
+- compatible : contains one of:
+ - "amlogic,meson-gxl-nfc"
+ - "amlogic,meson-axg-nfc"
+- clocks :
+ A list of phandle + clock-specifier pairs for the clocks listed
+ in clock-names.
+
+- clock-names: Should contain the following:
+ "core" - NFC module gate clock
+ "device" - device clock from eMMC sub clock controller
+ "rx" - rx clock phase
+ "tx" - tx clock phase
+
+- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC
+ controller port C
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Other properties:
+see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+
+Example demonstrate on AXG SoC:
+
+ sd_emmc_c_clkc: mmc@7000 {
+ compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
+ reg = <0x0 0x7000 0x0 0x800>;
+ };
+
+ nand-controller@7800 {
+ compatible = "amlogic,meson-axg-nfc";
+ reg = <0x0 0x7800 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+
+ clocks = < CLKID_SD_EMMC_C>,
+ <_emmc_c_clkc CLKID_MMC_DIV>,
+ <_emmc_c_clkc CLKID_MMC_PHASE_RX>,
+ <_emmc_c_clkc CLKID_MMC_PHASE_TX>;
+ clock-names = "core", "device", "rx", "tx";
+ amlogic,mmc-syscon = <_emmc_c_clkc>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ };
+ };
--
1.9.1
[PATCH RESEND v8 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller
From: Liang Yang Add initial support for the Amlogic NAND flash controller which found in the Meson-GXBB/GXL/AXG SoCs. Signed-off-by: Liang Yang Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- drivers/mtd/nand/raw/Kconfig | 10 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/meson_nand.c | 1468 + 3 files changed, 1479 insertions(+) create mode 100644 drivers/mtd/nand/raw/meson_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 1a55d3e..d05ff20 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -541,4 +541,14 @@ config MTD_NAND_TEGRA is supported. Extra OOB bytes when using HW ECC are currently not supported. +config MTD_NAND_MESON + tristate "Support for NAND controller on Amlogic's Meson SoCs" + depends on ARCH_MESON || COMPILE_TEST + depends on COMMON_CLK_AMLOGIC + select COMMON_CLK_REGMAP_MESON + select MFD_SYSCON + help + Enables support for NAND controller on Amlogic's Meson SoCs. + This controller is found on Meson GXBB, GXL, AXG SoCs. + endif # MTD_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 57159b3..a2cc2fe 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o +obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c new file mode 100644 index 000..e858d58 --- /dev/null +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -0,0 +1,1468 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson Nand Flash Controller Driver + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Liang Yang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NFC_REG_CMD0x00 +#define NFC_CMD_IDLE (0xc << 14) +#define NFC_CMD_CLE(0x5 << 14) +#define NFC_CMD_ALE(0x6 << 14) +#define NFC_CMD_ADL((0 << 16) | (3 << 20)) +#define NFC_CMD_ADH((1 << 16) | (3 << 20)) +#define NFC_CMD_AIL((2 << 16) | (3 << 20)) +#define NFC_CMD_AIH((3 << 16) | (3 << 20)) +#define NFC_CMD_SEED ((8 << 16) | (3 << 20)) +#define NFC_CMD_M2N((0 << 17) | (2 << 20)) +#define NFC_CMD_N2M((1 << 17) | (2 << 20)) +#define NFC_CMD_RB BIT(20) +#define NFC_CMD_SCRAMBLER_ENABLE BIT(19) +#define NFC_CMD_SCRAMBLER_DISABLE 0 +#define NFC_CMD_SHORTMODE_DISABLE 0 +#define NFC_CMD_RB_INT BIT(14) + +#define NFC_CMD_GET_SIZE(x)(((x) >> 22) & GENMASK(4, 0)) + +#define NFC_REG_CFG0x04 +#define NFC_REG_DADR 0x08 +#define NFC_REG_IADR 0x0c +#define NFC_REG_BUF0x10 +#define NFC_REG_INFO 0x14 +#define NFC_REG_DC 0x18 +#define NFC_REG_ADR0x1c +#define NFC_REG_DL 0x20 +#define NFC_REG_DH 0x24 +#define NFC_REG_CADR 0x28 +#define NFC_REG_SADR 0x2c +#define NFC_REG_PINS 0x30 +#define NFC_REG_VER0x38 + +#define NFC_RB_IRQ_EN BIT(21) + +#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ + ( \ + (cmd_dir) | \ + ((ran) << 19) | \ + ((bch) << 14) | \ + ((short_mode) << 13)| \ + (((page_size) & 0x7f) << 6) | \ + ((pages) & 0x3f)\ + ) + +#define GENCMDDADDRL(adl, addr)((adl) | ((addr) & 0x)) +#define GENCMDDADDRH(adh, addr)((adh) | (((addr) >> 16) & 0x)) +#define GENCMDIADDRL(ail, addr)((ail) | ((addr) & 0x)) +#define GENCMDIADDRH(aih, addr)((aih) | (((addr) >> 16) & 0x)) + +#define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N) + +#define ECC_CHECK_RETURN_FF(-1) + +#define NAND_CE0 (0xe << 10) +#define NAND_CE1 (0xd &l
[PATCH RESEND v8 0/4] clk: meson: add a sub EMMC clock controller support
This driver will add a MMC clock controller driver support. The original idea about adding a clock controller is during the discussion in the NAND driver mainline effort[1]. This driver is tested in the S400 board (AXG platform) with NAND driver. Changes since v7 [8] - move meson_clk_get_phase_delay_data() from header to driver - CONFIG sclk-div with COMMON_CLK_AMLOGIC instead of COMMON_CLK_AMLOGIC_AUDIO - remove onecell date and ID for internal MUX clk - use helper for functions for ONE_BASED in sclk-div - add ONE_BASED support for duty cycle Changes since v6 [7]: - add one based support for sclk divier - alloc sclk in probe for multiple instance - fix coding styles Changes since v5 [6]: - remove divider ops with .init and use sclk_div instead - drop CLK_DIVIDER_ROUND_CLOSEST in mux and div - drop the useless type cast Changes since v4 [5]: - use struct parm in phase delay driver - remove 0 delay releted part in phase delay driver - don't rebuild the parent name once again - add divider ops with .init Changes since v3 [4]: - separate clk-phase-delay driver - replace clk_get_rate() with clk_hw_get_rate() - collect Rob's R-Y - drop 'meson-' prefix from compatible string Changes since v2 [3]: - squash dt-binding clock-id patch - update license - fix alignment - construct a clk register helper() function Changes since v1 [2]: - implement phase clock - update compatible name - adjust file name - divider probe() into small functions, and re-use them [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13 [2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com [4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com [5] https://lkml.kernel.org/r/20180809070724.11935-4-yixun@amlogic.com [6] https://lkml.kernel.org/r/1539839245-13793-1-git-send-email-jianxin@amlogic.com [7] https://lkml.kernel.org/r/1541089855-19356-1-git-send-email-jianxin@amlogic.com [8] https://lkml.kernel.org/r/1544457877-51301-1-git-send-email-jianxin@amlogic.com Jianxin Pan (1): clk: meson: add one based divider support for sclk divider Yixun Lan (3): clk: meson: add emmc sub clock phase delay driver clk: meson: add DT documentation for emmc clock controller clk: meson: add sub MMC clock controller driver .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 +++ drivers/clk/meson/Kconfig | 9 + drivers/clk/meson/Makefile | 5 +- drivers/clk/meson/clk-phase-delay.c| 73 + drivers/clk/meson/clkc-audio.h | 8 - drivers/clk/meson/clkc.h | 17 +- drivers/clk/meson/mmc-clkc.c | 304 + drivers/clk/meson/sclk-div.c | 59 ++-- include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++ 9 files changed, 501 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt create mode 100644 drivers/clk/meson/clk-phase-delay.c create mode 100644 drivers/clk/meson/mmc-clkc.c create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h -- 1.9.1
[PATCH RESEND v8 1/4] clk: meson: add one based divider support for sclk divider
When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
one based divider (div = val), and zero value gates the clock
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 3 ++-
drivers/clk/meson/clkc-audio.h | 8 --
drivers/clk/meson/clkc.h | 10 ++-
drivers/clk/meson/sclk-div.c | 59 --
4 files changed, 50 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index a849aa8..acd8694 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,7 +4,8 @@
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o
-obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += sclk-div.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o
obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
index 0a7c157..286ff12 100644
--- a/drivers/clk/meson/clkc-audio.h
+++ b/drivers/clk/meson/clkc-audio.h
@@ -15,14 +15,6 @@ struct meson_clk_triphase_data {
struct parm ph2;
};
-struct meson_sclk_div_data {
- struct parm div;
- struct parm hi;
- unsigned int cached_div;
- struct clk_duty cached_duty;
-};
-
extern const struct clk_ops meson_clk_triphase_ops;
-extern const struct clk_ops meson_sclk_div_ops;
#endif /* __MESON_CLKC_AUDIO_H */
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 6183b22..00b3320 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -27,6 +27,14 @@ struct parm {
u8 width;
};
+struct meson_sclk_div_data {
+ struct parm div;
+ struct parm hi;
+ unsigned int cached_div;
+ struct clk_duty cached_duty;
+ u8 flags;
+};
+
static inline unsigned int meson_parm_read(struct regmap *map, struct parm *p)
{
unsigned int val;
@@ -118,10 +126,10 @@ struct clk_regmap _name = {
\
extern const struct clk_ops meson_clk_mpll_ops;
extern const struct clk_ops meson_clk_phase_ops;
extern const struct clk_ops meson_vid_pll_div_ro_ops;
+extern const struct clk_ops meson_sclk_div_ops;
struct clk_hw *meson_clk_hw_register_input(struct device *dev,
const char *of_name,
const char *clk_name,
unsigned long flags);
-
#endif /* __CLKC_H */
diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c
index bc64019..a6c425b 100644
--- a/drivers/clk/meson/sclk-div.c
+++ b/drivers/clk/meson/sclk-div.c
@@ -4,42 +4,60 @@
* Author: Jerome Brunet
*
* Sample clock generator divider:
- * This HW divider gates with value 0 but is otherwise a zero based divider:
+ * This HW divider gates with value 0
*
* val >= 1
- * divider = val + 1
+ * divider = val + 1 if ONE_BASED is not set, otherwise divider = val.
*
* The duty cycle may also be set for the LR clock variant. The duty cycle
* ratio is:
*
* hi = [0 - val]
- * duty_cycle = (1 + hi) / (1 + val)
+ * duty_cycle = (1 + hi) / (1 + val) if ONE_BASED is not set, otherwise:
+ * duty_cycle = hi / (1 + val)
*/
-#include "clkc-audio.h"
+#include "clkc.h"
-static inline struct meson_sclk_div_data *
-meson_sclk_div_data(struct clk_regmap *clk)
+static inline int get_reg(int val, unsigned char flag)
{
- return (struct meson_sclk_div_data *)clk->data;
+ WARN_ON(val < 1);
+ if ((flag & CLK_DIVIDER_ONE_BASED) || !val)
+ return val;
+ else
+ return val - 1;
+}
+
+static inline int get_value(int reg, unsigned char flag)
+{
+ if (flag & CLK_DIVIDER_ONE_BASED)
+ return reg;
+ else
+ return reg + 1;
}
-static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
+static inline struct meson_sclk_div_data *
+meson_sclk_div_data(struct clk_regmap *clk)
{
- return (1 << sclk->div.width) - 1;
+ return (struct meson_sclk_div_data *)clk->data;
}
static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
{
- return sclk_div_maxval(sclk) + 1;
+ unsigned int reg = clk_div_mask(sclk->div.width);
+
+ return get_value(reg, sclk->flags);
}
static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
unsigned long prate, int maxdiv)
{
int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+ int mindiv = get_value(1, sclk->flags);
- return clamp
[PATCH RESEND v8 4/4] clk: meson: add sub MMC clock controller driver
From: Yixun Lan
The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.
Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Kconfig| 9 ++
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/mmc-clkc.c | 304 +++
3 files changed, 314 insertions(+)
create mode 100644 drivers/clk/meson/mmc-clkc.c
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f..c84b0f7 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,15 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
+config COMMON_CLK_MMC_MESON
+ tristate "Meson MMC Sub Clock Controller Driver"
+ select MFD_SYSCON
+ select COMMON_CLK_AMLOGIC
+ help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ which include S905 (GXBB, GXL), A113D/X (AXG) devices.
+ Say Y if you want this clock enabled.
+
config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index d59620d..54416a2 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index 000..2582a98
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ * Author: Jianxin Pan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+
+#define SD_EMMC_CLOCK 0
+#define CLK_DELAY_STEP_PS 200
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS 4
+
+struct mmc_clkc_data {
+ struct meson_clk_phase_delay_data tx;
+ struct meson_clk_phase_delay_data rx;
+};
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+ .offset = SD_EMMC_CLOCK,
+ .mask = 0x3,
+ .shift = 6,
+};
+
+static const struct meson_sclk_div_data mmc_clkc_div_data = {
+ .div = {
+ .reg_off = SD_EMMC_CLOCK,
+ .width = 6,
+ },
+ .flags = CLK_DIVIDER_ONE_BASED,
+};
+
+static struct meson_clk_phase_data mmc_clkc_core_phase = {
+ .ph = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 8,
+ .width = 2,
+ }
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+ .tx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 10,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 16,
+ .width = 4,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+ .rx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 12,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 20,
+ .width = 4,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+};
+
+static const struct mmc_clkc_data mmc_clkc_axg_data = {
+ .tx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 10,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 16,
+ .width = 6,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+ .rx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 12,
+
[PATCH RESEND v8 3/4] clk: meson: add DT documentation for emmc clock controller
From: Yixun Lan
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 ++
include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
new file mode 100644
index 000..0f518e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
@@ -0,0 +1,39 @@
+* Amlogic MMC Sub Clock Controller Driver
+
+The Amlogic MMC clock controller generates and supplies clock to support
+MMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+ "amlogic,gx-mmc-clkc"
+ "amlogic,axg-mmc-clkc"
+
+- #clock-cells: should be 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names
+ - "clkin0", "clkin1"
+
+- reg: address of emmc sub clock register
+
+Example: Clock controller node:
+
+sd_mmc_c_clkc: clock-controller@7000 {
+ compatible = "amlogic,axg-mmc-clkc", "syscon";
+ reg = <0x0 0x7000 0x0 0x4>;
+ #clock-cells = <1>;
+
+ clock-names = "clkin0", "clkin1";
+ clocks = < CLKID_SD_MMC_C_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
+
+sd_emmc_b_clkc: clock-controller@5000 {
+ compatible = "amlogic,axg-mmc-clkc", "syscon";
+ reg = <0x0 0x5000 0x0 0x4>;
+
+ #clock-cells = <1>;
+ clock-names = "clkin0", "clkin1";
+ clocks = < CLKID_SD_EMMC_B_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h
b/include/dt-bindings/clock/amlogic,mmc-clkc.h
new file mode 100644
index 000..34a3c56
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV 0
+#define CLKID_MMC_PHASE_CORE 1
+#define CLKID_MMC_PHASE_TX 2
+#define CLKID_MMC_PHASE_RX 3
+
+#endif
--
1.9.1
[PATCH RESEND v8 2/4] clk: meson: add emmc sub clock phase delay driver
From: Yixun Lan
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/clk-phase-delay.c | 73 +
drivers/clk/meson/clkc.h| 7
3 files changed, 81 insertions(+)
create mode 100644 drivers/clk/meson/clk-phase-delay.c
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index acd8694..d59620d 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,6 +3,7 @@
#
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
vid-pll-div.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase-delay.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += sclk-div.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o
diff --git a/drivers/clk/meson/clk-phase-delay.c
b/drivers/clk/meson/clk-phase-delay.c
new file mode 100644
index 000..a6e6600
--- /dev/null
+++ b/drivers/clk/meson/clk-phase-delay.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ * Author: Jianxin Pan
+ */
+
+#include
+#include "clkc.h"
+
+static inline struct meson_clk_phase_delay_data *
+meson_clk_get_phase_delay_data(struct clk_regmap *clk)
+{
+ return clk->data;
+}
+
+static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph;
+ unsigned long period_ps, p, d;
+ int degrees;
+
+ ph = meson_clk_get_phase_delay_data(clk);
+ p = meson_parm_read(clk->map, >phase);
+ degrees = p * 360 / (1 << (ph->phase.width));
+
+ period_ps = DIV_ROUND_UP_ULL(NSEC_PER_SEC * 1000ull,
+clk_hw_get_rate(hw));
+
+ d = meson_parm_read(clk->map, >delay);
+ degrees += d * ph->delay_step_ps * 360 / period_ps;
+ degrees %= 360;
+
+ return degrees;
+}
+
+static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph;
+ unsigned long period_ps, d = 0;
+ unsigned int p;
+
+ ph = meson_clk_get_phase_delay_data(clk);
+ period_ps = DIV_ROUND_UP_ULL(NSEC_PER_SEC * 1000ull,
+clk_hw_get_rate(hw));
+
+ /*
+* First compute the phase index (p), the remainder (r) is the
+* part we'll try to acheive using the delays (d).
+*/
+ p = 360 / 1 << (ph->phase.width);
+ degrees = degrees / p;
+ d = DIV_ROUND_CLOSEST((degrees % p) * period_ps,
+ 360 * ph->delay_step_ps);
+ d = min(d, PMASK(ph->delay.width));
+
+ meson_parm_write(clk->map, >phase, degrees);
+ meson_parm_write(clk->map, >delay, d);
+ return 0;
+}
+
+const struct clk_ops meson_clk_phase_delay_ops = {
+ .get_phase = meson_clk_phase_delay_get_phase,
+ .set_phase = meson_clk_phase_delay_set_phase,
+};
+EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 00b3320..e6f0905 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -118,6 +118,12 @@ struct clk_regmap _name = {
\
}, \
};
+struct meson_clk_phase_delay_data {
+ struct parm phase;
+ struct parm delay;
+ unsigned intdelay_step_ps;
+};
+
/* clk_ops */
extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;
@@ -127,6 +133,7 @@ struct clk_regmap _name = {
\
extern const struct clk_ops meson_clk_phase_ops;
extern const struct clk_ops meson_vid_pll_div_ro_ops;
extern const struct clk_ops meson_sclk_div_ops;
+extern const struct clk_ops meson_clk_phase_delay_ops;
struct clk_hw *meson_clk_hw_register_input(struct device *dev,
const char *of_name,
--
1.9.1
[PATCH v8 1/4] clk: meson: add one based divider support for sclk divider
When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
one based divider (div = val), and zero value gates the clock
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 3 ++-
drivers/clk/meson/clkc-audio.h | 8 --
drivers/clk/meson/clkc.h | 10 ++-
drivers/clk/meson/sclk-div.c | 59 --
4 files changed, 50 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index a849aa8..acd8694 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,7 +4,8 @@
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o
-obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += sclk-div.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o
obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
index 0a7c157..286ff12 100644
--- a/drivers/clk/meson/clkc-audio.h
+++ b/drivers/clk/meson/clkc-audio.h
@@ -15,14 +15,6 @@ struct meson_clk_triphase_data {
struct parm ph2;
};
-struct meson_sclk_div_data {
- struct parm div;
- struct parm hi;
- unsigned int cached_div;
- struct clk_duty cached_duty;
-};
-
extern const struct clk_ops meson_clk_triphase_ops;
-extern const struct clk_ops meson_sclk_div_ops;
#endif /* __MESON_CLKC_AUDIO_H */
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 6183b22..00b3320 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -27,6 +27,14 @@ struct parm {
u8 width;
};
+struct meson_sclk_div_data {
+ struct parm div;
+ struct parm hi;
+ unsigned int cached_div;
+ struct clk_duty cached_duty;
+ u8 flags;
+};
+
static inline unsigned int meson_parm_read(struct regmap *map, struct parm *p)
{
unsigned int val;
@@ -118,10 +126,10 @@ struct clk_regmap _name = {
\
extern const struct clk_ops meson_clk_mpll_ops;
extern const struct clk_ops meson_clk_phase_ops;
extern const struct clk_ops meson_vid_pll_div_ro_ops;
+extern const struct clk_ops meson_sclk_div_ops;
struct clk_hw *meson_clk_hw_register_input(struct device *dev,
const char *of_name,
const char *clk_name,
unsigned long flags);
-
#endif /* __CLKC_H */
diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c
index bc64019..a6c425b 100644
--- a/drivers/clk/meson/sclk-div.c
+++ b/drivers/clk/meson/sclk-div.c
@@ -4,42 +4,60 @@
* Author: Jerome Brunet
*
* Sample clock generator divider:
- * This HW divider gates with value 0 but is otherwise a zero based divider:
+ * This HW divider gates with value 0
*
* val >= 1
- * divider = val + 1
+ * divider = val + 1 if ONE_BASED is not set, otherwise divider = val.
*
* The duty cycle may also be set for the LR clock variant. The duty cycle
* ratio is:
*
* hi = [0 - val]
- * duty_cycle = (1 + hi) / (1 + val)
+ * duty_cycle = (1 + hi) / (1 + val) if ONE_BASED is not set, otherwise:
+ * duty_cycle = hi / (1 + val)
*/
-#include "clkc-audio.h"
+#include "clkc.h"
-static inline struct meson_sclk_div_data *
-meson_sclk_div_data(struct clk_regmap *clk)
+static inline int get_reg(int val, unsigned char flag)
{
- return (struct meson_sclk_div_data *)clk->data;
+ WARN_ON(val < 1);
+ if ((flag & CLK_DIVIDER_ONE_BASED) || !val)
+ return val;
+ else
+ return val - 1;
+}
+
+static inline int get_value(int reg, unsigned char flag)
+{
+ if (flag & CLK_DIVIDER_ONE_BASED)
+ return reg;
+ else
+ return reg + 1;
}
-static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
+static inline struct meson_sclk_div_data *
+meson_sclk_div_data(struct clk_regmap *clk)
{
- return (1 << sclk->div.width) - 1;
+ return (struct meson_sclk_div_data *)clk->data;
}
static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
{
- return sclk_div_maxval(sclk) + 1;
+ unsigned int reg = clk_div_mask(sclk->div.width);
+
+ return get_value(reg, sclk->flags);
}
static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
unsigned long prate, int maxdiv)
{
int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+ int mindiv = get_value(1, sclk->flags);
- return clamp
[PATCH v8 0/4] clk: meson: add a sub EMMC clock controller support
This driver will add a MMC clock controller driver support. The original idea about adding a clock controller is during the discussion in the NAND driver mainline effort[1]. This driver is tested in the S400 board (AXG platform) with NAND driver. Changes since v7 [8] - move meson_clk_get_phase_delay_data() from header to driver - CONFIG sclk-div with COMMON_CLK_AMLOGIC instead of COMMON_CLK_AMLOGIC_AUDIO - remove onecell date and ID for internal MUX clk - use helper for functions for ONE_BASED in sclk-div - add ONE_BASED support for duty cycle Changes since v6 [7]: - add one based support for sclk divier - alloc sclk in probe for multiple instance - fix coding styles Changes since v5 [6]: - remove divider ops with .init and use sclk_div instead - drop CLK_DIVIDER_ROUND_CLOSEST in mux and div - drop the useless type cast Changes since v4 [5]: - use struct parm in phase delay driver - remove 0 delay releted part in phase delay driver - don't rebuild the parent name once again - add divider ops with .init Changes since v3 [4]: - separate clk-phase-delay driver - replace clk_get_rate() with clk_hw_get_rate() - collect Rob's R-Y - drop 'meson-' prefix from compatible string Changes since v2 [3]: - squash dt-binding clock-id patch - update license - fix alignment - construct a clk register helper() function Changes since v1 [2]: - implement phase clock - update compatible name - adjust file name - divider probe() into small functions, and re-use them [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13 [2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com [4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com [5] https://lkml.kernel.org/r/20180809070724.11935-4-yixun@amlogic.com [6] https://lkml.kernel.org/r/1539839245-13793-1-git-send-email-jianxin@amlogic.com [7] https://lkml.kernel.org/r/1541089855-19356-1-git-send-email-jianxin@amlogic.com [8] https://lkml.kernel.org/r/1544457877-51301-1-git-send-email-jianxin@amlogic.com Jianxin Pan (1): clk: meson: add one based divider support for sclk divider Yixun Lan (3): clk: meson: add emmc sub clock phase delay driver clk: meson: add DT documentation for emmc clock controller clk: meson: add sub MMC clock controller driver .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 +++ drivers/clk/meson/Kconfig | 9 + drivers/clk/meson/Makefile | 5 +- drivers/clk/meson/clk-phase-delay.c| 70 + drivers/clk/meson/clkc-audio.h | 8 - drivers/clk/meson/clkc.h | 17 +- drivers/clk/meson/mmc-clkc.c | 304 + drivers/clk/meson/sclk-div.c | 59 ++-- include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++ 9 files changed, 498 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt create mode 100644 drivers/clk/meson/clk-phase-delay.c create mode 100644 drivers/clk/meson/mmc-clkc.c create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h -- 1.9.1
[PATCH v8 4/4] clk: meson: add sub MMC clock controller driver
From: Yixun Lan
The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.
Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Kconfig| 9 ++
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/mmc-clkc.c | 304 +++
3 files changed, 314 insertions(+)
create mode 100644 drivers/clk/meson/mmc-clkc.c
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f..c84b0f7 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,15 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
+config COMMON_CLK_MMC_MESON
+ tristate "Meson MMC Sub Clock Controller Driver"
+ select MFD_SYSCON
+ select COMMON_CLK_AMLOGIC
+ help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ which include S905 (GXBB, GXL), A113D/X (AXG) devices.
+ Say Y if you want this clock enabled.
+
config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index d59620d..54416a2 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index 000..2582a98
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ * Author: Jianxin Pan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+
+/* clock ID used by internal driver */
+
+#define SD_EMMC_CLOCK 0
+#define CLK_DELAY_STEP_PS 200
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS 4
+
+struct mmc_clkc_data {
+ struct meson_clk_phase_delay_data tx;
+ struct meson_clk_phase_delay_data rx;
+};
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+ .offset = SD_EMMC_CLOCK,
+ .mask = 0x3,
+ .shift = 6,
+};
+
+static const struct meson_sclk_div_data mmc_clkc_div_data = {
+ .div = {
+ .reg_off = SD_EMMC_CLOCK,
+ .width = 6,
+ },
+ .flags = CLK_DIVIDER_ONE_BASED,
+};
+
+static struct meson_clk_phase_data mmc_clkc_core_phase = {
+ .ph = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 8,
+ .width = 2,
+ }
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+ .tx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 10,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 16,
+ .width = 4,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+ .rx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 12,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 20,
+ .width = 4,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+};
+
+static const struct mmc_clkc_data mmc_clkc_axg_data = {
+ .tx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 10,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 16,
+ .width = 6,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+ .rx = {
+ .phase = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = 12,
+
[PATCH v8 2/4] clk: meson: add emmc sub clock phase delay driver
From: Yixun Lan
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/clk-phase-delay.c | 70 +
drivers/clk/meson/clkc.h| 7
3 files changed, 78 insertions(+)
create mode 100644 drivers/clk/meson/clk-phase-delay.c
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index acd8694..d59620d 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,6 +3,7 @@
#
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
vid-pll-div.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase-delay.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += sclk-div.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o
diff --git a/drivers/clk/meson/clk-phase-delay.c
b/drivers/clk/meson/clk-phase-delay.c
new file mode 100644
index 000..88004d2
--- /dev/null
+++ b/drivers/clk/meson/clk-phase-delay.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ * Author: Jianxin Pan
+ */
+
+#include
+#include "clkc.h"
+
+static inline struct meson_clk_phase_delay_data *
+meson_clk_get_phase_delay_data(struct clk_regmap *clk)
+{
+ return clk->data;
+}
+
+static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph;
+ unsigned long period_ps, p, d;
+ int degrees;
+
+ ph = meson_clk_get_phase_delay_data(clk);
+ p = meson_parm_read(clk->map, >phase);
+ degrees = p * 360 / (1 << (ph->phase.width));
+
+ period_ps = DIV_ROUND_UP(NSEC_PER_SEC * 1000,
+clk_hw_get_rate(hw));
+
+ d = meson_parm_read(clk->map, >delay);
+ degrees += d * ph->delay_step_ps * 360 / period_ps;
+ degrees %= 360;
+
+ return degrees;
+}
+
+static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph;
+ unsigned long period_ps, d = 0, r;
+
+ ph = meson_clk_get_phase_delay_data(clk);
+ period_ps = DIV_ROUND_UP(NSEC_PER_SEC * 1000, clk_hw_get_rate(hw));
+
+ /*
+* First compute the phase index (p), the remainder (r) is the
+* part we'll try to acheive using the delays (d).
+*/
+ r = do_div(degrees, 360 / 1 << (ph->phase.width));
+ d = DIV_ROUND_CLOSEST(r * period_ps,
+ 360 * ph->delay_step_ps);
+ d = min(d, PMASK(ph->delay.width));
+
+ meson_parm_write(clk->map, >phase, degrees);
+ meson_parm_write(clk->map, >delay, d);
+ return 0;
+}
+
+const struct clk_ops meson_clk_phase_delay_ops = {
+ .get_phase = meson_clk_phase_delay_get_phase,
+ .set_phase = meson_clk_phase_delay_set_phase,
+};
+EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 00b3320..e6f0905 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -118,6 +118,12 @@ struct clk_regmap _name = {
\
}, \
};
+struct meson_clk_phase_delay_data {
+ struct parm phase;
+ struct parm delay;
+ unsigned intdelay_step_ps;
+};
+
/* clk_ops */
extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;
@@ -127,6 +133,7 @@ struct clk_regmap _name = {
\
extern const struct clk_ops meson_clk_phase_ops;
extern const struct clk_ops meson_vid_pll_div_ro_ops;
extern const struct clk_ops meson_sclk_div_ops;
+extern const struct clk_ops meson_clk_phase_delay_ops;
struct clk_hw *meson_clk_hw_register_input(struct device *dev,
const char *of_name,
--
1.9.1
[PATCH v8 3/4] clk: meson: add DT documentation for emmc clock controller
From: Yixun Lan
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 ++
include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
new file mode 100644
index 000..0f518e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
@@ -0,0 +1,39 @@
+* Amlogic MMC Sub Clock Controller Driver
+
+The Amlogic MMC clock controller generates and supplies clock to support
+MMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+ "amlogic,gx-mmc-clkc"
+ "amlogic,axg-mmc-clkc"
+
+- #clock-cells: should be 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names
+ - "clkin0", "clkin1"
+
+- reg: address of emmc sub clock register
+
+Example: Clock controller node:
+
+sd_mmc_c_clkc: clock-controller@7000 {
+ compatible = "amlogic,axg-mmc-clkc", "syscon";
+ reg = <0x0 0x7000 0x0 0x4>;
+ #clock-cells = <1>;
+
+ clock-names = "clkin0", "clkin1";
+ clocks = < CLKID_SD_MMC_C_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
+
+sd_emmc_b_clkc: clock-controller@5000 {
+ compatible = "amlogic,axg-mmc-clkc", "syscon";
+ reg = <0x0 0x5000 0x0 0x4>;
+
+ #clock-cells = <1>;
+ clock-names = "clkin0", "clkin1";
+ clocks = < CLKID_SD_EMMC_B_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h
b/include/dt-bindings/clock/amlogic,mmc-clkc.h
new file mode 100644
index 000..34a3c56
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV 0
+#define CLKID_MMC_PHASE_CORE 1
+#define CLKID_MMC_PHASE_TX 2
+#define CLKID_MMC_PHASE_RX 3
+
+#endif
--
1.9.1
[PATCH v8 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller
From: Liang Yang Add initial support for the Amlogic NAND flash controller which found in the Meson-GXBB/GXL/AXG SoCs. Signed-off-by: Liang Yang Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- drivers/mtd/nand/raw/Kconfig | 10 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/meson_nand.c | 1467 + 3 files changed, 1478 insertions(+) create mode 100644 drivers/mtd/nand/raw/meson_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 1a55d3e..d05ff20 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -541,4 +541,14 @@ config MTD_NAND_TEGRA is supported. Extra OOB bytes when using HW ECC are currently not supported. +config MTD_NAND_MESON + tristate "Support for NAND controller on Amlogic's Meson SoCs" + depends on ARCH_MESON || COMPILE_TEST + depends on COMMON_CLK_AMLOGIC + select COMMON_CLK_REGMAP_MESON + select MFD_SYSCON + help + Enables support for NAND controller on Amlogic's Meson SoCs. + This controller is found on Meson GXBB, GXL, AXG SoCs. + endif # MTD_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 57159b3..a2cc2fe 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o +obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c new file mode 100644 index 000..380c4e4 --- /dev/null +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -0,0 +1,1467 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson Nand Flash Controller Driver + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Liang Yang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NFC_REG_CMD0x00 +#define NFC_CMD_IDLE (0xc << 14) +#define NFC_CMD_CLE(0x5 << 14) +#define NFC_CMD_ALE(0x6 << 14) +#define NFC_CMD_ADL((0 << 16) | (3 << 20)) +#define NFC_CMD_ADH((1 << 16) | (3 << 20)) +#define NFC_CMD_AIL((2 << 16) | (3 << 20)) +#define NFC_CMD_AIH((3 << 16) | (3 << 20)) +#define NFC_CMD_SEED ((8 << 16) | (3 << 20)) +#define NFC_CMD_M2N((0 << 17) | (2 << 20)) +#define NFC_CMD_N2M((1 << 17) | (2 << 20)) +#define NFC_CMD_RB BIT(20) +#define NFC_CMD_SCRAMBLER_ENABLE BIT(19) +#define NFC_CMD_SCRAMBLER_DISABLE 0 +#define NFC_CMD_SHORTMODE_DISABLE 0 +#define NFC_CMD_RB_INT BIT(14) + +#define NFC_CMD_GET_SIZE(x)(((x) >> 22) & GENMASK(4, 0)) + +#define NFC_REG_CFG0x04 +#define NFC_REG_DADR 0x08 +#define NFC_REG_IADR 0x0c +#define NFC_REG_BUF0x10 +#define NFC_REG_INFO 0x14 +#define NFC_REG_DC 0x18 +#define NFC_REG_ADR0x1c +#define NFC_REG_DL 0x20 +#define NFC_REG_DH 0x24 +#define NFC_REG_CADR 0x28 +#define NFC_REG_SADR 0x2c +#define NFC_REG_PINS 0x30 +#define NFC_REG_VER0x38 + +#define NFC_RB_IRQ_EN BIT(21) + +#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ + ( \ + (cmd_dir) | \ + ((ran) << 19) | \ + ((bch) << 14) | \ + ((short_mode) << 13)| \ + (((page_size) & 0x7f) << 6) | \ + ((pages) & 0x3f)\ + ) + +#define GENCMDDADDRL(adl, addr)((adl) | ((addr) & 0x)) +#define GENCMDDADDRH(adh, addr)((adh) | (((addr) >> 16) & 0x)) +#define GENCMDIADDRL(ail, addr)((ail) | ((addr) & 0x)) +#define GENCMDIADDRH(aih, addr)((aih) | (((addr) >> 16) & 0x)) + +#define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N) + +#define ECC_CHECK_RETURN_FF(-1) + +#define NAND_CE0 (0xe << 10) +#define NAND_CE1 (0xd << 10) + +#define
[PATCH v8 1/2] dt-bindings: nand: meson: add Amlogic NAND controller driver
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
new file mode 100644
index 000..3983c11
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
@@ -0,0 +1,60 @@
+Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
+
+This file documents the properties in addition to those available in
+the MTD NAND bindings.
+
+Required properties:
+- compatible : contains one of:
+ - "amlogic,meson-gxl-nfc"
+ - "amlogic,meson-axg-nfc"
+- clocks :
+ A list of phandle + clock-specifier pairs for the clocks listed
+ in clock-names.
+
+- clock-names: Should contain the following:
+ "core" - NFC module gate clock
+ "device" - device clock from eMMC sub clock controller
+ "rx" - rx clock phase
+ "tx" - tx clock phase
+
+- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC
+ controller port C
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Other properties:
+see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+
+Example demonstrate on AXG SoC:
+
+ sd_emmc_c_clkc: mmc@7000 {
+ compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
+ reg = <0x0 0x7000 0x0 0x800>;
+ };
+
+ nand-controller@7800 {
+ compatible = "amlogic,meson-axg-nfc";
+ reg = <0x0 0x7800 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+
+ clocks = < CLKID_SD_EMMC_C>,
+ <_emmc_c_clkc CLKID_MMC_DIV>,
+ <_emmc_c_clkc CLKID_MMC_PHASE_RX>,
+ <_emmc_c_clkc CLKID_MMC_PHASE_TX>;
+ clock-names = "core", "device", "rx", "tx";
+ amlogic,mmc-syscon = <_emmc_c_clkc>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ };
+ };
--
1.9.1
[PATCH v8 0/2] mtd: rawnand: meson: add Amlogic NAND driver support
These two patches try to add initial NAND driver support for Amlogic Meson SoCs, current it has been tested on GXL(p212) and AXG(s400) platform. Changes since V6 at [8] - fix bitflips checking for blank pages - trace the latest commit with nand/next branch - checking the return of meson_nand_op_get_dma_safe_*input/output*_buf - add .detach_chip for free meson_nand.data_buf/info_buf Changes since V6 at [7] - use timings->tBERS_max as the maximum time out, delete NFC_CMD_RB_TIMEOUT - fix nand_rw_cmd and support small block flash and which row address less than 3 - fix coding style - replace readl/writel_* with readl/writel_relaxed* - delete ECC_SET_PROTECTED_OOB_BYTE and ECC_GET_PROTECTED_OOB_BYTE - implement dma access for read_buf and write_buf, more efficient. - delete waiting dma finish in write process and let NAND_CMD_PAGEPROG and RB command go on queuing - add waiting the completed flag of last ecc page be set, for more strict Changes since v5 at [6]: - use instr->delay_ns in exec_op() to caculate the delay cycle - delete struct meson_nfc_info_format and use macros instead - delete "is_scramble" in struct meson_nfc_nand_chip - add WARN_ON_ONCE() for chip > MAX_CE_NUM - drop param *mtd* or struct *nfc* if param *nand exist - substitute set_data_oob and get_data_oob for prase_data_oob and format_data_oob - split timings caculating and setting timings - move info_buf and data_buf to struct meson_nfc_nand_chip Changes since v4 at [5]: - remove the initial default divider(CLK_DIV_MASK) in meson_nfc_clk_init() - dt-bindings: remove staus, add "rx" and "tx" clock, and node rename Changes since v3 at [4]: - remove partition table and some used props from dt-bindings Changes since v2 at [3]: - remove some hardcode time value, like twb - use dev wait R/B instead of nand_soft_waitrdy - implement nfc ecc init by ecc helper - rework nfc buffer init to register the maximun buffer when several chips - free nfc buffer when error and cleanup - add variable to teack all the already assigned CS lines - fix mtd->name use the first cs line only - remove dt "nand-enable-scrambler" and use NAND_NEED_SCRAMBLING instead. - move setuping ECC fileds after the identification phase - use nand_scan() and attach_chip() - check one event to return IRQ_NONE - delete cast when of_device_get_match_data - use nand_controller_init() helper - remove nfc driver complains when calling devm_ioremap_resource - clear irqs before setting up irq handler Changes since v1 at [1]: - adopt property amlogic,nand-enable-scrambler - thanks Martin - drop nand pins in DT - convert clk access to emmc clkc model - fix regiser field definition alignment - drop nand-user-mode - parse cs id from DT - rework n2m, m2n function - explain why insert two "IDLE" command - implement exec_op() - drop meson_nfc_get_nand_chip_dts() - release resource once error occur in meson_nfc_nand_chips_init(), - call nand_cleanup(nand) once mtd_device_register fail Items not addressed ( or confirmed ) in this version: - convert to ECC conf helper() - convert to dma coherent API - how to construct mtd->name [1] https://lkml.kernel.org/r/20180613161314.14894-1-yixun@amlogic.com [2] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180719094612.5833-1-yixun@amlogic.com [4] https://lkml.kernel.org/r/1536317831-58056-1-git-send-email-jianxin@amlogic.com/ [5] https://lore.kernel.org/r/1537433449-65213-2-git-send-email-jianxin@amlogic.com/ [6] https://lore.kernel.org/r/1539839345-14021-1-git-send-email-jianxin@amlogic.com [7] https://lore.kernel.org/r/1541090542-19618-1-git-send-email-jianxin@amlogic.com [8] http://lkml.kernel.org/r/1542386439-30166-1-git-send-email-jianxin@amlogic.com Liang Yang (2): dt-bindings: nand: meson: add Amlogic NAND controller driver mtd: rawnand: meson: add support for Amlogic NAND flash controller .../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60 + drivers/mtd/nand/raw/Kconfig | 10 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/meson_nand.c | 1467 4 files changed, 1538 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt create mode 100644 drivers/mtd/nand/raw/meson_nand.c -- 1.9.1
Re: [PATCH RESEND v7 3/4] clk: meson: add sub MMC clock controller driver
On 2018/12/13 17:01, Jerome Brunet wrote: > On Thu, 2018-12-13 at 12:55 +0800, Jianxin Pan wrote: >> On 2018/12/12 0:59, Jerome Brunet wrote: >>> On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote: >>>> From: Yixun Lan >>>> >> [...] >>>> >>>> +config COMMON_CLK_MMC_MESON >>>> + tristate "Meson MMC Sub Clock Controller Driver" >>>> + select MFD_SYSCON >>>> + select COMMON_CLK_AMLOGIC >>>> + select COMMON_CLK_AMLOGIC_AUDIO >>> >>> No it is wrong for the mmc to select AUDIO clocks. >>> If as a result of your patch sclk is needed for things, make the necessary >>> change in the Makefile. >> OK, I will add COMMON_CLK_AMLOGIC_SCLKDIV for sclk-div. > > No! There is no reason to create a specific configuration for this. > please put it under COMMON_CLK_AMLOGIC OK, I will use COMMON_CLK_AMLOGIC and clkc.h for sclk-div in the next version. Thank you. > >> [...]>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include [...]
Re: [PATCH RESEND v7 4/4] clk: meson: add one based divider support for sclk divider
Hi Jerome,
Thanks for the fully review, we really appreciate your time.
On 2018/12/12 1:16, Jerome Brunet wrote:
> On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote:
>> When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
>> one based divider (div = val), and zero value gates the clock
>>
>> Signed-off-by: Jianxin Pan
>> ---
>> drivers/clk/meson/clkc-audio.h | 1 +
>> drivers/clk/meson/sclk-div.c | 28 ++--
>> 2 files changed, 19 insertions(+), 10 deletions(-)
>
> Such a patch should be done earlier in the series, at least before using sclk
> in your controller, otherwise thing will be broken in between
>
I will move it to the first one of the patchset.
> In general, I would prefer if you had added two helper function to deal with
> the translation between register value and divider value.
>
> Only these function should care about CLK_DIVIDER_ONE_BASED, the rest should
> just call them.
>
> This, we will be able to deal the with HI (duty cycle) part as well, which you
> completly skiped.
>
> I know your device does not have this, but still the code has to make sense.
>
OK, I will add two helper for value and register translation, and then appy
them to both div and hi.
>>
>> diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
>> index 0a7c157..9bd6ced 100644
>> --- a/drivers/clk/meson/clkc-audio.h
>> +++ b/drivers/clk/meson/clkc-audio.h
>> @@ -20,6 +20,7 @@ struct meson_sclk_div_data {
>> struct parm hi;
>> unsigned int cached_div;
>> struct clk_duty cached_duty;
>> +u8 flags;
>> };
>>
>> extern const struct clk_ops meson_clk_triphase_ops;
>> diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c
>> index bc64019..d98707b 100644
>> --- a/drivers/clk/meson/sclk-div.c
>> +++ b/drivers/clk/meson/sclk-div.c
>> @@ -24,22 +24,23 @@
>> return (struct meson_sclk_div_data *)clk->data;
>> }
>>
>> -static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
>> -{
>> -return (1 << sclk->div.width) - 1;
>> -}
>> -
>> static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
>> {
>> -return sclk_div_maxval(sclk) + 1;
>> +if (sclk->flags & CLK_DIVIDER_ONE_BASED)
>> +return clk_div_mask(sclk->div.width);
>> +else
>> +return clk_div_mask(sclk->div.width) + 1;
>
> seems over complicated.
> why no call clk_div_mask just once, and add 1 if necessary ?
Yes, I will use helper here.
>
>> }
>>
>> static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
>> unsigned long prate, int maxdiv)
>> {
>> int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
>> +struct clk_regmap *clk = to_clk_regmap(hw);
>> +struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
>> +int mindiv = (sclk->flags & CLK_DIVIDER_ONE_BASED) ? 1 : 2;
>
> This is why I want helpers, don't like this above
OK, I will replace it with helpers.
>
>>
>> -return clamp(div, 2, maxdiv);
>> +return clamp(div, mindiv, maxdiv);
>> }
>>
>> static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate,
>> @@ -47,7 +48,7 @@ static int sclk_div_bestdiv(struct clk_hw *hw, unsigned
>> long rate,
>> struct meson_sclk_div_data *sclk)
>> {
>> struct clk_hw *parent = clk_hw_get_parent(hw);
>> -int bestdiv = 0, i;
>> +int bestdiv = 0, i, mindiv;
>> unsigned long maxdiv, now, parent_now;
>> unsigned long best = 0, best_parent = 0;
>>
>> @@ -64,8 +65,9 @@ static int sclk_div_bestdiv(struct clk_hw *hw, unsigned
>> long rate,
>> * unsigned long in rate * i below
>> */
>> maxdiv = min(ULONG_MAX / rate, maxdiv);
>> +mindiv = (sclk->flags & CLK_DIVIDER_ONE_BASED) ? 1 : 2;
>>
>> -for (i = 2; i <= maxdiv; i++) {
>> +for (i = mindiv; i <= maxdiv; i++) {
>> /*
>> * It's the most ideal case if the requested rate can be
>> * divided from parent clock without needing to change
>> @@ -153,10 +155,14 @@ static int sclk_div_get_duty_cycle(struct clk_hw *hw,
>> static void sclk_apply_divider(struct clk_regmap *clk,
>> struct meson_sclk_div_data *sclk)
>> {
>> +unsigned int div;
>> +
>> if (MESON_PARM_APPLICABLE(>hi))
>> sclk_apply_ratio(clk, sclk);
>&
Re: [PATCH RESEND v7 3/4] clk: meson: add sub MMC clock controller driver
On 2018/12/12 0:59, Jerome Brunet wrote:
> On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote:
>> From: Yixun Lan
>>
[...]
>>
>> +config COMMON_CLK_MMC_MESON
>> +tristate "Meson MMC Sub Clock Controller Driver"
>> +select MFD_SYSCON
>> +select COMMON_CLK_AMLOGIC
>> +select COMMON_CLK_AMLOGIC_AUDIO
>
> No it is wrong for the mmc to select AUDIO clocks.
> If as a result of your patch sclk is needed for things, make the necessary
> change in the Makefile.
OK, I will add COMMON_CLK_AMLOGIC_SCLKDIV for sclk-div.
>
[...]>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "clkc.h"
>> +#include "clkc-audio.h"
>
> Again having audio in the mmc controller is wrong.
> Please make the necessary rework.
Yes, I will split out sclk-div.h from clkc-audio.h in the next version.
Thanks for your time.
>
>> +
>> +/* clock ID used by internal driver */
>> +#define CLKID_MMC_MUX 0
>> +
>> +#define SD_EMMC_CLOCK 0
>^
> why the multiple space here ? this looks odd
I will check the alignement in the whole patchset and fix them, Thank you.
>
>> +#define CLK_DELAY_STEP_PS 200
>
> Please keep thing aligned aligned consistently.
>
>> +
>> +#define MUX_CLK_NUM_PARENTS 2
>> +#define MMC_MAX_CLKS5
>> +
>> +struct mmc_clkc_data {
>> +struct meson_clk_phase_delay_data tx;
>> +struct meson_clk_phase_delay_data rx;
>
> Why use a tab above ?
OK
>
>> +};
>> +
>> +static struct clk_regmap_mux_data mmc_clkc_mux_data = {
>> +.offset = SD_EMMC_CLOCK,
>> +.mask = 0x3,
>> +.shift = 6,
>> +};
>> +
>> +static const struct meson_sclk_div_data mmc_clkc_div_data = {
>> +.div = {
>> +.reg_off = SD_EMMC_CLOCK,
>> +.shift = (0),
>> +.width = (6),
>
> Please remove the unncessary parenthesis
OK, I will remove them.
>
>> +},
>> +.hi = {
>> +.width = 0,
>> +},
>
> structure is a static const, all non-list members will be zero
> drop the
OK, I will remove it in the next version.
>
>> +.flags = CLK_DIVIDER_ONE_BASED,
>> +};
>> +
>> +static struct meson_clk_phase_data mmc_clkc_core_phase = {
>> +.ph = {
>> +.reg_off= SD_EMMC_CLOCK,
>> +.shift = 8,
>> +.width = 2,
>> +}
>> +};
>> +
>> +static const struct mmc_clkc_data mmc_clkc_gx_data = {
>> +.tx = {
>> +.phase = {
>> +.reg_off= SD_EMMC_CLOCK,
>> +.shift = 10,
>> +.width = 2,
>> +},
>> +.delay = {
>> +.reg_off= SD_EMMC_CLOCK,
>> +.shift = 16,
>> +.width = 4,
>> +},
>
> Again, an effort on alignement would appreciated, same below
OK, I will fix them.
>
>> +.delay_step_ps = CLK_DELAY_STEP_PS,
>> +},
>> +.rx = {
>> +.phase = {
>> +.reg_off= SD_EMMC_CLOCK,
>> +.shift = 12,
>> +.width = 2,
>> +},
>> +.delay = {
>> +.reg_off= SD_EMMC_CLOCK,
>> +.shift = 20,
>> +.width = 4,
>> +},
>> +.delay_step_ps = CLK_DELAY_STEP_PS,
>> +},
>> +};
>> +
>> +static const struct mmc_clkc_data mmc_clkc_axg_data = {
>> +.tx = {
>> +.phase = {
>> +.reg_off= SD_EMMC_CLOCK,
>> +.shift = 10,
>> +.width = 2,
>> +},
>> +.delay = {
>> +.reg_off= SD_EMMC_CLOCK,
>> +.shift = 16,
>> +.width = 6,
>> +},
>> +.delay_step_ps = CLK_DELAY_STEP_PS,
>> +},
>> +.rx = {
>> +.phase = {
>> +.reg_off= SD_EMMC_CLOCK,
>> +.shift = 12,
>> +.width = 2,
>> +},
>> +
Re: [PATCH RESEND v7 1/4] clk: meson: add emmc sub clock phase delay driver
HI Jerome,
On 2018/12/12 0:28, Jerome Brunet wrote:
> On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote:
>> From: Yixun Lan
>>
[...]
>> +
>> +static inline struct meson_clk_phase_delay_data *
>> +meson_clk_get_phase_delay_data(struct clk_regmap *clk)
>> +{
>> +return clk->data;
>> +}
>
> This is only usefull in the related clock driver, no need to export it
OK, I will move it to clk-phase-delay.c.
Thanks for the review.
>
>> +
>> /* clk_ops */
>> extern const struct clk_ops meson_clk_pll_ro_ops;
>> extern const struct clk_ops meson_clk_pll_ops;
>> @@ -112,5 +124,6 @@ struct clk_regmap _name = {
>> \
>> extern const struct clk_ops meson_clk_mpll_ro_ops;
>> extern const struct clk_ops meson_clk_mpll_ops;
>> extern const struct clk_ops meson_clk_phase_ops;
>> +extern const struct clk_ops meson_clk_phase_delay_ops;
>>
>> #endif /* __CLKC_H */
>
>
> .
>
[PATCH RESEND v7 2/4] clk: meson: add DT documentation for emmc clock controller
From: Yixun Lan
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 ++
include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
new file mode 100644
index 000..0f518e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
@@ -0,0 +1,39 @@
+* Amlogic MMC Sub Clock Controller Driver
+
+The Amlogic MMC clock controller generates and supplies clock to support
+MMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+ "amlogic,gx-mmc-clkc"
+ "amlogic,axg-mmc-clkc"
+
+- #clock-cells: should be 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names
+ - "clkin0", "clkin1"
+
+- reg: address of emmc sub clock register
+
+Example: Clock controller node:
+
+sd_mmc_c_clkc: clock-controller@7000 {
+ compatible = "amlogic,axg-mmc-clkc", "syscon";
+ reg = <0x0 0x7000 0x0 0x4>;
+ #clock-cells = <1>;
+
+ clock-names = "clkin0", "clkin1";
+ clocks = < CLKID_SD_MMC_C_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
+
+sd_emmc_b_clkc: clock-controller@5000 {
+ compatible = "amlogic,axg-mmc-clkc", "syscon";
+ reg = <0x0 0x5000 0x0 0x4>;
+
+ #clock-cells = <1>;
+ clock-names = "clkin0", "clkin1";
+ clocks = < CLKID_SD_EMMC_B_CLK0>,
+< CLKID_FCLK_DIV2>;
+};
diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h
b/include/dt-bindings/clock/amlogic,mmc-clkc.h
new file mode 100644
index 000..162b949
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson MMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Yixun Lan
+ */
+
+#ifndef __MMC_CLKC_H
+#define __MMC_CLKC_H
+
+#define CLKID_MMC_DIV 1
+#define CLKID_MMC_PHASE_CORE 2
+#define CLKID_MMC_PHASE_TX 3
+#define CLKID_MMC_PHASE_RX 4
+
+#endif
--
1.9.1
[PATCH RESEND v7 4/4] clk: meson: add one based divider support for sclk divider
When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
one based divider (div = val), and zero value gates the clock
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/clkc-audio.h | 1 +
drivers/clk/meson/sclk-div.c | 28 ++--
2 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
index 0a7c157..9bd6ced 100644
--- a/drivers/clk/meson/clkc-audio.h
+++ b/drivers/clk/meson/clkc-audio.h
@@ -20,6 +20,7 @@ struct meson_sclk_div_data {
struct parm hi;
unsigned int cached_div;
struct clk_duty cached_duty;
+ u8 flags;
};
extern const struct clk_ops meson_clk_triphase_ops;
diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c
index bc64019..d98707b 100644
--- a/drivers/clk/meson/sclk-div.c
+++ b/drivers/clk/meson/sclk-div.c
@@ -24,22 +24,23 @@
return (struct meson_sclk_div_data *)clk->data;
}
-static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
-{
- return (1 << sclk->div.width) - 1;
-}
-
static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
{
- return sclk_div_maxval(sclk) + 1;
+ if (sclk->flags & CLK_DIVIDER_ONE_BASED)
+ return clk_div_mask(sclk->div.width);
+ else
+ return clk_div_mask(sclk->div.width) + 1;
}
static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
unsigned long prate, int maxdiv)
{
int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+ int mindiv = (sclk->flags & CLK_DIVIDER_ONE_BASED) ? 1 : 2;
- return clamp(div, 2, maxdiv);
+ return clamp(div, mindiv, maxdiv);
}
static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate,
@@ -47,7 +48,7 @@ static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long
rate,
struct meson_sclk_div_data *sclk)
{
struct clk_hw *parent = clk_hw_get_parent(hw);
- int bestdiv = 0, i;
+ int bestdiv = 0, i, mindiv;
unsigned long maxdiv, now, parent_now;
unsigned long best = 0, best_parent = 0;
@@ -64,8 +65,9 @@ static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long
rate,
* unsigned long in rate * i below
*/
maxdiv = min(ULONG_MAX / rate, maxdiv);
+ mindiv = (sclk->flags & CLK_DIVIDER_ONE_BASED) ? 1 : 2;
- for (i = 2; i <= maxdiv; i++) {
+ for (i = mindiv; i <= maxdiv; i++) {
/*
* It's the most ideal case if the requested rate can be
* divided from parent clock without needing to change
@@ -153,10 +155,14 @@ static int sclk_div_get_duty_cycle(struct clk_hw *hw,
static void sclk_apply_divider(struct clk_regmap *clk,
struct meson_sclk_div_data *sclk)
{
+ unsigned int div;
+
if (MESON_PARM_APPLICABLE(>hi))
sclk_apply_ratio(clk, sclk);
- meson_parm_write(clk->map, >div, sclk->cached_div - 1);
+ div = (sclk->flags & CLK_DIVIDER_ONE_BASED) ?
+ sclk->cached_div : (sclk->cached_div - 1);
+ meson_parm_write(clk->map, >div, div);
}
static int sclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -223,6 +229,8 @@ static void sclk_div_init(struct clk_hw *hw)
/* if the divider is initially disabled, assume max */
if (!val)
sclk->cached_div = sclk_div_maxdiv(sclk);
+ else if (sclk->flags & CLK_DIVIDER_ONE_BASED)
+ sclk->cached_div = val;
else
sclk->cached_div = val + 1;
--
1.9.1
[PATCH RESEND v7 3/4] clk: meson: add sub MMC clock controller driver
From: Yixun Lan
The patch will add a MMC clock controller driver which used by MMC or NAND,
It provide a mux and divider clock, and three phase clocks - core, tx, tx.
Two clocks are provided as the parent of MMC clock controller from
upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Kconfig| 10 ++
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/mmc-clkc.c | 313 +++
3 files changed, 324 insertions(+)
create mode 100644 drivers/clk/meson/mmc-clkc.c
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index efaa70f..6bb0d44 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -15,6 +15,16 @@ config COMMON_CLK_MESON_AO
select COMMON_CLK_REGMAP_MESON
select RESET_CONTROLLER
+config COMMON_CLK_MMC_MESON
+ tristate "Meson MMC Sub Clock Controller Driver"
+ select MFD_SYSCON
+ select COMMON_CLK_AMLOGIC
+ select COMMON_CLK_AMLOGIC_AUDIO
+ help
+ Support for the MMC sub clock controller on Amlogic Meson Platform,
+ which include S905 (GXBB, GXL), A113D/X (AXG) devices.
+ Say Y if you want this clock enabled.
+
config COMMON_CLK_REGMAP_MESON
bool
select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 39ce566..31c16d5 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
new file mode 100644
index 000..f5a79a4
--- /dev/null
+++ b/drivers/clk/meson/mmc-clkc.c
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ * Author: Jianxin Pan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clkc.h"
+#include "clkc-audio.h"
+
+/* clock ID used by internal driver */
+#define CLKID_MMC_MUX 0
+
+#define SD_EMMC_CLOCK0
+#define CLK_DELAY_STEP_PS200
+
+#define MUX_CLK_NUM_PARENTS2
+#define MMC_MAX_CLKS 5
+
+struct mmc_clkc_data {
+ struct meson_clk_phase_delay_data tx;
+ struct meson_clk_phase_delay_data rx;
+};
+
+static struct clk_regmap_mux_data mmc_clkc_mux_data = {
+ .offset = SD_EMMC_CLOCK,
+ .mask = 0x3,
+ .shift = 6,
+};
+
+static const struct meson_sclk_div_data mmc_clkc_div_data = {
+ .div = {
+ .reg_off = SD_EMMC_CLOCK,
+ .shift = (0),
+ .width = (6),
+ },
+ .hi = {
+ .width = 0,
+ },
+ .flags = CLK_DIVIDER_ONE_BASED,
+};
+
+static struct meson_clk_phase_data mmc_clkc_core_phase = {
+ .ph = {
+ .reg_off= SD_EMMC_CLOCK,
+ .shift = 8,
+ .width = 2,
+ }
+};
+
+static const struct mmc_clkc_data mmc_clkc_gx_data = {
+ .tx = {
+ .phase = {
+ .reg_off= SD_EMMC_CLOCK,
+ .shift = 10,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off= SD_EMMC_CLOCK,
+ .shift = 16,
+ .width = 4,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+ .rx = {
+ .phase = {
+ .reg_off= SD_EMMC_CLOCK,
+ .shift = 12,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off= SD_EMMC_CLOCK,
+ .shift = 20,
+ .width = 4,
+ },
+ .delay_step_ps = CLK_DELAY_STEP_PS,
+ },
+};
+
+static const struct mmc_clkc_data mmc_clkc_axg_data = {
+ .tx = {
+ .phase = {
+ .reg_off= SD_EMMC_CLOCK,
+ .shift = 10,
+ .width = 2,
+ },
+ .delay = {
+ .reg_off= SD_EMMC_CLO
[PATCH RESEND v7 1/4] clk: meson: add emmc sub clock phase delay driver
From: Yixun Lan
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/clk-phase-delay.c | 64 +
drivers/clk/meson/clkc.h| 13
3 files changed, 78 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/meson/clk-phase-delay.c
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 72ec8c4..39ce566 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,7 +2,7 @@
# Makefile for Meson specific clk
#
-obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
clk-phase-delay.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
diff --git a/drivers/clk/meson/clk-phase-delay.c
b/drivers/clk/meson/clk-phase-delay.c
new file mode 100644
index 000..84e7b63
--- /dev/null
+++ b/drivers/clk/meson/clk-phase-delay.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson MMC Sub Clock Controller Driver
+ *
+ * Copyright (c) 2017 Baylibre SAS.
+ * Author: Jerome Brunet
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yixun Lan
+ * Author: Jianxin Pan
+ */
+
+#include
+#include "clkc.h"
+
+static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph;
+ unsigned long period_ps, p, d;
+ int degrees;
+
+ ph = meson_clk_get_phase_delay_data(clk);
+ p = meson_parm_read(clk->map, >phase);
+ degrees = p * 360 / (1 << (ph->phase.width));
+
+ period_ps = DIV_ROUND_UP(NSEC_PER_SEC * 1000,
+clk_hw_get_rate(hw));
+
+ d = meson_parm_read(clk->map, >delay);
+ degrees += d * ph->delay_step_ps * 360 / period_ps;
+ degrees %= 360;
+
+ return degrees;
+}
+
+static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_phase_delay_data *ph;
+ unsigned long period_ps, d = 0, r;
+
+ ph = meson_clk_get_phase_delay_data(clk);
+ period_ps = DIV_ROUND_UP(NSEC_PER_SEC * 1000, clk_hw_get_rate(hw));
+
+ /*
+* First compute the phase index (p), the remainder (r) is the
+* part we'll try to acheive using the delays (d).
+*/
+ r = do_div(degrees, 360 / 1 << (ph->phase.width));
+ d = DIV_ROUND_CLOSEST(r * period_ps,
+ 360 * ph->delay_step_ps);
+ d = min(d, PMASK(ph->delay.width));
+
+ meson_parm_write(clk->map, >phase, degrees);
+ meson_parm_write(clk->map, >delay, d);
+ return 0;
+}
+
+const struct clk_ops meson_clk_phase_delay_ops = {
+ .get_phase = meson_clk_phase_delay_get_phase,
+ .set_phase = meson_clk_phase_delay_set_phase,
+};
+EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 6b96d55..30470c6 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -105,6 +105,18 @@ struct clk_regmap _name = {
\
}, \
};
+struct meson_clk_phase_delay_data {
+ struct parm phase;
+ struct parm delay;
+ unsigned intdelay_step_ps;
+};
+
+static inline struct meson_clk_phase_delay_data *
+meson_clk_get_phase_delay_data(struct clk_regmap *clk)
+{
+ return clk->data;
+}
+
/* clk_ops */
extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;
@@ -112,5 +124,6 @@ struct clk_regmap _name = {
\
extern const struct clk_ops meson_clk_mpll_ro_ops;
extern const struct clk_ops meson_clk_mpll_ops;
extern const struct clk_ops meson_clk_phase_ops;
+extern const struct clk_ops meson_clk_phase_delay_ops;
#endif /* __CLKC_H */
--
1.9.1
[PATCH RESEND v7 0/4] clk: meson: add a sub EMMC clock controller support
This driver will add a MMC clock controller driver support. The original idea about adding a clock controller is during the discussion in the NAND driver mainline effort[1]. This driver is tested in the S400 board (AXG platform) with NAND driver. Changes since v6 [7]: - add one based support for sclk divier - alloc sclk in probe for multiple instance - fix coding styles Changes since v5 [6]: - remove divider ops with .init and use sclk_div instead - drop CLK_DIVIDER_ROUND_CLOSEST in mux and div - drop the useless type cast Changes since v4 [5]: - use struct parm in phase delay driver - remove 0 delay releted part in phase delay driver - don't rebuild the parent name once again - add divider ops with .init Changes since v3 [4]: - separate clk-phase-delay driver - replace clk_get_rate() with clk_hw_get_rate() - collect Rob's R-Y - drop 'meson-' prefix from compatible string Changes since v2 [3]: - squash dt-binding clock-id patch - update license - fix alignment - construct a clk register helper() function Changes since v1 [2]: - implement phase clock - update compatible name - adjust file name - divider probe() into small functions, and re-use them [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13 [2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com [4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com [5] https://lkml.kernel.org/r/20180809070724.11935-4-yixun@amlogic.com [6] https://lkml.kernel.org/r/1539839245-13793-1-git-send-email-jianxin@amlogic.com [7] https://lkml.kernel.org/r/1541089855-19356-1-git-send-email-jianxin@amlogic.com Yixun Lan (3): clk: meson: add emmc sub clock phase delay driver clk: meson: add DT documentation for emmc clock controller clk: meson: add sub MMC clock controller driver clk: meson: add one based divider support for sclk divider .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 +++ drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 3 +- drivers/clk/meson/clk-phase-delay.c| 64 + drivers/clk/meson/clkc-audio.h | 1 + drivers/clk/meson/clkc.h | 13 + drivers/clk/meson/mmc-clkc.c | 313 + drivers/clk/meson/sclk-div.c | 28 +- include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++ 9 files changed, 477 insertions(+), 11 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt create mode 100644 drivers/clk/meson/clk-phase-delay.c create mode 100644 drivers/clk/meson/mmc-clkc.c create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h -- 1.9.1
Re: [PATCH v7 2/4] clk: meson: add DT documentation for emmc clock controller
Hi Stephen, On 2018/12/4 6:45, Stephen Boyd wrote: > Quoting Jianxin Pan (2018-11-15 04:18:30) >> diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h >> b/include/dt-bindings/clock/amlogic,mmc-clkc.h >> new file mode 100644 >> index 000..162b949 >> --- /dev/null >> +++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h >> @@ -0,0 +1,17 @@ >> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ >> +/* >> + * Meson MMC sub clock tree IDs >> + * >> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. >> + * Author: Yixun Lan >> + */ >> + >> +#ifndef __MMC_CLKC_H >> +#define __MMC_CLKC_H >> + >> +#define CLKID_MMC_DIV 1 > > Why does the define numbering start with 1 instead of 0? > The Clock ID 0 is used by CLKID_MMC_MUX. CLKID_MMC_MUX is an internal clock which defined in drivers/clk/meson/mmc-clkc.c, and it's the parent of CLKID_MMC_DIV. >> +#define CLKID_MMC_PHASE_CORE 2 >> +#define CLKID_MMC_PHASE_TX 3 >> +#define CLKID_MMC_PHASE_RX 4 >> + > > . >
Re: [PATCH v7 2/4] clk: meson: add DT documentation for emmc clock controller
Hi Stephen, On 2018/12/4 6:45, Stephen Boyd wrote: > Quoting Jianxin Pan (2018-11-15 04:18:30) >> diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h >> b/include/dt-bindings/clock/amlogic,mmc-clkc.h >> new file mode 100644 >> index 000..162b949 >> --- /dev/null >> +++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h >> @@ -0,0 +1,17 @@ >> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ >> +/* >> + * Meson MMC sub clock tree IDs >> + * >> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. >> + * Author: Yixun Lan >> + */ >> + >> +#ifndef __MMC_CLKC_H >> +#define __MMC_CLKC_H >> + >> +#define CLKID_MMC_DIV 1 > > Why does the define numbering start with 1 instead of 0? > The Clock ID 0 is used by CLKID_MMC_MUX. CLKID_MMC_MUX is an internal clock which defined in drivers/clk/meson/mmc-clkc.c, and it's the parent of CLKID_MMC_DIV. >> +#define CLKID_MMC_PHASE_CORE 2 >> +#define CLKID_MMC_PHASE_TX 3 >> +#define CLKID_MMC_PHASE_RX 4 >> + > > . >
Re: [PATCH v7 0/4] clk: meson: add a sub EMMC clock controller support
Hi Jerome, I made some modifications as you suggested， could you please take a look? On 2018/11/15 20:18, Jianxin Pan wrote: > This driver will add a MMC clock controller driver support. > The original idea about adding a clock controller is during the > discussion in the NAND driver mainline effort[1]. > > This driver is tested in the S400 board (AXG platform) with NAND driver. > > Changes since v6 [7]: > - add one based support for sclk divier > - alloc sclk in probe for multiple instance > - fix coding styles > > Changes since v5 [6]: > - remove divider ops with .init and use sclk_div instead > - drop CLK_DIVIDER_ROUND_CLOSEST in mux and div > - drop the useless type cast > > Changes since v4 [5]: > - use struct parm in phase delay driver > - remove 0 delay releted part in phase delay driver > - don't rebuild the parent name once again > - add divider ops with .init > > Changes since v3 [4]: > - separate clk-phase-delay driver > - replace clk_get_rate() with clk_hw_get_rate() > - collect Rob's R-Y > - drop 'meson-' prefix from compatible string > > Changes since v2 [3]: > - squash dt-binding clock-id patch > - update license > - fix alignment > - construct a clk register helper() function > > Changes since v1 [2]: > - implement phase clock > - update compatible name > - adjust file name > - divider probe() into small functions, and re-use them > > [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13 > [2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com > [3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com > [4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com > [5] https://lkml.kernel.org/r/20180809070724.11935-4-yixun@amlogic.com > [6] > https://lkml.kernel.org/r/1539839245-13793-1-git-send-email-jianxin@amlogic.com > [7] > https://lkml.kernel.org/r/1541089855-19356-1-git-send-email-jianxin@amlogic.com > Yixun Lan (3): > clk: meson: add emmc sub clock phase delay driver > clk: meson: add DT documentation for emmc clock controller > clk: meson: add sub MMC clock controller driver > clk: meson: add one based divider support for sclk divider > > .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 +++ > drivers/clk/meson/Kconfig | 10 + > drivers/clk/meson/Makefile | 3 +- > drivers/clk/meson/clk-phase-delay.c| 64 + > drivers/clk/meson/clkc-audio.h | 1 + > drivers/clk/meson/clkc.h | 13 + > drivers/clk/meson/mmc-clkc.c | 313 > + > drivers/clk/meson/sclk-div.c | 28 +- > include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++ > 9 files changed, 477 insertions(+), 11 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt > create mode 100644 drivers/clk/meson/clk-phase-delay.c > create mode 100644 drivers/clk/meson/mmc-clkc.c > create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h >
Re: [PATCH v7 0/4] clk: meson: add a sub EMMC clock controller support
Hi Jerome, I made some modifications as you suggested， could you please take a look? On 2018/11/15 20:18, Jianxin Pan wrote: > This driver will add a MMC clock controller driver support. > The original idea about adding a clock controller is during the > discussion in the NAND driver mainline effort[1]. > > This driver is tested in the S400 board (AXG platform) with NAND driver. > > Changes since v6 [7]: > - add one based support for sclk divier > - alloc sclk in probe for multiple instance > - fix coding styles > > Changes since v5 [6]: > - remove divider ops with .init and use sclk_div instead > - drop CLK_DIVIDER_ROUND_CLOSEST in mux and div > - drop the useless type cast > > Changes since v4 [5]: > - use struct parm in phase delay driver > - remove 0 delay releted part in phase delay driver > - don't rebuild the parent name once again > - add divider ops with .init > > Changes since v3 [4]: > - separate clk-phase-delay driver > - replace clk_get_rate() with clk_hw_get_rate() > - collect Rob's R-Y > - drop 'meson-' prefix from compatible string > > Changes since v2 [3]: > - squash dt-binding clock-id patch > - update license > - fix alignment > - construct a clk register helper() function > > Changes since v1 [2]: > - implement phase clock > - update compatible name > - adjust file name > - divider probe() into small functions, and re-use them > > [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13 > [2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com > [3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com > [4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com > [5] https://lkml.kernel.org/r/20180809070724.11935-4-yixun@amlogic.com > [6] > https://lkml.kernel.org/r/1539839245-13793-1-git-send-email-jianxin@amlogic.com > [7] > https://lkml.kernel.org/r/1541089855-19356-1-git-send-email-jianxin@amlogic.com > Yixun Lan (3): > clk: meson: add emmc sub clock phase delay driver > clk: meson: add DT documentation for emmc clock controller > clk: meson: add sub MMC clock controller driver > clk: meson: add one based divider support for sclk divider > > .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 +++ > drivers/clk/meson/Kconfig | 10 + > drivers/clk/meson/Makefile | 3 +- > drivers/clk/meson/clk-phase-delay.c| 64 + > drivers/clk/meson/clkc-audio.h | 1 + > drivers/clk/meson/clkc.h | 13 + > drivers/clk/meson/mmc-clkc.c | 313 > + > drivers/clk/meson/sclk-div.c | 28 +- > include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++ > 9 files changed, 477 insertions(+), 11 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt > create mode 100644 drivers/clk/meson/clk-phase-delay.c > create mode 100644 drivers/clk/meson/mmc-clkc.c > create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h >
[PATCH v7 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller
From: Liang Yang Add initial support for the Amlogic NAND flash controller which found in the Meson-GXBB/GXL/AXG SoCs. Signed-off-by: Liang Yang Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- drivers/mtd/nand/raw/Kconfig | 10 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/meson_nand.c | 1417 + 3 files changed, 1428 insertions(+) create mode 100644 drivers/mtd/nand/raw/meson_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index c7efc31..223b041 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -541,4 +541,14 @@ config MTD_NAND_TEGRA is supported. Extra OOB bytes when using HW ECC are currently not supported. +config MTD_NAND_MESON + tristate "Support for NAND controller on Amlogic's Meson SoCs" + depends on ARCH_MESON || COMPILE_TEST + depends on COMMON_CLK_AMLOGIC + select COMMON_CLK_REGMAP_MESON + select MFD_SYSCON + help + Enables support for NAND controller on Amlogic's Meson SoCs. + This controller is found on Meson GXBB, GXL, AXG SoCs. + endif # MTD_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 57159b3..a2cc2fe 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o +obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c new file mode 100644 index 000..c566636 --- /dev/null +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -0,0 +1,1417 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson Nand Flash Controller Driver + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Liang Yang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NFC_REG_CMD0x00 +#define NFC_CMD_DRD(0x8 << 14) +#define NFC_CMD_IDLE (0xc << 14) +#define NFC_CMD_DWR(0x4 << 14) +#define NFC_CMD_CLE(0x5 << 14) +#define NFC_CMD_ALE(0x6 << 14) +#define NFC_CMD_ADL((0 << 16) | (3 << 20)) +#define NFC_CMD_ADH((1 << 16) | (3 << 20)) +#define NFC_CMD_AIL((2 << 16) | (3 << 20)) +#define NFC_CMD_AIH((3 << 16) | (3 << 20)) +#define NFC_CMD_SEED ((8 << 16) | (3 << 20)) +#define NFC_CMD_M2N((0 << 17) | (2 << 20)) +#define NFC_CMD_N2M((1 << 17) | (2 << 20)) +#define NFC_CMD_RB BIT(20) +#define NFC_CMD_IO6((0xb << 10) | (1 << 18)) +#define NFC_CMD_SCRAMBLER_ENABLE BIT(19) +#define NFC_CMD_RB_INT BIT(14) + +#define NFC_CMD_GET_SIZE(x)(((x) >> 22) & GENMASK(4, 0)) + +#define NFC_REG_CFG0x04 +#define NFC_REG_DADR 0x08 +#define NFC_REG_IADR 0x0c +#define NFC_REG_BUF0x10 +#define NFC_REG_INFO 0x14 +#define NFC_REG_DC 0x18 +#define NFC_REG_ADR0x1c +#define NFC_REG_DL 0x20 +#define NFC_REG_DH 0x24 +#define NFC_REG_CADR 0x28 +#define NFC_REG_SADR 0x2c +#define NFC_REG_PINS 0x30 +#define NFC_REG_VER0x38 + +#define NFC_RB_IRQ_EN BIT(21) +#define NFC_INT_MASK (3 << 20) + +#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ + ( \ + (cmd_dir) | \ + ((ran) << 19) | \ + ((bch) << 14) | \ + ((short_mode) << 13)| \ + (((page_size) & 0x7f) << 6) | \ + ((pages) & 0x3f)\ + ) + +#define GENCMDDADDRL(adl, addr)((adl) | ((addr) & 0x)) +#define GENCMDDADDRH(adh, addr)((adh) | (((addr) >> 16) & 0x)) +#define GENCMDIADDRL(ail, addr)((ail) | ((addr) & 0x)) +#define GENCMDIADDRH(aih, addr)((aih) | (((addr) >> 16) & 0x)) + +#define RB_STA(x) (1 << (26 + (x))) +#define DMA_DIR(dir)
[PATCH v7 1/2] dt-bindings: nand: meson: add Amlogic NAND controller driver
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
new file mode 100644
index 000..3983c11
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
@@ -0,0 +1,60 @@
+Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
+
+This file documents the properties in addition to those available in
+the MTD NAND bindings.
+
+Required properties:
+- compatible : contains one of:
+ - "amlogic,meson-gxl-nfc"
+ - "amlogic,meson-axg-nfc"
+- clocks :
+ A list of phandle + clock-specifier pairs for the clocks listed
+ in clock-names.
+
+- clock-names: Should contain the following:
+ "core" - NFC module gate clock
+ "device" - device clock from eMMC sub clock controller
+ "rx" - rx clock phase
+ "tx" - tx clock phase
+
+- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC
+ controller port C
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Other properties:
+see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+
+Example demonstrate on AXG SoC:
+
+ sd_emmc_c_clkc: mmc@7000 {
+ compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
+ reg = <0x0 0x7000 0x0 0x800>;
+ };
+
+ nand-controller@7800 {
+ compatible = "amlogic,meson-axg-nfc";
+ reg = <0x0 0x7800 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+
+ clocks = < CLKID_SD_EMMC_C>,
+ <_emmc_c_clkc CLKID_MMC_DIV>,
+ <_emmc_c_clkc CLKID_MMC_PHASE_RX>,
+ <_emmc_c_clkc CLKID_MMC_PHASE_TX>;
+ clock-names = "core", "device", "rx", "tx";
+ amlogic,mmc-syscon = <_emmc_c_clkc>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ };
+ };
--
1.9.1
[PATCH v7 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller
From: Liang Yang Add initial support for the Amlogic NAND flash controller which found in the Meson-GXBB/GXL/AXG SoCs. Signed-off-by: Liang Yang Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- drivers/mtd/nand/raw/Kconfig | 10 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/meson_nand.c | 1417 + 3 files changed, 1428 insertions(+) create mode 100644 drivers/mtd/nand/raw/meson_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index c7efc31..223b041 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -541,4 +541,14 @@ config MTD_NAND_TEGRA is supported. Extra OOB bytes when using HW ECC are currently not supported. +config MTD_NAND_MESON + tristate "Support for NAND controller on Amlogic's Meson SoCs" + depends on ARCH_MESON || COMPILE_TEST + depends on COMMON_CLK_AMLOGIC + select COMMON_CLK_REGMAP_MESON + select MFD_SYSCON + help + Enables support for NAND controller on Amlogic's Meson SoCs. + This controller is found on Meson GXBB, GXL, AXG SoCs. + endif # MTD_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 57159b3..a2cc2fe 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o +obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c new file mode 100644 index 000..c566636 --- /dev/null +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -0,0 +1,1417 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson Nand Flash Controller Driver + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Liang Yang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NFC_REG_CMD0x00 +#define NFC_CMD_DRD(0x8 << 14) +#define NFC_CMD_IDLE (0xc << 14) +#define NFC_CMD_DWR(0x4 << 14) +#define NFC_CMD_CLE(0x5 << 14) +#define NFC_CMD_ALE(0x6 << 14) +#define NFC_CMD_ADL((0 << 16) | (3 << 20)) +#define NFC_CMD_ADH((1 << 16) | (3 << 20)) +#define NFC_CMD_AIL((2 << 16) | (3 << 20)) +#define NFC_CMD_AIH((3 << 16) | (3 << 20)) +#define NFC_CMD_SEED ((8 << 16) | (3 << 20)) +#define NFC_CMD_M2N((0 << 17) | (2 << 20)) +#define NFC_CMD_N2M((1 << 17) | (2 << 20)) +#define NFC_CMD_RB BIT(20) +#define NFC_CMD_IO6((0xb << 10) | (1 << 18)) +#define NFC_CMD_SCRAMBLER_ENABLE BIT(19) +#define NFC_CMD_RB_INT BIT(14) + +#define NFC_CMD_GET_SIZE(x)(((x) >> 22) & GENMASK(4, 0)) + +#define NFC_REG_CFG0x04 +#define NFC_REG_DADR 0x08 +#define NFC_REG_IADR 0x0c +#define NFC_REG_BUF0x10 +#define NFC_REG_INFO 0x14 +#define NFC_REG_DC 0x18 +#define NFC_REG_ADR0x1c +#define NFC_REG_DL 0x20 +#define NFC_REG_DH 0x24 +#define NFC_REG_CADR 0x28 +#define NFC_REG_SADR 0x2c +#define NFC_REG_PINS 0x30 +#define NFC_REG_VER0x38 + +#define NFC_RB_IRQ_EN BIT(21) +#define NFC_INT_MASK (3 << 20) + +#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ + ( \ + (cmd_dir) | \ + ((ran) << 19) | \ + ((bch) << 14) | \ + ((short_mode) << 13)| \ + (((page_size) & 0x7f) << 6) | \ + ((pages) & 0x3f)\ + ) + +#define GENCMDDADDRL(adl, addr)((adl) | ((addr) & 0x)) +#define GENCMDDADDRH(adh, addr)((adh) | (((addr) >> 16) & 0x)) +#define GENCMDIADDRL(ail, addr)((ail) | ((addr) & 0x)) +#define GENCMDIADDRH(aih, addr)((aih) | (((addr) >> 16) & 0x)) + +#define RB_STA(x) (1 << (26 + (x))) +#define DMA_DIR(dir)
