from:"Kelvin Cheung"

Re: [PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-05-28 Thread Kelvin Cheung

Hi Boris,
I have the same feeling as Mychaela, and suffered from the 'high-level
controllers' as well.
Looking forward to your review, thanks!

Best regards,

Keguang Zhang

On 05/28/2016 08:12 PM, Boris Brezillon wrote:
> Hi Kelvin,
>
> On Sat, 28 May 2016 17:54:10 +0800
> Keguang Zhang <keguang.zh...@gmail.com> wrote:
>
>> From: Kelvin Cheung <keguang.zh...@gmail.com>
>>
>> This patch adds NAND driver for Loongson1B.
> I think your controller matches Mychaela's "high-level NAND controller"
> definition [1]. Mychaela, can you confirm the Loongson controller
> looks like yours?
>
> I'll do a detailed review of the code soon.
>
> Thanks,
>
> Boris
>
> [1]http://thread.gmane.org/gmane.linux.drivers.mtd/67346
>
>> Signed-off-by: Kelvin Cheung <keguang.zh...@gmail.com>
>>
>> ---
>> v3:
>>Replace __raw_readl/__raw_writel with readl/writel.
>>Split ls1x_nand into two structures: ls1x_nand_chip and 
>> ls1x_nand_controller.
>> V2:
>>Modify the dependency in Kconfig due to the changes of DMA module.
>> ---
>>  drivers/mtd/nand/Kconfig  |   8 +
>>  drivers/mtd/nand/Makefile |   1 +
>>  drivers/mtd/nand/loongson1_nand.c | 555 
>> ++
>>  3 files changed, 564 insertions(+)
>>  create mode 100644 drivers/mtd/nand/loongson1_nand.c
>>
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index f05e0e9..be20fb8 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -563,4 +563,12 @@ config MTD_NAND_QCOM
>>Enables support for NAND flash chips on SoCs containing the EBI2 NAND
>>controller. This controller is found on IPQ806x SoC.
>>  
>> +config MTD_NAND_LOONGSON1
>> +tristate "Support for Loongson1 SoC NAND controller"
>> +depends on MACH_LOONGSON32
>> +select DMADEVICES
>> +select LOONGSON1_DMA
>> +help
>> +Enables support for NAND Flash on Loongson1 SoC based boards.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index f553353..0310c0b 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)   += sunxi_nand.o
>>  obj-$(CONFIG_MTD_NAND_HISI504)  += hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>> +obj-$(CONFIG_MTD_NAND_LOONGSON1)+= loongson1_nand.o
>>  
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o
>> diff --git a/drivers/mtd/nand/loongson1_nand.c 
>> b/drivers/mtd/nand/loongson1_nand.c
>> new file mode 100644
>> index 000..86831773
>> --- /dev/null
>> +++ b/drivers/mtd/nand/loongson1_nand.c
>> @@ -0,0 +1,555 @@
>> +/*
>> + * NAND Flash Driver for Loongson 1 SoC
>> + *
>> + * Copyright (C) 2015-2016 Zhang, Keguang <keguang.zh...@gmail.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +
>> +/* Loongson 1 NAND Register Definitions */
>> +#define NAND_CMD0x0
>> +#define NAND_ADDRL  0x4
>> +#define NAND_ADDRH  0x8
>> +#define NAND_TIMING 0xc
>> +#define NAND_IDL0x10
>> +#define NAND_IDH0x14
>> +#define NAND_STATUS 0x14
>> +#define NAND_PARAM  0x18
>> +#define NAND_OP_NUM 0x1c
>> +#define NAND_CS_RDY 0x20
>> +
>> +#define NAND_DMA_ADDR   0x40
>> +
>> +/* NAND Command Register Bits */
>> +#define OP_DONE BIT(10)
>> +#define OP_SPAREBIT(9)
>> +#define OP_MAIN BIT(8)
>> +#define CMD_STATUS  BIT(7)
>> +#define CMD_RESET   BIT(6)
>> +#define CMD_READID  BIT(5)
>> +#define BLOCKS_ERASEBIT(4)
>> +#define CMD_ERASE   BIT(3)
>> +#define CMD_WRITE   BIT(2)
>> +#define CMD_READBIT(1)
>> +#define CMD_VALID   BIT(0)
>> +
>> +#define LS1X_NAND_TIMEOUT   20
>>

Re: [PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-05-28 Thread Kelvin Cheung

Hi Boris,
I have the same feeling as Mychaela, and suffered from the 'high-level
controllers' as well.
Looking forward to your review, thanks!

Best regards,

Keguang Zhang

On 05/28/2016 08:12 PM, Boris Brezillon wrote:
> Hi Kelvin,
>
> On Sat, 28 May 2016 17:54:10 +0800
> Keguang Zhang  wrote:
>
>> From: Kelvin Cheung 
>>
>> This patch adds NAND driver for Loongson1B.
> I think your controller matches Mychaela's "high-level NAND controller"
> definition [1]. Mychaela, can you confirm the Loongson controller
> looks like yours?
>
> I'll do a detailed review of the code soon.
>
> Thanks,
>
> Boris
>
> [1]http://thread.gmane.org/gmane.linux.drivers.mtd/67346
>
>> Signed-off-by: Kelvin Cheung 
>>
>> ---
>> v3:
>>Replace __raw_readl/__raw_writel with readl/writel.
>>Split ls1x_nand into two structures: ls1x_nand_chip and 
>> ls1x_nand_controller.
>> V2:
>>Modify the dependency in Kconfig due to the changes of DMA module.
>> ---
>>  drivers/mtd/nand/Kconfig  |   8 +
>>  drivers/mtd/nand/Makefile |   1 +
>>  drivers/mtd/nand/loongson1_nand.c | 555 
>> ++
>>  3 files changed, 564 insertions(+)
>>  create mode 100644 drivers/mtd/nand/loongson1_nand.c
>>
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index f05e0e9..be20fb8 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -563,4 +563,12 @@ config MTD_NAND_QCOM
>>Enables support for NAND flash chips on SoCs containing the EBI2 NAND
>>controller. This controller is found on IPQ806x SoC.
>>  
>> +config MTD_NAND_LOONGSON1
>> +tristate "Support for Loongson1 SoC NAND controller"
>> +depends on MACH_LOONGSON32
>> +select DMADEVICES
>> +select LOONGSON1_DMA
>> +help
>> +Enables support for NAND Flash on Loongson1 SoC based boards.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index f553353..0310c0b 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)   += sunxi_nand.o
>>  obj-$(CONFIG_MTD_NAND_HISI504)  += hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>> +obj-$(CONFIG_MTD_NAND_LOONGSON1)+= loongson1_nand.o
>>  
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o
>> diff --git a/drivers/mtd/nand/loongson1_nand.c 
>> b/drivers/mtd/nand/loongson1_nand.c
>> new file mode 100644
>> index 000..86831773
>> --- /dev/null
>> +++ b/drivers/mtd/nand/loongson1_nand.c
>> @@ -0,0 +1,555 @@
>> +/*
>> + * NAND Flash Driver for Loongson 1 SoC
>> + *
>> + * Copyright (C) 2015-2016 Zhang, Keguang 
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +
>> +/* Loongson 1 NAND Register Definitions */
>> +#define NAND_CMD0x0
>> +#define NAND_ADDRL  0x4
>> +#define NAND_ADDRH  0x8
>> +#define NAND_TIMING 0xc
>> +#define NAND_IDL0x10
>> +#define NAND_IDH0x14
>> +#define NAND_STATUS 0x14
>> +#define NAND_PARAM  0x18
>> +#define NAND_OP_NUM 0x1c
>> +#define NAND_CS_RDY 0x20
>> +
>> +#define NAND_DMA_ADDR   0x40
>> +
>> +/* NAND Command Register Bits */
>> +#define OP_DONE BIT(10)
>> +#define OP_SPAREBIT(9)
>> +#define OP_MAIN BIT(8)
>> +#define CMD_STATUS  BIT(7)
>> +#define CMD_RESET   BIT(6)
>> +#define CMD_READID  BIT(5)
>> +#define BLOCKS_ERASEBIT(4)
>> +#define CMD_ERASE   BIT(3)
>> +#define CMD_WRITE   BIT(2)
>> +#define CMD_READBIT(1)
>> +#define CMD_VALID   BIT(0)
>> +
>> +#define LS1X_NAND_TIMEOUT   20
>> +
>> +/* macros for registers read/write */
>> +#define nand_readl(nandc, off)  \
>>

[PATCH V3 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B

2014-10-17 Thread Kelvin Cheung

This patch adds cpufreq driver for Loongson1B which
is capable of changing the CPU frequency dynamically.

Signed-off-by: Kelvin Cheung 

---
V3:
   Remove superfluous devm_clk_put().
V2:
   Use devm_clk_get() instead of clk_get().
   Other minor fixes.
V1:
   Add cpufreq driver for Loongson1B.
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 223 +
 3 files changed, 234 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate "Loongson1 CPUFreq Driver"
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at .
+
+ If in doubt, say N.
+
 endmenu
 
 menu "PowerPC CPU frequency scaling drivers"
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..25fbd6a
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,223 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static struct {
+   struct device *dev;
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy->cur;
+   new_freq = policy->freq_table[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(ls1x_cpufreq.dev, "%u KHz --> %u KHz\n", old_freq, new_freq);
+   clk_set_parent(policy->clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) & ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy->clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i, ret;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1 << DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(ls1x_cpufreq.dev,
+   "failed to alloc cpufreq_frequency_table\n");
+   ret = -ENOMEM;
+   goto out;
+   }
+
+   for (i = 0; i < (steps - 1); i++) {
+   freq = pll_freq / (i + 1);
+   if ((freq < ls1x_cpufreq.min_freq) ||
+   (freq > ls1x_cpuf

[PATCH V2 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B

2014-10-17 Thread Kelvin Cheung

This patch adds cpufreq driver for Loongson1B which
is capable of changing the CPU frequency dynamically.

Signed-off-by: Kelvin Cheung 

---
V2:
   Use devm_clk_get() instead of clk_get().
   Other minor fixes.
V1:
   Add cpufreq driver for Loongson1B.
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 229 +
 3 files changed, 240 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate "Loongson1 CPUFreq Driver"
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at .
+
+ If in doubt, say N.
+
 endmenu
 
 menu "PowerPC CPU frequency scaling drivers"
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..1941c91
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,229 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static struct {
+   struct device *dev;
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy->cur;
+   new_freq = policy->freq_table[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(ls1x_cpufreq.dev, "%u KHz --> %u KHz\n", old_freq, new_freq);
+   clk_set_parent(policy->clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) & ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy->clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i, ret;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1 << DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(ls1x_cpufreq.dev,
+   "failed to alloc cpufreq_frequency_table\n");
+   ret = -ENOMEM;
+   goto out;
+   }
+
+   for (i = 0; i < (steps - 1); i++) {
+   freq = pll_freq / (i + 1);
+   if ((freq < ls1x_cpufreq.min_freq) ||
+   (freq > ls1x_cpufreq.max_freq))
+

[PATCH V2 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B

2014-10-17 Thread Kelvin Cheung

This patch adds cpufreq driver for Loongson1B which
is capable of changing the CPU frequency dynamically.

Signed-off-by: Kelvin Cheung 
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 229 +
 3 files changed, 240 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate "Loongson1 CPUFreq Driver"
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at .
+
+ If in doubt, say N.
+
 endmenu
 
 menu "PowerPC CPU frequency scaling drivers"
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..1941c91
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,229 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static struct {
+   struct device *dev;
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy->cur;
+   new_freq = policy->freq_table[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(ls1x_cpufreq.dev, "%u KHz --> %u KHz\n", old_freq, new_freq);
+   clk_set_parent(policy->clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) & ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy->clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i, ret;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1 << DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(ls1x_cpufreq.dev,
+   "failed to alloc cpufreq_frequency_table\n");
+   ret = -ENOMEM;
+   goto out;
+   }
+
+   for (i = 0; i < (steps - 1); i++) {
+   freq = pll_freq / (i + 1);
+   if ((freq < ls1x_cpufreq.min_freq) ||
+   (freq > ls1x_cpufreq.max_freq))
+   freq_tbl[i].frequency = CPUFREQ_ENTRY_INVALID;
+   else
+   freq_tbl[i].frequency = freq;
+

[PATCH V2 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B

2014-10-17 Thread Kelvin Cheung

This patch adds cpufreq driver for Loongson1B which
is capable of changing the CPU frequency dynamically.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 229 +
 3 files changed, 240 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate Loongson1 CPUFreq Driver
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at file:Documentation/cpu-freq/.
+
+ If in doubt, say N.
+
 endmenu
 
 menu PowerPC CPU frequency scaling drivers
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..1941c91
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,229 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/cpu.h
+#include linux/cpufreq.h
+#include linux/delay.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/slab.h
+
+#include asm/mach-loongson1/cpufreq.h
+#include asm/mach-loongson1/loongson1.h
+
+static struct {
+   struct device *dev;
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy-cur;
+   new_freq = policy-freq_table[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(ls1x_cpufreq.dev, %u KHz -- %u KHz\n, old_freq, new_freq);
+   clk_set_parent(policy-clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV)  ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy-clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i, ret;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1  DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(ls1x_cpufreq.dev,
+   failed to alloc cpufreq_frequency_table\n);
+   ret = -ENOMEM;
+   goto out;
+   }
+
+   for (i = 0; i  (steps - 1); i++) {
+   freq = pll_freq / (i + 1);
+   if ((freq  ls1x_cpufreq.min_freq) ||
+   (freq  ls1x_cpufreq.max_freq

[PATCH V2 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B

2014-10-17 Thread Kelvin Cheung

This patch adds cpufreq driver for Loongson1B which
is capable of changing the CPU frequency dynamically.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com

---
V2:
   Use devm_clk_get() instead of clk_get().
   Other minor fixes.
V1:
   Add cpufreq driver for Loongson1B.
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 229 +
 3 files changed, 240 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate Loongson1 CPUFreq Driver
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at file:Documentation/cpu-freq/.
+
+ If in doubt, say N.
+
 endmenu
 
 menu PowerPC CPU frequency scaling drivers
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..1941c91
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,229 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/cpu.h
+#include linux/cpufreq.h
+#include linux/delay.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/slab.h
+
+#include asm/mach-loongson1/cpufreq.h
+#include asm/mach-loongson1/loongson1.h
+
+static struct {
+   struct device *dev;
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy-cur;
+   new_freq = policy-freq_table[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(ls1x_cpufreq.dev, %u KHz -- %u KHz\n, old_freq, new_freq);
+   clk_set_parent(policy-clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV)  ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy-clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i, ret;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1  DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(ls1x_cpufreq.dev,
+   failed to alloc cpufreq_frequency_table\n);
+   ret = -ENOMEM;
+   goto out;
+   }
+
+   for (i = 0; i  (steps - 1); i++) {
+   freq = pll_freq / (i + 1

[PATCH V3 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B

2014-10-17 Thread Kelvin Cheung

This patch adds cpufreq driver for Loongson1B which
is capable of changing the CPU frequency dynamically.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com

---
V3:
   Remove superfluous devm_clk_put().
V2:
   Use devm_clk_get() instead of clk_get().
   Other minor fixes.
V1:
   Add cpufreq driver for Loongson1B.
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 223 +
 3 files changed, 234 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate Loongson1 CPUFreq Driver
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at file:Documentation/cpu-freq/.
+
+ If in doubt, say N.
+
 endmenu
 
 menu PowerPC CPU frequency scaling drivers
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..25fbd6a
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,223 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/cpu.h
+#include linux/cpufreq.h
+#include linux/delay.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/slab.h
+
+#include asm/mach-loongson1/cpufreq.h
+#include asm/mach-loongson1/loongson1.h
+
+static struct {
+   struct device *dev;
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy-cur;
+   new_freq = policy-freq_table[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(ls1x_cpufreq.dev, %u KHz -- %u KHz\n, old_freq, new_freq);
+   clk_set_parent(policy-clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV)  ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy-clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i, ret;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1  DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(ls1x_cpufreq.dev,
+   failed to alloc cpufreq_frequency_table\n);
+   ret = -ENOMEM;
+   goto out;
+   }
+
+   for (i = 0; i  (steps - 1); i

[PATCH 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B (UPDATED)

2014-10-15 Thread Kelvin Cheung

This patch adds cpufreq driver for Loongson1B which
is capable of changing the CPU frequency dynamically.

Signed-off-by: Kelvin Cheung 
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 233 +
 3 files changed, 244 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate "Loongson1 CPUFreq Driver"
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at .
+
+ If in doubt, say N.
+
 endmenu
 
 menu "PowerPC CPU frequency scaling drivers"
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..2655960
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,233 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static struct {
+   struct device *dev;
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy->cur;
+   new_freq = policy->freq_table[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(ls1x_cpufreq.dev, "%u KHz --> %u KHz\n", old_freq, new_freq);
+   clk_set_parent(policy->clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) & ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy->clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i, ret;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1 << DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(ls1x_cpufreq.dev,
+   "failed to alloc cpufreq_frequency_table\n");
+   ret = -ENOMEM;
+   goto out;
+   }
+
+   for (i = 0; i < (steps - 1); i++) {
+   freq = pll_freq / (i + 1);
+   if ((freq < ls1x_cpufreq.min_freq) ||
+   (freq > ls1x_cpufreq.max_freq))
+   freq_tbl[i].frequency = CPUFREQ_ENTRY_INVALID;
+   else
+   freq_tbl[i].frequency = freq;
+

[PATCH 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B (UPDATED)

2014-10-15 Thread Kelvin Cheung

This patch adds cpufreq driver for Loongson1B which
is capable of changing the CPU frequency dynamically.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 233 +
 3 files changed, 244 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate Loongson1 CPUFreq Driver
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at file:Documentation/cpu-freq/.
+
+ If in doubt, say N.
+
 endmenu
 
 menu PowerPC CPU frequency scaling drivers
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..2655960
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,233 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/cpu.h
+#include linux/cpufreq.h
+#include linux/delay.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/slab.h
+
+#include asm/mach-loongson1/cpufreq.h
+#include asm/mach-loongson1/loongson1.h
+
+static struct {
+   struct device *dev;
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy-cur;
+   new_freq = policy-freq_table[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(ls1x_cpufreq.dev, %u KHz -- %u KHz\n, old_freq, new_freq);
+   clk_set_parent(policy-clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV)  ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy-clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i, ret;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1  DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(ls1x_cpufreq.dev,
+   failed to alloc cpufreq_frequency_table\n);
+   ret = -ENOMEM;
+   goto out;
+   }
+
+   for (i = 0; i  (steps - 1); i++) {
+   freq = pll_freq / (i + 1);
+   if ((freq  ls1x_cpufreq.min_freq) ||
+   (freq  ls1x_cpufreq.max_freq

[PATCH 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B

2014-10-09 Thread Kelvin Cheung

Signed-off-by: Kelvin Cheung 
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 217 +
 3 files changed, 228 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate "Loongson1 CPUFreq Driver"
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at .
+
+ If in doubt, say N.
+
 endmenu
 
 menu "PowerPC CPU frequency scaling drivers"
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..3d9a410
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,217 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static struct {
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+   struct cpufreq_frequency_table *freq_tbl;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   struct device *dev = get_cpu_device(policy->cpu);
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy->cur;
+   new_freq = ls1x_cpufreq.freq_tbl[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(dev, "%u KHz --> %u KHz\n", old_freq, new_freq);
+   clk_set_parent(policy->clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) & ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy->clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct device *dev = get_cpu_device(policy->cpu);
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1 << DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(dev, "failed to alloc cpufreq_frequency_table\n");
+   return -ENOMEM;
+   }
+
+   for (i = 0; i < (steps - 1); i++) {
+   freq = pll_freq / (i + 1);
+   if ((freq < ls1x_cpufreq.min_freq) ||
+   (freq > ls1x_cpufreq.max_freq))
+   freq_tbl[i].frequency = CPUFREQ_ENTRY_INVALID;
+   else
+   freq_tbl[i].frequency = freq;
+   dev_dbg(dev, &quo

[PATCH 5/6] clk: ls1x: Update relationship among all clocks

2014-10-09 Thread Kelvin Cheung

 - Add clock lookups for APB devices.
 - Update clock relationship to make it more exact and clear.
 _
 ___| |
 OSC ___/   | MUX |___ XXX CLK
\___ PLL ___ XXX DIV ___| |
|_|

Signed-off-by: Kelvin Cheung 
---
 drivers/clk/clk-ls1x.c | 109 -
 1 file changed, 80 insertions(+), 29 deletions(-)

diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
index f20b750..ca80103 100644
--- a/drivers/clk/clk-ls1x.c
+++ b/drivers/clk/clk-ls1x.c
@@ -15,7 +15,8 @@
 
 #include 
 
-#define OSC33
+#define OSC(33 * 100)
+#define DIV_APB2
 
 static DEFINE_SPINLOCK(_lock);
 
@@ -29,13 +30,12 @@ static void ls1x_pll_clk_disable(struct clk_hw *hw)
 }
 
 static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
-unsigned long parent_rate)
+ unsigned long parent_rate)
 {
u32 pll, rate;
 
pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-   rate = ((12 + (pll & 0x3f)) * 100) +
-   pll >> 8) & 0x3ff) * 100) >> 10);
+   rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10);
rate *= OSC;
rate >>= 1;
 
@@ -48,8 +48,10 @@ static const struct clk_ops ls1x_pll_clk_ops = {
.recalc_rate = ls1x_pll_recalc_rate,
 };
 
-static struct clk * __init clk_register_pll(struct device *dev,
-const char *name, const char *parent_name, unsigned long flags)
+static struct clk *__init clk_register_pll(struct device *dev,
+  const char *name,
+  const char *parent_name,
+  unsigned long flags)
 {
struct clk_hw *hw;
struct clk *clk;
@@ -78,34 +80,83 @@ static struct clk * __init clk_register_pll(struct device 
*dev,
return clk;
 }
 
+static const char const *cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };
+static const char const *ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", };
+static const char const *dc_parents[] = { "dc_clk_div", "osc_33m_clk", };
+
 void __init ls1x_clk_init(void)
 {
struct clk *clk;
 
-   clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
-   clk_prepare_enable(clk);
-
-   clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
-   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
-   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
-   clk_prepare_enable(clk);
-   clk_register_clkdev(clk, "cpu", NULL);
-
-   clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
-   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
-   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
-   clk_prepare_enable(clk);
-   clk_register_clkdev(clk, "dc", NULL);
-
-   clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
-   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
-   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
-   clk_prepare_enable(clk);
-   clk_register_clkdev(clk, "ahb", NULL);
+   clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, CLK_IS_ROOT,
+ OSC);
+   clk_register_clkdev(clk, "osc_33m_clk", NULL);
+
+   /* clock derived from 33 MHz OSC clk */
+   clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);
+   clk_register_clkdev(clk, "pll_clk", NULL);
+
+   /* clock derived from PLL clk */
+   /* _
+* ___| |
+* OSC ___/   | MUX |___ CPU CLK
+*\___ PLL ___ CPU DIV ___| |
+*|_|
+*/
+   clk = clk_register_divider(NULL, "cpu_clk_div", "pll_clk",
+  CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
+  DIV_CPU_SHIFT, DIV_CPU_WIDTH,
+  CLK_DIVIDER_ONE_BASED |
+  CLK_DIVIDER_ROUND_CLOSEST, &_lock);
+   clk_register_clkdev(clk, "cpu_clk_div", NULL);
+   clk = clk_register_mux(NULL, "cpu_clk", cpu_parents,
+  ARRAY_SIZE(cpu_parents),
+  CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
+  BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
+   clk_register_clkdev(clk, "cpu_clk&q

[PATCH 5/6] clk: ls1x: Update relationship among all clocks

2014-10-09 Thread Kelvin Cheung

 - Add clock lookups for APB devices.
 - Update clock relationship to make it more exact and clear.
 _
 ___| |
 OSC ___/   | MUX |___ XXX CLK
\___ PLL ___ XXX DIV ___| |
|_|

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 drivers/clk/clk-ls1x.c | 109 -
 1 file changed, 80 insertions(+), 29 deletions(-)

diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
index f20b750..ca80103 100644
--- a/drivers/clk/clk-ls1x.c
+++ b/drivers/clk/clk-ls1x.c
@@ -15,7 +15,8 @@
 
 #include loongson1.h
 
-#define OSC33
+#define OSC(33 * 100)
+#define DIV_APB2
 
 static DEFINE_SPINLOCK(_lock);
 
@@ -29,13 +30,12 @@ static void ls1x_pll_clk_disable(struct clk_hw *hw)
 }
 
 static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
-unsigned long parent_rate)
+ unsigned long parent_rate)
 {
u32 pll, rate;
 
pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-   rate = ((12 + (pll  0x3f)) * 100) +
-   pll  8)  0x3ff) * 100)  10);
+   rate = 12 + (pll  0x3f) + (((pll  8)  0x3ff)  10);
rate *= OSC;
rate = 1;
 
@@ -48,8 +48,10 @@ static const struct clk_ops ls1x_pll_clk_ops = {
.recalc_rate = ls1x_pll_recalc_rate,
 };
 
-static struct clk * __init clk_register_pll(struct device *dev,
-const char *name, const char *parent_name, unsigned long flags)
+static struct clk *__init clk_register_pll(struct device *dev,
+  const char *name,
+  const char *parent_name,
+  unsigned long flags)
 {
struct clk_hw *hw;
struct clk *clk;
@@ -78,34 +80,83 @@ static struct clk * __init clk_register_pll(struct device 
*dev,
return clk;
 }
 
+static const char const *cpu_parents[] = { cpu_clk_div, osc_33m_clk, };
+static const char const *ahb_parents[] = { ahb_clk_div, osc_33m_clk, };
+static const char const *dc_parents[] = { dc_clk_div, osc_33m_clk, };
+
 void __init ls1x_clk_init(void)
 {
struct clk *clk;
 
-   clk = clk_register_pll(NULL, pll_clk, NULL, CLK_IS_ROOT);
-   clk_prepare_enable(clk);
-
-   clk = clk_register_divider(NULL, cpu_clk, pll_clk,
-   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
-   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
-   clk_prepare_enable(clk);
-   clk_register_clkdev(clk, cpu, NULL);
-
-   clk = clk_register_divider(NULL, dc_clk, pll_clk,
-   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
-   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
-   clk_prepare_enable(clk);
-   clk_register_clkdev(clk, dc, NULL);
-
-   clk = clk_register_divider(NULL, ahb_clk, pll_clk,
-   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
-   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
-   clk_prepare_enable(clk);
-   clk_register_clkdev(clk, ahb, NULL);
+   clk = clk_register_fixed_rate(NULL, osc_33m_clk, NULL, CLK_IS_ROOT,
+ OSC);
+   clk_register_clkdev(clk, osc_33m_clk, NULL);
+
+   /* clock derived from 33 MHz OSC clk */
+   clk = clk_register_pll(NULL, pll_clk, osc_33m_clk, 0);
+   clk_register_clkdev(clk, pll_clk, NULL);
+
+   /* clock derived from PLL clk */
+   /* _
+* ___| |
+* OSC ___/   | MUX |___ CPU CLK
+*\___ PLL ___ CPU DIV ___| |
+*|_|
+*/
+   clk = clk_register_divider(NULL, cpu_clk_div, pll_clk,
+  CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
+  DIV_CPU_SHIFT, DIV_CPU_WIDTH,
+  CLK_DIVIDER_ONE_BASED |
+  CLK_DIVIDER_ROUND_CLOSEST, _lock);
+   clk_register_clkdev(clk, cpu_clk_div, NULL);
+   clk = clk_register_mux(NULL, cpu_clk, cpu_parents,
+  ARRAY_SIZE(cpu_parents),
+  CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
+  BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, _lock);
+   clk_register_clkdev(clk, cpu_clk, NULL);
+
+   /* _
+* ___| |
+* OSC ___/   | MUX |___ DC  CLK
+*\___ PLL ___ DC  DIV ___| |
+*|_|
+*/
+   clk = clk_register_divider(NULL, dc_clk_div, pll_clk

[PATCH 6/6] cpufreq: Loongson1: Add cpufreq driver for Loongson1B

2014-10-09 Thread Kelvin Cheung

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 drivers/cpufreq/Kconfig|  10 ++
 drivers/cpufreq/Makefile   |   1 +
 drivers/cpufreq/ls1x-cpufreq.c | 217 +
 3 files changed, 228 insertions(+)
 create mode 100644 drivers/cpufreq/ls1x-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index ffe350f..99464d7 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -250,6 +250,16 @@ config LOONGSON2_CPUFREQ
 
  If in doubt, say N.
 
+config LOONGSON1_CPUFREQ
+   tristate Loongson1 CPUFreq Driver
+   help
+ This option adds a CPUFreq driver for loongson1 processors which
+ support software configurable cpu frequency.
+
+ For details, take a look at file:Documentation/cpu-freq/.
+
+ If in doubt, say N.
+
 endmenu
 
 menu PowerPC CPU frequency scaling drivers
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..aca7bd3 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_CRIS_MACH_ARTPEC3)   += 
cris-artpec3-cpufreq.o
 obj-$(CONFIG_ETRAXFS)  += cris-etraxfs-cpufreq.o
 obj-$(CONFIG_IA64_ACPI_CPUFREQ)+= ia64-acpi-cpufreq.o
 obj-$(CONFIG_LOONGSON2_CPUFREQ)+= loongson2_cpufreq.o
+obj-$(CONFIG_LOONGSON1_CPUFREQ)+= ls1x-cpufreq.o
 obj-$(CONFIG_SH_CPU_FREQ)  += sh-cpufreq.o
 obj-$(CONFIG_SPARC_US2E_CPUFREQ)   += sparc-us2e-cpufreq.o
 obj-$(CONFIG_SPARC_US3_CPUFREQ)+= sparc-us3-cpufreq.o
diff --git a/drivers/cpufreq/ls1x-cpufreq.c b/drivers/cpufreq/ls1x-cpufreq.c
new file mode 100644
index 000..3d9a410
--- /dev/null
+++ b/drivers/cpufreq/ls1x-cpufreq.c
@@ -0,0 +1,217 @@
+/*
+ * CPU Frequency Scaling for Loongson 1 SoC
+ *
+ * Copyright (C) 2014 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/cpu.h
+#include linux/cpufreq.h
+#include linux/delay.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/slab.h
+
+#include cpufreq.h
+#include loongson1.h
+
+static struct {
+   struct clk *clk;/* CPU clk */
+   struct clk *mux_clk;/* MUX of CPU clk */
+   struct clk *pll_clk;/* PLL clk */
+   struct clk *osc_clk;/* OSC clk */
+   unsigned int max_freq;
+   unsigned int min_freq;
+   struct cpufreq_frequency_table *freq_tbl;
+} ls1x_cpufreq;
+
+static int ls1x_cpufreq_notifier(struct notifier_block *nb,
+unsigned long val, void *data)
+{
+   if (val == CPUFREQ_POSTCHANGE)
+   current_cpu_data.udelay_val = loops_per_jiffy;
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block ls1x_cpufreq_notifier_block = {
+   .notifier_call = ls1x_cpufreq_notifier
+};
+
+static int ls1x_cpufreq_target(struct cpufreq_policy *policy,
+  unsigned int index)
+{
+   struct device *dev = get_cpu_device(policy-cpu);
+   unsigned int old_freq, new_freq;
+
+   old_freq = policy-cur;
+   new_freq = ls1x_cpufreq.freq_tbl[index].frequency;
+
+   /*
+* The procedure of reconfiguring CPU clk is as below.
+*
+*  - Reparent CPU clk to OSC clk
+*  - Reset CPU clock (very important)
+*  - Reconfigure CPU DIV
+*  - Reparent CPU clk back to CPU DIV clk
+*/
+
+   dev_dbg(dev, %u KHz -- %u KHz\n, old_freq, new_freq);
+   clk_set_parent(policy-clk, ls1x_cpufreq.osc_clk);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU,
+LS1X_CLK_PLL_DIV);
+   __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV)  ~(RST_CPU_EN | RST_CPU),
+LS1X_CLK_PLL_DIV);
+   clk_set_rate(ls1x_cpufreq.mux_clk, new_freq * 1000);
+   clk_set_parent(policy-clk, ls1x_cpufreq.mux_clk);
+
+   return 0;
+}
+
+static int ls1x_cpufreq_init(struct cpufreq_policy *policy)
+{
+   struct device *dev = get_cpu_device(policy-cpu);
+   struct cpufreq_frequency_table *freq_tbl;
+   unsigned int pll_freq, freq;
+   int steps, i;
+
+   pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000;
+
+   steps = 1  DIV_CPU_WIDTH;
+   freq_tbl = kzalloc(sizeof(*freq_tbl) * steps, GFP_KERNEL);
+   if (!freq_tbl) {
+   dev_err(dev, failed to alloc cpufreq_frequency_table\n);
+   return -ENOMEM;
+   }
+
+   for (i = 0; i  (steps - 1); i++) {
+   freq = pll_freq / (i + 1);
+   if ((freq  ls1x_cpufreq.min_freq) ||
+   (freq  ls1x_cpufreq.max_freq))
+   freq_tbl[i].frequency = CPUFREQ_ENTRY_INVALID;
+   else

[PATCH 4/4] MIPS: Loongson1B: Fix a typo

2012-10-23 Thread Kelvin Cheung

Fix a typo in the code.

Signed-off-by: Kelvin Cheung 
---
 arch/mips/loongson1/common/clock.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/loongson1/common/clock.c 
b/arch/mips/loongson1/common/clock.c
index 7db0a6a..07133de 100644
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -22,7 +22,7 @@ void __init plat_time_init(void)
/* setup mips r4k timer */
clk = clk_get(NULL, "cpu");
if (IS_ERR(clk))
-   panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
+   panic("unable to get cpu clock, err=%ld", PTR_ERR(clk));
 
mips_hpt_frequency = clk_get_rate(clk) / 2;
 }
-- 
1.7.1

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[PATCH 3/4] MIPS: Loongson1B: Update stmmac_mdio_bus_data

2012-10-23 Thread Kelvin Cheung

Update stmmac_mdio_bus_data accordingly due to the upstream change.

Signed-off-by: Kelvin Cheung 
---
 arch/mips/loongson1/common/platform.c |1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/mips/loongson1/common/platform.c 
b/arch/mips/loongson1/common/platform.c
index 5ca38dc..3a42276 100644
--- a/arch/mips/loongson1/common/platform.c
+++ b/arch/mips/loongson1/common/platform.c
@@ -71,7 +71,6 @@ static struct resource ls1x_eth0_resources[] = {
 };
 
 static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
-   .bus_id = 0,
.phy_mask   = 0,
 };
 
-- 
1.7.1

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[PATCH 2/4] MIPS: Loongson1B: improve ls1x_serial_setup()

2012-10-23 Thread Kelvin Cheung

Improve ls1x_serial_setup().

Signed-off-by: Kelvin Cheung 
---
 arch/mips/include/asm/mach-loongson1/platform.h |2 +-
 arch/mips/loongson1/common/platform.c   |9 +
 arch/mips/loongson1/ls1b/board.c|5 +
 3 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson1/platform.h 
b/arch/mips/include/asm/mach-loongson1/platform.h
index f584017..718a122 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -19,6 +19,6 @@ extern struct platform_device ls1x_ehci_device;
 extern struct platform_device ls1x_rtc_device;
 
 extern void __init ls1x_clk_init(void);
-void ls1x_serial_setup(void);
+extern void __init ls1x_serial_setup(struct platform_device *pdev);
 
 #endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/loongson1/common/platform.c 
b/arch/mips/loongson1/common/platform.c
index e92d59c..5ca38dc 100644
--- a/arch/mips/loongson1/common/platform.c
+++ b/arch/mips/loongson1/common/platform.c
@@ -42,16 +42,17 @@ struct platform_device ls1x_uart_device = {
},
 };
 
-void __init ls1x_serial_setup(void)
+void __init ls1x_serial_setup(struct platform_device *pdev)
 {
struct clk *clk;
struct plat_serial8250_port *p;
 
-   clk = clk_get(NULL, "dc");
+   clk = clk_get(NULL, pdev->name);
if (IS_ERR(clk))
-   panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
+   panic("unable to get %s clock, err=%ld",
+   pdev->name, PTR_ERR(clk));
 
-   for (p = ls1x_serial8250_port; p->flags != 0; ++p)
+   for (p = pdev->dev.platform_data; p->flags != 0; ++p)
p->uartclk = clk_get_rate(clk);
 }
 
diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c
index 295b1be..1fbd526 100644
--- a/arch/mips/loongson1/ls1b/board.c
+++ b/arch/mips/loongson1/ls1b/board.c
@@ -9,9 +9,6 @@
 
 #include 
 
-#include 
-#include 
-
 static struct platform_device *ls1b_platform_devices[] __initdata = {
_uart_device,
_eth0_device,
@@ -23,7 +20,7 @@ static int __init ls1b_platform_init(void)
 {
int err;
 
-   ls1x_serial_setup();
+   ls1x_serial_setup(_uart_device);
 
err = platform_add_devices(ls1b_platform_devices,
   ARRAY_SIZE(ls1b_platform_devices));
-- 
1.7.1

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[PATCH 1/4] MIPS: Loongson1B: use common clock infrastructure instead of private APIs

2012-10-23 Thread Kelvin Cheung

Use common clock infrastructure instead of private APIs.
1. Enable COMMON_CLK in the Kconfig.
2. Remove private clock APIs, which are replaced by the code in
   drivers/clk/clk-ls1x.c.
3. Modify header file for drivers/clk/clk-ls1x.c.

Signed-off-by: Kelvin Cheung 
---
 arch/mips/include/asm/mach-loongson1/platform.h |1 +
 arch/mips/include/asm/mach-loongson1/regs-clk.h |7 +-
 arch/mips/loongson1/Kconfig |2 +-
 arch/mips/loongson1/common/clock.c  |  157 +--
 4 files changed, 8 insertions(+), 159 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson1/platform.h 
b/arch/mips/include/asm/mach-loongson1/platform.h
index 2f17161..f584017 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -18,6 +18,7 @@ extern struct platform_device ls1x_eth0_device;
 extern struct platform_device ls1x_ehci_device;
 extern struct platform_device ls1x_rtc_device;
 
+extern void __init ls1x_clk_init(void);
 void ls1x_serial_setup(void);
 
 #endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h 
b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index 8efa7fb..a81fa3d 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,14 +20,15 @@
 
 /* Clock PLL Divisor Register Bits */
 #define DIV_DC_EN  (0x1 << 31)
-#define DIV_DC (0x1f << 26)
 #define DIV_CPU_EN (0x1 << 25)
-#define DIV_CPU(0x1f << 20)
 #define DIV_DDR_EN (0x1 << 19)
-#define DIV_DDR(0x1f << 14)
 
 #define DIV_DC_SHIFT   26
 #define DIV_CPU_SHIFT  20
 #define DIV_DDR_SHIFT  14
 
+#define DIV_DC_WIDTH   5
+#define DIV_CPU_WIDTH  5
+#define DIV_DDR_WIDTH  5
+
 #endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
index a9a14d6..fbf75f6 100644
--- a/arch/mips/loongson1/Kconfig
+++ b/arch/mips/loongson1/Kconfig
@@ -15,7 +15,7 @@ config LOONGSON1_LS1B
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
-   select HAVE_CLK
+   select COMMON_CLK
 
 endchoice
 
diff --git a/arch/mips/loongson1/common/clock.c 
b/arch/mips/loongson1/common/clock.c
index 1ec..7db0a6a 100644
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -7,170 +7,17 @@
  * option) any later version.
  */
 
-#include 
-#include 
-#include 
 #include 
 #include 
-#include 
 #include 
-
-#include 
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-struct clk *clk_get(struct device *dev, const char *name)
-{
-   struct clk *c;
-   struct clk *ret = NULL;
-
-   mutex_lock(_mutex);
-   list_for_each_entry(c, , node) {
-   if (!strcmp(c->name, name)) {
-   ret = c;
-   break;
-   }
-   }
-   mutex_unlock(_mutex);
-
-   return ret;
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
-   return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-   return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-static void pll_clk_init(struct clk *clk)
-{
-   u32 pll;
-
-   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-   clk->rate = (12 + (pll & 0x3f)) * 33 / 2
-   + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2;
-   clk->rate *= 100;
-}
-
-static void cpu_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk->parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU;
-   clk->rate = pll / (ctrl >> DIV_CPU_SHIFT);
-}
-
-static void ddr_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk->parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR;
-   clk->rate = pll / (ctrl >> DIV_DDR_SHIFT);
-}
-
-static void dc_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk->parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC;
-   clk->rate = pll / (ctrl >> DIV_DC_SHIFT);
-}
-
-static struct clk_ops pll_clk_ops = {
-   .init   = pll_clk_init,
-};
-
-static struct clk_ops cpu_clk_ops = {
-   .init   = cpu_clk_init,
-};
-
-static struct clk_ops ddr_clk_ops = {
-   .init   = ddr_clk_init,
-};
-
-static struct clk_ops dc_clk_ops = {
-   .init   = dc_clk_init,
-};
-
-static struct clk pll_clk = {
-   .name   = &q

[PATCH 0/4] MIPS: Loongson1B: enable common clock infrastructure

2012-10-23 Thread Kelvin Cheung

These patches enable common clock infrastructure of Loongson1, and
include other minor fixes.

Kelvin Cheung (4):
  MIPS: Loongson1B: use common clock infrastructure instead of
private APIs
  MIPS: Loongson1B: improve ls1x_serial_setup()
  MIPS: Loongson1B: Update stmmac_mdio_bus_data
  MIPS: Loongson1B: Fix a typo

 arch/mips/include/asm/mach-loongson1/platform.h |3 +-
 arch/mips/include/asm/mach-loongson1/regs-clk.h |7 +-
 arch/mips/loongson1/Kconfig |2 +-
 arch/mips/loongson1/common/clock.c  |  159 +--
 arch/mips/loongson1/common/platform.c   |   10 +-
 arch/mips/loongson1/ls1b/board.c|5 +-
 6 files changed, 16 insertions(+), 170 deletions(-)

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 0/4] MIPS: Loongson1B: enable common clock infrastructure

2012-10-23 Thread Kelvin Cheung

These patches enable common clock infrastructure of Loongson1, and
include other minor fixes.

Kelvin Cheung (4):
  MIPS: Loongson1B: use common clock infrastructure instead of
private APIs
  MIPS: Loongson1B: improve ls1x_serial_setup()
  MIPS: Loongson1B: Update stmmac_mdio_bus_data
  MIPS: Loongson1B: Fix a typo

 arch/mips/include/asm/mach-loongson1/platform.h |3 +-
 arch/mips/include/asm/mach-loongson1/regs-clk.h |7 +-
 arch/mips/loongson1/Kconfig |2 +-
 arch/mips/loongson1/common/clock.c  |  159 +--
 arch/mips/loongson1/common/platform.c   |   10 +-
 arch/mips/loongson1/ls1b/board.c|5 +-
 6 files changed, 16 insertions(+), 170 deletions(-)

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[PATCH 1/4] MIPS: Loongson1B: use common clock infrastructure instead of private APIs

2012-10-23 Thread Kelvin Cheung

Use common clock infrastructure instead of private APIs.
1. Enable COMMON_CLK in the Kconfig.
2. Remove private clock APIs, which are replaced by the code in
   drivers/clk/clk-ls1x.c.
3. Modify header file for drivers/clk/clk-ls1x.c.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 arch/mips/include/asm/mach-loongson1/platform.h |1 +
 arch/mips/include/asm/mach-loongson1/regs-clk.h |7 +-
 arch/mips/loongson1/Kconfig |2 +-
 arch/mips/loongson1/common/clock.c  |  157 +--
 4 files changed, 8 insertions(+), 159 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson1/platform.h 
b/arch/mips/include/asm/mach-loongson1/platform.h
index 2f17161..f584017 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -18,6 +18,7 @@ extern struct platform_device ls1x_eth0_device;
 extern struct platform_device ls1x_ehci_device;
 extern struct platform_device ls1x_rtc_device;
 
+extern void __init ls1x_clk_init(void);
 void ls1x_serial_setup(void);
 
 #endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h 
b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index 8efa7fb..a81fa3d 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,14 +20,15 @@
 
 /* Clock PLL Divisor Register Bits */
 #define DIV_DC_EN  (0x1  31)
-#define DIV_DC (0x1f  26)
 #define DIV_CPU_EN (0x1  25)
-#define DIV_CPU(0x1f  20)
 #define DIV_DDR_EN (0x1  19)
-#define DIV_DDR(0x1f  14)
 
 #define DIV_DC_SHIFT   26
 #define DIV_CPU_SHIFT  20
 #define DIV_DDR_SHIFT  14
 
+#define DIV_DC_WIDTH   5
+#define DIV_CPU_WIDTH  5
+#define DIV_DDR_WIDTH  5
+
 #endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
index a9a14d6..fbf75f6 100644
--- a/arch/mips/loongson1/Kconfig
+++ b/arch/mips/loongson1/Kconfig
@@ -15,7 +15,7 @@ config LOONGSON1_LS1B
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
-   select HAVE_CLK
+   select COMMON_CLK
 
 endchoice
 
diff --git a/arch/mips/loongson1/common/clock.c 
b/arch/mips/loongson1/common/clock.c
index 1ec..7db0a6a 100644
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -7,170 +7,17 @@
  * option) any later version.
  */
 
-#include linux/module.h
-#include linux/list.h
-#include linux/mutex.h
 #include linux/clk.h
 #include linux/err.h
-#include asm/clock.h
 #include asm/time.h
-
-#include loongson1.h
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-struct clk *clk_get(struct device *dev, const char *name)
-{
-   struct clk *c;
-   struct clk *ret = NULL;
-
-   mutex_lock(clocks_mutex);
-   list_for_each_entry(c, clocks, node) {
-   if (!strcmp(c-name, name)) {
-   ret = c;
-   break;
-   }
-   }
-   mutex_unlock(clocks_mutex);
-
-   return ret;
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
-   return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-   return clk-rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-static void pll_clk_init(struct clk *clk)
-{
-   u32 pll;
-
-   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-   clk-rate = (12 + (pll  0x3f)) * 33 / 2
-   + ((pll  8)  0x3ff) * 33 / 1024 / 2;
-   clk-rate *= 100;
-}
-
-static void cpu_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk-parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV)  DIV_CPU;
-   clk-rate = pll / (ctrl  DIV_CPU_SHIFT);
-}
-
-static void ddr_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk-parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV)  DIV_DDR;
-   clk-rate = pll / (ctrl  DIV_DDR_SHIFT);
-}
-
-static void dc_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk-parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV)  DIV_DC;
-   clk-rate = pll / (ctrl  DIV_DC_SHIFT);
-}
-
-static struct clk_ops pll_clk_ops = {
-   .init   = pll_clk_init,
-};
-
-static struct clk_ops cpu_clk_ops = {
-   .init   = cpu_clk_init,
-};
-
-static struct clk_ops ddr_clk_ops = {
-   .init   = ddr_clk_init,
-};
-
-static struct clk_ops dc_clk_ops = {
-   .init   = dc_clk_init,
-};
-
-static struct clk pll_clk = {
-   .name   = pll

[PATCH 2/4] MIPS: Loongson1B: improve ls1x_serial_setup()

2012-10-23 Thread Kelvin Cheung

Improve ls1x_serial_setup().

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 arch/mips/include/asm/mach-loongson1/platform.h |2 +-
 arch/mips/loongson1/common/platform.c   |9 +
 arch/mips/loongson1/ls1b/board.c|5 +
 3 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson1/platform.h 
b/arch/mips/include/asm/mach-loongson1/platform.h
index f584017..718a122 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -19,6 +19,6 @@ extern struct platform_device ls1x_ehci_device;
 extern struct platform_device ls1x_rtc_device;
 
 extern void __init ls1x_clk_init(void);
-void ls1x_serial_setup(void);
+extern void __init ls1x_serial_setup(struct platform_device *pdev);
 
 #endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/loongson1/common/platform.c 
b/arch/mips/loongson1/common/platform.c
index e92d59c..5ca38dc 100644
--- a/arch/mips/loongson1/common/platform.c
+++ b/arch/mips/loongson1/common/platform.c
@@ -42,16 +42,17 @@ struct platform_device ls1x_uart_device = {
},
 };
 
-void __init ls1x_serial_setup(void)
+void __init ls1x_serial_setup(struct platform_device *pdev)
 {
struct clk *clk;
struct plat_serial8250_port *p;
 
-   clk = clk_get(NULL, dc);
+   clk = clk_get(NULL, pdev-name);
if (IS_ERR(clk))
-   panic(unable to get dc clock, err=%ld, PTR_ERR(clk));
+   panic(unable to get %s clock, err=%ld,
+   pdev-name, PTR_ERR(clk));
 
-   for (p = ls1x_serial8250_port; p-flags != 0; ++p)
+   for (p = pdev-dev.platform_data; p-flags != 0; ++p)
p-uartclk = clk_get_rate(clk);
 }
 
diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c
index 295b1be..1fbd526 100644
--- a/arch/mips/loongson1/ls1b/board.c
+++ b/arch/mips/loongson1/ls1b/board.c
@@ -9,9 +9,6 @@
 
 #include platform.h
 
-#include linux/serial_8250.h
-#include loongson1.h
-
 static struct platform_device *ls1b_platform_devices[] __initdata = {
ls1x_uart_device,
ls1x_eth0_device,
@@ -23,7 +20,7 @@ static int __init ls1b_platform_init(void)
 {
int err;
 
-   ls1x_serial_setup();
+   ls1x_serial_setup(ls1x_uart_device);
 
err = platform_add_devices(ls1b_platform_devices,
   ARRAY_SIZE(ls1b_platform_devices));
-- 
1.7.1

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[PATCH 3/4] MIPS: Loongson1B: Update stmmac_mdio_bus_data

2012-10-23 Thread Kelvin Cheung

Update stmmac_mdio_bus_data accordingly due to the upstream change.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 arch/mips/loongson1/common/platform.c |1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/mips/loongson1/common/platform.c 
b/arch/mips/loongson1/common/platform.c
index 5ca38dc..3a42276 100644
--- a/arch/mips/loongson1/common/platform.c
+++ b/arch/mips/loongson1/common/platform.c
@@ -71,7 +71,6 @@ static struct resource ls1x_eth0_resources[] = {
 };
 
 static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
-   .bus_id = 0,
.phy_mask   = 0,
 };
 
-- 
1.7.1

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[PATCH 4/4] MIPS: Loongson1B: Fix a typo

2012-10-23 Thread Kelvin Cheung

Fix a typo in the code.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 arch/mips/loongson1/common/clock.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/loongson1/common/clock.c 
b/arch/mips/loongson1/common/clock.c
index 7db0a6a..07133de 100644
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -22,7 +22,7 @@ void __init plat_time_init(void)
/* setup mips r4k timer */
clk = clk_get(NULL, cpu);
if (IS_ERR(clk))
-   panic(unable to get dc clock, err=%ld, PTR_ERR(clk));
+   panic(unable to get cpu clock, err=%ld, PTR_ERR(clk));
 
mips_hpt_frequency = clk_get_rate(clk) / 2;
 }
-- 
1.7.1

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[PATCH resend] MIPS: Loongson1B: use common clock infrastructure instead of private APIs.

2012-09-27 Thread Kelvin Cheung

1. Remove private clock APIs, which are replaced by the code in
   drivers/clk/clk-ls1x.c
2. Enable COMMON_CLK in the Kconfig.
3. some minor modifications.

Signed-off-by: Kelvin Cheung 
---
 arch/mips/include/asm/mach-loongson1/platform.h |3 +-
 arch/mips/include/asm/mach-loongson1/regs-clk.h |7 +-
 arch/mips/loongson1/Kconfig |2 +-
 arch/mips/loongson1/common/clock.c  |  159 +--
 arch/mips/loongson1/common/platform.c   |9 +-
 arch/mips/loongson1/ls1b/board.c|5 +-
 6 files changed, 16 insertions(+), 169 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson1/platform.h 
b/arch/mips/include/asm/mach-loongson1/platform.h
index 2f17161..718a122 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -18,6 +18,7 @@ extern struct platform_device ls1x_eth0_device;
 extern struct platform_device ls1x_ehci_device;
 extern struct platform_device ls1x_rtc_device;
 
-void ls1x_serial_setup(void);
+extern void __init ls1x_clk_init(void);
+extern void __init ls1x_serial_setup(struct platform_device *pdev);
 
 #endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h 
b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index 8efa7fb..a81fa3d 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,14 +20,15 @@
 
 /* Clock PLL Divisor Register Bits */
 #define DIV_DC_EN  (0x1 << 31)
-#define DIV_DC (0x1f << 26)
 #define DIV_CPU_EN (0x1 << 25)
-#define DIV_CPU(0x1f << 20)
 #define DIV_DDR_EN (0x1 << 19)
-#define DIV_DDR(0x1f << 14)
 
 #define DIV_DC_SHIFT   26
 #define DIV_CPU_SHIFT  20
 #define DIV_DDR_SHIFT  14
 
+#define DIV_DC_WIDTH   5
+#define DIV_CPU_WIDTH  5
+#define DIV_DDR_WIDTH  5
+
 #endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
index a9a14d6..fbf75f6 100644
--- a/arch/mips/loongson1/Kconfig
+++ b/arch/mips/loongson1/Kconfig
@@ -15,7 +15,7 @@ config LOONGSON1_LS1B
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
-   select HAVE_CLK
+   select COMMON_CLK
 
 endchoice
 
diff --git a/arch/mips/loongson1/common/clock.c 
b/arch/mips/loongson1/common/clock.c
index 1ec..07133de 100644
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -7,175 +7,22 @@
  * option) any later version.
  */
 
-#include 
-#include 
-#include 
 #include 
 #include 
-#include 
 #include 
-
-#include 
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-struct clk *clk_get(struct device *dev, const char *name)
-{
-   struct clk *c;
-   struct clk *ret = NULL;
-
-   mutex_lock(_mutex);
-   list_for_each_entry(c, , node) {
-   if (!strcmp(c->name, name)) {
-   ret = c;
-   break;
-   }
-   }
-   mutex_unlock(_mutex);
-
-   return ret;
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
-   return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-   return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-static void pll_clk_init(struct clk *clk)
-{
-   u32 pll;
-
-   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-   clk->rate = (12 + (pll & 0x3f)) * 33 / 2
-   + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2;
-   clk->rate *= 100;
-}
-
-static void cpu_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk->parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU;
-   clk->rate = pll / (ctrl >> DIV_CPU_SHIFT);
-}
-
-static void ddr_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk->parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR;
-   clk->rate = pll / (ctrl >> DIV_DDR_SHIFT);
-}
-
-static void dc_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk->parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC;
-   clk->rate = pll / (ctrl >> DIV_DC_SHIFT);
-}
-
-static struct clk_ops pll_clk_ops = {
-   .init   = pll_clk_init,
-};
-
-static struct clk_ops cpu_clk_ops = {
-   .init   = cpu_clk_init,
-};
-
-static struct clk_ops ddr_clk_ops = {
-   .init   = ddr_clk_init,
-};
-
-static s

[PATCH resend] MIPS: Loongson1B: use common clock infrastructure instead of private APIs.

2012-09-27 Thread Kelvin Cheung

1. Remove private clock APIs, which are replaced by the code in
   drivers/clk/clk-ls1x.c
2. Enable COMMON_CLK in the Kconfig.
3. some minor modifications.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 arch/mips/include/asm/mach-loongson1/platform.h |3 +-
 arch/mips/include/asm/mach-loongson1/regs-clk.h |7 +-
 arch/mips/loongson1/Kconfig |2 +-
 arch/mips/loongson1/common/clock.c  |  159 +--
 arch/mips/loongson1/common/platform.c   |9 +-
 arch/mips/loongson1/ls1b/board.c|5 +-
 6 files changed, 16 insertions(+), 169 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson1/platform.h 
b/arch/mips/include/asm/mach-loongson1/platform.h
index 2f17161..718a122 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -18,6 +18,7 @@ extern struct platform_device ls1x_eth0_device;
 extern struct platform_device ls1x_ehci_device;
 extern struct platform_device ls1x_rtc_device;
 
-void ls1x_serial_setup(void);
+extern void __init ls1x_clk_init(void);
+extern void __init ls1x_serial_setup(struct platform_device *pdev);
 
 #endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h 
b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index 8efa7fb..a81fa3d 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,14 +20,15 @@
 
 /* Clock PLL Divisor Register Bits */
 #define DIV_DC_EN  (0x1  31)
-#define DIV_DC (0x1f  26)
 #define DIV_CPU_EN (0x1  25)
-#define DIV_CPU(0x1f  20)
 #define DIV_DDR_EN (0x1  19)
-#define DIV_DDR(0x1f  14)
 
 #define DIV_DC_SHIFT   26
 #define DIV_CPU_SHIFT  20
 #define DIV_DDR_SHIFT  14
 
+#define DIV_DC_WIDTH   5
+#define DIV_CPU_WIDTH  5
+#define DIV_DDR_WIDTH  5
+
 #endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
index a9a14d6..fbf75f6 100644
--- a/arch/mips/loongson1/Kconfig
+++ b/arch/mips/loongson1/Kconfig
@@ -15,7 +15,7 @@ config LOONGSON1_LS1B
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
-   select HAVE_CLK
+   select COMMON_CLK
 
 endchoice
 
diff --git a/arch/mips/loongson1/common/clock.c 
b/arch/mips/loongson1/common/clock.c
index 1ec..07133de 100644
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -7,175 +7,22 @@
  * option) any later version.
  */
 
-#include linux/module.h
-#include linux/list.h
-#include linux/mutex.h
 #include linux/clk.h
 #include linux/err.h
-#include asm/clock.h
 #include asm/time.h
-
-#include loongson1.h
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-struct clk *clk_get(struct device *dev, const char *name)
-{
-   struct clk *c;
-   struct clk *ret = NULL;
-
-   mutex_lock(clocks_mutex);
-   list_for_each_entry(c, clocks, node) {
-   if (!strcmp(c-name, name)) {
-   ret = c;
-   break;
-   }
-   }
-   mutex_unlock(clocks_mutex);
-
-   return ret;
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
-   return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-   return clk-rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-static void pll_clk_init(struct clk *clk)
-{
-   u32 pll;
-
-   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-   clk-rate = (12 + (pll  0x3f)) * 33 / 2
-   + ((pll  8)  0x3ff) * 33 / 1024 / 2;
-   clk-rate *= 100;
-}
-
-static void cpu_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk-parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV)  DIV_CPU;
-   clk-rate = pll / (ctrl  DIV_CPU_SHIFT);
-}
-
-static void ddr_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk-parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV)  DIV_DDR;
-   clk-rate = pll / (ctrl  DIV_DDR_SHIFT);
-}
-
-static void dc_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk-parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV)  DIV_DC;
-   clk-rate = pll / (ctrl  DIV_DC_SHIFT);
-}
-
-static struct clk_ops pll_clk_ops = {
-   .init   = pll_clk_init,
-};
-
-static struct clk_ops cpu_clk_ops = {
-   .init   = cpu_clk_init,
-};
-
-static struct clk_ops ddr_clk_ops = {
-   .init   = ddr_clk_init,
-};
-
-static struct clk_ops

[PATCH v3] clk: add Loongson1B clock support

2012-08-30 Thread Kelvin Cheung

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung 
---
 drivers/clk/Makefile   |1 +
 drivers/clk/clk-ls1x.c |  111 
 2 files changed, 112 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
 obj-$(CONFIG_ARCH_U300)+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
+obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000..f20b750
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang 
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define OSC33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+   return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   u32 pll, rate;
+
+   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+   rate = ((12 + (pll & 0x3f)) * 100) +
+   pll >> 8) & 0x3ff) * 100) >> 10);
+   rate *= OSC;
+   rate >>= 1;
+
+   return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+   .enable = ls1x_pll_clk_enable,
+   .disable = ls1x_pll_clk_disable,
+   .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+const char *name, const char *parent_name, unsigned long flags)
+{
+   struct clk_hw *hw;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   /* allocate the divider */
+   hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+   if (!hw) {
+   pr_err("%s: could not allocate clk_hw\n", __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.ops = _pll_clk_ops;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = (parent_name ? _name : NULL);
+   init.num_parents = (parent_name ? 1 : 0);
+   hw->init = 
+
+   /* register the clock */
+   clk = clk_register(dev, hw);
+
+   if (IS_ERR(clk))
+   kfree(hw);
+
+   return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+   struct clk *clk;
+
+   clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
+   clk_prepare_enable(clk);
+
+   clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "cpu", NULL);
+
+   clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "dc", NULL);
+
+   clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "ahb", NULL);
+   clk_register_clkdev(clk, "stmmaceth", NULL);
+
+   clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "apb", NULL);
+   clk_register_clkdev(clk, "serial8250", NULL);
+}
-- 
1.7.1

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[PATCH v3] clk: add Loongson1B clock support

2012-08-30 Thread Kelvin Cheung

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 drivers/clk/Makefile   |1 +
 drivers/clk/clk-ls1x.c |  111 
 2 files changed, 112 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
 obj-$(CONFIG_ARCH_U300)+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
+obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000..f20b750
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/io.h
+#include linux/slab.h
+#include linux/err.h
+
+#include loongson1.h
+
+#define OSC33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+   return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   u32 pll, rate;
+
+   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+   rate = ((12 + (pll  0x3f)) * 100) +
+   pll  8)  0x3ff) * 100)  10);
+   rate *= OSC;
+   rate = 1;
+
+   return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+   .enable = ls1x_pll_clk_enable,
+   .disable = ls1x_pll_clk_disable,
+   .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+const char *name, const char *parent_name, unsigned long flags)
+{
+   struct clk_hw *hw;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   /* allocate the divider */
+   hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+   if (!hw) {
+   pr_err(%s: could not allocate clk_hw\n, __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.ops = ls1x_pll_clk_ops;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = (parent_name ? parent_name : NULL);
+   init.num_parents = (parent_name ? 1 : 0);
+   hw-init = init;
+
+   /* register the clock */
+   clk = clk_register(dev, hw);
+
+   if (IS_ERR(clk))
+   kfree(hw);
+
+   return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+   struct clk *clk;
+
+   clk = clk_register_pll(NULL, pll_clk, NULL, CLK_IS_ROOT);
+   clk_prepare_enable(clk);
+
+   clk = clk_register_divider(NULL, cpu_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, cpu, NULL);
+
+   clk = clk_register_divider(NULL, dc_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, dc, NULL);
+
+   clk = clk_register_divider(NULL, ahb_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, ahb, NULL);
+   clk_register_clkdev(clk, stmmaceth, NULL);
+
+   clk = clk_register_fixed_factor(NULL, apb_clk, ahb_clk, 0, 1, 2);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, apb, NULL);
+   clk_register_clkdev(clk, serial8250, NULL);
+}
-- 
1.7.1

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[PATCH v3] clk: add Loongson1B clock support

2012-08-20 Thread Kelvin Cheung

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung 
---
 drivers/clk/Makefile   |1 +
 drivers/clk/clk-ls1x.c |  111 
 2 files changed, 112 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
 obj-$(CONFIG_ARCH_U300)+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
+obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000..f20b750
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang 
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define OSC33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+   return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   u32 pll, rate;
+
+   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+   rate = ((12 + (pll & 0x3f)) * 100) +
+   pll >> 8) & 0x3ff) * 100) >> 10);
+   rate *= OSC;
+   rate >>= 1;
+
+   return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+   .enable = ls1x_pll_clk_enable,
+   .disable = ls1x_pll_clk_disable,
+   .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+const char *name, const char *parent_name, unsigned long flags)
+{
+   struct clk_hw *hw;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   /* allocate the divider */
+   hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+   if (!hw) {
+   pr_err("%s: could not allocate clk_hw\n", __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.ops = _pll_clk_ops;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = (parent_name ? _name : NULL);
+   init.num_parents = (parent_name ? 1 : 0);
+   hw->init = 
+
+   /* register the clock */
+   clk = clk_register(dev, hw);
+
+   if (IS_ERR(clk))
+   kfree(hw);
+
+   return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+   struct clk *clk;
+
+   clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
+   clk_prepare_enable(clk);
+
+   clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "cpu", NULL);
+
+   clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "dc", NULL);
+
+   clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "ahb", NULL);
+   clk_register_clkdev(clk, "stmmaceth", NULL);
+
+   clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "apb", NULL);
+   clk_register_clkdev(clk, "serial8250", NULL);
+}
-- 
1.7.1

--
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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3] clk: add Loongson1B clock support

2012-08-20 Thread Kelvin Cheung

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 drivers/clk/Makefile   |1 +
 drivers/clk/clk-ls1x.c |  111 
 2 files changed, 112 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
 obj-$(CONFIG_ARCH_U300)+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
+obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000..f20b750
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/io.h
+#include linux/slab.h
+#include linux/err.h
+
+#include loongson1.h
+
+#define OSC33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+   return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   u32 pll, rate;
+
+   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+   rate = ((12 + (pll  0x3f)) * 100) +
+   pll  8)  0x3ff) * 100)  10);
+   rate *= OSC;
+   rate = 1;
+
+   return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+   .enable = ls1x_pll_clk_enable,
+   .disable = ls1x_pll_clk_disable,
+   .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+const char *name, const char *parent_name, unsigned long flags)
+{
+   struct clk_hw *hw;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   /* allocate the divider */
+   hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+   if (!hw) {
+   pr_err(%s: could not allocate clk_hw\n, __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.ops = ls1x_pll_clk_ops;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = (parent_name ? parent_name : NULL);
+   init.num_parents = (parent_name ? 1 : 0);
+   hw-init = init;
+
+   /* register the clock */
+   clk = clk_register(dev, hw);
+
+   if (IS_ERR(clk))
+   kfree(hw);
+
+   return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+   struct clk *clk;
+
+   clk = clk_register_pll(NULL, pll_clk, NULL, CLK_IS_ROOT);
+   clk_prepare_enable(clk);
+
+   clk = clk_register_divider(NULL, cpu_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, cpu, NULL);
+
+   clk = clk_register_divider(NULL, dc_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, dc, NULL);
+
+   clk = clk_register_divider(NULL, ahb_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, ahb, NULL);
+   clk_register_clkdev(clk, stmmaceth, NULL);
+
+   clk = clk_register_fixed_factor(NULL, apb_clk, ahb_clk, 0, 1, 2);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, apb, NULL);
+   clk_register_clkdev(clk, serial8250, NULL);
+}
-- 
1.7.1

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[PATCH v2] clk: add Loongson1B clock support

2012-08-18 Thread Kelvin Cheung

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung 
---
 drivers/clk/Makefile   |1 +
 drivers/clk/clk-ls1x.c |  108 
 2 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
 obj-$(CONFIG_ARCH_U300)+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
+obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000..ff12fc0
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang 
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define OSC33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+   return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   u32 pll, rate;
+
+   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+   rate = ((12 + (pll & 0x3f)) * 100) +
+   pll >> 8) & 0x3ff) * 100) >> 10);
+   rate *= OSC;
+   rate >>= 1;
+
+   return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+   .enable = ls1x_pll_clk_enable,
+   .disable = ls1x_pll_clk_disable,
+   .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+const char *name, const char *parent_name, unsigned long flags)
+{
+   struct clk_hw *hw;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   /* allocate the divider */
+   hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+   if (!hw) {
+   pr_err("%s: could not allocate clk_hw\n", __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.ops = _pll_clk_ops;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = (parent_name ? _name : NULL);
+   init.num_parents = (parent_name ? 1 : 0);
+   hw->init = 
+
+   /* register the clock */
+   clk = clk_register(dev, hw);
+
+   if (IS_ERR(clk))
+   kfree(hw);
+
+   return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+   struct clk *clk;
+
+   clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
+   clk_prepare_enable(clk);
+
+   clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "cpu", NULL);
+
+   clk = clk_register_divider(NULL, "ddr_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "ddr", NULL);
+   clk_register_clkdev(clk, "stmmaceth", NULL);
+
+   clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "dc", NULL);
+   clk_register_clkdev(clk, "serial8250", NULL);
+}
-- 
1.7.1

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[PATCH] MIPS: Loongson1B: use common clock infrastructure instead of private APIs.

2012-08-18 Thread Kelvin Cheung

1. Remove private clock APIs, which are replaced by the code in
   drivers/clk/clk-ls1x.c
2. Enable COMMON_CLK in the Kconfig.
3. some minor modifications.

Signed-off-by: Kelvin Cheung 
---
 arch/mips/include/asm/mach-loongson1/platform.h |3 +-
 arch/mips/include/asm/mach-loongson1/regs-clk.h |7 +-
 arch/mips/loongson1/Kconfig |2 +-
 arch/mips/loongson1/common/clock.c  |  159 +--
 arch/mips/loongson1/common/platform.c   |9 +-
 arch/mips/loongson1/ls1b/board.c|5 +-
 6 files changed, 16 insertions(+), 169 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson1/platform.h 
b/arch/mips/include/asm/mach-loongson1/platform.h
index 2f17161..718a122 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -18,6 +18,7 @@ extern struct platform_device ls1x_eth0_device;
 extern struct platform_device ls1x_ehci_device;
 extern struct platform_device ls1x_rtc_device;
 
-void ls1x_serial_setup(void);
+extern void __init ls1x_clk_init(void);
+extern void __init ls1x_serial_setup(struct platform_device *pdev);
 
 #endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h 
b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index 8efa7fb..a81fa3d 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,14 +20,15 @@
 
 /* Clock PLL Divisor Register Bits */
 #define DIV_DC_EN  (0x1 << 31)
-#define DIV_DC (0x1f << 26)
 #define DIV_CPU_EN (0x1 << 25)
-#define DIV_CPU(0x1f << 20)
 #define DIV_DDR_EN (0x1 << 19)
-#define DIV_DDR(0x1f << 14)
 
 #define DIV_DC_SHIFT   26
 #define DIV_CPU_SHIFT  20
 #define DIV_DDR_SHIFT  14
 
+#define DIV_DC_WIDTH   5
+#define DIV_CPU_WIDTH  5
+#define DIV_DDR_WIDTH  5
+
 #endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
index a9a14d6..fbf75f6 100644
--- a/arch/mips/loongson1/Kconfig
+++ b/arch/mips/loongson1/Kconfig
@@ -15,7 +15,7 @@ config LOONGSON1_LS1B
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
-   select HAVE_CLK
+   select COMMON_CLK
 
 endchoice
 
diff --git a/arch/mips/loongson1/common/clock.c 
b/arch/mips/loongson1/common/clock.c
index 1ec..07133de 100644
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -7,175 +7,22 @@
  * option) any later version.
  */
 
-#include 
-#include 
-#include 
 #include 
 #include 
-#include 
 #include 
-
-#include 
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-struct clk *clk_get(struct device *dev, const char *name)
-{
-   struct clk *c;
-   struct clk *ret = NULL;
-
-   mutex_lock(_mutex);
-   list_for_each_entry(c, , node) {
-   if (!strcmp(c->name, name)) {
-   ret = c;
-   break;
-   }
-   }
-   mutex_unlock(_mutex);
-
-   return ret;
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
-   return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-   return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-static void pll_clk_init(struct clk *clk)
-{
-   u32 pll;
-
-   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-   clk->rate = (12 + (pll & 0x3f)) * 33 / 2
-   + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2;
-   clk->rate *= 100;
-}
-
-static void cpu_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk->parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU;
-   clk->rate = pll / (ctrl >> DIV_CPU_SHIFT);
-}
-
-static void ddr_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk->parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR;
-   clk->rate = pll / (ctrl >> DIV_DDR_SHIFT);
-}
-
-static void dc_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk->parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC;
-   clk->rate = pll / (ctrl >> DIV_DC_SHIFT);
-}
-
-static struct clk_ops pll_clk_ops = {
-   .init   = pll_clk_init,
-};
-
-static struct clk_ops cpu_clk_ops = {
-   .init   = cpu_clk_init,
-};
-
-static struct clk_ops ddr_clk_ops = {
-   .init   = ddr_clk_init,
-};
-
-static s

[PATCH] clk: add Loongson1B clock support

2012-08-18 Thread Kelvin Cheung

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung 
---
 drivers/clk/Makefile   |1 +
 drivers/clk/clk-ls1x.c |  108 
 2 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
 obj-$(CONFIG_ARCH_U300)+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
+obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000..0aadf9d
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang 
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define OSC33
+
+static DEFINE_SPINLOCK(_lock);
+
+int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+   return 0;
+}
+
+void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   u32 pll, rate;
+
+   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+   rate = ((12 + (pll & 0x3f)) * 100) +
+   pll >> 8) & 0x3ff) * 100) >> 10);
+   rate *= OSC;
+   rate >>= 1;
+
+   return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+   .enable = ls1x_pll_clk_enable,
+   .disable = ls1x_pll_clk_disable,
+   .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+const char *name, const char *parent_name, unsigned long flags)
+{
+   struct clk_hw *hw;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   /* allocate the divider */
+   hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+   if (!hw) {
+   pr_err("%s: could not allocate clk_hw\n", __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.ops = _pll_clk_ops;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = (parent_name ? _name : NULL);
+   init.num_parents = (parent_name ? 1 : 0);
+   hw->init = 
+
+   /* register the clock */
+   clk = clk_register(dev, hw);
+
+   if (IS_ERR(clk))
+   kfree(hw);
+
+   return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+   struct clk *clk;
+
+   clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
+   clk_prepare_enable(clk);
+
+   clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "cpu", NULL);
+
+   clk = clk_register_divider(NULL, "ddr_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "ddr", NULL);
+   clk_register_clkdev(clk, "stmmaceth", NULL);
+
+   clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, "dc", NULL);
+   clk_register_clkdev(clk, "serial8250", NULL);
+}
-- 
1.7.1

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[PATCH] net/stmmac: fix issue of clk_get for Loongson1B.

2012-08-18 Thread Kelvin Cheung

When getting clock, give a chance to the CPUs without DT support,
which use Common Clock Framework, such as Loongson1B.

Signed-off-by: Kelvin Cheung 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index fd8882f..c136162 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2077,7 +2077,7 @@ struct stmmac_priv *stmmac_dvr_probe(struct device 
*device,
goto error_netdev_register;
}
 
-   priv->stmmac_clk = clk_get(priv->device, NULL);
+   priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
if (IS_ERR(priv->stmmac_clk)) {
pr_warning("%s: warning: cannot get CSR clock\n", __func__);
goto error_clk_get;
-- 
1.7.1

--
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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH] net/stmmac: fix issue of clk_get for Loongson1B.

2012-08-18 Thread Kelvin Cheung

When getting clock, give a chance to the CPUs without DT support,
which use Common Clock Framework, such as Loongson1B.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index fd8882f..c136162 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2077,7 +2077,7 @@ struct stmmac_priv *stmmac_dvr_probe(struct device 
*device,
goto error_netdev_register;
}
 
-   priv-stmmac_clk = clk_get(priv-device, NULL);
+   priv-stmmac_clk = clk_get(priv-device, STMMAC_RESOURCE_NAME);
if (IS_ERR(priv-stmmac_clk)) {
pr_warning(%s: warning: cannot get CSR clock\n, __func__);
goto error_clk_get;
-- 
1.7.1

--
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[PATCH] clk: add Loongson1B clock support

2012-08-18 Thread Kelvin Cheung

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 drivers/clk/Makefile   |1 +
 drivers/clk/clk-ls1x.c |  108 
 2 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
 obj-$(CONFIG_ARCH_U300)+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
+obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000..0aadf9d
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/io.h
+#include linux/slab.h
+#include linux/err.h
+#include asm/mach-loongson1/loongson1.h
+
+#include loongson1.h
+
+#define OSC33
+
+static DEFINE_SPINLOCK(_lock);
+
+int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+   return 0;
+}
+
+void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   u32 pll, rate;
+
+   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+   rate = ((12 + (pll  0x3f)) * 100) +
+   pll  8)  0x3ff) * 100)  10);
+   rate *= OSC;
+   rate = 1;
+
+   return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+   .enable = ls1x_pll_clk_enable,
+   .disable = ls1x_pll_clk_disable,
+   .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+const char *name, const char *parent_name, unsigned long flags)
+{
+   struct clk_hw *hw;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   /* allocate the divider */
+   hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+   if (!hw) {
+   pr_err(%s: could not allocate clk_hw\n, __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.ops = ls1x_pll_clk_ops;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = (parent_name ? parent_name : NULL);
+   init.num_parents = (parent_name ? 1 : 0);
+   hw-init = init;
+
+   /* register the clock */
+   clk = clk_register(dev, hw);
+
+   if (IS_ERR(clk))
+   kfree(hw);
+
+   return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+   struct clk *clk;
+
+   clk = clk_register_pll(NULL, pll_clk, NULL, CLK_IS_ROOT);
+   clk_prepare_enable(clk);
+
+   clk = clk_register_divider(NULL, cpu_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, cpu, NULL);
+
+   clk = clk_register_divider(NULL, ddr_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, ddr, NULL);
+   clk_register_clkdev(clk, stmmaceth, NULL);
+
+   clk = clk_register_divider(NULL, dc_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, dc, NULL);
+   clk_register_clkdev(clk, serial8250, NULL);
+}
-- 
1.7.1

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[PATCH] MIPS: Loongson1B: use common clock infrastructure instead of private APIs.

2012-08-18 Thread Kelvin Cheung

1. Remove private clock APIs, which are replaced by the code in
   drivers/clk/clk-ls1x.c
2. Enable COMMON_CLK in the Kconfig.
3. some minor modifications.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 arch/mips/include/asm/mach-loongson1/platform.h |3 +-
 arch/mips/include/asm/mach-loongson1/regs-clk.h |7 +-
 arch/mips/loongson1/Kconfig |2 +-
 arch/mips/loongson1/common/clock.c  |  159 +--
 arch/mips/loongson1/common/platform.c   |9 +-
 arch/mips/loongson1/ls1b/board.c|5 +-
 6 files changed, 16 insertions(+), 169 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson1/platform.h 
b/arch/mips/include/asm/mach-loongson1/platform.h
index 2f17161..718a122 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -18,6 +18,7 @@ extern struct platform_device ls1x_eth0_device;
 extern struct platform_device ls1x_ehci_device;
 extern struct platform_device ls1x_rtc_device;
 
-void ls1x_serial_setup(void);
+extern void __init ls1x_clk_init(void);
+extern void __init ls1x_serial_setup(struct platform_device *pdev);
 
 #endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h 
b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index 8efa7fb..a81fa3d 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,14 +20,15 @@
 
 /* Clock PLL Divisor Register Bits */
 #define DIV_DC_EN  (0x1  31)
-#define DIV_DC (0x1f  26)
 #define DIV_CPU_EN (0x1  25)
-#define DIV_CPU(0x1f  20)
 #define DIV_DDR_EN (0x1  19)
-#define DIV_DDR(0x1f  14)
 
 #define DIV_DC_SHIFT   26
 #define DIV_CPU_SHIFT  20
 #define DIV_DDR_SHIFT  14
 
+#define DIV_DC_WIDTH   5
+#define DIV_CPU_WIDTH  5
+#define DIV_DDR_WIDTH  5
+
 #endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
index a9a14d6..fbf75f6 100644
--- a/arch/mips/loongson1/Kconfig
+++ b/arch/mips/loongson1/Kconfig
@@ -15,7 +15,7 @@ config LOONGSON1_LS1B
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
-   select HAVE_CLK
+   select COMMON_CLK
 
 endchoice
 
diff --git a/arch/mips/loongson1/common/clock.c 
b/arch/mips/loongson1/common/clock.c
index 1ec..07133de 100644
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -7,175 +7,22 @@
  * option) any later version.
  */
 
-#include linux/module.h
-#include linux/list.h
-#include linux/mutex.h
 #include linux/clk.h
 #include linux/err.h
-#include asm/clock.h
 #include asm/time.h
-
-#include loongson1.h
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-struct clk *clk_get(struct device *dev, const char *name)
-{
-   struct clk *c;
-   struct clk *ret = NULL;
-
-   mutex_lock(clocks_mutex);
-   list_for_each_entry(c, clocks, node) {
-   if (!strcmp(c-name, name)) {
-   ret = c;
-   break;
-   }
-   }
-   mutex_unlock(clocks_mutex);
-
-   return ret;
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
-   return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-   return clk-rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-static void pll_clk_init(struct clk *clk)
-{
-   u32 pll;
-
-   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
-   clk-rate = (12 + (pll  0x3f)) * 33 / 2
-   + ((pll  8)  0x3ff) * 33 / 1024 / 2;
-   clk-rate *= 100;
-}
-
-static void cpu_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk-parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV)  DIV_CPU;
-   clk-rate = pll / (ctrl  DIV_CPU_SHIFT);
-}
-
-static void ddr_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk-parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV)  DIV_DDR;
-   clk-rate = pll / (ctrl  DIV_DDR_SHIFT);
-}
-
-static void dc_clk_init(struct clk *clk)
-{
-   u32 pll, ctrl;
-
-   pll = clk_get_rate(clk-parent);
-   ctrl = __raw_readl(LS1X_CLK_PLL_DIV)  DIV_DC;
-   clk-rate = pll / (ctrl  DIV_DC_SHIFT);
-}
-
-static struct clk_ops pll_clk_ops = {
-   .init   = pll_clk_init,
-};
-
-static struct clk_ops cpu_clk_ops = {
-   .init   = cpu_clk_init,
-};
-
-static struct clk_ops ddr_clk_ops = {
-   .init   = ddr_clk_init,
-};
-
-static struct clk_ops

[PATCH v2] clk: add Loongson1B clock support

2012-08-18 Thread Kelvin Cheung

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com
---
 drivers/clk/Makefile   |1 +
 drivers/clk/clk-ls1x.c |  108 
 2 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
 obj-$(CONFIG_ARCH_U300)+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
+obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000..ff12fc0
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/io.h
+#include linux/slab.h
+#include linux/err.h
+#include asm/mach-loongson1/loongson1.h
+
+#include loongson1.h
+
+#define OSC33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+   return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+   u32 pll, rate;
+
+   pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+   rate = ((12 + (pll  0x3f)) * 100) +
+   pll  8)  0x3ff) * 100)  10);
+   rate *= OSC;
+   rate = 1;
+
+   return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+   .enable = ls1x_pll_clk_enable,
+   .disable = ls1x_pll_clk_disable,
+   .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+const char *name, const char *parent_name, unsigned long flags)
+{
+   struct clk_hw *hw;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   /* allocate the divider */
+   hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+   if (!hw) {
+   pr_err(%s: could not allocate clk_hw\n, __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.ops = ls1x_pll_clk_ops;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = (parent_name ? parent_name : NULL);
+   init.num_parents = (parent_name ? 1 : 0);
+   hw-init = init;
+
+   /* register the clock */
+   clk = clk_register(dev, hw);
+
+   if (IS_ERR(clk))
+   kfree(hw);
+
+   return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+   struct clk *clk;
+
+   clk = clk_register_pll(NULL, pll_clk, NULL, CLK_IS_ROOT);
+   clk_prepare_enable(clk);
+
+   clk = clk_register_divider(NULL, cpu_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+   DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, cpu, NULL);
+
+   clk = clk_register_divider(NULL, ddr_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, ddr, NULL);
+   clk_register_clkdev(clk, stmmaceth, NULL);
+
+   clk = clk_register_divider(NULL, dc_clk, pll_clk,
+   CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, _lock);
+   clk_prepare_enable(clk);
+   clk_register_clkdev(clk, dc, NULL);
+   clk_register_clkdev(clk, serial8250, NULL);
+}
-- 
1.7.1

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[PATCH V7 4/4] (Updated) MIPS: Add defconfig for Loongson1B

2012-07-25 Thread Kelvin Cheung

This patch adds defconfig for Loongson1B.

Signed-off-by: Kelvin Cheung 

---
V7(updated):
Add CONFIG_USB_ANNOUNCE_NEW_DEVICES in default
configuration.
---
 arch/mips/configs/ls1b_defconfig |  109 ++
 1 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/configs/ls1b_defconfig

diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig
new file mode 100644
index 000..80cff8b
--- /dev/null
+++ b/arch/mips/configs/ls1b_defconfig
@@ -0,0 +1,109 @@
+CONFIG_MACH_LOONGSON1=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_EXPERT=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=m
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_DA=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=8
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB_HID=m
+CONFIG_HID_GENERIC=m
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_STORAGE=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_LOONGSON1=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+# CONFIG_EARLY_PRINTK is not set
-- 
1.7.1

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[PATCH V7 3/4] (Updated) MIPS: Add Makefile and Kconfig for Loongson1B

2012-07-25 Thread Kelvin Cheung

This patch adds Makefile and Kconfig related to Loongson1B.

Signed-off-by: Kelvin Cheung 

---
V7(updated):
Change the load address of kernel to 0x8010.
---
 arch/mips/Kbuild.platforms  |1 +
 arch/mips/Kconfig   |   31 +++
 arch/mips/loongson1/Kconfig |   21 +
 arch/mips/loongson1/Makefile|   11 +++
 arch/mips/loongson1/Platform|7 +++
 arch/mips/loongson1/common/Makefile |5 +
 arch/mips/loongson1/ls1b/Makefile   |5 +
 7 files changed, 81 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/loongson1/Kconfig
 create mode 100644 arch/mips/loongson1/Makefile
 create mode 100644 arch/mips/loongson1/Platform
 create mode 100644 arch/mips/loongson1/common/Makefile
 create mode 100644 arch/mips/loongson1/ls1b/Makefile

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5ce8029..d64786d 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -14,6 +14,7 @@ platforms += jz4740
 platforms += lantiq
 platforms += lasat
 platforms += loongson
+platforms += loongson1
 platforms += mipssim
 platforms += mti-malta
 platforms += netlogic
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 08dfc79..61e1459 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -265,6 +265,17 @@ config MACH_LOONGSON
  Chinese Academy of Sciences (CAS) in the People's Republic
  of China. The chief architect is Professor Weiwu Hu.
 
+config MACH_LOONGSON1
+   bool "Loongson1 family of machines"
+   select SYS_SUPPORTS_ZBOOT
+   help
+ This enables the support of Loongson1 family of machines.
+
+ Loongson1 is a family of 32-bit MIPS-compatible SoCs.
+ developed at Institute of Computing Technology (ICT),
+ Chinese Academy of Sciences (CAS) in the People's Republic
+ of China.
+
 config MIPS_MALTA
bool "MIPS Malta board"
select ARCH_MAY_HAVE_PC_FDC
@@ -838,6 +849,7 @@ source "arch/mips/txx9/Kconfig"
 source "arch/mips/vr41xx/Kconfig"
 source "arch/mips/cavium-octeon/Kconfig"
 source "arch/mips/loongson/Kconfig"
+source "arch/mips/loongson1/Kconfig"
 source "arch/mips/netlogic/Kconfig"
 
 endmenu
@@ -1219,6 +1231,14 @@ config CPU_LOONGSON2F
  have a similar programming interface with FPGA northbridge used in
  Loongson2E.
 
+config CPU_LOONGSON1B
+   bool "Loongson 1B"
+   depends on SYS_HAS_CPU_LOONGSON1B
+   select CPU_LOONGSON1
+   help
+ The Loongson 1B is a 32-bit SoC, which implements the MIPS32
+ release 2 instruction set.
+
 config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
@@ -1548,6 +1568,14 @@ config CPU_LOONGSON2
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
 
+config CPU_LOONGSON1
+   bool
+   select CPU_MIPS32
+   select CPU_MIPSR2
+   select CPU_HAS_PREFETCH
+   select CPU_SUPPORTS_32BIT_KERNEL
+   select CPU_SUPPORTS_HIGHMEM
+
 config CPU_BMIPS
bool
select CPU_MIPS32
@@ -1566,6 +1594,9 @@ config SYS_HAS_CPU_LOONGSON2F
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
select CPU_SUPPORTS_UNCACHED_ACCELERATED
 
+config SYS_HAS_CPU_LOONGSON1B
+   bool
+
 config SYS_HAS_CPU_MIPS32_R1
bool
 
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
new file mode 100644
index 000..237fa21
--- /dev/null
+++ b/arch/mips/loongson1/Kconfig
@@ -0,0 +1,21 @@
+if MACH_LOONGSON1
+
+choice
+   prompt "Machine Type"
+
+config LOONGSON1_LS1B
+   bool "Loongson LS1B board"
+   select CEVT_R4K
+   select CSRC_R4K
+   select SYS_HAS_CPU_LOONGSON1B
+   select DMA_NONCOHERENT
+   select BOOT_ELF32
+   select IRQ_CPU
+   select SYS_SUPPORTS_32BIT_KERNEL
+   select SYS_SUPPORTS_LITTLE_ENDIAN
+   select SYS_SUPPORTS_HIGHMEM
+   select SYS_HAS_EARLY_PRINTK
+
+endchoice
+
+endif # MACH_LOONGSON1
diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile
new file mode 100644
index 000..e9123c2
--- /dev/null
+++ b/arch/mips/loongson1/Makefile
@@ -0,0 +1,11 @@
+#
+# Common code for all Loongson1 based systems
+#
+
+obj-$(CONFIG_MACH_LOONGSON1) += common/
+
+#
+# Loongson LS1B board
+#
+
+obj-$(CONFIG_LOONGSON1_LS1B)  += ls1b/
diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform
new file mode 100644
index 000..99bdefe
--- /dev/null
+++ b/arch/mips/loongson1/Platform
@@ -0,0 +1,7 @@
+cflags-$(CONFIG_CPU_LOONGSON1)  += \
+   $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA 
-D_MIPS_ISA=_MIPS_ISA_MIPS32) \
+   -Wa,-mips32r2 -Wa,--trap
+
+platform-$(CONFIG_MACH_LOONGSON1)  += loongson1/
+cflags-$(CONFIG_MACH_LOONGSON1)+= 
-I$(srctree)/a

[PATCH V7 2/4] (Updated) MIPS: Add board support for Loongson1B

2012-07-25 Thread Kelvin Cheung

This patch adds basic platform devices for Loongson1B,
including serial port, ethernet, usb, rtc and interrupt handler.

Loongson1B UART is compatible with NS16550A.
Loongson1B GMAC is built around Synopsys IP Core.

Use normal descriptor instead of enhanced descriptor.
Thanks to Giuseppe for updating the normal descriptor
in stmmac driver.

Thanks to Zhao Zhang for implementing the RTC driver.

Signed-off-by: Kelvin Cheung 

---
V7(updated):
1.Remove 'ifdef' of platform devices. (Asked by Ralf)
2.Modify plat_stmmacenet_data accordingly due to the change
  of upstream.
---
 arch/mips/include/asm/mach-loongson1/irq.h   |   73 ++
 arch/mips/include/asm/mach-loongson1/loongson1.h |   44 ++
 arch/mips/include/asm/mach-loongson1/platform.h  |   23 +++
 arch/mips/include/asm/mach-loongson1/prom.h  |   24 +++
 arch/mips/include/asm/mach-loongson1/regs-clk.h  |   33 +
 arch/mips/include/asm/mach-loongson1/regs-wdt.h  |   22 +++
 arch/mips/include/asm/mach-loongson1/war.h   |   25 
 arch/mips/loongson1/common/clock.c   |  165 ++
 arch/mips/loongson1/common/irq.c |  147 +++
 arch/mips/loongson1/common/platform.c|  124 
 arch/mips/loongson1/common/prom.c|   87 
 arch/mips/loongson1/common/reset.c   |   45 ++
 arch/mips/loongson1/common/setup.c   |   29 
 arch/mips/loongson1/ls1b/board.c |   33 +
 14 files changed, 874 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/war.h
 create mode 100644 arch/mips/loongson1/common/clock.c
 create mode 100644 arch/mips/loongson1/common/irq.c
 create mode 100644 arch/mips/loongson1/common/platform.c
 create mode 100644 arch/mips/loongson1/common/prom.c
 create mode 100644 arch/mips/loongson1/common/reset.c
 create mode 100644 arch/mips/loongson1/common/setup.c
 create mode 100644 arch/mips/loongson1/ls1b/board.c

diff --git a/arch/mips/include/asm/mach-loongson1/irq.h 
b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 000..ccc42cc
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang 
+ *
+ * IRQ mappings for Loongson1.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_IRQ_H
+#define __ASM_MACH_LOONGSON1_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE  0
+#define MIPS_CPU_IRQ(x)(MIPS_CPU_IRQ_BASE + (x))
+
+#define SOFTINT0_IRQ   MIPS_CPU_IRQ(0)
+#define SOFTINT1_IRQ   MIPS_CPU_IRQ(1)
+#define INT0_IRQ   MIPS_CPU_IRQ(2)
+#define INT1_IRQ   MIPS_CPU_IRQ(3)
+#define INT2_IRQ   MIPS_CPU_IRQ(4)
+#define INT3_IRQ   MIPS_CPU_IRQ(5)
+#define INT4_IRQ   MIPS_CPU_IRQ(6)
+#define TIMER_IRQ  MIPS_CPU_IRQ(7) /* cpu timer */
+
+#define MIPS_CPU_IRQS  (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
+
+/*
+ * INT0~3 Interrupt Numbers
+ */
+#define LS1X_IRQ_BASE  MIPS_CPU_IRQS
+#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
+
+#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
+#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
+#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
+#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
+#define LS1X_CAN0_IRQ  LS1X_IRQ(0, 6)
+#define LS1X_CAN1_IRQ  LS1X_IRQ(0, 7)
+#define LS1X_SPI0_IRQ  LS1X_IRQ(0, 8)
+#define LS1X_SPI1_IRQ  LS1X_IRQ(0, 9)
+#define LS1X_AC97_IRQ  LS1X_IRQ(0, 10)
+#define LS1X_DMA0_IRQ  LS1X_IRQ(0, 13)
+#define LS1X_DMA1_IRQ  LS1X_IRQ(0, 14)
+#define LS1X_DMA2_IRQ  LS1X_IRQ(0, 15)
+#define LS1X_PWM0_IRQ  LS1X_IRQ(0, 17)
+#define LS1X_PWM1_IRQ  LS1X_IRQ(0, 18)
+#define LS1X_PWM2_IRQ  LS1X_IRQ(0, 19)
+#define LS1X_PWM3_IRQ  LS1X_IRQ(0, 20)
+#define LS1X_RTC_INT0_IRQ  LS1X_IRQ(0, 21)
+#define LS1X_RTC_INT1_IRQ  LS1X_IRQ(0, 22)
+#define LS1X_RTC_IN

[PATCH V7 2/4] (Updated) MIPS: Add board support for Loongson1B

2012-07-25 Thread Kelvin Cheung

This patch adds basic platform devices for Loongson1B,
including serial port, ethernet, usb, rtc and interrupt handler.

Loongson1B UART is compatible with NS16550A.
Loongson1B GMAC is built around Synopsys IP Core.

Use normal descriptor instead of enhanced descriptor.
Thanks to Giuseppe for updating the normal descriptor
in stmmac driver.

Thanks to Zhao Zhang for implementing the RTC driver.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com

---
V7(updated):
1.Remove 'ifdef' of platform devices. (Asked by Ralf)
2.Modify plat_stmmacenet_data accordingly due to the change
  of upstream.
---
 arch/mips/include/asm/mach-loongson1/irq.h   |   73 ++
 arch/mips/include/asm/mach-loongson1/loongson1.h |   44 ++
 arch/mips/include/asm/mach-loongson1/platform.h  |   23 +++
 arch/mips/include/asm/mach-loongson1/prom.h  |   24 +++
 arch/mips/include/asm/mach-loongson1/regs-clk.h  |   33 +
 arch/mips/include/asm/mach-loongson1/regs-wdt.h  |   22 +++
 arch/mips/include/asm/mach-loongson1/war.h   |   25 
 arch/mips/loongson1/common/clock.c   |  165 ++
 arch/mips/loongson1/common/irq.c |  147 +++
 arch/mips/loongson1/common/platform.c|  124 
 arch/mips/loongson1/common/prom.c|   87 
 arch/mips/loongson1/common/reset.c   |   45 ++
 arch/mips/loongson1/common/setup.c   |   29 
 arch/mips/loongson1/ls1b/board.c |   33 +
 14 files changed, 874 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/war.h
 create mode 100644 arch/mips/loongson1/common/clock.c
 create mode 100644 arch/mips/loongson1/common/irq.c
 create mode 100644 arch/mips/loongson1/common/platform.c
 create mode 100644 arch/mips/loongson1/common/prom.c
 create mode 100644 arch/mips/loongson1/common/reset.c
 create mode 100644 arch/mips/loongson1/common/setup.c
 create mode 100644 arch/mips/loongson1/ls1b/board.c

diff --git a/arch/mips/include/asm/mach-loongson1/irq.h 
b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 000..ccc42cc
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * IRQ mappings for Loongson1.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_IRQ_H
+#define __ASM_MACH_LOONGSON1_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE  0
+#define MIPS_CPU_IRQ(x)(MIPS_CPU_IRQ_BASE + (x))
+
+#define SOFTINT0_IRQ   MIPS_CPU_IRQ(0)
+#define SOFTINT1_IRQ   MIPS_CPU_IRQ(1)
+#define INT0_IRQ   MIPS_CPU_IRQ(2)
+#define INT1_IRQ   MIPS_CPU_IRQ(3)
+#define INT2_IRQ   MIPS_CPU_IRQ(4)
+#define INT3_IRQ   MIPS_CPU_IRQ(5)
+#define INT4_IRQ   MIPS_CPU_IRQ(6)
+#define TIMER_IRQ  MIPS_CPU_IRQ(7) /* cpu timer */
+
+#define MIPS_CPU_IRQS  (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
+
+/*
+ * INT0~3 Interrupt Numbers
+ */
+#define LS1X_IRQ_BASE  MIPS_CPU_IRQS
+#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n  5) + (x))
+
+#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
+#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
+#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
+#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
+#define LS1X_CAN0_IRQ  LS1X_IRQ(0, 6)
+#define LS1X_CAN1_IRQ  LS1X_IRQ(0, 7)
+#define LS1X_SPI0_IRQ  LS1X_IRQ(0, 8)
+#define LS1X_SPI1_IRQ  LS1X_IRQ(0, 9)
+#define LS1X_AC97_IRQ  LS1X_IRQ(0, 10)
+#define LS1X_DMA0_IRQ  LS1X_IRQ(0, 13)
+#define LS1X_DMA1_IRQ  LS1X_IRQ(0, 14)
+#define LS1X_DMA2_IRQ  LS1X_IRQ(0, 15)
+#define LS1X_PWM0_IRQ  LS1X_IRQ(0, 17)
+#define LS1X_PWM1_IRQ  LS1X_IRQ(0, 18)
+#define LS1X_PWM2_IRQ  LS1X_IRQ(0, 19)
+#define LS1X_PWM3_IRQ  LS1X_IRQ(0, 20)
+#define LS1X_RTC_INT0_IRQ  LS1X_IRQ(0, 21)
+#define LS1X_RTC_INT1_IRQ

[PATCH V7 3/4] (Updated) MIPS: Add Makefile and Kconfig for Loongson1B

2012-07-25 Thread Kelvin Cheung

This patch adds Makefile and Kconfig related to Loongson1B.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com

---
V7(updated):
Change the load address of kernel to 0x8010.
---
 arch/mips/Kbuild.platforms  |1 +
 arch/mips/Kconfig   |   31 +++
 arch/mips/loongson1/Kconfig |   21 +
 arch/mips/loongson1/Makefile|   11 +++
 arch/mips/loongson1/Platform|7 +++
 arch/mips/loongson1/common/Makefile |5 +
 arch/mips/loongson1/ls1b/Makefile   |5 +
 7 files changed, 81 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/loongson1/Kconfig
 create mode 100644 arch/mips/loongson1/Makefile
 create mode 100644 arch/mips/loongson1/Platform
 create mode 100644 arch/mips/loongson1/common/Makefile
 create mode 100644 arch/mips/loongson1/ls1b/Makefile

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5ce8029..d64786d 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -14,6 +14,7 @@ platforms += jz4740
 platforms += lantiq
 platforms += lasat
 platforms += loongson
+platforms += loongson1
 platforms += mipssim
 platforms += mti-malta
 platforms += netlogic
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 08dfc79..61e1459 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -265,6 +265,17 @@ config MACH_LOONGSON
  Chinese Academy of Sciences (CAS) in the People's Republic
  of China. The chief architect is Professor Weiwu Hu.
 
+config MACH_LOONGSON1
+   bool Loongson1 family of machines
+   select SYS_SUPPORTS_ZBOOT
+   help
+ This enables the support of Loongson1 family of machines.
+
+ Loongson1 is a family of 32-bit MIPS-compatible SoCs.
+ developed at Institute of Computing Technology (ICT),
+ Chinese Academy of Sciences (CAS) in the People's Republic
+ of China.
+
 config MIPS_MALTA
bool MIPS Malta board
select ARCH_MAY_HAVE_PC_FDC
@@ -838,6 +849,7 @@ source arch/mips/txx9/Kconfig
 source arch/mips/vr41xx/Kconfig
 source arch/mips/cavium-octeon/Kconfig
 source arch/mips/loongson/Kconfig
+source arch/mips/loongson1/Kconfig
 source arch/mips/netlogic/Kconfig
 
 endmenu
@@ -1219,6 +1231,14 @@ config CPU_LOONGSON2F
  have a similar programming interface with FPGA northbridge used in
  Loongson2E.
 
+config CPU_LOONGSON1B
+   bool Loongson 1B
+   depends on SYS_HAS_CPU_LOONGSON1B
+   select CPU_LOONGSON1
+   help
+ The Loongson 1B is a 32-bit SoC, which implements the MIPS32
+ release 2 instruction set.
+
 config CPU_MIPS32_R1
bool MIPS32 Release 1
depends on SYS_HAS_CPU_MIPS32_R1
@@ -1548,6 +1568,14 @@ config CPU_LOONGSON2
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
 
+config CPU_LOONGSON1
+   bool
+   select CPU_MIPS32
+   select CPU_MIPSR2
+   select CPU_HAS_PREFETCH
+   select CPU_SUPPORTS_32BIT_KERNEL
+   select CPU_SUPPORTS_HIGHMEM
+
 config CPU_BMIPS
bool
select CPU_MIPS32
@@ -1566,6 +1594,9 @@ config SYS_HAS_CPU_LOONGSON2F
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
select CPU_SUPPORTS_UNCACHED_ACCELERATED
 
+config SYS_HAS_CPU_LOONGSON1B
+   bool
+
 config SYS_HAS_CPU_MIPS32_R1
bool
 
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
new file mode 100644
index 000..237fa21
--- /dev/null
+++ b/arch/mips/loongson1/Kconfig
@@ -0,0 +1,21 @@
+if MACH_LOONGSON1
+
+choice
+   prompt Machine Type
+
+config LOONGSON1_LS1B
+   bool Loongson LS1B board
+   select CEVT_R4K
+   select CSRC_R4K
+   select SYS_HAS_CPU_LOONGSON1B
+   select DMA_NONCOHERENT
+   select BOOT_ELF32
+   select IRQ_CPU
+   select SYS_SUPPORTS_32BIT_KERNEL
+   select SYS_SUPPORTS_LITTLE_ENDIAN
+   select SYS_SUPPORTS_HIGHMEM
+   select SYS_HAS_EARLY_PRINTK
+
+endchoice
+
+endif # MACH_LOONGSON1
diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile
new file mode 100644
index 000..e9123c2
--- /dev/null
+++ b/arch/mips/loongson1/Makefile
@@ -0,0 +1,11 @@
+#
+# Common code for all Loongson1 based systems
+#
+
+obj-$(CONFIG_MACH_LOONGSON1) += common/
+
+#
+# Loongson LS1B board
+#
+
+obj-$(CONFIG_LOONGSON1_LS1B)  += ls1b/
diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform
new file mode 100644
index 000..99bdefe
--- /dev/null
+++ b/arch/mips/loongson1/Platform
@@ -0,0 +1,7 @@
+cflags-$(CONFIG_CPU_LOONGSON1)  += \
+   $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA 
-D_MIPS_ISA=_MIPS_ISA_MIPS32) \
+   -Wa,-mips32r2 -Wa,--trap
+
+platform-$(CONFIG_MACH_LOONGSON1)  += loongson1/
+cflags-$(CONFIG_MACH_LOONGSON1)+= 
-I$(srctree)/arch/mips/include/asm/mach-loongson1
+load-$(CONFIG_LOONGSON1_LS1B)  += 0x8010
diff --git a/arch/mips

[PATCH V7 4/4] (Updated) MIPS: Add defconfig for Loongson1B

2012-07-25 Thread Kelvin Cheung

This patch adds defconfig for Loongson1B.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com

---
V7(updated):
Add CONFIG_USB_ANNOUNCE_NEW_DEVICES in default
configuration.
---
 arch/mips/configs/ls1b_defconfig |  109 ++
 1 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/configs/ls1b_defconfig

diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig
new file mode 100644
index 000..80cff8b
--- /dev/null
+++ b/arch/mips/configs/ls1b_defconfig
@@ -0,0 +1,109 @@
+CONFIG_MACH_LOONGSON1=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_EXPERT=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=m
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_DA=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=8
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB_HID=m
+CONFIG_HID_GENERIC=m
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_STORAGE=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_LOONGSON1=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+# CONFIG_EARLY_PRINTK is not set
-- 
1.7.1

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH V7 4/4] MIPS: Add defconfig for Loongson1B

2012-07-07 Thread Kelvin Cheung

This patch adds defconfig for Loongson1B.

Signed-off-by: Kelvin Cheung 

---
V7(updated):
Add CONFIG_USB_ANNOUNCE_NEW_DEVICES in default
configuration.
---
 arch/mips/configs/ls1b_defconfig |  109 ++
 1 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/configs/ls1b_defconfig

diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig
new file mode 100644
index 000..80cff8b
--- /dev/null
+++ b/arch/mips/configs/ls1b_defconfig
@@ -0,0 +1,109 @@
+CONFIG_MACH_LOONGSON1=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_EXPERT=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=m
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_DA=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=8
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB_HID=m
+CONFIG_HID_GENERIC=m
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_STORAGE=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_LOONGSON1=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+# CONFIG_EARLY_PRINTK is not set
-- 
1.7.1

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[PATCH V7 3/4] MIPS: Add Makefile and Kconfig for Loongson1B

2012-07-07 Thread Kelvin Cheung

This patch adds Makefile and Kconfig related to Loongson1B.

Signed-off-by: Kelvin Cheung 

---
V7(updated):
Change the load address of kernel to 0x8010.
---
 arch/mips/Kbuild.platforms  |1 +
 arch/mips/Kconfig   |   31 +++
 arch/mips/loongson1/Kconfig |   21 +
 arch/mips/loongson1/Makefile|   11 +++
 arch/mips/loongson1/Platform|7 +++
 arch/mips/loongson1/common/Makefile |5 +
 arch/mips/loongson1/ls1b/Makefile   |5 +
 7 files changed, 81 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/loongson1/Kconfig
 create mode 100644 arch/mips/loongson1/Makefile
 create mode 100644 arch/mips/loongson1/Platform
 create mode 100644 arch/mips/loongson1/common/Makefile
 create mode 100644 arch/mips/loongson1/ls1b/Makefile

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5ce8029..d64786d 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -14,6 +14,7 @@ platforms += jz4740
 platforms += lantiq
 platforms += lasat
 platforms += loongson
+platforms += loongson1
 platforms += mipssim
 platforms += mti-malta
 platforms += netlogic
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 08dfc79..61e1459 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -265,6 +265,17 @@ config MACH_LOONGSON
  Chinese Academy of Sciences (CAS) in the People's Republic
  of China. The chief architect is Professor Weiwu Hu.
 
+config MACH_LOONGSON1
+   bool "Loongson1 family of machines"
+   select SYS_SUPPORTS_ZBOOT
+   help
+ This enables the support of Loongson1 family of machines.
+
+ Loongson1 is a family of 32-bit MIPS-compatible SoCs.
+ developed at Institute of Computing Technology (ICT),
+ Chinese Academy of Sciences (CAS) in the People's Republic
+ of China.
+
 config MIPS_MALTA
bool "MIPS Malta board"
select ARCH_MAY_HAVE_PC_FDC
@@ -838,6 +849,7 @@ source "arch/mips/txx9/Kconfig"
 source "arch/mips/vr41xx/Kconfig"
 source "arch/mips/cavium-octeon/Kconfig"
 source "arch/mips/loongson/Kconfig"
+source "arch/mips/loongson1/Kconfig"
 source "arch/mips/netlogic/Kconfig"
 
 endmenu
@@ -1219,6 +1231,14 @@ config CPU_LOONGSON2F
  have a similar programming interface with FPGA northbridge used in
  Loongson2E.
 
+config CPU_LOONGSON1B
+   bool "Loongson 1B"
+   depends on SYS_HAS_CPU_LOONGSON1B
+   select CPU_LOONGSON1
+   help
+ The Loongson 1B is a 32-bit SoC, which implements the MIPS32
+ release 2 instruction set.
+
 config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
@@ -1548,6 +1568,14 @@ config CPU_LOONGSON2
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
 
+config CPU_LOONGSON1
+   bool
+   select CPU_MIPS32
+   select CPU_MIPSR2
+   select CPU_HAS_PREFETCH
+   select CPU_SUPPORTS_32BIT_KERNEL
+   select CPU_SUPPORTS_HIGHMEM
+
 config CPU_BMIPS
bool
select CPU_MIPS32
@@ -1566,6 +1594,9 @@ config SYS_HAS_CPU_LOONGSON2F
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
select CPU_SUPPORTS_UNCACHED_ACCELERATED
 
+config SYS_HAS_CPU_LOONGSON1B
+   bool
+
 config SYS_HAS_CPU_MIPS32_R1
bool
 
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
new file mode 100644
index 000..237fa21
--- /dev/null
+++ b/arch/mips/loongson1/Kconfig
@@ -0,0 +1,21 @@
+if MACH_LOONGSON1
+
+choice
+   prompt "Machine Type"
+
+config LOONGSON1_LS1B
+   bool "Loongson LS1B board"
+   select CEVT_R4K
+   select CSRC_R4K
+   select SYS_HAS_CPU_LOONGSON1B
+   select DMA_NONCOHERENT
+   select BOOT_ELF32
+   select IRQ_CPU
+   select SYS_SUPPORTS_32BIT_KERNEL
+   select SYS_SUPPORTS_LITTLE_ENDIAN
+   select SYS_SUPPORTS_HIGHMEM
+   select SYS_HAS_EARLY_PRINTK
+
+endchoice
+
+endif # MACH_LOONGSON1
diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile
new file mode 100644
index 000..e9123c2
--- /dev/null
+++ b/arch/mips/loongson1/Makefile
@@ -0,0 +1,11 @@
+#
+# Common code for all Loongson1 based systems
+#
+
+obj-$(CONFIG_MACH_LOONGSON1) += common/
+
+#
+# Loongson LS1B board
+#
+
+obj-$(CONFIG_LOONGSON1_LS1B)  += ls1b/
diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform
new file mode 100644
index 000..99bdefe
--- /dev/null
+++ b/arch/mips/loongson1/Platform
@@ -0,0 +1,7 @@
+cflags-$(CONFIG_CPU_LOONGSON1)  += \
+   $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA 
-D_MIPS_ISA=_MIPS_ISA_MIPS32) \
+   -Wa,-mips32r2 -Wa,--trap
+
+platform-$(CONFIG_MACH_LOONGSON1)  += loongson1/
+cflags-$(CONFIG_MACH_LOONGSON1)+= 
-I$(srctree)/a

[PATCH V7 2/4] MIPS: Add board support for Loongson1B

2012-07-07 Thread Kelvin Cheung

This patch adds basic platform devices for Loongson1B,
including serial port, ethernet, usb, rtc and interrupt handler.

Loongson1B UART is compatible with NS16550A.
Loongson1B GMAC is built around Synopsys IP Core.

Use normal descriptor instead of enhanced descriptor.
Thanks to Giuseppe for updating the normal descriptor
in stmmac driver.

Thanks to Zhao Zhang for implementing the RTC driver.

Signed-off-by: Kelvin Cheung 

---
V7(updated):
1.Remove 'ifdef' of platform devices. (Asked by Ralf)
2.Modify plat_stmmacenet_data accordingly due to the change
  of upstream.
---
 arch/mips/include/asm/mach-loongson1/irq.h   |   73 ++
 arch/mips/include/asm/mach-loongson1/loongson1.h |   44 ++
 arch/mips/include/asm/mach-loongson1/platform.h  |   23 +++
 arch/mips/include/asm/mach-loongson1/prom.h  |   24 +++
 arch/mips/include/asm/mach-loongson1/regs-clk.h  |   33 +
 arch/mips/include/asm/mach-loongson1/regs-wdt.h  |   22 +++
 arch/mips/include/asm/mach-loongson1/war.h   |   25 
 arch/mips/loongson1/common/clock.c   |  165 ++
 arch/mips/loongson1/common/irq.c |  147 +++
 arch/mips/loongson1/common/platform.c|  124 
 arch/mips/loongson1/common/prom.c|   87 
 arch/mips/loongson1/common/reset.c   |   45 ++
 arch/mips/loongson1/common/setup.c   |   29 
 arch/mips/loongson1/ls1b/board.c |   33 +
 14 files changed, 874 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/war.h
 create mode 100644 arch/mips/loongson1/common/clock.c
 create mode 100644 arch/mips/loongson1/common/irq.c
 create mode 100644 arch/mips/loongson1/common/platform.c
 create mode 100644 arch/mips/loongson1/common/prom.c
 create mode 100644 arch/mips/loongson1/common/reset.c
 create mode 100644 arch/mips/loongson1/common/setup.c
 create mode 100644 arch/mips/loongson1/ls1b/board.c

diff --git a/arch/mips/include/asm/mach-loongson1/irq.h 
b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 000..ccc42cc
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang 
+ *
+ * IRQ mappings for Loongson1.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_IRQ_H
+#define __ASM_MACH_LOONGSON1_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE  0
+#define MIPS_CPU_IRQ(x)(MIPS_CPU_IRQ_BASE + (x))
+
+#define SOFTINT0_IRQ   MIPS_CPU_IRQ(0)
+#define SOFTINT1_IRQ   MIPS_CPU_IRQ(1)
+#define INT0_IRQ   MIPS_CPU_IRQ(2)
+#define INT1_IRQ   MIPS_CPU_IRQ(3)
+#define INT2_IRQ   MIPS_CPU_IRQ(4)
+#define INT3_IRQ   MIPS_CPU_IRQ(5)
+#define INT4_IRQ   MIPS_CPU_IRQ(6)
+#define TIMER_IRQ  MIPS_CPU_IRQ(7) /* cpu timer */
+
+#define MIPS_CPU_IRQS  (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
+
+/*
+ * INT0~3 Interrupt Numbers
+ */
+#define LS1X_IRQ_BASE  MIPS_CPU_IRQS
+#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
+
+#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
+#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
+#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
+#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
+#define LS1X_CAN0_IRQ  LS1X_IRQ(0, 6)
+#define LS1X_CAN1_IRQ  LS1X_IRQ(0, 7)
+#define LS1X_SPI0_IRQ  LS1X_IRQ(0, 8)
+#define LS1X_SPI1_IRQ  LS1X_IRQ(0, 9)
+#define LS1X_AC97_IRQ  LS1X_IRQ(0, 10)
+#define LS1X_DMA0_IRQ  LS1X_IRQ(0, 13)
+#define LS1X_DMA1_IRQ  LS1X_IRQ(0, 14)
+#define LS1X_DMA2_IRQ  LS1X_IRQ(0, 15)
+#define LS1X_PWM0_IRQ  LS1X_IRQ(0, 17)
+#define LS1X_PWM1_IRQ  LS1X_IRQ(0, 18)
+#define LS1X_PWM2_IRQ  LS1X_IRQ(0, 19)
+#define LS1X_PWM3_IRQ  LS1X_IRQ(0, 20)
+#define LS1X_RTC_INT0_IRQ  LS1X_IRQ(0, 21)
+#define LS1X_RTC_INT1_IRQ  LS1X_IRQ(0, 22)
+#define LS1X_RTC_IN

[PATCH V7 2/4] MIPS: Add board support for Loongson1B

2012-07-07 Thread Kelvin Cheung

This patch adds basic platform devices for Loongson1B,
including serial port, ethernet, usb, rtc and interrupt handler.

Loongson1B UART is compatible with NS16550A.
Loongson1B GMAC is built around Synopsys IP Core.

Use normal descriptor instead of enhanced descriptor.
Thanks to Giuseppe for updating the normal descriptor
in stmmac driver.

Thanks to Zhao Zhang for implementing the RTC driver.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com

---
V7(updated):
1.Remove 'ifdef' of platform devices. (Asked by Ralf)
2.Modify plat_stmmacenet_data accordingly due to the change
  of upstream.
---
 arch/mips/include/asm/mach-loongson1/irq.h   |   73 ++
 arch/mips/include/asm/mach-loongson1/loongson1.h |   44 ++
 arch/mips/include/asm/mach-loongson1/platform.h  |   23 +++
 arch/mips/include/asm/mach-loongson1/prom.h  |   24 +++
 arch/mips/include/asm/mach-loongson1/regs-clk.h  |   33 +
 arch/mips/include/asm/mach-loongson1/regs-wdt.h  |   22 +++
 arch/mips/include/asm/mach-loongson1/war.h   |   25 
 arch/mips/loongson1/common/clock.c   |  165 ++
 arch/mips/loongson1/common/irq.c |  147 +++
 arch/mips/loongson1/common/platform.c|  124 
 arch/mips/loongson1/common/prom.c|   87 
 arch/mips/loongson1/common/reset.c   |   45 ++
 arch/mips/loongson1/common/setup.c   |   29 
 arch/mips/loongson1/ls1b/board.c |   33 +
 14 files changed, 874 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-loongson1/irq.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/loongson1.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/platform.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/prom.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/regs-clk.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/regs-wdt.h
 create mode 100644 arch/mips/include/asm/mach-loongson1/war.h
 create mode 100644 arch/mips/loongson1/common/clock.c
 create mode 100644 arch/mips/loongson1/common/irq.c
 create mode 100644 arch/mips/loongson1/common/platform.c
 create mode 100644 arch/mips/loongson1/common/prom.c
 create mode 100644 arch/mips/loongson1/common/reset.c
 create mode 100644 arch/mips/loongson1/common/setup.c
 create mode 100644 arch/mips/loongson1/ls1b/board.c

diff --git a/arch/mips/include/asm/mach-loongson1/irq.h 
b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 000..ccc42cc
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang keguang.zh...@gmail.com
+ *
+ * IRQ mappings for Loongson1.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_IRQ_H
+#define __ASM_MACH_LOONGSON1_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE  0
+#define MIPS_CPU_IRQ(x)(MIPS_CPU_IRQ_BASE + (x))
+
+#define SOFTINT0_IRQ   MIPS_CPU_IRQ(0)
+#define SOFTINT1_IRQ   MIPS_CPU_IRQ(1)
+#define INT0_IRQ   MIPS_CPU_IRQ(2)
+#define INT1_IRQ   MIPS_CPU_IRQ(3)
+#define INT2_IRQ   MIPS_CPU_IRQ(4)
+#define INT3_IRQ   MIPS_CPU_IRQ(5)
+#define INT4_IRQ   MIPS_CPU_IRQ(6)
+#define TIMER_IRQ  MIPS_CPU_IRQ(7) /* cpu timer */
+
+#define MIPS_CPU_IRQS  (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
+
+/*
+ * INT0~3 Interrupt Numbers
+ */
+#define LS1X_IRQ_BASE  MIPS_CPU_IRQS
+#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n  5) + (x))
+
+#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
+#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
+#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
+#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
+#define LS1X_CAN0_IRQ  LS1X_IRQ(0, 6)
+#define LS1X_CAN1_IRQ  LS1X_IRQ(0, 7)
+#define LS1X_SPI0_IRQ  LS1X_IRQ(0, 8)
+#define LS1X_SPI1_IRQ  LS1X_IRQ(0, 9)
+#define LS1X_AC97_IRQ  LS1X_IRQ(0, 10)
+#define LS1X_DMA0_IRQ  LS1X_IRQ(0, 13)
+#define LS1X_DMA1_IRQ  LS1X_IRQ(0, 14)
+#define LS1X_DMA2_IRQ  LS1X_IRQ(0, 15)
+#define LS1X_PWM0_IRQ  LS1X_IRQ(0, 17)
+#define LS1X_PWM1_IRQ  LS1X_IRQ(0, 18)
+#define LS1X_PWM2_IRQ  LS1X_IRQ(0, 19)
+#define LS1X_PWM3_IRQ  LS1X_IRQ(0, 20)
+#define LS1X_RTC_INT0_IRQ  LS1X_IRQ(0, 21)
+#define LS1X_RTC_INT1_IRQ

[PATCH V7 3/4] MIPS: Add Makefile and Kconfig for Loongson1B

2012-07-07 Thread Kelvin Cheung

This patch adds Makefile and Kconfig related to Loongson1B.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com

---
V7(updated):
Change the load address of kernel to 0x8010.
---
 arch/mips/Kbuild.platforms  |1 +
 arch/mips/Kconfig   |   31 +++
 arch/mips/loongson1/Kconfig |   21 +
 arch/mips/loongson1/Makefile|   11 +++
 arch/mips/loongson1/Platform|7 +++
 arch/mips/loongson1/common/Makefile |5 +
 arch/mips/loongson1/ls1b/Makefile   |5 +
 7 files changed, 81 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/loongson1/Kconfig
 create mode 100644 arch/mips/loongson1/Makefile
 create mode 100644 arch/mips/loongson1/Platform
 create mode 100644 arch/mips/loongson1/common/Makefile
 create mode 100644 arch/mips/loongson1/ls1b/Makefile

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5ce8029..d64786d 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -14,6 +14,7 @@ platforms += jz4740
 platforms += lantiq
 platforms += lasat
 platforms += loongson
+platforms += loongson1
 platforms += mipssim
 platforms += mti-malta
 platforms += netlogic
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 08dfc79..61e1459 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -265,6 +265,17 @@ config MACH_LOONGSON
  Chinese Academy of Sciences (CAS) in the People's Republic
  of China. The chief architect is Professor Weiwu Hu.
 
+config MACH_LOONGSON1
+   bool Loongson1 family of machines
+   select SYS_SUPPORTS_ZBOOT
+   help
+ This enables the support of Loongson1 family of machines.
+
+ Loongson1 is a family of 32-bit MIPS-compatible SoCs.
+ developed at Institute of Computing Technology (ICT),
+ Chinese Academy of Sciences (CAS) in the People's Republic
+ of China.
+
 config MIPS_MALTA
bool MIPS Malta board
select ARCH_MAY_HAVE_PC_FDC
@@ -838,6 +849,7 @@ source arch/mips/txx9/Kconfig
 source arch/mips/vr41xx/Kconfig
 source arch/mips/cavium-octeon/Kconfig
 source arch/mips/loongson/Kconfig
+source arch/mips/loongson1/Kconfig
 source arch/mips/netlogic/Kconfig
 
 endmenu
@@ -1219,6 +1231,14 @@ config CPU_LOONGSON2F
  have a similar programming interface with FPGA northbridge used in
  Loongson2E.
 
+config CPU_LOONGSON1B
+   bool Loongson 1B
+   depends on SYS_HAS_CPU_LOONGSON1B
+   select CPU_LOONGSON1
+   help
+ The Loongson 1B is a 32-bit SoC, which implements the MIPS32
+ release 2 instruction set.
+
 config CPU_MIPS32_R1
bool MIPS32 Release 1
depends on SYS_HAS_CPU_MIPS32_R1
@@ -1548,6 +1568,14 @@ config CPU_LOONGSON2
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
 
+config CPU_LOONGSON1
+   bool
+   select CPU_MIPS32
+   select CPU_MIPSR2
+   select CPU_HAS_PREFETCH
+   select CPU_SUPPORTS_32BIT_KERNEL
+   select CPU_SUPPORTS_HIGHMEM
+
 config CPU_BMIPS
bool
select CPU_MIPS32
@@ -1566,6 +1594,9 @@ config SYS_HAS_CPU_LOONGSON2F
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
select CPU_SUPPORTS_UNCACHED_ACCELERATED
 
+config SYS_HAS_CPU_LOONGSON1B
+   bool
+
 config SYS_HAS_CPU_MIPS32_R1
bool
 
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
new file mode 100644
index 000..237fa21
--- /dev/null
+++ b/arch/mips/loongson1/Kconfig
@@ -0,0 +1,21 @@
+if MACH_LOONGSON1
+
+choice
+   prompt Machine Type
+
+config LOONGSON1_LS1B
+   bool Loongson LS1B board
+   select CEVT_R4K
+   select CSRC_R4K
+   select SYS_HAS_CPU_LOONGSON1B
+   select DMA_NONCOHERENT
+   select BOOT_ELF32
+   select IRQ_CPU
+   select SYS_SUPPORTS_32BIT_KERNEL
+   select SYS_SUPPORTS_LITTLE_ENDIAN
+   select SYS_SUPPORTS_HIGHMEM
+   select SYS_HAS_EARLY_PRINTK
+
+endchoice
+
+endif # MACH_LOONGSON1
diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile
new file mode 100644
index 000..e9123c2
--- /dev/null
+++ b/arch/mips/loongson1/Makefile
@@ -0,0 +1,11 @@
+#
+# Common code for all Loongson1 based systems
+#
+
+obj-$(CONFIG_MACH_LOONGSON1) += common/
+
+#
+# Loongson LS1B board
+#
+
+obj-$(CONFIG_LOONGSON1_LS1B)  += ls1b/
diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform
new file mode 100644
index 000..99bdefe
--- /dev/null
+++ b/arch/mips/loongson1/Platform
@@ -0,0 +1,7 @@
+cflags-$(CONFIG_CPU_LOONGSON1)  += \
+   $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA 
-D_MIPS_ISA=_MIPS_ISA_MIPS32) \
+   -Wa,-mips32r2 -Wa,--trap
+
+platform-$(CONFIG_MACH_LOONGSON1)  += loongson1/
+cflags-$(CONFIG_MACH_LOONGSON1)+= 
-I$(srctree)/arch/mips/include/asm/mach-loongson1
+load-$(CONFIG_LOONGSON1_LS1B)  += 0x8010
diff --git a/arch/mips

[PATCH V7 4/4] MIPS: Add defconfig for Loongson1B

2012-07-07 Thread Kelvin Cheung

This patch adds defconfig for Loongson1B.

Signed-off-by: Kelvin Cheung keguang.zh...@gmail.com

---
V7(updated):
Add CONFIG_USB_ANNOUNCE_NEW_DEVICES in default
configuration.
---
 arch/mips/configs/ls1b_defconfig |  109 ++
 1 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/configs/ls1b_defconfig

diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig
new file mode 100644
index 000..80cff8b
--- /dev/null
+++ b/arch/mips/configs/ls1b_defconfig
@@ -0,0 +1,109 @@
+CONFIG_MACH_LOONGSON1=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_EXPERT=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=m
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_DA=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=8
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB_HID=m
+CONFIG_HID_GENERIC=m
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_STORAGE=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_LOONGSON1=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+# CONFIG_EARLY_PRINTK is not set
-- 
1.7.1

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