Re: [PATCH] MAINTAINERS: Change QCOM entries
> On Dec 11, 2015, at 3:46 PM, Andy Gross wrote: > > From: Andy Gross > > This patch changes the email address for Andy Gross and David Brown and drops > Kumar Gala. In addition, it changes the location of the repository. > > Signed-off-by: Andy Gross > Signed-off-by: Andy Gross > — Acked-by: Kumar Gala - k-- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] MAINTAINERS: Change QCOM entries
> On Dec 11, 2015, at 3:46 PM, Andy Gross <andy.gr...@linaro.org> wrote: > > From: Andy Gross <agr...@codeaurora.org> > > This patch changes the email address for Andy Gross and David Brown and drops > Kumar Gala. In addition, it changes the location of the repository. > > Signed-off-by: Andy Gross <andy.gr...@linaro.org> > Signed-off-by: Andy Gross <agr...@codeaurora.org> > — Acked-by: Kumar Gala <ga...@codeaurora.org> - k-- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [GIT PULL] qcom SoC changes for 4.2-1
> On Jun 1, 2015, at 1:35 PM, Arnd Bergmann wrote: > > On Friday 29 May 2015 14:42:01 Arnd Bergmann wrote: >> On Thursday 28 May 2015 10:55:39 Kumar Gala wrote: >>> Qualcomm ARM Based SoC Updates for v4.2-1 >>> >>> * Added Subsystem Power Manager (SPM) driver >>> * Split out 32-bit specific SCM code >>> * Added HDCP SCM call >>> >>> >> >> Pulled into next/drivers, thanks! >> > > I've had to apply this patch on top of our for-next branch to make it > build for randconfig. > > Can you check that this makes sense? > > Arnd The QCOM_SCM makes sense, Lina can comment on the ARM_CPU_SUSPEND bit, but seems reasonable to me. - k > > diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig > index 5eea374c8fa6..01aa2fd3514d 100644 > --- a/drivers/soc/qcom/Kconfig > +++ b/drivers/soc/qcom/Kconfig > @@ -13,6 +13,8 @@ config QCOM_GSBI > config QCOM_PM > bool "Qualcomm Power Management" > depends on ARCH_QCOM && !ARM64 > + select QCOM_SCM > + select ARM_CPU_SUSPEND > help > QCOM Platform specific power driver to manage cores and L2 low power > modes. It interface with various system drivers to put the cores in > > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [GIT PULL] qcom SoC changes for 4.2-1
On Jun 1, 2015, at 1:35 PM, Arnd Bergmann a...@arndb.de wrote: On Friday 29 May 2015 14:42:01 Arnd Bergmann wrote: On Thursday 28 May 2015 10:55:39 Kumar Gala wrote: Qualcomm ARM Based SoC Updates for v4.2-1 * Added Subsystem Power Manager (SPM) driver * Split out 32-bit specific SCM code * Added HDCP SCM call Pulled into next/drivers, thanks! I've had to apply this patch on top of our for-next branch to make it build for randconfig. Can you check that this makes sense? Arnd The QCOM_SCM makes sense, Lina can comment on the ARM_CPU_SUSPEND bit, but seems reasonable to me. - k diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 5eea374c8fa6..01aa2fd3514d 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -13,6 +13,8 @@ config QCOM_GSBI config QCOM_PM bool Qualcomm Power Management depends on ARCH_QCOM !ARM64 + select QCOM_SCM + select ARM_CPU_SUSPEND help QCOM Platform specific power driver to manage cores and L2 low power modes. It interface with various system drivers to put the cores in -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64 SoCs. This
is used by things like determine if we have HDCP support or not on the
system.
Signed-off-by: Kumar Gala
---
* v6:
- Added comment about HDCP usage
- Folded in HDCP SCM call
- implement boot interfaces as -EINVAL
* v5:
- use common error defines from qcom_scm.h
- removed R*_STR defines
* v4:
- Folded in change to qcom_scm_cpu_power_down to remove HOTPLUG flag
from Lina.
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 406 +
3 files changed, 411 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 4269dba..8878800 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -190,6 +190,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool "Qualcomm Platforms"
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..90e0fa3
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,406 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "qcom_scm.h"
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) & 0xFF) << 8) | ((c) & 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) & 0xff) << 4) | \
+ (((b) & 0xff) << 6) | \
+ (((c) & 0xff) << 8) | \
+ (((d) & 0xff) << 10) | \
+ (((e) & 0xff) << 12) | \
+ (((f) & 0xff) << 14) | \
+ (((g) & 0xff) << 16) | \
+ (((h) & 0xff) << 18) | \
+ (((i) & 0xff) << 20) | \
+ (((j) & 0xff) << 22) | \
+ (num & 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+ return -EIO;
+ case QCOM_SCM_EINVAL_ADDR:
+ case QCOM_SCM_EINVAL_ARG:
+
Re: [GIT PULL] qcom SoC changes for 4.2-1
(Updated to pull in one long standing SCM change to add HDCP support) The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-soc-for-4.2-1 for you to fetch changes up to 9626b6993b2e6faf047d2d96958e8474edc9c7a5: firmware: qcom: scm: Add HDCP Support (2015-05-28 10:47:45 -0500) Qualcomm ARM Based SoC Updates for v4.2-1 * Added Subsystem Power Manager (SPM) driver * Split out 32-bit specific SCM code * Added HDCP SCM call Kumar Gala (1): firmware: qcom: scm: Split out 32-bit specific SCM code Lina Iyer (1): ARM: qcom: Add Subsystem Power Manager (SPM) driver jilai wang (1): firmware: qcom: scm: Add HDCP Support drivers/firmware/Makefile | 3 +- drivers/firmware/qcom_scm-32.c | 503 + drivers/firmware/qcom_scm.c| 474 -- drivers/firmware/qcom_scm.h| 47 drivers/soc/qcom/Kconfig | 7 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/spm.c | 385 +++ include/linux/qcom_scm.h | 13 +- 8 files changed, 995 insertions(+), 438 deletions(-) create mode 100644 drivers/firmware/qcom_scm-32.c create mode 100644 drivers/firmware/qcom_scm.h create mode 100644 drivers/soc/qcom/spm.c -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [GIT PULL] qcom SoC changes for 4.2-1
(Updated to pull in one long standing SCM change to add HDCP support) The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-soc-for-4.2-1 for you to fetch changes up to 9626b6993b2e6faf047d2d96958e8474edc9c7a5: firmware: qcom: scm: Add HDCP Support (2015-05-28 10:47:45 -0500) Qualcomm ARM Based SoC Updates for v4.2-1 * Added Subsystem Power Manager (SPM) driver * Split out 32-bit specific SCM code * Added HDCP SCM call Kumar Gala (1): firmware: qcom: scm: Split out 32-bit specific SCM code Lina Iyer (1): ARM: qcom: Add Subsystem Power Manager (SPM) driver jilai wang (1): firmware: qcom: scm: Add HDCP Support drivers/firmware/Makefile | 3 +- drivers/firmware/qcom_scm-32.c | 503 + drivers/firmware/qcom_scm.c| 474 -- drivers/firmware/qcom_scm.h| 47 drivers/soc/qcom/Kconfig | 7 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/spm.c | 385 +++ include/linux/qcom_scm.h | 13 +- 8 files changed, 995 insertions(+), 438 deletions(-) create mode 100644 drivers/firmware/qcom_scm-32.c create mode 100644 drivers/firmware/qcom_scm.h create mode 100644 drivers/soc/qcom/spm.c -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64 SoCs. This
is used by things like determine if we have HDCP support or not on the
system.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
* v6:
- Added comment about HDCP usage
- Folded in HDCP SCM call
- implement boot interfaces as -EINVAL
* v5:
- use common error defines from qcom_scm.h
- removed R*_STR defines
* v4:
- Folded in change to qcom_scm_cpu_power_down to remove HOTPLUG flag
from Lina.
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 406 +
3 files changed, 411 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 4269dba..8878800 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -190,6 +190,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool Qualcomm Platforms
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..90e0fa3
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,406 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include linux/cpumask.h
+#include linux/delay.h
+#include linux/mutex.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/qcom_scm.h
+
+#include asm/cacheflush.h
+#include asm/compiler.h
+#include asm/smp_plat.h
+
+#include qcom_scm.h
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) 0xFF) 8) | ((c) 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) 0xff) 4) | \
+ (((b) 0xff) 6) | \
+ (((c) 0xff) 8) | \
+ (((d) 0xff) 10) | \
+ (((e) 0xff) 12) | \
+ (((f) 0xff) 14) | \
+ (((g) 0xff) 16) | \
+ (((h) 0xff) 18) | \
+ (((i) 0xff) 20) | \
+ (((j) 0xff) 22) | \
+ (num 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+ return -EIO;
+ case QCOM_SCM_EINVAL_ADDR:
+ case QCOM_SCM_EINVAL_ARG:
+ return -EINVAL;
+ case
[GIT PULL] qcom SoC changes for 4.2
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-soc-for-4.2 for you to fetch changes up to b6a1dfbc7d57409accf213e78db7b059c206be9e: firmware: qcom: scm: Split out 32-bit specific SCM code (2015-04-28 14:20:40 -0500) Qualcomm ARM Based SoC Updates for v4.2 * Added Subsystem Power Manager (SPM) driver * Split out 32-bit specific SCM code Kumar Gala (1): firmware: qcom: scm: Split out 32-bit specific SCM code Lina Iyer (1): ARM: qcom: Add Subsystem Power Manager (SPM) driver drivers/firmware/Makefile | 3 +- drivers/firmware/qcom_scm-32.c | 480 + drivers/firmware/qcom_scm.c| 442 + drivers/firmware/qcom_scm.h| 38 drivers/soc/qcom/Kconfig | 7 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/spm.c | 385 + 7 files changed, 920 insertions(+), 436 deletions(-) create mode 100644 drivers/firmware/qcom_scm-32.c create mode 100644 drivers/firmware/qcom_scm.h create mode 100644 drivers/soc/qcom/spm.c -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom defconfig changes for 4.2
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-defconfig-for-4.2 for you to fetch changes up to e3db12b94ed4e70b7f8703a0c7396d6b9028b58a: ARM: config: multi_v7: Update to enable cpuidle for QCOM SoCs (2015-04-28 14:29:09 -0500) Qualcomm ARM Based defconfig Updates for v4.2 * Enable cpuidle for QCOM SoCs in qcom & multi_v7_defconfig Lina Iyer (2): ARM: config: Update qcom_defconfig to enable cpuidle ARM: config: multi_v7: Update to enable cpuidle for QCOM SoCs arch/arm/configs/multi_v7_defconfig | 2 ++ arch/arm/configs/qcom_defconfig | 2 ++ 2 files changed, 4 insertions(+) -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom arm64 dt changes for 4.2
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-arm64-for-4.2 for you to fetch changes up to a190a1ce9a51d3edd52de1b721276d780e0906bb: arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC board (2015-04-27 16:09:12 -0500) Qualcomm ARM64 Updates for v4.2 * Added SPMI PMIC Arbiter device tree node for MSM8916 * Added 8x16 chipset SPMI PMIC's nodes * Added MSM8916 restart device node * Added initial set of PMIC and SoC pins for APQ8016 SBC board Ivan T. Ivanov (4): arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916 arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes arm64: dts: qcom: Add MSM8916 restart device node arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC board .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 30 +++ arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 21 + arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 3 + arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 25 +- arch/arm64/boot/dts/qcom/pm8916.dtsi | 99 ++ 6 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom dt changes for 4.2
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-dt-for-4.2 for you to fetch changes up to b73b31577f70a1d03aee21d0127da44862b7b08e: ARM: dts: qcom: Add msm8660 PMU node (2015-04-27 16:15:28 -0500) Qualcomm ARM Based Device Tree Updates for v4.2 * Added support for regulators, USB Host & OTG, SATA, and i2c controllers on APQ8064 based platforms * Added PM8841/PM8941/PMA8084 device nodes * Added PMU support on MSM8660 Ivan T. Ivanov (3): ARM: dts: qcom: Add PM8841 functions device nodes ARM: dts: qcom: Add PM8941 functions device nodes ARM: dts: qcom: Add PMA8084 functions device nodes Nicolas Dechesne (2): ARM: dts: qcom: apq8064 - Add usb host support to CM QS-600 ARM: dts: qcom: apq8064 - Add USB OTG support for CM QS-600 Pramod Gurav (1): ARM: dts: qcom: apq8064-ifc6410 - Add DT alias for serial port Srinivas Kandagatla (8): ARM: dts: qcom: apq8064 - add RPM regulators support ARM: dts: qcom: apq8064-ifc6410 - Add basic regulators ARM: dts: qcom: apq8064 - Add usb host support. ARM: dts: qcom: apq8064 - Add USB OTG support ARM: dts: qcom: apq8064 - Add SATA controller support ARM: dts: qcom: apq8064-cm-qs600 - Add basic regulators ARM: dts: qcom: apq8064 - Move i2c1 pinctrl to apq8064.dtsi ARM: dts: qcom: apq8064 - add i2c3 node for panel. Stephen Boyd (1): ARM: dts: qcom: Add msm8660 PMU node arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 100 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 136 +++-- arch/arm/boot/dts/qcom-apq8064.dtsi | 175 +++- arch/arm/boot/dts/qcom-msm8660.dtsi | 5 + arch/arm/boot/dts/qcom-pm8841.dtsi | 18 +++ arch/arm/boot/dts/qcom-pm8941.dtsi | 133 - arch/arm/boot/dts/qcom-pma8084.dtsi | 92 +++ 7 files changed, 649 insertions(+), 10 deletions(-) -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom defconfig changes for 4.2
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-defconfig-for-4.2 for you to fetch changes up to e3db12b94ed4e70b7f8703a0c7396d6b9028b58a: ARM: config: multi_v7: Update to enable cpuidle for QCOM SoCs (2015-04-28 14:29:09 -0500) Qualcomm ARM Based defconfig Updates for v4.2 * Enable cpuidle for QCOM SoCs in qcom multi_v7_defconfig Lina Iyer (2): ARM: config: Update qcom_defconfig to enable cpuidle ARM: config: multi_v7: Update to enable cpuidle for QCOM SoCs arch/arm/configs/multi_v7_defconfig | 2 ++ arch/arm/configs/qcom_defconfig | 2 ++ 2 files changed, 4 insertions(+) -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom SoC changes for 4.2
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-soc-for-4.2 for you to fetch changes up to b6a1dfbc7d57409accf213e78db7b059c206be9e: firmware: qcom: scm: Split out 32-bit specific SCM code (2015-04-28 14:20:40 -0500) Qualcomm ARM Based SoC Updates for v4.2 * Added Subsystem Power Manager (SPM) driver * Split out 32-bit specific SCM code Kumar Gala (1): firmware: qcom: scm: Split out 32-bit specific SCM code Lina Iyer (1): ARM: qcom: Add Subsystem Power Manager (SPM) driver drivers/firmware/Makefile | 3 +- drivers/firmware/qcom_scm-32.c | 480 + drivers/firmware/qcom_scm.c| 442 + drivers/firmware/qcom_scm.h| 38 drivers/soc/qcom/Kconfig | 7 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/spm.c | 385 + 7 files changed, 920 insertions(+), 436 deletions(-) create mode 100644 drivers/firmware/qcom_scm-32.c create mode 100644 drivers/firmware/qcom_scm.h create mode 100644 drivers/soc/qcom/spm.c -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom dt changes for 4.2
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-dt-for-4.2 for you to fetch changes up to b73b31577f70a1d03aee21d0127da44862b7b08e: ARM: dts: qcom: Add msm8660 PMU node (2015-04-27 16:15:28 -0500) Qualcomm ARM Based Device Tree Updates for v4.2 * Added support for regulators, USB Host OTG, SATA, and i2c controllers on APQ8064 based platforms * Added PM8841/PM8941/PMA8084 device nodes * Added PMU support on MSM8660 Ivan T. Ivanov (3): ARM: dts: qcom: Add PM8841 functions device nodes ARM: dts: qcom: Add PM8941 functions device nodes ARM: dts: qcom: Add PMA8084 functions device nodes Nicolas Dechesne (2): ARM: dts: qcom: apq8064 - Add usb host support to CM QS-600 ARM: dts: qcom: apq8064 - Add USB OTG support for CM QS-600 Pramod Gurav (1): ARM: dts: qcom: apq8064-ifc6410 - Add DT alias for serial port Srinivas Kandagatla (8): ARM: dts: qcom: apq8064 - add RPM regulators support ARM: dts: qcom: apq8064-ifc6410 - Add basic regulators ARM: dts: qcom: apq8064 - Add usb host support. ARM: dts: qcom: apq8064 - Add USB OTG support ARM: dts: qcom: apq8064 - Add SATA controller support ARM: dts: qcom: apq8064-cm-qs600 - Add basic regulators ARM: dts: qcom: apq8064 - Move i2c1 pinctrl to apq8064.dtsi ARM: dts: qcom: apq8064 - add i2c3 node for panel. Stephen Boyd (1): ARM: dts: qcom: Add msm8660 PMU node arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 100 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 136 +++-- arch/arm/boot/dts/qcom-apq8064.dtsi | 175 +++- arch/arm/boot/dts/qcom-msm8660.dtsi | 5 + arch/arm/boot/dts/qcom-pm8841.dtsi | 18 +++ arch/arm/boot/dts/qcom-pm8941.dtsi | 133 - arch/arm/boot/dts/qcom-pma8084.dtsi | 92 +++ 7 files changed, 649 insertions(+), 10 deletions(-) -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom arm64 dt changes for 4.2
The following changes since commit b787f68c36d49bb1d9236f403813641efa74a031: Linux 4.1-rc1 (2015-04-26 17:59:10 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-arm64-for-4.2 for you to fetch changes up to a190a1ce9a51d3edd52de1b721276d780e0906bb: arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC board (2015-04-27 16:09:12 -0500) Qualcomm ARM64 Updates for v4.2 * Added SPMI PMIC Arbiter device tree node for MSM8916 * Added 8x16 chipset SPMI PMIC's nodes * Added MSM8916 restart device node * Added initial set of PMIC and SoC pins for APQ8016 SBC board Ivan T. Ivanov (4): arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916 arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes arm64: dts: qcom: Add MSM8916 restart device node arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC board .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 30 +++ arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 21 + arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 3 + arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 25 +- arch/arm64/boot/dts/qcom/pm8916.dtsi | 99 ++ 6 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components
> On May 11, 2015, at 2:21 PM, Mathieu Poirier
> wrote:
>
> On 11 May 2015 at 02:31, Ivan T. Ivanov wrote:
>> Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
>>
>> Signed-off-by: Ivan T. Ivanov
>> ---
>>
>> Changes since v2 [1]:
>> * Added "1x" to "qcom,coresight-replicator" compatible string, to match what
>> devicetree bindings documentations says.
>>
>> [1] http://www.spinics.net/lists/devicetree/msg77768.html
>>
>> arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi | 254
>>
>> 1 file changed, 254 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
>> b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
>> new file mode 100644
>> index 000..900f1f4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
>> @@ -0,0 +1,254 @@
>> +/*
>> + * Copyright (c) 2013 - 2015, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> + {
>> +
>> + tpiu@82 {
>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>> + reg = <0x82 0x1000>;
>> +
>> + clocks = < RPM_QDSS_CLK>, < RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + port {
>> + tpiu_in: endpoint {
>> + slave-mode;
>> + remote-endpoint = <_out1>;
>> + };
>> + };
>> + };
>> +
>> + funnel@821000 {
>> + compatible = "arm,coresight-funnel", "arm,primecell";
>> + reg = <0x821000 0x1000>;
>> +
>> + clocks = < RPM_QDSS_CLK>, < RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /*
>> +* Not described input ports:
>> +* 0 - connected to Resource and Power Manger CPU ETM
>> +* 1 - not-connected
>> +* 2 - connected to Modem CPU ETM
>> +* 3 - not-connected
>> +* 5 - not-connected
>> +* 6 - connected trought funnel to Wireless CPU ETM
>> +* 7 - connected to STM component
>> +*/
>> + port@4 {
>> + reg = <4>;
>> + funnel0_in4: endpoint {
>> + slave-mode;
>> + remote-endpoint = <_out>;
>> + };
>> + };
>> + port@8 {
>> + reg = <0>;
>> + funnel0_out: endpoint {
>> + remote-endpoint = <_in>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + replicator@824000 {
>> + compatible = "qcom,coresight-replicator1x", "arm,primecell";
>> + reg = <0x824000 0x1000>;
>> +
>> + clocks = < RPM_QDSS_CLK>, < RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + replicator_out0: endpoint {
>> + remote-endpoint = <_in>;
>> + };
>> + };
>> + port@1 {
>> + reg = <1>;
>> + replicator_out1: endpoint {
>> + remote-endpoint = <_in>;
>> + };
>> + };
>> + port@2 {
>> + reg = <0>;
>> + replicator_in: endpoint {
>> + slave-mode;
>> + remote-endpoint = <_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> +
Re: [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components
On May 11, 2015, at 2:21 PM, Mathieu Poirier mathieu.poir...@linaro.org
wrote:
On 11 May 2015 at 02:31, Ivan T. Ivanov ivan.iva...@linaro.org wrote:
Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
Changes since v2 [1]:
* Added 1x to qcom,coresight-replicator compatible string, to match what
devicetree bindings documentations says.
[1] http://www.spinics.net/lists/devicetree/msg77768.html
arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi | 254
1 file changed, 254 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
diff --git a/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
new file mode 100644
index 000..900f1f4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2013 - 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+soc {
+
+ tpiu@82 {
+ compatible = arm,coresight-tpiu, arm,primecell;
+ reg = 0x82 0x1000;
+
+ clocks = rpmcc RPM_QDSS_CLK, rpmcc RPM_QDSS_A_CLK;
+ clock-names = apb_pclk, atclk;
+
+ port {
+ tpiu_in: endpoint {
+ slave-mode;
+ remote-endpoint = replicator_out1;
+ };
+ };
+ };
+
+ funnel@821000 {
+ compatible = arm,coresight-funnel, arm,primecell;
+ reg = 0x821000 0x1000;
+
+ clocks = rpmcc RPM_QDSS_CLK, rpmcc RPM_QDSS_A_CLK;
+ clock-names = apb_pclk, atclk;
+
+ ports {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ /*
+* Not described input ports:
+* 0 - connected to Resource and Power Manger CPU ETM
+* 1 - not-connected
+* 2 - connected to Modem CPU ETM
+* 3 - not-connected
+* 5 - not-connected
+* 6 - connected trought funnel to Wireless CPU ETM
+* 7 - connected to STM component
+*/
+ port@4 {
+ reg = 4;
+ funnel0_in4: endpoint {
+ slave-mode;
+ remote-endpoint = funnel1_out;
+ };
+ };
+ port@8 {
+ reg = 0;
+ funnel0_out: endpoint {
+ remote-endpoint = etf_in;
+ };
+ };
+ };
+ };
+
+ replicator@824000 {
+ compatible = qcom,coresight-replicator1x, arm,primecell;
+ reg = 0x824000 0x1000;
+
+ clocks = rpmcc RPM_QDSS_CLK, rpmcc RPM_QDSS_A_CLK;
+ clock-names = apb_pclk, atclk;
+
+ ports {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ port@0 {
+ reg = 0;
+ replicator_out0: endpoint {
+ remote-endpoint = etr_in;
+ };
+ };
+ port@1 {
+ reg = 1;
+ replicator_out1: endpoint {
+ remote-endpoint = tpiu_in;
+ };
+ };
+ port@2 {
+ reg = 0;
+ replicator_in: endpoint {
+ slave-mode;
+ remote-endpoint = etf_out;
+ };
+ };
+ };
+ };
+
+ etf@825000 {
+ compatible = arm,coresight-tmc, arm,primecell;
+ reg = 0x825000 0x1000;
+
+ clocks = rpmcc RPM_QDSS_CLK, rpmcc RPM_QDSS_A_CLK;
+
Re: [PATCH v5 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
> On Apr 29, 2015, at 11:38 AM, Mark Rutland wrote:
>
> On Wed, Apr 29, 2015 at 05:18:04PM +0100, Kumar Gala wrote:
>>
>>> On Apr 29, 2015, at 10:42 AM, Mark Rutland wrote:
>>>
>>> Hi Kumar,
>>>
>>> On Tue, Apr 28, 2015 at 08:23:58PM +0100, Kumar Gala wrote:
>>>> Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
>>>
>>> What is the intended use of this on arm64 SoCs?
>>>
>>> Given the negative reaction to the SMP bringup [1] code that seems to be
>>> the only user, I'm somewhat confused as to why this is being pushed as a
>>> non-RFC in the mean time.
>>>
>>> Are there other users of this interface code? If so, could you please
>>> mention that in the commit message. I'd also ask that you would Cc me on
>>> future postings of this series.
>>>
>>> […]
>>
>> The SCM interface is needed for other things like display:
>>
>> https://patchwork.kernel.org/patch/6198691/
>
> Thanks for the link. It would be good if you could mention some users in
> the commit message.
I’ll update the commit message
>
>>>> +static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int
>>>> flags)
>>>> +{
>>>> + struct qcom_scm_desc desc = {0};
>>>> + unsigned int cpu = cpumask_first(cpus);
>>>> + u64 mpidr_el1 = cpu_logical_map(cpu);
>>>> +
>>>> + /* For now we assume only a single cpu is set in the mask */
>>>> + WARN_ON(cpumask_weight(cpus) != 1);
>>>> +
>>>> + if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
>>>> + pr_err("CPU%d:Failed to set boot address\n", cpu);
>>>> + return -ENOSYS;
>>>> + }
>>>> +
>>>> + desc.args[0] = virt_to_phys(entry);
>>>> + desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
>>>> + desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
>>>> + desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
>>>> + desc.args[4] = ~0ULL;
>>>> + desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
>>>> + desc.arginfo = QCOM_SCM_ARGS(6);
>>>> +
>>>> + return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC,
>>>> );
>>>> +}
>>>> +
>>>> +int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
>>>> +{
>>>> + int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
>>>> +
>>>> + return qcom_scm_set_boot_addr(entry, cpus, flags);
>>>> +}
>>>> +
>>>> +int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
>>>> +{
>>>> + int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
>>>> +
>>>> + return qcom_scm_set_boot_addr(entry, cpus, flags);
>>>> +}
>>>> +
>>>> +void __qcom_scm_cpu_power_down(u32 flags)
>>>> +{
>>>> + struct qcom_scm_desc desc = {0};
>>>> + desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
>>>> + desc.arginfo = QCOM_SCM_ARGS(1);
>>>> +
>>>> + qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
>>>> );
>>>> +}
>>>
>>> As mentioned in the other thread, I don't want to see this for arm64,
>>> and must NAK this portion.
>>
>> I can have these return an error code, but we want to keep the interface the
>> same between the 32-bit and 64-bit.
>
> I don't follow. If nothing calls these on the 64-bit side, then there's
> no interface they need to be there for.
>
> Thanks,
> Mark.
While nothing may call them, its still easier to try and keep the interface the
same between 32 and 64-bit side of things. Its the equivalent of when we have
a CONFIG_ option disabled, but still allow things to build.
- k
--
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a Linux Foundation Collaborative Project
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Re: [PATCH v5 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
> On Apr 29, 2015, at 10:42 AM, Mark Rutland wrote:
>
> Hi Kumar,
>
> On Tue, Apr 28, 2015 at 08:23:58PM +0100, Kumar Gala wrote:
>> Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
>
> What is the intended use of this on arm64 SoCs?
>
> Given the negative reaction to the SMP bringup [1] code that seems to be
> the only user, I'm somewhat confused as to why this is being pushed as a
> non-RFC in the mean time.
>
> Are there other users of this interface code? If so, could you please
> mention that in the commit message. I'd also ask that you would Cc me on
> future postings of this series.
>
> […]
The SCM interface is needed for other things like display:
https://patchwork.kernel.org/patch/6198691/
>
>> +static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int
>> flags)
>> +{
>> + struct qcom_scm_desc desc = {0};
>> + unsigned int cpu = cpumask_first(cpus);
>> + u64 mpidr_el1 = cpu_logical_map(cpu);
>> +
>> + /* For now we assume only a single cpu is set in the mask */
>> + WARN_ON(cpumask_weight(cpus) != 1);
>> +
>> + if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
>> + pr_err("CPU%d:Failed to set boot address\n", cpu);
>> + return -ENOSYS;
>> + }
>> +
>> + desc.args[0] = virt_to_phys(entry);
>> + desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
>> + desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
>> + desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
>> + desc.args[4] = ~0ULL;
>> + desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
>> + desc.arginfo = QCOM_SCM_ARGS(6);
>> +
>> + return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC,
>> );
>> +}
>> +
>> +int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
>> +{
>> + int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
>> +
>> + return qcom_scm_set_boot_addr(entry, cpus, flags);
>> +}
>> +
>> +int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
>> +{
>> + int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
>> +
>> + return qcom_scm_set_boot_addr(entry, cpus, flags);
>> +}
>> +
>> +void __qcom_scm_cpu_power_down(u32 flags)
>> +{
>> + struct qcom_scm_desc desc = {0};
>> + desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
>> + desc.arginfo = QCOM_SCM_ARGS(1);
>> +
>> + qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
>> );
>> +}
>
> As mentioned in the other thread, I don't want to see this for arm64,
> and must NAK this portion.
I can have these return an error code, but we want to keep the interface the
same between the 32-bit and 64-bit.
- k
--
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
On Apr 29, 2015, at 10:42 AM, Mark Rutland mark.rutl...@arm.com wrote:
Hi Kumar,
On Tue, Apr 28, 2015 at 08:23:58PM +0100, Kumar Gala wrote:
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
What is the intended use of this on arm64 SoCs?
Given the negative reaction to the SMP bringup [1] code that seems to be
the only user, I'm somewhat confused as to why this is being pushed as a
non-RFC in the mean time.
Are there other users of this interface code? If so, could you please
mention that in the commit message. I'd also ask that you would Cc me on
future postings of this series.
[…]
The SCM interface is needed for other things like display:
https://patchwork.kernel.org/patch/6198691/
+static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int
flags)
+{
+ struct qcom_scm_desc desc = {0};
+ unsigned int cpu = cpumask_first(cpus);
+ u64 mpidr_el1 = cpu_logical_map(cpu);
+
+ /* For now we assume only a single cpu is set in the mask */
+ WARN_ON(cpumask_weight(cpus) != 1);
+
+ if (mpidr_el1 ~MPIDR_HWID_BITMASK) {
+ pr_err(CPU%d:Failed to set boot address\n, cpu);
+ return -ENOSYS;
+ }
+
+ desc.args[0] = virt_to_phys(entry);
+ desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
+ desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
+ desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
+ desc.args[4] = ~0ULL;
+ desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
+ desc.arginfo = QCOM_SCM_ARGS(6);
+
+ return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC,
desc);
+}
+
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+{
+ int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
+
+ return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+{
+ int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
+
+ return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+void __qcom_scm_cpu_power_down(u32 flags)
+{
+ struct qcom_scm_desc desc = {0};
+ desc.args[0] = flags QCOM_SCM_FLUSH_FLAG_MASK;
+ desc.arginfo = QCOM_SCM_ARGS(1);
+
+ qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
desc);
+}
As mentioned in the other thread, I don't want to see this for arm64,
and must NAK this portion.
I can have these return an error code, but we want to keep the interface the
same between the 32-bit and 64-bit.
- k
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
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Re: [PATCH v5 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
On Apr 29, 2015, at 11:38 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Apr 29, 2015 at 05:18:04PM +0100, Kumar Gala wrote:
On Apr 29, 2015, at 10:42 AM, Mark Rutland mark.rutl...@arm.com wrote:
Hi Kumar,
On Tue, Apr 28, 2015 at 08:23:58PM +0100, Kumar Gala wrote:
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
What is the intended use of this on arm64 SoCs?
Given the negative reaction to the SMP bringup [1] code that seems to be
the only user, I'm somewhat confused as to why this is being pushed as a
non-RFC in the mean time.
Are there other users of this interface code? If so, could you please
mention that in the commit message. I'd also ask that you would Cc me on
future postings of this series.
[…]
The SCM interface is needed for other things like display:
https://patchwork.kernel.org/patch/6198691/
Thanks for the link. It would be good if you could mention some users in
the commit message.
I’ll update the commit message
+static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int
flags)
+{
+ struct qcom_scm_desc desc = {0};
+ unsigned int cpu = cpumask_first(cpus);
+ u64 mpidr_el1 = cpu_logical_map(cpu);
+
+ /* For now we assume only a single cpu is set in the mask */
+ WARN_ON(cpumask_weight(cpus) != 1);
+
+ if (mpidr_el1 ~MPIDR_HWID_BITMASK) {
+ pr_err(CPU%d:Failed to set boot address\n, cpu);
+ return -ENOSYS;
+ }
+
+ desc.args[0] = virt_to_phys(entry);
+ desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
+ desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
+ desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
+ desc.args[4] = ~0ULL;
+ desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
+ desc.arginfo = QCOM_SCM_ARGS(6);
+
+ return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC,
desc);
+}
+
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+{
+ int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
+
+ return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+{
+ int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
+
+ return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+void __qcom_scm_cpu_power_down(u32 flags)
+{
+ struct qcom_scm_desc desc = {0};
+ desc.args[0] = flags QCOM_SCM_FLUSH_FLAG_MASK;
+ desc.arginfo = QCOM_SCM_ARGS(1);
+
+ qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
desc);
+}
As mentioned in the other thread, I don't want to see this for arm64,
and must NAK this portion.
I can have these return an error code, but we want to keep the interface the
same between the 32-bit and 64-bit.
I don't follow. If nothing calls these on the 64-bit side, then there's
no interface they need to be there for.
Thanks,
Mark.
While nothing may call them, its still easier to try and keep the interface the
same between 32 and 64-bit side of things. Its the equivalent of when we have
a CONFIG_ option disabled, but still allow things to build.
- k
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 1/2] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala
---
v5:
Split out error defines in common qcom_scm.h
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c => qcom_scm-32.c} | 22 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 38 +++
4 files changed, 51 insertions(+), 454 deletions(-)
copy drivers/firmware/{qcom_scm.c => qcom_scm-32.c} (95%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 95%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..b08b822 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,13 +27,7 @@
#include
#include
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
+#include "qcom_scm.h"
#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
@@ -386,8 +380,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +404,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +427,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +436,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +464,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +473,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags & QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include
-#include
-#include
-#include
-#include
-#include
+#include
+#include
+#include
#include
-#include
-#include
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU20x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU30x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU00x04
-#define QCOM_SCM_FLAG_WARMBOOT_C
[PATCH v5 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala
Signed-off-by: Lina Iyer
---
* v5:
- use common error defines from qcom_scm.h
- removed R*_STR defines
* v4:
- Folded in change to qcom_scm_cpu_power_down to remove HOTPLUG flag
from Lina.
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 452 +
3 files changed, 457 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 4269dba..8878800 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -190,6 +190,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool "Qualcomm Platforms"
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..a95fd9b
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,452 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "qcom_scm.h"
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) & 0xFF) << 8) | ((c) & 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) & 0xff) << 4) | \
+ (((b) & 0xff) << 6) | \
+ (((c) & 0xff) << 8) | \
+ (((d) & 0xff) << 10) | \
+ (((e) & 0xff) << 12) | \
+ (((f) & 0xff) << 14) | \
+ (((g) & 0xff) << 16) | \
+ (((h) & 0xff) << 18) | \
+ (((i) & 0xff) << 20) | \
+ (((j) & 0xff) << 22) | \
+ (num & 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+ return -EIO;
+ case QCOM_SCM_EINVAL_ADDR:
+ case QCOM_SCM_EINVAL_ARG:
+ return -EINVAL;
+ case QCOM_SCM_EOPNOTSUPP:
+ return -EOPNOTSUPP;
+ case QCOM_SCM_
Re: [PATCH v4 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
> On Apr 28, 2015, at 8:11 AM, Christopher Covington
> wrote:
>
> Hi Kumar,
>
> On 04/27/2015 05:23 PM, Kumar Gala wrote:
>
>> --- /dev/null
>> +++ b/drivers/firmware/qcom_scm-64.c
>> @@ -0,0 +1,465 @@
>> +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
>> + * 02110-1301, USA.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include
>> +#include
>> +#include
>> +
>> +#include "qcom_scm.h"
>> +
>> +#define QCOM_SCM_SIP_FNID(s, c) (s) & 0xFF) << 8) | ((c) & 0xFF)) |
>> 0x0200)
>> +
>> +#define MAX_QCOM_SCM_ARGS 10
>> +#define MAX_QCOM_SCM_RETS 3
>> +
>> +#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
>> +(((a) & 0xff) << 4) | \
>> +(((b) & 0xff) << 6) | \
>> +(((c) & 0xff) << 8) | \
>> +(((d) & 0xff) << 10) | \
>> +(((e) & 0xff) << 12) | \
>> +(((f) & 0xff) << 14) | \
>> +(((g) & 0xff) << 16) | \
>> +(((h) & 0xff) << 18) | \
>> +(((i) & 0xff) << 20) | \
>> +(((j) & 0xff) << 22) | \
>> +(num & 0x))
>> +
>> +#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0,
>> 0, 0, 0, 0, 0)
>> +
>> +/**
>> + * struct qcom_scm_desc
>> + * @arginfo: Metadata describing the arguments in args[]
>> + * @args: The array of arguments for the secure syscall
>> + * @ret: The values returned by the secure syscall
>> + * @extra_arg_buf: The buffer containing extra arguments
>> + (that don't fit in available registers)
>> + * @x5: The 4rd argument to the secure syscall or physical address of
>> +extra_arg_buf
>> + */
>> +struct qcom_scm_desc {
>> +u32 arginfo;
>> +u64 args[MAX_QCOM_SCM_ARGS];
>> +u64 ret[MAX_QCOM_SCM_RETS];
>> +
>> +/* private */
>> +void *extra_arg_buf;
>> +u64 x5;
>> +};
>> +
>> +
>> +#define QCOM_SCM_ENOMEM -5
>> +#define QCOM_SCM_EOPNOTSUPP -4
>> +#define QCOM_SCM_EINVAL_ADDR-3
>> +#define QCOM_SCM_EINVAL_ARG -2
>> +#define QCOM_SCM_ERROR -1
>> +#define QCOM_SCM_INTERRUPTED1
>> +#define QCOM_SCM_EBUSY -55
>> +#define QCOM_SCM_V2_EBUSY -12
>
> Any reason to duplicate ENOMEM through INTERRUPTED rather than put them in the
> common header?
No reason to duplicate them, just hadn’t noticed.
>> +static DEFINE_MUTEX(qcom_scm_lock);
>> +
>> +#define QCOM_SCM_EBUSY_WAIT_MS 30
>> +#define QCOM_SCM_EBUSY_MAX_RETRY 20
>> +
>> +#define N_EXT_QCOM_SCM_ARGS 7
>> +#define FIRST_EXT_ARG_IDX 3
>> +#define SMC_ATOMIC_SYSCALL 31
>> +#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
>> +#define SMC64_MASK 0x4000
>> +#define SMC_ATOMIC_MASK 0x8000
>> +#define IS_CALL_AVAIL_CMD 1
>> +
>> +#define R0_STR "x0"
>> +#define R1_STR "x1"
>> +#define R2_STR "x2"
>> +#define R3_STR "x3"
>> +#define R4_STR "x4"
>> +#define R5_STR "x5"
>
> What is the purpose of these macros?
Probably left over from when those code was merged between 32 and 64-bit, I’ll
just inline them.
Thanks for the review.
- k
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
On Apr 28, 2015, at 8:11 AM, Christopher Covington c...@codeaurora.org
wrote:
Hi Kumar,
On 04/27/2015 05:23 PM, Kumar Gala wrote:
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,465 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include linux/cpumask.h
+#include linux/delay.h
+#include linux/mutex.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/qcom_scm.h
+
+#include asm/cacheflush.h
+#include asm/compiler.h
+#include asm/smp_plat.h
+
+#include qcom_scm.h
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) 0xFF) 8) | ((c) 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+(((a) 0xff) 4) | \
+(((b) 0xff) 6) | \
+(((c) 0xff) 8) | \
+(((d) 0xff) 10) | \
+(((e) 0xff) 12) | \
+(((f) 0xff) 14) | \
+(((g) 0xff) 16) | \
+(((h) 0xff) 18) | \
+(((i) 0xff) 20) | \
+(((j) 0xff) 22) | \
+(num 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+extra_arg_buf
+ */
+struct qcom_scm_desc {
+u32 arginfo;
+u64 args[MAX_QCOM_SCM_ARGS];
+u64 ret[MAX_QCOM_SCM_RETS];
+
+/* private */
+void *extra_arg_buf;
+u64 x5;
+};
+
+
+#define QCOM_SCM_ENOMEM -5
+#define QCOM_SCM_EOPNOTSUPP -4
+#define QCOM_SCM_EINVAL_ADDR-3
+#define QCOM_SCM_EINVAL_ARG -2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED1
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
Any reason to duplicate ENOMEM through INTERRUPTED rather than put them in the
common header?
No reason to duplicate them, just hadn’t noticed.
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+#define R0_STR x0
+#define R1_STR x1
+#define R2_STR x2
+#define R3_STR x3
+#define R4_STR x4
+#define R5_STR x5
What is the purpose of these macros?
Probably left over from when those code was merged between 32 and 64-bit, I’ll
just inline them.
Thanks for the review.
- k
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
* v5:
- use common error defines from qcom_scm.h
- removed R*_STR defines
* v4:
- Folded in change to qcom_scm_cpu_power_down to remove HOTPLUG flag
from Lina.
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 452 +
3 files changed, 457 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 4269dba..8878800 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -190,6 +190,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool Qualcomm Platforms
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..a95fd9b
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,452 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include linux/cpumask.h
+#include linux/delay.h
+#include linux/mutex.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/qcom_scm.h
+
+#include asm/cacheflush.h
+#include asm/compiler.h
+#include asm/smp_plat.h
+
+#include qcom_scm.h
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) 0xFF) 8) | ((c) 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) 0xff) 4) | \
+ (((b) 0xff) 6) | \
+ (((c) 0xff) 8) | \
+ (((d) 0xff) 10) | \
+ (((e) 0xff) 12) | \
+ (((f) 0xff) 14) | \
+ (((g) 0xff) 16) | \
+ (((h) 0xff) 18) | \
+ (((i) 0xff) 20) | \
+ (((j) 0xff) 22) | \
+ (num 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+ return -EIO;
+ case QCOM_SCM_EINVAL_ADDR:
+ case QCOM_SCM_EINVAL_ARG:
+ return -EINVAL;
+ case QCOM_SCM_EOPNOTSUPP:
+ return -EOPNOTSUPP;
+ case QCOM_SCM_ENOMEM:
+ return
[PATCH v5 1/2] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v5:
Split out error defines in common qcom_scm.h
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c = qcom_scm-32.c} | 22 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 38 +++
4 files changed, 51 insertions(+), 454 deletions(-)
copy drivers/firmware/{qcom_scm.c = qcom_scm-32.c} (95%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 95%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..b08b822 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,13 +27,7 @@
#include asm/outercache.h
#include asm/cacheflush.h
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
+#include qcom_scm.h
#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
@@ -386,8 +380,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +404,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +427,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +436,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +464,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +473,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include linux/slab.h
-#include linux/io.h
-#include linux/module.h
-#include linux/mutex.h
-#include linux/errno.h
-#include linux/err.h
+#include linux/cpumask.h
+#include linux/export.h
+#include linux/types.h
#include linux/qcom_scm.h
-#include asm/outercache.h
-#include asm/cacheflush.h
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU1
[PATCH v4 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala
Signed-off-by: Lina Iyer
---
* v4:
- Folded in change to qcom_scm_cpu_power_down to remove HOTPLUG flag
from Lina.
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 465 +
3 files changed, 470 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 4269dba..8878800 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -190,6 +190,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool "Qualcomm Platforms"
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..38b8360
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,465 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "qcom_scm.h"
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) & 0xFF) << 8) | ((c) & 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) & 0xff) << 4) | \
+ (((b) & 0xff) << 6) | \
+ (((c) & 0xff) << 8) | \
+ (((d) & 0xff) << 10) | \
+ (((e) & 0xff) << 12) | \
+ (((f) & 0xff) << 14) | \
+ (((g) & 0xff) << 16) | \
+ (((h) & 0xff) << 18) | \
+ (((i) & 0xff) << 20) | \
+ (((j) & 0xff) << 22) | \
+ (num & 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_ENOMEM-5
+#define QCOM_SCM_EOPNOTSUPP-4
+#define QCOM_SCM_EINVAL_ADDR -3
+#define QCOM_SCM_EINVAL_ARG-2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED 1
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+#define R0_STR "x0"
+#define R1_STR "x1"
+#define R2_STR "x2"
+#define R3_STR "x3"
+#define R4_STR "x4"
+#define R5_STR "x5&quo
[PATCH v4 1/2] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala
---
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c => qcom_scm-32.c} | 15 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 29 ++
4 files changed, 42 insertions(+), 447 deletions(-)
copy drivers/firmware/{qcom_scm.c => qcom_scm-32.c} (96%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 96%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..89be15e 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,6 +27,7 @@
#include
#include
+#include "qcom_scm.h"
#define QCOM_SCM_ENOMEM-5
#define QCOM_SCM_EOPNOTSUPP-4
@@ -386,8 +387,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +411,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +434,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +443,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +471,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +480,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags & QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include
-#include
-#include
-#include
-#include
-#include
+#include
+#include
+#include
#include
-#include
-#include
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU20x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU30x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU00x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU10x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU20x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU30x40
-
-struct qcom_scm_entry {
- int flag;
- void *entry;
-};
-
-static struct qcom_scm_entry qcom_scm_wb[] = {
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
- { .flag = QCOM_SC
Re: [PATCH v2 0/7] ARM: dts: qcom: Add more device coniguration nodes
> On Apr 20, 2015, at 2:45 AM, Ivan T. Ivanov wrote: > > Recent Qualcomm PMIC's devices are accessed over SPMI bus. > Every PMIC has several "sub-function" devices inside. > > First three patches are adding device nodes to PM8841, PM8941 and PMA8084 > PMIC's. > Next two are introducing PM8916 PMIC chip with its device nodes. The sixth one > add restart device node for MSM8916 chip. And the last one add initial GPIO > definitions for APQ8016 SBC board. > > checkpatch will complain about "appears un-documented" for several drivers, > but I am expecting they to mergeed soon, hopefully during this merge window. > > Changes since v0 [2]: > > * Add proper IRQ_TYPE_* specifiers in the interrupt bidings. > > Patches are created top of Kumar's kernel tree and tags/qcom-dt-for-4.1 [1]. > > [1] https://lkml.org/lkml/2015/3/27/599 > [2] http://comments.gmane.org/gmane.linux.ports.arm.msm/12610 > > Ivan T. Ivanov (7): > ARM: dts: qcom: Add PM8841 functions device nodes > ARM: dts: qcom: Add PM8941 functions device nodes > ARM: dts: qcom: Add PMA8084 functions device nodes > arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916 > arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes > arm64: dts: qcom: Add MSM8916 restart device node > arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC >board > > arch/arm/boot/dts/qcom-pm8841.dtsi | 18 +++ > arch/arm/boot/dts/qcom-pm8941.dtsi | 133 - > arch/arm/boot/dts/qcom-pma8084.dtsi| 92 ++ > .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 30 + > arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 21 > arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 3 + > arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 1 + > arch/arm64/boot/dts/qcom/msm8916.dtsi | 25 +++- > arch/arm64/boot/dts/qcom/pm8916.dtsi | 99 +++ > 9 files changed, 420 insertions(+), 2 deletions(-) > create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi applied - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: qcom: Add msm8660 PMU node
> On Feb 10, 2015, at 7:06 PM, Stephen Boyd wrote: > > Enable perf events on msm8660 devices by adding the pmu node. > > Signed-off-by: Stephen Boyd > --- > arch/arm/boot/dts/qcom-msm8660.dtsi | 5 + > 1 file changed, 5 insertions(+) applied - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 1/2] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c = qcom_scm-32.c} | 15 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 29 ++
4 files changed, 42 insertions(+), 447 deletions(-)
copy drivers/firmware/{qcom_scm.c = qcom_scm-32.c} (96%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 96%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..89be15e 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,6 +27,7 @@
#include asm/outercache.h
#include asm/cacheflush.h
+#include qcom_scm.h
#define QCOM_SCM_ENOMEM-5
#define QCOM_SCM_EOPNOTSUPP-4
@@ -386,8 +387,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +411,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +434,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +443,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +471,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +480,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include linux/slab.h
-#include linux/io.h
-#include linux/module.h
-#include linux/mutex.h
-#include linux/errno.h
-#include linux/err.h
+#include linux/cpumask.h
+#include linux/export.h
+#include linux/types.h
#include linux/qcom_scm.h
-#include asm/outercache.h
-#include asm/cacheflush.h
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU20x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU30x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU00x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU10x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU20x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU30x40
Re: [PATCH v2 0/7] ARM: dts: qcom: Add more device coniguration nodes
On Apr 20, 2015, at 2:45 AM, Ivan T. Ivanov ivan.iva...@linaro.org wrote: Recent Qualcomm PMIC's devices are accessed over SPMI bus. Every PMIC has several sub-function devices inside. First three patches are adding device nodes to PM8841, PM8941 and PMA8084 PMIC's. Next two are introducing PM8916 PMIC chip with its device nodes. The sixth one add restart device node for MSM8916 chip. And the last one add initial GPIO definitions for APQ8016 SBC board. checkpatch will complain about appears un-documented for several drivers, but I am expecting they to mergeed soon, hopefully during this merge window. Changes since v0 [2]: * Add proper IRQ_TYPE_* specifiers in the interrupt bidings. Patches are created top of Kumar's kernel tree and tags/qcom-dt-for-4.1 [1]. [1] https://lkml.org/lkml/2015/3/27/599 [2] http://comments.gmane.org/gmane.linux.ports.arm.msm/12610 Ivan T. Ivanov (7): ARM: dts: qcom: Add PM8841 functions device nodes ARM: dts: qcom: Add PM8941 functions device nodes ARM: dts: qcom: Add PMA8084 functions device nodes arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916 arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes arm64: dts: qcom: Add MSM8916 restart device node arm64: dts: qcom: Add initial set of PMIC and SoC pins for APQ8016 SBC board arch/arm/boot/dts/qcom-pm8841.dtsi | 18 +++ arch/arm/boot/dts/qcom-pm8941.dtsi | 133 - arch/arm/boot/dts/qcom-pma8084.dtsi| 92 ++ .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 30 + arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 21 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 3 + arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 25 +++- arch/arm64/boot/dts/qcom/pm8916.dtsi | 99 +++ 9 files changed, 420 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi applied - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: qcom: Add msm8660 PMU node
On Feb 10, 2015, at 7:06 PM, Stephen Boyd sb...@codeaurora.org wrote: Enable perf events on msm8660 devices by adding the pmu node. Signed-off-by: Stephen Boyd sb...@codeaurora.org --- arch/arm/boot/dts/qcom-msm8660.dtsi | 5 + 1 file changed, 5 insertions(+) applied - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 2/2] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
* v4:
- Folded in change to qcom_scm_cpu_power_down to remove HOTPLUG flag
from Lina.
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 465 +
3 files changed, 470 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 4269dba..8878800 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -190,6 +190,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool Qualcomm Platforms
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..38b8360
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,465 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include linux/cpumask.h
+#include linux/delay.h
+#include linux/mutex.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/qcom_scm.h
+
+#include asm/cacheflush.h
+#include asm/compiler.h
+#include asm/smp_plat.h
+
+#include qcom_scm.h
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) 0xFF) 8) | ((c) 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) 0xff) 4) | \
+ (((b) 0xff) 6) | \
+ (((c) 0xff) 8) | \
+ (((d) 0xff) 10) | \
+ (((e) 0xff) 12) | \
+ (((f) 0xff) 14) | \
+ (((g) 0xff) 16) | \
+ (((h) 0xff) 18) | \
+ (((i) 0xff) 20) | \
+ (((j) 0xff) 22) | \
+ (num 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_ENOMEM-5
+#define QCOM_SCM_EOPNOTSUPP-4
+#define QCOM_SCM_EINVAL_ADDR -3
+#define QCOM_SCM_EINVAL_ARG-2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED 1
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+#define R0_STR x0
+#define R1_STR x1
+#define R2_STR x2
+#define R3_STR x3
+#define R4_STR x4
+#define R5_STR x5
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR
[PATCH v3 3/3] arm64: qcom: add cpu operations
From: Abhimanyu Kapur
Add qcom cpu operations for arm-v8 cpus. Implement secondary cpu boot ops
As a part of this change update device tree documentation for:
1. Arm cortex-a ACC device which provides percpu reg
2. Armv8 cortex-a compatible string in arm/cpus.txt
Signed-off-by: Abhimanyu Kapur
Signed-off-by: Kumar Gala
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 +
Documentation/devicetree/bindings/arm/msm/acc.txt | 19 ++
arch/arm64/kernel/Makefile | 3 +
arch/arm64/kernel/cpu_ops.c| 4 +
.../kernel/qcom-special-cpu-ops-dont-copy-this.c | 281 +
5 files changed, 309 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/acc.txt
create mode 100644 arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 8b9e0a9..35cabe5 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,8 @@ nodes to be present and contain the properties described
below.
be one of:
"psci"
"spin-table"
+"qcom,arm-cortex-acc"
+
# On ARM 32-bit systems this property is optional and
can be one of:
"allwinner,sun6i-a31"
diff --git a/Documentation/devicetree/bindings/arm/msm/acc.txt
b/Documentation/devicetree/bindings/arm/msm/acc.txt
new file mode 100644
index 000..ae2d725
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/acc.txt
@@ -0,0 +1,19 @@
+Application Processor Sub-system (APSS) Application Clock Controller (ACC)
+
+The ACC provides clock, power domain, and reset control to a CPU. There is one
ACC
+register region per CPU within the APSS remapped region as well as an alias
register
+region that remaps accesses to the ACC associated with the CPU accessing the
region.
+
+Required properties:
+- compatible: Must be "qcom,arm-cortex-acc"
+- reg: The first element specifies the base address and size of
+ the register region. An optional second element
specifies
+ the base address and size of the alias register region.
+
+Example:
+
+ clock-controller@b088000 {
+ compatible = "qcom,arm-cortex-acc";
+ reg = <0x0b088000 0x1000>,
+ <0x0b008000 0x1000>;
+ }
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 5ee07ee..8d77ac5 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -25,6 +25,9 @@ arm64-obj-$(CONFIG_COMPAT)+= sys32.o kuser32.o
signal32.o \
arm64-obj-$(CONFIG_FUNCTION_TRACER)+= ftrace.o entry-ftrace.o
arm64-obj-$(CONFIG_MODULES)+= arm64ksyms.o module.o
arm64-obj-$(CONFIG_SMP)+= smp.o smp_spin_table.o
topology.o
+ifdef CONFIG_SMP
+arm64-obj-$(CONFIG_ARCH_QCOM) += qcom-special-cpu-ops-dont-copy-this.o
+endif
arm64-obj-$(CONFIG_PERF_EVENTS)+= perf_regs.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
index cce9524..d002168 100644
--- a/arch/arm64/kernel/cpu_ops.c
+++ b/arch/arm64/kernel/cpu_ops.c
@@ -24,6 +24,7 @@
extern const struct cpu_operations smp_spin_table_ops;
extern const struct cpu_operations cpu_psci_ops;
+extern const struct cpu_operations qcom_cortex_a_ops;
const struct cpu_operations *cpu_ops[NR_CPUS];
@@ -32,6 +33,9 @@ static const struct cpu_operations *supported_cpu_ops[]
__initconst = {
_spin_table_ops,
#endif
_psci_ops,
+#ifdef CONFIG_ARCH_QCOM
+ _cortex_a_ops,
+#endif
NULL,
};
diff --git a/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
b/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
new file mode 100644
index 000..5037aa9
--- /dev/null
+++ b/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
@@ -0,0 +1,281 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* MSM ARMv8 CPU Operations
+ * Based on arch/arm64/kernel/smp_spin_table.c
+ */
+
+#i
[PATCH v3 1/3] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala
---
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c => qcom_scm-32.c} | 15 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 29 ++
4 files changed, 42 insertions(+), 447 deletions(-)
copy drivers/firmware/{qcom_scm.c => qcom_scm-32.c} (96%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 96%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..89be15e 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,6 +27,7 @@
#include
#include
+#include "qcom_scm.h"
#define QCOM_SCM_ENOMEM-5
#define QCOM_SCM_EOPNOTSUPP-4
@@ -386,8 +387,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +411,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +434,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +443,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +471,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +480,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags & QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include
-#include
-#include
-#include
-#include
-#include
+#include
+#include
+#include
#include
-#include
-#include
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU20x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU30x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU00x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU10x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU20x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU30x40
-
-struct qcom_scm_entry {
- int flag;
- void *entry;
-};
-
-static struct qcom_scm_entry qcom_scm_wb[] = {
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
- { .flag = QCOM_SC
[PATCH v3 2/3] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala
---
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 466 +
3 files changed, 471 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 610965dd..11e97d8 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -180,6 +180,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool "Qualcomm Platforms"
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..72b75d6
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,466 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "qcom_scm.h"
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) & 0xFF) << 8) | ((c) & 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) & 0xff) << 4) | \
+ (((b) & 0xff) << 6) | \
+ (((c) & 0xff) << 8) | \
+ (((d) & 0xff) << 10) | \
+ (((e) & 0xff) << 12) | \
+ (((f) & 0xff) << 14) | \
+ (((g) & 0xff) << 16) | \
+ (((h) & 0xff) << 18) | \
+ (((i) & 0xff) << 20) | \
+ (((j) & 0xff) << 22) | \
+ (num & 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_ENOMEM-5
+#define QCOM_SCM_EOPNOTSUPP-4
+#define QCOM_SCM_EINVAL_ADDR -3
+#define QCOM_SCM_EINVAL_ARG-2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED 1
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+#define R0_STR "x0"
+#define R1_STR "x1"
+#define R2_STR "x2"
+#define R3_STR "x3"
+#define R4_STR "x4"
+#define R5_STR "x5"
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+
[PATCH v3 0/3] Add smp booting support for Qualcomm ARMv8 SoCs
This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm SoCs. To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM interfaces to setup the boot/release addresses for the secondary CPUs. In addition we need a uniquie set of cpu ops. I'm aware the desired methods for booting secondary CPUs is either via spintable or PSCI. However, these SoCs are shipping with a firmware that does not support those methods. TODO: * clean up docs related to 'qcom,arm-cortex-acc' and L2 v3: * dropped use of pen, just release CPUs directly into secondary_start v2: * Dropped introduction and use of CPU_METHOD_OF_DECLARE * Moved qcom cpu ops from drivers/soc/qcom to arch/arm64/kernel * Renamed msm to qcom in cpu ops code, minor cleans (remove dead defines/code) - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
> On Apr 14, 2015, at 11:36 AM, Mark Rutland wrote: > > On Fri, Apr 10, 2015 at 11:05:29AM +0100, Catalin Marinas wrote: >> On Thu, Apr 09, 2015 at 12:37:06PM -0500, Kumar Gala wrote: >>> This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm >>> SoCs. >>> >>> To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM >>> interfaces to >>> setup the boot/release addresses for the secondary CPUs. In addition we >>> need >>> a uniquie set of cpu ops. I'm aware the desired methods for booting >>> secondary >>> CPUs is either via spintable or PSCI. However, these SoCs are shipping >>> with a >>> firmware that does not support those methods. >> >> And the reason is? Some guesses: >> >> a) QC doesn't think boot interface (and cpuidle) standardisation is >> worth the effort (to put it nicely) >> b) The hardware was available before we even mentioned PSCI >> c) PSCI is not suitable for the QC's SCM interface >> d) Any combination of the above >> >> I strongly suspect it's point (a). Should we expect future QC hardware >> to do the same? >> >> You could argue the reason was (b), though we've been discussing PSCI >> for at least two years and, according to QC press releases, MSM8916 >> started sampling in 2014. >> >> The only valid reason is (c) and if that's the case, I would expect a >> proposal for a new firmware interface protocol (it could be PSCI-based), >> well documented, that can be shared with others that may encounter the >> same shortcomings. > > There's no need to even fork PSCI. The PSCI specification will evolve > over time as vendors request changes and we try to accomodate them. > > If there's something that PSCI doesn't do that you need it to, contact > ARM. Other vendors already have. But what is someone to do between the period of getting PSCI spec updated and needing to ship a product with firmware? The take still sounds like if you don’t implement an exact version of PSCI you are screwed from being supported in the upstream ARM64 kernel. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 4/5] arm64: smp: move the pen to a header file
> On Apr 9, 2015, at 4:17 PM, Arnd Bergmann wrote: > > On Thursday 09 April 2015 12:37:10 Kumar Gala wrote: >> From: Abhimanyu Kapur >> >> Move the secondary_pen_release variable and the secondary_holding_pen >> entry function to asm/smp_plat.h so that the other cpu ops implementations >> can share them. >> >> Signed-off-by: Abhimanyu Kapur >> Signed-off-by: Kumar Gala >> > > I don't believe your SMP implementation can be so broken to require this. > Please fix the code instead to not use a holding pen. > > Arnd Yeah, I can drop this. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 4/5] arm64: smp: move the pen to a header file
> On Apr 14, 2015, at 10:59 AM, Mark Rutland wrote: > > On Thu, Apr 09, 2015 at 06:37:10PM +0100, Kumar Gala wrote: >> From: Abhimanyu Kapur >> >> Move the secondary_pen_release variable and the secondary_holding_pen >> entry function to asm/smp_plat.h so that the other cpu ops implementations >> can share them. > > If anything, this should all be moved into smp_spin_table.c, and made > static. > > We made a mistake with the pen (and allowing multiple CPUs to enter the > kernel at once). That mistake shouldn't be spread further. > > Mark. Yeah, it appears I can drop this and just set the secondary cores to enter secondary_entry. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v6 1/2] DT: hwspinlock: Add binding documentation for Qualcomm hwmutex
> On Feb 27, 2015, at 4:30 PM, Bjorn Andersson > wrote: > > Add binding documentation for the Qualcomm Hardware Mutex. > > Signed-off-by: Bjorn Andersson > — > Acked-by: Kumar Gala - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
> On Apr 14, 2015, at 9:21 AM, Kumar Gala wrote: > >>>> >>>> So please come up with proper technical arguments rather than the kernel >>>> should take whatever SoC vendors dreamt of. >>> >>> There is no technical argument to be made. This is about the >>> community and you as maintainer wanting to accept code that complies >>> to your decision or not. >> >> If you are not willing to make technical arguments, I don't have to >> provide any further reasons in this thread. It's your choice. In the >> meantime, the short answer is NAK. I assume you would than NAK someone trying to get support for their Nexus 9 Tablet using a Tegra K1. It appears the shipping code for that device didn’t use PSCI (again guessing because it wasn’t available at the time). https://android.googlesource.com/kernel/tegra/+/android-tegra-flounder-3.10-lollipop-release/arch/arm64/mach-tegra/platsmp.c If so, I find this counter to the Linux kernel communities normal desire to support the most hardware platforms. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
> On Apr 13, 2015, at 4:41 AM, Catalin Marinas wrote: > > On Fri, Apr 10, 2015 at 02:06:33PM -0500, Kumar Gala wrote: >> On Apr 10, 2015, at 11:10 AM, Catalin Marinas >> wrote: >>> On Fri, Apr 10, 2015 at 10:24:46AM -0500, Kumar Gala wrote: >>>> On Apr 10, 2015, at 5:05 AM, Catalin Marinas >>>> wrote: >>>>> On Thu, Apr 09, 2015 at 12:37:06PM -0500, Kumar Gala wrote: >>>>>> This patch set adds support for SMP boot on the MSM8x16 family of >>>>>> Qualcomm SoCs. >>>>>> >>>>>> To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM >>>>>> interfaces to >>>>>> setup the boot/release addresses for the secondary CPUs. In addition we >>>>>> need >>>>>> a uniquie set of cpu ops. I'm aware the desired methods for booting >>>>>> secondary >>>>>> CPUs is either via spintable or PSCI. However, these SoCs are shipping >>>>>> with a >>>>>> firmware that does not support those methods. >>>>> >>>>> And the reason is? Some guesses: >>>>> >>>>> a) QC doesn't think boot interface (and cpuidle) standardisation is >>>>> worth the effort (to put it nicely) >>>>> b) The hardware was available before we even mentioned PSCI >>>>> c) PSCI is not suitable for the QC's SCM interface >>>>> d) Any combination of the above >>>>> >>>>> I strongly suspect it's point (a). Should we expect future QC hardware >>>>> to do the same? >>>>> >>>>> You could argue the reason was (b), though we've been discussing PSCI >>>>> for at least two years and, according to QC press releases, MSM8916 >>>>> started sampling in 2014. >>>>> >>>>> The only valid reason is (c) and if that's the case, I would expect a >>>>> proposal for a new firmware interface protocol (it could be PSCI-based), >>>>> well documented, that can be shared with others that may encounter the >>>>> same shortcomings. >>>> >>>> Does it matter? I’ve always felt the kernel was a place of inclusion. >>>> Qualcomm choose for whatever reason to not use PSCI or spin table. >>>> You don’t like it, I might not like it, but it is what it is. >>> >>> Yes, it matters, but only if Qualcomm wants the SoC support in mainline. >>> Just because Qualcomm Inc does not want to invest in implementing a >>> standard firmware interface is not a good enough reason to merge the >>> kernel code. >> >> The reason to merge the code upstream it expands functionality for a >> platform. > > This alone has never been a good enough reason. Code (both design and > style) needs to pass the review. You haven’t really made any comments about the code itself, other than just not liking the firmware interface. > There is nothing that says when someone licenses an ARM core that they >> must also implement this standard. > > Just to be perfectly clear: this has nothing to do with ARM Ltd nor the > ARM hardware licensing terms. ARM Ltd doesn't even require you to use > Linux, that's your choice. But when you make an OS choice, you have to > abide by its rules. But Linux has tended to support hardware as broadly as it can. Yes it tries to get firmware to improve but there are numerous devices with embedded firmware interfaces that Linux probably would love to change but deals with because they are fixed. > Qualcomm choose for whatever reasons to not implement it. There are >> examples on other architectures supporting non-standard platforms all >> the time (x86 supported Voyager and SGI VIS for a long time). As far >> as I can tell you are just wanting uniformity to impose this rule. > > Don't confuse non-standard hardware (which has always been acceptable on > ARM) with non-standard ways of entering the kernel from firmware, > whether it's a primary or secondary CPU. Just look at how many smp_ops > structures are defined on x86. When Voyager was supported it had a unique means for SMP bring up. In the 4.0 kernel MIPS supports 13 different means, PowerPC has 14 different means, ARM has 36 different means. >>> What if Qualcomm decides that it doesn't like DT, nor ACPI but comes up >>> with yet another way to describe hardware because that's what the >>> firmware provides? Should the kernel community take it? You could argue >>> that this is a significant change but it's about the principle
Re: [RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
On Apr 13, 2015, at 4:41 AM, Catalin Marinas catalin.mari...@arm.com wrote: On Fri, Apr 10, 2015 at 02:06:33PM -0500, Kumar Gala wrote: On Apr 10, 2015, at 11:10 AM, Catalin Marinas catalin.mari...@arm.com wrote: On Fri, Apr 10, 2015 at 10:24:46AM -0500, Kumar Gala wrote: On Apr 10, 2015, at 5:05 AM, Catalin Marinas catalin.mari...@arm.com wrote: On Thu, Apr 09, 2015 at 12:37:06PM -0500, Kumar Gala wrote: This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm SoCs. To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM interfaces to setup the boot/release addresses for the secondary CPUs. In addition we need a uniquie set of cpu ops. I'm aware the desired methods for booting secondary CPUs is either via spintable or PSCI. However, these SoCs are shipping with a firmware that does not support those methods. And the reason is? Some guesses: a) QC doesn't think boot interface (and cpuidle) standardisation is worth the effort (to put it nicely) b) The hardware was available before we even mentioned PSCI c) PSCI is not suitable for the QC's SCM interface d) Any combination of the above I strongly suspect it's point (a). Should we expect future QC hardware to do the same? You could argue the reason was (b), though we've been discussing PSCI for at least two years and, according to QC press releases, MSM8916 started sampling in 2014. The only valid reason is (c) and if that's the case, I would expect a proposal for a new firmware interface protocol (it could be PSCI-based), well documented, that can be shared with others that may encounter the same shortcomings. Does it matter? I’ve always felt the kernel was a place of inclusion. Qualcomm choose for whatever reason to not use PSCI or spin table. You don’t like it, I might not like it, but it is what it is. Yes, it matters, but only if Qualcomm wants the SoC support in mainline. Just because Qualcomm Inc does not want to invest in implementing a standard firmware interface is not a good enough reason to merge the kernel code. The reason to merge the code upstream it expands functionality for a platform. This alone has never been a good enough reason. Code (both design and style) needs to pass the review. You haven’t really made any comments about the code itself, other than just not liking the firmware interface. There is nothing that says when someone licenses an ARM core that they must also implement this standard. Just to be perfectly clear: this has nothing to do with ARM Ltd nor the ARM hardware licensing terms. ARM Ltd doesn't even require you to use Linux, that's your choice. But when you make an OS choice, you have to abide by its rules. But Linux has tended to support hardware as broadly as it can. Yes it tries to get firmware to improve but there are numerous devices with embedded firmware interfaces that Linux probably would love to change but deals with because they are fixed. Qualcomm choose for whatever reasons to not implement it. There are examples on other architectures supporting non-standard platforms all the time (x86 supported Voyager and SGI VIS for a long time). As far as I can tell you are just wanting uniformity to impose this rule. Don't confuse non-standard hardware (which has always been acceptable on ARM) with non-standard ways of entering the kernel from firmware, whether it's a primary or secondary CPU. Just look at how many smp_ops structures are defined on x86. When Voyager was supported it had a unique means for SMP bring up. In the 4.0 kernel MIPS supports 13 different means, PowerPC has 14 different means, ARM has 36 different means. What if Qualcomm decides that it doesn't like DT, nor ACPI but comes up with yet another way to describe hardware because that's what the firmware provides? Should the kernel community take it? You could argue that this is a significant change but it's about the principle. And each SoC with its own non-standard boot protocol for no good reason is significant. I wouldn’t argue that because we are talking about something that has an extremely small impact on the maintainability or changes to how the kernel actually functions. It's not about one particular case but about where to draw the line. Just multiply this change by the number of SoC variants and you'll no longer see this as extremely small impact. Why would we accept it for Qualcomm and reject it for others? It's either giving up trying to standardise this altogether or enforcing rules. Since you only care about Qualcomm hardware, you don't care about the overall picture. By your reasoning, Qualcomm may solely decide to change the booting for the primary CPU as well, ignore single Image requirements (well, why would Qualcomm care about other SoCs) and so on. The kernel community should just accept such changes without questioning because they expand platform functionality. I
Re: [RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
On Apr 14, 2015, at 9:21 AM, Kumar Gala ga...@codeaurora.org wrote: So please come up with proper technical arguments rather than the kernel should take whatever SoC vendors dreamt of. There is no technical argument to be made. This is about the community and you as maintainer wanting to accept code that complies to your decision or not. If you are not willing to make technical arguments, I don't have to provide any further reasons in this thread. It's your choice. In the meantime, the short answer is NAK. I assume you would than NAK someone trying to get support for their Nexus 9 Tablet using a Tegra K1. It appears the shipping code for that device didn’t use PSCI (again guessing because it wasn’t available at the time). https://android.googlesource.com/kernel/tegra/+/android-tegra-flounder-3.10-lollipop-release/arch/arm64/mach-tegra/platsmp.c If so, I find this counter to the Linux kernel communities normal desire to support the most hardware platforms. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v6 1/2] DT: hwspinlock: Add binding documentation for Qualcomm hwmutex
On Feb 27, 2015, at 4:30 PM, Bjorn Andersson bjorn.anders...@sonymobile.com wrote: Add binding documentation for the Qualcomm Hardware Mutex. Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com — Acked-by: Kumar Gala ga...@codeaurora.org - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 1/3] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c = qcom_scm-32.c} | 15 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 29 ++
4 files changed, 42 insertions(+), 447 deletions(-)
copy drivers/firmware/{qcom_scm.c = qcom_scm-32.c} (96%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 96%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..89be15e 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,6 +27,7 @@
#include asm/outercache.h
#include asm/cacheflush.h
+#include qcom_scm.h
#define QCOM_SCM_ENOMEM-5
#define QCOM_SCM_EOPNOTSUPP-4
@@ -386,8 +387,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +411,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +434,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +443,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +471,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +480,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include linux/slab.h
-#include linux/io.h
-#include linux/module.h
-#include linux/mutex.h
-#include linux/errno.h
-#include linux/err.h
+#include linux/cpumask.h
+#include linux/export.h
+#include linux/types.h
#include linux/qcom_scm.h
-#include asm/outercache.h
-#include asm/cacheflush.h
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU20x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU30x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU00x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU10x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU20x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU30x40
[PATCH v3 3/3] arm64: qcom: add cpu operations
From: Abhimanyu Kapur abhim...@codeaurora.org
Add qcom cpu operations for arm-v8 cpus. Implement secondary cpu boot ops
As a part of this change update device tree documentation for:
1. Arm cortex-a ACC device which provides percpu reg
2. Armv8 cortex-a compatible string in arm/cpus.txt
Signed-off-by: Abhimanyu Kapur abhim...@codeaurora.org
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 +
Documentation/devicetree/bindings/arm/msm/acc.txt | 19 ++
arch/arm64/kernel/Makefile | 3 +
arch/arm64/kernel/cpu_ops.c| 4 +
.../kernel/qcom-special-cpu-ops-dont-copy-this.c | 281 +
5 files changed, 309 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/acc.txt
create mode 100644 arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 8b9e0a9..35cabe5 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,8 @@ nodes to be present and contain the properties described
below.
be one of:
psci
spin-table
+qcom,arm-cortex-acc
+
# On ARM 32-bit systems this property is optional and
can be one of:
allwinner,sun6i-a31
diff --git a/Documentation/devicetree/bindings/arm/msm/acc.txt
b/Documentation/devicetree/bindings/arm/msm/acc.txt
new file mode 100644
index 000..ae2d725
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/acc.txt
@@ -0,0 +1,19 @@
+Application Processor Sub-system (APSS) Application Clock Controller (ACC)
+
+The ACC provides clock, power domain, and reset control to a CPU. There is one
ACC
+register region per CPU within the APSS remapped region as well as an alias
register
+region that remaps accesses to the ACC associated with the CPU accessing the
region.
+
+Required properties:
+- compatible: Must be qcom,arm-cortex-acc
+- reg: The first element specifies the base address and size of
+ the register region. An optional second element
specifies
+ the base address and size of the alias register region.
+
+Example:
+
+ clock-controller@b088000 {
+ compatible = qcom,arm-cortex-acc;
+ reg = 0x0b088000 0x1000,
+ 0x0b008000 0x1000;
+ }
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 5ee07ee..8d77ac5 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -25,6 +25,9 @@ arm64-obj-$(CONFIG_COMPAT)+= sys32.o kuser32.o
signal32.o \
arm64-obj-$(CONFIG_FUNCTION_TRACER)+= ftrace.o entry-ftrace.o
arm64-obj-$(CONFIG_MODULES)+= arm64ksyms.o module.o
arm64-obj-$(CONFIG_SMP)+= smp.o smp_spin_table.o
topology.o
+ifdef CONFIG_SMP
+arm64-obj-$(CONFIG_ARCH_QCOM) += qcom-special-cpu-ops-dont-copy-this.o
+endif
arm64-obj-$(CONFIG_PERF_EVENTS)+= perf_regs.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
index cce9524..d002168 100644
--- a/arch/arm64/kernel/cpu_ops.c
+++ b/arch/arm64/kernel/cpu_ops.c
@@ -24,6 +24,7 @@
extern const struct cpu_operations smp_spin_table_ops;
extern const struct cpu_operations cpu_psci_ops;
+extern const struct cpu_operations qcom_cortex_a_ops;
const struct cpu_operations *cpu_ops[NR_CPUS];
@@ -32,6 +33,9 @@ static const struct cpu_operations *supported_cpu_ops[]
__initconst = {
smp_spin_table_ops,
#endif
cpu_psci_ops,
+#ifdef CONFIG_ARCH_QCOM
+ qcom_cortex_a_ops,
+#endif
NULL,
};
diff --git a/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
b/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
new file mode 100644
index 000..5037aa9
--- /dev/null
+++ b/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
@@ -0,0 +1,281 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* MSM ARMv8 CPU Operations
+ * Based on arch/arm64/kernel/smp_spin_table.c
+ */
+
+#include linux
Re: [RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
On Apr 14, 2015, at 11:36 AM, Mark Rutland mark.rutl...@arm.com wrote: On Fri, Apr 10, 2015 at 11:05:29AM +0100, Catalin Marinas wrote: On Thu, Apr 09, 2015 at 12:37:06PM -0500, Kumar Gala wrote: This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm SoCs. To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM interfaces to setup the boot/release addresses for the secondary CPUs. In addition we need a uniquie set of cpu ops. I'm aware the desired methods for booting secondary CPUs is either via spintable or PSCI. However, these SoCs are shipping with a firmware that does not support those methods. And the reason is? Some guesses: a) QC doesn't think boot interface (and cpuidle) standardisation is worth the effort (to put it nicely) b) The hardware was available before we even mentioned PSCI c) PSCI is not suitable for the QC's SCM interface d) Any combination of the above I strongly suspect it's point (a). Should we expect future QC hardware to do the same? You could argue the reason was (b), though we've been discussing PSCI for at least two years and, according to QC press releases, MSM8916 started sampling in 2014. The only valid reason is (c) and if that's the case, I would expect a proposal for a new firmware interface protocol (it could be PSCI-based), well documented, that can be shared with others that may encounter the same shortcomings. There's no need to even fork PSCI. The PSCI specification will evolve over time as vendors request changes and we try to accomodate them. If there's something that PSCI doesn't do that you need it to, contact ARM. Other vendors already have. But what is someone to do between the period of getting PSCI spec updated and needing to ship a product with firmware? The take still sounds like if you don’t implement an exact version of PSCI you are screwed from being supported in the upstream ARM64 kernel. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 4/5] arm64: smp: move the pen to a header file
On Apr 9, 2015, at 4:17 PM, Arnd Bergmann a...@arndb.de wrote: On Thursday 09 April 2015 12:37:10 Kumar Gala wrote: From: Abhimanyu Kapur abhim...@codeaurora.org Move the secondary_pen_release variable and the secondary_holding_pen entry function to asm/smp_plat.h so that the other cpu ops implementations can share them. Signed-off-by: Abhimanyu Kapur abhim...@codeaurora.org Signed-off-by: Kumar Gala ga...@codeaurora.org I don't believe your SMP implementation can be so broken to require this. Please fix the code instead to not use a holding pen. Arnd Yeah, I can drop this. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC PATCH 4/5] arm64: smp: move the pen to a header file
On Apr 14, 2015, at 10:59 AM, Mark Rutland mark.rutl...@arm.com wrote: On Thu, Apr 09, 2015 at 06:37:10PM +0100, Kumar Gala wrote: From: Abhimanyu Kapur abhim...@codeaurora.org Move the secondary_pen_release variable and the secondary_holding_pen entry function to asm/smp_plat.h so that the other cpu ops implementations can share them. If anything, this should all be moved into smp_spin_table.c, and made static. We made a mistake with the pen (and allowing multiple CPUs to enter the kernel at once). That mistake shouldn't be spread further. Mark. Yeah, it appears I can drop this and just set the secondary cores to enter secondary_entry. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 0/3] Add smp booting support for Qualcomm ARMv8 SoCs
This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm SoCs. To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM interfaces to setup the boot/release addresses for the secondary CPUs. In addition we need a uniquie set of cpu ops. I'm aware the desired methods for booting secondary CPUs is either via spintable or PSCI. However, these SoCs are shipping with a firmware that does not support those methods. TODO: * clean up docs related to 'qcom,arm-cortex-acc' and L2 v3: * dropped use of pen, just release CPUs directly into secondary_start v2: * Dropped introduction and use of CPU_METHOD_OF_DECLARE * Moved qcom cpu ops from drivers/soc/qcom to arch/arm64/kernel * Renamed msm to qcom in cpu ops code, minor cleans (remove dead defines/code) - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 2/3] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 466 +
3 files changed, 471 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 610965dd..11e97d8 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -180,6 +180,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool Qualcomm Platforms
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..72b75d6
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,466 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include linux/cpumask.h
+#include linux/delay.h
+#include linux/mutex.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/qcom_scm.h
+
+#include asm/cacheflush.h
+#include asm/compiler.h
+#include asm/smp_plat.h
+
+#include qcom_scm.h
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) 0xFF) 8) | ((c) 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) 0xff) 4) | \
+ (((b) 0xff) 6) | \
+ (((c) 0xff) 8) | \
+ (((d) 0xff) 10) | \
+ (((e) 0xff) 12) | \
+ (((f) 0xff) 14) | \
+ (((g) 0xff) 16) | \
+ (((h) 0xff) 18) | \
+ (((i) 0xff) 20) | \
+ (((j) 0xff) 22) | \
+ (num 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_ENOMEM-5
+#define QCOM_SCM_EOPNOTSUPP-4
+#define QCOM_SCM_EINVAL_ADDR -3
+#define QCOM_SCM_EINVAL_ARG-2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED 1
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+#define R0_STR x0
+#define R1_STR x1
+#define R2_STR x2
+#define R3_STR x3
+#define R4_STR x4
+#define R5_STR x5
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+ return -EIO;
+ case QCOM_SCM_EINVAL_ADDR:
+ case QCOM_SCM_EINVAL_ARG:
+ return -EINVAL
Re: [PATCH] ARM: dts: qcom: Add msm8660 PMU node
> On Apr 10, 2015, at 7:19 PM, Stephen Boyd wrote: > > On 02/10/15 17:06, Stephen Boyd wrote: >> Enable perf events on msm8660 devices by adding the pmu node. >> >> Signed-off-by: Stephen Boyd >> --- > > Ping? Sorry, trying to clear out patches on a Friday night before going > home. I just missed it will pick it up for 4.2 merge. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: qcom: Add msm8660 PMU node
On Apr 10, 2015, at 7:19 PM, Stephen Boyd sb...@codeaurora.org wrote: On 02/10/15 17:06, Stephen Boyd wrote: Enable perf events on msm8660 devices by adding the pmu node. Signed-off-by: Stephen Boyd sb...@codeaurora.org --- Ping? Sorry, trying to clear out patches on a Friday night before going home. I just missed it will pick it up for 4.2 merge. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH v2 1/4] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala
---
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c => qcom_scm-32.c} | 15 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 29 ++
4 files changed, 42 insertions(+), 447 deletions(-)
copy drivers/firmware/{qcom_scm.c => qcom_scm-32.c} (96%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 96%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..89be15e 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,6 +27,7 @@
#include
#include
+#include "qcom_scm.h"
#define QCOM_SCM_ENOMEM-5
#define QCOM_SCM_EOPNOTSUPP-4
@@ -386,8 +387,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +411,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +434,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +443,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +471,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +480,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags & QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include
-#include
-#include
-#include
-#include
-#include
+#include
+#include
+#include
#include
-#include
-#include
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU20x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU30x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU00x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU10x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU20x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU30x40
-
-struct qcom_scm_entry {
- int flag;
- void *entry;
-};
-
-static struct qcom_scm_entry qcom_scm_wb[] = {
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
- { .flag = QCOM_SC
[RFC PATCH v2 2/4] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala
---
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 466 +
3 files changed, 471 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 610965dd..11e97d8 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -180,6 +180,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool "Qualcomm Platforms"
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..72b75d6
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,466 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "qcom_scm.h"
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) & 0xFF) << 8) | ((c) & 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) & 0xff) << 4) | \
+ (((b) & 0xff) << 6) | \
+ (((c) & 0xff) << 8) | \
+ (((d) & 0xff) << 10) | \
+ (((e) & 0xff) << 12) | \
+ (((f) & 0xff) << 14) | \
+ (((g) & 0xff) << 16) | \
+ (((h) & 0xff) << 18) | \
+ (((i) & 0xff) << 20) | \
+ (((j) & 0xff) << 22) | \
+ (num & 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_ENOMEM-5
+#define QCOM_SCM_EOPNOTSUPP-4
+#define QCOM_SCM_EINVAL_ADDR -3
+#define QCOM_SCM_EINVAL_ARG-2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED 1
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+#define R0_STR "x0"
+#define R1_STR "x1"
+#define R2_STR "x2"
+#define R3_STR "x3"
+#define R4_STR "x4"
+#define R5_STR "x5"
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+
[RFC PATCH v2 4/4] arm64: qcom: add cpu operations
From: Abhimanyu Kapur
Add qcom cpu operations for arm-v8 cpus. Implement secondary cpu boot ops
As a part of this change update device tree documentation for:
1. Arm cortex-a ACC device which provides percpu reg
2. Armv8 cortex-a compatible string in arm/cpus.txt
Signed-off-by: Abhimanyu Kapur
Signed-off-by: Kumar Gala
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 +
Documentation/devicetree/bindings/arm/msm/acc.txt | 19 ++
arch/arm64/kernel/Makefile | 3 +
arch/arm64/kernel/cpu_ops.c| 4 +
.../kernel/qcom-special-cpu-ops-dont-copy-this.c | 329 +
5 files changed, 357 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/acc.txt
create mode 100644 arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 8b9e0a9..35cabe5 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,8 @@ nodes to be present and contain the properties described
below.
be one of:
"psci"
"spin-table"
+"qcom,arm-cortex-acc"
+
# On ARM 32-bit systems this property is optional and
can be one of:
"allwinner,sun6i-a31"
diff --git a/Documentation/devicetree/bindings/arm/msm/acc.txt
b/Documentation/devicetree/bindings/arm/msm/acc.txt
new file mode 100644
index 000..ae2d725
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/acc.txt
@@ -0,0 +1,19 @@
+Application Processor Sub-system (APSS) Application Clock Controller (ACC)
+
+The ACC provides clock, power domain, and reset control to a CPU. There is one
ACC
+register region per CPU within the APSS remapped region as well as an alias
register
+region that remaps accesses to the ACC associated with the CPU accessing the
region.
+
+Required properties:
+- compatible: Must be "qcom,arm-cortex-acc"
+- reg: The first element specifies the base address and size of
+ the register region. An optional second element
specifies
+ the base address and size of the alias register region.
+
+Example:
+
+ clock-controller@b088000 {
+ compatible = "qcom,arm-cortex-acc";
+ reg = <0x0b088000 0x1000>,
+ <0x0b008000 0x1000>;
+ }
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 5ee07ee..8d77ac5 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -25,6 +25,9 @@ arm64-obj-$(CONFIG_COMPAT)+= sys32.o kuser32.o
signal32.o \
arm64-obj-$(CONFIG_FUNCTION_TRACER)+= ftrace.o entry-ftrace.o
arm64-obj-$(CONFIG_MODULES)+= arm64ksyms.o module.o
arm64-obj-$(CONFIG_SMP)+= smp.o smp_spin_table.o
topology.o
+ifdef CONFIG_SMP
+arm64-obj-$(CONFIG_ARCH_QCOM) += qcom-special-cpu-ops-dont-copy-this.o
+endif
arm64-obj-$(CONFIG_PERF_EVENTS)+= perf_regs.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
index cce9524..d002168 100644
--- a/arch/arm64/kernel/cpu_ops.c
+++ b/arch/arm64/kernel/cpu_ops.c
@@ -24,6 +24,7 @@
extern const struct cpu_operations smp_spin_table_ops;
extern const struct cpu_operations cpu_psci_ops;
+extern const struct cpu_operations qcom_cortex_a_ops;
const struct cpu_operations *cpu_ops[NR_CPUS];
@@ -32,6 +33,9 @@ static const struct cpu_operations *supported_cpu_ops[]
__initconst = {
_spin_table_ops,
#endif
_psci_ops,
+#ifdef CONFIG_ARCH_QCOM
+ _cortex_a_ops,
+#endif
NULL,
};
diff --git a/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
b/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
new file mode 100644
index 000..11995d6
--- /dev/null
+++ b/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
@@ -0,0 +1,329 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* MSM ARMv8 CPU Operations
+ * Based on arch/arm64/kernel/smp_spin_table.c
+ */
+
+#i
[RFC PATCH v3 3/4] arm64: smp: move the pen to a header file
From: Abhimanyu Kapur
Move the secondary_pen_release variable and the secondary_holding_pen
entry function to asm/smp_plat.h so that the other cpu ops implementations
can share them.
Signed-off-by: Abhimanyu Kapur
Signed-off-by: Kumar Gala
---
arch/arm64/include/asm/smp_plat.h | 2 ++
arch/arm64/kernel/smp.c| 1 +
arch/arm64/kernel/smp_spin_table.c | 3 ---
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/smp_plat.h
b/arch/arm64/include/asm/smp_plat.h
index 59e2823..235ff04 100644
--- a/arch/arm64/include/asm/smp_plat.h
+++ b/arch/arm64/include/asm/smp_plat.h
@@ -34,10 +34,12 @@ static inline u32 mpidr_hash_size(void)
return 1 << mpidr_hash.bits;
}
+extern void secondary_holding_pen(void);
/*
* Logical CPU mapping.
*/
extern u64 __cpu_logical_map[NR_CPUS];
#define cpu_logical_map(cpu)__cpu_logical_map[cpu]
+extern volatile unsigned long secondary_holding_pen_release;
#endif /* __ASM_SMP_PLAT_H */
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 328b8ce..4ce1f23 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -61,6 +61,7 @@
* where to place its SVC stack
*/
struct secondary_data secondary_data;
+volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
enum ipi_msg_type {
IPI_RESCHEDULE,
diff --git a/arch/arm64/kernel/smp_spin_table.c
b/arch/arm64/kernel/smp_spin_table.c
index 14944e5..808536e 100644
--- a/arch/arm64/kernel/smp_spin_table.c
+++ b/arch/arm64/kernel/smp_spin_table.c
@@ -28,9 +28,6 @@
#include
#include
-extern void secondary_holding_pen(void);
-volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
-
static phys_addr_t cpu_release_addr[NR_CPUS];
/*
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
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Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm SoCs. To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM interfaces to setup the boot/release addresses for the secondary CPUs. In addition we need a uniquie set of cpu ops. I'm aware the desired methods for booting secondary CPUs is either via spintable or PSCI. However, these SoCs are shipping with a firmware that does not support those methods. v2: * Dropped introduction and use of CPU_METHOD_OF_DECLARE * Moved qcom cpu ops from drivers/soc/qcom to arch/arm64/kernel * Renamed msm to qcom in cpu ops code, minor cleans (remove dead defines/code) - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH v3 3/4] arm64: smp: move the pen to a header file
From: Abhimanyu Kapur abhim...@codeaurora.org
Move the secondary_pen_release variable and the secondary_holding_pen
entry function to asm/smp_plat.h so that the other cpu ops implementations
can share them.
Signed-off-by: Abhimanyu Kapur abhim...@codeaurora.org
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm64/include/asm/smp_plat.h | 2 ++
arch/arm64/kernel/smp.c| 1 +
arch/arm64/kernel/smp_spin_table.c | 3 ---
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/smp_plat.h
b/arch/arm64/include/asm/smp_plat.h
index 59e2823..235ff04 100644
--- a/arch/arm64/include/asm/smp_plat.h
+++ b/arch/arm64/include/asm/smp_plat.h
@@ -34,10 +34,12 @@ static inline u32 mpidr_hash_size(void)
return 1 mpidr_hash.bits;
}
+extern void secondary_holding_pen(void);
/*
* Logical CPU mapping.
*/
extern u64 __cpu_logical_map[NR_CPUS];
#define cpu_logical_map(cpu)__cpu_logical_map[cpu]
+extern volatile unsigned long secondary_holding_pen_release;
#endif /* __ASM_SMP_PLAT_H */
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 328b8ce..4ce1f23 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -61,6 +61,7 @@
* where to place its SVC stack
*/
struct secondary_data secondary_data;
+volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
enum ipi_msg_type {
IPI_RESCHEDULE,
diff --git a/arch/arm64/kernel/smp_spin_table.c
b/arch/arm64/kernel/smp_spin_table.c
index 14944e5..808536e 100644
--- a/arch/arm64/kernel/smp_spin_table.c
+++ b/arch/arm64/kernel/smp_spin_table.c
@@ -28,9 +28,6 @@
#include asm/io.h
#include asm/smp_plat.h
-extern void secondary_holding_pen(void);
-volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
-
static phys_addr_t cpu_release_addr[NR_CPUS];
/*
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm SoCs. To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM interfaces to setup the boot/release addresses for the secondary CPUs. In addition we need a uniquie set of cpu ops. I'm aware the desired methods for booting secondary CPUs is either via spintable or PSCI. However, these SoCs are shipping with a firmware that does not support those methods. v2: * Dropped introduction and use of CPU_METHOD_OF_DECLARE * Moved qcom cpu ops from drivers/soc/qcom to arch/arm64/kernel * Renamed msm to qcom in cpu ops code, minor cleans (remove dead defines/code) - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH v2 4/4] arm64: qcom: add cpu operations
From: Abhimanyu Kapur abhim...@codeaurora.org
Add qcom cpu operations for arm-v8 cpus. Implement secondary cpu boot ops
As a part of this change update device tree documentation for:
1. Arm cortex-a ACC device which provides percpu reg
2. Armv8 cortex-a compatible string in arm/cpus.txt
Signed-off-by: Abhimanyu Kapur abhim...@codeaurora.org
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 +
Documentation/devicetree/bindings/arm/msm/acc.txt | 19 ++
arch/arm64/kernel/Makefile | 3 +
arch/arm64/kernel/cpu_ops.c| 4 +
.../kernel/qcom-special-cpu-ops-dont-copy-this.c | 329 +
5 files changed, 357 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/acc.txt
create mode 100644 arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 8b9e0a9..35cabe5 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,8 @@ nodes to be present and contain the properties described
below.
be one of:
psci
spin-table
+qcom,arm-cortex-acc
+
# On ARM 32-bit systems this property is optional and
can be one of:
allwinner,sun6i-a31
diff --git a/Documentation/devicetree/bindings/arm/msm/acc.txt
b/Documentation/devicetree/bindings/arm/msm/acc.txt
new file mode 100644
index 000..ae2d725
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/acc.txt
@@ -0,0 +1,19 @@
+Application Processor Sub-system (APSS) Application Clock Controller (ACC)
+
+The ACC provides clock, power domain, and reset control to a CPU. There is one
ACC
+register region per CPU within the APSS remapped region as well as an alias
register
+region that remaps accesses to the ACC associated with the CPU accessing the
region.
+
+Required properties:
+- compatible: Must be qcom,arm-cortex-acc
+- reg: The first element specifies the base address and size of
+ the register region. An optional second element
specifies
+ the base address and size of the alias register region.
+
+Example:
+
+ clock-controller@b088000 {
+ compatible = qcom,arm-cortex-acc;
+ reg = 0x0b088000 0x1000,
+ 0x0b008000 0x1000;
+ }
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 5ee07ee..8d77ac5 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -25,6 +25,9 @@ arm64-obj-$(CONFIG_COMPAT)+= sys32.o kuser32.o
signal32.o \
arm64-obj-$(CONFIG_FUNCTION_TRACER)+= ftrace.o entry-ftrace.o
arm64-obj-$(CONFIG_MODULES)+= arm64ksyms.o module.o
arm64-obj-$(CONFIG_SMP)+= smp.o smp_spin_table.o
topology.o
+ifdef CONFIG_SMP
+arm64-obj-$(CONFIG_ARCH_QCOM) += qcom-special-cpu-ops-dont-copy-this.o
+endif
arm64-obj-$(CONFIG_PERF_EVENTS)+= perf_regs.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
index cce9524..d002168 100644
--- a/arch/arm64/kernel/cpu_ops.c
+++ b/arch/arm64/kernel/cpu_ops.c
@@ -24,6 +24,7 @@
extern const struct cpu_operations smp_spin_table_ops;
extern const struct cpu_operations cpu_psci_ops;
+extern const struct cpu_operations qcom_cortex_a_ops;
const struct cpu_operations *cpu_ops[NR_CPUS];
@@ -32,6 +33,9 @@ static const struct cpu_operations *supported_cpu_ops[]
__initconst = {
smp_spin_table_ops,
#endif
cpu_psci_ops,
+#ifdef CONFIG_ARCH_QCOM
+ qcom_cortex_a_ops,
+#endif
NULL,
};
diff --git a/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
b/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
new file mode 100644
index 000..11995d6
--- /dev/null
+++ b/arch/arm64/kernel/qcom-special-cpu-ops-dont-copy-this.c
@@ -0,0 +1,329 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* MSM ARMv8 CPU Operations
+ * Based on arch/arm64/kernel/smp_spin_table.c
+ */
+
+#include linux
[RFC PATCH v2 2/4] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 466 +
3 files changed, 471 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 610965dd..11e97d8 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -180,6 +180,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool Qualcomm Platforms
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..72b75d6
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,466 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include linux/cpumask.h
+#include linux/delay.h
+#include linux/mutex.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/qcom_scm.h
+
+#include asm/cacheflush.h
+#include asm/compiler.h
+#include asm/smp_plat.h
+
+#include qcom_scm.h
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) 0xFF) 8) | ((c) 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) 0xff) 4) | \
+ (((b) 0xff) 6) | \
+ (((c) 0xff) 8) | \
+ (((d) 0xff) 10) | \
+ (((e) 0xff) 12) | \
+ (((f) 0xff) 14) | \
+ (((g) 0xff) 16) | \
+ (((h) 0xff) 18) | \
+ (((i) 0xff) 20) | \
+ (((j) 0xff) 22) | \
+ (num 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_ENOMEM-5
+#define QCOM_SCM_EOPNOTSUPP-4
+#define QCOM_SCM_EINVAL_ADDR -3
+#define QCOM_SCM_EINVAL_ARG-2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED 1
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+#define R0_STR x0
+#define R1_STR x1
+#define R2_STR x2
+#define R3_STR x3
+#define R4_STR x4
+#define R5_STR x5
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+ return -EIO;
+ case QCOM_SCM_EINVAL_ADDR:
+ case QCOM_SCM_EINVAL_ARG:
+ return -EINVAL
[RFC PATCH v2 1/4] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c = qcom_scm-32.c} | 15 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 29 ++
4 files changed, 42 insertions(+), 447 deletions(-)
copy drivers/firmware/{qcom_scm.c = qcom_scm-32.c} (96%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 96%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..89be15e 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,6 +27,7 @@
#include asm/outercache.h
#include asm/cacheflush.h
+#include qcom_scm.h
#define QCOM_SCM_ENOMEM-5
#define QCOM_SCM_EOPNOTSUPP-4
@@ -386,8 +387,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +411,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +434,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +443,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +471,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +480,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include linux/slab.h
-#include linux/io.h
-#include linux/module.h
-#include linux/mutex.h
-#include linux/errno.h
-#include linux/err.h
+#include linux/cpumask.h
+#include linux/export.h
+#include linux/types.h
#include linux/qcom_scm.h
-#include asm/outercache.h
-#include asm/cacheflush.h
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU20x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU30x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU00x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU10x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU20x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU30x40
[RFC PATCH 2/5] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala
---
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 466 +
3 files changed, 471 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 610965dd..11e97d8 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -180,6 +180,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool "Qualcomm Platforms"
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..72b75d6
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,466 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "qcom_scm.h"
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) & 0xFF) << 8) | ((c) & 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) & 0xff) << 4) | \
+ (((b) & 0xff) << 6) | \
+ (((c) & 0xff) << 8) | \
+ (((d) & 0xff) << 10) | \
+ (((e) & 0xff) << 12) | \
+ (((f) & 0xff) << 14) | \
+ (((g) & 0xff) << 16) | \
+ (((h) & 0xff) << 18) | \
+ (((i) & 0xff) << 20) | \
+ (((j) & 0xff) << 22) | \
+ (num & 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_ENOMEM-5
+#define QCOM_SCM_EOPNOTSUPP-4
+#define QCOM_SCM_EINVAL_ADDR -3
+#define QCOM_SCM_EINVAL_ARG-2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED 1
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+#define R0_STR "x0"
+#define R1_STR "x1"
+#define R2_STR "x2"
+#define R3_STR "x3"
+#define R4_STR "x4"
+#define R5_STR "x5"
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+
[RFC PATCH 3/5] arm64: introduce CPU_OF_TABLES for cpu ops selection
From: Abhimanyu Kapur
Add support to arm64 to provide a dt-based method to allow soc-vendors to
supply cpu_ops. Also move psci and smp_spin_table ops to use CPU_OF_TABLES.
Signed-off-by: Abhimanyu Kapur
Signed-off-by: Kumar Gala
---
arch/arm64/include/asm/cpu_ops.h | 5 +
arch/arm64/kernel/cpu_ops.c| 27 +--
arch/arm64/kernel/psci.c | 1 +
arch/arm64/kernel/smp_spin_table.c | 3 ++-
4 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
index da301ee..a7efab8 100644
--- a/arch/arm64/include/asm/cpu_ops.h
+++ b/arch/arm64/include/asm/cpu_ops.h
@@ -67,4 +67,9 @@ extern const struct cpu_operations *cpu_ops[NR_CPUS];
int __init cpu_read_ops(struct device_node *dn, int cpu);
void __init cpu_read_bootcpu_ops(void);
+#define CPU_METHOD_OF_DECLARE(name, __ops) \
+ static const struct cpu_operations *__cpu_method_table_##name \
+ __used __section(__cpu_method_of_table) \
+ = __ops;
+
#endif /* ifndef __ASM_CPU_OPS_H */
diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
index cce9524..ad33f98 100644
--- a/arch/arm64/kernel/cpu_ops.c
+++ b/arch/arm64/kernel/cpu_ops.c
@@ -22,29 +22,20 @@
#include
#include
-extern const struct cpu_operations smp_spin_table_ops;
-extern const struct cpu_operations cpu_psci_ops;
-
const struct cpu_operations *cpu_ops[NR_CPUS];
-static const struct cpu_operations *supported_cpu_ops[] __initconst = {
-#ifdef CONFIG_SMP
- _spin_table_ops,
-#endif
- _psci_ops,
- NULL,
-};
+extern struct cpu_operations __cpu_method_of_table[];
+static const struct cpu_operations *__cpu_method_of_table_sentinel
+ __used __section(__cpu_method_of_table_end);
-static const struct cpu_operations * __init cpu_get_ops(const char *name)
+const struct cpu_operations * __init cpu_get_ops(const char *name)
{
- const struct cpu_operations **ops = supported_cpu_ops;
-
- while (*ops) {
- if (!strcmp(name, (*ops)->name))
- return *ops;
+ const struct cpu_operations **start = (void *)__cpu_method_of_table;
- ops++;
- }
+ for (; *start; start++) {
+ if (!strcmp((*start)->name, name))
+ return *start;
+ };
return NULL;
}
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
index 9b8a70a..2f255c7 100644
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -523,3 +523,4 @@ const struct cpu_operations cpu_psci_ops = {
#endif
};
+CPU_METHOD_OF_DECLARE(psci, _psci_ops);
diff --git a/arch/arm64/kernel/smp_spin_table.c
b/arch/arm64/kernel/smp_spin_table.c
index 14944e5..b41a8b4 100644
--- a/arch/arm64/kernel/smp_spin_table.c
+++ b/arch/arm64/kernel/smp_spin_table.c
@@ -119,9 +119,10 @@ static int smp_spin_table_cpu_boot(unsigned int cpu)
return 0;
}
-const struct cpu_operations smp_spin_table_ops = {
+static const struct cpu_operations smp_spin_table_ops = {
.name = "spin-table",
.cpu_init = smp_spin_table_cpu_init,
.cpu_prepare= smp_spin_table_cpu_prepare,
.cpu_boot = smp_spin_table_cpu_boot,
};
+CPU_METHOD_OF_DECLARE(spin_table, _spin_table_ops);
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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[RFC PATCH 5/5] arm64: qcom: add cpu operations
From: Abhimanyu Kapur
Add qcom cpu operations for arm-v8 cpus. Implement secondary cpu boot ops
As a part of this change update device tree documentation for:
1. Arm cortex-a ACC device which provides percpu reg
2. Armv8 cortex-a compatible string in arm/cpus.txt
Signed-off-by: Abhimanyu Kapur
Signed-off-by: Kumar Gala
---
Documentation/devicetree/bindings/arm/cpus.txt| 2 +
Documentation/devicetree/bindings/arm/msm/acc.txt | 19 ++
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/cpu_ops.c| 343 ++
4 files changed, 365 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/acc.txt
create mode 100644 drivers/soc/qcom/cpu_ops.c
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 8b9e0a9..35cabe5 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,8 @@ nodes to be present and contain the properties described
below.
be one of:
"psci"
"spin-table"
+"qcom,arm-cortex-acc"
+
# On ARM 32-bit systems this property is optional and
can be one of:
"allwinner,sun6i-a31"
diff --git a/Documentation/devicetree/bindings/arm/msm/acc.txt
b/Documentation/devicetree/bindings/arm/msm/acc.txt
new file mode 100644
index 000..ae2d725
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/acc.txt
@@ -0,0 +1,19 @@
+Application Processor Sub-system (APSS) Application Clock Controller (ACC)
+
+The ACC provides clock, power domain, and reset control to a CPU. There is one
ACC
+register region per CPU within the APSS remapped region as well as an alias
register
+region that remaps accesses to the ACC associated with the CPU accessing the
region.
+
+Required properties:
+- compatible: Must be "qcom,arm-cortex-acc"
+- reg: The first element specifies the base address and size of
+ the register region. An optional second element
specifies
+ the base address and size of the alias register region.
+
+Example:
+
+ clock-controller@b088000 {
+ compatible = "qcom,arm-cortex-acc";
+ reg = <0x0b088000 0x1000>,
+ <0x0b008000 0x1000>;
+ }
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 4389012..bb6030a 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_ARM64)+= cpu_ops.o
obj-$(CONFIG_QCOM_GSBI)+= qcom_gsbi.o
diff --git a/drivers/soc/qcom/cpu_ops.c b/drivers/soc/qcom/cpu_ops.c
new file mode 100644
index 000..d831cb0
--- /dev/null
+++ b/drivers/soc/qcom/cpu_ops.c
@@ -0,0 +1,343 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* MSM ARMv8 CPU Operations
+ * Based on arch/arm64/kernel/smp_spin_table.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+static DEFINE_RAW_SPINLOCK(boot_lock);
+
+DEFINE_PER_CPU(int, cold_boot_done);
+
+#if 0
+static int cold_boot_flags[] = {
+ 0,
+ QCOM_SCM_FLAG_COLDBOOT_CPU1,
+ QCOM_SCM_FLAG_COLDBOOT_CPU2,
+ QCOM_SCM_FLAG_COLDBOOT_CPU3,
+};
+#endif
+
+/* CPU power domain register offsets */
+#define CPU_PWR_CTL0x4
+#define CPU_PWR_GATE_CTL 0x14
+#define LDO_BHS_PWR_CTL0x28
+
+/* L2 power domain register offsets */
+#define L2_PWR_CTL_OVERRIDE0xc
+#define L2_PWR_CTL 0x14
+#define L2_PWR_STATUS 0x18
+#defineL2_CORE_CBCR0x58
+#define L1_RST_DIS 0x284
+
+#define L2_SPM_STS 0xc
+#define L2_VREG_CTL0x1c
+
+#define SCM_IO_READ1
+#define SCM_IO_WRITE 2
+
+/*
+ * struct msm_l2ccc_of_info: represents of data for l2 cache clock controller.
+ * @compat: compat string for l2 cache clock controller
+ * @l2_pon: l2 cache power on routine
+ */
+struct msm_l2ccc_of_info {
+ const char *compat;
+ int (*l2_power_on) (struct device_node *dn, u32 l2_mask, int cpu);
+ u32 l2_p
[RFC PATCH 4/5] arm64: smp: move the pen to a header file
From: Abhimanyu Kapur
Move the secondary_pen_release variable and the secondary_holding_pen
entry function to asm/smp_plat.h so that the other cpu ops implementations
can share them.
Signed-off-by: Abhimanyu Kapur
Signed-off-by: Kumar Gala
---
arch/arm64/include/asm/smp_plat.h | 2 ++
arch/arm64/kernel/smp.c| 1 +
arch/arm64/kernel/smp_spin_table.c | 3 ---
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/smp_plat.h
b/arch/arm64/include/asm/smp_plat.h
index 59e2823..235ff04 100644
--- a/arch/arm64/include/asm/smp_plat.h
+++ b/arch/arm64/include/asm/smp_plat.h
@@ -34,10 +34,12 @@ static inline u32 mpidr_hash_size(void)
return 1 << mpidr_hash.bits;
}
+extern void secondary_holding_pen(void);
/*
* Logical CPU mapping.
*/
extern u64 __cpu_logical_map[NR_CPUS];
#define cpu_logical_map(cpu)__cpu_logical_map[cpu]
+extern volatile unsigned long secondary_holding_pen_release;
#endif /* __ASM_SMP_PLAT_H */
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 328b8ce..4ce1f23 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -61,6 +61,7 @@
* where to place its SVC stack
*/
struct secondary_data secondary_data;
+volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
enum ipi_msg_type {
IPI_RESCHEDULE,
diff --git a/arch/arm64/kernel/smp_spin_table.c
b/arch/arm64/kernel/smp_spin_table.c
index b41a8b4..be833b9 100644
--- a/arch/arm64/kernel/smp_spin_table.c
+++ b/arch/arm64/kernel/smp_spin_table.c
@@ -28,9 +28,6 @@
#include
#include
-extern void secondary_holding_pen(void);
-volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
-
static phys_addr_t cpu_release_addr[NR_CPUS];
/*
--
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm SoCs. To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM interfaces to setup the boot/release addresses for the secondary CPUs. In addition we need a uniquie set of cpu ops. I'm aware the desired methods for booting secondary CPUs is either via spintable or PSCI. However, these SoCs are shipping with a firmware that does not support those methods. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 1/5] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala
---
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c => qcom_scm-32.c} | 15 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 29 ++
4 files changed, 42 insertions(+), 447 deletions(-)
copy drivers/firmware/{qcom_scm.c => qcom_scm-32.c} (96%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 96%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..89be15e 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,6 +27,7 @@
#include
#include
+#include "qcom_scm.h"
#define QCOM_SCM_ENOMEM-5
#define QCOM_SCM_EOPNOTSUPP-4
@@ -386,8 +387,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +411,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +434,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +443,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +471,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +480,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags & QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include
-#include
-#include
-#include
-#include
-#include
+#include
+#include
+#include
#include
-#include
-#include
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU20x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU30x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU00x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU10x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU20x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU30x40
-
-struct qcom_scm_entry {
- int flag;
- void *entry;
-};
-
-static struct qcom_scm_entry qcom_scm_wb[] = {
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
- { .flag = QCOM_SC
[RFC PATCH 3/5] arm64: introduce CPU_OF_TABLES for cpu ops selection
From: Abhimanyu Kapur abhim...@codeaurora.org
Add support to arm64 to provide a dt-based method to allow soc-vendors to
supply cpu_ops. Also move psci and smp_spin_table ops to use CPU_OF_TABLES.
Signed-off-by: Abhimanyu Kapur abhim...@codeaurora.org
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm64/include/asm/cpu_ops.h | 5 +
arch/arm64/kernel/cpu_ops.c| 27 +--
arch/arm64/kernel/psci.c | 1 +
arch/arm64/kernel/smp_spin_table.c | 3 ++-
4 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
index da301ee..a7efab8 100644
--- a/arch/arm64/include/asm/cpu_ops.h
+++ b/arch/arm64/include/asm/cpu_ops.h
@@ -67,4 +67,9 @@ extern const struct cpu_operations *cpu_ops[NR_CPUS];
int __init cpu_read_ops(struct device_node *dn, int cpu);
void __init cpu_read_bootcpu_ops(void);
+#define CPU_METHOD_OF_DECLARE(name, __ops) \
+ static const struct cpu_operations *__cpu_method_table_##name \
+ __used __section(__cpu_method_of_table) \
+ = __ops;
+
#endif /* ifndef __ASM_CPU_OPS_H */
diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
index cce9524..ad33f98 100644
--- a/arch/arm64/kernel/cpu_ops.c
+++ b/arch/arm64/kernel/cpu_ops.c
@@ -22,29 +22,20 @@
#include linux/of.h
#include linux/string.h
-extern const struct cpu_operations smp_spin_table_ops;
-extern const struct cpu_operations cpu_psci_ops;
-
const struct cpu_operations *cpu_ops[NR_CPUS];
-static const struct cpu_operations *supported_cpu_ops[] __initconst = {
-#ifdef CONFIG_SMP
- smp_spin_table_ops,
-#endif
- cpu_psci_ops,
- NULL,
-};
+extern struct cpu_operations __cpu_method_of_table[];
+static const struct cpu_operations *__cpu_method_of_table_sentinel
+ __used __section(__cpu_method_of_table_end);
-static const struct cpu_operations * __init cpu_get_ops(const char *name)
+const struct cpu_operations * __init cpu_get_ops(const char *name)
{
- const struct cpu_operations **ops = supported_cpu_ops;
-
- while (*ops) {
- if (!strcmp(name, (*ops)-name))
- return *ops;
+ const struct cpu_operations **start = (void *)__cpu_method_of_table;
- ops++;
- }
+ for (; *start; start++) {
+ if (!strcmp((*start)-name, name))
+ return *start;
+ };
return NULL;
}
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
index 9b8a70a..2f255c7 100644
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -523,3 +523,4 @@ const struct cpu_operations cpu_psci_ops = {
#endif
};
+CPU_METHOD_OF_DECLARE(psci, cpu_psci_ops);
diff --git a/arch/arm64/kernel/smp_spin_table.c
b/arch/arm64/kernel/smp_spin_table.c
index 14944e5..b41a8b4 100644
--- a/arch/arm64/kernel/smp_spin_table.c
+++ b/arch/arm64/kernel/smp_spin_table.c
@@ -119,9 +119,10 @@ static int smp_spin_table_cpu_boot(unsigned int cpu)
return 0;
}
-const struct cpu_operations smp_spin_table_ops = {
+static const struct cpu_operations smp_spin_table_ops = {
.name = spin-table,
.cpu_init = smp_spin_table_cpu_init,
.cpu_prepare= smp_spin_table_cpu_prepare,
.cpu_boot = smp_spin_table_cpu_boot,
};
+CPU_METHOD_OF_DECLARE(spin_table, smp_spin_table_ops);
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 2/5] firmware: qcom: scm: Add support for ARM64 SoCs
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 466 +
3 files changed, 471 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 610965dd..11e97d8 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -180,6 +180,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool Qualcomm Platforms
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND)+= iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 000..72b75d6
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,466 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include linux/cpumask.h
+#include linux/delay.h
+#include linux/mutex.h
+#include linux/slab.h
+#include linux/types.h
+#include linux/qcom_scm.h
+
+#include asm/cacheflush.h
+#include asm/compiler.h
+#include asm/smp_plat.h
+
+#include qcom_scm.h
+
+#define QCOM_SCM_SIP_FNID(s, c) (s) 0xFF) 8) | ((c) 0xFF)) |
0x0200)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) 0xff) 4) | \
+ (((b) 0xff) 6) | \
+ (((c) 0xff) 8) | \
+ (((d) 0xff) 10) | \
+ (((e) 0xff) 12) | \
+ (((f) 0xff) 14) | \
+ (((g) 0xff) 16) | \
+ (((h) 0xff) 18) | \
+ (((i) 0xff) 20) | \
+ (((j) 0xff) 22) | \
+ (num 0x))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_ENOMEM-5
+#define QCOM_SCM_EOPNOTSUPP-4
+#define QCOM_SCM_EINVAL_ADDR -3
+#define QCOM_SCM_EINVAL_ARG-2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED 1
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x4000
+#define SMC_ATOMIC_MASK 0x8000
+#define IS_CALL_AVAIL_CMD 1
+
+#define R0_STR x0
+#define R1_STR x1
+#define R2_STR x2
+#define R3_STR x3
+#define R4_STR x4
+#define R5_STR x5
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+ return -EIO;
+ case QCOM_SCM_EINVAL_ADDR:
+ case QCOM_SCM_EINVAL_ARG:
+ return -EINVAL
[RFC PATCH 0/5] Add smp booting support for Qualcomm ARMv8 SoCs
This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm SoCs. To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM interfaces to setup the boot/release addresses for the secondary CPUs. In addition we need a uniquie set of cpu ops. I'm aware the desired methods for booting secondary CPUs is either via spintable or PSCI. However, these SoCs are shipping with a firmware that does not support those methods. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 1/5] firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c = qcom_scm-32.c} | 15 +-
drivers/firmware/qcom_scm.c| 442 +
drivers/firmware/qcom_scm.h| 29 ++
4 files changed, 42 insertions(+), 447 deletions(-)
copy drivers/firmware/{qcom_scm.c = qcom_scm-32.c} (96%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 96%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..89be15e 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,6 +27,7 @@
#include asm/outercache.h
#include asm/cacheflush.h
+#include qcom_scm.h
#define QCOM_SCM_ENOMEM-5
#define QCOM_SCM_EOPNOTSUPP-4
@@ -386,8 +387,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +411,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +434,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const
cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +443,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +471,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const
cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +480,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include linux/slab.h
-#include linux/io.h
-#include linux/module.h
-#include linux/mutex.h
-#include linux/errno.h
-#include linux/err.h
+#include linux/cpumask.h
+#include linux/export.h
+#include linux/types.h
#include linux/qcom_scm.h
-#include asm/outercache.h
-#include asm/cacheflush.h
-
-
-#define QCOM_SCM_ENOMEM-5
-#define QCOM_SCM_EOPNOTSUPP-4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG-2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU00x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU10x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU20x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU30x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU00x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU10x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU20x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU30x40
[RFC PATCH 5/5] arm64: qcom: add cpu operations
From: Abhimanyu Kapur abhim...@codeaurora.org
Add qcom cpu operations for arm-v8 cpus. Implement secondary cpu boot ops
As a part of this change update device tree documentation for:
1. Arm cortex-a ACC device which provides percpu reg
2. Armv8 cortex-a compatible string in arm/cpus.txt
Signed-off-by: Abhimanyu Kapur abhim...@codeaurora.org
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
Documentation/devicetree/bindings/arm/cpus.txt| 2 +
Documentation/devicetree/bindings/arm/msm/acc.txt | 19 ++
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/cpu_ops.c| 343 ++
4 files changed, 365 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/acc.txt
create mode 100644 drivers/soc/qcom/cpu_ops.c
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 8b9e0a9..35cabe5 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,8 @@ nodes to be present and contain the properties described
below.
be one of:
psci
spin-table
+qcom,arm-cortex-acc
+
# On ARM 32-bit systems this property is optional and
can be one of:
allwinner,sun6i-a31
diff --git a/Documentation/devicetree/bindings/arm/msm/acc.txt
b/Documentation/devicetree/bindings/arm/msm/acc.txt
new file mode 100644
index 000..ae2d725
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/acc.txt
@@ -0,0 +1,19 @@
+Application Processor Sub-system (APSS) Application Clock Controller (ACC)
+
+The ACC provides clock, power domain, and reset control to a CPU. There is one
ACC
+register region per CPU within the APSS remapped region as well as an alias
register
+region that remaps accesses to the ACC associated with the CPU accessing the
region.
+
+Required properties:
+- compatible: Must be qcom,arm-cortex-acc
+- reg: The first element specifies the base address and size of
+ the register region. An optional second element
specifies
+ the base address and size of the alias register region.
+
+Example:
+
+ clock-controller@b088000 {
+ compatible = qcom,arm-cortex-acc;
+ reg = 0x0b088000 0x1000,
+ 0x0b008000 0x1000;
+ }
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 4389012..bb6030a 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_ARM64)+= cpu_ops.o
obj-$(CONFIG_QCOM_GSBI)+= qcom_gsbi.o
diff --git a/drivers/soc/qcom/cpu_ops.c b/drivers/soc/qcom/cpu_ops.c
new file mode 100644
index 000..d831cb0
--- /dev/null
+++ b/drivers/soc/qcom/cpu_ops.c
@@ -0,0 +1,343 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* MSM ARMv8 CPU Operations
+ * Based on arch/arm64/kernel/smp_spin_table.c
+ */
+
+#include linux/bitops.h
+#include linux/cpu.h
+#include linux/cpumask.h
+#include linux/delay.h
+#include linux/init.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/smp.h
+#include linux/qcom_scm.h
+
+#include asm/barrier.h
+#include asm/cacheflush.h
+#include asm/cpu_ops.h
+#include asm/cputype.h
+#include asm/smp_plat.h
+
+static DEFINE_RAW_SPINLOCK(boot_lock);
+
+DEFINE_PER_CPU(int, cold_boot_done);
+
+#if 0
+static int cold_boot_flags[] = {
+ 0,
+ QCOM_SCM_FLAG_COLDBOOT_CPU1,
+ QCOM_SCM_FLAG_COLDBOOT_CPU2,
+ QCOM_SCM_FLAG_COLDBOOT_CPU3,
+};
+#endif
+
+/* CPU power domain register offsets */
+#define CPU_PWR_CTL0x4
+#define CPU_PWR_GATE_CTL 0x14
+#define LDO_BHS_PWR_CTL0x28
+
+/* L2 power domain register offsets */
+#define L2_PWR_CTL_OVERRIDE0xc
+#define L2_PWR_CTL 0x14
+#define L2_PWR_STATUS 0x18
+#defineL2_CORE_CBCR0x58
+#define L1_RST_DIS 0x284
+
+#define L2_SPM_STS 0xc
+#define L2_VREG_CTL0x1c
+
+#define SCM_IO_READ1
+#define SCM_IO_WRITE 2
+
+/*
+ * struct msm_l2ccc_of_info: represents of data for l2 cache clock controller.
+ * @compat: compat string for l2 cache clock controller
+ * @l2_pon: l2 cache
[RFC PATCH 4/5] arm64: smp: move the pen to a header file
From: Abhimanyu Kapur abhim...@codeaurora.org
Move the secondary_pen_release variable and the secondary_holding_pen
entry function to asm/smp_plat.h so that the other cpu ops implementations
can share them.
Signed-off-by: Abhimanyu Kapur abhim...@codeaurora.org
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm64/include/asm/smp_plat.h | 2 ++
arch/arm64/kernel/smp.c| 1 +
arch/arm64/kernel/smp_spin_table.c | 3 ---
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/smp_plat.h
b/arch/arm64/include/asm/smp_plat.h
index 59e2823..235ff04 100644
--- a/arch/arm64/include/asm/smp_plat.h
+++ b/arch/arm64/include/asm/smp_plat.h
@@ -34,10 +34,12 @@ static inline u32 mpidr_hash_size(void)
return 1 mpidr_hash.bits;
}
+extern void secondary_holding_pen(void);
/*
* Logical CPU mapping.
*/
extern u64 __cpu_logical_map[NR_CPUS];
#define cpu_logical_map(cpu)__cpu_logical_map[cpu]
+extern volatile unsigned long secondary_holding_pen_release;
#endif /* __ASM_SMP_PLAT_H */
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 328b8ce..4ce1f23 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -61,6 +61,7 @@
* where to place its SVC stack
*/
struct secondary_data secondary_data;
+volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
enum ipi_msg_type {
IPI_RESCHEDULE,
diff --git a/arch/arm64/kernel/smp_spin_table.c
b/arch/arm64/kernel/smp_spin_table.c
index b41a8b4..be833b9 100644
--- a/arch/arm64/kernel/smp_spin_table.c
+++ b/arch/arm64/kernel/smp_spin_table.c
@@ -28,9 +28,6 @@
#include asm/io.h
#include asm/smp_plat.h
-extern void secondary_holding_pen(void);
-volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
-
static phys_addr_t cpu_release_addr[NR_CPUS];
/*
--
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Re: [PATCH] arm64: dts: Add Qualcomm APQ8016 SBC evaluation board dts
On Apr 3, 2015, at 1:18 PM, Olof Johansson wrote: > On Fri, Apr 03, 2015 at 11:14:01AM -0700, Olof Johansson wrote: >> On Fri, Apr 03, 2015 at 11:12:17AM -0700, Olof Johansson wrote: >>> On Mon, Mar 23, 2015 at 05:51:05PM -0500, Kumar Gala wrote: >>>> Add initial device tree support for Qualcomm APQ8016 SBC Evaluation board. >>>> This board is also referred to as the DragonBoard 410c. >>>> >>>> Signed-off-by: Kumar Gala >>> >>> Hi, >>> >>> Patch applied but see comment below. >> >> You both sent us the patch and a pull request with this patch in >> it. Please only send patches to a...@kernel.org that you intend for us >> to apply. > > Uh, need more coffee, please ignore. I got confused since your patch didn't > apply cleanly due to the dts/qcom directory creation. > > > -Olof Ok, but this should be part of the 'qcom-dt-for-4.1’ so hopefully you will end up pulling all of that in as well - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] arm64: dts: Add Qualcomm APQ8016 SBC evaluation board dts
On Apr 3, 2015, at 1:18 PM, Olof Johansson o...@lixom.net wrote: On Fri, Apr 03, 2015 at 11:14:01AM -0700, Olof Johansson wrote: On Fri, Apr 03, 2015 at 11:12:17AM -0700, Olof Johansson wrote: On Mon, Mar 23, 2015 at 05:51:05PM -0500, Kumar Gala wrote: Add initial device tree support for Qualcomm APQ8016 SBC Evaluation board. This board is also referred to as the DragonBoard 410c. Signed-off-by: Kumar Gala ga...@codeaurora.org Hi, Patch applied but see comment below. You both sent us the patch and a pull request with this patch in it. Please only send patches to a...@kernel.org that you intend for us to apply. Uh, need more coffee, please ignore. I got confused since your patch didn't apply cleanly due to the dts/qcom directory creation. -Olof Ok, but this should be part of the 'qcom-dt-for-4.1’ so hopefully you will end up pulling all of that in as well - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [GIT PULL] qcom SoC changes for v4.1
On Apr 2, 2015, at 3:37 AM, Nicolas Dechesne wrote: > Andy, Kumar, > > On Mon, Mar 16, 2015 at 10:03 PM, Kumar Gala wrote: >> Andy Gross (1): >> soc: qcom: gsbi: Add support for ADM CRCI muxing > > this commit seems to break the boot on IFC6410, it was initially > reported on kernelci.org, see report and bootlog [1]. > > running git bisect led me to: > > e5fdad68d47ed344832b7ca4e18b2e9708d8141e is the first bad commit > commit e5fdad68d47ed344832b7ca4e18b2e9708d8141e > Author: Andy Gross > Date: Mon Feb 9 16:01:06 2015 -0600 > >soc: qcom: gsbi: Add support for ADM CRCI muxing > >This patch adds automatic configuration for the ADM CRCI muxing required to >support DMA operations for GSBI clients. The GSBI mode and > instance determine >the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA >works properly. > >Signed-off-by: Andy Gross >Signed-off-by: Kumar Gala > > > [1] > http://kernelci.org/boot/all/job/arm-soc/kernel/v4.0-rc4-354-ga0690e6586df/ I think we need to associated DT updates. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [GIT PULL] qcom SoC changes for v4.1
On Apr 2, 2015, at 3:37 AM, Nicolas Dechesne nicolas.deche...@linaro.org wrote: Andy, Kumar, On Mon, Mar 16, 2015 at 10:03 PM, Kumar Gala ga...@codeaurora.org wrote: Andy Gross (1): soc: qcom: gsbi: Add support for ADM CRCI muxing this commit seems to break the boot on IFC6410, it was initially reported on kernelci.org, see report and bootlog [1]. running git bisect led me to: e5fdad68d47ed344832b7ca4e18b2e9708d8141e is the first bad commit commit e5fdad68d47ed344832b7ca4e18b2e9708d8141e Author: Andy Gross agr...@codeaurora.org Date: Mon Feb 9 16:01:06 2015 -0600 soc: qcom: gsbi: Add support for ADM CRCI muxing This patch adds automatic configuration for the ADM CRCI muxing required to support DMA operations for GSBI clients. The GSBI mode and instance determine the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA works properly. Signed-off-by: Andy Gross agr...@codeaurora.org Signed-off-by: Kumar Gala ga...@codeaurora.org [1] http://kernelci.org/boot/all/job/arm-soc/kernel/v4.0-rc4-354-ga0690e6586df/ I think we need to associated DT updates. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 5/7] arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes
On Apr 1, 2015, at 10:05 AM, Ivan T. Ivanov wrote:
> PM9816 has 2 SPMI devices per physical package. Add PMIC configuration
> nodes including sub-function device nodes and include them in boards,
> which are using 8x16 based chipset.
>
> PM9816 sub-function devices include:
>
> * GPIO block, with 4 pins
> * MPP block, with 4 pins
> * Volatage ADC (VADC), with multiple inputs
> * Thermal sensor device, which is using on chip VADC
> channel report PMIC die temperature.
> * Power key device, which is responsible for clean system
> reboot or shutdown
> * RTC device
>
> Signed-off-by: Ivan T. Ivanov
> ---
> arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 +
> arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 1 +
> arch/arm64/boot/dts/qcom/pm8916.dtsi | 93 +++
> 3 files changed, 95 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> index 703a4f1..58f0055f 100644
> --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> @@ -12,6 +12,7 @@
> */
>
> #include "msm8916.dtsi"
> +#include "pm8916.dtsi"
>
> / {
> aliases {
> diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
> b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
> index bea871b..a1aa0b2 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
> @@ -12,6 +12,7 @@
> */
>
> #include "msm8916.dtsi"
> +#include "pm8916.dtsi"
>
> / {
> aliases {
> diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi
> b/arch/arm64/boot/dts/qcom/pm8916.dtsi
> new file mode 100644
> index 000..2a5ad2c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
> @@ -0,0 +1,93 @@
> +#include
> +#include
> +#include
> +
> +_bus {
> +
> + usid0: pm8916@0 {
> + compatible ="qcom,spmi-pmic";
> + reg = <0x0 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + rtc@6000 {
> + compatible = "qcom,pm8941-rtc";
> + reg = <0x6000 0x6100>;
> + reg-names = "rtc", "alarm";
> + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> + pwrkey@800 {
> + compatible = "qcom,pm8941-pwrkey";
> + reg = <0x800>;
> + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> + debounce = <15625>;
> + bias-pull-up;
> + };
> +
> + pm8916_gpios: gpios@c000 {
> + compatible = "qcom,pm8916-gpio";
> + reg = <0xc000 0x400>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <0 0xc0 0 0>, <0 0xc1 0 0>, <0 0xc2 0 0>,
> <0 0xc3 0 0>;
please cleanup level/edge cell values to use defines
> + };
> +
> + pm8916_mpps: mpps@a000 {
> + compatible = "qcom,pm8916-mpp";
> + reg = <0xa000 0x400>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <0 0xa0 0 0>, <0 0xa1 0 0>, <0 0xa2 0 0>,
> <0 0xa3 0 0>;
please cleanup level/edge cell values to use defines
> + };
> +
> + pm8916_temp: temp-alarm@2400 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0x2400 0x100>;
> + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
> + io-channels = <_vadc VADC_DIE_TEMP>;
> + io-channel-names = "thermal";
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pm8916_vadc: vadc@3100 {
> + compatible = "qcom,spmi-vadc";
> + reg = <0x3100 0x100>;
> + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> +
> + usb_in {
> + reg = ;
> + qcom,pre-scaling = <1 10>;
> + };
> + vph_pwr {
> + reg = ;
> + qcom,pre-scaling = <1 3>;
> + };
> + die_temp {
> + reg = ;
> + };
> + ref_625mv {
> + reg = ;
> + };
> + ref_1250v {
> + reg = ;
> + };
> + ref_gnd {
> + reg = ;
> + };
> + ref_vdd {
> +
Re: [PATCH 4/7] arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916
On Apr 1, 2015, at 10:05 AM, Ivan T. Ivanov wrote:
> Add SPMI PMIC Arbiter configuration nodes for MSM8916.
>
> Signed-off-by: Ivan T. Ivanov
> ---
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index f212b83..02a4916 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -192,5 +192,23 @@
> status = "disabled";
> };
> };
> +
> + spmi_bus: spmi@200f000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x200f000 0x1000>,
> + <0x240 0x40>,
> + <0x2c0 0x40>,
> + <0x380 0x20>,
> + <0x200a000 0x2100>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = <0 190 0>;
please cleanup level/edge cell values to use defines
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + };
> };
> };
> --
> 1.9.1
>
--
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Re: [PATCH 2/7] ARM: dts: qcom: Add PM8941 functions device nodes
On Apr 1, 2015, at 10:05 AM, Ivan T. Ivanov wrote: > Add configuration nodes for following devices: > > * GPIO block, with 36 pins > * MPP block, with 8 pins > * Current ADC (IADC) > * Volatage ADC (VADC), with multiple inputs > * Thermal sensor device, which is using on chip VADC > channel report PMIC die temperature > * Power key device, which is responsible for clean system > reboot or shutdown > * White LED device > * RTC device > > Signed-off-by: Ivan T. Ivanov > --- > arch/arm/boot/dts/qcom-pm8941.dtsi | 98 ++ > 1 file changed, 98 insertions(+) please cleanup level/edge cell values to use defines - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/7] ARM: dts: qcom: Add PM8841 functions device nodes
On Apr 1, 2015, at 10:05 AM, Ivan T. Ivanov wrote:
> Add configuration nodes for multi purpose pins and
> thermal sensor devices. Thermal sensor will report
> PMIC die temperature.
>
> Signed-off-by: Ivan T. Ivanov
> ---
> arch/arm/boot/dts/qcom-pm8841.dtsi | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi
> b/arch/arm/boot/dts/qcom-pm8841.dtsi
> index 73813cc..5c109bd 100644
> --- a/arch/arm/boot/dts/qcom-pm8841.dtsi
> +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
> @@ -7,6 +7,20 @@
> reg = <0x4 SPMI_USID>;
> #address-cells = <1>;
> #size-cells = <0>;
> +
> + pm8841_mpps: mpps@a000 {
> + compatible = "qcom,pm8841-mpp";
> + reg = <0xa000 0x400>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>,
> <4 0xa3 0 0>;
What’s the interrupt parent here with 4 cells? Can we cleanup the last cell to
use proper define for level/edge etc.
> + };
> +
> + temp-alarm@2400 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0x2400 0x100>;
> + interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>;
> + };
> };
>
> usid5: pm8841@5 {
> --
> 1.9.1
>
--
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Re: [PATCH 1/7] ARM: dts: qcom: Add PM8841 functions device nodes
On Apr 1, 2015, at 10:05 AM, Ivan T. Ivanov ivan.iva...@linaro.org wrote:
Add configuration nodes for multi purpose pins and
thermal sensor devices. Thermal sensor will report
PMIC die temperature.
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
arch/arm/boot/dts/qcom-pm8841.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi
b/arch/arm/boot/dts/qcom-pm8841.dtsi
index 73813cc..5c109bd 100644
--- a/arch/arm/boot/dts/qcom-pm8841.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -7,6 +7,20 @@
reg = 0x4 SPMI_USID;
#address-cells = 1;
#size-cells = 0;
+
+ pm8841_mpps: mpps@a000 {
+ compatible = qcom,pm8841-mpp;
+ reg = 0xa000 0x400;
+ gpio-controller;
+ #gpio-cells = 2;
+ interrupts = 4 0xa0 0 0, 4 0xa1 0 0, 4 0xa2 0 0,
4 0xa3 0 0;
What’s the interrupt parent here with 4 cells? Can we cleanup the last cell to
use proper define for level/edge etc.
+ };
+
+ temp-alarm@2400 {
+ compatible = qcom,spmi-temp-alarm;
+ reg = 0x2400 0x100;
+ interrupts = 4 0x24 0 IRQ_TYPE_EDGE_RISING;
+ };
};
usid5: pm8841@5 {
--
1.9.1
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 4/7] arm64: dts: qcom: Add SPMI PMIC Arbiter node for MSM8916
On Apr 1, 2015, at 10:05 AM, Ivan T. Ivanov ivan.iva...@linaro.org wrote:
Add SPMI PMIC Arbiter configuration nodes for MSM8916.
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index f212b83..02a4916 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -192,5 +192,23 @@
status = disabled;
};
};
+
+ spmi_bus: spmi@200f000 {
+ compatible = qcom,spmi-pmic-arb;
+ reg = 0x200f000 0x1000,
+ 0x240 0x40,
+ 0x2c0 0x40,
+ 0x380 0x20,
+ 0x200a000 0x2100;
+ reg-names = core, chnls, obsrvr, intr, cnfg;
+ interrupt-names = periph_irq;
+ interrupts = 0 190 0;
please cleanup level/edge cell values to use defines
+ qcom,ee = 0;
+ qcom,channel = 0;
+ #address-cells = 2;
+ #size-cells = 0;
+ interrupt-controller;
+ #interrupt-cells = 4;
+ };
};
};
--
1.9.1
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 2/7] ARM: dts: qcom: Add PM8941 functions device nodes
On Apr 1, 2015, at 10:05 AM, Ivan T. Ivanov ivan.iva...@linaro.org wrote: Add configuration nodes for following devices: * GPIO block, with 36 pins * MPP block, with 8 pins * Current ADC (IADC) * Volatage ADC (VADC), with multiple inputs * Thermal sensor device, which is using on chip VADC channel report PMIC die temperature * Power key device, which is responsible for clean system reboot or shutdown * White LED device * RTC device Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org --- arch/arm/boot/dts/qcom-pm8941.dtsi | 98 ++ 1 file changed, 98 insertions(+) please cleanup level/edge cell values to use defines - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 5/7] arm64: dts: qcom: Add 8x16 chipset SPMI PMIC's nodes
On Apr 1, 2015, at 10:05 AM, Ivan T. Ivanov ivan.iva...@linaro.org wrote:
PM9816 has 2 SPMI devices per physical package. Add PMIC configuration
nodes including sub-function device nodes and include them in boards,
which are using 8x16 based chipset.
PM9816 sub-function devices include:
* GPIO block, with 4 pins
* MPP block, with 4 pins
* Volatage ADC (VADC), with multiple inputs
* Thermal sensor device, which is using on chip VADC
channel report PMIC die temperature.
* Power key device, which is responsible for clean system
reboot or shutdown
* RTC device
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 +
arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 1 +
arch/arm64/boot/dts/qcom/pm8916.dtsi | 93 +++
3 files changed, 95 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8916.dtsi
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 703a4f1..58f0055f 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -12,6 +12,7 @@
*/
#include msm8916.dtsi
+#include pm8916.dtsi
/ {
aliases {
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
index bea871b..a1aa0b2 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -12,6 +12,7 @@
*/
#include msm8916.dtsi
+#include pm8916.dtsi
/ {
aliases {
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi
b/arch/arm64/boot/dts/qcom/pm8916.dtsi
new file mode 100644
index 000..2a5ad2c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -0,0 +1,93 @@
+#include dt-bindings/iio/qcom,spmi-vadc.h
+#include dt-bindings/interrupt-controller/irq.h
+#include dt-bindings/spmi/spmi.h
+
+spmi_bus {
+
+ usid0: pm8916@0 {
+ compatible =qcom,spmi-pmic;
+ reg = 0x0 SPMI_USID;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ rtc@6000 {
+ compatible = qcom,pm8941-rtc;
+ reg = 0x6000 0x6100;
+ reg-names = rtc, alarm;
+ interrupts = 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING;
+ };
+
+ pwrkey@800 {
+ compatible = qcom,pm8941-pwrkey;
+ reg = 0x800;
+ interrupts = 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH;
+ debounce = 15625;
+ bias-pull-up;
+ };
+
+ pm8916_gpios: gpios@c000 {
+ compatible = qcom,pm8916-gpio;
+ reg = 0xc000 0x400;
+ gpio-controller;
+ #gpio-cells = 2;
+ interrupts = 0 0xc0 0 0, 0 0xc1 0 0, 0 0xc2 0 0,
0 0xc3 0 0;
please cleanup level/edge cell values to use defines
+ };
+
+ pm8916_mpps: mpps@a000 {
+ compatible = qcom,pm8916-mpp;
+ reg = 0xa000 0x400;
+ gpio-controller;
+ #gpio-cells = 2;
+ interrupts = 0 0xa0 0 0, 0 0xa1 0 0, 0 0xa2 0 0,
0 0xa3 0 0;
please cleanup level/edge cell values to use defines
+ };
+
+ pm8916_temp: temp-alarm@2400 {
+ compatible = qcom,spmi-temp-alarm;
+ reg = 0x2400 0x100;
+ interrupts = 0 0x24 0 IRQ_TYPE_EDGE_RISING;
+ io-channels = pm8916_vadc VADC_DIE_TEMP;
+ io-channel-names = thermal;
+ #thermal-sensor-cells = 0;
+ };
+
+ pm8916_vadc: vadc@3100 {
+ compatible = qcom,spmi-vadc;
+ reg = 0x3100 0x100;
+ interrupts = 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING;
+ #address-cells = 1;
+ #size-cells = 0;
+ #io-channel-cells = 1;
+
+ usb_in {
+ reg = VADC_USBIN;
+ qcom,pre-scaling = 1 10;
+ };
+ vph_pwr {
+ reg = VADC_VSYS;
+ qcom,pre-scaling = 1 3;
+ };
+ die_temp {
+ reg = VADC_DIE_TEMP;
+ };
+ ref_625mv {
+ reg = VADC_REF_625MV;
+ };
+ ref_1250v {
+ reg = VADC_REF_1250MV;
+ };
+ ref_gnd {
+ reg = VADC_GND_REF;
+ };
+ ref_vdd {
+ reg
[GIT PULL] qcom dt changes for 4.1
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539: Linux 4.0-rc1 (2015-02-22 18:21:14 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-dt-for-4.1 for you to fetch changes up to 1be95ed01c190ca74677798348306a50ad0d46c1: ARM: dts: qcom: Add idle state device nodes for 8064 (2015-03-25 16:38:16 -0500) Qualcomm ARM Based Device Tree Updates for v4.1 * Updated GIC binding to include Qualcomm GIC compatible * Added binding and updated dts for TCSR (Top Control and Status Register) * Added LCC clocks to IPQ8064/APQ8064/MSM8960 device trees * Added LPASS support to IPQ8064 device tree * Added SPMI PMIC & device support to APQ8084 and MSM8974 * Added support for MSM8916/APQ8016 SoC (64-bit) and MTP8916/SBC8016 boards * Added support for qcom,saw2 & qcom,idle-states on MSM8974/APQ8084/APQ8064 Andy Gross (5): mfd: qcom,tcsr: Add device tree binding for TCSR arm: dts: qcom: Add TCSR support for APQ8064 arm: dts: qcom: Add TCSR support for IPQ8064 arm: dts: qcom: Add TCSR support for MSM8660 arm: dts: qcom: Add TCSR support for MSM8960 Georgi Djakov (1): dt-bindings: Add #defines for MSM8916 clocks and resets Ivan T. Ivanov (3): arm: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974 arm: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes arm: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes Kenneth Westfield (1): arm: dts: qcom: Add LPASS Audio HW to IPQ8064 device tree Kumar Gala (4): arm: qcom: dts: gic: add compatible string for Qualcomm MSM GICs arm: dts: qcom: Add LCC nodes arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts arm64: dts: Add Qualcomm APQ8016 SBC evaluation board dts Lina Iyer (8): devicetree: bindings: Update qcom,saw2 node bindings devicetree: bindings: Document qcom,idle-states ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs ARM: dts: qcom: Add idle states device nodes for 8974/8074 ARM: dts: qcom: Add idle states device nodes for 8084 ARM: dts: qcom: Add idle state device nodes for 8064 Documentation/devicetree/bindings/arm/gic.txt | 2 + .../bindings/arm/msm/qcom,idle-state.txt | 84 + .../devicetree/bindings/arm/msm/qcom,saw2.txt | 40 - .../devicetree/bindings/clock/qcom,gcc.txt | 1 + .../devicetree/bindings/mfd/qcom,tcsr.txt | 22 +++ arch/arm/boot/dts/qcom-apq8064.dtsi| 51 +- arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 2 + arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 1 + arch/arm/boot/dts/qcom-apq8084-mtp.dts | 1 + arch/arm/boot/dts/qcom-apq8084.dtsi| 56 +- arch/arm/boot/dts/qcom-ipq8064.dtsi| 38 arch/arm/boot/dts/qcom-msm8660.dtsi| 8 + arch/arm/boot/dts/qcom-msm8960.dtsi| 15 ++ .../boot/dts/qcom-msm8974-sony-xperia-honami.dts | 2 + arch/arm/boot/dts/qcom-msm8974.dtsi| 56 +- arch/arm/boot/dts/qcom-pm8841.dtsi | 18 ++ arch/arm/boot/dts/qcom-pm8941.dtsi | 18 ++ arch/arm/boot/dts/qcom-pma8084.dtsi| 18 ++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/qcom/Makefile | 5 + arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 21 +++ arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 33 arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 22 +++ arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 33 arch/arm64/boot/dts/qcom/msm8916.dtsi | 196 + include/dt-bindings/clock/qcom,gcc-msm8916.h | 156 include/dt-bindings/reset/qcom,gcc-msm8916.h | 108 27 files changed, 989 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt create mode 100644 arch/arm/boot/dts/qcom-pm8841.dtsi create mode 100644 arch/arm/boot/dts/qcom-pm8941.dtsi create mode 100644 arch/arm/boot/dts/qcom-pma8084.dtsi create mode 100644 arch/arm64/boot/dts/qcom/Makefile create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc.dts create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8916.dtsi create mode 100644 include/dt-bindings/clock/
[GIT PULL] qcom defconfig changes for 4.1-1
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539: Linux 4.0-rc1 (2015-02-22 18:21:14 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-defconfig-for-4.1-1 for you to fetch changes up to dc344b62121c4e2ba5bd9d5bf7a2b4ce5f0487ce: ARM: qcom: Increase MMC_BLOCK_MINORS in defconfig (2015-03-25 16:16:59 -0500) Qualcomm ARM Based defconfig Updates for v4.1-1 * Increase MMC_BLOCK_MINORS to 32 since qcom platforms have more than 16 partitions Georgi Djakov (1): ARM: qcom: Increase MMC_BLOCK_MINORS in defconfig Rajendra Nayak (1): arm: qcom: Enable lpass clock driver in defconfig Stephen Boyd (1): arm: qcom: Update defconfig arch/arm/configs/qcom_defconfig | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom cleanup changes for 4.1
The following changes since commit 9eccca0843205f87c00404b663188b88eb248051: Linux 4.0-rc3 (2015-03-08 16:09:09 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-cleanup-for-4.1 for you to fetch changes up to 27842bb18b004a2802f4b3221c79ce638c4bf6ee: mmc: Remove msm_sdcc driver (2015-03-27 11:31:02 -0500) General cleanups for MSM/QCOM for 4.1 * Removal of mach-msm and associated drivers cleanups that have been ack'd by associated maintainers Stephen Boyd (3): ARM: Remove mach-msm and associated ARM architecture code gpio: Remove gpio-msm-v1 driver mmc: Remove msm_sdcc driver Documentation/arm/00-INDEX |2 - Documentation/arm/msm/gpiomux.txt | 176 --- MAINTAINERS | 20 +- arch/arm/Kconfig| 14 - arch/arm/Kconfig.debug | 29 +- arch/arm/Makefile |2 - arch/arm/configs/msm_defconfig | 121 -- arch/arm/include/debug/msm.S| 14 - arch/arm/mach-msm/Kconfig | 109 -- arch/arm/mach-msm/Makefile | 23 - arch/arm/mach-msm/Makefile.boot |3 - arch/arm/mach-msm/board-halibut.c | 110 -- arch/arm/mach-msm/board-msm7x30.c | 191 --- arch/arm/mach-msm/board-qsd8x50.c | 254 arch/arm/mach-msm/board-sapphire.c | 114 -- arch/arm/mach-msm/board-trout-gpio.c| 233 arch/arm/mach-msm/board-trout-mmc.c | 185 --- arch/arm/mach-msm/board-trout-panel.c | 292 - arch/arm/mach-msm/board-trout.c | 111 -- arch/arm/mach-msm/board-trout.h | 162 --- arch/arm/mach-msm/clock-pcom.c | 176 --- arch/arm/mach-msm/clock-pcom.h | 145 --- arch/arm/mach-msm/clock.c | 28 - arch/arm/mach-msm/clock.h | 43 - arch/arm/mach-msm/common.h | 41 - arch/arm/mach-msm/devices-msm7x00.c | 480 arch/arm/mach-msm/devices-msm7x30.c | 246 arch/arm/mach-msm/devices-qsd8x50.c | 388 -- arch/arm/mach-msm/devices.h | 53 - arch/arm/mach-msm/dma.c | 298 - arch/arm/mach-msm/gpiomux-8x50.c| 51 - arch/arm/mach-msm/gpiomux-v1.h | 67 -- arch/arm/mach-msm/gpiomux.c | 111 -- arch/arm/mach-msm/gpiomux.h | 84 -- arch/arm/mach-msm/include/mach/clk.h| 31 - arch/arm/mach-msm/include/mach/dma.h| 151 --- arch/arm/mach-msm/include/mach/entry-macro.S| 36 - arch/arm/mach-msm/include/mach/hardware.h | 18 - arch/arm/mach-msm/include/mach/irqs-7x00.h | 75 -- arch/arm/mach-msm/include/mach/irqs-7x30.h | 153 --- arch/arm/mach-msm/include/mach/irqs-8x50.h | 88 -- arch/arm/mach-msm/include/mach/irqs.h | 37 - arch/arm/mach-msm/include/mach/msm_gpiomux.h| 38 - arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | 108 -- arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | 103 -- arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | 125 -- arch/arm/mach-msm/include/mach/msm_iomap.h | 53 - arch/arm/mach-msm/include/mach/msm_smd.h| 109 -- arch/arm/mach-msm/include/mach/sirc.h | 98 -- arch/arm/mach-msm/include/mach/vreg.h | 29 - arch/arm/mach-msm/io.c | 161 --- arch/arm/mach-msm/irq-vic.c | 363 -- arch/arm/mach-msm/irq.c | 151 --- arch/arm/mach-msm/last_radio_log.c | 71 -- arch/arm/mach-msm/proc_comm.c | 129 -- arch/arm/mach-msm/proc_comm.h | 258 arch/arm/mach-msm/sirc.c| 172 --- arch/arm/mach-msm/smd.c | 1034 arch/arm/mach-msm/smd_debug.c | 311 - arch/arm/mach-msm/smd_private.h | 403 --- arch/arm/mach-msm/vreg.c| 220 drivers/gpio/Kconfig|8 - drivers/gpio/Makefile |1 - drivers/gpio/gpio-msm-v1.c | 714 --- drivers/mmc/host/Kconfig|8 - drivers/mmc/host/Makefile |1 - drivers/mmc/host/msm_sdcc.c | 1474 --- drivers/mmc/host/msm_sdcc.h | 256 include/linux/platform_data/mmc-msm_sdcc.h | 27 - 69 files changed, 8
[GIT PULL] qcom dt changes for 4.1
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539: Linux 4.0-rc1 (2015-02-22 18:21:14 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-dt-for-4.1 for you to fetch changes up to 1be95ed01c190ca74677798348306a50ad0d46c1: ARM: dts: qcom: Add idle state device nodes for 8064 (2015-03-25 16:38:16 -0500) Qualcomm ARM Based Device Tree Updates for v4.1 * Updated GIC binding to include Qualcomm GIC compatible * Added binding and updated dts for TCSR (Top Control and Status Register) * Added LCC clocks to IPQ8064/APQ8064/MSM8960 device trees * Added LPASS support to IPQ8064 device tree * Added SPMI PMIC device support to APQ8084 and MSM8974 * Added support for MSM8916/APQ8016 SoC (64-bit) and MTP8916/SBC8016 boards * Added support for qcom,saw2 qcom,idle-states on MSM8974/APQ8084/APQ8064 Andy Gross (5): mfd: qcom,tcsr: Add device tree binding for TCSR arm: dts: qcom: Add TCSR support for APQ8064 arm: dts: qcom: Add TCSR support for IPQ8064 arm: dts: qcom: Add TCSR support for MSM8660 arm: dts: qcom: Add TCSR support for MSM8960 Georgi Djakov (1): dt-bindings: Add #defines for MSM8916 clocks and resets Ivan T. Ivanov (3): arm: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974 arm: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes arm: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes Kenneth Westfield (1): arm: dts: qcom: Add LPASS Audio HW to IPQ8064 device tree Kumar Gala (4): arm: qcom: dts: gic: add compatible string for Qualcomm MSM GICs arm: dts: qcom: Add LCC nodes arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts arm64: dts: Add Qualcomm APQ8016 SBC evaluation board dts Lina Iyer (8): devicetree: bindings: Update qcom,saw2 node bindings devicetree: bindings: Document qcom,idle-states ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs ARM: dts: qcom: Add idle states device nodes for 8974/8074 ARM: dts: qcom: Add idle states device nodes for 8084 ARM: dts: qcom: Add idle state device nodes for 8064 Documentation/devicetree/bindings/arm/gic.txt | 2 + .../bindings/arm/msm/qcom,idle-state.txt | 84 + .../devicetree/bindings/arm/msm/qcom,saw2.txt | 40 - .../devicetree/bindings/clock/qcom,gcc.txt | 1 + .../devicetree/bindings/mfd/qcom,tcsr.txt | 22 +++ arch/arm/boot/dts/qcom-apq8064.dtsi| 51 +- arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 2 + arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 1 + arch/arm/boot/dts/qcom-apq8084-mtp.dts | 1 + arch/arm/boot/dts/qcom-apq8084.dtsi| 56 +- arch/arm/boot/dts/qcom-ipq8064.dtsi| 38 arch/arm/boot/dts/qcom-msm8660.dtsi| 8 + arch/arm/boot/dts/qcom-msm8960.dtsi| 15 ++ .../boot/dts/qcom-msm8974-sony-xperia-honami.dts | 2 + arch/arm/boot/dts/qcom-msm8974.dtsi| 56 +- arch/arm/boot/dts/qcom-pm8841.dtsi | 18 ++ arch/arm/boot/dts/qcom-pm8941.dtsi | 18 ++ arch/arm/boot/dts/qcom-pma8084.dtsi| 18 ++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/qcom/Makefile | 5 + arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 21 +++ arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 33 arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 22 +++ arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 33 arch/arm64/boot/dts/qcom/msm8916.dtsi | 196 + include/dt-bindings/clock/qcom,gcc-msm8916.h | 156 include/dt-bindings/reset/qcom,gcc-msm8916.h | 108 27 files changed, 989 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt create mode 100644 arch/arm/boot/dts/qcom-pm8841.dtsi create mode 100644 arch/arm/boot/dts/qcom-pm8941.dtsi create mode 100644 arch/arm/boot/dts/qcom-pma8084.dtsi create mode 100644 arch/arm64/boot/dts/qcom/Makefile create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc.dts create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8916.dtsi create mode 100644 include/dt-bindings/clock/qcom,gcc
[GIT PULL] qcom defconfig changes for 4.1-1
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539: Linux 4.0-rc1 (2015-02-22 18:21:14 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-defconfig-for-4.1-1 for you to fetch changes up to dc344b62121c4e2ba5bd9d5bf7a2b4ce5f0487ce: ARM: qcom: Increase MMC_BLOCK_MINORS in defconfig (2015-03-25 16:16:59 -0500) Qualcomm ARM Based defconfig Updates for v4.1-1 * Increase MMC_BLOCK_MINORS to 32 since qcom platforms have more than 16 partitions Georgi Djakov (1): ARM: qcom: Increase MMC_BLOCK_MINORS in defconfig Rajendra Nayak (1): arm: qcom: Enable lpass clock driver in defconfig Stephen Boyd (1): arm: qcom: Update defconfig arch/arm/configs/qcom_defconfig | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom cleanup changes for 4.1
The following changes since commit 9eccca0843205f87c00404b663188b88eb248051: Linux 4.0-rc3 (2015-03-08 16:09:09 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-cleanup-for-4.1 for you to fetch changes up to 27842bb18b004a2802f4b3221c79ce638c4bf6ee: mmc: Remove msm_sdcc driver (2015-03-27 11:31:02 -0500) General cleanups for MSM/QCOM for 4.1 * Removal of mach-msm and associated drivers cleanups that have been ack'd by associated maintainers Stephen Boyd (3): ARM: Remove mach-msm and associated ARM architecture code gpio: Remove gpio-msm-v1 driver mmc: Remove msm_sdcc driver Documentation/arm/00-INDEX |2 - Documentation/arm/msm/gpiomux.txt | 176 --- MAINTAINERS | 20 +- arch/arm/Kconfig| 14 - arch/arm/Kconfig.debug | 29 +- arch/arm/Makefile |2 - arch/arm/configs/msm_defconfig | 121 -- arch/arm/include/debug/msm.S| 14 - arch/arm/mach-msm/Kconfig | 109 -- arch/arm/mach-msm/Makefile | 23 - arch/arm/mach-msm/Makefile.boot |3 - arch/arm/mach-msm/board-halibut.c | 110 -- arch/arm/mach-msm/board-msm7x30.c | 191 --- arch/arm/mach-msm/board-qsd8x50.c | 254 arch/arm/mach-msm/board-sapphire.c | 114 -- arch/arm/mach-msm/board-trout-gpio.c| 233 arch/arm/mach-msm/board-trout-mmc.c | 185 --- arch/arm/mach-msm/board-trout-panel.c | 292 - arch/arm/mach-msm/board-trout.c | 111 -- arch/arm/mach-msm/board-trout.h | 162 --- arch/arm/mach-msm/clock-pcom.c | 176 --- arch/arm/mach-msm/clock-pcom.h | 145 --- arch/arm/mach-msm/clock.c | 28 - arch/arm/mach-msm/clock.h | 43 - arch/arm/mach-msm/common.h | 41 - arch/arm/mach-msm/devices-msm7x00.c | 480 arch/arm/mach-msm/devices-msm7x30.c | 246 arch/arm/mach-msm/devices-qsd8x50.c | 388 -- arch/arm/mach-msm/devices.h | 53 - arch/arm/mach-msm/dma.c | 298 - arch/arm/mach-msm/gpiomux-8x50.c| 51 - arch/arm/mach-msm/gpiomux-v1.h | 67 -- arch/arm/mach-msm/gpiomux.c | 111 -- arch/arm/mach-msm/gpiomux.h | 84 -- arch/arm/mach-msm/include/mach/clk.h| 31 - arch/arm/mach-msm/include/mach/dma.h| 151 --- arch/arm/mach-msm/include/mach/entry-macro.S| 36 - arch/arm/mach-msm/include/mach/hardware.h | 18 - arch/arm/mach-msm/include/mach/irqs-7x00.h | 75 -- arch/arm/mach-msm/include/mach/irqs-7x30.h | 153 --- arch/arm/mach-msm/include/mach/irqs-8x50.h | 88 -- arch/arm/mach-msm/include/mach/irqs.h | 37 - arch/arm/mach-msm/include/mach/msm_gpiomux.h| 38 - arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | 108 -- arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | 103 -- arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | 125 -- arch/arm/mach-msm/include/mach/msm_iomap.h | 53 - arch/arm/mach-msm/include/mach/msm_smd.h| 109 -- arch/arm/mach-msm/include/mach/sirc.h | 98 -- arch/arm/mach-msm/include/mach/vreg.h | 29 - arch/arm/mach-msm/io.c | 161 --- arch/arm/mach-msm/irq-vic.c | 363 -- arch/arm/mach-msm/irq.c | 151 --- arch/arm/mach-msm/last_radio_log.c | 71 -- arch/arm/mach-msm/proc_comm.c | 129 -- arch/arm/mach-msm/proc_comm.h | 258 arch/arm/mach-msm/sirc.c| 172 --- arch/arm/mach-msm/smd.c | 1034 arch/arm/mach-msm/smd_debug.c | 311 - arch/arm/mach-msm/smd_private.h | 403 --- arch/arm/mach-msm/vreg.c| 220 drivers/gpio/Kconfig|8 - drivers/gpio/Makefile |1 - drivers/gpio/gpio-msm-v1.c | 714 --- drivers/mmc/host/Kconfig|8 - drivers/mmc/host/Makefile |1 - drivers/mmc/host/msm_sdcc.c | 1474 --- drivers/mmc/host/msm_sdcc.h | 256 include/linux/platform_data/mmc-msm_sdcc.h | 27 - 69 files changed, 8
Re: [PATCH V5 0/2] add support for pmic_arb v2 and correct framework
On Mar 26, 2015, at 4:51 AM, Ivan T. Ivanov wrote: > > On Wed, 2015-03-25 at 11:37 -0600, Gilad Avidov wrote: >> pmic_arb v2 has no support for spmi non-data commands and thus >> returns -EOPNOTSUPP on .cmd callback. This causes a failure in >> spmi_drv_probe() which sends a wakeup command to the slave before >> probing its driver. This patchset removes the wakeup from >> spmi_drv_probe() since the spmi spec stipulates that a slaves >> default state is active and doesn't need a wakeup. >> >> Changes from v3 to v4: >> * Remove the claim that this is a bug fix off the commit text >> * Unmap the core register space as soon as we know that it will not be used >> * Assign the core reg space to a local until we know if it appropriate to use >> it to configure the controller fields (on v1) or unmap it (on v2). >> >> Changes from v4 to v5: >> * remove the unmap added in v4 since it is used again and the mapping is >> managed. >> * correct printf formatting for 64bit compilers. >> * correct base address for reading the channel table. >> >> Gilad Avidov (2): >> spmi: remove wakeup command before slave probe >> spmi: pmic_arb: add support for hw version 2 > > Thank you Gilad. This is fine now. Tested on APQ8084 > (controller v1) and MSM8916 (controller v2). > > I am wandering which is the appropriate tree to merge this? > > Kumar? We’ve been asking Greg to pick up SPMI patches. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH V5 0/2] add support for pmic_arb v2 and correct framework
On Mar 26, 2015, at 4:51 AM, Ivan T. Ivanov iiva...@mm-sol.com wrote: On Wed, 2015-03-25 at 11:37 -0600, Gilad Avidov wrote: pmic_arb v2 has no support for spmi non-data commands and thus returns -EOPNOTSUPP on .cmd callback. This causes a failure in spmi_drv_probe() which sends a wakeup command to the slave before probing its driver. This patchset removes the wakeup from spmi_drv_probe() since the spmi spec stipulates that a slaves default state is active and doesn't need a wakeup. Changes from v3 to v4: * Remove the claim that this is a bug fix off the commit text * Unmap the core register space as soon as we know that it will not be used * Assign the core reg space to a local until we know if it appropriate to use it to configure the controller fields (on v1) or unmap it (on v2). Changes from v4 to v5: * remove the unmap added in v4 since it is used again and the mapping is managed. * correct printf formatting for 64bit compilers. * correct base address for reading the channel table. Gilad Avidov (2): spmi: remove wakeup command before slave probe spmi: pmic_arb: add support for hw version 2 Thank you Gilad. This is fine now. Tested on APQ8084 (controller v1) and MSM8916 (controller v2). I am wandering which is the appropriate tree to merge this? Kumar? We’ve been asking Greg to pick up SPMI patches. - k -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
