Re: [Linux-stm32] [PATCH] ARM: dts: stm32: enable STM32MP1 crypto/CRC accelerators unconditionally

[Lionel DEBIEVE]

Hi Ahmad,

These IPs could be enabled in the secure side. To avoid any concurrency 
access, I prefer to keep all that crypto IPs status disable.
For examples, RNG can be managed in OP-TEE, so it will remain disable in 
Linux.

BR,

Lionel

On 1/19/21 10:52 AM, Ahmad Fatoum wrote:

There is no SoC-external hardware support needed for the hash1, rng1,
crc1 and cryp1 IP blocks to function. Enable them thus unconditionally
instead of replicating their enablement in board device trees.

Signed-off-by: Ahmad Fatoum 
---
  arch/arm/boot/dts/stm32mp151.dtsi  |  3 ---
  arch/arm/boot/dts/stm32mp157a-stinger96.dtsi   |  4 
  arch/arm/boot/dts/stm32mp157c-dk2.dts  |  4 
  arch/arm/boot/dts/stm32mp157c-ed1.dts  | 16 
  arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi |  4 
  arch/arm/boot/dts/stm32mp15xc.dtsi |  1 -
  arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi   |  8 
  arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi   |  4 
  arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 12 
  arch/arm/boot/dts/stm32mp15xx-osd32.dtsi   |  4 
  10 files changed, 60 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi 
b/arch/arm/boot/dts/stm32mp151.dtsi
index 3c75abacb374..c2d998343b6a 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -1297,7 +1297,6 @@ hash1: hash@54002000 {
dmas = < 31 0x2 0x1000A02 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
-   status = "disabled";
};
  
  		rng1: rng@54003000 {

@@ -1305,7 +1304,6 @@ rng1: rng@54003000 {
reg = <0x54003000 0x400>;
clocks = < RNG1_K>;
resets = < RNG1_R>;
-   status = "disabled";
};
  
  		mdma1: dma-controller@5800 {

@@ -1402,7 +1400,6 @@ crc1: crc@58009000 {
compatible = "st,stm32f7-crc";
reg = <0x58009000 0x400>;
clocks = < CRC1>;
-   status = "disabled";
};
  
  		stmmac_axi_config_0: stmmac-axi-config {

diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi 
b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
index 58275bcf9e26..268a99291d79 100644
--- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
+++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
@@ -253,10 +253,6 @@ _regulators {
vdd_3v3_usbfs-supply = <_usb>;
  };
  
- {

-   status = "okay";
-};
-
   {
status = "okay";
  };
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts 
b/arch/arm/boot/dts/stm32mp157c-dk2.dts
index 2bc92ef3aeb9..045636555ddd 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
@@ -29,10 +29,6 @@ chosen {
};
  };
  
- {

-   status = "okay";
-};
-
   {
status = "okay";
phy-dsi-supply = <>;
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts 
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 81a7d5849db4..f69622097e89 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -115,14 +115,6 @@ adc1: adc@0 {
};
  };
  
- {

-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
   {
pinctrl-names = "default";
pinctrl-0 = <_ch1_pins_a _ch2_pins_a>;
@@ -144,10 +136,6 @@  {
contiguous-area = <_reserved>;
  };
  
- {

-   status = "okay";
-};
-
   {
pinctrl-names = "default", "sleep";
pinctrl-0 = <_pins_a>;
@@ -325,10 +313,6 @@ _regulators {
vdd_3v3_usbfs-supply = <_usb>;
  };
  
- {

-   status = "okay";
-};
-
   {
status = "okay";
  };
diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi 
b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
index 6cf49a0a9e69..a2aca1982bf6 100644
--- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
@@ -250,10 +250,6 @@ _rproc {
status = "okay";
  };
  
- {

-   status = "okay";
-};
-
   {
status = "okay";
  };
diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi 
b/arch/arm/boot/dts/stm32mp15xc.dtsi
index b06a55a2fa18..86953d7ddde0 100644
--- a/arch/arm/boot/dts/stm32mp15xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xc.dtsi
@@ -12,7 +12,6 @@ cryp1: cryp@54001000 {
interrupts = ;
clocks = < CRYP1>;
resets = < CRYP1_R>;
-   status = "disabled";
};
};
  };
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
index ac46ab363e1b..603c14054509 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
@@ -377,14 +377,6 @@ flash0: mx66l51235l@0 {
};
  };
  
- {

-   status = "okay";
-};
-
- {
-   status = 

[PATCH 3/3] ARM: dts: stm32: enable CRYP by default on stm32mp15

[Lionel Debieve]

Enable CRYP1 device for cryp accelerated support on
stm32mp157C-EV1/DK2 STMicroelectronics platforms.

Signed-off-by: Nicolas Toromanoff 
Signed-off-by: Lionel Debieve 
---
 arch/arm/boot/dts/stm32mp157c-dk2.dts | 4 
 arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts 
b/arch/arm/boot/dts/stm32mp157c-dk2.dts
index 045636555ddd..2bc92ef3aeb9 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
@@ -29,6 +29,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
phy-dsi-supply = <>;
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts 
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 99796ffa43bf..74b9aaa611b5 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -136,6 +136,10 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
contiguous-area = <_reserved>;
 };
-- 
2.17.1

[PATCH 2/3] ARM: dts: stm32: enable CRC1 by default on stm32mp15

[Lionel Debieve]

From: Nicolas Toromanoff 

Enable CRC1 device for CRC-32 accelerated support on
stm32mp15 STMicroelectronics platforms.

Signed-off-by: Nicolas Toromanoff 
Signed-off-by: Lionel Debieve 
---
 arch/arm/boot/dts/stm32mp157c-ed1.dts  | 4 
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts 
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 1a98a29b3283..99796ffa43bf 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -115,6 +115,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_ch1_pins_a _ch2_pins_a>;
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
index e92a18542306..4e74e55a4f07 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -124,6 +124,10 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
2.17.1

[PATCH 0/3] ARM: dts: stm32: enable crypto controllers

[Lionel Debieve]

Enable the crypto controllers in the STM32MP157C-EV1 and STM32MP157A-DK1
STM32MP157C-DK2 boards.

Lionel Debieve (2):
  ARM: dts: stm32: enable HASH by default on stm32mp15
  ARM: dts: stm32: enable CRYP by default on stm32mp15

Nicolas Toromanoff (1):
  ARM: dts: stm32: enable CRC1 by default on stm32mp15

 arch/arm/boot/dts/stm32mp157c-dk2.dts  |  4 
 arch/arm/boot/dts/stm32mp157c-ed1.dts  | 12 
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi |  8 
 3 files changed, 24 insertions(+)

-- 
2.17.1

[PATCH 1/3] ARM: dts: stm32: enable HASH by default on stm32mp15

[Lionel Debieve]

Enable HASH1 device for HASH accelerated support on
stm32mp15 STMicroelectronics platforms.

Signed-off-by: Lionel Debieve 
---
 arch/arm/boot/dts/stm32mp157c-ed1.dts  | 4 
 arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts 
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 2e77ccec3fc1..1a98a29b3283 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -136,6 +136,10 @@
contiguous-area = <_reserved>;
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default", "sleep";
pinctrl-0 = <_pins_a>;
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi 
b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
index 93398cfae97e..e92a18542306 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -151,6 +151,10 @@
contiguous-area = <_reserved>;
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default", "sleep";
pinctrl-0 = <_pins_a>;
-- 
2.17.1

[PATCH 1/1] ARM: multi_v7_defconfig: add STM32 crypto support

[Lionel Debieve]

Enable crypto controllers enabling following flags as module:
CONFIG_CRYPTO_DEV_STM32_CRC
CONFIG_CRYPTO_DEV_STM32_HASH
CONFIG_CRYPTO_DEV_STM32_CRYP

Signed-off-by: Lionel Debieve 
---
 arch/arm/configs/multi_v7_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index a611b0c1e540..57eafa2d7775 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -1133,6 +1133,9 @@ CONFIG_CRYPTO_DEV_ATMEL_AES=m
 CONFIG_CRYPTO_DEV_ATMEL_TDES=m
 CONFIG_CRYPTO_DEV_ATMEL_SHA=m
 CONFIG_CRYPTO_DEV_ROCKCHIP=m
+CONFIG_CRYPTO_DEV_STM32_CRC=m
+CONFIG_CRYPTO_DEV_STM32_HASH=m
+CONFIG_CRYPTO_DEV_STM32_CRYP=m
 CONFIG_CMA_SIZE_MBYTES=64
 CONFIG_PRINTK_TIME=y
 CONFIG_MAGIC_SYSRQ=y
-- 
2.17.1

[PATCH 1/1] ARM: dts: stm32: Add HASH support on stm32mp157c

[Lionel Debieve]

This patch add HASH instance of the stm32mp157c SoC

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index b66f673b5038..cb39fb6d9960 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -702,6 +702,18 @@
status = "disabled";
};
 
+   hash1: hash@54002000 {
+   compatible = "st,stm32f756-hash";
+   reg = <0x54002000 0x400>;
+   interrupts = ;
+   clocks = < HASH1>;
+   resets = < HASH1_R>;
+   dmas = < 31 0x10 0x1000A02 0x0 0x0 0x0>;
+   dma-names = "in";
+   dma-maxburst = <2>;
+   status = "disabled";
+   };
+
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
-- 
2.15.1

[PATCH 1/1] ARM: dts: stm32: Add HASH support on stm32mp157c

[Lionel Debieve]

This patch add HASH instance of the stm32mp157c SoC

Signed-off-by: Lionel Debieve 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index b66f673b5038..cb39fb6d9960 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -702,6 +702,18 @@
status = "disabled";
};
 
+   hash1: hash@54002000 {
+   compatible = "st,stm32f756-hash";
+   reg = <0x54002000 0x400>;
+   interrupts = ;
+   clocks = < HASH1>;
+   resets = < HASH1_R>;
+   dmas = < 31 0x10 0x1000A02 0x0 0x0 0x0>;
+   dma-names = "in";
+   dma-maxburst = <2>;
+   status = "disabled";
+   };
+
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
-- 
2.15.1

[PATCH 0/4] ARM: dts: Add cryptographic support for stm32mp157c

[Lionel Debieve]

Patches serie add support or RNG, CRYP and CRC IPs for stm32mp157c SoC
and add RNG default support for ev1 board.

Lionel Debieve (4):
  ARM: dts: stm32: Add RNG support on stm32mp157c
  ARM: dts: stm32: Enable RNG for stm32mp157c-ed1
  ARM: dts: stm32: Add CRYP support on stm32mp157c
  ARM: dts: stm32: Add CRC support on stm32mp157c

 arch/arm/boot/dts/stm32mp157c-ed1.dts |  4 
 arch/arm/boot/dts/stm32mp157c.dtsi| 25 +
 2 files changed, 29 insertions(+)

-- 
2.15.1

[PATCH 0/4] ARM: dts: Add cryptographic support for stm32mp157c

[Lionel Debieve]

Patches serie add support or RNG, CRYP and CRC IPs for stm32mp157c SoC
and add RNG default support for ev1 board.

Lionel Debieve (4):
  ARM: dts: stm32: Add RNG support on stm32mp157c
  ARM: dts: stm32: Enable RNG for stm32mp157c-ed1
  ARM: dts: stm32: Add CRYP support on stm32mp157c
  ARM: dts: stm32: Add CRC support on stm32mp157c

 arch/arm/boot/dts/stm32mp157c-ed1.dts |  4 
 arch/arm/boot/dts/stm32mp157c.dtsi| 25 +
 2 files changed, 29 insertions(+)

-- 
2.15.1

[PATCH 4/4] ARM: dts: stm32: Add CRC support on stm32mp157c

[Lionel Debieve]

This patch add CRC instance of the stm32mp157c SoC

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index 5ce7d28f8a1f..2962decacd87 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -185,6 +185,13 @@
status = "disabled";
};
 
+   crc1: crc@58009000 {
+   compatible = "st,stm32f7-crc";
+   reg = <0x58009000 0x400>;
+   clocks = < CRC1>;
+   status = "disabled";
+   };
+
usart1: serial@5c00 {
compatible = "st,stm32h7-uart";
reg = <0x5c00 0x400>;
-- 
2.15.1

[PATCH 4/4] ARM: dts: stm32: Add CRC support on stm32mp157c

[Lionel Debieve]

This patch add CRC instance of the stm32mp157c SoC

Signed-off-by: Lionel Debieve 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index 5ce7d28f8a1f..2962decacd87 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -185,6 +185,13 @@
status = "disabled";
};
 
+   crc1: crc@58009000 {
+   compatible = "st,stm32f7-crc";
+   reg = <0x58009000 0x400>;
+   clocks = < CRC1>;
+   status = "disabled";
+   };
+
usart1: serial@5c00 {
compatible = "st,stm32h7-uart";
reg = <0x5c00 0x400>;
-- 
2.15.1

[PATCH 1/4] ARM: dts: stm32: Add RNG support on stm32mp157c

[Lionel Debieve]

This patch add RNG instance of the stm32mp157c SoC

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc3eda6..bf00885971b3 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -5,6 +5,7 @@
  */
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -167,6 +168,14 @@
#reset-cells = <1>;
};
 
+   rng1: rng@54003000 {
+   compatible = "st,stm32-rng";
+   reg = <0x54003000 0x400>;
+   clocks = < RNG1_K>;
+   resets = < RNG1_R>;
+   status = "disabled";
+   };
+
usart1: serial@5c00 {
compatible = "st,stm32h7-uart";
reg = <0x5c00 0x400>;
-- 
2.15.1

[PATCH 3/4] ARM: dts: stm32: Add CRYP support on stm32mp157c

[Lionel Debieve]

This patch add CRYP instance of the stm32mp157c SoC

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bf00885971b3..5ce7d28f8a1f 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -168,6 +168,15 @@
#reset-cells = <1>;
};
 
+   cryp1: cryp@54001000 {
+   compatible = "st,stm32mp1-cryp";
+   reg = <0x54001000 0x400>;
+   interrupts = ;
+   clocks = < CRYP1>;
+   resets = < CRYP1_R>;
+   status = "disabled";
+   };
+
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
-- 
2.15.1

[PATCH 1/4] ARM: dts: stm32: Add RNG support on stm32mp157c

[Lionel Debieve]

This patch add RNG instance of the stm32mp157c SoC

Signed-off-by: Lionel Debieve 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc3eda6..bf00885971b3 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -5,6 +5,7 @@
  */
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -167,6 +168,14 @@
#reset-cells = <1>;
};
 
+   rng1: rng@54003000 {
+   compatible = "st,stm32-rng";
+   reg = <0x54003000 0x400>;
+   clocks = < RNG1_K>;
+   resets = < RNG1_R>;
+   status = "disabled";
+   };
+
usart1: serial@5c00 {
compatible = "st,stm32h7-uart";
reg = <0x5c00 0x400>;
-- 
2.15.1

[PATCH 3/4] ARM: dts: stm32: Add CRYP support on stm32mp157c

[Lionel Debieve]

This patch add CRYP instance of the stm32mp157c SoC

Signed-off-by: Lionel Debieve 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bf00885971b3..5ce7d28f8a1f 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -168,6 +168,15 @@
#reset-cells = <1>;
};
 
+   cryp1: cryp@54001000 {
+   compatible = "st,stm32mp1-cryp";
+   reg = <0x54001000 0x400>;
+   interrupts = ;
+   clocks = < CRYP1>;
+   resets = < CRYP1_R>;
+   status = "disabled";
+   };
+
rng1: rng@54003000 {
compatible = "st,stm32-rng";
reg = <0x54003000 0x400>;
-- 
2.15.1

[PATCH 2/4] ARM: dts: stm32: Enable RNG for stm32mp157c-ed1

[Lionel Debieve]

Enable stm32-hwrng for ed1 and ev1 boards

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts 
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 9f90337a22e3..2a992525919c 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -25,6 +25,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.15.1

[PATCH 2/4] ARM: dts: stm32: Enable RNG for stm32mp157c-ed1

[Lionel Debieve]

Enable stm32-hwrng for ed1 and ev1 boards

Signed-off-by: Lionel Debieve 
---
 arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts 
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 9f90337a22e3..2a992525919c 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -25,6 +25,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.15.1

[PATCH 0/2] Fix stm32-rng for default state and suspend

[Lionel Debieve]

This series are fixing the default build state for stm32-rng that
activate the driver with arm multi_v7_defconfig.
Second patch is fixing the power suspend/resume behavior which was
not working.

Lionel Debieve (2):
  hwrng: stm32 - define default state for rng driver
  hwrng: stm32-rng: Fix pm_suspend issue

 drivers/char/hw_random/Kconfig | 1 +
 drivers/char/hw_random/stm32-rng.c | 9 +++--
 2 files changed, 8 insertions(+), 2 deletions(-)

-- 
2.15.1

[PATCH 0/2] Fix stm32-rng for default state and suspend

[Lionel Debieve]

This series are fixing the default build state for stm32-rng that
activate the driver with arm multi_v7_defconfig.
Second patch is fixing the power suspend/resume behavior which was
not working.

Lionel Debieve (2):
  hwrng: stm32 - define default state for rng driver
  hwrng: stm32-rng: Fix pm_suspend issue

 drivers/char/hw_random/Kconfig | 1 +
 drivers/char/hw_random/stm32-rng.c | 9 +++--
 2 files changed, 8 insertions(+), 2 deletions(-)

-- 
2.15.1

[PATCH 1/2] hwrng: stm32 - define default state for rng driver

[Lionel Debieve]

Define default state for stm32_rng driver. It will
be default selected with multi_v7_defconfig

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/char/hw_random/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index d53541e96bee..c34b257d852d 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -347,6 +347,7 @@ config HW_RANDOM_STM32
tristate "STMicroelectronics STM32 random number generator"
depends on HW_RANDOM && (ARCH_STM32 || COMPILE_TEST)
depends on HAS_IOMEM
+   default HW_RANDOM
help
  This driver provides kernel-side support for the Random Number
  Generator hardware found on STM32 microcontrollers.
-- 
2.15.1

[PATCH 1/2] hwrng: stm32 - define default state for rng driver

[Lionel Debieve]

Define default state for stm32_rng driver. It will
be default selected with multi_v7_defconfig

Signed-off-by: Lionel Debieve 
---
 drivers/char/hw_random/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index d53541e96bee..c34b257d852d 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -347,6 +347,7 @@ config HW_RANDOM_STM32
tristate "STMicroelectronics STM32 random number generator"
depends on HW_RANDOM && (ARCH_STM32 || COMPILE_TEST)
depends on HAS_IOMEM
+   default HW_RANDOM
help
  This driver provides kernel-side support for the Random Number
  Generator hardware found on STM32 microcontrollers.
-- 
2.15.1

[PATCH 2/2] hwrng: stm32-rng - fix pm_suspend issue

[Lionel Debieve]

When suspend is called after pm_runtime_suspend,
same callback is used and access to rng register is
freezing system. By calling the pm_runtime_force_suspend,
it first checks that runtime has been already done.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/char/hw_random/stm32-rng.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 0d2328da3b76..042860d97b15 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -187,8 +187,13 @@ static int stm32_rng_runtime_resume(struct device *dev)
 }
 #endif
 
-static UNIVERSAL_DEV_PM_OPS(stm32_rng_pm_ops, stm32_rng_runtime_suspend,
-   stm32_rng_runtime_resume, NULL);
+static const struct dev_pm_ops stm32_rng_pm_ops = {
+   SET_RUNTIME_PM_OPS(stm32_rng_runtime_suspend,
+  stm32_rng_runtime_resume, NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
+};
+
 
 static const struct of_device_id stm32_rng_match[] = {
{
-- 
2.15.1

[PATCH 2/2] hwrng: stm32-rng - fix pm_suspend issue

[Lionel Debieve]

When suspend is called after pm_runtime_suspend,
same callback is used and access to rng register is
freezing system. By calling the pm_runtime_force_suspend,
it first checks that runtime has been already done.

Signed-off-by: Lionel Debieve 
---
 drivers/char/hw_random/stm32-rng.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 0d2328da3b76..042860d97b15 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -187,8 +187,13 @@ static int stm32_rng_runtime_resume(struct device *dev)
 }
 #endif
 
-static UNIVERSAL_DEV_PM_OPS(stm32_rng_pm_ops, stm32_rng_runtime_suspend,
-   stm32_rng_runtime_resume, NULL);
+static const struct dev_pm_ops stm32_rng_pm_ops = {
+   SET_RUNTIME_PM_OPS(stm32_rng_runtime_suspend,
+  stm32_rng_runtime_resume, NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
+};
+
 
 static const struct of_device_id stm32_rng_match[] = {
{
-- 
2.15.1

[PATCH Resend 5/5] hwrng: stm32 - rework read timeout calculation

[Lionel Debieve]

Increase timeout delay to support longer timing linked
to rng initialization. Measurement is based on timer instead
of instructions per iteration which is not powerful on all
targets.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/char/hw_random/stm32-rng.c | 25 ++---
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 709a8d061be3..0d2328da3b76 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -35,15 +36,6 @@
 
 #define RNG_DR 0x08
 
-/*
- * It takes 40 cycles @ 48MHz to generate each random number (e.g. <1us).
- * At the time of writing STM32 parts max out at ~200MHz meaning a timeout
- * of 500 leaves us a very comfortable margin for error. The loop to which
- * the timeout applies takes at least 4 instructions per iteration so the
- * timeout is enough to take us up to multi-GHz parts!
- */
-#define RNG_TIMEOUT 500
-
 struct stm32_rng_private {
struct hwrng rng;
void __iomem *base;
@@ -63,13 +55,16 @@ static int stm32_rng_read(struct hwrng *rng, void *data, 
size_t max, bool wait)
 
while (max > sizeof(u32)) {
sr = readl_relaxed(priv->base + RNG_SR);
+   /* Manage timeout which is based on timer and take */
+   /* care of initial delay time when enabling rng */
if (!sr && wait) {
-   unsigned int timeout = RNG_TIMEOUT;
-
-   do {
-   cpu_relax();
-   sr = readl_relaxed(priv->base + RNG_SR);
-   } while (!sr && --timeout);
+   retval = readl_relaxed_poll_timeout_atomic(priv->base
+  + RNG_SR,
+  sr, sr,
+  10, 5);
+   if (retval)
+   dev_err((struct device *)priv->rng.priv,
+   "%s: timeout %x!\n", __func__, sr);
}
 
/* If error detected or data not ready... */
-- 
2.15.1

[PATCH Resend 5/5] hwrng: stm32 - rework read timeout calculation

[Lionel Debieve]

Increase timeout delay to support longer timing linked
to rng initialization. Measurement is based on timer instead
of instructions per iteration which is not powerful on all
targets.

Signed-off-by: Lionel Debieve 
---
 drivers/char/hw_random/stm32-rng.c | 25 ++---
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 709a8d061be3..0d2328da3b76 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -35,15 +36,6 @@
 
 #define RNG_DR 0x08
 
-/*
- * It takes 40 cycles @ 48MHz to generate each random number (e.g. <1us).
- * At the time of writing STM32 parts max out at ~200MHz meaning a timeout
- * of 500 leaves us a very comfortable margin for error. The loop to which
- * the timeout applies takes at least 4 instructions per iteration so the
- * timeout is enough to take us up to multi-GHz parts!
- */
-#define RNG_TIMEOUT 500
-
 struct stm32_rng_private {
struct hwrng rng;
void __iomem *base;
@@ -63,13 +55,16 @@ static int stm32_rng_read(struct hwrng *rng, void *data, 
size_t max, bool wait)
 
while (max > sizeof(u32)) {
sr = readl_relaxed(priv->base + RNG_SR);
+   /* Manage timeout which is based on timer and take */
+   /* care of initial delay time when enabling rng */
if (!sr && wait) {
-   unsigned int timeout = RNG_TIMEOUT;
-
-   do {
-   cpu_relax();
-   sr = readl_relaxed(priv->base + RNG_SR);
-   } while (!sr && --timeout);
+   retval = readl_relaxed_poll_timeout_atomic(priv->base
+  + RNG_SR,
+  sr, sr,
+  10, 5);
+   if (retval)
+   dev_err((struct device *)priv->rng.priv,
+   "%s: timeout %x!\n", __func__, sr);
}
 
/* If error detected or data not ready... */
-- 
2.15.1

[PATCH Resend 0/5] hwrng: stm32 - Improvement for stm32-rng

[Lionel Debieve]

This set of patches add extended functionalities for stm32 rng
driver.
Patch #1 includes a reset during probe to avoid any error status
which can occur during bootup process and keep safe rng integrity.

Patch #3 adds a new property to manage the clock error detection
feature which can be disabled on specific target.

Patch #5 rework the timeout calculation for read value that was
previously defined based on loop operation and is now based on
timer.

Lionel Debieve (5):
  hwrng: stm32 - add reset during probe
  dt-bindings: rng: add reset node for stm32
  hwrng: stm32 - allow disable clock error detection
  dt-bindings: rng: add clock detection error for stm32
  hwrng: stm32 - rework read timeout calculation

 .../devicetree/bindings/rng/st,stm32-rng.txt   |  4 ++
 drivers/char/hw_random/stm32-rng.c | 44 ++
 2 files changed, 32 insertions(+), 16 deletions(-)

-- 
2.15.1

[PATCH Resend 0/5] hwrng: stm32 - Improvement for stm32-rng

[Lionel Debieve]

This set of patches add extended functionalities for stm32 rng
driver.
Patch #1 includes a reset during probe to avoid any error status
which can occur during bootup process and keep safe rng integrity.

Patch #3 adds a new property to manage the clock error detection
feature which can be disabled on specific target.

Patch #5 rework the timeout calculation for read value that was
previously defined based on loop operation and is now based on
timer.

Lionel Debieve (5):
  hwrng: stm32 - add reset during probe
  dt-bindings: rng: add reset node for stm32
  hwrng: stm32 - allow disable clock error detection
  dt-bindings: rng: add clock detection error for stm32
  hwrng: stm32 - rework read timeout calculation

 .../devicetree/bindings/rng/st,stm32-rng.txt   |  4 ++
 drivers/char/hw_random/stm32-rng.c | 44 ++
 2 files changed, 32 insertions(+), 16 deletions(-)

-- 
2.15.1

[PATCH Resend 3/5] hwrng: stm32 - allow disable clock error detection

[Lionel Debieve]

Add a new property that allow to disable the clock error
detection which is required when the clock source selected
is out of specification (which is not mandatory).

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/char/hw_random/stm32-rng.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 83c695938a2d..709a8d061be3 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -26,6 +26,7 @@
 
 #define RNG_CR 0x00
 #define RNG_CR_RNGEN BIT(2)
+#define RNG_CR_CED BIT(5)
 
 #define RNG_SR 0x04
 #define RNG_SR_SEIS BIT(6)
@@ -48,6 +49,7 @@ struct stm32_rng_private {
void __iomem *base;
struct clk *clk;
struct reset_control *rst;
+   bool ced;
 };
 
 static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
@@ -101,7 +103,11 @@ static int stm32_rng_init(struct hwrng *rng)
if (err)
return err;
 
-   writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
+   if (priv->ced)
+   writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
+   else
+   writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED,
+  priv->base + RNG_CR);
 
/* clear error indicators */
writel_relaxed(0, priv->base + RNG_SR);
@@ -149,6 +155,8 @@ static int stm32_rng_probe(struct platform_device *ofdev)
reset_control_deassert(priv->rst);
}
 
+   priv->ced = of_property_read_bool(np, "clock-error-detect");
+
dev_set_drvdata(dev, priv);
 
priv->rng.name = dev_driver_string(dev),
-- 
2.15.1

[PATCH Resend 3/5] hwrng: stm32 - allow disable clock error detection

[Lionel Debieve]

Add a new property that allow to disable the clock error
detection which is required when the clock source selected
is out of specification (which is not mandatory).

Signed-off-by: Lionel Debieve 
---
 drivers/char/hw_random/stm32-rng.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 83c695938a2d..709a8d061be3 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -26,6 +26,7 @@
 
 #define RNG_CR 0x00
 #define RNG_CR_RNGEN BIT(2)
+#define RNG_CR_CED BIT(5)
 
 #define RNG_SR 0x04
 #define RNG_SR_SEIS BIT(6)
@@ -48,6 +49,7 @@ struct stm32_rng_private {
void __iomem *base;
struct clk *clk;
struct reset_control *rst;
+   bool ced;
 };
 
 static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
@@ -101,7 +103,11 @@ static int stm32_rng_init(struct hwrng *rng)
if (err)
return err;
 
-   writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
+   if (priv->ced)
+   writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
+   else
+   writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED,
+  priv->base + RNG_CR);
 
/* clear error indicators */
writel_relaxed(0, priv->base + RNG_SR);
@@ -149,6 +155,8 @@ static int stm32_rng_probe(struct platform_device *ofdev)
reset_control_deassert(priv->rst);
}
 
+   priv->ced = of_property_read_bool(np, "clock-error-detect");
+
dev_set_drvdata(dev, priv);
 
priv->rng.name = dev_driver_string(dev),
-- 
2.15.1

[PATCH Resend 2/5] dt-bindings: rng: add reset node for stm32

[Lionel Debieve]

Adding optional resets property for rng.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt 
b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
index 47f04176f93b..cb7ca78135ff 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
@@ -11,6 +11,9 @@ Required properties:
 - interrupts : The designated IRQ line for the RNG
 - clocks : The clock needed to enable the RNG
 
+Optional properties:
+- resets : The reset to properly start RNG
+
 Example:
 
rng: rng@50060800 {
-- 
2.15.1

[PATCH Resend 2/5] dt-bindings: rng: add reset node for stm32

[Lionel Debieve]

Adding optional resets property for rng.

Signed-off-by: Lionel Debieve 
---
 Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt 
b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
index 47f04176f93b..cb7ca78135ff 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
@@ -11,6 +11,9 @@ Required properties:
 - interrupts : The designated IRQ line for the RNG
 - clocks : The clock needed to enable the RNG
 
+Optional properties:
+- resets : The reset to properly start RNG
+
 Example:
 
rng: rng@50060800 {
-- 
2.15.1

[PATCH Resend 4/5] dt-bindings: rng: add clock detection error for stm32

[Lionel Debieve]

Add optional property to enable the clock detection error
on rng block. It is used to allow slow clock source which
give correct entropy for rng.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt 
b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
index cb7ca78135ff..1dfa7d51e006 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
@@ -13,6 +13,7 @@ Required properties:
 
 Optional properties:
 - resets : The reset to properly start RNG
+- clock-error-detect : Enable the clock detection management
 
 Example:
 
-- 
2.15.1

[PATCH Resend 4/5] dt-bindings: rng: add clock detection error for stm32

[Lionel Debieve]

Add optional property to enable the clock detection error
on rng block. It is used to allow slow clock source which
give correct entropy for rng.

Signed-off-by: Lionel Debieve 
---
 Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt 
b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
index cb7ca78135ff..1dfa7d51e006 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
@@ -13,6 +13,7 @@ Required properties:
 
 Optional properties:
 - resets : The reset to properly start RNG
+- clock-error-detect : Enable the clock detection management
 
 Example:
 
-- 
2.15.1

[PATCH Resend 1/5] hwrng: stm32 - add reset during probe

[Lionel Debieve]

Avoid issue when probing the RNG without
reset if bad status has been detected previously

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/char/hw_random/stm32-rng.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 63d84e6f1891..83c695938a2d 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define RNG_CR 0x00
@@ -46,6 +47,7 @@ struct stm32_rng_private {
struct hwrng rng;
void __iomem *base;
struct clk *clk;
+   struct reset_control *rst;
 };
 
 static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
@@ -140,6 +142,13 @@ static int stm32_rng_probe(struct platform_device *ofdev)
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
 
+   priv->rst = devm_reset_control_get(>dev, NULL);
+   if (!IS_ERR(priv->rst)) {
+   reset_control_assert(priv->rst);
+   udelay(2);
+   reset_control_deassert(priv->rst);
+   }
+
dev_set_drvdata(dev, priv);
 
priv->rng.name = dev_driver_string(dev),
-- 
2.15.1

[PATCH Resend 1/5] hwrng: stm32 - add reset during probe

[Lionel Debieve]

Avoid issue when probing the RNG without
reset if bad status has been detected previously

Signed-off-by: Lionel Debieve 
---
 drivers/char/hw_random/stm32-rng.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 63d84e6f1891..83c695938a2d 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define RNG_CR 0x00
@@ -46,6 +47,7 @@ struct stm32_rng_private {
struct hwrng rng;
void __iomem *base;
struct clk *clk;
+   struct reset_control *rst;
 };
 
 static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
@@ -140,6 +142,13 @@ static int stm32_rng_probe(struct platform_device *ofdev)
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
 
+   priv->rst = devm_reset_control_get(>dev, NULL);
+   if (!IS_ERR(priv->rst)) {
+   reset_control_assert(priv->rst);
+   udelay(2);
+   reset_control_deassert(priv->rst);
+   }
+
dev_set_drvdata(dev, priv);
 
priv->rng.name = dev_driver_string(dev),
-- 
2.15.1

[PATCH 3/5] hwrng: stm32 - allow disable clock error detection

[Lionel Debieve]

Add a new property that allow to disable the clock error
detection which is required when the clock source selected
is out of specification (which is not mandatory).

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/char/hw_random/stm32-rng.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 83c695938a2d..709a8d061be3 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -26,6 +26,7 @@
 
 #define RNG_CR 0x00
 #define RNG_CR_RNGEN BIT(2)
+#define RNG_CR_CED BIT(5)
 
 #define RNG_SR 0x04
 #define RNG_SR_SEIS BIT(6)
@@ -48,6 +49,7 @@ struct stm32_rng_private {
void __iomem *base;
struct clk *clk;
struct reset_control *rst;
+   bool ced;
 };
 
 static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
@@ -101,7 +103,11 @@ static int stm32_rng_init(struct hwrng *rng)
if (err)
return err;
 
-   writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
+   if (priv->ced)
+   writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
+   else
+   writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED,
+  priv->base + RNG_CR);
 
/* clear error indicators */
writel_relaxed(0, priv->base + RNG_SR);
@@ -149,6 +155,8 @@ static int stm32_rng_probe(struct platform_device *ofdev)
reset_control_deassert(priv->rst);
}
 
+   priv->ced = of_property_read_bool(np, "clock-error-detect");
+
dev_set_drvdata(dev, priv);
 
priv->rng.name = dev_driver_string(dev),
-- 
2.15.1

[PATCH 3/5] hwrng: stm32 - allow disable clock error detection

[Lionel Debieve]

Add a new property that allow to disable the clock error
detection which is required when the clock source selected
is out of specification (which is not mandatory).

Signed-off-by: Lionel Debieve 
---
 drivers/char/hw_random/stm32-rng.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 83c695938a2d..709a8d061be3 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -26,6 +26,7 @@
 
 #define RNG_CR 0x00
 #define RNG_CR_RNGEN BIT(2)
+#define RNG_CR_CED BIT(5)
 
 #define RNG_SR 0x04
 #define RNG_SR_SEIS BIT(6)
@@ -48,6 +49,7 @@ struct stm32_rng_private {
void __iomem *base;
struct clk *clk;
struct reset_control *rst;
+   bool ced;
 };
 
 static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
@@ -101,7 +103,11 @@ static int stm32_rng_init(struct hwrng *rng)
if (err)
return err;
 
-   writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
+   if (priv->ced)
+   writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
+   else
+   writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED,
+  priv->base + RNG_CR);
 
/* clear error indicators */
writel_relaxed(0, priv->base + RNG_SR);
@@ -149,6 +155,8 @@ static int stm32_rng_probe(struct platform_device *ofdev)
reset_control_deassert(priv->rst);
}
 
+   priv->ced = of_property_read_bool(np, "clock-error-detect");
+
dev_set_drvdata(dev, priv);
 
priv->rng.name = dev_driver_string(dev),
-- 
2.15.1

[PATCH 4/5] dt-bindings: rng: add clock detection error for stm32

[Lionel Debieve]

Add optional property to enable the clock detection error
on rng block. It is used to allow slow clock source which
give correct entropy for rng.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt 
b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
index cb7ca78135ff..1dfa7d51e006 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
@@ -13,6 +13,7 @@ Required properties:
 
 Optional properties:
 - resets : The reset to properly start RNG
+- clock-error-detect : Enable the clock detection management
 
 Example:
 
-- 
2.15.1

[PATCH 4/5] dt-bindings: rng: add clock detection error for stm32

[Lionel Debieve]

Add optional property to enable the clock detection error
on rng block. It is used to allow slow clock source which
give correct entropy for rng.

Signed-off-by: Lionel Debieve 
---
 Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt 
b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
index cb7ca78135ff..1dfa7d51e006 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
@@ -13,6 +13,7 @@ Required properties:
 
 Optional properties:
 - resets : The reset to properly start RNG
+- clock-error-detect : Enable the clock detection management
 
 Example:
 
-- 
2.15.1

[PATCH 1/5] hwrng: stm32 - add reset during probe

[Lionel Debieve]

Avoid issue when probing the RNG without
reset if bad status has been detected previously

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/char/hw_random/stm32-rng.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 63d84e6f1891..83c695938a2d 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define RNG_CR 0x00
@@ -46,6 +47,7 @@ struct stm32_rng_private {
struct hwrng rng;
void __iomem *base;
struct clk *clk;
+   struct reset_control *rst;
 };
 
 static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
@@ -140,6 +142,13 @@ static int stm32_rng_probe(struct platform_device *ofdev)
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
 
+   priv->rst = devm_reset_control_get(>dev, NULL);
+   if (!IS_ERR(priv->rst)) {
+   reset_control_assert(priv->rst);
+   udelay(2);
+   reset_control_deassert(priv->rst);
+   }
+
dev_set_drvdata(dev, priv);
 
priv->rng.name = dev_driver_string(dev),
-- 
2.15.1

[PATCH 1/5] hwrng: stm32 - add reset during probe

[Lionel Debieve]

Avoid issue when probing the RNG without
reset if bad status has been detected previously

Signed-off-by: Lionel Debieve 
---
 drivers/char/hw_random/stm32-rng.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
index 63d84e6f1891..83c695938a2d 100644
--- a/drivers/char/hw_random/stm32-rng.c
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define RNG_CR 0x00
@@ -46,6 +47,7 @@ struct stm32_rng_private {
struct hwrng rng;
void __iomem *base;
struct clk *clk;
+   struct reset_control *rst;
 };
 
 static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
@@ -140,6 +142,13 @@ static int stm32_rng_probe(struct platform_device *ofdev)
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
 
+   priv->rst = devm_reset_control_get(>dev, NULL);
+   if (!IS_ERR(priv->rst)) {
+   reset_control_assert(priv->rst);
+   udelay(2);
+   reset_control_deassert(priv->rst);
+   }
+
dev_set_drvdata(dev, priv);
 
priv->rng.name = dev_driver_string(dev),
-- 
2.15.1

[PATCH 0/5] hwrng: stm32 - Improvement for stm32-rng

[Lionel Debieve]

This set of patches add extended functionalities for stm32 rng
driver.
Patch #1 includes a reset during probe to avoid any error status
which can occur during bootup process and keep safe rng integrity.

Patch #3 adds a new property to manage the clock error detection
feature which can be disabled on specific target.

Patch #5 rework the timeout calculation for read value that was
previously defined based on loop operation and is now based on
timer.

Lionel Debieve (5):
  hwrng: stm32 - add reset during probe
  dt-bindings: rng: add reset node for stm32
  hwrng: stm32 - allow disable clock error detection
  dt-bindings: rng: add clock detection error for stm32
  hwrng: stm32 - rework read timeout calculation

 .../devicetree/bindings/rng/st,stm32-rng.txt   |  4 ++
 drivers/char/hw_random/stm32-rng.c | 44 ++
 2 files changed, 32 insertions(+), 16 deletions(-)

-- 
2.15.1

[PATCH 0/5] hwrng: stm32 - Improvement for stm32-rng

[Lionel Debieve]

This set of patches add extended functionalities for stm32 rng
driver.
Patch #1 includes a reset during probe to avoid any error status
which can occur during bootup process and keep safe rng integrity.

Patch #3 adds a new property to manage the clock error detection
feature which can be disabled on specific target.

Patch #5 rework the timeout calculation for read value that was
previously defined based on loop operation and is now based on
timer.

Lionel Debieve (5):
  hwrng: stm32 - add reset during probe
  dt-bindings: rng: add reset node for stm32
  hwrng: stm32 - allow disable clock error detection
  dt-bindings: rng: add clock detection error for stm32
  hwrng: stm32 - rework read timeout calculation

 .../devicetree/bindings/rng/st,stm32-rng.txt   |  4 ++
 drivers/char/hw_random/stm32-rng.c | 44 ++
 2 files changed, 32 insertions(+), 16 deletions(-)

-- 
2.15.1

[PATCH 2/5] dt-bindings: rng: add reset node for stm32

[Lionel Debieve]

Adding optional resets property for rng.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt 
b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
index 47f04176f93b..cb7ca78135ff 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
@@ -11,6 +11,9 @@ Required properties:
 - interrupts : The designated IRQ line for the RNG
 - clocks : The clock needed to enable the RNG
 
+Optional properties:
+- resets : The reset to properly start RNG
+
 Example:
 
rng: rng@50060800 {
-- 
2.15.1

[PATCH 2/5] dt-bindings: rng: add reset node for stm32

[Lionel Debieve]

Adding optional resets property for rng.

Signed-off-by: Lionel Debieve 
---
 Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt 
b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
index 47f04176f93b..cb7ca78135ff 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
@@ -11,6 +11,9 @@ Required properties:
 - interrupts : The designated IRQ line for the RNG
 - clocks : The clock needed to enable the RNG
 
+Optional properties:
+- resets : The reset to properly start RNG
+
 Example:
 
rng: rng@50060800 {
-- 
2.15.1

[PATCH 2/3] crypto: stm32/hash: fix performance issues

[Lionel Debieve]

From: Lionel Debieve <lionel.debi...@st.com>

Fixing bugs link to stress tests. Bad results are
detected during testmgr selftests executing in a
faster environment. bufcnt value may be resetted and
false IT are sometimes detected.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/crypto/stm32/stm32-hash.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index 73cdc3b4dca8..d8444aeb6609 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -743,13 +743,15 @@ static int stm32_hash_final_req(struct stm32_hash_dev 
*hdev)
struct ahash_request *req = hdev->req;
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
int err;
+   int buflen = rctx->bufcnt;
+
+   rctx->bufcnt = 0;
 
if (!(rctx->flags & HASH_FLAGS_CPU))
err = stm32_hash_dma_send(hdev);
else
-   err = stm32_hash_xmit_cpu(hdev, rctx->buffer, rctx->bufcnt, 1);
+   err = stm32_hash_xmit_cpu(hdev, rctx->buffer, buflen, 1);
 
-   rctx->bufcnt = 0;
 
return err;
 }
@@ -1096,6 +1098,8 @@ static irqreturn_t stm32_hash_irq_handler(int irq, void 
*dev_id)
reg &= ~HASH_SR_OUTPUT_READY;
stm32_hash_write(hdev, HASH_SR, reg);
hdev->flags |= HASH_FLAGS_OUTPUT_READY;
+   /* Disable IT*/
+   stm32_hash_write(hdev, HASH_IMR, 0);
return IRQ_WAKE_THREAD;
}
 
-- 
2.15.1

[PATCH 2/3] crypto: stm32/hash: fix performance issues

[Lionel Debieve]

From: Lionel Debieve 

Fixing bugs link to stress tests. Bad results are
detected during testmgr selftests executing in a
faster environment. bufcnt value may be resetted and
false IT are sometimes detected.

Signed-off-by: Lionel Debieve 
---
 drivers/crypto/stm32/stm32-hash.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index 73cdc3b4dca8..d8444aeb6609 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -743,13 +743,15 @@ static int stm32_hash_final_req(struct stm32_hash_dev 
*hdev)
struct ahash_request *req = hdev->req;
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
int err;
+   int buflen = rctx->bufcnt;
+
+   rctx->bufcnt = 0;
 
if (!(rctx->flags & HASH_FLAGS_CPU))
err = stm32_hash_dma_send(hdev);
else
-   err = stm32_hash_xmit_cpu(hdev, rctx->buffer, rctx->bufcnt, 1);
+   err = stm32_hash_xmit_cpu(hdev, rctx->buffer, buflen, 1);
 
-   rctx->bufcnt = 0;
 
return err;
 }
@@ -1096,6 +1098,8 @@ static irqreturn_t stm32_hash_irq_handler(int irq, void 
*dev_id)
reg &= ~HASH_SR_OUTPUT_READY;
stm32_hash_write(hdev, HASH_SR, reg);
hdev->flags |= HASH_FLAGS_OUTPUT_READY;
+   /* Disable IT*/
+   stm32_hash_write(hdev, HASH_IMR, 0);
return IRQ_WAKE_THREAD;
}
 
-- 
2.15.1

[PATCH 1/3] crypto: stm32/hash: avoid error if maxburst not defined

[Lionel Debieve]

From: Lionel Debieve <lionel.debi...@st.com>

dma-maxburst is an optional value and must not return
error in case of dma not used (or max-burst not defined).

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/crypto/stm32/stm32-hash.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index 4ca4a264a833..73cdc3b4dca8 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -1404,18 +1404,19 @@ MODULE_DEVICE_TABLE(of, stm32_hash_of_match);
 static int stm32_hash_get_of_match(struct stm32_hash_dev *hdev,
   struct device *dev)
 {
-   int err;
-
hdev->pdata = of_device_get_match_data(dev);
if (!hdev->pdata) {
dev_err(dev, "no compatible OF match\n");
return -EINVAL;
}
 
-   err = of_property_read_u32(dev->of_node, "dma-maxburst",
-  >dma_maxburst);
+   if (of_property_read_u32(dev->of_node, "dma-maxburst",
+>dma_maxburst)) {
+   dev_info(dev, "dma-maxburst not specified, using 0\n");
+   hdev->dma_maxburst = 0;
+   }
 
-   return err;
+   return 0;
 }
 
 static int stm32_hash_probe(struct platform_device *pdev)
-- 
2.15.1

[PATCH 1/3] crypto: stm32/hash: avoid error if maxburst not defined

[Lionel Debieve]

From: Lionel Debieve 

dma-maxburst is an optional value and must not return
error in case of dma not used (or max-burst not defined).

Signed-off-by: Lionel Debieve 
---
 drivers/crypto/stm32/stm32-hash.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index 4ca4a264a833..73cdc3b4dca8 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -1404,18 +1404,19 @@ MODULE_DEVICE_TABLE(of, stm32_hash_of_match);
 static int stm32_hash_get_of_match(struct stm32_hash_dev *hdev,
   struct device *dev)
 {
-   int err;
-
hdev->pdata = of_device_get_match_data(dev);
if (!hdev->pdata) {
dev_err(dev, "no compatible OF match\n");
return -EINVAL;
}
 
-   err = of_property_read_u32(dev->of_node, "dma-maxburst",
-  >dma_maxburst);
+   if (of_property_read_u32(dev->of_node, "dma-maxburst",
+>dma_maxburst)) {
+   dev_info(dev, "dma-maxburst not specified, using 0\n");
+   hdev->dma_maxburst = 0;
+   }
 
-   return err;
+   return 0;
 }
 
 static int stm32_hash_probe(struct platform_device *pdev)
-- 
2.15.1

[PATCH 3/3] crypto: stm32/hash: rework padding length

[Lionel Debieve]

From: Lionel Debieve <lionel.debi...@st.com>

Due to another patch, the dma fails when padding is
needed as the given length is not correct.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/crypto/stm32/stm32-hash.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index d8444aeb6609..80b9ec76bbb5 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -626,7 +626,7 @@ static int stm32_hash_dma_send(struct stm32_hash_dev *hdev)
writesl(hdev->io_base + HASH_DIN, buffer,
DIV_ROUND_UP(ncp, sizeof(u32)));
}
-   stm32_hash_set_nblw(hdev, DIV_ROUND_UP(ncp, sizeof(u32)));
+   stm32_hash_set_nblw(hdev, ncp);
reg = stm32_hash_read(hdev, HASH_STR);
reg |= HASH_STR_DCAL;
stm32_hash_write(hdev, HASH_STR, reg);
-- 
2.15.1

[PATCH 3/3] crypto: stm32/hash: rework padding length

[Lionel Debieve]

From: Lionel Debieve 

Due to another patch, the dma fails when padding is
needed as the given length is not correct.

Signed-off-by: Lionel Debieve 
---
 drivers/crypto/stm32/stm32-hash.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index d8444aeb6609..80b9ec76bbb5 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -626,7 +626,7 @@ static int stm32_hash_dma_send(struct stm32_hash_dev *hdev)
writesl(hdev->io_base + HASH_DIN, buffer,
DIV_ROUND_UP(ncp, sizeof(u32)));
}
-   stm32_hash_set_nblw(hdev, DIV_ROUND_UP(ncp, sizeof(u32)));
+   stm32_hash_set_nblw(hdev, ncp);
reg = stm32_hash_read(hdev, HASH_STR);
reg |= HASH_STR_DCAL;
stm32_hash_write(hdev, HASH_STR, reg);
-- 
2.15.1

[PATCH 0/3] crypto: stm32/hash: Correction to improve robustness

[Lionel Debieve]

From: Lionel Debieve <lionel.debi...@st.com>

Hi,

This patch serie will improve global robustness for stm32-hash driver. 

Patch #1 is fixing dma-burst issue when configuration is not set.
Patch #2 solves issue that occurs when irq append during final req processing.
Patch #3 is fixing an issue that have been introduced while managing padding but
breaking the padding length calculation by hardware to generate correct hash.

Regards,

Lionel Debieve (3):
  crypto: stm32/hash: avoid error if maxburst not defined
  crypto: stm32/hash: fix performance issues
  crypto: stm32/hash: rework padding length

 drivers/crypto/stm32/stm32-hash.c | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

-- 
2.15.1

[PATCH 0/3] crypto: stm32/hash: Correction to improve robustness

[Lionel Debieve]

From: Lionel Debieve 

Hi,

This patch serie will improve global robustness for stm32-hash driver. 

Patch #1 is fixing dma-burst issue when configuration is not set.
Patch #2 solves issue that occurs when irq append during final req processing.
Patch #3 is fixing an issue that have been introduced while managing padding but
breaking the padding length calculation by hardware to generate correct hash.

Regards,

Lionel Debieve (3):
  crypto: stm32/hash: avoid error if maxburst not defined
  crypto: stm32/hash: fix performance issues
  crypto: stm32/hash: rework padding length

 drivers/crypto/stm32/stm32-hash.c | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

-- 
2.15.1

[PATCH 1/1] crypto: stm32/hash - Fix return issue in update

[Lionel Debieve]

When update data reached the threshold for data processing,
we must inform that processing is on going.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/crypto/stm32/stm32-hash.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index c462be7..4ca4a26 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -895,7 +895,6 @@ static int stm32_hash_enqueue(struct ahash_request *req, 
unsigned int op)
 static int stm32_hash_update(struct ahash_request *req)
 {
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
-   int ret;
 
if (!req->nbytes || !(rctx->flags & HASH_FLAGS_CPU))
return 0;
@@ -909,12 +908,7 @@ static int stm32_hash_update(struct ahash_request *req)
return 0;
}
 
-   ret = stm32_hash_enqueue(req, HASH_OP_UPDATE);
-
-   if (rctx->flags & HASH_FLAGS_FINUP)
-   return ret;
-
-   return 0;
+   return stm32_hash_enqueue(req, HASH_OP_UPDATE);
 }
 
 static int stm32_hash_final(struct ahash_request *req)
-- 
2.7.4

[PATCH 1/1] crypto: stm32/hash - Fix return issue in update

[Lionel Debieve]

When update data reached the threshold for data processing,
we must inform that processing is on going.

Signed-off-by: Lionel Debieve 
---
 drivers/crypto/stm32/stm32-hash.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index c462be7..4ca4a26 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -895,7 +895,6 @@ static int stm32_hash_enqueue(struct ahash_request *req, 
unsigned int op)
 static int stm32_hash_update(struct ahash_request *req)
 {
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
-   int ret;
 
if (!req->nbytes || !(rctx->flags & HASH_FLAGS_CPU))
return 0;
@@ -909,12 +908,7 @@ static int stm32_hash_update(struct ahash_request *req)
return 0;
}
 
-   ret = stm32_hash_enqueue(req, HASH_OP_UPDATE);
-
-   if (rctx->flags & HASH_FLAGS_FINUP)
-   return ret;
-
-   return 0;
+   return stm32_hash_enqueue(req, HASH_OP_UPDATE);
 }
 
 static int stm32_hash_final(struct ahash_request *req)
-- 
2.7.4

Re: [PATCH 1/2] crypto: stm32 - Fix uninitialized data usage

[Lionel DEBIEVE]

Hi Arnd,

I've already push this fix for review last month, waiting the ack.

"
From: Lionel Debieve <lionel.debi...@st.com>
To: Herbert Xu <herb...@gondor.apana.org.au>, "David S . Miller"
<da...@davemloft.net>, Maxime Coquelin <mcoquelin.st...@gmail.com>, 
Alexandre
  Torgue <alexandre.tor...@st.com>, <linux-cry...@vger.kernel.org>,
<linux-arm-ker...@lists.infradead.org>, <linux-kernel@vger.kernel.org>
CC: Benjamin Gaignard <benjamin.gaign...@st.com>, Fabien Dessenne
<fabien.desse...@st.com>, Ludovic Barre <ludovic.ba...@st.com>
Subject: [PATCH 1/1] crypto: stm32/hash - Remove uninitialized symbol
Date: Fri, 18 Aug 2017 15:54:01 +0200
"

Sorry if you receive this mail twice, I didn't see any mail in the mailing 
list, maybe server issue.

I'm reviewing your second part patch.

BR,

Lionel

> On 09/12/2017 11:35 AM, Arnd Bergmann wrote:
>> The error handling in stm32_hash_irq_thread passes
>> uninitialized data into stm32_hash_finish_req, as gcc
>> points out:
>> drivers/crypto/stm32/stm32-hash.c: In function 'stm32_hash_irq_thread':
>> drivers/crypto/stm32/stm32-hash.c:1088:2: error: 'err' may be used 
>> uninitialized in this function [-Werror=maybe-uninitialized]
>> I could not tell what data should be passed there instead,
>> so this changes the code to always pass zero, making it
>> well-defined, though possibly still wrong. Please check.
>> Signed-off-by: Arnd Bergmann <a...@arndb.de>
>> ---
>>drivers/crypto/stm32/stm32-hash.c | 3 +--
>>1 file changed, 1 insertion(+), 2 deletions(-)
>> diff --git a/drivers/crypto/stm32/stm32-hash.c 
>> b/drivers/crypto/stm32/stm32-hash.c
>> index b585ce54a802..3c23a23e9ee5 100644
>> --- a/drivers/crypto/stm32/stm32-hash.c
>> +++ b/drivers/crypto/stm32/stm32-hash.c
>> @@ -1067,7 +1067,6 @@ static int stm32_hash_cra_sha256_init(struct 
>> crypto_tfm *tfm)
>>static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
>>{
>>struct stm32_hash_dev *hdev = dev_id;
>> -int err;
>>
>>if (HASH_FLAGS_CPU & hdev->flags) {
>>if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
>> @@ -1085,7 +1084,7 @@ static irqreturn_t stm32_hash_irq_thread(int irq, void 
>> *dev_id)
>>
>>finish:
>>/*Finish current request */
>> -stm32_hash_finish_req(hdev->req, err);
>> +stm32_hash_finish_req(hdev->req, 0);
>>
>>return IRQ_HANDLED;
>>}
>

Re: [PATCH 1/2] crypto: stm32 - Fix uninitialized data usage

[Lionel DEBIEVE]

Hi Arnd,

I've already push this fix for review last month, waiting the ack.

"
From: Lionel Debieve 
To: Herbert Xu , "David S . Miller"
, Maxime Coquelin , 
Alexandre
  Torgue , ,
, 
CC: Benjamin Gaignard , Fabien Dessenne
, Ludovic Barre 
Subject: [PATCH 1/1] crypto: stm32/hash - Remove uninitialized symbol
Date: Fri, 18 Aug 2017 15:54:01 +0200
"

Sorry if you receive this mail twice, I didn't see any mail in the mailing 
list, maybe server issue.

I'm reviewing your second part patch.

BR,

Lionel

> On 09/12/2017 11:35 AM, Arnd Bergmann wrote:
>> The error handling in stm32_hash_irq_thread passes
>> uninitialized data into stm32_hash_finish_req, as gcc
>> points out:
>> drivers/crypto/stm32/stm32-hash.c: In function 'stm32_hash_irq_thread':
>> drivers/crypto/stm32/stm32-hash.c:1088:2: error: 'err' may be used 
>> uninitialized in this function [-Werror=maybe-uninitialized]
>> I could not tell what data should be passed there instead,
>> so this changes the code to always pass zero, making it
>> well-defined, though possibly still wrong. Please check.
>> Signed-off-by: Arnd Bergmann 
>> ---
>>drivers/crypto/stm32/stm32-hash.c | 3 +--
>>1 file changed, 1 insertion(+), 2 deletions(-)
>> diff --git a/drivers/crypto/stm32/stm32-hash.c 
>> b/drivers/crypto/stm32/stm32-hash.c
>> index b585ce54a802..3c23a23e9ee5 100644
>> --- a/drivers/crypto/stm32/stm32-hash.c
>> +++ b/drivers/crypto/stm32/stm32-hash.c
>> @@ -1067,7 +1067,6 @@ static int stm32_hash_cra_sha256_init(struct 
>> crypto_tfm *tfm)
>>static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
>>{
>>struct stm32_hash_dev *hdev = dev_id;
>> -int err;
>>
>>if (HASH_FLAGS_CPU & hdev->flags) {
>>if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
>> @@ -1085,7 +1084,7 @@ static irqreturn_t stm32_hash_irq_thread(int irq, void 
>> *dev_id)
>>
>>finish:
>>/*Finish current request */
>> -stm32_hash_finish_req(hdev->req, err);
>> +stm32_hash_finish_req(hdev->req, 0);
>>
>>return IRQ_HANDLED;
>>}
>

[PATCH 1/1] crypto: stm32/hash - Remove uninitialized symbol

[Lionel Debieve]

Remove err symbol as this is not used in the thread context
and the variable is not initialized.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/crypto/stm32/stm32-hash.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index b585ce5..b34ee85 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -1067,7 +1067,6 @@ static int stm32_hash_cra_sha256_init(struct crypto_tfm 
*tfm)
 static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
 {
struct stm32_hash_dev *hdev = dev_id;
-   int err;
 
if (HASH_FLAGS_CPU & hdev->flags) {
if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
@@ -1084,8 +1083,8 @@ static irqreturn_t stm32_hash_irq_thread(int irq, void 
*dev_id)
return IRQ_HANDLED;
 
 finish:
-   /*Finish current request */
-   stm32_hash_finish_req(hdev->req, err);
+   /* Finish current request */
+   stm32_hash_finish_req(hdev->req, 0);
 
return IRQ_HANDLED;
 }
-- 
2.7.4

[PATCH 1/1] crypto: stm32/hash - Remove uninitialized symbol

[Lionel Debieve]

Remove err symbol as this is not used in the thread context
and the variable is not initialized.

Signed-off-by: Lionel Debieve 
---
 drivers/crypto/stm32/stm32-hash.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
index b585ce5..b34ee85 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -1067,7 +1067,6 @@ static int stm32_hash_cra_sha256_init(struct crypto_tfm 
*tfm)
 static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
 {
struct stm32_hash_dev *hdev = dev_id;
-   int err;
 
if (HASH_FLAGS_CPU & hdev->flags) {
if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
@@ -1084,8 +1083,8 @@ static irqreturn_t stm32_hash_irq_thread(int irq, void 
*dev_id)
return IRQ_HANDLED;
 
 finish:
-   /*Finish current request */
-   stm32_hash_finish_req(hdev->req, err);
+   /* Finish current request */
+   stm32_hash_finish_req(hdev->req, 0);
 
return IRQ_HANDLED;
 }
-- 
2.7.4

Re: [PATCH v5] crypto : stm32 - Add STM32F4 CRC32 support

[Lionel DEBIEVE]

Hi Cosar,
Sorry for the delay to feedback.
This implementation is in the good way. But it should be better to use 
platform data and use array with type of algs instead of
duplicating the algo description for each platform. If we add a new 
platform, with another type of crc, we will again duplicate the section.
This is how I did it in stm32-hash.c.
BR,
Lionel

On 08/03/2017 03:46 PM, Cosar Dindar wrote:
> This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
>
> As an hardware limitation polynomial and key setting are not supported.
> They are fixed as 0x4C11DB7 (poly) and 0x (key).
> CRC32C Castagnoli algorithm is not used.
>
> Signed-off-by: Cosar Dindar 
> ---
> Changes in v5:
>- shash_alg struct definitons are defined seperately according to
>  the platform type.
> Changes in v4:
>- Edited patch summary.
> Changes in v3:
>- Rearranged patch order to fix build test error.
> Changes in v2:
>- Patchset created instead of one patch.
>
>   drivers/crypto/stm32/stm32_crc32.c | 101 
> -
>   1 file changed, 89 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/crypto/stm32/stm32_crc32.c 
> b/drivers/crypto/stm32/stm32_crc32.c
> index ec83b1e..39b28b8 100644
> --- a/drivers/crypto/stm32/stm32_crc32.c
> +++ b/drivers/crypto/stm32/stm32_crc32.c
> @@ -1,12 +1,14 @@
>   /*
>* Copyright (C) STMicroelectronics SA 2017
>* Author: Fabien Dessenne 
> + * Author: Cosar Dindar 
>* License terms:  GNU General Public License (GPL), version 2
>*/
>   
>   #include 
>   #include 
>   #include 
> +#include 
>   #include 
>   
>   #include 
> @@ -37,8 +39,12 @@ struct stm32_crc {
>   struct device*dev;
>   void __iomem *regs;
>   struct clk   *clk;
> + struct shash_alg *algs;
>   u8   pending_data[sizeof(u32)];
>   size_t   nb_pending_bytes;
> + bool key_support;
> + bool poly_support;
> + bool reverse_support;
>   };
>   
>   struct stm32_crc_list {
> @@ -106,13 +112,31 @@ static int stm32_crc_init(struct shash_desc *desc)
>   }
>   spin_unlock_bh(_list.lock);
>   
> - /* Reset, set key, poly and configure in bit reverse mode */
> - writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> - writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> - writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> + /* set key */
> + if (ctx->crc->key_support) {
> + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> + } else if (mctx->key != CRC_INIT_DEFAULT) {
> + dev_err(ctx->crc->dev, "Unsupported key value! Should be: 
> 0x%x\n",
> + CRC_INIT_DEFAULT);
> + return -EINVAL;
> + }
> +
> + /* set poly */
> + if (ctx->crc->poly_support)
> + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> +
> + /* reset and configure in bit reverse mode if supported */
> + if (ctx->crc->reverse_support)
> + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> + else
> + writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
> +
> + /* store partial result */
> + if (!ctx->crc->reverse_support)
> + ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
> + else
> + ctx->partial = readl(ctx->crc->regs + CRC_DR);
>   
> - /* Store partial result */
> - ctx->partial = readl(ctx->crc->regs + CRC_DR);
>   ctx->crc->nb_pending_bytes = 0;
>   
>   return 0;
> @@ -135,7 +159,12 @@ static int stm32_crc_update(struct shash_desc *desc, 
> const u8 *d8,
>   
>   if (crc->nb_pending_bytes == sizeof(u32)) {
>   /* Process completed pending data */
> - writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + writel(bitrev32(*(u32 *)crc->pending_data),
> +crc->regs + CRC_DR);
> + else
> + writel(*(u32 *)crc->pending_data,
> +crc->regs + CRC_DR);
>   crc->nb_pending_bytes = 0;
>   }
>   }
> @@ -143,10 +172,16 @@ static int stm32_crc_update(struct shash_desc *desc, 
> const u8 *d8,
>   d32 = (u32 *)d8;
>   for (i = 0; i < length >> 2; i++)
>   /* Process 32 bits data */
> - writel(*(d32++), crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
> + else
> + writel(*(d32++), crc->regs + CRC_DR);
>   
>   /* Store partial result */
> - ctx->partial = readl(crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + 

Re: [PATCH v5] crypto : stm32 - Add STM32F4 CRC32 support

[Lionel DEBIEVE]

Hi Cosar,
Sorry for the delay to feedback.
This implementation is in the good way. But it should be better to use 
platform data and use array with type of algs instead of
duplicating the algo description for each platform. If we add a new 
platform, with another type of crc, we will again duplicate the section.
This is how I did it in stm32-hash.c.
BR,
Lionel

On 08/03/2017 03:46 PM, Cosar Dindar wrote:
> This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
>
> As an hardware limitation polynomial and key setting are not supported.
> They are fixed as 0x4C11DB7 (poly) and 0x (key).
> CRC32C Castagnoli algorithm is not used.
>
> Signed-off-by: Cosar Dindar 
> ---
> Changes in v5:
>- shash_alg struct definitons are defined seperately according to
>  the platform type.
> Changes in v4:
>- Edited patch summary.
> Changes in v3:
>- Rearranged patch order to fix build test error.
> Changes in v2:
>- Patchset created instead of one patch.
>
>   drivers/crypto/stm32/stm32_crc32.c | 101 
> -
>   1 file changed, 89 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/crypto/stm32/stm32_crc32.c 
> b/drivers/crypto/stm32/stm32_crc32.c
> index ec83b1e..39b28b8 100644
> --- a/drivers/crypto/stm32/stm32_crc32.c
> +++ b/drivers/crypto/stm32/stm32_crc32.c
> @@ -1,12 +1,14 @@
>   /*
>* Copyright (C) STMicroelectronics SA 2017
>* Author: Fabien Dessenne 
> + * Author: Cosar Dindar 
>* License terms:  GNU General Public License (GPL), version 2
>*/
>   
>   #include 
>   #include 
>   #include 
> +#include 
>   #include 
>   
>   #include 
> @@ -37,8 +39,12 @@ struct stm32_crc {
>   struct device*dev;
>   void __iomem *regs;
>   struct clk   *clk;
> + struct shash_alg *algs;
>   u8   pending_data[sizeof(u32)];
>   size_t   nb_pending_bytes;
> + bool key_support;
> + bool poly_support;
> + bool reverse_support;
>   };
>   
>   struct stm32_crc_list {
> @@ -106,13 +112,31 @@ static int stm32_crc_init(struct shash_desc *desc)
>   }
>   spin_unlock_bh(_list.lock);
>   
> - /* Reset, set key, poly and configure in bit reverse mode */
> - writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> - writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> - writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> + /* set key */
> + if (ctx->crc->key_support) {
> + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> + } else if (mctx->key != CRC_INIT_DEFAULT) {
> + dev_err(ctx->crc->dev, "Unsupported key value! Should be: 
> 0x%x\n",
> + CRC_INIT_DEFAULT);
> + return -EINVAL;
> + }
> +
> + /* set poly */
> + if (ctx->crc->poly_support)
> + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> +
> + /* reset and configure in bit reverse mode if supported */
> + if (ctx->crc->reverse_support)
> + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> + else
> + writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
> +
> + /* store partial result */
> + if (!ctx->crc->reverse_support)
> + ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
> + else
> + ctx->partial = readl(ctx->crc->regs + CRC_DR);
>   
> - /* Store partial result */
> - ctx->partial = readl(ctx->crc->regs + CRC_DR);
>   ctx->crc->nb_pending_bytes = 0;
>   
>   return 0;
> @@ -135,7 +159,12 @@ static int stm32_crc_update(struct shash_desc *desc, 
> const u8 *d8,
>   
>   if (crc->nb_pending_bytes == sizeof(u32)) {
>   /* Process completed pending data */
> - writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + writel(bitrev32(*(u32 *)crc->pending_data),
> +crc->regs + CRC_DR);
> + else
> + writel(*(u32 *)crc->pending_data,
> +crc->regs + CRC_DR);
>   crc->nb_pending_bytes = 0;
>   }
>   }
> @@ -143,10 +172,16 @@ static int stm32_crc_update(struct shash_desc *desc, 
> const u8 *d8,
>   d32 = (u32 *)d8;
>   for (i = 0; i < length >> 2; i++)
>   /* Process 32 bits data */
> - writel(*(d32++), crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
> + else
> + writel(*(d32++), crc->regs + CRC_DR);
>   
>   /* Store partial result */
> - ctx->partial = readl(crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
> + else
> + 

Re: [RESEND,PATCH v4 3/3] crypto : stm32 - Add STM32F4 CRC32 support

[Lionel DEBIEVE]

Hi Cosar,

-   ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
+   /* For F4 series only CRC32 algorithm will be used */
+   if (of_device_is_compatible(crc->dev->of_node, "st,stm32f4-crc"))
+   algs_size = 1;
+   else
+   algs_size = ARRAY_SIZE(algs);
+
+   ret = crypto_register_shashes(algs, algs_size);

Should it be better to have a dedicated array per platform data instead? Could 
be new platform update?

BR,

Lionel


On 07/17/2017 10:27 AM, Cosar Dindar wrote:
> This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
>
> As an hardware limitation polynomial and key setting are not supported.
> They are fixed as 0x4C11DB7 (poly) and 0x (key).
> CRC32C Castagnoli algorithm is not used.
>
> Signed-off-by: Cosar Dindar 
> Reviewed-by: Fabien Dessenne 
> ---
>   drivers/crypto/stm32/stm32_crc32.c | 68 
> --
>   1 file changed, 58 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/crypto/stm32/stm32_crc32.c 
> b/drivers/crypto/stm32/stm32_crc32.c
> index ec83b1e..12fbd98 100644
> --- a/drivers/crypto/stm32/stm32_crc32.c
> +++ b/drivers/crypto/stm32/stm32_crc32.c
> @@ -7,6 +7,7 @@
>   #include 
>   #include 
>   #include 
> +#include 
>   #include 
>   
>   #include 
> @@ -39,6 +40,9 @@ struct stm32_crc {
>   struct clk   *clk;
>   u8   pending_data[sizeof(u32)];
>   size_t   nb_pending_bytes;
> + bool key_support;
> + bool poly_support;
> + bool reverse_support;
>   };
>   
>   struct stm32_crc_list {
> @@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
>   }
>   spin_unlock_bh(_list.lock);
>   
> - /* Reset, set key, poly and configure in bit reverse mode */
> - writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> - writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> - writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> + /* set key */
> + if (ctx->crc->key_support) {
> + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> + } else if (mctx->key != CRC_INIT_DEFAULT) {
> + dev_err(ctx->crc->dev, "Unsupported key value! Should be: 
> 0x%x\n",
> + CRC_INIT_DEFAULT);
> + return -EINVAL;
> + }
> +
> + /* set poly */
> + if (ctx->crc->poly_support)
> + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> +
> + /* reset and configure in bit reverse mode if supported */
> + if (ctx->crc->reverse_support)
> + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> + else
> + writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
> +
> + /* store partial result */
> + if (!ctx->crc->reverse_support)
> + ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
> + else
> + ctx->partial = readl(ctx->crc->regs + CRC_DR);
>   
> - /* Store partial result */
> - ctx->partial = readl(ctx->crc->regs + CRC_DR);
>   ctx->crc->nb_pending_bytes = 0;
>   
>   return 0;
> @@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, 
> const u8 *d8,
>   
>   if (crc->nb_pending_bytes == sizeof(u32)) {
>   /* Process completed pending data */
> - writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + writel(bitrev32(*(u32 *)crc->pending_data),
> +crc->regs + CRC_DR);
> + else
> + writel(*(u32 *)crc->pending_data,
> +crc->regs + CRC_DR);
>   crc->nb_pending_bytes = 0;
>   }
>   }
> @@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc, 
> const u8 *d8,
>   d32 = (u32 *)d8;
>   for (i = 0; i < length >> 2; i++)
>   /* Process 32 bits data */
> - writel(*(d32++), crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
> + else
> + writel(*(d32++), crc->regs + CRC_DR);
>   
>   /* Store partial result */
> - ctx->partial = readl(crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
> + else
> + ctx->partial = readl(crc->regs + CRC_DR);
>   
>   /* Check for pending data (non 32 bits) */
>   length &= 3;
> @@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev)
>   struct stm32_crc *crc;
>   struct resource *res;
>   int ret;
> + int algs_size;
>   
>   crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
>   if (!crc)
> @@ 

Re: [RESEND,PATCH v4 3/3] crypto : stm32 - Add STM32F4 CRC32 support

[Lionel DEBIEVE]

Hi Cosar,

-   ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
+   /* For F4 series only CRC32 algorithm will be used */
+   if (of_device_is_compatible(crc->dev->of_node, "st,stm32f4-crc"))
+   algs_size = 1;
+   else
+   algs_size = ARRAY_SIZE(algs);
+
+   ret = crypto_register_shashes(algs, algs_size);

Should it be better to have a dedicated array per platform data instead? Could 
be new platform update?

BR,

Lionel


On 07/17/2017 10:27 AM, Cosar Dindar wrote:
> This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
>
> As an hardware limitation polynomial and key setting are not supported.
> They are fixed as 0x4C11DB7 (poly) and 0x (key).
> CRC32C Castagnoli algorithm is not used.
>
> Signed-off-by: Cosar Dindar 
> Reviewed-by: Fabien Dessenne 
> ---
>   drivers/crypto/stm32/stm32_crc32.c | 68 
> --
>   1 file changed, 58 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/crypto/stm32/stm32_crc32.c 
> b/drivers/crypto/stm32/stm32_crc32.c
> index ec83b1e..12fbd98 100644
> --- a/drivers/crypto/stm32/stm32_crc32.c
> +++ b/drivers/crypto/stm32/stm32_crc32.c
> @@ -7,6 +7,7 @@
>   #include 
>   #include 
>   #include 
> +#include 
>   #include 
>   
>   #include 
> @@ -39,6 +40,9 @@ struct stm32_crc {
>   struct clk   *clk;
>   u8   pending_data[sizeof(u32)];
>   size_t   nb_pending_bytes;
> + bool key_support;
> + bool poly_support;
> + bool reverse_support;
>   };
>   
>   struct stm32_crc_list {
> @@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
>   }
>   spin_unlock_bh(_list.lock);
>   
> - /* Reset, set key, poly and configure in bit reverse mode */
> - writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> - writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> - writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> + /* set key */
> + if (ctx->crc->key_support) {
> + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> + } else if (mctx->key != CRC_INIT_DEFAULT) {
> + dev_err(ctx->crc->dev, "Unsupported key value! Should be: 
> 0x%x\n",
> + CRC_INIT_DEFAULT);
> + return -EINVAL;
> + }
> +
> + /* set poly */
> + if (ctx->crc->poly_support)
> + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> +
> + /* reset and configure in bit reverse mode if supported */
> + if (ctx->crc->reverse_support)
> + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> + else
> + writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
> +
> + /* store partial result */
> + if (!ctx->crc->reverse_support)
> + ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
> + else
> + ctx->partial = readl(ctx->crc->regs + CRC_DR);
>   
> - /* Store partial result */
> - ctx->partial = readl(ctx->crc->regs + CRC_DR);
>   ctx->crc->nb_pending_bytes = 0;
>   
>   return 0;
> @@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, 
> const u8 *d8,
>   
>   if (crc->nb_pending_bytes == sizeof(u32)) {
>   /* Process completed pending data */
> - writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + writel(bitrev32(*(u32 *)crc->pending_data),
> +crc->regs + CRC_DR);
> + else
> + writel(*(u32 *)crc->pending_data,
> +crc->regs + CRC_DR);
>   crc->nb_pending_bytes = 0;
>   }
>   }
> @@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc, 
> const u8 *d8,
>   d32 = (u32 *)d8;
>   for (i = 0; i < length >> 2; i++)
>   /* Process 32 bits data */
> - writel(*(d32++), crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
> + else
> + writel(*(d32++), crc->regs + CRC_DR);
>   
>   /* Store partial result */
> - ctx->partial = readl(crc->regs + CRC_DR);
> + if (!ctx->crc->reverse_support)
> + ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
> + else
> + ctx->partial = readl(crc->regs + CRC_DR);
>   
>   /* Check for pending data (non 32 bits) */
>   length &= 3;
> @@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev)
>   struct stm32_crc *crc;
>   struct resource *res;
>   int ret;
> + int algs_size;
>   
>   crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
>   if (!crc)
> @@ -269,13 +303,26 @@ static int stm32_crc_probe(struct 

[PATCH 2/2] crypto: stm32 - Support for STM32 HASH module

[Lionel Debieve]

This module register a HASH module that support multiples
algorithms: MD5, SHA1, SHA224, SHA256.

It includes the support of HMAC hardware processing corresponding
to the supported algorithms. DMA or IRQ mode are used depending
on data length.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/crypto/stm32/Kconfig  |   13 +
 drivers/crypto/stm32/Makefile |1 +
 drivers/crypto/stm32/stm32-hash.c | 1576 +
 3 files changed, 1590 insertions(+)
 create mode 100644 drivers/crypto/stm32/stm32-hash.c

diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 7dd14f8..602332e 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -5,3 +5,16 @@ config CRC_DEV_STM32
help
   This enables support for the CRC32 hw accelerator which can be found
  on STMicroelectronics STM32 SOC.
+
+config HASH_DEV_STM32
+   tristate "Support for STM32 hash accelerators"
+   depends on ARCH_STM32
+   depends on HAS_DMA
+   select CRYPTO_HASH
+   select CRYPTO_MD5
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_ENGINE
+   help
+  This enables support for the HASH hw accelerator which can be found
+ on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 4db2f28..73cd56c 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
+obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
\ No newline at end of file
diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
new file mode 100644
index 000..7bba90c
--- /dev/null
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -0,0 +1,1576 @@
+/*
+ * This file is part of STM32 Crypto driver for Linux.
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Lionel DEBIEVE <lionel.debi...@st.com> for STMicroelectronics.
+ *
+ * License terms: GPL V2.0.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HASH_CR0x00
+#define HASH_DIN   0x04
+#define HASH_STR   0x08
+#define HASH_IMR   0x20
+#define HASH_SR0x24
+#define HASH_CSR(x)(0x0F8 + ((x) * 0x04))
+#define HASH_HREG(x)   (0x310 + ((x) * 0x04))
+#define HASH_HWCFGR0x3F0
+#define HASH_VER   0x3F4
+#define HASH_ID0x3F8
+
+/* Control Register */
+#define HASH_CR_INIT   BIT(2)
+#define HASH_CR_DMAE   BIT(3)
+#define HASH_CR_DATATYPE_POS   4
+#define HASH_CR_MODE   BIT(6)
+#define HASH_CR_MDMAT  BIT(13)
+#define HASH_CR_DMAA   BIT(14)
+#define HASH_CR_LKEY   BIT(16)
+
+#define HASH_CR_ALGO_SHA1  0x0
+#define HASH_CR_ALGO_MD5   0x80
+#define HASH_CR_ALGO_SHA2240x4
+#define HASH_CR_ALGO_SHA2560x40080
+
+/* Interrupt */
+#define HASH_DINIE BIT(0)
+#define HASH_DCIE  BIT(1)
+
+/* Interrupt Mask */
+#define HASH_MASK_CALC_COMPLETION  BIT(0)
+#define HASH_MASK_DATA_INPUT   BIT(1)
+
+/* Context swap register */
+#define HASH_CSR_REGISTER_NUMBER   53
+
+/* Status Flags */
+#define HASH_SR_DATA_INPUT_READY   BIT(0)
+#define HASH_SR_OUTPUT_READY   BIT(1)
+#define HASH_SR_DMA_ACTIVE BIT(2)
+#define HASH_SR_BUSY   BIT(3)
+
+/* STR Register */
+#define HASH_STR_NBLW_MASK GENMASK(4, 0)
+#define HASH_STR_DCAL  BIT(8)
+
+#define HASH_FLAGS_INITBIT(0)
+#define HASH_FLAGS_OUTPUT_READYBIT(1)
+#define HASH_FLAGS_CPU BIT(2)
+#define HASH_FLAGS_DMA_READY   BIT(3)
+#define HASH_FLAGS_DMA_ACTIVE  BIT(4)
+#define HASH_FLAGS_HMAC_INIT   BIT(5)
+#define HASH_FLAGS_HMAC_FINAL  BIT(6)
+#define HASH_FLAGS_HMAC_KEYBIT(7)

[PATCH 2/2] crypto: stm32 - Support for STM32 HASH module

[Lionel Debieve]

This module register a HASH module that support multiples
algorithms: MD5, SHA1, SHA224, SHA256.

It includes the support of HMAC hardware processing corresponding
to the supported algorithms. DMA or IRQ mode are used depending
on data length.

Signed-off-by: Lionel Debieve 
---
 drivers/crypto/stm32/Kconfig  |   13 +
 drivers/crypto/stm32/Makefile |1 +
 drivers/crypto/stm32/stm32-hash.c | 1576 +
 3 files changed, 1590 insertions(+)
 create mode 100644 drivers/crypto/stm32/stm32-hash.c

diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 7dd14f8..602332e 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -5,3 +5,16 @@ config CRC_DEV_STM32
help
   This enables support for the CRC32 hw accelerator which can be found
  on STMicroelectronics STM32 SOC.
+
+config HASH_DEV_STM32
+   tristate "Support for STM32 hash accelerators"
+   depends on ARCH_STM32
+   depends on HAS_DMA
+   select CRYPTO_HASH
+   select CRYPTO_MD5
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_ENGINE
+   help
+  This enables support for the HASH hw accelerator which can be found
+ on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 4db2f28..73cd56c 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
+obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
\ No newline at end of file
diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
new file mode 100644
index 000..7bba90c
--- /dev/null
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -0,0 +1,1576 @@
+/*
+ * This file is part of STM32 Crypto driver for Linux.
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Lionel DEBIEVE  for STMicroelectronics.
+ *
+ * License terms: GPL V2.0.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HASH_CR0x00
+#define HASH_DIN   0x04
+#define HASH_STR   0x08
+#define HASH_IMR   0x20
+#define HASH_SR0x24
+#define HASH_CSR(x)(0x0F8 + ((x) * 0x04))
+#define HASH_HREG(x)   (0x310 + ((x) * 0x04))
+#define HASH_HWCFGR0x3F0
+#define HASH_VER   0x3F4
+#define HASH_ID0x3F8
+
+/* Control Register */
+#define HASH_CR_INIT   BIT(2)
+#define HASH_CR_DMAE   BIT(3)
+#define HASH_CR_DATATYPE_POS   4
+#define HASH_CR_MODE   BIT(6)
+#define HASH_CR_MDMAT  BIT(13)
+#define HASH_CR_DMAA   BIT(14)
+#define HASH_CR_LKEY   BIT(16)
+
+#define HASH_CR_ALGO_SHA1  0x0
+#define HASH_CR_ALGO_MD5   0x80
+#define HASH_CR_ALGO_SHA2240x4
+#define HASH_CR_ALGO_SHA2560x40080
+
+/* Interrupt */
+#define HASH_DINIE BIT(0)
+#define HASH_DCIE  BIT(1)
+
+/* Interrupt Mask */
+#define HASH_MASK_CALC_COMPLETION  BIT(0)
+#define HASH_MASK_DATA_INPUT   BIT(1)
+
+/* Context swap register */
+#define HASH_CSR_REGISTER_NUMBER   53
+
+/* Status Flags */
+#define HASH_SR_DATA_INPUT_READY   BIT(0)
+#define HASH_SR_OUTPUT_READY   BIT(1)
+#define HASH_SR_DMA_ACTIVE BIT(2)
+#define HASH_SR_BUSY   BIT(3)
+
+/* STR Register */
+#define HASH_STR_NBLW_MASK GENMASK(4, 0)
+#define HASH_STR_DCAL  BIT(8)
+
+#define HASH_FLAGS_INITBIT(0)
+#define HASH_FLAGS_OUTPUT_READYBIT(1)
+#define HASH_FLAGS_CPU BIT(2)
+#define HASH_FLAGS_DMA_READY   BIT(3)
+#define HASH_FLAGS_DMA_ACTIVE  BIT(4)
+#define HASH_FLAGS_HMAC_INIT   BIT(5)
+#define HASH_FLAGS_HMAC_FINAL  BIT(6)
+#define HASH_FLAGS_HMAC_KEYBIT(7)
+
+#define HASH_FLAGS_FINAL   BIT(15)
+#define 

[PATCH 0/2] STM32 HASH crypto driver

[Lionel Debieve]

This set of patches adds a new crypto driver for STMicroelectronics stm32 HW.
This drivers uses the crypto API and provides with HW-enabled md5, sha1,
sha224, sha256 hash based algorithms.
It makes use of the crypto engine to support ahash requests.

This driver was successfully tested with tcrypt / testmgr.

Note:
Since two other set of patches (update of STM32 CRC32 and addition of STM32
CRYP) are being proposed, it may happen that there are some minor conflicts in
'Kconfig' and 'Makefile'. In that case, I will fix the issue in due course.

Lionel Debieve (2):
  dt-bindings: Document STM32 HASH bindings
  crypto: stm32 - Support for STM32 HASH module

 .../devicetree/bindings/crypto/st,stm32-hash.txt   |   30 +
 drivers/crypto/stm32/Kconfig   |   13 +
 drivers/crypto/stm32/Makefile  |1 +
 drivers/crypto/stm32/stm32-hash.c  | 1576 
 4 files changed, 1620 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-hash.txt
 create mode 100644 drivers/crypto/stm32/stm32-hash.c

-- 
2.7.4

[PATCH 0/2] STM32 HASH crypto driver

[Lionel Debieve]

This set of patches adds a new crypto driver for STMicroelectronics stm32 HW.
This drivers uses the crypto API and provides with HW-enabled md5, sha1,
sha224, sha256 hash based algorithms.
It makes use of the crypto engine to support ahash requests.

This driver was successfully tested with tcrypt / testmgr.

Note:
Since two other set of patches (update of STM32 CRC32 and addition of STM32
CRYP) are being proposed, it may happen that there are some minor conflicts in
'Kconfig' and 'Makefile'. In that case, I will fix the issue in due course.

Lionel Debieve (2):
  dt-bindings: Document STM32 HASH bindings
  crypto: stm32 - Support for STM32 HASH module

 .../devicetree/bindings/crypto/st,stm32-hash.txt   |   30 +
 drivers/crypto/stm32/Kconfig   |   13 +
 drivers/crypto/stm32/Makefile  |1 +
 drivers/crypto/stm32/stm32-hash.c  | 1576 
 4 files changed, 1620 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-hash.txt
 create mode 100644 drivers/crypto/stm32/stm32-hash.c

-- 
2.7.4

[PATCH 1/2] dt-bindings: Document STM32 HASH bindings

[Lionel Debieve]

This adds documentation of device tree bindings for the STM32
HASH controller.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 .../devicetree/bindings/crypto/st,stm32-hash.txt   | 30 ++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-hash.txt

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-hash.txt
new file mode 100644
index 000..04fc246
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.txt
@@ -0,0 +1,30 @@
+* STMicroelectronics STM32 HASH
+
+Required properties:
+- compatible: Should contain entries for this and backward compatible
+  HASH versions:
+  - "st,stm32f456-hash" for stm32 F456.
+  - "st,stm32f756-hash" for stm32 F756.
+- reg: The address and length of the peripheral registers space
+- interrupts: the interrupt specifier for the HASH
+- clocks: The input clock of the HASH instance
+
+Optional properties:
+- resets: The input reset of the HASH instance
+- dmas: DMA specifiers for the HASH. See the DMA client binding,
+Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request name. Should be "in" if a dma is present.
+- dma-maxburst: Set number of maximum dma burst supported
+
+Example:
+
+hash1: hash@50060400 {
+   compatible = "st,stm32f756-hash";
+   reg = <0x50060400 0x400>;
+   interrupts = <80>;
+   clocks = < 0 STM32F7_AHB2_CLOCK(HASH)>;
+   resets = < STM32F7_AHB2_RESET(HASH)>;
+   dmas = < 7 2 0x400 0x0>;
+   dma-names = "in";
+   dma-maxburst = <0>;
+};
-- 
2.7.4

[PATCH 1/2] dt-bindings: Document STM32 HASH bindings

[Lionel Debieve]

This adds documentation of device tree bindings for the STM32
HASH controller.

Signed-off-by: Lionel Debieve 
---
 .../devicetree/bindings/crypto/st,stm32-hash.txt   | 30 ++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-hash.txt

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-hash.txt
new file mode 100644
index 000..04fc246
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.txt
@@ -0,0 +1,30 @@
+* STMicroelectronics STM32 HASH
+
+Required properties:
+- compatible: Should contain entries for this and backward compatible
+  HASH versions:
+  - "st,stm32f456-hash" for stm32 F456.
+  - "st,stm32f756-hash" for stm32 F756.
+- reg: The address and length of the peripheral registers space
+- interrupts: the interrupt specifier for the HASH
+- clocks: The input clock of the HASH instance
+
+Optional properties:
+- resets: The input reset of the HASH instance
+- dmas: DMA specifiers for the HASH. See the DMA client binding,
+Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request name. Should be "in" if a dma is present.
+- dma-maxburst: Set number of maximum dma burst supported
+
+Example:
+
+hash1: hash@50060400 {
+   compatible = "st,stm32f756-hash";
+   reg = <0x50060400 0x400>;
+   interrupts = <80>;
+   clocks = < 0 STM32F7_AHB2_CLOCK(HASH)>;
+   resets = < STM32F7_AHB2_RESET(HASH)>;
+   dmas = < 7 2 0x400 0x0>;
+   dma-names = "in";
+   dma-maxburst = <0>;
+};
-- 
2.7.4

[PATCH 3/3] crypto: stm32 - Rename module to use generic crypto

[Lionel Debieve]

The complete stm32 module is rename as crypto
in order to use generic naming

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/Makefile   | 2 +-
 drivers/crypto/stm32/Kconfig  | 6 +++---
 drivers/crypto/stm32/Makefile | 3 +--
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 463f335..d4d69cec 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -32,7 +32,7 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
 obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
 obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
 obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
-obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32/
+obj-$(CONFIG_ARCH_STM32) += stm32/
 obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
 obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
 obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 09b4ec8..7dd14f8 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -1,7 +1,7 @@
-config CRYPTO_DEV_STM32
-   tristate "Support for STM32 crypto accelerators"
+config CRC_DEV_STM32
+   tristate "Support for STM32 crc accelerators"
depends on ARCH_STM32
select CRYPTO_HASH
help
   This enables support for the CRC32 hw accelerator which can be found
- on STMicroelectronis STM32 SOC.
+ on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 73b4c6e..4db2f28 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1,2 +1 @@
-obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32_cryp.o
-stm32_cryp-objs := stm32_crc32.o
+obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
-- 
2.7.4

[PATCH 3/3] crypto: stm32 - Rename module to use generic crypto

[Lionel Debieve]

The complete stm32 module is rename as crypto
in order to use generic naming

Signed-off-by: Lionel Debieve 
Reviewed-by: Fabien Dessenne 
---
 drivers/crypto/Makefile   | 2 +-
 drivers/crypto/stm32/Kconfig  | 6 +++---
 drivers/crypto/stm32/Makefile | 3 +--
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 463f335..d4d69cec 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -32,7 +32,7 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
 obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
 obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
 obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
-obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32/
+obj-$(CONFIG_ARCH_STM32) += stm32/
 obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
 obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
 obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 09b4ec8..7dd14f8 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -1,7 +1,7 @@
-config CRYPTO_DEV_STM32
-   tristate "Support for STM32 crypto accelerators"
+config CRC_DEV_STM32
+   tristate "Support for STM32 crc accelerators"
depends on ARCH_STM32
select CRYPTO_HASH
help
   This enables support for the CRC32 hw accelerator which can be found
- on STMicroelectronis STM32 SOC.
+ on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 73b4c6e..4db2f28 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1,2 +1 @@
-obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32_cryp.o
-stm32_cryp-objs := stm32_crc32.o
+obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
-- 
2.7.4

[PATCH 1/3] crypto: stm32 - CRC use relaxed function

[Lionel Debieve]

In case of arm soc support, readl and writel will
be optimized using relaxed functions

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/stm32/stm32_crc32.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/crypto/stm32/stm32_crc32.c 
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..04d2f4b 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -107,12 +107,12 @@ static int stm32_crc_init(struct shash_desc *desc)
spin_unlock_bh(_list.lock);
 
/* Reset, set key, poly and configure in bit reverse mode */
-   writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
-   writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
-   writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+   writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+   writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+   writel_relaxed(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
 
/* Store partial result */
-   ctx->partial = readl(ctx->crc->regs + CRC_DR);
+   ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR);
ctx->crc->nb_pending_bytes = 0;
 
return 0;
@@ -135,7 +135,8 @@ static int stm32_crc_update(struct shash_desc *desc, const 
u8 *d8,
 
if (crc->nb_pending_bytes == sizeof(u32)) {
/* Process completed pending data */
-   writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
+   writel_relaxed(*(u32 *)crc->pending_data,
+  crc->regs + CRC_DR);
crc->nb_pending_bytes = 0;
}
}
@@ -143,10 +144,10 @@ static int stm32_crc_update(struct shash_desc *desc, 
const u8 *d8,
d32 = (u32 *)d8;
for (i = 0; i < length >> 2; i++)
/* Process 32 bits data */
-   writel(*(d32++), crc->regs + CRC_DR);
+   writel_relaxed(*(d32++), crc->regs + CRC_DR);
 
/* Store partial result */
-   ctx->partial = readl(crc->regs + CRC_DR);
+   ctx->partial = readl_relaxed(crc->regs + CRC_DR);
 
/* Check for pending data (non 32 bits) */
length &= 3;
-- 
2.7.4

[PATCH 1/3] crypto: stm32 - CRC use relaxed function

[Lionel Debieve]

In case of arm soc support, readl and writel will
be optimized using relaxed functions

Signed-off-by: Lionel Debieve 
Reviewed-by: Fabien Dessenne 
---
 drivers/crypto/stm32/stm32_crc32.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/crypto/stm32/stm32_crc32.c 
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..04d2f4b 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -107,12 +107,12 @@ static int stm32_crc_init(struct shash_desc *desc)
spin_unlock_bh(_list.lock);
 
/* Reset, set key, poly and configure in bit reverse mode */
-   writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
-   writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
-   writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+   writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+   writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+   writel_relaxed(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
 
/* Store partial result */
-   ctx->partial = readl(ctx->crc->regs + CRC_DR);
+   ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR);
ctx->crc->nb_pending_bytes = 0;
 
return 0;
@@ -135,7 +135,8 @@ static int stm32_crc_update(struct shash_desc *desc, const 
u8 *d8,
 
if (crc->nb_pending_bytes == sizeof(u32)) {
/* Process completed pending data */
-   writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
+   writel_relaxed(*(u32 *)crc->pending_data,
+  crc->regs + CRC_DR);
crc->nb_pending_bytes = 0;
}
}
@@ -143,10 +144,10 @@ static int stm32_crc_update(struct shash_desc *desc, 
const u8 *d8,
d32 = (u32 *)d8;
for (i = 0; i < length >> 2; i++)
/* Process 32 bits data */
-   writel(*(d32++), crc->regs + CRC_DR);
+   writel_relaxed(*(d32++), crc->regs + CRC_DR);
 
/* Store partial result */
-   ctx->partial = readl(crc->regs + CRC_DR);
+   ctx->partial = readl_relaxed(crc->regs + CRC_DR);
 
/* Check for pending data (non 32 bits) */
length &= 3;
-- 
2.7.4

[PATCH 0/3] STM32 CRC update

[Lionel Debieve]

This set of patches update the STM32 CRC driver.
It contains two corrections and one global Kconfig rework.
First correction is about the relaxed usage in scope of arm
platform usage, second about a unbind driver issue.
Last patch is about a Kconfig rework that make configuration
generic for STM32 crypto algos, HASH and CRYP are pushed
accordingly.

Lionel Debieve (3):
  crypto: stm32 - CRC use relaxed function
  crypto: stm32 - solve crc issue during unbind
  crypto: stm32 - Rename module to use generic crypto

 drivers/crypto/Makefile|  2 +-
 drivers/crypto/stm32/Kconfig   |  6 +++---
 drivers/crypto/stm32/Makefile  |  3 +--
 drivers/crypto/stm32/stm32_crc32.c | 17 +
 4 files changed, 14 insertions(+), 14 deletions(-)

-- 
2.7.4

[PATCH 2/3] crypto: stm32 - solve crc issue during unbind

[Lionel Debieve]

Use the correct unregister_shashes function to
to remove the registered algo

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>
---
 drivers/crypto/stm32/stm32_crc32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/stm32/stm32_crc32.c 
b/drivers/crypto/stm32/stm32_crc32.c
index 04d2f4b..090582b 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -296,7 +296,7 @@ static int stm32_crc_remove(struct platform_device *pdev)
list_del(>list);
spin_unlock(_list.lock);
 
-   crypto_unregister_shash(algs);
+   crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
 
clk_disable_unprepare(crc->clk);
 
-- 
2.7.4

[PATCH 0/3] STM32 CRC update

[Lionel Debieve]

This set of patches update the STM32 CRC driver.
It contains two corrections and one global Kconfig rework.
First correction is about the relaxed usage in scope of arm
platform usage, second about a unbind driver issue.
Last patch is about a Kconfig rework that make configuration
generic for STM32 crypto algos, HASH and CRYP are pushed
accordingly.

Lionel Debieve (3):
  crypto: stm32 - CRC use relaxed function
  crypto: stm32 - solve crc issue during unbind
  crypto: stm32 - Rename module to use generic crypto

 drivers/crypto/Makefile|  2 +-
 drivers/crypto/stm32/Kconfig   |  6 +++---
 drivers/crypto/stm32/Makefile  |  3 +--
 drivers/crypto/stm32/stm32_crc32.c | 17 +
 4 files changed, 14 insertions(+), 14 deletions(-)

-- 
2.7.4

[PATCH 2/3] crypto: stm32 - solve crc issue during unbind

[Lionel Debieve]

Use the correct unregister_shashes function to
to remove the registered algo

Signed-off-by: Lionel Debieve 
Reviewed-by: Fabien Dessenne 
---
 drivers/crypto/stm32/stm32_crc32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/stm32/stm32_crc32.c 
b/drivers/crypto/stm32/stm32_crc32.c
index 04d2f4b..090582b 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -296,7 +296,7 @@ static int stm32_crc_remove(struct platform_device *pdev)
list_del(>list);
spin_unlock(_list.lock);
 
-   crypto_unregister_shash(algs);
+   crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
 
clk_disable_unprepare(crc->clk);
 
-- 
2.7.4

Re: [PATCH RT 1/1] remoteproc: Prevent schedule while atomic

[Lionel DEBIEVE]

Hi,

Looking at the thread discussion, except architecture discussion around the 
IRQF_ONESHOT, I think it could go to upstream too.

I'll re-upload patch for upstream.

Thanks for reviewing.

BR,

Lionel


On 03/30/2017 09:54 AM, Lee Jones wrote:
> On Wed, 29 Mar 2017, Sebastian Andrzej Siewior wrote:
>
>> On 2017-03-22 09:05:58 [-0700], Steven Rostedt wrote:
>>> On Wed, 22 Mar 2017 16:18:43 +0100
>>> Lionel Debieve <lionel.debi...@st.com> wrote:
>>>
>>>> Use raw_spin_lock in enable/disable channel as it comes from
>>>> interrupt context.
>>>>
>>>> BUG: sleeping function called from invalid context at
>>>> kernel/locking/rtmutex.c:995
>>>> in_atomic(): 1, irqs_disabled(): 128, pid: 307, name: pulseaudio
>>>> Preemption disabled at:
>>>> [] __handle_domain_irq+0x4c/0xec
>>>> CPU: 0 PID: 307 Comm: pulseaudio
>>>> Hardware name: STi SoC with Flattened Device Tree
>>>> [] (unwind_backtrace)
>>>> [] (show_stack)
>>>> [] (dump_stack)
>>>> [] (___might_sleep)
>>>> [] (rt_spin_lock)
>>>> [] (sti_mbox_disable_channel)
>>>> [] (sti_mbox_irq_handler)
>>>> [] (__handle_irq_event_percpu)
>>>> [] (handle_irq_event_percpu)
>>>> [] (handle_irq_event)
>>>> [] (handle_fasteoi_irq)
>>>> [] (generic_handle_irq)
>>>> [] (__handle_domain_irq)
>>>> [] (gic_handle_irq)
>>>>
>>>> Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
>>> Looks fine to me. Should this go to mainline?
>>>
>>> Acked-by: Steven Rostedt (VMware) <rost...@goodmis.org>
>> Could this be applied upstream, please? From looking at the thread there
>> was no reason not to do so.
> Acked-by: Lee Jones <lee.jo...@linaro.org>
>
>>>> ---
>>>>   drivers/mailbox/mailbox-sti.c | 12 ++--
>>>>   1 file changed, 6 insertions(+), 6 deletions(-)
>>>>
>>>> diff --git a/drivers/mailbox/mailbox-sti.c
>>>> b/drivers/mailbox/mailbox-sti.c index 41bcd33..f9674ca 100644
>>>> --- a/drivers/mailbox/mailbox-sti.c
>>>> +++ b/drivers/mailbox/mailbox-sti.c
>>>> @@ -60,7 +60,7 @@ struct sti_mbox_device {
>>>>void __iomem*base;
>>>>const char  *name;
>>>>u32 enabled[STI_MBOX_INST_MAX];
>>>> -  spinlock_t  lock;
>>>> +  raw_spinlock_t  lock;
>>>>   };
>>>>   
>>>>   /**
>>>> @@ -129,10 +129,10 @@ static void sti_mbox_enable_channel(struct
>>>> mbox_chan *chan) unsigned long flags;
>>>>void __iomem *base = MBOX_BASE(mdev, instance);
>>>>   
>>>> -  spin_lock_irqsave(>lock, flags);
>>>> +  raw_spin_lock_irqsave(>lock, flags);
>>>>mdev->enabled[instance] |= BIT(channel);
>>>>writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET);
>>>> -  spin_unlock_irqrestore(>lock, flags);
>>>> +  raw_spin_unlock_irqrestore(>lock, flags);
>>>>   }
>>>>   
>>>>   static void sti_mbox_disable_channel(struct mbox_chan *chan)
>>>> @@ -144,10 +144,10 @@ static void sti_mbox_disable_channel(struct
>>>> mbox_chan *chan) unsigned long flags;
>>>>void __iomem *base = MBOX_BASE(mdev, instance);
>>>>   
>>>> -  spin_lock_irqsave(>lock, flags);
>>>> +  raw_spin_lock_irqsave(>lock, flags);
>>>>mdev->enabled[instance] &= ~BIT(channel);
>>>>writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET);
>>>> -  spin_unlock_irqrestore(>lock, flags);
>>>> +  raw_spin_unlock_irqrestore(>lock, flags);
>>>>   }
>>>>   
>>>>   static void sti_mbox_clear_irq(struct mbox_chan *chan)
>>>> @@ -450,7 +450,7 @@ static int sti_mbox_probe(struct platform_device
>>>> *pdev) mdev->dev   = >dev;
>>>>mdev->mbox  = mbox;
>>>>   
>>>> -  spin_lock_init(>lock);
>>>> +  raw_spin_lock_init(>lock);
>>>>   
>>>>/* STi Mailbox does not have a Tx-Done or Tx-Ready IRQ */
>>>>mbox->txdone_irq= false;
>> Sebastian

Re: [PATCH RT 1/1] remoteproc: Prevent schedule while atomic

[Lionel DEBIEVE]

Hi,

Looking at the thread discussion, except architecture discussion around the 
IRQF_ONESHOT, I think it could go to upstream too.

I'll re-upload patch for upstream.

Thanks for reviewing.

BR,

Lionel


On 03/30/2017 09:54 AM, Lee Jones wrote:
> On Wed, 29 Mar 2017, Sebastian Andrzej Siewior wrote:
>
>> On 2017-03-22 09:05:58 [-0700], Steven Rostedt wrote:
>>> On Wed, 22 Mar 2017 16:18:43 +0100
>>> Lionel Debieve  wrote:
>>>
>>>> Use raw_spin_lock in enable/disable channel as it comes from
>>>> interrupt context.
>>>>
>>>> BUG: sleeping function called from invalid context at
>>>> kernel/locking/rtmutex.c:995
>>>> in_atomic(): 1, irqs_disabled(): 128, pid: 307, name: pulseaudio
>>>> Preemption disabled at:
>>>> [] __handle_domain_irq+0x4c/0xec
>>>> CPU: 0 PID: 307 Comm: pulseaudio
>>>> Hardware name: STi SoC with Flattened Device Tree
>>>> [] (unwind_backtrace)
>>>> [] (show_stack)
>>>> [] (dump_stack)
>>>> [] (___might_sleep)
>>>> [] (rt_spin_lock)
>>>> [] (sti_mbox_disable_channel)
>>>> [] (sti_mbox_irq_handler)
>>>> [] (__handle_irq_event_percpu)
>>>> [] (handle_irq_event_percpu)
>>>> [] (handle_irq_event)
>>>> [] (handle_fasteoi_irq)
>>>> [] (generic_handle_irq)
>>>> [] (__handle_domain_irq)
>>>> [] (gic_handle_irq)
>>>>
>>>> Signed-off-by: Lionel Debieve 
>>> Looks fine to me. Should this go to mainline?
>>>
>>> Acked-by: Steven Rostedt (VMware) 
>> Could this be applied upstream, please? From looking at the thread there
>> was no reason not to do so.
> Acked-by: Lee Jones 
>
>>>> ---
>>>>   drivers/mailbox/mailbox-sti.c | 12 ++--
>>>>   1 file changed, 6 insertions(+), 6 deletions(-)
>>>>
>>>> diff --git a/drivers/mailbox/mailbox-sti.c
>>>> b/drivers/mailbox/mailbox-sti.c index 41bcd33..f9674ca 100644
>>>> --- a/drivers/mailbox/mailbox-sti.c
>>>> +++ b/drivers/mailbox/mailbox-sti.c
>>>> @@ -60,7 +60,7 @@ struct sti_mbox_device {
>>>>void __iomem*base;
>>>>const char  *name;
>>>>u32 enabled[STI_MBOX_INST_MAX];
>>>> -  spinlock_t  lock;
>>>> +  raw_spinlock_t  lock;
>>>>   };
>>>>   
>>>>   /**
>>>> @@ -129,10 +129,10 @@ static void sti_mbox_enable_channel(struct
>>>> mbox_chan *chan) unsigned long flags;
>>>>void __iomem *base = MBOX_BASE(mdev, instance);
>>>>   
>>>> -  spin_lock_irqsave(>lock, flags);
>>>> +  raw_spin_lock_irqsave(>lock, flags);
>>>>mdev->enabled[instance] |= BIT(channel);
>>>>writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET);
>>>> -  spin_unlock_irqrestore(>lock, flags);
>>>> +  raw_spin_unlock_irqrestore(>lock, flags);
>>>>   }
>>>>   
>>>>   static void sti_mbox_disable_channel(struct mbox_chan *chan)
>>>> @@ -144,10 +144,10 @@ static void sti_mbox_disable_channel(struct
>>>> mbox_chan *chan) unsigned long flags;
>>>>void __iomem *base = MBOX_BASE(mdev, instance);
>>>>   
>>>> -  spin_lock_irqsave(>lock, flags);
>>>> +  raw_spin_lock_irqsave(>lock, flags);
>>>>mdev->enabled[instance] &= ~BIT(channel);
>>>>writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET);
>>>> -  spin_unlock_irqrestore(>lock, flags);
>>>> +  raw_spin_unlock_irqrestore(>lock, flags);
>>>>   }
>>>>   
>>>>   static void sti_mbox_clear_irq(struct mbox_chan *chan)
>>>> @@ -450,7 +450,7 @@ static int sti_mbox_probe(struct platform_device
>>>> *pdev) mdev->dev   = >dev;
>>>>mdev->mbox  = mbox;
>>>>   
>>>> -  spin_lock_init(>lock);
>>>> +  raw_spin_lock_init(>lock);
>>>>   
>>>>/* STi Mailbox does not have a Tx-Done or Tx-Ready IRQ */
>>>>mbox->txdone_irq= false;
>> Sebastian

Re: [PATCH RT 1/1] remoteproc: Prevent schedule while atomic

[Lionel DEBIEVE]

On 03/22/2017 07:47 PM, Julia Cartwright wrote:
> On Wed, Mar 22, 2017 at 01:30:12PM -0500, Grygorii Strashko wrote:
>> On 03/22/2017 01:01 PM, Steven Rostedt wrote:
>>> On Wed, 22 Mar 2017 12:37:59 -0500
>>> Julia Cartwright  wrote:
>>>
 Which kernel were you testing on, here?  From what I can tell, this
 should have been fixed with Thomas's commit:

 2a1d3ab8986d ("genirq: Handle force threading of irqs with primary
 and thread handler")
>>> Thanks Julia for looking into this. I just looked at the code, and saw
>>> that it does very little with the lock held, and was fine with the
>>> conversion. But if that interrupt handler should be in a thread, we
>>> should see if that's the issue first.
>>
>> It will not be threaded because there are IRQF_ONESHOT used.
>>
>>  ret = devm_request_threaded_irq(>dev, irq,
>>  sti_mbox_irq_handler,
>>  sti_mbox_thread_handler,
>>  IRQF_ONESHOT, mdev->name, mdev);
> Indeed.  I had skipped over this important detail when I was skimming
> through the code.
>
> Thanks for clarifying!
>
> Is IRQF_ONESHOT really necessary for this device?  The primary handler
> invokes sti_mbox_disable_channel() on the interrupting channel, which I
> would hope would acquiesce the pending interrupt at the device-level?
>
> Also, as written there are num_inst reads of STI_IRQ_VAL_OFFSET in the
> primary handler, which seems inefficient...(unless of course reading
> incurs side effects, here).
>
> Julia

First to reply Julia, test was made using 4.9.y kernel branch.
For the IRQF_ONESHOT, I rely on Lee (adding in mail thread) that was at the 
device driver origin.

Steven, you're also right as the patch can be also pushed in mainline too.

Lionel

Re: [PATCH RT 1/1] remoteproc: Prevent schedule while atomic

[Lionel DEBIEVE]

On 03/22/2017 07:47 PM, Julia Cartwright wrote:
> On Wed, Mar 22, 2017 at 01:30:12PM -0500, Grygorii Strashko wrote:
>> On 03/22/2017 01:01 PM, Steven Rostedt wrote:
>>> On Wed, 22 Mar 2017 12:37:59 -0500
>>> Julia Cartwright  wrote:
>>>
 Which kernel were you testing on, here?  From what I can tell, this
 should have been fixed with Thomas's commit:

 2a1d3ab8986d ("genirq: Handle force threading of irqs with primary
 and thread handler")
>>> Thanks Julia for looking into this. I just looked at the code, and saw
>>> that it does very little with the lock held, and was fine with the
>>> conversion. But if that interrupt handler should be in a thread, we
>>> should see if that's the issue first.
>>
>> It will not be threaded because there are IRQF_ONESHOT used.
>>
>>  ret = devm_request_threaded_irq(>dev, irq,
>>  sti_mbox_irq_handler,
>>  sti_mbox_thread_handler,
>>  IRQF_ONESHOT, mdev->name, mdev);
> Indeed.  I had skipped over this important detail when I was skimming
> through the code.
>
> Thanks for clarifying!
>
> Is IRQF_ONESHOT really necessary for this device?  The primary handler
> invokes sti_mbox_disable_channel() on the interrupting channel, which I
> would hope would acquiesce the pending interrupt at the device-level?
>
> Also, as written there are num_inst reads of STI_IRQ_VAL_OFFSET in the
> primary handler, which seems inefficient...(unless of course reading
> incurs side effects, here).
>
> Julia

First to reply Julia, test was made using 4.9.y kernel branch.
For the IRQF_ONESHOT, I rely on Lee (adding in mail thread) that was at the 
device driver origin.

Steven, you're also right as the patch can be also pushed in mainline too.

Lionel

Re: [PATCH RT 1/1] remoteproc: Prevent schedule while atomic

[Lionel DEBIEVE]

On 03/22/2017 05:05 PM, Steven Rostedt wrote:
> On Wed, 22 Mar 2017 16:18:43 +0100
> Lionel Debieve <lionel.debi...@st.com> wrote:
>
>> Use raw_spin_lock in enable/disable channel as it comes from
>> interrupt context.
>>
>> BUG: sleeping function called from invalid context at
>> kernel/locking/rtmutex.c:995
>> in_atomic(): 1, irqs_disabled(): 128, pid: 307, name: pulseaudio
>> Preemption disabled at:
>> [] __handle_domain_irq+0x4c/0xec
>> CPU: 0 PID: 307 Comm: pulseaudio
>> Hardware name: STi SoC with Flattened Device Tree
>> [] (unwind_backtrace)
>> [] (show_stack)
>> [] (dump_stack)
>> [] (___might_sleep)
>> [] (rt_spin_lock)
>> [] (sti_mbox_disable_channel)
>> [] (sti_mbox_irq_handler)
>> [] (__handle_irq_event_percpu)
>> [] (handle_irq_event_percpu)
>> [] (handle_irq_event)
>> [] (handle_fasteoi_irq)
>> [] (generic_handle_irq)
>> [] (__handle_domain_irq)
>> [] (gic_handle_irq)
>>
>> Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
> Looks fine to me. Should this go to mainline?
>
> Acked-by: Steven Rostedt (VMware) <rost...@goodmis.org>
>
> -- Steve

Will look deeper if it can be.

Lionel

>
>> ---
>>   drivers/mailbox/mailbox-sti.c | 12 ++--
>>   1 file changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/mailbox/mailbox-sti.c
>> b/drivers/mailbox/mailbox-sti.c index 41bcd33..f9674ca 100644
>> --- a/drivers/mailbox/mailbox-sti.c
>> +++ b/drivers/mailbox/mailbox-sti.c
>> @@ -60,7 +60,7 @@ struct sti_mbox_device {
>>  void __iomem*base;
>>  const char  *name;
>>  u32 enabled[STI_MBOX_INST_MAX];
>> -spinlock_t  lock;
>> +raw_spinlock_t  lock;
>>   };
>>   
>>   /**
>> @@ -129,10 +129,10 @@ static void sti_mbox_enable_channel(struct
>> mbox_chan *chan) unsigned long flags;
>>  void __iomem *base = MBOX_BASE(mdev, instance);
>>   
>> -spin_lock_irqsave(>lock, flags);
>> +raw_spin_lock_irqsave(>lock, flags);
>>  mdev->enabled[instance] |= BIT(channel);
>>  writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET);
>> -spin_unlock_irqrestore(>lock, flags);
>> +raw_spin_unlock_irqrestore(>lock, flags);
>>   }
>>   
>>   static void sti_mbox_disable_channel(struct mbox_chan *chan)
>> @@ -144,10 +144,10 @@ static void sti_mbox_disable_channel(struct
>> mbox_chan *chan) unsigned long flags;
>>  void __iomem *base = MBOX_BASE(mdev, instance);
>>   
>> -spin_lock_irqsave(>lock, flags);
>> +raw_spin_lock_irqsave(>lock, flags);
>>  mdev->enabled[instance] &= ~BIT(channel);
>>  writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET);
>> -spin_unlock_irqrestore(>lock, flags);
>> +raw_spin_unlock_irqrestore(>lock, flags);
>>   }
>>   
>>   static void sti_mbox_clear_irq(struct mbox_chan *chan)
>> @@ -450,7 +450,7 @@ static int sti_mbox_probe(struct platform_device
>> *pdev) mdev->dev = >dev;
>>  mdev->mbox  = mbox;
>>   
>> -spin_lock_init(>lock);
>> +raw_spin_lock_init(>lock);
>>   
>>  /* STi Mailbox does not have a Tx-Done or Tx-Ready IRQ */
>>  mbox->txdone_irq= false;
>

Re: [PATCH RT 1/1] remoteproc: Prevent schedule while atomic

[Lionel DEBIEVE]

On 03/22/2017 05:05 PM, Steven Rostedt wrote:
> On Wed, 22 Mar 2017 16:18:43 +0100
> Lionel Debieve  wrote:
>
>> Use raw_spin_lock in enable/disable channel as it comes from
>> interrupt context.
>>
>> BUG: sleeping function called from invalid context at
>> kernel/locking/rtmutex.c:995
>> in_atomic(): 1, irqs_disabled(): 128, pid: 307, name: pulseaudio
>> Preemption disabled at:
>> [] __handle_domain_irq+0x4c/0xec
>> CPU: 0 PID: 307 Comm: pulseaudio
>> Hardware name: STi SoC with Flattened Device Tree
>> [] (unwind_backtrace)
>> [] (show_stack)
>> [] (dump_stack)
>> [] (___might_sleep)
>> [] (rt_spin_lock)
>> [] (sti_mbox_disable_channel)
>> [] (sti_mbox_irq_handler)
>> [] (__handle_irq_event_percpu)
>> [] (handle_irq_event_percpu)
>> [] (handle_irq_event)
>> [] (handle_fasteoi_irq)
>> [] (generic_handle_irq)
>> [] (__handle_domain_irq)
>> [] (gic_handle_irq)
>>
>> Signed-off-by: Lionel Debieve 
> Looks fine to me. Should this go to mainline?
>
> Acked-by: Steven Rostedt (VMware) 
>
> -- Steve

Will look deeper if it can be.

Lionel

>
>> ---
>>   drivers/mailbox/mailbox-sti.c | 12 ++--
>>   1 file changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/mailbox/mailbox-sti.c
>> b/drivers/mailbox/mailbox-sti.c index 41bcd33..f9674ca 100644
>> --- a/drivers/mailbox/mailbox-sti.c
>> +++ b/drivers/mailbox/mailbox-sti.c
>> @@ -60,7 +60,7 @@ struct sti_mbox_device {
>>  void __iomem*base;
>>  const char  *name;
>>  u32 enabled[STI_MBOX_INST_MAX];
>> -spinlock_t  lock;
>> +raw_spinlock_t  lock;
>>   };
>>   
>>   /**
>> @@ -129,10 +129,10 @@ static void sti_mbox_enable_channel(struct
>> mbox_chan *chan) unsigned long flags;
>>  void __iomem *base = MBOX_BASE(mdev, instance);
>>   
>> -spin_lock_irqsave(>lock, flags);
>> +raw_spin_lock_irqsave(>lock, flags);
>>  mdev->enabled[instance] |= BIT(channel);
>>  writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET);
>> -spin_unlock_irqrestore(>lock, flags);
>> +raw_spin_unlock_irqrestore(>lock, flags);
>>   }
>>   
>>   static void sti_mbox_disable_channel(struct mbox_chan *chan)
>> @@ -144,10 +144,10 @@ static void sti_mbox_disable_channel(struct
>> mbox_chan *chan) unsigned long flags;
>>  void __iomem *base = MBOX_BASE(mdev, instance);
>>   
>> -spin_lock_irqsave(>lock, flags);
>> +raw_spin_lock_irqsave(>lock, flags);
>>  mdev->enabled[instance] &= ~BIT(channel);
>>  writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET);
>> -spin_unlock_irqrestore(>lock, flags);
>> +raw_spin_unlock_irqrestore(>lock, flags);
>>   }
>>   
>>   static void sti_mbox_clear_irq(struct mbox_chan *chan)
>> @@ -450,7 +450,7 @@ static int sti_mbox_probe(struct platform_device
>> *pdev) mdev->dev = >dev;
>>  mdev->mbox  = mbox;
>>   
>> -spin_lock_init(>lock);
>> +raw_spin_lock_init(>lock);
>>   
>>  /* STi Mailbox does not have a Tx-Done or Tx-Ready IRQ */
>>  mbox->txdone_irq= false;
>

[PATCH 1/1] tty: serial: st-asc: Make the locking RT aware

[Lionel Debieve]

The lock is a sleeping lock and local_irq_save() is not the
standard implementation now. Working for both -RT and non
RT.

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/tty/serial/st-asc.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/st-asc.c b/drivers/tty/serial/st-asc.c
index c334bcc..4889396 100644
--- a/drivers/tty/serial/st-asc.c
+++ b/drivers/tty/serial/st-asc.c
@@ -887,13 +887,12 @@ static void asc_console_write(struct console *co, const 
char *s, unsigned count)
int locked = 1;
u32 intenable;
 
-   local_irq_save(flags);
if (port->sysrq)
locked = 0; /* asc_interrupt has already claimed the lock */
else if (oops_in_progress)
-   locked = spin_trylock(>lock);
+   locked = spin_trylock_irqsave(>lock, flags);
else
-   spin_lock(>lock);
+   spin_lock_irqsave(>lock, flags);
 
/*
 * Disable interrupts so we don't get the IRQ line bouncing
@@ -911,8 +910,7 @@ static void asc_console_write(struct console *co, const 
char *s, unsigned count)
asc_out(port, ASC_INTEN, intenable);
 
if (locked)
-   spin_unlock(>lock);
-   local_irq_restore(flags);
+   spin_unlock_irqrestore(>lock, flags);
 }
 
 static int asc_console_setup(struct console *co, char *options)
-- 
2.7.4

[PATCH 1/1] tty: serial: st-asc: Make the locking RT aware

[Lionel Debieve]

The lock is a sleeping lock and local_irq_save() is not the
standard implementation now. Working for both -RT and non
RT.

Signed-off-by: Lionel Debieve 
---
 drivers/tty/serial/st-asc.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/st-asc.c b/drivers/tty/serial/st-asc.c
index c334bcc..4889396 100644
--- a/drivers/tty/serial/st-asc.c
+++ b/drivers/tty/serial/st-asc.c
@@ -887,13 +887,12 @@ static void asc_console_write(struct console *co, const 
char *s, unsigned count)
int locked = 1;
u32 intenable;
 
-   local_irq_save(flags);
if (port->sysrq)
locked = 0; /* asc_interrupt has already claimed the lock */
else if (oops_in_progress)
-   locked = spin_trylock(>lock);
+   locked = spin_trylock_irqsave(>lock, flags);
else
-   spin_lock(>lock);
+   spin_lock_irqsave(>lock, flags);
 
/*
 * Disable interrupts so we don't get the IRQ line bouncing
@@ -911,8 +910,7 @@ static void asc_console_write(struct console *co, const 
char *s, unsigned count)
asc_out(port, ASC_INTEN, intenable);
 
if (locked)
-   spin_unlock(>lock);
-   local_irq_restore(flags);
+   spin_unlock_irqrestore(>lock, flags);
 }
 
 static int asc_console_setup(struct console *co, char *options)
-- 
2.7.4

RE: [PATCH RT] tty: serial: st-asc: Make the locking RT aware

[Lionel DEBIEVE]

OK, resend without.
BR
Lionel

-Original Message-
From: Steven Rostedt [mailto:rost...@goodmis.org] 
Sent: mercredi 22 mars 2017 17:11
To: Lionel DEBIEVE <lionel.debi...@st.com>
Cc: Thomas Gleixner <t...@linutronix.de>; linux-rt-us...@vger.kernel.org; 
linux-kernel@vger.kernel.org; bige...@linutronix.de; Patrice CHOTARD 
<patrice.chot...@st.com>; Greg Kroah-Hartman <gre...@linuxfoundation.org>; Jiri 
Slaby <jsl...@suse.com>
Subject: Re: [PATCH RT] tty: serial: st-asc: Make the locking RT aware

On Wed, 22 Mar 2017 08:43:50 +
Lionel DEBIEVE <lionel.debi...@st.com> wrote:

> Just to agree with Thomas.
> 
> Do you want me to resend the patch without RT tag?
>

Yes please. And hopefully it will be picked up in mainline.

-- Steve

RE: [PATCH RT] tty: serial: st-asc: Make the locking RT aware

[Lionel DEBIEVE]

OK, resend without.
BR
Lionel

-Original Message-
From: Steven Rostedt [mailto:rost...@goodmis.org] 
Sent: mercredi 22 mars 2017 17:11
To: Lionel DEBIEVE 
Cc: Thomas Gleixner ; linux-rt-us...@vger.kernel.org; 
linux-kernel@vger.kernel.org; bige...@linutronix.de; Patrice CHOTARD 
; Greg Kroah-Hartman ; Jiri 
Slaby 
Subject: Re: [PATCH RT] tty: serial: st-asc: Make the locking RT aware

On Wed, 22 Mar 2017 08:43:50 +
Lionel DEBIEVE  wrote:

> Just to agree with Thomas.
> 
> Do you want me to resend the patch without RT tag?
>

Yes please. And hopefully it will be picked up in mainline.

-- Steve

[PATCH RT 1/1] remoteproc: Prevent schedule while atomic

[Lionel Debieve]

Use raw_spin_lock in enable/disable channel as it comes from
interrupt context.

BUG: sleeping function called from invalid context at
kernel/locking/rtmutex.c:995
in_atomic(): 1, irqs_disabled(): 128, pid: 307, name: pulseaudio
Preemption disabled at:
[] __handle_domain_irq+0x4c/0xec
CPU: 0 PID: 307 Comm: pulseaudio
Hardware name: STi SoC with Flattened Device Tree
[] (unwind_backtrace)
[] (show_stack)
[] (dump_stack)
[] (___might_sleep)
[] (rt_spin_lock)
[] (sti_mbox_disable_channel)
[] (sti_mbox_irq_handler)
[] (__handle_irq_event_percpu)
[] (handle_irq_event_percpu)
[] (handle_irq_event)
[] (handle_fasteoi_irq)
[] (generic_handle_irq)
[] (__handle_domain_irq)
[] (gic_handle_irq)

Signed-off-by: Lionel Debieve <lionel.debi...@st.com>
---
 drivers/mailbox/mailbox-sti.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/mailbox/mailbox-sti.c b/drivers/mailbox/mailbox-sti.c
index 41bcd33..f9674ca 100644
--- a/drivers/mailbox/mailbox-sti.c
+++ b/drivers/mailbox/mailbox-sti.c
@@ -60,7 +60,7 @@ struct sti_mbox_device {
void __iomem*base;
const char  *name;
u32 enabled[STI_MBOX_INST_MAX];
-   spinlock_t  lock;
+   raw_spinlock_t  lock;
 };
 
 /**
@@ -129,10 +129,10 @@ static void sti_mbox_enable_channel(struct mbox_chan 
*chan)
unsigned long flags;
void __iomem *base = MBOX_BASE(mdev, instance);
 
-   spin_lock_irqsave(>lock, flags);
+   raw_spin_lock_irqsave(>lock, flags);
mdev->enabled[instance] |= BIT(channel);
writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET);
-   spin_unlock_irqrestore(>lock, flags);
+   raw_spin_unlock_irqrestore(>lock, flags);
 }
 
 static void sti_mbox_disable_channel(struct mbox_chan *chan)
@@ -144,10 +144,10 @@ static void sti_mbox_disable_channel(struct mbox_chan 
*chan)
unsigned long flags;
void __iomem *base = MBOX_BASE(mdev, instance);
 
-   spin_lock_irqsave(>lock, flags);
+   raw_spin_lock_irqsave(>lock, flags);
mdev->enabled[instance] &= ~BIT(channel);
writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET);
-   spin_unlock_irqrestore(>lock, flags);
+   raw_spin_unlock_irqrestore(>lock, flags);
 }
 
 static void sti_mbox_clear_irq(struct mbox_chan *chan)
@@ -450,7 +450,7 @@ static int sti_mbox_probe(struct platform_device *pdev)
mdev->dev   = >dev;
mdev->mbox  = mbox;
 
-   spin_lock_init(>lock);
+   raw_spin_lock_init(>lock);
 
/* STi Mailbox does not have a Tx-Done or Tx-Ready IRQ */
mbox->txdone_irq= false;
-- 
2.7.4

[PATCH RT 1/1] remoteproc: Prevent schedule while atomic

[Lionel Debieve]

Use raw_spin_lock in enable/disable channel as it comes from
interrupt context.

BUG: sleeping function called from invalid context at
kernel/locking/rtmutex.c:995
in_atomic(): 1, irqs_disabled(): 128, pid: 307, name: pulseaudio
Preemption disabled at:
[] __handle_domain_irq+0x4c/0xec
CPU: 0 PID: 307 Comm: pulseaudio
Hardware name: STi SoC with Flattened Device Tree
[] (unwind_backtrace)
[] (show_stack)
[] (dump_stack)
[] (___might_sleep)
[] (rt_spin_lock)
[] (sti_mbox_disable_channel)
[] (sti_mbox_irq_handler)
[] (__handle_irq_event_percpu)
[] (handle_irq_event_percpu)
[] (handle_irq_event)
[] (handle_fasteoi_irq)
[] (generic_handle_irq)
[] (__handle_domain_irq)
[] (gic_handle_irq)

Signed-off-by: Lionel Debieve 
---
 drivers/mailbox/mailbox-sti.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/mailbox/mailbox-sti.c b/drivers/mailbox/mailbox-sti.c
index 41bcd33..f9674ca 100644
--- a/drivers/mailbox/mailbox-sti.c
+++ b/drivers/mailbox/mailbox-sti.c
@@ -60,7 +60,7 @@ struct sti_mbox_device {
void __iomem*base;
const char  *name;
u32 enabled[STI_MBOX_INST_MAX];
-   spinlock_t  lock;
+   raw_spinlock_t  lock;
 };
 
 /**
@@ -129,10 +129,10 @@ static void sti_mbox_enable_channel(struct mbox_chan 
*chan)
unsigned long flags;
void __iomem *base = MBOX_BASE(mdev, instance);
 
-   spin_lock_irqsave(>lock, flags);
+   raw_spin_lock_irqsave(>lock, flags);
mdev->enabled[instance] |= BIT(channel);
writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET);
-   spin_unlock_irqrestore(>lock, flags);
+   raw_spin_unlock_irqrestore(>lock, flags);
 }
 
 static void sti_mbox_disable_channel(struct mbox_chan *chan)
@@ -144,10 +144,10 @@ static void sti_mbox_disable_channel(struct mbox_chan 
*chan)
unsigned long flags;
void __iomem *base = MBOX_BASE(mdev, instance);
 
-   spin_lock_irqsave(>lock, flags);
+   raw_spin_lock_irqsave(>lock, flags);
mdev->enabled[instance] &= ~BIT(channel);
writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET);
-   spin_unlock_irqrestore(>lock, flags);
+   raw_spin_unlock_irqrestore(>lock, flags);
 }
 
 static void sti_mbox_clear_irq(struct mbox_chan *chan)
@@ -450,7 +450,7 @@ static int sti_mbox_probe(struct platform_device *pdev)
mdev->dev   = >dev;
mdev->mbox  = mbox;
 
-   spin_lock_init(>lock);
+   raw_spin_lock_init(>lock);
 
/* STi Mailbox does not have a Tx-Done or Tx-Ready IRQ */
mbox->txdone_irq= false;
-- 
2.7.4

Re: [PATCH RT] tty: serial: st-asc: Make the locking RT aware

[Lionel DEBIEVE]

Just to agree with Thomas.

Do you want me to resend the patch without RT tag?

BR,
Lionel


On 03/21/2017 09:15 PM, Steven Rostedt wrote:
> On Tue, 21 Mar 2017 19:51:47 +0100 (CET)
> Thomas Gleixner  wrote:
>
>> On Tue, 21 Mar 2017, Steven Rostedt wrote:
/*
 * Disable interrupts so we don't get the IRQ line
 bouncing
>>> I'm nervous about the above comment, which in full is:
>>>
>>> /*
>>>  * Disable interrupts so we don't get the IRQ line bouncing
>>>  * up and down while interrupts are disabled.
>>>  */
>>>
>>> I'm not sure if disabling interrupts helps on an SMP system. This
>>> patch does change what happens when port->sysrq is set. But I'm not
>>> sure we care.
>> It disables interrupts at the device level which obviously helps
>> whether on SMP or not.
>>
> OK, so this has nothing to do with the local_irq_save() that is being
> removed, which would be fine then.
>
>
> -- Steve
>

Re: [PATCH RT] tty: serial: st-asc: Make the locking RT aware

[Lionel DEBIEVE]

Just to agree with Thomas.

Do you want me to resend the patch without RT tag?

BR,
Lionel


On 03/21/2017 09:15 PM, Steven Rostedt wrote:
> On Tue, 21 Mar 2017 19:51:47 +0100 (CET)
> Thomas Gleixner  wrote:
>
>> On Tue, 21 Mar 2017, Steven Rostedt wrote:
/*
 * Disable interrupts so we don't get the IRQ line
 bouncing
>>> I'm nervous about the above comment, which in full is:
>>>
>>> /*
>>>  * Disable interrupts so we don't get the IRQ line bouncing
>>>  * up and down while interrupts are disabled.
>>>  */
>>>
>>> I'm not sure if disabling interrupts helps on an SMP system. This
>>> patch does change what happens when port->sysrq is set. But I'm not
>>> sure we care.
>> It disables interrupts at the device level which obviously helps
>> whether on SMP or not.
>>
> OK, so this has nothing to do with the local_irq_save() that is being
> removed, which would be fine then.
>
>
> -- Steve
>