Re: [PATCH 1/5] iio:adc:at91_adc8xx: introduce new atmel adc driver

[Ludovic Desroches]

On Tue, Dec 22, 2015 at 06:34:00PM +, Jonathan Cameron wrote:
> On 21/12/15 09:24, Ludovic Desroches wrote:
> > This driver supports the new version of the Atmel ADC device introduced
> > with the SAMA5D2 SoC family.
> > 
> > Signed-off-by: Ludovic Desroches 
> A few more bits and bobs from me. Mostly looking good.
> 
> Jonathan
> > ---
> >  .../devicetree/bindings/iio/adc/at91_adc8xx.txt|  27 ++
> >  drivers/iio/adc/Kconfig|  11 +
> >  drivers/iio/adc/Makefile   |   1 +
> >  drivers/iio/adc/at91_adc8xx.c  | 417 
> > +
> >  4 files changed, 456 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
> >  create mode 100644 drivers/iio/adc/at91_adc8xx.c
> > 
> > diff --git a/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt 
> > b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
> > new file mode 100644
> > index 000..64ad6a5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
> > @@ -0,0 +1,27 @@
> > +* AT91 SAMA5D2 Analog to Digital Converter (ADC)
> > +
> > +Required properties:
> > +  - compatible: Should be "atmel,sama5d2-adc".
> > +  - reg: Should contain ADC registers location and length.
> > +  - interrupts: Should contain the IRQ line for the ADC.
> > +  - clocks: phandles to clocks.
> > +  - clock-names: tuple listing clock names.
> > +  Required elements: "adc_clk", "adc_op_clk". "adc_clk" is the 
> > peripheral
> > +  clock, "adc_clk" is the sampling clock.
> > +  - vref-supply: Supply used as reference for conversions.
> > +
> > +Optional properties:
> > +  - vddana-supply: Supply for the adc device.
> > +
> > +
> > +Example:
> > +
> > +adc: adc@fc03 {
> > +   compatible = "atmel,sama5d2-adc";
> > +   reg = <0xfc03 0x100>;
> > +   interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
> > +   clocks = <_clk>, <_op_clk>;
> > +   clock-names = "adc_clk", "adc_op_clk";
> > +   vddana-supply = <_3v3_lp_reg>;
> > +   vref-supply = <_3v3_lp_reg>;
> > +}
> > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> > index 9162dfe..5819e41 100644
> > --- a/drivers/iio/adc/Kconfig
> > +++ b/drivers/iio/adc/Kconfig
> > @@ -131,6 +131,17 @@ config AT91_ADC
> >   To compile this driver as a module, choose M here: the module will be
> >   called at91_adc.
> >  
> > +config AT91_ADC8xx
> > +   tristate "Atmel AT91 ADC 8xx"
> > +   depends on ARCH_AT91
> > +   depends on INPUT
> > +   help
> > + Say yes here to build support for Atmel ADC 8xx which is available
> > + from SAMA5D2 SoC family.
> > +
> > + To compile this driver as a module, choose M here: the module will be
> > + called at91_adc8xx.
> > +
> >  config AXP288_ADC
> > tristate "X-Powers AXP288 ADC driver"
> > depends on MFD_AXP20X
> > diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> > index 91a65bf..d684a52 100644
> > --- a/drivers/iio/adc/Makefile
> > +++ b/drivers/iio/adc/Makefile
> > @@ -14,6 +14,7 @@ obj-$(CONFIG_AD7793) += ad7793.o
> >  obj-$(CONFIG_AD7887) += ad7887.o
> >  obj-$(CONFIG_AD799X) += ad799x.o
> >  obj-$(CONFIG_AT91_ADC) += at91_adc.o
> > +obj-$(CONFIG_AT91_ADC8xx) += at91_adc8xx.o
> >  obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
> >  obj-$(CONFIG_BERLIN2_ADC) += berlin2-adc.o
> >  obj-$(CONFIG_CC10001_ADC) += cc10001_adc.o
> > diff --git a/drivers/iio/adc/at91_adc8xx.c b/drivers/iio/adc/at91_adc8xx.c
> > new file mode 100644
> > index 000..8b4a6e7
> > --- /dev/null
> > +++ b/drivers/iio/adc/at91_adc8xx.c
> > @@ -0,0 +1,417 @@
> > +/*
> > + * Atmel ADC driver for SAMA5D2 devices and later.
> > + *
> > + * Copyright (C) 2015 Atmel,
> > + *   2015 Ludovic Desroches 
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

Re: [PATCH 1/5] iio:adc:at91_adc8xx: introduce new atmel adc driver

[Ludovic Desroches]

On Tue, Dec 22, 2015 at 06:34:00PM +, Jonathan Cameron wrote:
> On 21/12/15 09:24, Ludovic Desroches wrote:
> > This driver supports the new version of the Atmel ADC device introduced
> > with the SAMA5D2 SoC family.
> > 
> > Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
> A few more bits and bobs from me. Mostly looking good.
> 
> Jonathan
> > ---
> >  .../devicetree/bindings/iio/adc/at91_adc8xx.txt|  27 ++
> >  drivers/iio/adc/Kconfig|  11 +
> >  drivers/iio/adc/Makefile   |   1 +
> >  drivers/iio/adc/at91_adc8xx.c  | 417 
> > +
> >  4 files changed, 456 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
> >  create mode 100644 drivers/iio/adc/at91_adc8xx.c
> > 
> > diff --git a/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt 
> > b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
> > new file mode 100644
> > index 000..64ad6a5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
> > @@ -0,0 +1,27 @@
> > +* AT91 SAMA5D2 Analog to Digital Converter (ADC)
> > +
> > +Required properties:
> > +  - compatible: Should be "atmel,sama5d2-adc".
> > +  - reg: Should contain ADC registers location and length.
> > +  - interrupts: Should contain the IRQ line for the ADC.
> > +  - clocks: phandles to clocks.
> > +  - clock-names: tuple listing clock names.
> > +  Required elements: "adc_clk", "adc_op_clk". "adc_clk" is the 
> > peripheral
> > +  clock, "adc_clk" is the sampling clock.
> > +  - vref-supply: Supply used as reference for conversions.
> > +
> > +Optional properties:
> > +  - vddana-supply: Supply for the adc device.
> > +
> > +
> > +Example:
> > +
> > +adc: adc@fc03 {
> > +   compatible = "atmel,sama5d2-adc";
> > +   reg = <0xfc03 0x100>;
> > +   interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
> > +   clocks = <_clk>, <_op_clk>;
> > +   clock-names = "adc_clk", "adc_op_clk";
> > +   vddana-supply = <_3v3_lp_reg>;
> > +   vref-supply = <_3v3_lp_reg>;
> > +}
> > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> > index 9162dfe..5819e41 100644
> > --- a/drivers/iio/adc/Kconfig
> > +++ b/drivers/iio/adc/Kconfig
> > @@ -131,6 +131,17 @@ config AT91_ADC
> >   To compile this driver as a module, choose M here: the module will be
> >   called at91_adc.
> >  
> > +config AT91_ADC8xx
> > +   tristate "Atmel AT91 ADC 8xx"
> > +   depends on ARCH_AT91
> > +   depends on INPUT
> > +   help
> > + Say yes here to build support for Atmel ADC 8xx which is available
> > + from SAMA5D2 SoC family.
> > +
> > + To compile this driver as a module, choose M here: the module will be
> > + called at91_adc8xx.
> > +
> >  config AXP288_ADC
> > tristate "X-Powers AXP288 ADC driver"
> > depends on MFD_AXP20X
> > diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> > index 91a65bf..d684a52 100644
> > --- a/drivers/iio/adc/Makefile
> > +++ b/drivers/iio/adc/Makefile
> > @@ -14,6 +14,7 @@ obj-$(CONFIG_AD7793) += ad7793.o
> >  obj-$(CONFIG_AD7887) += ad7887.o
> >  obj-$(CONFIG_AD799X) += ad799x.o
> >  obj-$(CONFIG_AT91_ADC) += at91_adc.o
> > +obj-$(CONFIG_AT91_ADC8xx) += at91_adc8xx.o
> >  obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
> >  obj-$(CONFIG_BERLIN2_ADC) += berlin2-adc.o
> >  obj-$(CONFIG_CC10001_ADC) += cc10001_adc.o
> > diff --git a/drivers/iio/adc/at91_adc8xx.c b/drivers/iio/adc/at91_adc8xx.c
> > new file mode 100644
> > index 000..8b4a6e7
> > --- /dev/null
> > +++ b/drivers/iio/adc/at91_adc8xx.c
> > @@ -0,0 +1,417 @@
> > +/*
> > + * Atmel ADC driver for SAMA5D2 devices and later.
> > + *
> > + * Copyright (C) 2015 Atmel,
> > + *   2015 Ludovic Desroches <ludovic.desroc...@atmel.com>
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >

Re: [PATCH 1/5] iio:adc:at91_adc8xx: introduce new atmel adc driver

[Ludovic Desroches]

On Tue, Dec 22, 2015 at 06:51:18PM -0600, Rob Herring wrote:
> On Mon, Dec 21, 2015 at 10:24:08AM +0100, Ludovic Desroches wrote:
> > This driver supports the new version of the Atmel ADC device introduced
> > with the SAMA5D2 SoC family.
> > 
> > Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
> > ---
> >  .../devicetree/bindings/iio/adc/at91_adc8xx.txt|  27 ++
> >  drivers/iio/adc/Kconfig|  11 +
> >  drivers/iio/adc/Makefile   |   1 +
> >  drivers/iio/adc/at91_adc8xx.c  | 417 
> > +
> >  4 files changed, 456 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
> >  create mode 100644 drivers/iio/adc/at91_adc8xx.c
> > 
> > diff --git a/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt 
> > b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
> > new file mode 100644
> > index 000..64ad6a5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
> > @@ -0,0 +1,27 @@
> > +* AT91 SAMA5D2 Analog to Digital Converter (ADC)
> > +
> > +Required properties:
> > +  - compatible: Should be "atmel,sama5d2-adc".
> > +  - reg: Should contain ADC registers location and length.
> > +  - interrupts: Should contain the IRQ line for the ADC.
> > +  - clocks: phandles to clocks.
> > +  - clock-names: tuple listing clock names.
> > +  Required elements: "adc_clk", "adc_op_clk". "adc_clk" is the 
> > peripheral
> > +  clock, "adc_clk" is the sampling clock.
> > +  - vref-supply: Supply used as reference for conversions.
> > +
> > +Optional properties:
> > +  - vddana-supply: Supply for the adc device.
> 
> What makes a supply optional? If chip dependent, then then you need a 
> more specific compatible string.
> 

I thought I had read that we can supply an external vddana or having a
default one. Double checking the datasheet. I can't find it, I probably
read it on a draft version. Will move the vddana supply to required
properties.

Thanks

Ludovic
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Re: [PATCH 1/5] iio:adc:at91_adc8xx: introduce new atmel adc driver

[Ludovic Desroches]

On Wed, Dec 23, 2015 at 11:27:00AM +0100, Ludovic Desroches wrote:
> On Tue, Dec 22, 2015 at 06:34:00PM +, Jonathan Cameron wrote:
> > On 21/12/15 09:24, Ludovic Desroches wrote:
> > > This driver supports the new version of the Atmel ADC device introduced
> > > with the SAMA5D2 SoC family.
> > > 

[...]

> > > +static irqreturn_t at91_adc_interrupt(int irq, void *private)
> > > +{
> > > + struct iio_dev *indio = private;
> > > + struct at91_adc_state *st = iio_priv(indio);
> > > + u32 status = at91_adc_readl(st, ADC_ISR);
> > > +
> > > + status &= at91_adc_readl(st, ADC_IMR);
> > > + if (status & 0xFFF) {
> > > + st->last_value = at91_adc_readl(st, st->chan->address);
> > If this is a polled read - is there any reason to read this value here
> > rather than outside the interrupt?
> 
> No it can be done outside the interrupt. I have taken some parts from the
> previous driver but it was reading a register used by all the channels
> when it has been designed. So yes there is probably no more reason to
> read it into the interrupt.
> 

Thinking about it. Is it really useful to move reading outside the
interrupt?

By the way this is not a polled read.

> > > + st->done = true;
> > > + wake_up_interruptible(>wq_data_available);
> > > + }
> > > +
> > > + return IRQ_HANDLED;
> > > +}

Ludovic
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[PATCH 5/5] ARM: at91/defconfig: add sama5d2 adc support in sama5_defconfig

[Ludovic Desroches]

Signed-off-by: Ludovic Desroches 
---
 arch/arm/configs/sama5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index c11bab7..afbda41 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -187,6 +187,7 @@ CONFIG_AT_XDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
+CONFIG_AT91_SAMA5D2_ADC=y
 CONFIG_PWM=y
 CONFIG_PWM_ATMEL=y
 CONFIG_PWM_ATMEL_TCB=y
-- 
2.5.0

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[PATCH 3/5] ARM: at91/dt: sama5d2: add adc device

[Ludovic Desroches]

Add the ADC device.

Signed-off-by: Ludovic Desroches 
---
 arch/arm/boot/dts/sama5d2.dtsi | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 545264b..91c6e42 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -92,7 +92,7 @@
adc_op_clk: adc_op_clk{
compatible = "fixed-clock";
#clock-cells = <0>;
-   clock-frequency = <100>;
+   clock-frequency = <600>;
};
};
 
@@ -1061,6 +1061,15 @@
status = "disabled";
};
 
+   adc: adc@fc03 {
+   compatible = "atmel,sama5d2-adc";
+   reg = <0xfc03 0x100>;
+   interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
+   clocks = <_clk>, <_op_clk>;
+   clock-names = "adc_clk", "adc_op_clk";
+   status = "disabled";
+   };
+
pioA: pinctrl@fc038000 {
compatible = "atmel,sama5d2-pinctrl";
reg = <0xfc038000 0x600>;
-- 
2.5.0

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[PATCH 2/5] MAINTAINERS: add entry for Atmel ADC 8xx driver

[Ludovic Desroches]

Signed-off-by: Ludovic Desroches 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a27c660..5971c25 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1927,6 +1927,12 @@ M:   Nicolas Ferre 
 S: Supported
 F: drivers/tty/serial/atmel_serial.c
 
+ATMEL ADC 8xx DRIVER
+M: Ludovic Desroches 
+L: linux-...@vger.kernel.org
+S: Supported
+F: drivers/iio/adc/at91_adc8xx.c
+
 ATMEL Audio ALSA driver
 M: Nicolas Ferre 
 L: alsa-de...@alsa-project.org (moderated for non-subscribers)
-- 
2.5.0

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[PATCH 4/5] ARM: at91/dt: sama5d2 Xplained: enable the adc device

[Ludovic Desroches]

Enable the adc on the sama5d2 Xplained board.

Signed-off-by: Ludovic Desroches 
---
 arch/arm/boot/dts/at91-sama5d2_xplained.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index c2fcc29..6b263d4 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -251,7 +251,29 @@
};
};
 
+   adc: adc@fc03 {
+   vddana-supply = <_3v3_lp_reg>;
+   vref-supply = <_3v3_lp_reg>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_adc_default>;
+   status = "okay";
+   };
+
pinctrl@fc038000 {
+   /*
+* There is no real pinmux for ADC, if the pin
+* is not requested by another peripheral then
+* the muxing is done when channel is enabled.
+* Requesting pins for ADC is GPIO is
+* encouraged to prevent conflicts and to
+* disable bias in order to be in the same
+* state when the pin is not muxed to the adc.
+*/
+   pinctrl_adc_default: adc_default {
+   pinmux = ;
+   bias-disable;
+   };
+
pinctrl_flx0_default: flx0_default {
pinmux = ,
 ;
-- 
2.5.0

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[PATCH 1/5] iio:adc:at91_adc8xx: introduce new atmel adc driver

[Ludovic Desroches]

This driver supports the new version of the Atmel ADC device introduced
with the SAMA5D2 SoC family.

Signed-off-by: Ludovic Desroches 
---
 .../devicetree/bindings/iio/adc/at91_adc8xx.txt|  27 ++
 drivers/iio/adc/Kconfig|  11 +
 drivers/iio/adc/Makefile   |   1 +
 drivers/iio/adc/at91_adc8xx.c  | 417 +
 4 files changed, 456 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
 create mode 100644 drivers/iio/adc/at91_adc8xx.c

diff --git a/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt 
b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
new file mode 100644
index 000..64ad6a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
@@ -0,0 +1,27 @@
+* AT91 SAMA5D2 Analog to Digital Converter (ADC)
+
+Required properties:
+  - compatible: Should be "atmel,sama5d2-adc".
+  - reg: Should contain ADC registers location and length.
+  - interrupts: Should contain the IRQ line for the ADC.
+  - clocks: phandles to clocks.
+  - clock-names: tuple listing clock names.
+  Required elements: "adc_clk", "adc_op_clk". "adc_clk" is the peripheral
+  clock, "adc_clk" is the sampling clock.
+  - vref-supply: Supply used as reference for conversions.
+
+Optional properties:
+  - vddana-supply: Supply for the adc device.
+
+
+Example:
+
+adc: adc@fc03 {
+   compatible = "atmel,sama5d2-adc";
+   reg = <0xfc03 0x100>;
+   interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
+   clocks = <_clk>, <_op_clk>;
+   clock-names = "adc_clk", "adc_op_clk";
+   vddana-supply = <_3v3_lp_reg>;
+   vref-supply = <_3v3_lp_reg>;
+}
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9162dfe..5819e41 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -131,6 +131,17 @@ config AT91_ADC
  To compile this driver as a module, choose M here: the module will be
  called at91_adc.
 
+config AT91_ADC8xx
+   tristate "Atmel AT91 ADC 8xx"
+   depends on ARCH_AT91
+   depends on INPUT
+   help
+ Say yes here to build support for Atmel ADC 8xx which is available
+ from SAMA5D2 SoC family.
+
+ To compile this driver as a module, choose M here: the module will be
+ called at91_adc8xx.
+
 config AXP288_ADC
tristate "X-Powers AXP288 ADC driver"
depends on MFD_AXP20X
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 91a65bf..d684a52 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_AD7793) += ad7793.o
 obj-$(CONFIG_AD7887) += ad7887.o
 obj-$(CONFIG_AD799X) += ad799x.o
 obj-$(CONFIG_AT91_ADC) += at91_adc.o
+obj-$(CONFIG_AT91_ADC8xx) += at91_adc8xx.o
 obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
 obj-$(CONFIG_BERLIN2_ADC) += berlin2-adc.o
 obj-$(CONFIG_CC10001_ADC) += cc10001_adc.o
diff --git a/drivers/iio/adc/at91_adc8xx.c b/drivers/iio/adc/at91_adc8xx.c
new file mode 100644
index 000..8b4a6e7
--- /dev/null
+++ b/drivers/iio/adc/at91_adc8xx.c
@@ -0,0 +1,417 @@
+/*
+ * Atmel ADC driver for SAMA5D2 devices and later.
+ *
+ * Copyright (C) 2015 Atmel,
+ *   2015 Ludovic Desroches 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ADC_CR 0x00/* Control Register */
+#defineADC_CR_SWRSTBIT(0)  /* Software 
Reset */
+#defineADC_CR_STARTBIT(1)  /* Start 
Conversion */
+#defineADC_CR_TSCALIB  BIT(2)  /* Touchscreen 
Calibration */
+#defineADC_CR_CMPRST   BIT(4)  /* Comparison 
Restart */
+#define ADC_MR 0x04/* Mode Register */
+#defineADC_MR_TRGSEL(v)(v << 1)/* Trigger 
Selection */
+#defineADC_MR_TRGSEL_TRIG0 0   /* 
ADTRG */
+#defineADC_MR_TRGSEL_TRIG1 1   /* 
TIOA0 */
+#defineADC_MR_TRGSEL_TRIG2 2   /* 
TIOA1 */
+#defineADC_MR_TRGSEL_TRIG3 3   /* 
TIOA2 */
+#defineADC_MR_TRGSE

[PATCH 0/5] Introduce at91_adc8xx driver

[Ludovic Desroches]

Hi,

This is the very basic support for the adc introduced with the SAMA5D2 SoC
family.

The goal is to provide something to the user as soon as possible instead of
waiting for a full featured driver.

Only unsigned conversions on a software tigger are supported. Next steps are
signed conversions, differential channels, hardware triggers, dma support,
touchscreen support, and others.

Ludovic Desroches (5):
  iio:adc:at91_adc8xx: introduce new atmel adc driver
  MAINTAINERS: add entry for Atmel ADC 8xx driver
  ARM: at91/dt: sama5d2: add adc device
  ARM: at91/dt: sama5d2 Xplained: enable the adc device
  ARM: at91/defconfig: add sama5d2 adc support in sama5_defconfig

 .../devicetree/bindings/iio/adc/at91_adc8xx.txt|  27 ++
 MAINTAINERS|   6 +
 arch/arm/boot/dts/at91-sama5d2_xplained.dts|  22 ++
 arch/arm/boot/dts/sama5d2.dtsi |  11 +-
 arch/arm/configs/sama5_defconfig   |   1 +
 drivers/iio/adc/Kconfig|  11 +
 drivers/iio/adc/Makefile   |   1 +
 drivers/iio/adc/at91_adc8xx.c  | 417 +
 8 files changed, 495 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
 create mode 100644 drivers/iio/adc/at91_adc8xx.c

-- 
2.5.0

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[PATCH 5/5] ARM: at91/defconfig: add sama5d2 adc support in sama5_defconfig

[Ludovic Desroches]

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 arch/arm/configs/sama5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index c11bab7..afbda41 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -187,6 +187,7 @@ CONFIG_AT_XDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
+CONFIG_AT91_SAMA5D2_ADC=y
 CONFIG_PWM=y
 CONFIG_PWM_ATMEL=y
 CONFIG_PWM_ATMEL_TCB=y
-- 
2.5.0

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[PATCH 3/5] ARM: at91/dt: sama5d2: add adc device

[Ludovic Desroches]

Add the ADC device.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 arch/arm/boot/dts/sama5d2.dtsi | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 545264b..91c6e42 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -92,7 +92,7 @@
adc_op_clk: adc_op_clk{
compatible = "fixed-clock";
#clock-cells = <0>;
-   clock-frequency = <100>;
+   clock-frequency = <600>;
};
};
 
@@ -1061,6 +1061,15 @@
status = "disabled";
};
 
+   adc: adc@fc03 {
+   compatible = "atmel,sama5d2-adc";
+   reg = <0xfc03 0x100>;
+   interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
+   clocks = <_clk>, <_op_clk>;
+   clock-names = "adc_clk", "adc_op_clk";
+   status = "disabled";
+   };
+
pioA: pinctrl@fc038000 {
compatible = "atmel,sama5d2-pinctrl";
reg = <0xfc038000 0x600>;
-- 
2.5.0

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[PATCH 0/5] Introduce at91_adc8xx driver

[Ludovic Desroches]

Hi,

This is the very basic support for the adc introduced with the SAMA5D2 SoC
family.

The goal is to provide something to the user as soon as possible instead of
waiting for a full featured driver.

Only unsigned conversions on a software tigger are supported. Next steps are
signed conversions, differential channels, hardware triggers, dma support,
touchscreen support, and others.

Ludovic Desroches (5):
  iio:adc:at91_adc8xx: introduce new atmel adc driver
  MAINTAINERS: add entry for Atmel ADC 8xx driver
  ARM: at91/dt: sama5d2: add adc device
  ARM: at91/dt: sama5d2 Xplained: enable the adc device
  ARM: at91/defconfig: add sama5d2 adc support in sama5_defconfig

 .../devicetree/bindings/iio/adc/at91_adc8xx.txt|  27 ++
 MAINTAINERS|   6 +
 arch/arm/boot/dts/at91-sama5d2_xplained.dts|  22 ++
 arch/arm/boot/dts/sama5d2.dtsi |  11 +-
 arch/arm/configs/sama5_defconfig   |   1 +
 drivers/iio/adc/Kconfig|  11 +
 drivers/iio/adc/Makefile   |   1 +
 drivers/iio/adc/at91_adc8xx.c  | 417 +
 8 files changed, 495 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
 create mode 100644 drivers/iio/adc/at91_adc8xx.c

-- 
2.5.0

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[PATCH 4/5] ARM: at91/dt: sama5d2 Xplained: enable the adc device

[Ludovic Desroches]

Enable the adc on the sama5d2 Xplained board.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 arch/arm/boot/dts/at91-sama5d2_xplained.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index c2fcc29..6b263d4 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -251,7 +251,29 @@
};
};
 
+   adc: adc@fc03 {
+   vddana-supply = <_3v3_lp_reg>;
+   vref-supply = <_3v3_lp_reg>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_adc_default>;
+   status = "okay";
+   };
+
pinctrl@fc038000 {
+   /*
+* There is no real pinmux for ADC, if the pin
+* is not requested by another peripheral then
+* the muxing is done when channel is enabled.
+* Requesting pins for ADC is GPIO is
+* encouraged to prevent conflicts and to
+* disable bias in order to be in the same
+* state when the pin is not muxed to the adc.
+*/
+   pinctrl_adc_default: adc_default {
+   pinmux = ;
+   bias-disable;
+   };
+
pinctrl_flx0_default: flx0_default {
pinmux = ,
 ;
-- 
2.5.0

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[PATCH 1/5] iio:adc:at91_adc8xx: introduce new atmel adc driver

[Ludovic Desroches]

This driver supports the new version of the Atmel ADC device introduced
with the SAMA5D2 SoC family.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 .../devicetree/bindings/iio/adc/at91_adc8xx.txt|  27 ++
 drivers/iio/adc/Kconfig|  11 +
 drivers/iio/adc/Makefile   |   1 +
 drivers/iio/adc/at91_adc8xx.c  | 417 +
 4 files changed, 456 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
 create mode 100644 drivers/iio/adc/at91_adc8xx.c

diff --git a/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt 
b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
new file mode 100644
index 000..64ad6a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/at91_adc8xx.txt
@@ -0,0 +1,27 @@
+* AT91 SAMA5D2 Analog to Digital Converter (ADC)
+
+Required properties:
+  - compatible: Should be "atmel,sama5d2-adc".
+  - reg: Should contain ADC registers location and length.
+  - interrupts: Should contain the IRQ line for the ADC.
+  - clocks: phandles to clocks.
+  - clock-names: tuple listing clock names.
+  Required elements: "adc_clk", "adc_op_clk". "adc_clk" is the peripheral
+  clock, "adc_clk" is the sampling clock.
+  - vref-supply: Supply used as reference for conversions.
+
+Optional properties:
+  - vddana-supply: Supply for the adc device.
+
+
+Example:
+
+adc: adc@fc03 {
+   compatible = "atmel,sama5d2-adc";
+   reg = <0xfc03 0x100>;
+   interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
+   clocks = <_clk>, <_op_clk>;
+   clock-names = "adc_clk", "adc_op_clk";
+   vddana-supply = <_3v3_lp_reg>;
+   vref-supply = <_3v3_lp_reg>;
+}
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9162dfe..5819e41 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -131,6 +131,17 @@ config AT91_ADC
  To compile this driver as a module, choose M here: the module will be
  called at91_adc.
 
+config AT91_ADC8xx
+   tristate "Atmel AT91 ADC 8xx"
+   depends on ARCH_AT91
+   depends on INPUT
+   help
+ Say yes here to build support for Atmel ADC 8xx which is available
+ from SAMA5D2 SoC family.
+
+ To compile this driver as a module, choose M here: the module will be
+ called at91_adc8xx.
+
 config AXP288_ADC
tristate "X-Powers AXP288 ADC driver"
depends on MFD_AXP20X
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 91a65bf..d684a52 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_AD7793) += ad7793.o
 obj-$(CONFIG_AD7887) += ad7887.o
 obj-$(CONFIG_AD799X) += ad799x.o
 obj-$(CONFIG_AT91_ADC) += at91_adc.o
+obj-$(CONFIG_AT91_ADC8xx) += at91_adc8xx.o
 obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
 obj-$(CONFIG_BERLIN2_ADC) += berlin2-adc.o
 obj-$(CONFIG_CC10001_ADC) += cc10001_adc.o
diff --git a/drivers/iio/adc/at91_adc8xx.c b/drivers/iio/adc/at91_adc8xx.c
new file mode 100644
index 000..8b4a6e7
--- /dev/null
+++ b/drivers/iio/adc/at91_adc8xx.c
@@ -0,0 +1,417 @@
+/*
+ * Atmel ADC driver for SAMA5D2 devices and later.
+ *
+ * Copyright (C) 2015 Atmel,
+ *   2015 Ludovic Desroches <ludovic.desroc...@atmel.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ADC_CR 0x00/* Control Register */
+#defineADC_CR_SWRSTBIT(0)  /* Software 
Reset */
+#defineADC_CR_STARTBIT(1)  /* Start 
Conversion */
+#defineADC_CR_TSCALIB  BIT(2)  /* Touchscreen 
Calibration */
+#defineADC_CR_CMPRST   BIT(4)  /* Comparison 
Restart */
+#define ADC_MR 0x04/* Mode Register */
+#defineADC_MR_TRGSEL(v)(v << 1)/* Trigger 
Selection */
+#defineADC_MR_TRGSEL_TRIG0 0   /* 
ADTRG */
+#defineADC_MR_TRGSEL_TRIG1 1   /* 
TIOA0 */
+#defineADC_MR_TRGSEL_TRIG2 2   /* 
TIOA1 */
+#defineADC

[PATCH 2/5] MAINTAINERS: add entry for Atmel ADC 8xx driver

[Ludovic Desroches]

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a27c660..5971c25 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1927,6 +1927,12 @@ M:   Nicolas Ferre <nicolas.fe...@atmel.com>
 S: Supported
 F: drivers/tty/serial/atmel_serial.c
 
+ATMEL ADC 8xx DRIVER
+M: Ludovic Desroches <ludovic.desroc...@atmel.com>
+L: linux-...@vger.kernel.org
+S: Supported
+F: drivers/iio/adc/at91_adc8xx.c
+
 ATMEL Audio ALSA driver
 M: Nicolas Ferre <nicolas.fe...@atmel.com>
 L: alsa-de...@alsa-project.org (moderated for non-subscribers)
-- 
2.5.0

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Re: [PATCH v2] mmc: sdhci: restore behavior when setting VDD via external regulator

[Ludovic Desroches]

Hi Ulf, Jisheng,

On Fri, Dec 11, 2015 at 03:48:04PM +0100, Ulf Hansson wrote:
> + Ludovic (We had some discussions around this code recently as well)
> 
> On 11 December 2015 at 14:36, Jisheng Zhang  wrote:
> > After commit 52221610dd84 ("mmc: sdhci: Improve external VDD regulator
> > support"), for the VDD is supplied via external regulators, we ignore
> > the code to convert a VDD voltage request into one of the standard
> > SDHCI voltage levels, then program it in the SDHCI_POWER_CONTROL. This
> > brings two issues:
> >
> > 1. SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON quirk isn't handled properly any
> > more.
> >
> > 2. What's more, once SDHCI_POWER_ON bit is set, some controllers such
> > as the sdhci-pxav3 used in marvell berlin SoCs require the voltage
> > levels programming in the SDHCI_POWER_CONTROL register, even the VDD
> > is supplied by external regulator. So the host in marvell berlin SoCs
> > still works fine after the commit. However, commit 3cbc6123a93d ("mmc:
> > sdhci: Set SDHCI_POWER_ON with external vmmc") sets the SDHCI_POWER_ON
> > bit, this would make the host in marvell berlin SoCs won't work any
> > more with external vmmc.
> >
> > This patch restores the behavior when setting VDD through external
> > regulator by moving the call of mmc_regulator_set_ocr() to the end
> > of sdhci_set_power() function.
> >
> > After this patch, the sdcard on Marvell Berlin SoC boards work again.
> >
> > Signed-off-by: Jisheng Zhang 
> > Fixes: 52221610dd84 ("mmc: sdhci: Improve external VDD ...")

Reviewed-by: Ludovic Desroches 
Tested-by: Ludovic Desroches 

Even if the patch sounds good for me, I wanted to test it. As planned,
with this patch, I can describe my vcc regulator without breaking the
behavior of my sdhci controller.


Regards

Ludovic

> > ---
> > Since v1:
> >  - add more details about why the sdhci-pxav3 used in marvell berlin
> >SoCs need this patch.
> >
> >  drivers/mmc/host/sdhci.c | 19 ++-
> >  1 file changed, 6 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index b48565e..616aa90 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -1274,19 +1274,6 @@ static void sdhci_set_power(struct sdhci_host *host, 
> > unsigned char mode,
> > struct mmc_host *mmc = host->mmc;
> > u8 pwr = 0;
> >
> > -   if (!IS_ERR(mmc->supply.vmmc)) {
> > -   spin_unlock_irq(>lock);
> > -   mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
> > -   spin_lock_irq(>lock);
> > -
> > -   if (mode != MMC_POWER_OFF)
> > -   sdhci_writeb(host, SDHCI_POWER_ON, 
> > SDHCI_POWER_CONTROL);
> > -   else
> > -   sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
> > -
> > -   return;
> > -   }
> > -
> > if (mode != MMC_POWER_OFF) {
> > switch (1 << vdd) {
> > case MMC_VDD_165_195:
> > @@ -1345,6 +1332,12 @@ static void sdhci_set_power(struct sdhci_host *host, 
> > unsigned char mode,
> > if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
> > mdelay(10);
> > }
> > +
> > +   if (!IS_ERR(mmc->supply.vmmc)) {
> > +   spin_unlock_irq(>lock);
> > +   mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
> > +   spin_lock_irq(>lock);
> > +   }
> >  }
> >
> >  
> > /*\
> > --
> > 2.6.3
> >
> 
> My concern with this patch is that it might fix the problem for your
> SDHCI variant, but will break it for others.
> I guess we can give it try, unless or until someone reports a problem.
> 
> Although, I would like to get Ludovic's input on this change, before I
> decide to do anything.
> 
> Kind regards
> Uffe
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Re: [PATCH v2] mmc: sdhci: restore behavior when setting VDD via external regulator

[Ludovic Desroches]

Hi Ulf, Jisheng,

On Fri, Dec 11, 2015 at 03:48:04PM +0100, Ulf Hansson wrote:
> + Ludovic (We had some discussions around this code recently as well)
> 
> On 11 December 2015 at 14:36, Jisheng Zhang <jszh...@marvell.com> wrote:
> > After commit 52221610dd84 ("mmc: sdhci: Improve external VDD regulator
> > support"), for the VDD is supplied via external regulators, we ignore
> > the code to convert a VDD voltage request into one of the standard
> > SDHCI voltage levels, then program it in the SDHCI_POWER_CONTROL. This
> > brings two issues:
> >
> > 1. SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON quirk isn't handled properly any
> > more.
> >
> > 2. What's more, once SDHCI_POWER_ON bit is set, some controllers such
> > as the sdhci-pxav3 used in marvell berlin SoCs require the voltage
> > levels programming in the SDHCI_POWER_CONTROL register, even the VDD
> > is supplied by external regulator. So the host in marvell berlin SoCs
> > still works fine after the commit. However, commit 3cbc6123a93d ("mmc:
> > sdhci: Set SDHCI_POWER_ON with external vmmc") sets the SDHCI_POWER_ON
> > bit, this would make the host in marvell berlin SoCs won't work any
> > more with external vmmc.
> >
> > This patch restores the behavior when setting VDD through external
> > regulator by moving the call of mmc_regulator_set_ocr() to the end
> > of sdhci_set_power() function.
> >
> > After this patch, the sdcard on Marvell Berlin SoC boards work again.
> >
> > Signed-off-by: Jisheng Zhang <jszh...@marvell.com>
> > Fixes: 52221610dd84 ("mmc: sdhci: Improve external VDD ...")

Reviewed-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
Tested-by: Ludovic Desroches <ludovic.desroc...@atmel.com>

Even if the patch sounds good for me, I wanted to test it. As planned,
with this patch, I can describe my vcc regulator without breaking the
behavior of my sdhci controller.


Regards

Ludovic

> > ---
> > Since v1:
> >  - add more details about why the sdhci-pxav3 used in marvell berlin
> >SoCs need this patch.
> >
> >  drivers/mmc/host/sdhci.c | 19 ++-
> >  1 file changed, 6 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index b48565e..616aa90 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -1274,19 +1274,6 @@ static void sdhci_set_power(struct sdhci_host *host, 
> > unsigned char mode,
> > struct mmc_host *mmc = host->mmc;
> > u8 pwr = 0;
> >
> > -   if (!IS_ERR(mmc->supply.vmmc)) {
> > -   spin_unlock_irq(>lock);
> > -   mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
> > -   spin_lock_irq(>lock);
> > -
> > -   if (mode != MMC_POWER_OFF)
> > -   sdhci_writeb(host, SDHCI_POWER_ON, 
> > SDHCI_POWER_CONTROL);
> > -   else
> > -   sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
> > -
> > -   return;
> > -   }
> > -
> > if (mode != MMC_POWER_OFF) {
> > switch (1 << vdd) {
> > case MMC_VDD_165_195:
> > @@ -1345,6 +1332,12 @@ static void sdhci_set_power(struct sdhci_host *host, 
> > unsigned char mode,
> > if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
> > mdelay(10);
> > }
> > +
> > +   if (!IS_ERR(mmc->supply.vmmc)) {
> > +   spin_unlock_irq(>lock);
> > +   mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
> > +   spin_lock_irq(>lock);
> > +   }
> >  }
> >
> >  
> > /*\
> > --
> > 2.6.3
> >
> 
> My concern with this patch is that it might fix the problem for your
> SDHCI variant, but will break it for others.
> I guess we can give it try, unless or until someone reports a problem.
> 
> Although, I would like to get Ludovic's input on this change, before I
> decide to do anything.
> 
> Kind regards
> Uffe
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Re: [PATCH v2] mmc: sdhci: restore behavior when setting VDD via external regulator

[Ludovic Desroches]

On Fri, Dec 11, 2015 at 03:48:04PM +0100, Ulf Hansson wrote:
> + Ludovic (We had some discussions around this code recently as well)
> 

Thanks Ulf.

> On 11 December 2015 at 14:36, Jisheng Zhang  wrote:
> > After commit 52221610dd84 ("mmc: sdhci: Improve external VDD regulator
> > support"), for the VDD is supplied via external regulators, we ignore
> > the code to convert a VDD voltage request into one of the standard
> > SDHCI voltage levels, then program it in the SDHCI_POWER_CONTROL. This
> > brings two issues:
> >
> > 1. SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON quirk isn't handled properly any
> > more.
> >
> > 2. What's more, once SDHCI_POWER_ON bit is set, some controllers such
> > as the sdhci-pxav3 used in marvell berlin SoCs require the voltage
> > levels programming in the SDHCI_POWER_CONTROL register, even the VDD
> > is supplied by external regulator.So the host in marvell berlin SoCs
> > still works fine after the commit.

I am not sure to understand this part. You explain that the controller
in berlin SoC requireis the voltage level programming even if there is an
external regulator for VDD. I agree this part, I am in the same
situation with atmel controller. It is not smart to rely on the voltage
level if we have an external regulator but it follows the sdhci specs.

That I don't understand is that you say it still works fine after this
commit... If you need to set the voltage level in the
SDHCI_POWER_CONTROL register, it is broken by this commit if you declare
an external regulator.

> > However, commit 3cbc6123a93d ("mmc:
> > sdhci: Set SDHCI_POWER_ON with external vmmc") sets the SDHCI_POWER_ON
> > bit, this would make the host in marvell berlin SoCs won't work any
> > more with external vmmc.
> >
> > This patch restores the behavior when setting VDD through external
> > regulator by moving the call of mmc_regulator_set_ocr() to the end
> > of sdhci_set_power() function.
> >
> > After this patch, the sdcard on Marvell Berlin SoC boards work again.
> >
> > Signed-off-by: Jisheng Zhang 
> > Fixes: 52221610dd84 ("mmc: sdhci: Improve external VDD ...")
> > ---
> > Since v1:
> >  - add more details about why the sdhci-pxav3 used in marvell berlin
> >SoCs need this patch.
> >
> >  drivers/mmc/host/sdhci.c | 19 ++-
> >  1 file changed, 6 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index b48565e..616aa90 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -1274,19 +1274,6 @@ static void sdhci_set_power(struct sdhci_host *host, 
> > unsigned char mode,
> > struct mmc_host *mmc = host->mmc;
> > u8 pwr = 0;
> >
> > -   if (!IS_ERR(mmc->supply.vmmc)) {
> > -   spin_unlock_irq(>lock);
> > -   mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
> > -   spin_lock_irq(>lock);
> > -
> > -   if (mode != MMC_POWER_OFF)
> > -   sdhci_writeb(host, SDHCI_POWER_ON, 
> > SDHCI_POWER_CONTROL);
> > -   else
> > -   sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
> > -
> > -   return;
> > -   }
> > -
> > if (mode != MMC_POWER_OFF) {
> > switch (1 << vdd) {
> > case MMC_VDD_165_195:
> > @@ -1345,6 +1332,12 @@ static void sdhci_set_power(struct sdhci_host *host, 
> > unsigned char mode,
> > if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
> > mdelay(10);
> > }
> > +
> > +   if (!IS_ERR(mmc->supply.vmmc)) {
> > +   spin_unlock_irq(>lock);
> > +   mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
> > +   spin_lock_irq(>lock);
> > +   }
> >  }
> >
> >  
> > /*\
> > --
> > 2.6.3
> >
> 
> My concern with this patch is that it might fix the problem for your
> SDHCI variant, but will break it for others.
> I guess we can give it try, unless or until someone reports a problem.
> 
> Although, I would like to get Ludovic's input on this change, before I
> decide to do anything.
>

I would be pleased to get this patch since it would solve one of my
issues.

Concerning the risk to take this patch. I would say one part of this
patch is safe, the other one maybe not.

Reading the log of commit 52221610dd84, it is not a bug fix. It was done
in this way because it seemed logical to not set the voltage level in
the SDHCI_POWER_CONTROL if we have an external regulator.

Moving mmc_regulator_set_ocr at the end could cause issue since it
changes the sequence order: the regulator is configured after the
SDHCI_POWER_CONTROL register.

Regards

Ludovic
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Re: [PATCH v2] mmc: sdhci: restore behavior when setting VDD via external regulator

[Ludovic Desroches]

On Fri, Dec 11, 2015 at 03:48:04PM +0100, Ulf Hansson wrote:
> + Ludovic (We had some discussions around this code recently as well)
> 

Thanks Ulf.

> On 11 December 2015 at 14:36, Jisheng Zhang  wrote:
> > After commit 52221610dd84 ("mmc: sdhci: Improve external VDD regulator
> > support"), for the VDD is supplied via external regulators, we ignore
> > the code to convert a VDD voltage request into one of the standard
> > SDHCI voltage levels, then program it in the SDHCI_POWER_CONTROL. This
> > brings two issues:
> >
> > 1. SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON quirk isn't handled properly any
> > more.
> >
> > 2. What's more, once SDHCI_POWER_ON bit is set, some controllers such
> > as the sdhci-pxav3 used in marvell berlin SoCs require the voltage
> > levels programming in the SDHCI_POWER_CONTROL register, even the VDD
> > is supplied by external regulator.So the host in marvell berlin SoCs
> > still works fine after the commit.

I am not sure to understand this part. You explain that the controller
in berlin SoC requireis the voltage level programming even if there is an
external regulator for VDD. I agree this part, I am in the same
situation with atmel controller. It is not smart to rely on the voltage
level if we have an external regulator but it follows the sdhci specs.

That I don't understand is that you say it still works fine after this
commit... If you need to set the voltage level in the
SDHCI_POWER_CONTROL register, it is broken by this commit if you declare
an external regulator.

> > However, commit 3cbc6123a93d ("mmc:
> > sdhci: Set SDHCI_POWER_ON with external vmmc") sets the SDHCI_POWER_ON
> > bit, this would make the host in marvell berlin SoCs won't work any
> > more with external vmmc.
> >
> > This patch restores the behavior when setting VDD through external
> > regulator by moving the call of mmc_regulator_set_ocr() to the end
> > of sdhci_set_power() function.
> >
> > After this patch, the sdcard on Marvell Berlin SoC boards work again.
> >
> > Signed-off-by: Jisheng Zhang 
> > Fixes: 52221610dd84 ("mmc: sdhci: Improve external VDD ...")
> > ---
> > Since v1:
> >  - add more details about why the sdhci-pxav3 used in marvell berlin
> >SoCs need this patch.
> >
> >  drivers/mmc/host/sdhci.c | 19 ++-
> >  1 file changed, 6 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index b48565e..616aa90 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -1274,19 +1274,6 @@ static void sdhci_set_power(struct sdhci_host *host, 
> > unsigned char mode,
> > struct mmc_host *mmc = host->mmc;
> > u8 pwr = 0;
> >
> > -   if (!IS_ERR(mmc->supply.vmmc)) {
> > -   spin_unlock_irq(>lock);
> > -   mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
> > -   spin_lock_irq(>lock);
> > -
> > -   if (mode != MMC_POWER_OFF)
> > -   sdhci_writeb(host, SDHCI_POWER_ON, 
> > SDHCI_POWER_CONTROL);
> > -   else
> > -   sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
> > -
> > -   return;
> > -   }
> > -
> > if (mode != MMC_POWER_OFF) {
> > switch (1 << vdd) {
> > case MMC_VDD_165_195:
> > @@ -1345,6 +1332,12 @@ static void sdhci_set_power(struct sdhci_host *host, 
> > unsigned char mode,
> > if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
> > mdelay(10);
> > }
> > +
> > +   if (!IS_ERR(mmc->supply.vmmc)) {
> > +   spin_unlock_irq(>lock);
> > +   mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
> > +   spin_lock_irq(>lock);
> > +   }
> >  }
> >
> >  
> > /*\
> > --
> > 2.6.3
> >
> 
> My concern with this patch is that it might fix the problem for your
> SDHCI variant, but will break it for others.
> I guess we can give it try, unless or until someone reports a problem.
> 
> Although, I would like to get Ludovic's input on this change, before I
> decide to do anything.
>

I would be pleased to get this patch since it would solve one of my
issues.

Concerning the risk to take this patch. I would say one part of this
patch is safe, the other one maybe not.

Reading the log of commit 52221610dd84, it is not a bug fix. It was done
in this way because it seemed logical to not set the voltage level in
the SDHCI_POWER_CONTROL if we have an external regulator.

Moving mmc_regulator_set_ocr at the end could cause issue since it
changes the sequence order: the regulator is configured after the
SDHCI_POWER_CONTROL register.

Regards

Ludovic
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Please 

Re: [RESEND RFC PATCH 0/2] Expose the PIO_ISR register on SAMA5D3

[Ludovic Desroches]

Hi Peter,

On Tue, Dec 08, 2015 at 04:20:06AM +0100, Peter Rosin wrote:
> From: Peter Rosin 
> 
> Hi!
> 
> I have a signal connected to a gpio pin which is the output of
> a comparator. By changing the level of one of the inputs to the
> comparator, I can detect the envelope of the other input to
> the comparator by using a series of measurements much in the
> same maner a manual ADC works, but watching for changes on the
> comparator over a period of time instead of only the immediate
> output.
> 
> Now, the input signal to the comparator might have a high frequency,
> which will cause the output from the comparator (and thus the GPIO
> input) to change rapidly.
> 
> A common(?) idiom for this is to use the interrupt status register
> to catch the glitches, but then not have any interrupt tied to
> the pin as that could possibly generate pointless bursts of
> (expensive) interrupts.
> 

Well I don't know if this use case as already been considered. I
understand you don't want to be overwhelmed by interrupts but why not
using the interrupt to start polling the PDSR (Pin Data Status
Register)?

I am really not confortable about exposing the ISR since there is a
clean on read. You have taken precautions by checking the IMR before but
if there is a single driver using a gpio as an irq, you will never get
the ISR.

Regards

Ludovic

> So, these two patches expose an interface to the PIO_ISR register
> of the pio controllers on the platform I'm targetting. The first
> patch adds some infrastructure to the gpio core and the second
> patch hooks up "my" pin controller.
> 
> But hey, this seems like an old problem and I was surprised that
> I had to touch the source to do it. Which makes me wonder what I'm
> missing and what others needing to see short pulses on a pin but not
> needing/wanting interrupts are doing?
> 
> Yes, there needs to be a way to select the interrupt edge w/o
> actually arming the interrupt, that is missing. And probably
> other things too, but I didn't want to do more work in case this
> is a dead end for some reason...
> 
> Cheers,
> Peter
> 
> Peter Rosin (2):
>   gpio: Add isr property of gpio pins
>   pinctrl: at91: expose the isr bit
> 
>  Documentation/gpio/sysfs.txt   |   12 ++
>  drivers/gpio/gpiolib-sysfs.c   |   30 
>  drivers/gpio/gpiolib.c |   15 
>  drivers/pinctrl/pinctrl-at91.c |   50 
> 
>  include/linux/gpio/consumer.h  |1 +
>  include/linux/gpio/driver.h|2 ++
>  6 files changed, 106 insertions(+), 4 deletions(-)
> 
> -- 
> 1.7.10.4
> 
> --
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> the body of a message to majord...@vger.kernel.org
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Re: [RESEND RFC PATCH 0/2] Expose the PIO_ISR register on SAMA5D3

[Ludovic Desroches]

Hi Peter,

On Tue, Dec 08, 2015 at 04:20:06AM +0100, Peter Rosin wrote:
> From: Peter Rosin 
> 
> Hi!
> 
> I have a signal connected to a gpio pin which is the output of
> a comparator. By changing the level of one of the inputs to the
> comparator, I can detect the envelope of the other input to
> the comparator by using a series of measurements much in the
> same maner a manual ADC works, but watching for changes on the
> comparator over a period of time instead of only the immediate
> output.
> 
> Now, the input signal to the comparator might have a high frequency,
> which will cause the output from the comparator (and thus the GPIO
> input) to change rapidly.
> 
> A common(?) idiom for this is to use the interrupt status register
> to catch the glitches, but then not have any interrupt tied to
> the pin as that could possibly generate pointless bursts of
> (expensive) interrupts.
> 

Well I don't know if this use case as already been considered. I
understand you don't want to be overwhelmed by interrupts but why not
using the interrupt to start polling the PDSR (Pin Data Status
Register)?

I am really not confortable about exposing the ISR since there is a
clean on read. You have taken precautions by checking the IMR before but
if there is a single driver using a gpio as an irq, you will never get
the ISR.

Regards

Ludovic

> So, these two patches expose an interface to the PIO_ISR register
> of the pio controllers on the platform I'm targetting. The first
> patch adds some infrastructure to the gpio core and the second
> patch hooks up "my" pin controller.
> 
> But hey, this seems like an old problem and I was surprised that
> I had to touch the source to do it. Which makes me wonder what I'm
> missing and what others needing to see short pulses on a pin but not
> needing/wanting interrupts are doing?
> 
> Yes, there needs to be a way to select the interrupt edge w/o
> actually arming the interrupt, that is missing. And probably
> other things too, but I didn't want to do more work in case this
> is a dead end for some reason...
> 
> Cheers,
> Peter
> 
> Peter Rosin (2):
>   gpio: Add isr property of gpio pins
>   pinctrl: at91: expose the isr bit
> 
>  Documentation/gpio/sysfs.txt   |   12 ++
>  drivers/gpio/gpiolib-sysfs.c   |   30 
>  drivers/gpio/gpiolib.c |   15 
>  drivers/pinctrl/pinctrl-at91.c |   50 
> 
>  include/linux/gpio/consumer.h  |1 +
>  include/linux/gpio/driver.h|2 ++
>  6 files changed, 106 insertions(+), 4 deletions(-)
> 
> -- 
> 1.7.10.4
> 
> --
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> the body of a message to majord...@vger.kernel.org
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Re: [PATCH 1/1] dmaengine: at_xdmac: fix at_xdmac_prep_dma_memcpy()

[Ludovic Desroches]

On Mon, Dec 07, 2015 at 03:58:56PM +0100, Cyrille Pitchen wrote:
> This patch fixes at_xdmac_prep_dma_memcpy(). Indeed the data width field
> of the Channel Configuration register was not updated properly in the
> loop: the bits of the dwidth field were not cleared before adding their
> new value.
> 
> Signed-off-by: Cyrille Pitchen 

Thanks.

Acked-by: Ludovic Desroches 
Fixes: e1f7c9eee70 ("dmaengine: at_xdmac: creation of the atmel eXtended
DMA Controller driver")
Cc: sta...@vger.kernel.org #4.1 and later (minor conflict due to the 
introduction of at_xdmac_align_width() in 4.2 to factorize code)

> ---
>  drivers/dma/at_xdmac.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
> index 90040e99f5f3..39f59666f93f 100644
> --- a/drivers/dma/at_xdmac.c
> +++ b/drivers/dma/at_xdmac.c
> @@ -1096,6 +1096,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, 
> dma_addr_t dest, dma_addr_t src,
>   /* Check remaining length and change data width if needed. */
>   dwidth = at_xdmac_align_width(chan,
> src_addr | dst_addr | xfer_size);
> + chan_cc &= ~AT_XDMAC_CC_DWIDTH_MASK;
>   chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
>  
>   ublen = xfer_size >> dwidth;
> -- 
> 1.8.2.2
> 
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Re: [PATCH 1/1] dmaengine: at_xdmac: fix at_xdmac_prep_dma_memcpy()

[Ludovic Desroches]

On Mon, Dec 07, 2015 at 03:58:56PM +0100, Cyrille Pitchen wrote:
> This patch fixes at_xdmac_prep_dma_memcpy(). Indeed the data width field
> of the Channel Configuration register was not updated properly in the
> loop: the bits of the dwidth field were not cleared before adding their
> new value.
> 
> Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>

Thanks.

Acked-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
Fixes: e1f7c9eee70 ("dmaengine: at_xdmac: creation of the atmel eXtended
DMA Controller driver")
Cc: sta...@vger.kernel.org #4.1 and later (minor conflict due to the 
introduction of at_xdmac_align_width() in 4.2 to factorize code)

> ---
>  drivers/dma/at_xdmac.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
> index 90040e99f5f3..39f59666f93f 100644
> --- a/drivers/dma/at_xdmac.c
> +++ b/drivers/dma/at_xdmac.c
> @@ -1096,6 +1096,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, 
> dma_addr_t dest, dma_addr_t src,
>   /* Check remaining length and change data width if needed. */
>   dwidth = at_xdmac_align_width(chan,
> src_addr | dst_addr | xfer_size);
> + chan_cc &= ~AT_XDMAC_CC_DWIDTH_MASK;
>   chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
>  
>   ublen = xfer_size >> dwidth;
> -- 
> 1.8.2.2
> 
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Re: [PATCH v2 1/4] i2c: at91: add upport for the HOLD field

[Ludovic Desroches]

Sorry forget this one, I have sent an old version.

On Thu, Dec 03, 2015 at 10:53:51AM +0100, Ludovic Desroches wrote:
> The hold field allows to configure the data hold time which can be set
> with the help of the generic binding 'i2c-sda-hold-time-ns'. This
> feature has been introduced with SAMA5D4 SoC family.
> 
> Signed-off-by: Ludovic Desroches 
> ---
>  drivers/i2c/busses/i2c-at91.c | 53 
> ---
>  1 file changed, 50 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
> index 10835d1..921d32b 100644
> --- a/drivers/i2c/busses/i2c-at91.c
> +++ b/drivers/i2c/busses/i2c-at91.c
> @@ -64,6 +64,8 @@
>  #define  AT91_TWI_IADR   0x000c  /* Internal Address Register */
>  
>  #define  AT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
> */
> +#define  AT91_TWI_CWGR_HOLD_MAX  0x1f
> +#define  AT91_TWI_CWGR_HOLD(x)   (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
>  
>  #define  AT91_TWI_SR 0x0020  /* Status Register */
>  #define  AT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
> @@ -110,6 +112,7 @@ struct at91_twi_pdata {
>   unsigned clk_offset;
>   bool has_unre_flag;
>   bool has_alt_cmd;
> + bool has_hold_field;
>   struct at_dma_slave dma_slave;
>  };
>  
> @@ -187,10 +190,11 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
>   */
>  static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
>  {
> - int ckdiv, cdiv, div;
> + int ckdiv, cdiv, div, hold = 0;
>   struct at91_twi_pdata *pdata = dev->pdata;
>   int offset = pdata->clk_offset;
>   int max_ckdiv = pdata->clk_max_div;
> + u32 twd_hold_time_ns = 0;
>  
>   div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
>  2 * twi_clk) - offset);
> @@ -204,8 +208,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev 
> *dev, int twi_clk)
>   cdiv = 255;
>   }
>  
> - dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
> - dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
> + if (pdata->has_hold_field) {
> + of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
> +  _hold_time_ns);
> +
> + /*
> +  * hold time = HOLD + 3 x T_peripheral_clock
> +  * Use clk rate in kHz to prevent overflows when computing
> +  * hold.
> +  */
> + hold = DIV_ROUND_UP(twd_hold_time_ns
> + * (clk_get_rate(dev->clk) / 1000), 100);
> + hold -= 3;
> + if (hold < 0)
> + hold = 0;
> + if (hold > AT91_TWI_CWGR_HOLD_MAX) {
> + dev_warn(dev->dev,
> +  "HOLD field set to its maximum value (%d 
> instead of %d)\n",
> +  AT91_TWI_CWGR_HOLD_MAX, hold);
> + hold = AT91_TWI_CWGR_HOLD_MAX;
> + }
> + }
> +
> + dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
> + | AT91_TWI_CWGR_HOLD(hold);
> +
> + dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
> + cdiv, ckdiv, hold, twd_hold_time_ns);
>  }
>  
>  static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
> @@ -797,6 +826,7 @@ static struct at91_twi_pdata at91rm9200_config = {
>   .clk_offset = 3,
>   .has_unre_flag = true,
>   .has_alt_cmd = false,
> + .has_hold_field = false,
>  };
>  
>  static struct at91_twi_pdata at91sam9261_config = {
> @@ -804,6 +834,7 @@ static struct at91_twi_pdata at91sam9261_config = {
>   .clk_offset = 4,
>   .has_unre_flag = false,
>   .has_alt_cmd = false,
> + .has_hold_field = false,
>  };
>  
>  static struct at91_twi_pdata at91sam9260_config = {
> @@ -811,6 +842,7 @@ static struct at91_twi_pdata at91sam9260_config = {
>   .clk_offset = 4,
>   .has_unre_flag = false,
>   .has_alt_cmd = false,
> + .has_hold_field = false,
>  };
>  
>  static struct at91_twi_pdata at91sam9g20_config = {
> @@ -818,6 +850,7 @@ static struct at91_twi_pdata at91sam9g20_config = {
>   .clk_offset = 4,
>   .has_unre_flag = false,
>   .has_alt_cmd = false,
> + .has_hold_field = false,
>  };
>  
>  static struct at91_twi_pdata at91sam9g10_config = {
> @@ -825,6 +858,7 @@ static struct at91_twi_pdata at91sam9g10_config = {
>

[PATCH v2 4/4] ARM: at91/dt: sama5d2 Xplained: pmic needs a specific sda hold time

[Ludovic Desroches]

Data have to be held longer for the PMIC device. The ACT8945A
datasheet claims that minimum SDA data hold time is about 300 ns.

Signed-off-by: Ludovic Desroches 
---
 arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index ad6de73..9bced00 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -129,6 +129,7 @@
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <_i2c0_default>;
+   i2c-sda-hold-time-ns = <350>;
status = "okay";
 
pmic: act8865@5b {
-- 
2.5.0

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[PATCH v2 3/4] ARM: at91/dt: sama5d4: update i2c compatible string

[Ludovic Desroches]

A new compatible string has been introduced: atmel,sama5d4-i2c. It
allows to use the i2c-sda-hold-time-ns property if needed.

Signed-off-by: Ludovic Desroches 
---
 arch/arm/boot/dts/sama5d4.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 2193637..83d7e7c 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -916,7 +916,7 @@
};
 
i2c0: i2c@f8014000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8014000 0x4000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
@@ -935,7 +935,7 @@
};
 
i2c1: i2c@f8018000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8018000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
@@ -975,7 +975,7 @@
};
 
i2c2: i2c@f8024000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8024000 0x4000>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
-- 
2.5.0

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[PATCH v2 1/4] i2c: at91: add upport for the HOLD field

[Ludovic Desroches]

The hold field allows to configure the data hold time which can be set
with the help of the generic binding 'i2c-sda-hold-time-ns'. This
feature has been introduced with SAMA5D4 SoC family.

Signed-off-by: Ludovic Desroches 
---
 drivers/i2c/busses/i2c-at91.c | 53 ---
 1 file changed, 50 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 10835d1..921d32b 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -64,6 +64,8 @@
 #defineAT91_TWI_IADR   0x000c  /* Internal Address Register */
 
 #defineAT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
*/
+#defineAT91_TWI_CWGR_HOLD_MAX  0x1f
+#defineAT91_TWI_CWGR_HOLD(x)   (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
 
 #defineAT91_TWI_SR 0x0020  /* Status Register */
 #defineAT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
@@ -110,6 +112,7 @@ struct at91_twi_pdata {
unsigned clk_offset;
bool has_unre_flag;
bool has_alt_cmd;
+   bool has_hold_field;
struct at_dma_slave dma_slave;
 };
 
@@ -187,10 +190,11 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  */
 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 {
-   int ckdiv, cdiv, div;
+   int ckdiv, cdiv, div, hold = 0;
struct at91_twi_pdata *pdata = dev->pdata;
int offset = pdata->clk_offset;
int max_ckdiv = pdata->clk_max_div;
+   u32 twd_hold_time_ns = 0;
 
div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
   2 * twi_clk) - offset);
@@ -204,8 +208,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, 
int twi_clk)
cdiv = 255;
}
 
-   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
-   dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
+   if (pdata->has_hold_field) {
+   of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
+_hold_time_ns);
+
+   /*
+* hold time = HOLD + 3 x T_peripheral_clock
+* Use clk rate in kHz to prevent overflows when computing
+* hold.
+*/
+   hold = DIV_ROUND_UP(twd_hold_time_ns
+   * (clk_get_rate(dev->clk) / 1000), 100);
+   hold -= 3;
+   if (hold < 0)
+   hold = 0;
+   if (hold > AT91_TWI_CWGR_HOLD_MAX) {
+   dev_warn(dev->dev,
+"HOLD field set to its maximum value (%d 
instead of %d)\n",
+AT91_TWI_CWGR_HOLD_MAX, hold);
+   hold = AT91_TWI_CWGR_HOLD_MAX;
+   }
+   }
+
+   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
+   | AT91_TWI_CWGR_HOLD(hold);
+
+   dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
+   cdiv, ckdiv, hold, twd_hold_time_ns);
 }
 
 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
@@ -797,6 +826,7 @@ static struct at91_twi_pdata at91rm9200_config = {
.clk_offset = 3,
.has_unre_flag = true,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9261_config = {
@@ -804,6 +834,7 @@ static struct at91_twi_pdata at91sam9261_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9260_config = {
@@ -811,6 +842,7 @@ static struct at91_twi_pdata at91sam9260_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g20_config = {
@@ -818,6 +850,7 @@ static struct at91_twi_pdata at91sam9g20_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g10_config = {
@@ -825,6 +858,7 @@ static struct at91_twi_pdata at91sam9g10_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static const struct platform_device_id at91_twi_devtypes[] = {
@@ -854,6 +888,15 @@ static struct at91_twi_pdata at91sam9x5_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
+};
+
+static struct at91_twi_pdata sama5d4_config = {
+   .clk_max_div = 7,
+   .clk_offset = 4,
+   .has_unre_flag = false,
+   .has_alt_cmd = false,
+   .has_hold_field = true,

[PATCH v2 2/4] i2c: at91: update bindings documention

[Ludovic Desroches]

The i2c-sda-hold-time-ns property is supported from atmel,sama5d4-i2c.

Signed-off-by: Ludovic Desroches 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/i2c/i2c-at91.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt 
b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
index 6e81dc1..ef973a0 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
@@ -3,7 +3,7 @@ I2C for Atmel platforms
 Required properties :
 - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
  "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
- "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c"
+ "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c"
 - reg: physical base address of the controller and length of memory mapped
  region.
 - interrupts: interrupt number to the cpu.
@@ -17,6 +17,8 @@ Optional properties:
 - dma-names: should contain "tx" and "rx".
 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for 
FIFO
   capable I2C controllers.
+- i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c"
+  and "atmel,sama5d2-i2c".
 - Child nodes conforming to i2c bus binding
 
 Examples :
@@ -52,6 +54,7 @@ i2c0: i2c@f8034600 {
#size-cells = <0>;
clocks = <>;
atmel,fifo-size = <16>;
+   i2c-sda-hold-time-ns = <336>;
 
wm8731: wm8731@1a {
compatible = "wm8731";
-- 
2.5.0

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 1/4] i2c: at91: add support for the HOLD field

[Ludovic Desroches]

The hold field allows to configure the data hold time which can be set
with the help of the generic binding 'i2c-sda-hold-time-ns'. This
feature has been introduced with SAMA5D4 SoC family.

Signed-off-by: Ludovic Desroches 
---
 drivers/i2c/busses/i2c-at91.c | 53 ---
 1 file changed, 50 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 10835d1..921d32b 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -64,6 +64,8 @@
 #defineAT91_TWI_IADR   0x000c  /* Internal Address Register */
 
 #defineAT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
*/
+#defineAT91_TWI_CWGR_HOLD_MAX  0x1f
+#defineAT91_TWI_CWGR_HOLD(x)   (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
 
 #defineAT91_TWI_SR 0x0020  /* Status Register */
 #defineAT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
@@ -110,6 +112,7 @@ struct at91_twi_pdata {
unsigned clk_offset;
bool has_unre_flag;
bool has_alt_cmd;
+   bool has_hold_field;
struct at_dma_slave dma_slave;
 };
 
@@ -187,10 +190,11 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  */
 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 {
-   int ckdiv, cdiv, div;
+   int ckdiv, cdiv, div, hold = 0;
struct at91_twi_pdata *pdata = dev->pdata;
int offset = pdata->clk_offset;
int max_ckdiv = pdata->clk_max_div;
+   u32 twd_hold_time_ns = 0;
 
div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
   2 * twi_clk) - offset);
@@ -204,8 +208,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, 
int twi_clk)
cdiv = 255;
}
 
-   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
-   dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
+   if (pdata->has_hold_field) {
+   of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
+_hold_time_ns);
+
+   /*
+* hold time = HOLD + 3 x T_peripheral_clock
+* Use clk rate in kHz to prevent overflows when computing
+* hold.
+*/
+   hold = DIV_ROUND_UP(twd_hold_time_ns
+   * (clk_get_rate(dev->clk) / 1000), 100);
+   hold -= 3;
+   if (hold < 0)
+   hold = 0;
+   if (hold > AT91_TWI_CWGR_HOLD_MAX) {
+   dev_warn(dev->dev,
+"HOLD field set to its maximum value (%d 
instead of %d)\n",
+AT91_TWI_CWGR_HOLD_MAX, hold);
+   hold = AT91_TWI_CWGR_HOLD_MAX;
+   }
+   }
+
+   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
+   | AT91_TWI_CWGR_HOLD(hold);
+
+   dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
+   cdiv, ckdiv, hold, twd_hold_time_ns);
 }
 
 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
@@ -797,6 +826,7 @@ static struct at91_twi_pdata at91rm9200_config = {
.clk_offset = 3,
.has_unre_flag = true,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9261_config = {
@@ -804,6 +834,7 @@ static struct at91_twi_pdata at91sam9261_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9260_config = {
@@ -811,6 +842,7 @@ static struct at91_twi_pdata at91sam9260_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g20_config = {
@@ -818,6 +850,7 @@ static struct at91_twi_pdata at91sam9g20_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g10_config = {
@@ -825,6 +858,7 @@ static struct at91_twi_pdata at91sam9g10_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static const struct platform_device_id at91_twi_devtypes[] = {
@@ -854,6 +888,15 @@ static struct at91_twi_pdata at91sam9x5_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
+};
+
+static struct at91_twi_pdata sama5d4_config = {
+   .clk_max_div = 7,
+   .clk_offset = 4,
+   .has_unre_flag = false,
+   .has_alt_cmd = false,
+   .has_hold_field = true,

[PATCH v2 0/4] i2c: at91: add support for SDA HOLD

[Ludovic Desroches]

Changes:
- from v1:
  - fix typos,
  - change MAX_HOLD macro to follow Nicolas' advice,
  - make it clear that sama5d2 also support i2c-sda-hold-time-ns.

Ludovic Desroches (4):
  i2c: at91: add support for the HOLD field
  i2c: at91: update bindings documention
  ARM: at91/dt: sama5d4: update i2c compatible string
  ARM: at91/dt: sama5d2 Xplained: pmic needs a specific sda hold time

 Documentation/devicetree/bindings/i2c/i2c-at91.txt |  5 +-
 arch/arm/boot/dts/at91-sama5d2_xplained.dts|  1 +
 arch/arm/boot/dts/sama5d4.dtsi |  6 +--
 drivers/i2c/busses/i2c-at91.c  | 53 --
 4 files changed, 58 insertions(+), 7 deletions(-)

-- 
2.5.0

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[PATCH v2 4/4] ARM: at91/dt: sama5d2 Xplained: pmic needs a specific sda hold time

[Ludovic Desroches]

Data have to be held longer for the PMIC device. The ACT8945A
datasheet claims that minimum SDA data hold time is about 300 ns.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index ad6de73..9bced00 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -129,6 +129,7 @@
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <_i2c0_default>;
+   i2c-sda-hold-time-ns = <350>;
status = "okay";
 
pmic: act8865@5b {
-- 
2.5.0

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[PATCH v2 3/4] ARM: at91/dt: sama5d4: update i2c compatible string

[Ludovic Desroches]

A new compatible string has been introduced: atmel,sama5d4-i2c. It
allows to use the i2c-sda-hold-time-ns property if needed.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 arch/arm/boot/dts/sama5d4.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 2193637..83d7e7c 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -916,7 +916,7 @@
};
 
i2c0: i2c@f8014000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8014000 0x4000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
@@ -935,7 +935,7 @@
};
 
i2c1: i2c@f8018000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8018000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
@@ -975,7 +975,7 @@
};
 
i2c2: i2c@f8024000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8024000 0x4000>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
-- 
2.5.0

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Re: [PATCH v2 1/4] i2c: at91: add upport for the HOLD field

[Ludovic Desroches]

Sorry forget this one, I have sent an old version.

On Thu, Dec 03, 2015 at 10:53:51AM +0100, Ludovic Desroches wrote:
> The hold field allows to configure the data hold time which can be set
> with the help of the generic binding 'i2c-sda-hold-time-ns'. This
> feature has been introduced with SAMA5D4 SoC family.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
> ---
>  drivers/i2c/busses/i2c-at91.c | 53 
> ---
>  1 file changed, 50 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
> index 10835d1..921d32b 100644
> --- a/drivers/i2c/busses/i2c-at91.c
> +++ b/drivers/i2c/busses/i2c-at91.c
> @@ -64,6 +64,8 @@
>  #define  AT91_TWI_IADR   0x000c  /* Internal Address Register */
>  
>  #define  AT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
> */
> +#define  AT91_TWI_CWGR_HOLD_MAX  0x1f
> +#define  AT91_TWI_CWGR_HOLD(x)   (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
>  
>  #define  AT91_TWI_SR 0x0020  /* Status Register */
>  #define  AT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
> @@ -110,6 +112,7 @@ struct at91_twi_pdata {
>   unsigned clk_offset;
>   bool has_unre_flag;
>   bool has_alt_cmd;
> + bool has_hold_field;
>   struct at_dma_slave dma_slave;
>  };
>  
> @@ -187,10 +190,11 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
>   */
>  static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
>  {
> - int ckdiv, cdiv, div;
> + int ckdiv, cdiv, div, hold = 0;
>   struct at91_twi_pdata *pdata = dev->pdata;
>   int offset = pdata->clk_offset;
>   int max_ckdiv = pdata->clk_max_div;
> + u32 twd_hold_time_ns = 0;
>  
>   div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
>  2 * twi_clk) - offset);
> @@ -204,8 +208,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev 
> *dev, int twi_clk)
>   cdiv = 255;
>   }
>  
> - dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
> - dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
> + if (pdata->has_hold_field) {
> + of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
> +  _hold_time_ns);
> +
> + /*
> +  * hold time = HOLD + 3 x T_peripheral_clock
> +  * Use clk rate in kHz to prevent overflows when computing
> +  * hold.
> +  */
> + hold = DIV_ROUND_UP(twd_hold_time_ns
> + * (clk_get_rate(dev->clk) / 1000), 100);
> + hold -= 3;
> + if (hold < 0)
> + hold = 0;
> + if (hold > AT91_TWI_CWGR_HOLD_MAX) {
> + dev_warn(dev->dev,
> +  "HOLD field set to its maximum value (%d 
> instead of %d)\n",
> +  AT91_TWI_CWGR_HOLD_MAX, hold);
> + hold = AT91_TWI_CWGR_HOLD_MAX;
> + }
> + }
> +
> + dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
> + | AT91_TWI_CWGR_HOLD(hold);
> +
> + dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
> + cdiv, ckdiv, hold, twd_hold_time_ns);
>  }
>  
>  static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
> @@ -797,6 +826,7 @@ static struct at91_twi_pdata at91rm9200_config = {
>   .clk_offset = 3,
>   .has_unre_flag = true,
>   .has_alt_cmd = false,
> + .has_hold_field = false,
>  };
>  
>  static struct at91_twi_pdata at91sam9261_config = {
> @@ -804,6 +834,7 @@ static struct at91_twi_pdata at91sam9261_config = {
>   .clk_offset = 4,
>   .has_unre_flag = false,
>   .has_alt_cmd = false,
> + .has_hold_field = false,
>  };
>  
>  static struct at91_twi_pdata at91sam9260_config = {
> @@ -811,6 +842,7 @@ static struct at91_twi_pdata at91sam9260_config = {
>   .clk_offset = 4,
>   .has_unre_flag = false,
>   .has_alt_cmd = false,
> + .has_hold_field = false,
>  };
>  
>  static struct at91_twi_pdata at91sam9g20_config = {
> @@ -818,6 +850,7 @@ static struct at91_twi_pdata at91sam9g20_config = {
>   .clk_offset = 4,
>   .has_unre_flag = false,
>   .has_alt_cmd = false,
> + .has_hold_field = false,
>  };
>  
>  static struct at91_twi_pdata at91sam9g10_config = {
> @@ -825,6 +858,7 @@ static struct at91_twi_pd

[PATCH v2 0/4] i2c: at91: add support for SDA HOLD

[Ludovic Desroches]

Changes:
- from v1:
  - fix typos,
  - change MAX_HOLD macro to follow Nicolas' advice,
  - make it clear that sama5d2 also support i2c-sda-hold-time-ns.

Ludovic Desroches (4):
  i2c: at91: add support for the HOLD field
  i2c: at91: update bindings documention
  ARM: at91/dt: sama5d4: update i2c compatible string
  ARM: at91/dt: sama5d2 Xplained: pmic needs a specific sda hold time

 Documentation/devicetree/bindings/i2c/i2c-at91.txt |  5 +-
 arch/arm/boot/dts/at91-sama5d2_xplained.dts|  1 +
 arch/arm/boot/dts/sama5d4.dtsi |  6 +--
 drivers/i2c/busses/i2c-at91.c  | 53 --
 4 files changed, 58 insertions(+), 7 deletions(-)

-- 
2.5.0

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[PATCH v2 1/4] i2c: at91: add support for the HOLD field

[Ludovic Desroches]

The hold field allows to configure the data hold time which can be set
with the help of the generic binding 'i2c-sda-hold-time-ns'. This
feature has been introduced with SAMA5D4 SoC family.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 drivers/i2c/busses/i2c-at91.c | 53 ---
 1 file changed, 50 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 10835d1..921d32b 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -64,6 +64,8 @@
 #defineAT91_TWI_IADR   0x000c  /* Internal Address Register */
 
 #defineAT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
*/
+#defineAT91_TWI_CWGR_HOLD_MAX  0x1f
+#defineAT91_TWI_CWGR_HOLD(x)   (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
 
 #defineAT91_TWI_SR 0x0020  /* Status Register */
 #defineAT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
@@ -110,6 +112,7 @@ struct at91_twi_pdata {
unsigned clk_offset;
bool has_unre_flag;
bool has_alt_cmd;
+   bool has_hold_field;
struct at_dma_slave dma_slave;
 };
 
@@ -187,10 +190,11 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  */
 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 {
-   int ckdiv, cdiv, div;
+   int ckdiv, cdiv, div, hold = 0;
struct at91_twi_pdata *pdata = dev->pdata;
int offset = pdata->clk_offset;
int max_ckdiv = pdata->clk_max_div;
+   u32 twd_hold_time_ns = 0;
 
div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
   2 * twi_clk) - offset);
@@ -204,8 +208,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, 
int twi_clk)
cdiv = 255;
}
 
-   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
-   dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
+   if (pdata->has_hold_field) {
+   of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
+_hold_time_ns);
+
+   /*
+* hold time = HOLD + 3 x T_peripheral_clock
+* Use clk rate in kHz to prevent overflows when computing
+* hold.
+*/
+   hold = DIV_ROUND_UP(twd_hold_time_ns
+   * (clk_get_rate(dev->clk) / 1000), 100);
+   hold -= 3;
+   if (hold < 0)
+   hold = 0;
+   if (hold > AT91_TWI_CWGR_HOLD_MAX) {
+   dev_warn(dev->dev,
+"HOLD field set to its maximum value (%d 
instead of %d)\n",
+AT91_TWI_CWGR_HOLD_MAX, hold);
+   hold = AT91_TWI_CWGR_HOLD_MAX;
+   }
+   }
+
+   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
+   | AT91_TWI_CWGR_HOLD(hold);
+
+   dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
+   cdiv, ckdiv, hold, twd_hold_time_ns);
 }
 
 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
@@ -797,6 +826,7 @@ static struct at91_twi_pdata at91rm9200_config = {
.clk_offset = 3,
.has_unre_flag = true,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9261_config = {
@@ -804,6 +834,7 @@ static struct at91_twi_pdata at91sam9261_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9260_config = {
@@ -811,6 +842,7 @@ static struct at91_twi_pdata at91sam9260_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g20_config = {
@@ -818,6 +850,7 @@ static struct at91_twi_pdata at91sam9g20_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g10_config = {
@@ -825,6 +858,7 @@ static struct at91_twi_pdata at91sam9g10_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static const struct platform_device_id at91_twi_devtypes[] = {
@@ -854,6 +888,15 @@ static struct at91_twi_pdata at91sam9x5_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
+};
+
+static struct at91_twi_pdata sama5d4_config = {
+   .clk_max_div = 7,
+   .clk_offset = 4,
+   .has_unre_flag = false,
+   .has_alt_cmd = fa

[PATCH v2 2/4] i2c: at91: update bindings documention

[Ludovic Desroches]

The i2c-sda-hold-time-ns property is supported from atmel,sama5d4-i2c.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/i2c/i2c-at91.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt 
b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
index 6e81dc1..ef973a0 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
@@ -3,7 +3,7 @@ I2C for Atmel platforms
 Required properties :
 - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
  "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
- "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c"
+ "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c"
 - reg: physical base address of the controller and length of memory mapped
  region.
 - interrupts: interrupt number to the cpu.
@@ -17,6 +17,8 @@ Optional properties:
 - dma-names: should contain "tx" and "rx".
 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for 
FIFO
   capable I2C controllers.
+- i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c"
+  and "atmel,sama5d2-i2c".
 - Child nodes conforming to i2c bus binding
 
 Examples :
@@ -52,6 +54,7 @@ i2c0: i2c@f8034600 {
#size-cells = <0>;
clocks = <>;
atmel,fifo-size = <16>;
+   i2c-sda-hold-time-ns = <336>;
 
wm8731: wm8731@1a {
compatible = "wm8731";
-- 
2.5.0

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[PATCH v2 1/4] i2c: at91: add upport for the HOLD field

[Ludovic Desroches]

The hold field allows to configure the data hold time which can be set
with the help of the generic binding 'i2c-sda-hold-time-ns'. This
feature has been introduced with SAMA5D4 SoC family.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 drivers/i2c/busses/i2c-at91.c | 53 ---
 1 file changed, 50 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 10835d1..921d32b 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -64,6 +64,8 @@
 #defineAT91_TWI_IADR   0x000c  /* Internal Address Register */
 
 #defineAT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
*/
+#defineAT91_TWI_CWGR_HOLD_MAX  0x1f
+#defineAT91_TWI_CWGR_HOLD(x)   (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
 
 #defineAT91_TWI_SR 0x0020  /* Status Register */
 #defineAT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
@@ -110,6 +112,7 @@ struct at91_twi_pdata {
unsigned clk_offset;
bool has_unre_flag;
bool has_alt_cmd;
+   bool has_hold_field;
struct at_dma_slave dma_slave;
 };
 
@@ -187,10 +190,11 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  */
 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 {
-   int ckdiv, cdiv, div;
+   int ckdiv, cdiv, div, hold = 0;
struct at91_twi_pdata *pdata = dev->pdata;
int offset = pdata->clk_offset;
int max_ckdiv = pdata->clk_max_div;
+   u32 twd_hold_time_ns = 0;
 
div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
   2 * twi_clk) - offset);
@@ -204,8 +208,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, 
int twi_clk)
cdiv = 255;
}
 
-   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
-   dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
+   if (pdata->has_hold_field) {
+   of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
+_hold_time_ns);
+
+   /*
+* hold time = HOLD + 3 x T_peripheral_clock
+* Use clk rate in kHz to prevent overflows when computing
+* hold.
+*/
+   hold = DIV_ROUND_UP(twd_hold_time_ns
+   * (clk_get_rate(dev->clk) / 1000), 100);
+   hold -= 3;
+   if (hold < 0)
+   hold = 0;
+   if (hold > AT91_TWI_CWGR_HOLD_MAX) {
+   dev_warn(dev->dev,
+"HOLD field set to its maximum value (%d 
instead of %d)\n",
+AT91_TWI_CWGR_HOLD_MAX, hold);
+   hold = AT91_TWI_CWGR_HOLD_MAX;
+   }
+   }
+
+   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
+   | AT91_TWI_CWGR_HOLD(hold);
+
+   dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
+   cdiv, ckdiv, hold, twd_hold_time_ns);
 }
 
 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
@@ -797,6 +826,7 @@ static struct at91_twi_pdata at91rm9200_config = {
.clk_offset = 3,
.has_unre_flag = true,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9261_config = {
@@ -804,6 +834,7 @@ static struct at91_twi_pdata at91sam9261_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9260_config = {
@@ -811,6 +842,7 @@ static struct at91_twi_pdata at91sam9260_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g20_config = {
@@ -818,6 +850,7 @@ static struct at91_twi_pdata at91sam9g20_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g10_config = {
@@ -825,6 +858,7 @@ static struct at91_twi_pdata at91sam9g10_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static const struct platform_device_id at91_twi_devtypes[] = {
@@ -854,6 +888,15 @@ static struct at91_twi_pdata at91sam9x5_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
+};
+
+static struct at91_twi_pdata sama5d4_config = {
+   .clk_max_div = 7,
+   .clk_offset = 4,
+   .has_unre_flag = false,
+   .has_alt_cmd = fa

[PATCH] dmaengine: at_xdmac: fix bad behavior in interleaved mode

[Ludovic Desroches]

From: Sylvain ETIENNE 

When performing interleaved transfers with numf > 1, an extra line is
copied. The mbr.bc field is incremented once too often. The length of
the block is (BLEN+1) microblocks.

Signed-off-by: Sylvain ETIENNE 
Signed-off-by: Ludovic Desroches 
Fixes: 4e5385784e69 ("dmaengine: at_xdmac: handle numf > 1")
---
 drivers/dma/at_xdmac.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 7f039de..c8faaa5 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -965,7 +965,9 @@ at_xdmac_prep_interleaved(struct dma_chan *chan,
NULL,
src_addr, dst_addr,
xt, xt->sgl);
-   for (i = 0; i < xt->numf; i++)
+
+   /* Length of the block is (BLEN+1) microblocks. */
+   for (i = 0; i < xt->numf - 1; i++)
at_xdmac_increment_block_count(chan, first);
 
dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 
0x%p\n",
-- 
2.5.0

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[PATCH 4/4] ARM: at91/dt: sama5d2 Xplained: pmic needs a specific sda hold time

[Ludovic Desroches]

Data have to been hold longer for the PMIC device.

Signed-off-by: Ludovic Desroches 
---
 arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index ad6de73..9bced00 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -129,6 +129,7 @@
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <_i2c0_default>;
+   i2c-sda-hold-time-ns = <350>;
status = "okay";
 
pmic: act8865@5b {
-- 
2.5.0

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[PATCH 3/4] ARM: at91/dt: sama5d4: update i2c compatible string

[Ludovic Desroches]

A new compatible string has been introduced: atmel,sama5d4-i2c. It
allows to use the i2c-sda-hold-time-ns property if needed.

Signed-off-by: Ludovic Desroches 
---
 arch/arm/boot/dts/sama5d4.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 2193637..83d7e7c 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -916,7 +916,7 @@
};
 
i2c0: i2c@f8014000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8014000 0x4000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
@@ -935,7 +935,7 @@
};
 
i2c1: i2c@f8018000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8018000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
@@ -975,7 +975,7 @@
};
 
i2c2: i2c@f8024000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8024000 0x4000>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
-- 
2.5.0

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[PATCH 2/4] i2c: at91: update bindings documention

[Ludovic Desroches]

The i2c-sda-hold-time-ns property is supported from atmel,sama5d4-i2c.

Signed-off-by: Ludovic Desroches 
---
 Documentation/devicetree/bindings/i2c/i2c-at91.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt 
b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
index 6e81dc1..67c6f2e 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
@@ -3,7 +3,7 @@ I2C for Atmel platforms
 Required properties :
 - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
  "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
- "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c"
+ "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c"
 - reg: physical base address of the controller and length of memory mapped
  region.
 - interrupts: interrupt number to the cpu.
@@ -17,6 +17,7 @@ Optional properties:
 - dma-names: should contain "tx" and "rx".
 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for 
FIFO
   capable I2C controllers.
+- i2c-sda-hold-time-ns: TWD hold time, only available from "atmel,sama5d4-i2c".
 - Child nodes conforming to i2c bus binding
 
 Examples :
@@ -52,6 +53,7 @@ i2c0: i2c@f8034600 {
#size-cells = <0>;
clocks = <>;
atmel,fifo-size = <16>;
+   i2c-sda-hold-time-ns = <336>;
 
wm8731: wm8731@1a {
compatible = "wm8731";
-- 
2.5.0

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[PATCH 1/4] i2c: at91: add upport for the HOLD field

[Ludovic Desroches]

The hold field allows to configure the data hold time which can be set
with the help of the generic binding 'i2c-sda-hold-time-ns'. This
feature has been introduced with SAMA5D4 SoC family.

Signed-off-by: Ludovic Desroches 
---
 drivers/i2c/busses/i2c-at91.c | 54 ---
 1 file changed, 51 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 10835d1..09e1690 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -64,6 +64,7 @@
 #defineAT91_TWI_IADR   0x000c  /* Internal Address Register */
 
 #defineAT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
*/
+#defineAT91_TWI_CWGR_HOLD(x)   (((x) & 0x1f) << 24)
 
 #defineAT91_TWI_SR 0x0020  /* Status Register */
 #defineAT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
@@ -110,6 +111,7 @@ struct at91_twi_pdata {
unsigned clk_offset;
bool has_unre_flag;
bool has_alt_cmd;
+   bool has_hold_field;
struct at_dma_slave dma_slave;
 };
 
@@ -187,10 +189,13 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  */
 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 {
-   int ckdiv, cdiv, div;
+   int ckdiv, cdiv, div, hold = 0;
struct at91_twi_pdata *pdata = dev->pdata;
int offset = pdata->clk_offset;
int max_ckdiv = pdata->clk_max_div;
+   u32 twd_hold_time_ns = 0;
+
+#define MAX_HOLD 31
 
div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
   2 * twi_clk) - offset);
@@ -204,8 +209,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, 
int twi_clk)
cdiv = 255;
}
 
-   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
-   dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
+   if (pdata->has_hold_field) {
+   of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
+_hold_time_ns);
+
+   /*
+* hold time = HOLD + 3 x T_peripheral_clock
+* Use clk rate in kHz to prevent overflows when computing
+* hold.
+*/
+   hold = DIV_ROUND_UP(twd_hold_time_ns
+   * (clk_get_rate(dev->clk) / 1000), 100);
+   hold -= 3;
+   if (hold < 0)
+   hold = 0;
+   if (hold > MAX_HOLD) {
+   dev_warn(dev->dev,
+"HOLD field set to its maximum value (%d 
instead of %d)\n",
+MAX_HOLD, hold);
+   hold = MAX_HOLD;
+   }
+   }
+
+   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
+   | AT91_TWI_CWGR_HOLD(hold);
+
+   dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
+   cdiv, ckdiv, hold, twd_hold_time_ns);
 }
 
 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
@@ -797,6 +827,7 @@ static struct at91_twi_pdata at91rm9200_config = {
.clk_offset = 3,
.has_unre_flag = true,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9261_config = {
@@ -804,6 +835,7 @@ static struct at91_twi_pdata at91sam9261_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9260_config = {
@@ -811,6 +843,7 @@ static struct at91_twi_pdata at91sam9260_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g20_config = {
@@ -818,6 +851,7 @@ static struct at91_twi_pdata at91sam9g20_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g10_config = {
@@ -825,6 +859,7 @@ static struct at91_twi_pdata at91sam9g10_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static const struct platform_device_id at91_twi_devtypes[] = {
@@ -854,6 +889,15 @@ static struct at91_twi_pdata at91sam9x5_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
+};
+
+static struct at91_twi_pdata sama5d4_config = {
+   .clk_max_div = 7,
+   .clk_offset = 4,
+   .has_unre_flag = false,
+   .has_alt_cmd = false,
+   .has_hold_field = true,
 };
 
 static struct at91_twi_pdata sama5d2_config = {
@@ -861,6 +905,7 @@ static struc

Re: [PATCH] ARM: at91/dt: add always-on to 1.8V regulator

[Ludovic Desroches]

On Wed, Dec 02, 2015 at 11:06:40AM +0100, Nicolas Ferre wrote:
> As the SDHCI controller needs the 1.8V line to be always enabled for some eMMC
> configurations, set the proper "regulator-always-on" property to the board DTS
> files.
> Note that the sdhci classical regulator definitions doesn't suit our 
> controller
> for this 1.8V purpose.
> 
> Signed-off-by: Nicolas Ferre 

Acked-by: Ludovic Desroches 

> ---
>  arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
> b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> index ad6de73ed5a5..e74df327cdd3 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> @@ -184,6 +184,7 @@
>   regulator-name = 
> "VDD_SDHC_1V8";
>   regulator-min-microvolt 
> = <180>;
>   regulator-max-microvolt 
> = <180>;
> + regulator-always-on;
>   };
>   };
>   };
> -- 
> 2.1.3
> 
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[PATCH] dmaengine: at_xdmac: fix bad behavior in interleaved mode

[Ludovic Desroches]

From: Sylvain ETIENNE <sylvain.etie...@ingenico.com>

When performing interleaved transfers with numf > 1, an extra line is
copied. The mbr.bc field is incremented once too often. The length of
the block is (BLEN+1) microblocks.

Signed-off-by: Sylvain ETIENNE <sylvain.etie...@ingenico.com>
Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
Fixes: 4e5385784e69 ("dmaengine: at_xdmac: handle numf > 1")
---
 drivers/dma/at_xdmac.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 7f039de..c8faaa5 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -965,7 +965,9 @@ at_xdmac_prep_interleaved(struct dma_chan *chan,
NULL,
src_addr, dst_addr,
xt, xt->sgl);
-   for (i = 0; i < xt->numf; i++)
+
+   /* Length of the block is (BLEN+1) microblocks. */
+   for (i = 0; i < xt->numf - 1; i++)
at_xdmac_increment_block_count(chan, first);
 
dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 
0x%p\n",
-- 
2.5.0

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[PATCH 2/4] i2c: at91: update bindings documention

[Ludovic Desroches]

The i2c-sda-hold-time-ns property is supported from atmel,sama5d4-i2c.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 Documentation/devicetree/bindings/i2c/i2c-at91.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt 
b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
index 6e81dc1..67c6f2e 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
@@ -3,7 +3,7 @@ I2C for Atmel platforms
 Required properties :
 - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
  "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
- "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c"
+ "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c"
 - reg: physical base address of the controller and length of memory mapped
  region.
 - interrupts: interrupt number to the cpu.
@@ -17,6 +17,7 @@ Optional properties:
 - dma-names: should contain "tx" and "rx".
 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for 
FIFO
   capable I2C controllers.
+- i2c-sda-hold-time-ns: TWD hold time, only available from "atmel,sama5d4-i2c".
 - Child nodes conforming to i2c bus binding
 
 Examples :
@@ -52,6 +53,7 @@ i2c0: i2c@f8034600 {
#size-cells = <0>;
clocks = <>;
atmel,fifo-size = <16>;
+   i2c-sda-hold-time-ns = <336>;
 
wm8731: wm8731@1a {
compatible = "wm8731";
-- 
2.5.0

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[PATCH 1/4] i2c: at91: add upport for the HOLD field

[Ludovic Desroches]

The hold field allows to configure the data hold time which can be set
with the help of the generic binding 'i2c-sda-hold-time-ns'. This
feature has been introduced with SAMA5D4 SoC family.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 drivers/i2c/busses/i2c-at91.c | 54 ---
 1 file changed, 51 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 10835d1..09e1690 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -64,6 +64,7 @@
 #defineAT91_TWI_IADR   0x000c  /* Internal Address Register */
 
 #defineAT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
*/
+#defineAT91_TWI_CWGR_HOLD(x)   (((x) & 0x1f) << 24)
 
 #defineAT91_TWI_SR 0x0020  /* Status Register */
 #defineAT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
@@ -110,6 +111,7 @@ struct at91_twi_pdata {
unsigned clk_offset;
bool has_unre_flag;
bool has_alt_cmd;
+   bool has_hold_field;
struct at_dma_slave dma_slave;
 };
 
@@ -187,10 +189,13 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  */
 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 {
-   int ckdiv, cdiv, div;
+   int ckdiv, cdiv, div, hold = 0;
struct at91_twi_pdata *pdata = dev->pdata;
int offset = pdata->clk_offset;
int max_ckdiv = pdata->clk_max_div;
+   u32 twd_hold_time_ns = 0;
+
+#define MAX_HOLD 31
 
div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
   2 * twi_clk) - offset);
@@ -204,8 +209,33 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, 
int twi_clk)
cdiv = 255;
}
 
-   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
-   dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
+   if (pdata->has_hold_field) {
+   of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
+_hold_time_ns);
+
+   /*
+* hold time = HOLD + 3 x T_peripheral_clock
+* Use clk rate in kHz to prevent overflows when computing
+* hold.
+*/
+   hold = DIV_ROUND_UP(twd_hold_time_ns
+   * (clk_get_rate(dev->clk) / 1000), 100);
+   hold -= 3;
+   if (hold < 0)
+   hold = 0;
+   if (hold > MAX_HOLD) {
+   dev_warn(dev->dev,
+"HOLD field set to its maximum value (%d 
instead of %d)\n",
+MAX_HOLD, hold);
+   hold = MAX_HOLD;
+   }
+   }
+
+   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
+   | AT91_TWI_CWGR_HOLD(hold);
+
+   dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
+   cdiv, ckdiv, hold, twd_hold_time_ns);
 }
 
 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
@@ -797,6 +827,7 @@ static struct at91_twi_pdata at91rm9200_config = {
.clk_offset = 3,
.has_unre_flag = true,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9261_config = {
@@ -804,6 +835,7 @@ static struct at91_twi_pdata at91sam9261_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9260_config = {
@@ -811,6 +843,7 @@ static struct at91_twi_pdata at91sam9260_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g20_config = {
@@ -818,6 +851,7 @@ static struct at91_twi_pdata at91sam9g20_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static struct at91_twi_pdata at91sam9g10_config = {
@@ -825,6 +859,7 @@ static struct at91_twi_pdata at91sam9g10_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
 };
 
 static const struct platform_device_id at91_twi_devtypes[] = {
@@ -854,6 +889,15 @@ static struct at91_twi_pdata at91sam9x5_config = {
.clk_offset = 4,
.has_unre_flag = false,
.has_alt_cmd = false,
+   .has_hold_field = false,
+};
+
+static struct at91_twi_pdata sama5d4_config = {
+   .clk_max_div = 7,
+   .clk_offset = 4,
+   .has_unre_flag = false,
+   .has_alt_cmd = false,
+   .has_hold_field = true,
 };
 
 static struct at91_twi_pdata sama5d2_config =

Re: [PATCH] ARM: at91/dt: add always-on to 1.8V regulator

[Ludovic Desroches]

On Wed, Dec 02, 2015 at 11:06:40AM +0100, Nicolas Ferre wrote:
> As the SDHCI controller needs the 1.8V line to be always enabled for some eMMC
> configurations, set the proper "regulator-always-on" property to the board DTS
> files.
> Note that the sdhci classical regulator definitions doesn't suit our 
> controller
> for this 1.8V purpose.
> 
> Signed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com>

Acked-by: Ludovic Desroches <ludovic.desroc...@atmel.com>

> ---
>  arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
> b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> index ad6de73ed5a5..e74df327cdd3 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> @@ -184,6 +184,7 @@
>   regulator-name = 
> "VDD_SDHC_1V8";
>   regulator-min-microvolt 
> = <180>;
>   regulator-max-microvolt 
> = <180>;
> + regulator-always-on;
>   };
>   };
>   };
> -- 
> 2.1.3
> 
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[PATCH 3/4] ARM: at91/dt: sama5d4: update i2c compatible string

[Ludovic Desroches]

A new compatible string has been introduced: atmel,sama5d4-i2c. It
allows to use the i2c-sda-hold-time-ns property if needed.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 arch/arm/boot/dts/sama5d4.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 2193637..83d7e7c 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -916,7 +916,7 @@
};
 
i2c0: i2c@f8014000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8014000 0x4000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
@@ -935,7 +935,7 @@
};
 
i2c1: i2c@f8018000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8018000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
@@ -975,7 +975,7 @@
};
 
i2c2: i2c@f8024000 {
-   compatible = "atmel,at91sam9x5-i2c";
+   compatible = "atmel,sama5d4-i2c";
reg = <0xf8024000 0x4000>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
dmas = <
-- 
2.5.0

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[PATCH 4/4] ARM: at91/dt: sama5d2 Xplained: pmic needs a specific sda hold time

[Ludovic Desroches]

Data have to been hold longer for the PMIC device.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index ad6de73..9bced00 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -129,6 +129,7 @@
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <_i2c0_default>;
+   i2c-sda-hold-time-ns = <350>;
status = "okay";
 
pmic: act8865@5b {
-- 
2.5.0

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[PATCH] pinctrl: at91-pio4: fix memleak after using dt map

[Ludovic Desroches]

configs is allocated by pinconf_generic_parse_dt_config(),
pinctrl_utils_add_map_configs() duplicates configs so it can and has to
be freed to prevent memory leaks.

Signed-off-by: Ludovic Desroches 
Reported-by: Yingjoe Chen 
---
 drivers/pinctrl/pinctrl-at91-pio4.c | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c 
b/drivers/pinctrl/pinctrl-at91-pio4.c
index 33edd07..3a384ee 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -500,7 +500,8 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev 
*pctldev,
if (!num_pins) {
dev_err(pctldev->dev, "no pins found in node %s\n",
of_node_full_name(np));
-   return -EINVAL;
+   ret = -EINVAL;
+   goto exit;
}
 
/*
@@ -514,19 +515,19 @@ static int atmel_pctl_dt_subnode_to_map(struct 
pinctrl_dev *pctldev,
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
reserve);
if (ret < 0)
-   return ret;
+   goto exit;
 
for (i = 0; i < num_pins; i++) {
const char *group, *func;
 
ret = of_property_read_u32_index(np, "pinmux", i, );
if (ret)
-   return ret;
+   goto exit;
 
ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, ,
   );
if (ret)
-   return ret;
+   goto exit;
 
pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
  group, func);
@@ -537,11 +538,13 @@ static int atmel_pctl_dt_subnode_to_map(struct 
pinctrl_dev *pctldev,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (ret < 0)
-   return ret;
+   goto exit;
}
}
 
-   return 0;
+exit:
+   kfree(configs);
+   return ret;
 }
 
 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
-- 
2.5.0

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[PATCH] ARM: at91: fix pinctrl driver selection

[Ludovic Desroches]

Move the selection of the pinctrl driver to SoC family level since we
have two pinctrl drivers. It is useless to select one which is not
compatible with the SoC.

Signed-off-by: Ludovic Desroches 
---

This patch is an improvement of this one (already acked by Linus and Nicolas):
https://lkml.org/lkml/2015/9/16/522

Without it, at91 pio4 driver is not compiled causing boot failure for SAMA5D2.

 arch/arm/mach-at91/Kconfig | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 9267300..28656c2 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -4,7 +4,6 @@ menuconfig ARCH_AT91
select ARCH_REQUIRE_GPIOLIB
select COMMON_CLK_AT91
select PINCTRL
-   select PINCTRL_AT91
select SOC_BUS
 
 if ARCH_AT91
@@ -17,6 +16,7 @@ config SOC_SAMA5D2
select HAVE_AT91_USB_CLK
select HAVE_AT91_H32MX
select HAVE_AT91_GENERATED_CLK
+   select PINCTRL_AT91PIO4
help
  Select this if ou are using one of Atmel's SAMA5D2 family SoC.
 
@@ -27,6 +27,7 @@ config SOC_SAMA5D3
select HAVE_AT91_UTMI
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
+   select PINCTRL_AT91
help
  Select this if you are using one of Atmel's SAMA5D3 family SoC.
  This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
@@ -40,6 +41,7 @@ config SOC_SAMA5D4
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
select HAVE_AT91_H32MX
+   select PINCTRL_AT91
help
  Select this if you are using one of Atmel's SAMA5D4 family SoC.
 
@@ -50,6 +52,7 @@ config SOC_AT91RM9200
select CPU_ARM920T
select HAVE_AT91_USB_CLK
select MIGHT_HAVE_PCI
+   select PINCTRL_AT91
select SOC_SAM_V4_V5
select SRAM if PM
help
@@ -65,6 +68,7 @@ config SOC_AT91SAM9
select HAVE_AT91_UTMI
select HAVE_FB_ATMEL
select MEMORY
+   select PINCTRL_AT91
select SOC_SAM_V4_V5
select SRAM if PM
help
-- 
2.5.0

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Re: [PATCH] pinctrl: update document for pinconf_generic_parse_dt_config

[Ludovic Desroches]

On Tue, Dec 01, 2015 at 11:12:16AM +0100, Linus Walleij wrote:
> On Wed, Nov 25, 2015 at 1:13 PM, Yingjoe Chen  
> wrote:
> 
> > The returned configs from pinconf_generic_parse_dt_config() is
> > duplicated from original. Make it clear it must be freed when no
> > longer necessary.
> >
> > Signed-off-by: Yingjoe Chen 
> 
> Patch applied.
> 
> > It seems memleak in pinctrl-mtk-common.c[1] is not alone. After a quick
> > glance I notice similar issues in drivers/pinctrl/pinctrl-at91-pio4.c and
> > drivers/pinctrl/nomadik/pinctrl-abx500.c.
> 
> Patches fixing them are coming? ;)

Yes, it's planned.

Regards

Ludovic
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Re: [PATCH] pinctrl: update document for pinconf_generic_parse_dt_config

[Ludovic Desroches]

On Tue, Dec 01, 2015 at 11:12:16AM +0100, Linus Walleij wrote:
> On Wed, Nov 25, 2015 at 1:13 PM, Yingjoe Chen  
> wrote:
> 
> > The returned configs from pinconf_generic_parse_dt_config() is
> > duplicated from original. Make it clear it must be freed when no
> > longer necessary.
> >
> > Signed-off-by: Yingjoe Chen 
> 
> Patch applied.
> 
> > It seems memleak in pinctrl-mtk-common.c[1] is not alone. After a quick
> > glance I notice similar issues in drivers/pinctrl/pinctrl-at91-pio4.c and
> > drivers/pinctrl/nomadik/pinctrl-abx500.c.
> 
> Patches fixing them are coming? ;)

Yes, it's planned.

Regards

Ludovic
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[PATCH] ARM: at91: fix pinctrl driver selection

[Ludovic Desroches]

Move the selection of the pinctrl driver to SoC family level since we
have two pinctrl drivers. It is useless to select one which is not
compatible with the SoC.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---

This patch is an improvement of this one (already acked by Linus and Nicolas):
https://lkml.org/lkml/2015/9/16/522

Without it, at91 pio4 driver is not compiled causing boot failure for SAMA5D2.

 arch/arm/mach-at91/Kconfig | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 9267300..28656c2 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -4,7 +4,6 @@ menuconfig ARCH_AT91
select ARCH_REQUIRE_GPIOLIB
select COMMON_CLK_AT91
select PINCTRL
-   select PINCTRL_AT91
select SOC_BUS
 
 if ARCH_AT91
@@ -17,6 +16,7 @@ config SOC_SAMA5D2
select HAVE_AT91_USB_CLK
select HAVE_AT91_H32MX
select HAVE_AT91_GENERATED_CLK
+   select PINCTRL_AT91PIO4
help
  Select this if ou are using one of Atmel's SAMA5D2 family SoC.
 
@@ -27,6 +27,7 @@ config SOC_SAMA5D3
select HAVE_AT91_UTMI
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
+   select PINCTRL_AT91
help
  Select this if you are using one of Atmel's SAMA5D3 family SoC.
  This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
@@ -40,6 +41,7 @@ config SOC_SAMA5D4
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
select HAVE_AT91_H32MX
+   select PINCTRL_AT91
help
  Select this if you are using one of Atmel's SAMA5D4 family SoC.
 
@@ -50,6 +52,7 @@ config SOC_AT91RM9200
select CPU_ARM920T
select HAVE_AT91_USB_CLK
select MIGHT_HAVE_PCI
+   select PINCTRL_AT91
select SOC_SAM_V4_V5
select SRAM if PM
help
@@ -65,6 +68,7 @@ config SOC_AT91SAM9
select HAVE_AT91_UTMI
select HAVE_FB_ATMEL
select MEMORY
+   select PINCTRL_AT91
select SOC_SAM_V4_V5
select SRAM if PM
help
-- 
2.5.0

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[PATCH] pinctrl: at91-pio4: fix memleak after using dt map

[Ludovic Desroches]

configs is allocated by pinconf_generic_parse_dt_config(),
pinctrl_utils_add_map_configs() duplicates configs so it can and has to
be freed to prevent memory leaks.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
Reported-by: Yingjoe Chen <yingjoe.c...@mediatek.com>
---
 drivers/pinctrl/pinctrl-at91-pio4.c | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c 
b/drivers/pinctrl/pinctrl-at91-pio4.c
index 33edd07..3a384ee 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -500,7 +500,8 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev 
*pctldev,
if (!num_pins) {
dev_err(pctldev->dev, "no pins found in node %s\n",
of_node_full_name(np));
-   return -EINVAL;
+   ret = -EINVAL;
+   goto exit;
}
 
/*
@@ -514,19 +515,19 @@ static int atmel_pctl_dt_subnode_to_map(struct 
pinctrl_dev *pctldev,
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
reserve);
if (ret < 0)
-   return ret;
+   goto exit;
 
for (i = 0; i < num_pins; i++) {
const char *group, *func;
 
ret = of_property_read_u32_index(np, "pinmux", i, );
if (ret)
-   return ret;
+   goto exit;
 
ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, ,
   );
if (ret)
-   return ret;
+   goto exit;
 
pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
  group, func);
@@ -537,11 +538,13 @@ static int atmel_pctl_dt_subnode_to_map(struct 
pinctrl_dev *pctldev,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (ret < 0)
-   return ret;
+   goto exit;
}
}
 
-   return 0;
+exit:
+   kfree(configs);
+   return ret;
 }
 
 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
-- 
2.5.0

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Re: [PATCH 1/3] i2c: at91: add setting HOLD field of TWIHS_CWGR via DT

[Ludovic Desroches]

On Mon, Nov 30, 2015 at 04:13:20PM +0100, Wolfram Sang wrote:
> On Tue, Nov 24, 2015 at 02:47:40PM +0100, Ludovic Desroches wrote:
> > From: Wenyou Yang 
> > 
> > Add the HOLD field management. Some i2c devices need a longer data hold
> > time than the one given in the i2c bus specification. Since this value
> > depends on the i2c device connected to the bus, add a DT property to
> > configure it: "atmel,twd-hold-cycles".
> 
> We already have "i2c-sda-hold-time-ns". Can you use that one? Sorry that
> this is not obviously documented, I am working on it...
> 

I think we can use it, I'll rework the patch to convert duration in
number of cycles.
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Re: [PATCH 1/3] i2c: at91: add setting HOLD field of TWIHS_CWGR via DT

[Ludovic Desroches]

On Mon, Nov 30, 2015 at 04:13:20PM +0100, Wolfram Sang wrote:
> On Tue, Nov 24, 2015 at 02:47:40PM +0100, Ludovic Desroches wrote:
> > From: Wenyou Yang <wenyou.y...@atmel.com>
> > 
> > Add the HOLD field management. Some i2c devices need a longer data hold
> > time than the one given in the i2c bus specification. Since this value
> > depends on the i2c device connected to the bus, add a DT property to
> > configure it: "atmel,twd-hold-cycles".
> 
> We already have "i2c-sda-hold-time-ns". Can you use that one? Sorry that
> this is not obviously documented, I am working on it...
> 

I think we can use it, I'll rework the patch to convert duration in
number of cycles.
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Re: [PATCH] mmc: sdhci-of-at91: controller is suspended too early

[Ludovic Desroches]

On Fri, Nov 27, 2015 at 03:11:58PM +0100, Ulf Hansson wrote:
> On 26 November 2015 at 17:41, Ludovic Desroches
>  wrote:
> > When calling sdhci_add_host(), the controller is already suspended. It
> > causes to read 0 in registers.
> > Increment the device's usage counter before calling sdhci_add_host(),
> > decrement it after and put it in suspend if it is possible.
> >
> > Signed-off-by: Ludovic Desroches 
> > Fixes: "mmc: sdhci-of-at91: add PM support"
> 
> Thanks, applied for next!
> 
> Actually I decided to squash this change into the "Fixes commit"
> itself, thus not breaking bisecting.

Ok perfect. Thanks

Regards

Ludovic
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Re: [PATCH] mmc: sdhci-of-at91: controller is suspended too early

[Ludovic Desroches]

On Fri, Nov 27, 2015 at 03:11:58PM +0100, Ulf Hansson wrote:
> On 26 November 2015 at 17:41, Ludovic Desroches
> <ludovic.desroc...@atmel.com> wrote:
> > When calling sdhci_add_host(), the controller is already suspended. It
> > causes to read 0 in registers.
> > Increment the device's usage counter before calling sdhci_add_host(),
> > decrement it after and put it in suspend if it is possible.
> >
> > Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
> > Fixes: "mmc: sdhci-of-at91: add PM support"
> 
> Thanks, applied for next!
> 
> Actually I decided to squash this change into the "Fixes commit"
> itself, thus not breaking bisecting.

Ok perfect. Thanks

Regards

Ludovic
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[PATCH] mmc: sdhci-of-at91: controller is suspended too early

[Ludovic Desroches]

When calling sdhci_add_host(), the controller is already suspended. It
causes to read 0 in registers.
Increment the device's usage counter before calling sdhci_add_host(),
decrement it after and put it in suspend if it is possible.

Signed-off-by: Ludovic Desroches 
Fixes: "mmc: sdhci-of-at91: add PM support"
---
 drivers/mmc/host/sdhci-of-at91.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
index 81ab9db..7e7d8f0 100644
--- a/drivers/mmc/host/sdhci-of-at91.c
+++ b/drivers/mmc/host/sdhci-of-at91.c
@@ -200,6 +200,7 @@ static int sdhci_at91_probe(struct platform_device *pdev)
 
sdhci_get_of_property(pdev);
 
+   pm_runtime_get_noresume(>dev);
pm_runtime_set_active(>dev);
pm_runtime_enable(>dev);
pm_runtime_set_autosuspend_delay(>dev, 50);
@@ -209,6 +210,8 @@ static int sdhci_at91_probe(struct platform_device *pdev)
if (ret)
goto pm_runtime_disable;
 
+   pm_runtime_put_autosuspend(>dev);
+
return 0;
 
 pm_runtime_disable:
-- 
2.5.0

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Re: [PATCH v2] mmc: sdhci at91: add PM support

[Ludovic Desroches]

On Thu, Nov 26, 2015 at 05:24:40PM +0100, Ulf Hansson wrote:
> On 26 November 2015 at 17:07, Ludovic Desroches
>  wrote:
> > On Tue, Nov 10, 2015 at 12:12:30PM +0100, Ulf Hansson wrote:
> >> On 10 November 2015 at 11:36, Ludovic Desroches
> >>  wrote:
> >> > Add runtime PM support and use runtime_force_suspend|resume() for system
> >> > PM.
> >> >
> >
> > [...]
> >
> >> >  static int sdhci_at91_probe(struct platform_device *pdev)
> >> >  {
> >> > const struct of_device_id   *match;
> >> > @@ -148,6 +206,11 @@ static int sdhci_at91_probe(struct platform_device 
> >> > *pdev)
> >> > if (ret)
> >> > goto clocks_disable_unprepare;
> >> >
> >> > +   pm_runtime_set_active(>dev);
> >> > +   pm_runtime_enable(>dev);
> >> > +   pm_runtime_set_autosuspend_delay(>dev, 50);
> >> > +   pm_runtime_use_autosuspend(>dev);
> >>
> >> Move these four runtime PM calls above sdhci_add_host(), as after that
> >> point the host is used and thus runtime PM operations starts.
> >
> > Sadly I have discovered a bit late it is not working when doing this
> > because the controller has been suspended before doing the
> > sdhci_add_host().
> >
> > What is the right way to fix it? Calling pm_runtime_get_noresume()
> 
> I would do that before pm_runtime_enable().
> 
> > before sdhci_add_host() and calling pm_runtime_put_autosuspend() after?
> 
> Yes. Sorry for not spotting this before.

No problem, I am faulty too, it was not so trivial!

I am sending the fix. Thanks

Regards

Ludovic
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Re: [PATCH v2] mmc: sdhci at91: add PM support

[Ludovic Desroches]

On Tue, Nov 10, 2015 at 12:12:30PM +0100, Ulf Hansson wrote:
> On 10 November 2015 at 11:36, Ludovic Desroches
>  wrote:
> > Add runtime PM support and use runtime_force_suspend|resume() for system
> > PM.
> >

[...]

> >  static int sdhci_at91_probe(struct platform_device *pdev)
> >  {
> > const struct of_device_id   *match;
> > @@ -148,6 +206,11 @@ static int sdhci_at91_probe(struct platform_device 
> > *pdev)
> > if (ret)
> > goto clocks_disable_unprepare;
> >
> > +   pm_runtime_set_active(>dev);
> > +   pm_runtime_enable(>dev);
> > +   pm_runtime_set_autosuspend_delay(>dev, 50);
> > +   pm_runtime_use_autosuspend(>dev);
> 
> Move these four runtime PM calls above sdhci_add_host(), as after that
> point the host is used and thus runtime PM operations starts.

Sadly I have discovered a bit late it is not working when doing this
because the controller has been suspended before doing the
sdhci_add_host().

What is the right way to fix it? Calling pm_runtime_get_noresume()
before sdhci_add_host() and calling pm_runtime_put_autosuspend() after?

> 
> > +
> > return 0;
> >
> >  clocks_disable_unprepare:
> > @@ -165,6 +228,7 @@ static int sdhci_at91_remove(struct platform_device 
> > *pdev)
> > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> > struct sdhci_at91_priv  *priv = pltfm_host->priv;
> >

Regards

Ludovic
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Re: [PATCH v2] mmc: sdhci at91: add PM support

[Ludovic Desroches]

On Tue, Nov 10, 2015 at 12:12:30PM +0100, Ulf Hansson wrote:
> On 10 November 2015 at 11:36, Ludovic Desroches
> <ludovic.desroc...@atmel.com> wrote:
> > Add runtime PM support and use runtime_force_suspend|resume() for system
> > PM.
> >

[...]

> >  static int sdhci_at91_probe(struct platform_device *pdev)
> >  {
> > const struct of_device_id   *match;
> > @@ -148,6 +206,11 @@ static int sdhci_at91_probe(struct platform_device 
> > *pdev)
> > if (ret)
> > goto clocks_disable_unprepare;
> >
> > +   pm_runtime_set_active(>dev);
> > +   pm_runtime_enable(>dev);
> > +   pm_runtime_set_autosuspend_delay(>dev, 50);
> > +   pm_runtime_use_autosuspend(>dev);
> 
> Move these four runtime PM calls above sdhci_add_host(), as after that
> point the host is used and thus runtime PM operations starts.

Sadly I have discovered a bit late it is not working when doing this
because the controller has been suspended before doing the
sdhci_add_host().

What is the right way to fix it? Calling pm_runtime_get_noresume()
before sdhci_add_host() and calling pm_runtime_put_autosuspend() after?

> 
> > +
> > return 0;
> >
> >  clocks_disable_unprepare:
> > @@ -165,6 +228,7 @@ static int sdhci_at91_remove(struct platform_device 
> > *pdev)
> > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> > struct sdhci_at91_priv  *priv = pltfm_host->priv;
> >

Regards

Ludovic
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Re: [PATCH v2] mmc: sdhci at91: add PM support

[Ludovic Desroches]

On Thu, Nov 26, 2015 at 05:24:40PM +0100, Ulf Hansson wrote:
> On 26 November 2015 at 17:07, Ludovic Desroches
> <ludovic.desroc...@atmel.com> wrote:
> > On Tue, Nov 10, 2015 at 12:12:30PM +0100, Ulf Hansson wrote:
> >> On 10 November 2015 at 11:36, Ludovic Desroches
> >> <ludovic.desroc...@atmel.com> wrote:
> >> > Add runtime PM support and use runtime_force_suspend|resume() for system
> >> > PM.
> >> >
> >
> > [...]
> >
> >> >  static int sdhci_at91_probe(struct platform_device *pdev)
> >> >  {
> >> > const struct of_device_id   *match;
> >> > @@ -148,6 +206,11 @@ static int sdhci_at91_probe(struct platform_device 
> >> > *pdev)
> >> > if (ret)
> >> > goto clocks_disable_unprepare;
> >> >
> >> > +   pm_runtime_set_active(>dev);
> >> > +   pm_runtime_enable(>dev);
> >> > +   pm_runtime_set_autosuspend_delay(>dev, 50);
> >> > +   pm_runtime_use_autosuspend(>dev);
> >>
> >> Move these four runtime PM calls above sdhci_add_host(), as after that
> >> point the host is used and thus runtime PM operations starts.
> >
> > Sadly I have discovered a bit late it is not working when doing this
> > because the controller has been suspended before doing the
> > sdhci_add_host().
> >
> > What is the right way to fix it? Calling pm_runtime_get_noresume()
> 
> I would do that before pm_runtime_enable().
> 
> > before sdhci_add_host() and calling pm_runtime_put_autosuspend() after?
> 
> Yes. Sorry for not spotting this before.

No problem, I am faulty too, it was not so trivial!

I am sending the fix. Thanks

Regards

Ludovic
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[PATCH] mmc: sdhci-of-at91: controller is suspended too early

[Ludovic Desroches]

When calling sdhci_add_host(), the controller is already suspended. It
causes to read 0 in registers.
Increment the device's usage counter before calling sdhci_add_host(),
decrement it after and put it in suspend if it is possible.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
Fixes: "mmc: sdhci-of-at91: add PM support"
---
 drivers/mmc/host/sdhci-of-at91.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
index 81ab9db..7e7d8f0 100644
--- a/drivers/mmc/host/sdhci-of-at91.c
+++ b/drivers/mmc/host/sdhci-of-at91.c
@@ -200,6 +200,7 @@ static int sdhci_at91_probe(struct platform_device *pdev)
 
sdhci_get_of_property(pdev);
 
+   pm_runtime_get_noresume(>dev);
pm_runtime_set_active(>dev);
pm_runtime_enable(>dev);
pm_runtime_set_autosuspend_delay(>dev, 50);
@@ -209,6 +210,8 @@ static int sdhci_at91_probe(struct platform_device *pdev)
if (ret)
goto pm_runtime_disable;
 
+   pm_runtime_put_autosuspend(>dev);
+
return 0;
 
 pm_runtime_disable:
-- 
2.5.0

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Re: [PATCH 1/2] mmc: sdhci: set bus voltage before enabling bus power

[Ludovic Desroches]

On Tue, Nov 24, 2015 at 02:56:21PM +0100, Ulf Hansson wrote:
> On 24 November 2015 at 14:12, Ludovic Desroches
>  wrote:
> > On Tue, Nov 24, 2015 at 12:01:53PM +0100, Ulf Hansson wrote:
> >> On 24 November 2015 at 10:23, Ludovic Desroches
> >>  wrote:
> >> > Hi Ulf,
> >> >
> >> > On Mon, Nov 09, 2015 at 05:30:26PM +0100, Ludovic Desroches wrote:
> >> >> On Mon, Nov 09, 2015 at 05:00:46PM +0100, Ulf Hansson wrote:
> >> >
> >> > [...]
> >> >
> >> >> > Now, this discussion was interesting, but I forgot what problem you
> >> >> > actually where trying to solve? :-)
> >> >>
> >> >> There is this discussion because of two things:
> >> >> - Fixing something I consider as a bug: when I have a VMMC, only
> >> >>   setting/clearing bit 0. Our controller strictly obeys to the spec and
> >> >>   check the 'SD Bus Voltage Select' field. Since we put a reserved value
> >> >>   (000), the Power On is not performed.
> >> >> - I was trying to get help to understand what is this 'SD Bus Voltage'.
> >> >>   For our controller and sdhci_set_power(), it seems to stand for VMMC.
> >> >>   For me, everything concerning bus voltage is related to VQMMC, so I 
> >> >> was
> >> >>   disappointed.
> >> >
> >> > Do you plan to take the patch for VMMC? If yes, I will send a new patch
> >> > for the device tree (I'll only add vmmc, not vqmmc as discussed); if
> >> > not, forget these two patches.
> >> >
> >>
> >> Which patch do you refer to for "VMMC"?
> >>
> >
> > This one to not write an invalid voltage in the power control register
> > even if we have an external regulator for vmmc.
> >
> 
> As I stated earlier, according to the SDHCI spec in the section for
> the Power Control Register. Bit 0 needs to be set when communicating
> with the card as it will for
> example enable the clock.
> 

I am okay with bit 0. I don't want to change this part, it will be done
later in sdhci_set_power(). My concern is only about bit 3-1, I want to
go through the switch statement.

> I suspect if I apply your patch several sdhci variants would break,
> don't you think?

I wouldn't sign it with my blood but I don't think so. It seems they
don't care about the SD bus Voltage since they work with an unsupported
voltage.

Regards

Ludovic
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[PATCH 2/3] i2c: at91: add DT property "atmel,twd-hold-cycles" to binding

[Ludovic Desroches]

From: Wenyou Yang 

Add a DT property "atmel,twd-hold-cycles" to specify the HOLD
filed of TWIHS_CWGR register to increase the TWD hold time.

Signed-off-by: Wenyou Yang 
Signed-off-by: Ludovic Desroches 
---
 Documentation/devicetree/bindings/i2c/i2c-at91.txt | 4 
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt 
b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
index 6e81dc1..c81a0cb 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
@@ -17,6 +17,9 @@ Optional properties:
 - dma-names: should contain "tx" and "rx".
 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for 
FIFO
   capable I2C controllers.
+- atmel,twd-hold-cycles: number of cycles for TWD hold time whose value is
+  determinated by (atmel,twd-hold-cycles + 3) x t_peripheral_clock,
+  maximum value is 0x1f.
 - Child nodes conforming to i2c bus binding
 
 Examples :
@@ -29,6 +32,7 @@ i2c0: i2c@fff84000 {
#size-cells = <0>;
clocks = <_clk>;
clock-frequency = <40>;
+   atmel,twd-hold-cycles = <2>;
 
24c512@50 {
compatible = "24c512";
-- 
2.5.0

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[PATCH 3/3] ARM: dts: at91: specify DT property "atmel,twd-hold-cycles"

[Ludovic Desroches]

From: Wenyou Yang 

Specify the device tree property "atmel,twd-hold-cycles" to 25
to adapt to the PMIC ACT8945A.

Signed-off-by: Wenyou Yang 
---
 arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index ad6de73..25ffd86 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -129,6 +129,7 @@
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <_i2c0_default>;
+   atmel,twd-hold-cycles = <25>;
status = "okay";
 
pmic: act8865@5b {
-- 
2.5.0

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[PATCH 1/3] i2c: at91: add setting HOLD field of TWIHS_CWGR via DT

[Ludovic Desroches]

From: Wenyou Yang 

Add the HOLD field management. Some i2c devices need a longer data hold
time than the one given in the i2c bus specification. Since this value
depends on the i2c device connected to the bus, add a DT property to
configure it: "atmel,twd-hold-cycles".

Signed-off-by: Wenyou Yang 
Signed-off-by: Ludovic Desroches 
---
 drivers/i2c/busses/i2c-at91.c | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 10835d1..b3595ea 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -64,6 +64,7 @@
 #defineAT91_TWI_IADR   0x000c  /* Internal Address Register */
 
 #defineAT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
*/
+#defineAT91_TWI_CWGR_HOLD(x)   (((x) & 0x1f) << 24)
 
 #defineAT91_TWI_SR 0x0020  /* Status Register */
 #defineAT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
@@ -185,7 +186,8 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  * Calculate symmetric clock as stated in datasheet:
  * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
  */
-static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
+static void at91_calc_twi_clock(struct at91_twi_dev *dev,
+   int twi_clk, u32 twd_hold)
 {
int ckdiv, cdiv, div;
struct at91_twi_pdata *pdata = dev->pdata;
@@ -204,7 +206,9 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, 
int twi_clk)
cdiv = 255;
}
 
-   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
+   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
+   | AT91_TWI_CWGR_HOLD(twd_hold);
+
dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
 }
 
@@ -994,6 +998,7 @@ static int at91_twi_probe(struct platform_device *pdev)
int rc;
u32 phy_addr;
u32 bus_clk_rate;
+   u32 twd_hold_cycles = 0;
 
dev = devm_kzalloc(>dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
@@ -1050,7 +1055,10 @@ static int at91_twi_probe(struct platform_device *pdev)
if (rc)
bus_clk_rate = DEFAULT_TWI_CLK_HZ;
 
-   at91_calc_twi_clock(dev, bus_clk_rate);
+   of_property_read_u32(dev->dev->of_node, "atmel,twd-hold-cycles",
+_hold_cycles);
+
+   at91_calc_twi_clock(dev, bus_clk_rate, twd_hold_cycles);
at91_init_twi_bus(dev);
 
snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
-- 
2.5.0

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Re: [PATCH 1/2] mmc: sdhci: set bus voltage before enabling bus power

[Ludovic Desroches]

On Tue, Nov 24, 2015 at 12:01:53PM +0100, Ulf Hansson wrote:
> On 24 November 2015 at 10:23, Ludovic Desroches
>  wrote:
> > Hi Ulf,
> >
> > On Mon, Nov 09, 2015 at 05:30:26PM +0100, Ludovic Desroches wrote:
> >> On Mon, Nov 09, 2015 at 05:00:46PM +0100, Ulf Hansson wrote:
> >
> > [...]
> >
> >> > Now, this discussion was interesting, but I forgot what problem you
> >> > actually where trying to solve? :-)
> >>
> >> There is this discussion because of two things:
> >> - Fixing something I consider as a bug: when I have a VMMC, only
> >>   setting/clearing bit 0. Our controller strictly obeys to the spec and
> >>   check the 'SD Bus Voltage Select' field. Since we put a reserved value
> >>   (000), the Power On is not performed.
> >> - I was trying to get help to understand what is this 'SD Bus Voltage'.
> >>   For our controller and sdhci_set_power(), it seems to stand for VMMC.
> >>   For me, everything concerning bus voltage is related to VQMMC, so I was
> >>   disappointed.
> >
> > Do you plan to take the patch for VMMC? If yes, I will send a new patch
> > for the device tree (I'll only add vmmc, not vqmmc as discussed); if
> > not, forget these two patches.
> >
> 
> Which patch do you refer to for "VMMC"?
> 

This one to not write an invalid voltage in the power control register
even if we have an external regulator for vmmc.

Regards

Ludovic
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[PATCH] dmaengine: at_xdmac: fix false condition for memset_sg transfers

[Ludovic Desroches]

The code was not in agreement with the comments.

Signed-off-by: Ludovic Desroches 
Cc: sta...@vger.kernel.org # 4.3 and later
---
 drivers/dma/at_xdmac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 7f039de..3b68471 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -1333,7 +1333,7 @@ at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct 
scatterlist *sgl,
 * since we don't care about the stride anymore.
 */
if ((i == (sg_len - 1)) &&
-   sg_dma_len(ppsg) == sg_dma_len(psg)) {
+   sg_dma_len(psg) == sg_dma_len(sg)) {
dev_dbg(chan2dev(chan),
"%s: desc 0x%p can be merged with desc 0x%p\n",
__func__, desc, pdesc);
-- 
2.5.0

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Re: [PATCH 1/2] mmc: sdhci: set bus voltage before enabling bus power

[Ludovic Desroches]

Hi Ulf,

On Mon, Nov 09, 2015 at 05:30:26PM +0100, Ludovic Desroches wrote:
> On Mon, Nov 09, 2015 at 05:00:46PM +0100, Ulf Hansson wrote:

[...]

> > Now, this discussion was interesting, but I forgot what problem you
> > actually where trying to solve? :-)
> 
> There is this discussion because of two things:
> - Fixing something I consider as a bug: when I have a VMMC, only
>   setting/clearing bit 0. Our controller strictly obeys to the spec and
>   check the 'SD Bus Voltage Select' field. Since we put a reserved value
>   (000), the Power On is not performed.
> - I was trying to get help to understand what is this 'SD Bus Voltage'.
>   For our controller and sdhci_set_power(), it seems to stand for VMMC.
>   For me, everything concerning bus voltage is related to VQMMC, so I was
>   disappointed.

Do you plan to take the patch for VMMC? If yes, I will send a new patch
for the device tree (I'll only add vmmc, not vqmmc as discussed); if
not, forget these two patches.

Regards

Ludovic
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Re: [PATCH 1/2] mmc: sdhci: set bus voltage before enabling bus power

[Ludovic Desroches]

Hi Ulf,

On Mon, Nov 09, 2015 at 05:30:26PM +0100, Ludovic Desroches wrote:
> On Mon, Nov 09, 2015 at 05:00:46PM +0100, Ulf Hansson wrote:

[...]

> > Now, this discussion was interesting, but I forgot what problem you
> > actually where trying to solve? :-)
> 
> There is this discussion because of two things:
> - Fixing something I consider as a bug: when I have a VMMC, only
>   setting/clearing bit 0. Our controller strictly obeys to the spec and
>   check the 'SD Bus Voltage Select' field. Since we put a reserved value
>   (000), the Power On is not performed.
> - I was trying to get help to understand what is this 'SD Bus Voltage'.
>   For our controller and sdhci_set_power(), it seems to stand for VMMC.
>   For me, everything concerning bus voltage is related to VQMMC, so I was
>   disappointed.

Do you plan to take the patch for VMMC? If yes, I will send a new patch
for the device tree (I'll only add vmmc, not vqmmc as discussed); if
not, forget these two patches.

Regards

Ludovic
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[PATCH] dmaengine: at_xdmac: fix false condition for memset_sg transfers

[Ludovic Desroches]

The code was not in agreement with the comments.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
Cc: sta...@vger.kernel.org # 4.3 and later
---
 drivers/dma/at_xdmac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 7f039de..3b68471 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -1333,7 +1333,7 @@ at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct 
scatterlist *sgl,
 * since we don't care about the stride anymore.
 */
if ((i == (sg_len - 1)) &&
-   sg_dma_len(ppsg) == sg_dma_len(psg)) {
+   sg_dma_len(psg) == sg_dma_len(sg)) {
dev_dbg(chan2dev(chan),
"%s: desc 0x%p can be merged with desc 0x%p\n",
__func__, desc, pdesc);
-- 
2.5.0

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Re: [PATCH 1/2] mmc: sdhci: set bus voltage before enabling bus power

[Ludovic Desroches]

On Tue, Nov 24, 2015 at 02:56:21PM +0100, Ulf Hansson wrote:
> On 24 November 2015 at 14:12, Ludovic Desroches
> <ludovic.desroc...@atmel.com> wrote:
> > On Tue, Nov 24, 2015 at 12:01:53PM +0100, Ulf Hansson wrote:
> >> On 24 November 2015 at 10:23, Ludovic Desroches
> >> <ludovic.desroc...@atmel.com> wrote:
> >> > Hi Ulf,
> >> >
> >> > On Mon, Nov 09, 2015 at 05:30:26PM +0100, Ludovic Desroches wrote:
> >> >> On Mon, Nov 09, 2015 at 05:00:46PM +0100, Ulf Hansson wrote:
> >> >
> >> > [...]
> >> >
> >> >> > Now, this discussion was interesting, but I forgot what problem you
> >> >> > actually where trying to solve? :-)
> >> >>
> >> >> There is this discussion because of two things:
> >> >> - Fixing something I consider as a bug: when I have a VMMC, only
> >> >>   setting/clearing bit 0. Our controller strictly obeys to the spec and
> >> >>   check the 'SD Bus Voltage Select' field. Since we put a reserved value
> >> >>   (000), the Power On is not performed.
> >> >> - I was trying to get help to understand what is this 'SD Bus Voltage'.
> >> >>   For our controller and sdhci_set_power(), it seems to stand for VMMC.
> >> >>   For me, everything concerning bus voltage is related to VQMMC, so I 
> >> >> was
> >> >>   disappointed.
> >> >
> >> > Do you plan to take the patch for VMMC? If yes, I will send a new patch
> >> > for the device tree (I'll only add vmmc, not vqmmc as discussed); if
> >> > not, forget these two patches.
> >> >
> >>
> >> Which patch do you refer to for "VMMC"?
> >>
> >
> > This one to not write an invalid voltage in the power control register
> > even if we have an external regulator for vmmc.
> >
> 
> As I stated earlier, according to the SDHCI spec in the section for
> the Power Control Register. Bit 0 needs to be set when communicating
> with the card as it will for
> example enable the clock.
> 

I am okay with bit 0. I don't want to change this part, it will be done
later in sdhci_set_power(). My concern is only about bit 3-1, I want to
go through the switch statement.

> I suspect if I apply your patch several sdhci variants would break,
> don't you think?

I wouldn't sign it with my blood but I don't think so. It seems they
don't care about the SD bus Voltage since they work with an unsupported
voltage.

Regards

Ludovic
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Re: [PATCH 1/2] mmc: sdhci: set bus voltage before enabling bus power

[Ludovic Desroches]

On Tue, Nov 24, 2015 at 12:01:53PM +0100, Ulf Hansson wrote:
> On 24 November 2015 at 10:23, Ludovic Desroches
> <ludovic.desroc...@atmel.com> wrote:
> > Hi Ulf,
> >
> > On Mon, Nov 09, 2015 at 05:30:26PM +0100, Ludovic Desroches wrote:
> >> On Mon, Nov 09, 2015 at 05:00:46PM +0100, Ulf Hansson wrote:
> >
> > [...]
> >
> >> > Now, this discussion was interesting, but I forgot what problem you
> >> > actually where trying to solve? :-)
> >>
> >> There is this discussion because of two things:
> >> - Fixing something I consider as a bug: when I have a VMMC, only
> >>   setting/clearing bit 0. Our controller strictly obeys to the spec and
> >>   check the 'SD Bus Voltage Select' field. Since we put a reserved value
> >>   (000), the Power On is not performed.
> >> - I was trying to get help to understand what is this 'SD Bus Voltage'.
> >>   For our controller and sdhci_set_power(), it seems to stand for VMMC.
> >>   For me, everything concerning bus voltage is related to VQMMC, so I was
> >>   disappointed.
> >
> > Do you plan to take the patch for VMMC? If yes, I will send a new patch
> > for the device tree (I'll only add vmmc, not vqmmc as discussed); if
> > not, forget these two patches.
> >
> 
> Which patch do you refer to for "VMMC"?
> 

This one to not write an invalid voltage in the power control register
even if we have an external regulator for vmmc.

Regards

Ludovic
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[PATCH 2/3] i2c: at91: add DT property "atmel,twd-hold-cycles" to binding

[Ludovic Desroches]

From: Wenyou Yang <wenyou.y...@atmel.com>

Add a DT property "atmel,twd-hold-cycles" to specify the HOLD
filed of TWIHS_CWGR register to increase the TWD hold time.

Signed-off-by: Wenyou Yang <wenyou.y...@atmel.com>
Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 Documentation/devicetree/bindings/i2c/i2c-at91.txt | 4 
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt 
b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
index 6e81dc1..c81a0cb 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
@@ -17,6 +17,9 @@ Optional properties:
 - dma-names: should contain "tx" and "rx".
 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for 
FIFO
   capable I2C controllers.
+- atmel,twd-hold-cycles: number of cycles for TWD hold time whose value is
+  determinated by (atmel,twd-hold-cycles + 3) x t_peripheral_clock,
+  maximum value is 0x1f.
 - Child nodes conforming to i2c bus binding
 
 Examples :
@@ -29,6 +32,7 @@ i2c0: i2c@fff84000 {
#size-cells = <0>;
clocks = <_clk>;
clock-frequency = <40>;
+   atmel,twd-hold-cycles = <2>;
 
24c512@50 {
compatible = "24c512";
-- 
2.5.0

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[PATCH 1/3] i2c: at91: add setting HOLD field of TWIHS_CWGR via DT

[Ludovic Desroches]

From: Wenyou Yang <wenyou.y...@atmel.com>

Add the HOLD field management. Some i2c devices need a longer data hold
time than the one given in the i2c bus specification. Since this value
depends on the i2c device connected to the bus, add a DT property to
configure it: "atmel,twd-hold-cycles".

Signed-off-by: Wenyou Yang <wenyou.y...@atmel.com>
Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 drivers/i2c/busses/i2c-at91.c | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 10835d1..b3595ea 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -64,6 +64,7 @@
 #defineAT91_TWI_IADR   0x000c  /* Internal Address Register */
 
 #defineAT91_TWI_CWGR   0x0010  /* Clock Waveform Generator Reg 
*/
+#defineAT91_TWI_CWGR_HOLD(x)   (((x) & 0x1f) << 24)
 
 #defineAT91_TWI_SR 0x0020  /* Status Register */
 #defineAT91_TWI_TXCOMP BIT(0)  /* Transmission Complete */
@@ -185,7 +186,8 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  * Calculate symmetric clock as stated in datasheet:
  * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
  */
-static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
+static void at91_calc_twi_clock(struct at91_twi_dev *dev,
+   int twi_clk, u32 twd_hold)
 {
int ckdiv, cdiv, div;
struct at91_twi_pdata *pdata = dev->pdata;
@@ -204,7 +206,9 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, 
int twi_clk)
cdiv = 255;
}
 
-   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
+   dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
+   | AT91_TWI_CWGR_HOLD(twd_hold);
+
dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
 }
 
@@ -994,6 +998,7 @@ static int at91_twi_probe(struct platform_device *pdev)
int rc;
u32 phy_addr;
u32 bus_clk_rate;
+   u32 twd_hold_cycles = 0;
 
dev = devm_kzalloc(>dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
@@ -1050,7 +1055,10 @@ static int at91_twi_probe(struct platform_device *pdev)
if (rc)
bus_clk_rate = DEFAULT_TWI_CLK_HZ;
 
-   at91_calc_twi_clock(dev, bus_clk_rate);
+   of_property_read_u32(dev->dev->of_node, "atmel,twd-hold-cycles",
+_hold_cycles);
+
+   at91_calc_twi_clock(dev, bus_clk_rate, twd_hold_cycles);
at91_init_twi_bus(dev);
 
snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
-- 
2.5.0

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[PATCH 3/3] ARM: dts: at91: specify DT property "atmel,twd-hold-cycles"

[Ludovic Desroches]

From: Wenyou Yang 

Specify the device tree property "atmel,twd-hold-cycles" to 25
to adapt to the PMIC ACT8945A.

Signed-off-by: Wenyou Yang 
---
 arch/arm/boot/dts/at91-sama5d2_xplained.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts 
b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index ad6de73..25ffd86 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -129,6 +129,7 @@
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <_i2c0_default>;
+   atmel,twd-hold-cycles = <25>;
status = "okay";
 
pmic: act8865@5b {
-- 
2.5.0

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[PATCH 3/3] mmc: atmel-mci: atmci_convert_chksize depends on controller version

[Ludovic Desroches]

The atmci_convert_chksize() function is no more valid for controller
version 0x600 due to the introduction of '2 data' chunk size.

Signed-off-by: Ludovic Desroches 
---
 drivers/mmc/host/atmel-mci.c | 43 +++
 1 file changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index 9f3bb61..a36ebda 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -180,20 +180,6 @@
 #  define ATMCI_PDC_CONNECTED  1
 #endif
 
-/*
- * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
- * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
- *
- * This can be done by finding most significant bit set.
- */
-static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
-{
-   if (maxburst > 1)
-   return fls(maxburst) - 2;
-   else
-   return 0;
-}
-
 #define AUTOSUSPEND_DELAY  50
 
 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | 
ATMCI_UNRE)
@@ -732,6 +718,29 @@ static inline unsigned int atmci_get_version(struct 
atmel_mci *host)
return atmci_readl(host, ATMCI_VERSION) & 0x0fff;
 }
 
+/*
+ * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
+ * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
+ * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
+ * 8 -> 3, 16 -> 4.
+ *
+ * This can be done by finding most significant bit set.
+ */
+static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
+unsigned int maxburst)
+{
+   unsigned int version = atmci_get_version(host);
+   unsigned int offset = 2;
+
+   if (version >= 0x600)
+   offset = 1;
+
+   if (maxburst > 1)
+   return fls(maxburst) - offset;
+   else
+   return 0;
+}
+
 static void atmci_timeout_timer(unsigned long data)
 {
struct atmel_mci *host;
@@ -1182,11 +1191,13 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct 
mmc_data *data)
if (data->flags & MMC_DATA_READ) {
direction = DMA_FROM_DEVICE;
host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
-   maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
+   maxburst = atmci_convert_chksize(host,
+host->dma_conf.src_maxburst);
} else {
direction = DMA_TO_DEVICE;
host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
-   maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
+   maxburst = atmci_convert_chksize(host,
+host->dma_conf.dst_maxburst);
}
 
if (host->caps.has_dma_conf_reg)
-- 
2.5.0

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[PATCH 2/3] MAINTAINERS: remove atmel-mci-regs.h file

[Ludovic Desroches]

Remove atmel-mci-regs.h file since it has been merged in atmel-mci.c.

Signed-off-by: Ludovic Desroches 
---
 MAINTAINERS | 1 -
 1 file changed, 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b2ab9fc..1df3df3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1904,7 +1904,6 @@ ATMEL AT91 / AT32 MCI DRIVER
 M: Ludovic Desroches 
 S: Maintained
 F: drivers/mmc/host/atmel-mci.c
-F: drivers/mmc/host/atmel-mci-regs.h
 
 ATMEL AT91 / AT32 SERIAL DRIVER
 M: Nicolas Ferre 
-- 
2.5.0

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[PATCH 1/3] mmc: atmel-mci: move atmel-mci-regs.h content in atmel-mci.c

[Ludovic Desroches]

atmel-mci-regs.h is only included in atmel-mci.c so move its content in
the driver and do some cleanup in these definitions to remove checkpatch
errors.

Signed-off-by: Ludovic Desroches 
---
 drivers/mmc/host/atmel-mci-regs.h | 171 --
 drivers/mmc/host/atmel-mci.c  | 150 -
 2 files changed, 149 insertions(+), 172 deletions(-)
 delete mode 100644 drivers/mmc/host/atmel-mci-regs.h

diff --git a/drivers/mmc/host/atmel-mci-regs.h 
b/drivers/mmc/host/atmel-mci-regs.h
deleted file mode 100644
index 0aa44e6..000
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Atmel MultiMedia Card Interface driver
- *
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/*
- * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
- * Registers and bitfields marked with [2] are only available in MCI2
- */
-
-#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
-#define __DRIVERS_MMC_ATMEL_MCI_H__
-
-/* MCI Register Definitions */
-#define ATMCI_CR   0x  /* Control */
-# define ATMCI_CR_MCIEN(  1 <<  0) /* MCI Enable */
-# define ATMCI_CR_MCIDIS   (  1 <<  1) /* MCI Disable */
-# define ATMCI_CR_PWSEN(  1 <<  2) /* Power Save 
Enable */
-# define ATMCI_CR_PWSDIS   (  1 <<  3) /* Power Save Disable */
-# define ATMCI_CR_SWRST(  1 <<  7) /* Software 
Reset */
-#define ATMCI_MR   0x0004  /* Mode */
-# define ATMCI_MR_CLKDIV(x)((x) <<  0) /* Clock Divider */
-# define ATMCI_MR_PWSDIV(x)((x) <<  8) /* Power Saving Divider 
*/
-# define ATMCI_MR_RDPROOF  (  1 << 11) /* Read Proof */
-# define ATMCI_MR_WRPROOF  (  1 << 12) /* Write Proof */
-# define ATMCI_MR_PDCFBYTE (  1 << 13) /* Force Byte Transfer 
*/
-# define ATMCI_MR_PDCPADV  (  1 << 14) /* Padding Value */
-# define ATMCI_MR_PDCMODE  (  1 << 15) /* PDC-oriented Mode */
-# define ATMCI_MR_CLKODD(x)((x) << 16) /* LSB of Clock Divider 
*/
-#define ATMCI_DTOR 0x0008  /* Data Timeout */
-# define ATMCI_DTOCYC(x)   ((x) <<  0) /* Data Timeout Cycles 
*/
-# define ATMCI_DTOMUL(x)   ((x) <<  4) /* Data Timeout 
Multiplier */
-#define ATMCI_SDCR 0x000c  /* SD Card / SDIO */
-# define ATMCI_SDCSEL_SLOT_A   (  0 <<  0) /* Select SD slot A */
-# define ATMCI_SDCSEL_SLOT_B   (  1 <<  0) /* Select SD slot A */
-# define ATMCI_SDCSEL_MASK (  3 <<  0)
-# define ATMCI_SDCBUS_1BIT (  0 <<  6) /* 1-bit data bus */
-# define ATMCI_SDCBUS_4BIT (  2 <<  6) /* 4-bit data bus */
-# define ATMCI_SDCBUS_8BIT (  3 <<  6) /* 8-bit data bus[2] */
-# define ATMCI_SDCBUS_MASK (  3 <<  6)
-#define ATMCI_ARGR 0x0010  /* Command Argument */
-#define ATMCI_CMDR 0x0014  /* Command */
-# define ATMCI_CMDR_CMDNB(x)   ((x) <<  0) /* Command Opcode */
-# define ATMCI_CMDR_RSPTYP_NONE(  0 <<  6) /* No response 
*/
-# define ATMCI_CMDR_RSPTYP_48BIT   (  1 <<  6) /* 48-bit response */
-# define ATMCI_CMDR_RSPTYP_136BIT  (  2 <<  6) /* 136-bit response */
-# define ATMCI_CMDR_SPCMD_INIT (  1 <<  8) /* Initialization 
command */
-# define ATMCI_CMDR_SPCMD_SYNC (  2 <<  8) /* Synchronized command 
*/
-# define ATMCI_CMDR_SPCMD_INT  (  4 <<  8) /* Interrupt command */
-# define ATMCI_CMDR_SPCMD_INTRESP  (  5 <<  8) /* Interrupt response */
-# define ATMCI_CMDR_OPDCMD (  1 << 11) /* Open Drain */
-# define ATMCI_CMDR_MAXLAT_5CYC(  0 << 12) /* Max latency 
5 cycles */
-# define ATMCI_CMDR_MAXLAT_64CYC   (  1 << 12) /* Max latency 64 
cycles */
-# define ATMCI_CMDR_START_XFER (  1 << 16) /* Start data transfer 
*/
-# define ATMCI_CMDR_STOP_XFER  (  2 << 16) /* Stop data transfer */
-# define ATMCI_CMDR_TRDIR_WRITE(  0 << 18) /* Write data */
-# define ATMCI_CMDR_TRDIR_READ (  1 << 18) /* Read data */
-# define ATMCI_CMDR_BLOCK  (  0 << 19) /* Single-block 
transfer */
-# define ATMCI_CMDR_MULTI_BLOCK(  1 << 19) /* Multi-block 
transfer */
-# define ATMCI_CMDR_STREAM (  2 &

[PATCH 2/2] dmaengine: at_xdmac: fix spurious flag status for mem2mem transfers

[Ludovic Desroches]

When setting the channel configuration register, the perid field is not
set to 0 since it is useless for mem2mem transfers. Unfortunately, a
device has 0 as perid. It could cause spurious flags status because
the controller could mix some events from the two channels.
For that reason, use the highest perid value for mem2mem transfers since it
doesn't match the perid of other devices.

Signed-off-by: Ludovic Desroches 
---
 drivers/dma/at_xdmac.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index d09277f..b90e62f 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -863,8 +863,12 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
 * access. Hopefully we can access DDR through both ports (at least on
 * SAMA5D4x), so we can use the same interface for source and dest,
 * that solves the fact we don't know the direction.
+* ERRATA: Even if useless for memory transfers, the PERID has to not
+* match the one of another channel. If not, it could lead to spurious
+* flag status.
 */
-   u32 chan_cc = AT_XDMAC_CC_DIF(0)
+   u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
+   | AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0)
| AT_XDMAC_CC_MBSIZE_SIXTEEN
| AT_XDMAC_CC_TYPE_MEM_TRAN;
@@ -1039,8 +1043,12 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, 
dma_addr_t dest, dma_addr_t src,
 * access DDR through both ports (at least on SAMA5D4x), so we can use
 * the same interface for source and dest, that solves the fact we
 * don't know the direction.
+* ERRATA: Even if useless for memory transfers, the PERID has to not
+* match the one of another channel. If not, it could lead to spurious
+* flag status.
 */
-   u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
+   u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
+   | AT_XDMAC_CC_DAM_INCREMENTED_AM
| AT_XDMAC_CC_SAM_INCREMENTED_AM
| AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0)
@@ -1140,8 +1148,12 @@ static struct at_xdmac_desc 
*at_xdmac_memset_create_desc(struct dma_chan *chan,
 * access. Hopefully we can access DDR through both ports (at least on
 * SAMA5D4x), so we can use the same interface for source and dest,
 * that solves the fact we don't know the direction.
+* ERRATA: Even if useless for memory transfers, the PERID has to not
+* match the one of another channel. If not, it could lead to spurious
+* flag status.
 */
-   u32 chan_cc = AT_XDMAC_CC_DAM_UBS_AM
+   u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
+   | AT_XDMAC_CC_DAM_UBS_AM
| AT_XDMAC_CC_SAM_INCREMENTED_AM
| AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0)
-- 
2.5.0

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[PATCH 1/2] dmaengine: at_xdmac: fix macro typo

[Ludovic Desroches]

Fix typo in a macro which was not used until now. It explains why there
is no error at compilation time.

Signed-off-by: Ludovic Desroches 
Fixes: e1f7c9eee707 "dmaengine: at_xdmac: creation of the atmel eXtended
DMA Controller driver"
Cc: sta...@vger.kernel.org # 3.19 and later
---
 drivers/dma/at_xdmac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 7f039de..d09277f 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -156,7 +156,7 @@
 #defineAT_XDMAC_CC_WRIP(0x1 << 23) /* Write in 
Progress (read only) */
 #defineAT_XDMAC_CC_WRIP_DONE   (0x0 << 23)
 #defineAT_XDMAC_CC_WRIP_IN_PROGRESS(0x1 << 23)
-#defineAT_XDMAC_CC_PERID(i)(0x7f & (h) << 24)  /* 
Channel Peripheral Identifier */
+#defineAT_XDMAC_CC_PERID(i)(0x7f & (i) << 24)  /* 
Channel Peripheral Identifier */
 #define AT_XDMAC_CDS_MSP   0x2C/* Channel Data Stride Memory Set 
Pattern */
 #define AT_XDMAC_CSUS  0x30/* Channel Source Microblock Stride */
 #define AT_XDMAC_CDUS  0x34/* Channel Destination Microblock 
Stride */
-- 
2.5.0

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[PATCH 2/2] dmaengine: at_xdmac: fix spurious flag status for mem2mem transfers

[Ludovic Desroches]

When setting the channel configuration register, the perid field is not
set to 0 since it is useless for mem2mem transfers. Unfortunately, a
device has 0 as perid. It could cause spurious flags status because
the controller could mix some events from the two channels.
For that reason, use the highest perid value for mem2mem transfers since it
doesn't match the perid of other devices.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 drivers/dma/at_xdmac.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index d09277f..b90e62f 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -863,8 +863,12 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
 * access. Hopefully we can access DDR through both ports (at least on
 * SAMA5D4x), so we can use the same interface for source and dest,
 * that solves the fact we don't know the direction.
+* ERRATA: Even if useless for memory transfers, the PERID has to not
+* match the one of another channel. If not, it could lead to spurious
+* flag status.
 */
-   u32 chan_cc = AT_XDMAC_CC_DIF(0)
+   u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
+   | AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0)
| AT_XDMAC_CC_MBSIZE_SIXTEEN
| AT_XDMAC_CC_TYPE_MEM_TRAN;
@@ -1039,8 +1043,12 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, 
dma_addr_t dest, dma_addr_t src,
 * access DDR through both ports (at least on SAMA5D4x), so we can use
 * the same interface for source and dest, that solves the fact we
 * don't know the direction.
+* ERRATA: Even if useless for memory transfers, the PERID has to not
+* match the one of another channel. If not, it could lead to spurious
+* flag status.
 */
-   u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
+   u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
+   | AT_XDMAC_CC_DAM_INCREMENTED_AM
| AT_XDMAC_CC_SAM_INCREMENTED_AM
| AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0)
@@ -1140,8 +1148,12 @@ static struct at_xdmac_desc 
*at_xdmac_memset_create_desc(struct dma_chan *chan,
 * access. Hopefully we can access DDR through both ports (at least on
 * SAMA5D4x), so we can use the same interface for source and dest,
 * that solves the fact we don't know the direction.
+* ERRATA: Even if useless for memory transfers, the PERID has to not
+* match the one of another channel. If not, it could lead to spurious
+* flag status.
 */
-   u32 chan_cc = AT_XDMAC_CC_DAM_UBS_AM
+   u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
+   | AT_XDMAC_CC_DAM_UBS_AM
| AT_XDMAC_CC_SAM_INCREMENTED_AM
| AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0)
-- 
2.5.0

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[PATCH 1/2] dmaengine: at_xdmac: fix macro typo

[Ludovic Desroches]

Fix typo in a macro which was not used until now. It explains why there
is no error at compilation time.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
Fixes: e1f7c9eee707 "dmaengine: at_xdmac: creation of the atmel eXtended
DMA Controller driver"
Cc: sta...@vger.kernel.org # 3.19 and later
---
 drivers/dma/at_xdmac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 7f039de..d09277f 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -156,7 +156,7 @@
 #defineAT_XDMAC_CC_WRIP(0x1 << 23) /* Write in 
Progress (read only) */
 #defineAT_XDMAC_CC_WRIP_DONE   (0x0 << 23)
 #defineAT_XDMAC_CC_WRIP_IN_PROGRESS(0x1 << 23)
-#defineAT_XDMAC_CC_PERID(i)(0x7f & (h) << 24)  /* 
Channel Peripheral Identifier */
+#defineAT_XDMAC_CC_PERID(i)(0x7f & (i) << 24)  /* 
Channel Peripheral Identifier */
 #define AT_XDMAC_CDS_MSP   0x2C/* Channel Data Stride Memory Set 
Pattern */
 #define AT_XDMAC_CSUS  0x30/* Channel Source Microblock Stride */
 #define AT_XDMAC_CDUS  0x34/* Channel Destination Microblock 
Stride */
-- 
2.5.0

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[PATCH 1/3] mmc: atmel-mci: move atmel-mci-regs.h content in atmel-mci.c

[Ludovic Desroches]

atmel-mci-regs.h is only included in atmel-mci.c so move its content in
the driver and do some cleanup in these definitions to remove checkpatch
errors.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 drivers/mmc/host/atmel-mci-regs.h | 171 --
 drivers/mmc/host/atmel-mci.c  | 150 -
 2 files changed, 149 insertions(+), 172 deletions(-)
 delete mode 100644 drivers/mmc/host/atmel-mci-regs.h

diff --git a/drivers/mmc/host/atmel-mci-regs.h 
b/drivers/mmc/host/atmel-mci-regs.h
deleted file mode 100644
index 0aa44e6..000
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Atmel MultiMedia Card Interface driver
- *
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/*
- * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
- * Registers and bitfields marked with [2] are only available in MCI2
- */
-
-#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
-#define __DRIVERS_MMC_ATMEL_MCI_H__
-
-/* MCI Register Definitions */
-#define ATMCI_CR   0x  /* Control */
-# define ATMCI_CR_MCIEN(  1 <<  0) /* MCI Enable */
-# define ATMCI_CR_MCIDIS   (  1 <<  1) /* MCI Disable */
-# define ATMCI_CR_PWSEN(  1 <<  2) /* Power Save 
Enable */
-# define ATMCI_CR_PWSDIS   (  1 <<  3) /* Power Save Disable */
-# define ATMCI_CR_SWRST(  1 <<  7) /* Software 
Reset */
-#define ATMCI_MR   0x0004  /* Mode */
-# define ATMCI_MR_CLKDIV(x)((x) <<  0) /* Clock Divider */
-# define ATMCI_MR_PWSDIV(x)((x) <<  8) /* Power Saving Divider 
*/
-# define ATMCI_MR_RDPROOF  (  1 << 11) /* Read Proof */
-# define ATMCI_MR_WRPROOF  (  1 << 12) /* Write Proof */
-# define ATMCI_MR_PDCFBYTE (  1 << 13) /* Force Byte Transfer 
*/
-# define ATMCI_MR_PDCPADV  (  1 << 14) /* Padding Value */
-# define ATMCI_MR_PDCMODE  (  1 << 15) /* PDC-oriented Mode */
-# define ATMCI_MR_CLKODD(x)((x) << 16) /* LSB of Clock Divider 
*/
-#define ATMCI_DTOR 0x0008  /* Data Timeout */
-# define ATMCI_DTOCYC(x)   ((x) <<  0) /* Data Timeout Cycles 
*/
-# define ATMCI_DTOMUL(x)   ((x) <<  4) /* Data Timeout 
Multiplier */
-#define ATMCI_SDCR 0x000c  /* SD Card / SDIO */
-# define ATMCI_SDCSEL_SLOT_A   (  0 <<  0) /* Select SD slot A */
-# define ATMCI_SDCSEL_SLOT_B   (  1 <<  0) /* Select SD slot A */
-# define ATMCI_SDCSEL_MASK (  3 <<  0)
-# define ATMCI_SDCBUS_1BIT (  0 <<  6) /* 1-bit data bus */
-# define ATMCI_SDCBUS_4BIT (  2 <<  6) /* 4-bit data bus */
-# define ATMCI_SDCBUS_8BIT (  3 <<  6) /* 8-bit data bus[2] */
-# define ATMCI_SDCBUS_MASK (  3 <<  6)
-#define ATMCI_ARGR 0x0010  /* Command Argument */
-#define ATMCI_CMDR 0x0014  /* Command */
-# define ATMCI_CMDR_CMDNB(x)   ((x) <<  0) /* Command Opcode */
-# define ATMCI_CMDR_RSPTYP_NONE(  0 <<  6) /* No response 
*/
-# define ATMCI_CMDR_RSPTYP_48BIT   (  1 <<  6) /* 48-bit response */
-# define ATMCI_CMDR_RSPTYP_136BIT  (  2 <<  6) /* 136-bit response */
-# define ATMCI_CMDR_SPCMD_INIT (  1 <<  8) /* Initialization 
command */
-# define ATMCI_CMDR_SPCMD_SYNC (  2 <<  8) /* Synchronized command 
*/
-# define ATMCI_CMDR_SPCMD_INT  (  4 <<  8) /* Interrupt command */
-# define ATMCI_CMDR_SPCMD_INTRESP  (  5 <<  8) /* Interrupt response */
-# define ATMCI_CMDR_OPDCMD (  1 << 11) /* Open Drain */
-# define ATMCI_CMDR_MAXLAT_5CYC(  0 << 12) /* Max latency 
5 cycles */
-# define ATMCI_CMDR_MAXLAT_64CYC   (  1 << 12) /* Max latency 64 
cycles */
-# define ATMCI_CMDR_START_XFER (  1 << 16) /* Start data transfer 
*/
-# define ATMCI_CMDR_STOP_XFER  (  2 << 16) /* Stop data transfer */
-# define ATMCI_CMDR_TRDIR_WRITE(  0 << 18) /* Write data */
-# define ATMCI_CMDR_TRDIR_READ (  1 << 18) /* Read data */
-# define ATMCI_CMDR_BLOCK  (  0 << 19) /* Single-block 
transfer */
-# define ATMCI_CMDR_MULTI_BLOCK(  1 << 19) /* Multi-block 
transfer */
-#

[PATCH 3/3] mmc: atmel-mci: atmci_convert_chksize depends on controller version

[Ludovic Desroches]

The atmci_convert_chksize() function is no more valid for controller
version 0x600 due to the introduction of '2 data' chunk size.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 drivers/mmc/host/atmel-mci.c | 43 +++
 1 file changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index 9f3bb61..a36ebda 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -180,20 +180,6 @@
 #  define ATMCI_PDC_CONNECTED  1
 #endif
 
-/*
- * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
- * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
- *
- * This can be done by finding most significant bit set.
- */
-static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
-{
-   if (maxburst > 1)
-   return fls(maxburst) - 2;
-   else
-   return 0;
-}
-
 #define AUTOSUSPEND_DELAY  50
 
 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | 
ATMCI_UNRE)
@@ -732,6 +718,29 @@ static inline unsigned int atmci_get_version(struct 
atmel_mci *host)
return atmci_readl(host, ATMCI_VERSION) & 0x0fff;
 }
 
+/*
+ * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
+ * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
+ * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
+ * 8 -> 3, 16 -> 4.
+ *
+ * This can be done by finding most significant bit set.
+ */
+static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
+unsigned int maxburst)
+{
+   unsigned int version = atmci_get_version(host);
+   unsigned int offset = 2;
+
+   if (version >= 0x600)
+   offset = 1;
+
+   if (maxburst > 1)
+   return fls(maxburst) - offset;
+   else
+   return 0;
+}
+
 static void atmci_timeout_timer(unsigned long data)
 {
struct atmel_mci *host;
@@ -1182,11 +1191,13 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct 
mmc_data *data)
if (data->flags & MMC_DATA_READ) {
direction = DMA_FROM_DEVICE;
host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
-   maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
+   maxburst = atmci_convert_chksize(host,
+host->dma_conf.src_maxburst);
} else {
direction = DMA_TO_DEVICE;
host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
-   maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
+   maxburst = atmci_convert_chksize(host,
+host->dma_conf.dst_maxburst);
}
 
if (host->caps.has_dma_conf_reg)
-- 
2.5.0

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[PATCH 2/3] MAINTAINERS: remove atmel-mci-regs.h file

[Ludovic Desroches]

Remove atmel-mci-regs.h file since it has been merged in atmel-mci.c.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---
 MAINTAINERS | 1 -
 1 file changed, 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b2ab9fc..1df3df3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1904,7 +1904,6 @@ ATMEL AT91 / AT32 MCI DRIVER
 M: Ludovic Desroches <ludovic.desroc...@atmel.com>
 S: Maintained
 F: drivers/mmc/host/atmel-mci.c
-F: drivers/mmc/host/atmel-mci-regs.h
 
 ATMEL AT91 / AT32 SERIAL DRIVER
 M: Nicolas Ferre <nicolas.fe...@atmel.com>
-- 
2.5.0

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Re: [PATCH v2] pinctrl: at91-pio4: use %pr format string for resource

[Ludovic Desroches]

On Wed, Nov 18, 2015 at 04:21:17PM +0100, Arnd Bergmann wrote:
> resource_size_t may be defined as 32 or 64 bit depending on configuration,
> so it cannot be printed using the normal format strings, as gcc correctly
> warns:
> 
> pinctrl-at91-pio4.c: In function 'atmel_pinctrl_probe':
> pinctrl-at91-pio4.c:1003:41: warning: format '%u' expects argument of type 
> 'unsigned int', but argument 5 has type 'resource_size_t {aka long long 
> unsigned int}' [-Wformat=]
>dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
> 
> This changes the format string to use the special "%pr" format
> string that prints a resource, and changes the arguments so we
> the resource structure directly.
> 
> Signed-off-by: Arnd Bergmann 
Acked-by: Ludovic Desroches 

Thanks.

> ---
> v2: don't break ordering of arguments, that part was correct already, unlike
> what I said in v1.
> 
> diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c 
> b/drivers/pinctrl/pinctrl-at91-pio4.c
> index 33edd07d9149..abdc16e5a970 100644
> --- a/drivers/pinctrl/pinctrl-at91-pio4.c
> +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
> @@ -1000,7 +1000,7 @@ static int atmel_pinctrl_probe(struct platform_device 
> *pdev)
>   atmel_pioctrl->irqs[i] = res->start;
>   irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
>   irq_set_handler_data(res->start, atmel_pioctrl);
> - dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
> + dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
>   }
>  
>   atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
> 
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Re: [PATCH v2] pinctrl: at91-pio4: use %pr format string for resource

[Ludovic Desroches]

On Wed, Nov 18, 2015 at 04:21:17PM +0100, Arnd Bergmann wrote:
> resource_size_t may be defined as 32 or 64 bit depending on configuration,
> so it cannot be printed using the normal format strings, as gcc correctly
> warns:
> 
> pinctrl-at91-pio4.c: In function 'atmel_pinctrl_probe':
> pinctrl-at91-pio4.c:1003:41: warning: format '%u' expects argument of type 
> 'unsigned int', but argument 5 has type 'resource_size_t {aka long long 
> unsigned int}' [-Wformat=]
>dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
> 
> This changes the format string to use the special "%pr" format
> string that prints a resource, and changes the arguments so we
> the resource structure directly.
> 
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
Acked-by: Ludovic Desroches <ludovic.desroc...@atmel.com>

Thanks.

> ---
> v2: don't break ordering of arguments, that part was correct already, unlike
> what I said in v1.
> 
> diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c 
> b/drivers/pinctrl/pinctrl-at91-pio4.c
> index 33edd07d9149..abdc16e5a970 100644
> --- a/drivers/pinctrl/pinctrl-at91-pio4.c
> +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
> @@ -1000,7 +1000,7 @@ static int atmel_pinctrl_probe(struct platform_device 
> *pdev)
>   atmel_pioctrl->irqs[i] = res->start;
>   irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
>   irq_set_handler_data(res->start, atmel_pioctrl);
> - dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
> + dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
>   }
>  
>   atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
> 
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Re: [PATCH v2 4/7] ARM: at91/dt: sama5d2: add pio controller node

[Ludovic Desroches]

On Tue, Nov 17, 2015 at 11:15:11AM -0800, Olof Johansson wrote:
> On Tue, Nov 17, 2015 at 3:06 AM, Linus Walleij  
> wrote:
> > On Tue, Nov 10, 2015 at 1:30 AM, Olof Johansson  wrote:
> >> On Mon, Sep 21, 2015 at 11:24 AM, Linus Walleij
> >>  wrote:
> >>> On Wed, Sep 16, 2015 at 8:37 AM, Ludovic Desroches
> >>>  wrote:
> >>>
> >>>> Add pio4 controller node to enable pinmux and gpio.
> >>>>
> >>>> Signed-off-by: Ludovic Desroches 
> >>>
> >>> Patch applied.
> >>
> >> Please don't merge DT changes through driver trees unless there's a
> >> very specific reason to do so, since it introduces random conflicts.
> >
> > Sorry :(
> >
> > Even noted this in the pull request to Torvalds, it was in the bottom
> > of my patch stack so had been in -next for ages, I was afraid it
> > would create more problem than it solves if I reverted the patch,
> > but I guess I should have done so anyways.
> 
> Yeah, it's OK -- I spotted that pull request later as well.
> 
> It's not a big deal in most specific instances, I'd say. It's just in
> aggregate it becomes a bother.
> 
> So, just see this as a public reminder since we've seen it creep into
> other driver trees a bit more lately. Mistakes will still happen but
> try to keep it down. And for those who submit patches, feel free to
> point out in the patch that you don't expect the driver/subsystem
> maintainer to apply it to help them out.
> 

Ok. Sorry, I didn't think it could cause so many conflicts if not taken
by Nicolas.


Ludovic
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Re: [PATCH] pinctrl: at91-pio4: use %pr format string for resource

[Ludovic Desroches]

Hi Arnd,

On Thu, Nov 12, 2015 at 03:15:38PM +0100, Arnd Bergmann wrote:
> resource_size_t may be defined as 32 or 64 bit depending on configuration,
> so it cannot be printed using the normal format strings, as gcc correctly
> warns:
> 
> pinctrl-at91-pio4.c: In function 'atmel_pinctrl_probe':
> pinctrl-at91-pio4.c:1003:41: warning: format '%u' expects argument of type 
> 'unsigned int', but argument 5 has type 'resource_size_t {aka long long 
> unsigned int}' [-Wformat=]
>dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
> 
> This changes the format string to use the special "%pr" format
> string that prints a resource, and changes the arguments so we
> the resource structure directly. I'm also swapping out the arguments
> to match the text in the format string.
> 

I agree the format change but not swapping out the arguments. Why do you have
the feeling they are not matching the text?

Few lines before you have:
res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
atmel_pioctrl->irqs[i] = res->start;

Each bank has its own irq line this is what I want to print with hwirq.
Of course it assumes that interrupts are declared in the right order.

Regards

Ludovic

> Signed-off-by: Arnd Bergmann 
> 
> diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c 
> b/drivers/pinctrl/pinctrl-at91-pio4.c
> index 33edd07d9149..23217e990eaf 100644
> --- a/drivers/pinctrl/pinctrl-at91-pio4.c
> +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
> @@ -1000,7 +1000,7 @@ static int atmel_pinctrl_probe(struct platform_device 
> *pdev)
>   atmel_pioctrl->irqs[i] = res->start;
>   irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
>   irq_set_handler_data(res->start, atmel_pioctrl);
> - dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
> + dev_dbg(dev, "bank %pr: hwirq=%u\n", res, i);
>   }
>  
>   atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
> 
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Re: [PATCH] MAINTAINERS: Atmel drivers: change NAND and ISI entries

[Ludovic Desroches]

On Tue, Nov 17, 2015 at 11:21:35AM +0100, Nicolas Ferre wrote:
> Update Josh's entries about NAND and ISI drivers.
> Thanks for your work with Atmel Josh!
> 
> Signed-off-by: Nicolas Ferre 
> Cc: Ludovic Desroches 
> Cc: Wenyou Yang 
> Cc: Josh Wu 

Acked-by: Ludovic Desroches 

> ---
>  MAINTAINERS | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e9caa4b28828..3c9d0d0ba0e8 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1931,7 +1931,7 @@ S:  Supported
>  F:   drivers/i2c/busses/i2c-at91.c
>  
>  ATMEL ISI DRIVER
> -M:   Josh Wu 
> +M:   Ludovic Desroches 
>  L:   linux-me...@vger.kernel.org
>  S:   Supported
>  F:   drivers/media/platform/soc_camera/atmel-isi.c
> @@ -1950,7 +1950,8 @@ S:  Supported
>  F:   drivers/net/ethernet/cadence/
>  
>  ATMEL NAND DRIVER
> -M:   Josh Wu 
> +M:   Wenyou Yang 
> +M:   Josh Wu 
>  L:   linux-...@lists.infradead.org
>  S:   Supported
>  F:   drivers/mtd/nand/atmel_nand*
> -- 
> 2.1.3
> 
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Re: [PATCH] pinctrl: at91-pio4: use %pr format string for resource

[Ludovic Desroches]

Hi Arnd,

On Thu, Nov 12, 2015 at 03:15:38PM +0100, Arnd Bergmann wrote:
> resource_size_t may be defined as 32 or 64 bit depending on configuration,
> so it cannot be printed using the normal format strings, as gcc correctly
> warns:
> 
> pinctrl-at91-pio4.c: In function 'atmel_pinctrl_probe':
> pinctrl-at91-pio4.c:1003:41: warning: format '%u' expects argument of type 
> 'unsigned int', but argument 5 has type 'resource_size_t {aka long long 
> unsigned int}' [-Wformat=]
>dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
> 
> This changes the format string to use the special "%pr" format
> string that prints a resource, and changes the arguments so we
> the resource structure directly. I'm also swapping out the arguments
> to match the text in the format string.
> 

I agree the format change but not swapping out the arguments. Why do you have
the feeling they are not matching the text?

Few lines before you have:
res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
atmel_pioctrl->irqs[i] = res->start;

Each bank has its own irq line this is what I want to print with hwirq.
Of course it assumes that interrupts are declared in the right order.

Regards

Ludovic

> Signed-off-by: Arnd Bergmann 
> 
> diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c 
> b/drivers/pinctrl/pinctrl-at91-pio4.c
> index 33edd07d9149..23217e990eaf 100644
> --- a/drivers/pinctrl/pinctrl-at91-pio4.c
> +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
> @@ -1000,7 +1000,7 @@ static int atmel_pinctrl_probe(struct platform_device 
> *pdev)
>   atmel_pioctrl->irqs[i] = res->start;
>   irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
>   irq_set_handler_data(res->start, atmel_pioctrl);
> - dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
> + dev_dbg(dev, "bank %pr: hwirq=%u\n", res, i);
>   }
>  
>   atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
> 
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Re: [PATCH] MAINTAINERS: Atmel drivers: change NAND and ISI entries

[Ludovic Desroches]

On Tue, Nov 17, 2015 at 11:21:35AM +0100, Nicolas Ferre wrote:
> Update Josh's entries about NAND and ISI drivers.
> Thanks for your work with Atmel Josh!
> 
> Signed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com>
> Cc: Ludovic Desroches <ludovic.desroc...@atmel.com>
> Cc: Wenyou Yang <wenyou.y...@atmel.com>
> Cc: Josh Wu <rainyfeel...@outlook.com>

Acked-by: Ludovic Desroches <ludovic.desroc...@atmel.com>

> ---
>  MAINTAINERS | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e9caa4b28828..3c9d0d0ba0e8 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1931,7 +1931,7 @@ S:  Supported
>  F:   drivers/i2c/busses/i2c-at91.c
>  
>  ATMEL ISI DRIVER
> -M:   Josh Wu <josh...@atmel.com>
> +M:   Ludovic Desroches <ludovic.desroc...@atmel.com>
>  L:   linux-me...@vger.kernel.org
>  S:   Supported
>  F:   drivers/media/platform/soc_camera/atmel-isi.c
> @@ -1950,7 +1950,8 @@ S:  Supported
>  F:   drivers/net/ethernet/cadence/
>  
>  ATMEL NAND DRIVER
> -M:   Josh Wu <josh...@atmel.com>
> +M:   Wenyou Yang <wenyou.y...@atmel.com>
> +M:   Josh Wu <rainyfeel...@outlook.com>
>  L:   linux-...@lists.infradead.org
>  S:   Supported
>  F:   drivers/mtd/nand/atmel_nand*
> -- 
> 2.1.3
> 
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Re: [PATCH v2 4/7] ARM: at91/dt: sama5d2: add pio controller node

[Ludovic Desroches]

On Tue, Nov 17, 2015 at 11:15:11AM -0800, Olof Johansson wrote:
> On Tue, Nov 17, 2015 at 3:06 AM, Linus Walleij <linus.wall...@linaro.org> 
> wrote:
> > On Tue, Nov 10, 2015 at 1:30 AM, Olof Johansson <o...@lixom.net> wrote:
> >> On Mon, Sep 21, 2015 at 11:24 AM, Linus Walleij
> >> <linus.wall...@linaro.org> wrote:
> >>> On Wed, Sep 16, 2015 at 8:37 AM, Ludovic Desroches
> >>> <ludovic.desroc...@atmel.com> wrote:
> >>>
> >>>> Add pio4 controller node to enable pinmux and gpio.
> >>>>
> >>>> Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
> >>>
> >>> Patch applied.
> >>
> >> Please don't merge DT changes through driver trees unless there's a
> >> very specific reason to do so, since it introduces random conflicts.
> >
> > Sorry :(
> >
> > Even noted this in the pull request to Torvalds, it was in the bottom
> > of my patch stack so had been in -next for ages, I was afraid it
> > would create more problem than it solves if I reverted the patch,
> > but I guess I should have done so anyways.
> 
> Yeah, it's OK -- I spotted that pull request later as well.
> 
> It's not a big deal in most specific instances, I'd say. It's just in
> aggregate it becomes a bother.
> 
> So, just see this as a public reminder since we've seen it creep into
> other driver trees a bit more lately. Mistakes will still happen but
> try to keep it down. And for those who submit patches, feel free to
> point out in the patch that you don't expect the driver/subsystem
> maintainer to apply it to help them out.
> 

Ok. Sorry, I didn't think it could cause so many conflicts if not taken
by Nicolas.


Ludovic
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[PATCH v4] mmc: sdhci at91: add PM support

[Ludovic Desroches]

Add runtime PM support and use runtime_force_suspend|resume() for system
PM.

Signed-off-by: Ludovic Desroches 
---

Changes:
- from v3: add error handling of runtime PM
- from v2: cleanup thanks to Ulf feedback
- from v1: take a runtime PM centric approach

 drivers/mmc/host/sdhci-of-at91.c | 72 ++--
 1 file changed, 70 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
index 06d0b50..81ab9db 100644
--- a/drivers/mmc/host/sdhci-of-at91.c
+++ b/drivers/mmc/host/sdhci-of-at91.c
@@ -21,6 +21,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "sdhci-pltfm.h"
 
@@ -51,6 +53,60 @@ static const struct of_device_id sdhci_at91_dt_match[] = {
{}
 };
 
+#ifdef CONFIG_PM
+static int sdhci_at91_runtime_suspend(struct device *dev)
+{
+   struct sdhci_host *host = dev_get_drvdata(dev);
+   struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+   struct sdhci_at91_priv *priv = pltfm_host->priv;
+   int ret;
+
+   ret = sdhci_runtime_suspend_host(host);
+
+   clk_disable_unprepare(priv->gck);
+   clk_disable_unprepare(priv->hclock);
+   clk_disable_unprepare(priv->mainck);
+
+   return ret;
+}
+
+static int sdhci_at91_runtime_resume(struct device *dev)
+{
+   struct sdhci_host *host = dev_get_drvdata(dev);
+   struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+   struct sdhci_at91_priv *priv = pltfm_host->priv;
+   int ret;
+
+   ret = clk_prepare_enable(priv->mainck);
+   if (ret) {
+   dev_err(dev, "can't enable mainck\n");
+   return ret;
+   }
+
+   ret = clk_prepare_enable(priv->hclock);
+   if (ret) {
+   dev_err(dev, "can't enable hclock\n");
+   return ret;
+   }
+
+   ret = clk_prepare_enable(priv->gck);
+   if (ret) {
+   dev_err(dev, "can't enable gck\n");
+   return ret;
+   }
+
+   return sdhci_runtime_resume_host(host);
+}
+#endif /* CONFIG_PM */
+
+static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
+   SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
+  sdhci_at91_runtime_resume,
+  NULL)
+};
+
 static int sdhci_at91_probe(struct platform_device *pdev)
 {
const struct of_device_id   *match;
@@ -144,12 +200,20 @@ static int sdhci_at91_probe(struct platform_device *pdev)
 
sdhci_get_of_property(pdev);
 
+   pm_runtime_set_active(>dev);
+   pm_runtime_enable(>dev);
+   pm_runtime_set_autosuspend_delay(>dev, 50);
+   pm_runtime_use_autosuspend(>dev);
+
ret = sdhci_add_host(host);
if (ret)
-   goto clocks_disable_unprepare;
+   goto pm_runtime_disable;
 
return 0;
 
+pm_runtime_disable:
+   pm_runtime_disable(>dev);
+   pm_runtime_set_suspended(>dev);
 clocks_disable_unprepare:
clk_disable_unprepare(priv->gck);
clk_disable_unprepare(priv->mainck);
@@ -165,6 +229,10 @@ static int sdhci_at91_remove(struct platform_device *pdev)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_at91_priv  *priv = pltfm_host->priv;
 
+   pm_runtime_get_sync(>dev);
+   pm_runtime_disable(>dev);
+   pm_runtime_put_noidle(>dev);
+
sdhci_pltfm_unregister(pdev);
 
clk_disable_unprepare(priv->gck);
@@ -178,7 +246,7 @@ static struct platform_driver sdhci_at91_driver = {
.driver = {
.name   = "sdhci-at91",
.of_match_table = sdhci_at91_dt_match,
-   .pm = SDHCI_PLTFM_PMOPS,
+   .pm = _at91_dev_pm_ops,
},
.probe  = sdhci_at91_probe,
.remove = sdhci_at91_remove,
-- 
2.5.0

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[PATCH v4] mmc: sdhci at91: add PM support

[Ludovic Desroches]

Add runtime PM support and use runtime_force_suspend|resume() for system
PM.

Signed-off-by: Ludovic Desroches <ludovic.desroc...@atmel.com>
---

Changes:
- from v3: add error handling of runtime PM
- from v2: cleanup thanks to Ulf feedback
- from v1: take a runtime PM centric approach

 drivers/mmc/host/sdhci-of-at91.c | 72 ++--
 1 file changed, 70 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
index 06d0b50..81ab9db 100644
--- a/drivers/mmc/host/sdhci-of-at91.c
+++ b/drivers/mmc/host/sdhci-of-at91.c
@@ -21,6 +21,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "sdhci-pltfm.h"
 
@@ -51,6 +53,60 @@ static const struct of_device_id sdhci_at91_dt_match[] = {
{}
 };
 
+#ifdef CONFIG_PM
+static int sdhci_at91_runtime_suspend(struct device *dev)
+{
+   struct sdhci_host *host = dev_get_drvdata(dev);
+   struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+   struct sdhci_at91_priv *priv = pltfm_host->priv;
+   int ret;
+
+   ret = sdhci_runtime_suspend_host(host);
+
+   clk_disable_unprepare(priv->gck);
+   clk_disable_unprepare(priv->hclock);
+   clk_disable_unprepare(priv->mainck);
+
+   return ret;
+}
+
+static int sdhci_at91_runtime_resume(struct device *dev)
+{
+   struct sdhci_host *host = dev_get_drvdata(dev);
+   struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+   struct sdhci_at91_priv *priv = pltfm_host->priv;
+   int ret;
+
+   ret = clk_prepare_enable(priv->mainck);
+   if (ret) {
+   dev_err(dev, "can't enable mainck\n");
+   return ret;
+   }
+
+   ret = clk_prepare_enable(priv->hclock);
+   if (ret) {
+   dev_err(dev, "can't enable hclock\n");
+   return ret;
+   }
+
+   ret = clk_prepare_enable(priv->gck);
+   if (ret) {
+   dev_err(dev, "can't enable gck\n");
+   return ret;
+   }
+
+   return sdhci_runtime_resume_host(host);
+}
+#endif /* CONFIG_PM */
+
+static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
+   SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
+  sdhci_at91_runtime_resume,
+  NULL)
+};
+
 static int sdhci_at91_probe(struct platform_device *pdev)
 {
const struct of_device_id   *match;
@@ -144,12 +200,20 @@ static int sdhci_at91_probe(struct platform_device *pdev)
 
sdhci_get_of_property(pdev);
 
+   pm_runtime_set_active(>dev);
+   pm_runtime_enable(>dev);
+   pm_runtime_set_autosuspend_delay(>dev, 50);
+   pm_runtime_use_autosuspend(>dev);
+
ret = sdhci_add_host(host);
if (ret)
-   goto clocks_disable_unprepare;
+   goto pm_runtime_disable;
 
return 0;
 
+pm_runtime_disable:
+   pm_runtime_disable(>dev);
+   pm_runtime_set_suspended(>dev);
 clocks_disable_unprepare:
clk_disable_unprepare(priv->gck);
clk_disable_unprepare(priv->mainck);
@@ -165,6 +229,10 @@ static int sdhci_at91_remove(struct platform_device *pdev)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_at91_priv  *priv = pltfm_host->priv;
 
+   pm_runtime_get_sync(>dev);
+   pm_runtime_disable(>dev);
+   pm_runtime_put_noidle(>dev);
+
sdhci_pltfm_unregister(pdev);
 
clk_disable_unprepare(priv->gck);
@@ -178,7 +246,7 @@ static struct platform_driver sdhci_at91_driver = {
.driver = {
.name   = "sdhci-at91",
.of_match_table = sdhci_at91_dt_match,
-   .pm = SDHCI_PLTFM_PMOPS,
+   .pm = _at91_dev_pm_ops,
},
.probe  = sdhci_at91_probe,
.remove = sdhci_at91_remove,
-- 
2.5.0

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