Re: [PATCH 11/18] spi: qup: properly detect extra interrupts

[Matthew McClintock]

On Wed, Jun 14, 2017 at 2:59 PM, Andy Gross <andy.gr...@linaro.org> wrote:
> On Wed, Jun 14, 2017 at 12:57:25PM +0530, Sricharan R wrote:
>> Hi Varada,
>>
>> On 6/14/2017 11:22 AM, Varadarajan Narayanan wrote:
>> > It's possible for a SPI transaction to complete and get another
>> > interrupt and have it processed on the same spi_transfer before the
>> > transfer_one can set it to NULL.
>> >
>> > This masks unexpected interrupts, so let's set the spi_transfer to
>> > NULL in the interrupt once the transaction is done. So we can
>> > properly detect these bad interrupts and print warning messages.
>> >
>> > Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
>> > Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
>> > ---
>> >  drivers/spi/spi-qup.c | 20 +++-
>> >  1 file changed, 11 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
>> > index bd53e82..1a2a9d9 100644
>> > --- a/drivers/spi/spi-qup.c
>> > +++ b/drivers/spi/spi-qup.c
>> > @@ -496,13 +496,13 @@ static irqreturn_t spi_qup_qup_irq(int irq, void 
>> > *dev_id)
>> > struct spi_qup *controller = dev_id;
>> > struct spi_transfer *xfer;
>> > u32 opflags, qup_err, spi_err;
>> > -   unsigned long flags;
>> > int error = 0;
>> > +   bool done = 0;
>> >
>> > -   spin_lock_irqsave(>lock, flags);
>> > +   spin_lock(>lock);
>> > xfer = controller->xfer;
>> > controller->xfer = NULL;
>> > -   spin_unlock_irqrestore(>lock, flags);
>> > +   spin_unlock(>lock);
>>
>>  Why change the locking here ?
>>
>> >
>> > qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
>> > spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
>> > @@ -556,16 +556,19 @@ static irqreturn_t spi_qup_qup_irq(int irq, void 
>> > *dev_id)
>> > spi_qup_write(controller, xfer);
>> > }
>> >
>> > -   spin_lock_irqsave(>lock, flags);
>> > -   controller->error = error;
>> > -   controller->xfer = xfer;
>> > -   spin_unlock_irqrestore(>lock, flags);
>> > -
>> > /* re-read opflags as flags may have changed due to actions above */
>> > opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
>> >
>> > if ((controller->rx_bytes == xfer->len &&
>> > (opflags & QUP_OP_MAX_INPUT_DONE_FLAG)) ||  error)
>> > +   done = true;
>> > +
>> > +   spin_lock(>lock);
>> > +   controller->error = error;
>> > +   controller->xfer = done ? NULL : xfer;
>> > +   spin_unlock(>lock);
>> > +
>> > +   if (done)
>> > complete(>done);
>> >
>>   Its not clear, why the driver is setting the controller->xfer = NULL
>>   and restoring it inside the irq. This patch seems to fix things on
>>   top of that.
>
> I think the original intent was to make sure that the irqhandler knew that 
> there
> was no outstanding transaction.  This begs the question of why that would ever
> be necessary.  I think it would suffice to rework all of that to remove that
> behavior and perhaps enable/disable the irq as we need to during transactions.
>
> I've never been a fan of the controller->xfer being set to NULL.

Also, this patch presumably fixes an issue seen on Dakota SoCs,
doesn't add or remote the NULL bits.

-M

Re: [PATCH 11/18] spi: qup: properly detect extra interrupts

[Matthew McClintock]

On Wed, Jun 14, 2017 at 2:59 PM, Andy Gross  wrote:
> On Wed, Jun 14, 2017 at 12:57:25PM +0530, Sricharan R wrote:
>> Hi Varada,
>>
>> On 6/14/2017 11:22 AM, Varadarajan Narayanan wrote:
>> > It's possible for a SPI transaction to complete and get another
>> > interrupt and have it processed on the same spi_transfer before the
>> > transfer_one can set it to NULL.
>> >
>> > This masks unexpected interrupts, so let's set the spi_transfer to
>> > NULL in the interrupt once the transaction is done. So we can
>> > properly detect these bad interrupts and print warning messages.
>> >
>> > Signed-off-by: Matthew McClintock 
>> > Signed-off-by: Varadarajan Narayanan 
>> > ---
>> >  drivers/spi/spi-qup.c | 20 +++-
>> >  1 file changed, 11 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
>> > index bd53e82..1a2a9d9 100644
>> > --- a/drivers/spi/spi-qup.c
>> > +++ b/drivers/spi/spi-qup.c
>> > @@ -496,13 +496,13 @@ static irqreturn_t spi_qup_qup_irq(int irq, void 
>> > *dev_id)
>> > struct spi_qup *controller = dev_id;
>> > struct spi_transfer *xfer;
>> > u32 opflags, qup_err, spi_err;
>> > -   unsigned long flags;
>> > int error = 0;
>> > +   bool done = 0;
>> >
>> > -   spin_lock_irqsave(>lock, flags);
>> > +   spin_lock(>lock);
>> > xfer = controller->xfer;
>> > controller->xfer = NULL;
>> > -   spin_unlock_irqrestore(>lock, flags);
>> > +   spin_unlock(>lock);
>>
>>  Why change the locking here ?
>>
>> >
>> > qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
>> > spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
>> > @@ -556,16 +556,19 @@ static irqreturn_t spi_qup_qup_irq(int irq, void 
>> > *dev_id)
>> > spi_qup_write(controller, xfer);
>> > }
>> >
>> > -   spin_lock_irqsave(>lock, flags);
>> > -   controller->error = error;
>> > -   controller->xfer = xfer;
>> > -   spin_unlock_irqrestore(>lock, flags);
>> > -
>> > /* re-read opflags as flags may have changed due to actions above */
>> > opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
>> >
>> > if ((controller->rx_bytes == xfer->len &&
>> > (opflags & QUP_OP_MAX_INPUT_DONE_FLAG)) ||  error)
>> > +   done = true;
>> > +
>> > +   spin_lock(>lock);
>> > +   controller->error = error;
>> > +   controller->xfer = done ? NULL : xfer;
>> > +   spin_unlock(>lock);
>> > +
>> > +   if (done)
>> > complete(>done);
>> >
>>   Its not clear, why the driver is setting the controller->xfer = NULL
>>   and restoring it inside the irq. This patch seems to fix things on
>>   top of that.
>
> I think the original intent was to make sure that the irqhandler knew that 
> there
> was no outstanding transaction.  This begs the question of why that would ever
> be necessary.  I think it would suffice to rework all of that to remove that
> behavior and perhaps enable/disable the irq as we need to during transactions.
>
> I've never been a fan of the controller->xfer being set to NULL.

Also, this patch presumably fixes an issue seen on Dakota SoCs,
doesn't add or remote the NULL bits.

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

On May 25, 2016, at 1:24 AM, Al Viro  wrote:
> 
> diff --git a/lib/iov_iter.c b/lib/iov_iter.c
> index 28cb431..0cd5227 100644
> --- a/lib/iov_iter.c
> +++ b/lib/iov_iter.c
> @@ -101,7 +101,7 @@
> #define iterate_and_advance(i, n, v, I, B, K) {   \
>   if (unlikely(i->count < n)) \
>   n = i->count;   \
> - if (n) {\
> + if (i->count) { \
>   size_t skip = i->iov_offset;\
>   if (unlikely(i->type & ITER_BVEC)) {\
>   const struct bio_vec *bvec; \
> 
> Could you see if your reproducer is fixed by that?

Yes, this fixes my issue.

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

On May 25, 2016, at 1:24 AM, Al Viro  wrote:
> 
> diff --git a/lib/iov_iter.c b/lib/iov_iter.c
> index 28cb431..0cd5227 100644
> --- a/lib/iov_iter.c
> +++ b/lib/iov_iter.c
> @@ -101,7 +101,7 @@
> #define iterate_and_advance(i, n, v, I, B, K) {   \
>   if (unlikely(i->count < n)) \
>   n = i->count;   \
> - if (n) {\
> + if (i->count) { \
>   size_t skip = i->iov_offset;\
>   if (unlikely(i->type & ITER_BVEC)) {\
>   const struct bio_vec *bvec; \
> 
> Could you see if your reproducer is fixed by that?

Yes, this fixes my issue.

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

> On May 24, 2016, at 8:28 PM, Al Viro  wrote:
> 
> The next obvious question is which binary it is and what's the return
> address to userland; make that
>   if (!size)
>   printk(KERN_ERR "crap in %s[%x]",
>   current->comm,
>   current_pt_regs()->rip);
> (in the same place)

This is an ARM board, no rip. Quick log without, can re-run again later tonight 
or maybe tomorrow:

[8.008054] crap in udevd

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

> On May 24, 2016, at 8:28 PM, Al Viro  wrote:
> 
> The next obvious question is which binary it is and what's the return
> address to userland; make that
>   if (!size)
>   printk(KERN_ERR "crap in %s[%x]",
>   current->comm,
>   current_pt_regs()->rip);
> (in the same place)

This is an ARM board, no rip. Quick log without, can re-run again later tonight 
or maybe tomorrow:

[8.008054] crap in udevd

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

> On May 24, 2016, at 8:10 PM, Al Viro  wrote:
> 
> Slap the WARN_ON(!size); in the very beginning of iov_iter_advance(), see
> where it's triggered...

diff --git a/lib/iov_iter.c b/lib/iov_iter.c
index 28cb431..d89e154 100644
--- a/lib/iov_iter.c
+++ b/lib/iov_iter.c
@@ -488,6 +488,7 @@ EXPORT_SYMBOL(iov_iter_copy_from_user_atomic);

 void iov_iter_advance(struct iov_iter *i, size_t size)
 {
+   WARN_ON(!size);
iterate_and_advance(i, size, v, 0, 0, 0)
 }
 EXPORT_SYMBOL(iov_iter_advance);

[1.359869] This architecture does not have kernel memory protection.
init started: BusyBox v1.24.1 ()
starting pid 78, tty '': '/etc/init.d/rcS'
[1.435863] random: udevadm urandom read with 0 bits of entropy available
[1.448116] [ cut here ]
[1.448193] WARNING: CPU: 1 PID: 88 at lib/iov_iter.c:491 
iov_iter_advance+0xf0/0x1b8
[1.451973] Modules linked in:
[1.462753] CPU: 1 PID: 88 Comm: udevd Not tainted 4.6.0 #195
[1.462793] Hardware name: Qualcomm (Flattened Device Tree)
[1.468346] [] (unwind_backtrace) from [] 
(show_stack+0x20/0x24)
[1.473713] [] (show_stack) from [] 
(dump_stack+0x90/0xa4)
[1.481701] [] (dump_stack) from [] (__warn+0xf8/0x110)
[1.488727] [] (__warn) from [] 
(warn_slowpath_null+0x30/0x38)
[1.495588] [] (warn_slowpath_null) from [] 
(iov_iter_advance+0xf0/0x1b8)
[1.503244] [] (iov_iter_advance) from [] 
(do_readv_writev+0x2d0/0x370)
[1.511827] [] (do_readv_writev) from [] 
(vfs_readv+0x50/0x68)
[1.519983] [] (vfs_readv) from [] (do_readv+0x5c/0xb8)
[1.527621] [] (do_readv) from [] (SyS_readv+0x1c/0x20)
[1.534485] [] (SyS_readv) from [] 
(ret_fast_syscall+0x0/0x3c)
[1.541556] ---[ end trace eef892a602dbe329 ]---

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

> On May 24, 2016, at 8:10 PM, Al Viro  wrote:
> 
> Slap the WARN_ON(!size); in the very beginning of iov_iter_advance(), see
> where it's triggered...

diff --git a/lib/iov_iter.c b/lib/iov_iter.c
index 28cb431..d89e154 100644
--- a/lib/iov_iter.c
+++ b/lib/iov_iter.c
@@ -488,6 +488,7 @@ EXPORT_SYMBOL(iov_iter_copy_from_user_atomic);

 void iov_iter_advance(struct iov_iter *i, size_t size)
 {
+   WARN_ON(!size);
iterate_and_advance(i, size, v, 0, 0, 0)
 }
 EXPORT_SYMBOL(iov_iter_advance);

[1.359869] This architecture does not have kernel memory protection.
init started: BusyBox v1.24.1 ()
starting pid 78, tty '': '/etc/init.d/rcS'
[1.435863] random: udevadm urandom read with 0 bits of entropy available
[1.448116] [ cut here ]
[1.448193] WARNING: CPU: 1 PID: 88 at lib/iov_iter.c:491 
iov_iter_advance+0xf0/0x1b8
[1.451973] Modules linked in:
[1.462753] CPU: 1 PID: 88 Comm: udevd Not tainted 4.6.0 #195
[1.462793] Hardware name: Qualcomm (Flattened Device Tree)
[1.468346] [] (unwind_backtrace) from [] 
(show_stack+0x20/0x24)
[1.473713] [] (show_stack) from [] 
(dump_stack+0x90/0xa4)
[1.481701] [] (dump_stack) from [] (__warn+0xf8/0x110)
[1.488727] [] (__warn) from [] 
(warn_slowpath_null+0x30/0x38)
[1.495588] [] (warn_slowpath_null) from [] 
(iov_iter_advance+0xf0/0x1b8)
[1.503244] [] (iov_iter_advance) from [] 
(do_readv_writev+0x2d0/0x370)
[1.511827] [] (do_readv_writev) from [] 
(vfs_readv+0x50/0x68)
[1.519983] [] (vfs_readv) from [] (do_readv+0x5c/0xb8)
[1.527621] [] (do_readv) from [] (SyS_readv+0x1c/0x20)
[1.534485] [] (SyS_readv) from [] 
(ret_fast_syscall+0x0/0x3c)
[1.541556] ---[ end trace eef892a602dbe329 ]---

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

> On May 24, 2016, at 6:41 PM, Al Viro  wrote:
> 
> Again, I understand what's going on kernel-side; the only tricky part is how
> to fix it without bringing the nasal daemons back.  I think I have a solution
> and I'm going to post it tonight if it survives the local beating.  In any
> case, the testcase above deserves being added to LTP - it's a real regression.

I’m running a simple busybox rootfs with the following init script:

https://gist.github.com/7b12fdb5d7def9a835291a79c060fa07

And inittab:

https://gist.github.com/5a840b7eaa48f321836125f15147d0e9

Happy to turn on ftrace, dyndbg, and provide more logs.

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

> On May 24, 2016, at 6:41 PM, Al Viro  wrote:
> 
> Again, I understand what's going on kernel-side; the only tricky part is how
> to fix it without bringing the nasal daemons back.  I think I have a solution
> and I'm going to post it tonight if it survives the local beating.  In any
> case, the testcase above deserves being added to LTP - it's a real regression.

I’m running a simple busybox rootfs with the following init script:

https://gist.github.com/7b12fdb5d7def9a835291a79c060fa07

And inittab:

https://gist.github.com/5a840b7eaa48f321836125f15147d0e9

Happy to turn on ftrace, dyndbg, and provide more logs.

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

> On May 24, 2016, at 2:36 PM, Larry Finger <larry.fin...@lwfinger.net> wrote:
> 
> On 05/24/2016 02:25 PM, Matthew McClintock wrote:
>> On May 24, 2016, at 2:16 PM, Larry Finger <larry.fin...@lwfinger.net> wrote:
>>> 
>>> On 05/24/2016 02:13 PM, Matthew McClintock wrote:
>>>> I’m seeing this too, same commit if you want another person to 
>>>> test/reproduce.
>>> 
>>> If you do a pull today, does that fix your problem?
>> 
>> Hmm, no. Which commit am I looking for? I’m on 
>> a56f489502e28caac56c8a0735549740f0ae0711
> 
> Commit 84787c572d402644dca4874aba73324d9f8e3948 is working for me. I have a 
> fixup in lib/iov_iter.c with a dump_stack() call if the fixup was needed. 
> That dump is not triggered. I do not seem to have a56f489502e yet.

Still seeing the issue on top of tree and the above commit. Re-ran bisection 
just to be sure.

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

> On May 24, 2016, at 2:36 PM, Larry Finger  wrote:
> 
> On 05/24/2016 02:25 PM, Matthew McClintock wrote:
>> On May 24, 2016, at 2:16 PM, Larry Finger  wrote:
>>> 
>>> On 05/24/2016 02:13 PM, Matthew McClintock wrote:
>>>> I’m seeing this too, same commit if you want another person to 
>>>> test/reproduce.
>>> 
>>> If you do a pull today, does that fix your problem?
>> 
>> Hmm, no. Which commit am I looking for? I’m on 
>> a56f489502e28caac56c8a0735549740f0ae0711
> 
> Commit 84787c572d402644dca4874aba73324d9f8e3948 is working for me. I have a 
> fixup in lib/iov_iter.c with a dump_stack() call if the fixup was needed. 
> That dump is not triggered. I do not seem to have a56f489502e yet.

Still seeing the issue on top of tree and the above commit. Re-ran bisection 
just to be sure.

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

On May 24, 2016, at 2:16 PM, Larry Finger <larry.fin...@lwfinger.net> wrote:
> 
> On 05/24/2016 02:13 PM, Matthew McClintock wrote:
>> I’m seeing this too, same commit if you want another person to 
>> test/reproduce.
> 
> If you do a pull today, does that fix your problem?

Hmm, no. Which commit am I looking for? I’m on 
a56f489502e28caac56c8a0735549740f0ae0711

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

On May 24, 2016, at 2:16 PM, Larry Finger  wrote:
> 
> On 05/24/2016 02:13 PM, Matthew McClintock wrote:
>> I’m seeing this too, same commit if you want another person to 
>> test/reproduce.
> 
> If you do a pull today, does that fix your problem?

Hmm, no. Which commit am I looking for? I’m on 
a56f489502e28caac56c8a0735549740f0ae0711

-M

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

I’m seeing this too, same commit if you want another person to test/reproduce.

-M

> On May 24, 2016, at 11:10 AM, Larry Finger  wrote:
> 
> On 05/23/2016 07:18 PM, Al Viro wrote:
>> On Mon, May 23, 2016 at 04:30:43PM -0500, Larry Finger wrote:
>>> The mainline kernels past 4.6.0 fail hang when logging in. There are no
>>> error messages, and the machine seems to be waiting for some event that
>>> never happens.
>>> 
>>> The problem has been bisected to commit dd254f5a382c ("fold checks into
>>> iterate_and_advance()"). The bisection has been verified.
>>> 
>>> The problem is the call from iov_iter_advance(). When I reinstated the old
>>> macro with a new name and used it in that routine, the system works.
>>> Obviously, the call that seems to be incorrect has some benefits. My
>>> quich-and-dirty patch is attached.
>>> 
>>> I will be willing to test any patch you prepare.
>> 
>> Hangs where and how?  A reproducer, please...  This is really weird - the
>> only change there is in the cases when
>>  * iov_iter_advance(i, n) is called with n greater than the remaining
>> amount.  It's a bug, plain and simple - old variant would've been left in
>> seriously buggered state and at the very least we want to catch any such
>> places for the sake of backports
>>  * iov_iter_advance(i, 0) - both old and new code leave *i unchanged,
>> but the old one dereferences i->iov[0], which be pointing beyond the end of
>> array by that point.  The value read from there was not used by the old code,
>> at that.
>> 
>>  Could you slap WARN_ON(size > i->count) in the very beginning of
>> iov_iter_advance() (the mainline variant) and see what triggers on your
>> reproducer?
> 
> As I wrote earlier, i->count was greater than zero, but size was zero, which 
> caused the bulk of iterate_and_advance() to be skipped.
> 
> For now, the following one-line hack allows my system to boot:
> 
> diff --git a/fs/read_write.c b/fs/read_write.c
> index 933b53a..d5d64d9 100644
> --- a/fs/read_write.c
> +++ b/fs/read_write.c
> @@ -721,6 +721,7 @@ static ssize_t do_loop_readv_writev(struct file *filp, 
> struct iov_iter *iter,
>ret += nr;
>if (nr != iovec.iov_len)
>break;
> +   nr = max_t(ssize_t, nr, 1);
>iov_iter_advance(iter, nr);
>}
> 
> I have no idea what subtle bug in do_loop_readv_writev() is causing nr to be 
> zero, but it seems to have been exposed by commit dd254f5a382c.
> 
> Larry
> 
> 

Re: Regression in 4.6.0-git - bisected to commit dd254f5a382c

[Matthew McClintock]

I’m seeing this too, same commit if you want another person to test/reproduce.

-M

> On May 24, 2016, at 11:10 AM, Larry Finger  wrote:
> 
> On 05/23/2016 07:18 PM, Al Viro wrote:
>> On Mon, May 23, 2016 at 04:30:43PM -0500, Larry Finger wrote:
>>> The mainline kernels past 4.6.0 fail hang when logging in. There are no
>>> error messages, and the machine seems to be waiting for some event that
>>> never happens.
>>> 
>>> The problem has been bisected to commit dd254f5a382c ("fold checks into
>>> iterate_and_advance()"). The bisection has been verified.
>>> 
>>> The problem is the call from iov_iter_advance(). When I reinstated the old
>>> macro with a new name and used it in that routine, the system works.
>>> Obviously, the call that seems to be incorrect has some benefits. My
>>> quich-and-dirty patch is attached.
>>> 
>>> I will be willing to test any patch you prepare.
>> 
>> Hangs where and how?  A reproducer, please...  This is really weird - the
>> only change there is in the cases when
>>  * iov_iter_advance(i, n) is called with n greater than the remaining
>> amount.  It's a bug, plain and simple - old variant would've been left in
>> seriously buggered state and at the very least we want to catch any such
>> places for the sake of backports
>>  * iov_iter_advance(i, 0) - both old and new code leave *i unchanged,
>> but the old one dereferences i->iov[0], which be pointing beyond the end of
>> array by that point.  The value read from there was not used by the old code,
>> at that.
>> 
>>  Could you slap WARN_ON(size > i->count) in the very beginning of
>> iov_iter_advance() (the mainline variant) and see what triggers on your
>> reproducer?
> 
> As I wrote earlier, i->count was greater than zero, but size was zero, which 
> caused the bulk of iterate_and_advance() to be skipped.
> 
> For now, the following one-line hack allows my system to boot:
> 
> diff --git a/fs/read_write.c b/fs/read_write.c
> index 933b53a..d5d64d9 100644
> --- a/fs/read_write.c
> +++ b/fs/read_write.c
> @@ -721,6 +721,7 @@ static ssize_t do_loop_readv_writev(struct file *filp, 
> struct iov_iter *iter,
>ret += nr;
>if (nr != iovec.iov_len)
>break;
> +   nr = max_t(ssize_t, nr, 1);
>iov_iter_advance(iter, nr);
>}
> 
> I have no idea what subtle bug in do_loop_readv_writev() is causing nr to be 
> zero, but it seems to have been exposed by commit dd254f5a382c.
> 
> Larry
> 
> 

Re: [PATCH V3 2/4] cpufreq: dt: Add generic platform-device creation support

[Matthew McClintock]

On Mar 30, 2016, at 3:15 AM, Viresh Kumar <viresh.ku...@linaro.org> wrote:
> 
> Multiple platforms are using the generic cpufreq-dt driver now, and all
> of them are required to create a platform device with name "cpufreq-dt",
> in order to get the cpufreq-dt probed.
> 
> Many of them do it from platform code, others have special drivers just
> to do that.
> 
> It would be more sensible to do this at a generic place, where all such
> platform can mark their entries.
> 
> This patch adds a separate file to get this device created. Currently
> the compat list of platforms that we support is empty, and will be
> filled in as and when we move platforms to use it.
> 
> It always compiles as part of the kernel and so doesn't need a
> module-exit operation.
> 
> Signed-off-by: Viresh Kumar <viresh.ku...@linaro.org>
> Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>

Test on ipq4019.

Tested-by: Matthew McClintock <mmccl...@codeaurora.org>

-M

Re: [PATCH V3 2/4] cpufreq: dt: Add generic platform-device creation support

[Matthew McClintock]

On Mar 30, 2016, at 3:15 AM, Viresh Kumar  wrote:
> 
> Multiple platforms are using the generic cpufreq-dt driver now, and all
> of them are required to create a platform device with name "cpufreq-dt",
> in order to get the cpufreq-dt probed.
> 
> Many of them do it from platform code, others have special drivers just
> to do that.
> 
> It would be more sensible to do this at a generic place, where all such
> platform can mark their entries.
> 
> This patch adds a separate file to get this device created. Currently
> the compat list of platforms that we support is empty, and will be
> filled in as and when we move platforms to use it.
> 
> It always compiles as part of the kernel and so doesn't need a
> module-exit operation.
> 
> Signed-off-by: Viresh Kumar 
> Reviewed-by: Krzysztof Kozlowski 

Test on ipq4019.

Tested-by: Matthew McClintock 

-M

Re: [PATCH 2/2] qcom: ipq4019: Add LDO regulator driver for SDHC controller

[Matthew McClintock]

On Apr 6, 2016, at 12:02 AM, Sreedhar Sambangi  wrote:
> 
>>> +config REGULATOR_IPQ4019
>> How bout REGULATOR_QCOM_IPQ4019.
> 
> Sounds good, Will update in V2

Also prefix the name with “Qualcomm” and insert it in the list in order.

-M

Re: [PATCH 2/2] qcom: ipq4019: Add LDO regulator driver for SDHC controller

[Matthew McClintock]

On Apr 6, 2016, at 12:02 AM, Sreedhar Sambangi  wrote:
> 
>>> +config REGULATOR_IPQ4019
>> How bout REGULATOR_QCOM_IPQ4019.
> 
> Sounds good, Will update in V2

Also prefix the name with “Qualcomm” and insert it in the list in order.

-M

Re: [PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Matthew McClintock]

On Mar 28, 2016, at 1:15 PM, Guenter Roeck  wrote:
> 
>>> What SoC(s) is this in. Use SoC specific compatible strings please.
>> 
>> So ipq4019 wins the race because we are the first to try to enable watchdog 
>> for this block?
>> 
>> qcom,kpss-ipq4019 ?
>> 
> It is a dedicated watchdog block, isn't it ? "qcom,kpss-ipq4019" would not
> refer to a specific block. Devicetree maintainers may have a better idea,
> but it seems to me that there should be 'wdt' or 'watchdog' in the property
> name.

Sounds fine to me, if no one has any other comments I’ll use this one in the 
next spin of the patch.

-M

Re: [PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Matthew McClintock]

On Mar 28, 2016, at 1:15 PM, Guenter Roeck  wrote:
> 
>>> What SoC(s) is this in. Use SoC specific compatible strings please.
>> 
>> So ipq4019 wins the race because we are the first to try to enable watchdog 
>> for this block?
>> 
>> qcom,kpss-ipq4019 ?
>> 
> It is a dedicated watchdog block, isn't it ? "qcom,kpss-ipq4019" would not
> refer to a specific block. Devicetree maintainers may have a better idea,
> but it seems to me that there should be 'wdt' or 'watchdog' in the property
> name.

Sounds fine to me, if no one has any other comments I’ll use this one in the 
next spin of the patch.

-M

Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

[Matthew McClintock]

On Mar 28, 2016, at 4:56 PM, Guenter Roeck  wrote:
> 
>> So taken from the timer offset 0x0208A000 I just have a generic counter 
>> register CPU0_APCS_GPT0_CNT at 0x8
>> 
>> What doc are you looking at?
>> 
> "Qualcomm Snapdragon 600 Processor APQ8064 Hardware Register Description"
> 
> It is available for download from the Qualcomm web site.
> 
> See chapter 12.10.3, "Watchdog timer registers". The register block is at
> 0x28882000. Registers are almost the same, except for the offset and the
> definition of the bits in the enable register.
> 
> LPASS is "Low Power Audio Subsystem". Maybe it has its own watchdog.

This block is here:

11.15 KPSS CPU0 Timer Registers (0x0208A000 CPU0_APCS_TMR_BASE)

-M

Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

[Matthew McClintock]

On Mar 28, 2016, at 4:56 PM, Guenter Roeck  wrote:
> 
>> So taken from the timer offset 0x0208A000 I just have a generic counter 
>> register CPU0_APCS_GPT0_CNT at 0x8
>> 
>> What doc are you looking at?
>> 
> "Qualcomm Snapdragon 600 Processor APQ8064 Hardware Register Description"
> 
> It is available for download from the Qualcomm web site.
> 
> See chapter 12.10.3, "Watchdog timer registers". The register block is at
> 0x28882000. Registers are almost the same, except for the offset and the
> definition of the bits in the enable register.
> 
> LPASS is "Low Power Audio Subsystem". Maybe it has its own watchdog.

This block is here:

11.15 KPSS CPU0 Timer Registers (0x0208A000 CPU0_APCS_TMR_BASE)

-M

Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

[Matthew McClintock]

On Mar 28, 2016, at 1:13 PM, Guenter Roeck  wrote:
> 
>>> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg
>>> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is
>>> undefined.
>> 
>> I honestly don’t see anything at 0x8 for either blocks that looks like this. 
>> For the new block bit 0 is enabling and bit 1 enabled interrupts.
>> 
> That is from the APQ8064 datasheet. 

So taken from the timer offset 0x0208A000 I just have a generic counter 
register CPU0_APCS_GPT0_CNT at 0x8

What doc are you looking at?

-M

Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

[Matthew McClintock]

On Mar 28, 2016, at 1:13 PM, Guenter Roeck  wrote:
> 
>>> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg
>>> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is
>>> undefined.
>> 
>> I honestly don’t see anything at 0x8 for either blocks that looks like this. 
>> For the new block bit 0 is enabling and bit 1 enabled interrupts.
>> 
> That is from the APQ8064 datasheet. 

So taken from the timer offset 0x0208A000 I just have a generic counter 
register CPU0_APCS_GPT0_CNT at 0x8

What doc are you looking at?

-M

Re: [PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Matthew McClintock]

On Mar 25, 2016, at 9:15 AM, Rob Herring <r...@kernel.org> wrote:
> 
> On Wed, Mar 23, 2016 at 05:05:04PM -0500, Matthew McClintock wrote:
>> Update the compatible string to add new device tree binding
>> 
>> CC: linux-watch...@vger.kernel.org
>> Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
>> ---
>> Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
>> 1 file changed, 1 insertion(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt 
>> b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>> index 60bb2f98..45b37cf 100644
>> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>> @@ -6,6 +6,7 @@ Required properties :
>> 
>>  "qcom,kpss-timer"
>>  "qcom,scss-timer"
>> +"qcom,kpss-standalone"
> 
> What SoC(s) is this in. Use SoC specific compatible strings please.

So ipq4019 wins the race because we are the first to try to enable watchdog for 
this block?

qcom,kpss-ipq4019 ?

-M

Re: [PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Matthew McClintock]

On Mar 25, 2016, at 9:15 AM, Rob Herring  wrote:
> 
> On Wed, Mar 23, 2016 at 05:05:04PM -0500, Matthew McClintock wrote:
>> Update the compatible string to add new device tree binding
>> 
>> CC: linux-watch...@vger.kernel.org
>> Signed-off-by: Matthew McClintock 
>> ---
>> Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
>> 1 file changed, 1 insertion(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt 
>> b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>> index 60bb2f98..45b37cf 100644
>> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>> @@ -6,6 +6,7 @@ Required properties :
>> 
>>  "qcom,kpss-timer"
>>  "qcom,scss-timer"
>> +"qcom,kpss-standalone"
> 
> What SoC(s) is this in. Use SoC specific compatible strings please.

So ipq4019 wins the race because we are the first to try to enable watchdog for 
this block?

qcom,kpss-ipq4019 ?

-M

Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

[Matthew McClintock]

> On Mar 25, 2016, at 11:23 AM, Guenter Roeck  wrote:
> 
>> -#define WDT_RST 0x38
>> -#define WDT_EN  0x40
>> -#define WDT_BITE_TIME   0x5C
>> +enum wdt_reg {
>> +WDT_RST,
>> +WDT_EN,
>> +WDT_BITE_TIME,
>> +};
>> +
>> +static const u32 reg_offset_data_apcs_tmr[] = {
>> +[WDT_RST] = 0x38,
>> +[WDT_EN] = 0x40,
>> +[WDT_BITE_TIME] = 0x5C,
>> +};
>> +
>> +static const u32 reg_offset_data_kpss[] = {
>> +[WDT_RST] = 0x4,
>> +[WDT_EN] = 0x8,
> 
> Does this work ? In the datasheet I have in front of me (APQ8064), the 
> watchdog
> at this address uses different bits. At address 0x40 (eg GSS_A5_APCS_WDT0_EN),

0x40 is acps_tmr, and looks fine.

> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg
> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is
> undefined.

I honestly don’t see anything at 0x8 for either blocks that looks like this. 
For the new block bit 0 is enabling and bit 1 enabled interrupts.

> Or does "qcom,kpss-standalone" refer to some other watchdog ?

APQ8064 would be the apcs_tmr block variant which is unchanged. MSM8916 as well 
as IPQ4019 would use the new kpss variant.

I went with block names I found internally here, but I will be the first to 
admit I am terrible at names. The old block name for APQ was CPU0_ACPS_TMR 
(where really the watchdog is a subset of a timer block), and on the IPQ4019 
it’s called APCS_KPSS_WDT and it’s really just a watchdog block.

I kept the same driver because the register’s currently in use were compatible. 
By the way, I tested this on an IPQ806x and IPQ4019 both new and old blocks.

Let me know if you need more details.

-M

Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

[Matthew McClintock]

> On Mar 25, 2016, at 11:23 AM, Guenter Roeck  wrote:
> 
>> -#define WDT_RST 0x38
>> -#define WDT_EN  0x40
>> -#define WDT_BITE_TIME   0x5C
>> +enum wdt_reg {
>> +WDT_RST,
>> +WDT_EN,
>> +WDT_BITE_TIME,
>> +};
>> +
>> +static const u32 reg_offset_data_apcs_tmr[] = {
>> +[WDT_RST] = 0x38,
>> +[WDT_EN] = 0x40,
>> +[WDT_BITE_TIME] = 0x5C,
>> +};
>> +
>> +static const u32 reg_offset_data_kpss[] = {
>> +[WDT_RST] = 0x4,
>> +[WDT_EN] = 0x8,
> 
> Does this work ? In the datasheet I have in front of me (APQ8064), the 
> watchdog
> at this address uses different bits. At address 0x40 (eg GSS_A5_APCS_WDT0_EN),

0x40 is acps_tmr, and looks fine.

> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg
> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is
> undefined.

I honestly don’t see anything at 0x8 for either blocks that looks like this. 
For the new block bit 0 is enabling and bit 1 enabled interrupts.

> Or does "qcom,kpss-standalone" refer to some other watchdog ?

APQ8064 would be the apcs_tmr block variant which is unchanged. MSM8916 as well 
as IPQ4019 would use the new kpss variant.

I went with block names I found internally here, but I will be the first to 
admit I am terrible at names. The old block name for APQ was CPU0_ACPS_TMR 
(where really the watchdog is a subset of a timer block), and on the IPQ4019 
it’s called APCS_KPSS_WDT and it’s really just a watchdog block.

I kept the same driver because the register’s currently in use were compatible. 
By the way, I tested this on an IPQ806x and IPQ4019 both new and old blocks.

Let me know if you need more details.

-M

Re: [PATCH 08/17] watchdog: qcom: configure BARK time in addition to BITE time

[Matthew McClintock]

On Mar 24, 2016, at 11:17 AM, Guenter Roeck  wrote:
> 
>>> Why isn't TZ configuring the bark time to what it wants? I'm lost
>>> why we have to do this for them.
>> 
>> So it was done like this to ensure we had a valid upgrade. The bootloader is 
>> using the watchdog to ensure the system is bootable and if not it will 
>> revert back to the working images.
>> 
>> Bottom line is, for some versions of TZ out there, if we enable watchdog 
>> coming out of boot the bark time is already configured by the boot loader 
>> and TZ is configured to intercept this interrupt and do some register saving 
>> (for crashdump) and we end up getting a watchdog reset during boot.
>> 
>> It’s even a little more complex, because in order for the TZ to save the 
>> registers you need to pad the BITE time a bit higher than the BARK time, but 
>> I was leaving that for another day.
>> 
> Sounds like an op[timal target for using pretimeout ?

So the bark is basically a pretimeout, sure I think that will work. We can 
configure it to be off by default.

Thanks for the heads up, I’ll take a look.

-M

Re: [PATCH 08/17] watchdog: qcom: configure BARK time in addition to BITE time

[Matthew McClintock]

On Mar 24, 2016, at 11:17 AM, Guenter Roeck  wrote:
> 
>>> Why isn't TZ configuring the bark time to what it wants? I'm lost
>>> why we have to do this for them.
>> 
>> So it was done like this to ensure we had a valid upgrade. The bootloader is 
>> using the watchdog to ensure the system is bootable and if not it will 
>> revert back to the working images.
>> 
>> Bottom line is, for some versions of TZ out there, if we enable watchdog 
>> coming out of boot the bark time is already configured by the boot loader 
>> and TZ is configured to intercept this interrupt and do some register saving 
>> (for crashdump) and we end up getting a watchdog reset during boot.
>> 
>> It’s even a little more complex, because in order for the TZ to save the 
>> registers you need to pad the BITE time a bit higher than the BARK time, but 
>> I was leaving that for another day.
>> 
> Sounds like an op[timal target for using pretimeout ?

So the bark is basically a pretimeout, sure I think that will work. We can 
configure it to be off by default.

Thanks for the heads up, I’ll take a look.

-M

Re: [PATCH 06/17] watchdog: qcom: update device tree bindings

[Matthew McClintock]

> On Mar 23, 2016, at 5:26 PM, Stephen Boyd <sb...@codeaurora.org> wrote:
> 
> On 03/23/2016 03:05 PM, Matthew McClintock wrote:
>> Update the compatible string to align with driver
>> 
>> CC: linux-watch...@vger.kernel.org
>> Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
> 
> I had a patch similar to this before
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325235.html

Whoops, your patch looks better. Will drop this one.

-M

Re: [PATCH 06/17] watchdog: qcom: update device tree bindings

[Matthew McClintock]

> On Mar 23, 2016, at 5:26 PM, Stephen Boyd  wrote:
> 
> On 03/23/2016 03:05 PM, Matthew McClintock wrote:
>> Update the compatible string to align with driver
>> 
>> CC: linux-watch...@vger.kernel.org
>> Signed-off-by: Matthew McClintock 
> 
> I had a patch similar to this before
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325235.html

Whoops, your patch looks better. Will drop this one.

-M

Re: [PATCH 08/17] watchdog: qcom: configure BARK time in addition to BITE time

[Matthew McClintock]

On Mar 23, 2016, at 5:42 PM, Stephen Boyd <sb...@codeaurora.org> wrote:
> 
> On 03/23, Matthew McClintock wrote:
>> For certain parts and some versions of TZ, TZ will reset the chip
>> when a BARK is triggered even though it was not configured here. So
>> by default let's configure this BARK time as well.
>> 
> 
> Why isn't TZ configuring the bark time to what it wants? I'm lost
> why we have to do this for them.

So it was done like this to ensure we had a valid upgrade. The bootloader is 
using the watchdog to ensure the system is bootable and if not it will revert 
back to the working images.

Bottom line is, for some versions of TZ out there, if we enable watchdog coming 
out of boot the bark time is already configured by the boot loader and TZ is 
configured to intercept this interrupt and do some register saving (for 
crashdump) and we end up getting a watchdog reset during boot.

It’s even a little more complex, because in order for the TZ to save the 
registers you need to pad the BITE time a bit higher than the BARK time, but I 
was leaving that for another day.

-M

Re: [PATCH 08/17] watchdog: qcom: configure BARK time in addition to BITE time

[Matthew McClintock]

On Mar 23, 2016, at 5:42 PM, Stephen Boyd  wrote:
> 
> On 03/23, Matthew McClintock wrote:
>> For certain parts and some versions of TZ, TZ will reset the chip
>> when a BARK is triggered even though it was not configured here. So
>> by default let's configure this BARK time as well.
>> 
> 
> Why isn't TZ configuring the bark time to what it wants? I'm lost
> why we have to do this for them.

So it was done like this to ensure we had a valid upgrade. The bootloader is 
using the watchdog to ensure the system is bootable and if not it will revert 
back to the working images.

Bottom line is, for some versions of TZ out there, if we enable watchdog coming 
out of boot the bark time is already configured by the boot loader and TZ is 
configured to intercept this interrupt and do some register saving (for 
crashdump) and we end up getting a watchdog reset during boot.

It’s even a little more complex, because in order for the TZ to save the 
registers you need to pad the BITE time a bit higher than the BARK time, but I 
was leaving that for another day.

-M

Re: [PATCH 14/17] cpufreq: ipq4019: add cpufreq driver

[Matthew McClintock]

On Mar 24, 2016, at 1:44 AM, Viresh Kumar <viresh.ku...@linaro.org> wrote:
> 
> On 23-03-16, 17:05, Matthew McClintock wrote:
>> Add cpufreq driver for ipq4019 SoC. This driver simply instantiates
>> cpufreq-dt.
>> 
>> Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
>> ---
>> drivers/cpufreq/Kconfig.arm   |  9 +
>> drivers/cpufreq/Makefile  |  1 +
>> drivers/cpufreq/ipq4019-cpufreq.c | 35 +++
>> 3 files changed, 45 insertions(+)
>> create mode 100644 drivers/cpufreq/ipq4019-cpufreq.c
> 
> I have just sent a patchset and cc'd you:
> "[PATCH 0/3] cpufreq: dt: Create platform device from generic code"
> 
> and so this patch may get replaced now.

Cool, thanks. I will look at re-spinning with your changes.

-M

Re: [PATCH 14/17] cpufreq: ipq4019: add cpufreq driver

[Matthew McClintock]

On Mar 24, 2016, at 1:44 AM, Viresh Kumar  wrote:
> 
> On 23-03-16, 17:05, Matthew McClintock wrote:
>> Add cpufreq driver for ipq4019 SoC. This driver simply instantiates
>> cpufreq-dt.
>> 
>> Signed-off-by: Matthew McClintock 
>> ---
>> drivers/cpufreq/Kconfig.arm   |  9 +
>> drivers/cpufreq/Makefile  |  1 +
>> drivers/cpufreq/ipq4019-cpufreq.c | 35 +++
>> 3 files changed, 45 insertions(+)
>> create mode 100644 drivers/cpufreq/ipq4019-cpufreq.c
> 
> I have just sent a patchset and cc'd you:
> "[PATCH 0/3] cpufreq: dt: Create platform device from generic code"
> 
> and so this patch may get replaced now.

Cool, thanks. I will look at re-spinning with your changes.

-M

[PATCH 04/17] clk: qcom: ipq4019: switch remaining defines to enums

[Matthew McClintock]

When this was added not all the remaining defines were switched over to
use enums, so let's complete that process here

Reported-by: Stephen Boyd <sb...@codeaurora.org>
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 60 ++
 1 file changed, 25 insertions(+), 35 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 21def7f..38ada8d 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -129,20 +129,10 @@ static const char * const gcc_xo_ddr_500_200[] = {
 };
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-#define P_XO 0
-#define FE_PLL_200 1
-#define FE_PLL_500 2
-#define DDRC_PLL_666  3
-
-#define DDRC_PLL_666_SDCC  1
-#define FE_PLL_125_DLY 1
-
-#define FE_PLL_WCSS2G 1
-#define FE_PLL_WCSS5G 1
 
 static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
F(4800, P_XO, 1, 0, 0),
-   F(2, FE_PLL_200, 1, 0, 0),
+   F(2, P_FEPLL200, 1, 0, 0),
{ }
 };
 
@@ -334,15 +324,15 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = {
-   F(1843200, FE_PLL_200, 1, 144, 15625),
-   F(3686400, FE_PLL_200, 1, 288, 15625),
-   F(7372800, FE_PLL_200, 1, 576, 15625),
-   F(14745600, FE_PLL_200, 1, 1152, 15625),
-   F(1600, FE_PLL_200, 1, 2, 25),
+   F(1843200, P_FEPLL200, 1, 144, 15625),
+   F(3686400, P_FEPLL200, 1, 288, 15625),
+   F(7372800, P_FEPLL200, 1, 576, 15625),
+   F(14745600, P_FEPLL200, 1, 1152, 15625),
+   F(1600, P_FEPLL200, 1, 2, 25),
F(2400, P_XO, 1, 1, 2),
-   F(3200, FE_PLL_200, 1, 4, 25),
-   F(4000, FE_PLL_200, 1, 1, 5),
-   F(4640, FE_PLL_200, 1, 29, 125),
+   F(3200, P_FEPLL200, 1, 4, 25),
+   F(4000, P_FEPLL200, 1, 1, 5),
+   F(4640, P_FEPLL200, 1, 29, 125),
F(4800, P_XO, 1, 0, 0),
{ }
 };
@@ -410,9 +400,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
-   F(125,  FE_PLL_200, 1, 16, 0),
-   F(250,  FE_PLL_200, 1,  8, 0),
-   F(500,  FE_PLL_200, 1,  4, 0),
+   F(125,  P_FEPLL200, 1, 16, 0),
+   F(250,  P_FEPLL200, 1,  8, 0),
+   F(500,  P_FEPLL200, 1,  4, 0),
{ }
 };
 
@@ -512,11 +502,11 @@ static struct clk_branch gcc_gp3_clk = {
 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
F(144000,P_XO,  1,  3, 240),
F(40,P_XO,  1,  1, 0),
-   F(2000,  FE_PLL_500,1,  1, 25),
-   F(2500,  FE_PLL_500,1,  1, 20),
-   F(5000,  FE_PLL_500,1,  1, 10),
-   F(1, FE_PLL_500,1,  1, 5),
-   F(19300, DDRC_PLL_666_SDCC, 1,  0, 0),
+   F(2000,  P_FEPLL500,1,  1, 25),
+   F(2500,  P_FEPLL500,1,  1, 20),
+   F(5000,  P_FEPLL500,1,  1, 10),
+   F(1, P_FEPLL500,1,  1, 5),
+   F(19300, P_DDRPLL,  1,  0, 0),
{ }
 };
 
@@ -536,9 +526,9 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
 
 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
F(4800, P_XO,  1, 0, 0),
-   F(2, FE_PLL_200,   1, 0, 0),
-   F(5, FE_PLL_500,   1, 0, 0),
-   F(62600, DDRC_PLL_666, 1, 0, 0),
+   F(2, P_FEPLL200,   1, 0, 0),
+   F(5, P_FEPLL500,   1, 0, 0),
+   F(62600, P_DDRPLLAPSS, 1, 0, 0),
{ }
 };
 
@@ -557,7 +547,7 @@ static struct clk_rcg2 apps_clk_src = {
 
 static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = {
F(4800, P_XO,  1, 0, 0),
-   F(1, FE_PLL_200,   2, 0, 0),
+   F(1, P_FEPLL200,   2, 0, 0),
{ }
 };
 
@@ -941,7 +931,7 @@ static struct clk_branch gcc_usb2_mock_utmi_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
-   F(200, FE_PLL_200, 10, 0, 0),
+   F(200, P_FEPLL200, 10, 0, 0),
{ }
 };
 
@@ -1008,7 +998,7 @@ static struct clk_branch gcc_usb3_mock_utmi_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = {
-   F(12500, FE_PLL_125_DLY, 1, 0, 0),
+   F(12500, P_FEPLL125DLY, 1, 0, 0),
{ }
 };
 
@@ -1028,7 +1018,7 @@ static struct clk_rcg2 fephy_125m_dly_clk_src = {
 
 static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = {
F(4800, P_XO, 1, 0, 0),
-   F(25000, FE_PLL_WCSS2G, 1, 0, 0),
+   F(25000, P_FEPLLWCSS2G, 1, 0, 0),
{ }
 };
 
@@ -1098,7 +1088,7 @@ static struct clk_branch gcc_wcss2g_rtc_clk = {
 
 static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = {
F(4800, P_XO, 1, 0, 0),
-  

[PATCH 04/17] clk: qcom: ipq4019: switch remaining defines to enums

[Matthew McClintock]

When this was added not all the remaining defines were switched over to
use enums, so let's complete that process here

Reported-by: Stephen Boyd 
Signed-off-by: Matthew McClintock 
---
 drivers/clk/qcom/gcc-ipq4019.c | 60 ++
 1 file changed, 25 insertions(+), 35 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 21def7f..38ada8d 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -129,20 +129,10 @@ static const char * const gcc_xo_ddr_500_200[] = {
 };
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-#define P_XO 0
-#define FE_PLL_200 1
-#define FE_PLL_500 2
-#define DDRC_PLL_666  3
-
-#define DDRC_PLL_666_SDCC  1
-#define FE_PLL_125_DLY 1
-
-#define FE_PLL_WCSS2G 1
-#define FE_PLL_WCSS5G 1
 
 static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
F(4800, P_XO, 1, 0, 0),
-   F(2, FE_PLL_200, 1, 0, 0),
+   F(2, P_FEPLL200, 1, 0, 0),
{ }
 };
 
@@ -334,15 +324,15 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = {
-   F(1843200, FE_PLL_200, 1, 144, 15625),
-   F(3686400, FE_PLL_200, 1, 288, 15625),
-   F(7372800, FE_PLL_200, 1, 576, 15625),
-   F(14745600, FE_PLL_200, 1, 1152, 15625),
-   F(1600, FE_PLL_200, 1, 2, 25),
+   F(1843200, P_FEPLL200, 1, 144, 15625),
+   F(3686400, P_FEPLL200, 1, 288, 15625),
+   F(7372800, P_FEPLL200, 1, 576, 15625),
+   F(14745600, P_FEPLL200, 1, 1152, 15625),
+   F(1600, P_FEPLL200, 1, 2, 25),
F(2400, P_XO, 1, 1, 2),
-   F(3200, FE_PLL_200, 1, 4, 25),
-   F(4000, FE_PLL_200, 1, 1, 5),
-   F(4640, FE_PLL_200, 1, 29, 125),
+   F(3200, P_FEPLL200, 1, 4, 25),
+   F(4000, P_FEPLL200, 1, 1, 5),
+   F(4640, P_FEPLL200, 1, 29, 125),
F(4800, P_XO, 1, 0, 0),
{ }
 };
@@ -410,9 +400,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
-   F(125,  FE_PLL_200, 1, 16, 0),
-   F(250,  FE_PLL_200, 1,  8, 0),
-   F(500,  FE_PLL_200, 1,  4, 0),
+   F(125,  P_FEPLL200, 1, 16, 0),
+   F(250,  P_FEPLL200, 1,  8, 0),
+   F(500,  P_FEPLL200, 1,  4, 0),
{ }
 };
 
@@ -512,11 +502,11 @@ static struct clk_branch gcc_gp3_clk = {
 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
F(144000,P_XO,  1,  3, 240),
F(40,P_XO,  1,  1, 0),
-   F(2000,  FE_PLL_500,1,  1, 25),
-   F(2500,  FE_PLL_500,1,  1, 20),
-   F(5000,  FE_PLL_500,1,  1, 10),
-   F(1, FE_PLL_500,1,  1, 5),
-   F(19300, DDRC_PLL_666_SDCC, 1,  0, 0),
+   F(2000,  P_FEPLL500,1,  1, 25),
+   F(2500,  P_FEPLL500,1,  1, 20),
+   F(5000,  P_FEPLL500,1,  1, 10),
+   F(1, P_FEPLL500,1,  1, 5),
+   F(19300, P_DDRPLL,  1,  0, 0),
{ }
 };
 
@@ -536,9 +526,9 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
 
 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
F(4800, P_XO,  1, 0, 0),
-   F(2, FE_PLL_200,   1, 0, 0),
-   F(5, FE_PLL_500,   1, 0, 0),
-   F(62600, DDRC_PLL_666, 1, 0, 0),
+   F(2, P_FEPLL200,   1, 0, 0),
+   F(5, P_FEPLL500,   1, 0, 0),
+   F(62600, P_DDRPLLAPSS, 1, 0, 0),
{ }
 };
 
@@ -557,7 +547,7 @@ static struct clk_rcg2 apps_clk_src = {
 
 static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = {
F(4800, P_XO,  1, 0, 0),
-   F(1, FE_PLL_200,   2, 0, 0),
+   F(1, P_FEPLL200,   2, 0, 0),
{ }
 };
 
@@ -941,7 +931,7 @@ static struct clk_branch gcc_usb2_mock_utmi_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
-   F(200, FE_PLL_200, 10, 0, 0),
+   F(200, P_FEPLL200, 10, 0, 0),
{ }
 };
 
@@ -1008,7 +998,7 @@ static struct clk_branch gcc_usb3_mock_utmi_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = {
-   F(12500, FE_PLL_125_DLY, 1, 0, 0),
+   F(12500, P_FEPLL125DLY, 1, 0, 0),
{ }
 };
 
@@ -1028,7 +1018,7 @@ static struct clk_rcg2 fephy_125m_dly_clk_src = {
 
 static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = {
F(4800, P_XO, 1, 0, 0),
-   F(25000, FE_PLL_WCSS2G, 1, 0, 0),
+   F(25000, P_FEPLLWCSS2G, 1, 0, 0),
{ }
 };
 
@@ -1098,7 +1088,7 @@ static struct clk_branch gcc_wcss2g_rtc_clk = {
 
 static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = {
F(4800, P_XO, 1, 0, 0),
-   F(25000, FE_PLL_WCSS5G, 1, 0, 0),
+   F(25000

[PATCH 11/17] qcom: ipq4019: add support for reset via qcom,ps-hold

[Matthew McClintock]

This will allow these types of boards to be rebooted.

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 00a5e9e..acb851d 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -179,5 +179,10 @@
timeout-sec = <10>;
status = "disabled";
};
+
+   restart@4ab000 {
+   compatible = "qcom,pshold";
+   reg = <0x4ab000 0x4>;
+   };
};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 11/17] qcom: ipq4019: add support for reset via qcom,ps-hold

[Matthew McClintock]

This will allow these types of boards to be rebooted.

Signed-off-by: Matthew McClintock 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 00a5e9e..acb851d 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -179,5 +179,10 @@
timeout-sec = <10>;
status = "disabled";
};
+
+   restart@4ab000 {
+   compatible = "qcom,pshold";
+   reg = <0x4ab000 0x4>;
+   };
};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Matthew McClintock]

Update the compatible string to add new device tree binding

CC: linux-watch...@vger.kernel.org
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
index 60bb2f98..45b37cf 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -6,6 +6,7 @@ Required properties :
 
"qcom,kpss-timer"
"qcom,scss-timer"
+   "qcom,kpss-standalone"
 
 - reg : shall contain base register location and length
 - clocks : shall contain the input clock
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 06/17] watchdog: qcom: update device tree bindings

[Matthew McClintock]

Update the compatible string to align with driver

CC: linux-watch...@vger.kernel.org
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
index 4726924..60bb2f98 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -4,9 +4,8 @@ Qualcomm Krait Processor Sub-system (KPSS) Watchdog
 Required properties :
 - compatible : shall contain only one of the following:
 
-   "qcom,kpss-wdt-msm8960"
-   "qcom,kpss-wdt-apq8064"
-   "qcom,kpss-wdt-ipq8064"
+   "qcom,kpss-timer"
+   "qcom,scss-timer"
 
 - reg : shall contain base register location and length
 - clocks : shall contain the input clock
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Matthew McClintock]

Update the compatible string to add new device tree binding

CC: linux-watch...@vger.kernel.org
Signed-off-by: Matthew McClintock 
---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
index 60bb2f98..45b37cf 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -6,6 +6,7 @@ Required properties :
 
"qcom,kpss-timer"
"qcom,scss-timer"
+   "qcom,kpss-standalone"
 
 - reg : shall contain base register location and length
 - clocks : shall contain the input clock
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 06/17] watchdog: qcom: update device tree bindings

[Matthew McClintock]

Update the compatible string to align with driver

CC: linux-watch...@vger.kernel.org
Signed-off-by: Matthew McClintock 
---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt 
b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
index 4726924..60bb2f98 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -4,9 +4,8 @@ Qualcomm Krait Processor Sub-system (KPSS) Watchdog
 Required properties :
 - compatible : shall contain only one of the following:
 
-   "qcom,kpss-wdt-msm8960"
-   "qcom,kpss-wdt-apq8064"
-   "qcom,kpss-wdt-ipq8064"
+   "qcom,kpss-timer"
+   "qcom,scss-timer"
 
 - reg : shall contain base register location and length
 - clocks : shall contain the input clock
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

[Matthew McClintock]

Commit 0dfd582e026a ("watchdog: qcom: use timer devicetree binding") moved
to use the watchdog as a subset timer register block. Some devices have the
watchdog completely standalone with slightly different register offsets as
well so let's account for the differences here.

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 drivers/watchdog/qcom-wdt.c | 69 -
 1 file changed, 49 insertions(+), 20 deletions(-)

diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index 20563cc..e46f18d 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -19,17 +19,37 @@
 #include 
 #include 
 
-#define WDT_RST0x38
-#define WDT_EN 0x40
-#define WDT_BITE_TIME  0x5C
+enum wdt_reg {
+   WDT_RST,
+   WDT_EN,
+   WDT_BITE_TIME,
+};
+
+static const u32 reg_offset_data_apcs_tmr[] = {
+   [WDT_RST] = 0x38,
+   [WDT_EN] = 0x40,
+   [WDT_BITE_TIME] = 0x5C,
+};
+
+static const u32 reg_offset_data_kpss[] = {
+   [WDT_RST] = 0x4,
+   [WDT_EN] = 0x8,
+   [WDT_BITE_TIME] = 0x14,
+};
 
 struct qcom_wdt {
struct watchdog_device  wdd;
struct clk  *clk;
unsigned long   rate;
void __iomem*base;
+   const u32   *layout;
 };
 
+static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
+{
+   return wdt->base + wdt->layout[reg];
+}
+
 static inline
 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
 {
@@ -40,10 +60,10 @@ static int qcom_wdt_start(struct watchdog_device *wdd)
 {
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 
-   writel(0, wdt->base + WDT_EN);
-   writel(1, wdt->base + WDT_RST);
-   writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME);
-   writel(1, wdt->base + WDT_EN);
+   writel(0, wdt_addr(wdt, WDT_EN));
+   writel(1, wdt_addr(wdt, WDT_RST));
+   writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
+   writel(1, wdt_addr(wdt, WDT_EN));
return 0;
 }
 
@@ -51,7 +71,7 @@ static int qcom_wdt_stop(struct watchdog_device *wdd)
 {
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 
-   writel(0, wdt->base + WDT_EN);
+   writel(0, wdt_addr(wdt, WDT_EN));
return 0;
 }
 
@@ -59,7 +79,7 @@ static int qcom_wdt_ping(struct watchdog_device *wdd)
 {
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 
-   writel(1, wdt->base + WDT_RST);
+   writel(1, wdt_addr(wdt, WDT_RST));
return 0;
 }
 
@@ -82,10 +102,10 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, 
unsigned long action,
 */
timeout = 128 * wdt->rate / 1000;
 
-   writel(0, wdt->base + WDT_EN);
-   writel(1, wdt->base + WDT_RST);
-   writel(timeout, wdt->base + WDT_BITE_TIME);
-   writel(1, wdt->base + WDT_EN);
+   writel(0, wdt_addr(wdt, WDT_EN));
+   writel(1, wdt_addr(wdt, WDT_RST));
+   writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
+   writel(1, wdt_addr(wdt, WDT_EN));
 
/*
 * Actually make sure the above sequence hits hardware before sleeping.
@@ -112,14 +132,29 @@ static const struct watchdog_info qcom_wdt_info = {
.identity   = KBUILD_MODNAME,
 };
 
+static const struct of_device_id qcom_wdt_of_table[] = {
+   { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
+   { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
+   { .compatible = "qcom,kpss-standalone", .data = _offset_data_kpss},
+   { },
+};
+MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
+
 static int qcom_wdt_probe(struct platform_device *pdev)
 {
struct qcom_wdt *wdt;
struct resource *res;
struct device_node *np = pdev->dev.of_node;
+   const struct of_device_id *match;
u32 percpu_offset;
int ret;
 
+   match = of_match_node(qcom_wdt_of_table, np);
+   if (!match) {
+   dev_err(>dev, "Unsupported QCOM WDT module\n");
+   return -ENODEV;
+   }
+
wdt = devm_kzalloc(>dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
@@ -170,6 +205,7 @@ static int qcom_wdt_probe(struct platform_device *pdev)
wdt->wdd.min_timeout = 1;
wdt->wdd.max_timeout = 0x1000U / wdt->rate;
wdt->wdd.parent = >dev;
+   wdt->layout = match->data;
 
/*
 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
@@ -202,13 +238,6 @@ static int qcom_wdt_remove(struct platform_device *pdev)
return 0;
 }
 
-static const struct of_device_id qcom_wdt_of_table[] = {
-   { .compatible = "qcom,kpss-timer" },
-   { .compatible = "qcom,scss-timer" },
-   { },
-};
-MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
-
 static struct platf

[PATCH 13/17] qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This will allow boards to enable the I2C bus

CC: Sricharan R <srich...@qti.qualcomm.com>
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 99e64f4..1937edf 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,6 +25,7 @@
 
aliases {
spi0 = _0;
+   i2c0 = _0;
};
 
cpus {
@@ -126,6 +127,18 @@
status = "disabled";
};
 
+   i2c_0: i2c@78b7000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b7000 0x6000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+< GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
 acc0: clock-controller@b088000 {
 compatible = "qcom,kpss-acc-v1";
 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

[Matthew McClintock]

Commit 0dfd582e026a ("watchdog: qcom: use timer devicetree binding") moved
to use the watchdog as a subset timer register block. Some devices have the
watchdog completely standalone with slightly different register offsets as
well so let's account for the differences here.

Signed-off-by: Matthew McClintock 
---
 drivers/watchdog/qcom-wdt.c | 69 -
 1 file changed, 49 insertions(+), 20 deletions(-)

diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index 20563cc..e46f18d 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -19,17 +19,37 @@
 #include 
 #include 
 
-#define WDT_RST0x38
-#define WDT_EN 0x40
-#define WDT_BITE_TIME  0x5C
+enum wdt_reg {
+   WDT_RST,
+   WDT_EN,
+   WDT_BITE_TIME,
+};
+
+static const u32 reg_offset_data_apcs_tmr[] = {
+   [WDT_RST] = 0x38,
+   [WDT_EN] = 0x40,
+   [WDT_BITE_TIME] = 0x5C,
+};
+
+static const u32 reg_offset_data_kpss[] = {
+   [WDT_RST] = 0x4,
+   [WDT_EN] = 0x8,
+   [WDT_BITE_TIME] = 0x14,
+};
 
 struct qcom_wdt {
struct watchdog_device  wdd;
struct clk  *clk;
unsigned long   rate;
void __iomem*base;
+   const u32   *layout;
 };
 
+static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
+{
+   return wdt->base + wdt->layout[reg];
+}
+
 static inline
 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
 {
@@ -40,10 +60,10 @@ static int qcom_wdt_start(struct watchdog_device *wdd)
 {
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 
-   writel(0, wdt->base + WDT_EN);
-   writel(1, wdt->base + WDT_RST);
-   writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME);
-   writel(1, wdt->base + WDT_EN);
+   writel(0, wdt_addr(wdt, WDT_EN));
+   writel(1, wdt_addr(wdt, WDT_RST));
+   writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
+   writel(1, wdt_addr(wdt, WDT_EN));
return 0;
 }
 
@@ -51,7 +71,7 @@ static int qcom_wdt_stop(struct watchdog_device *wdd)
 {
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 
-   writel(0, wdt->base + WDT_EN);
+   writel(0, wdt_addr(wdt, WDT_EN));
return 0;
 }
 
@@ -59,7 +79,7 @@ static int qcom_wdt_ping(struct watchdog_device *wdd)
 {
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 
-   writel(1, wdt->base + WDT_RST);
+   writel(1, wdt_addr(wdt, WDT_RST));
return 0;
 }
 
@@ -82,10 +102,10 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, 
unsigned long action,
 */
timeout = 128 * wdt->rate / 1000;
 
-   writel(0, wdt->base + WDT_EN);
-   writel(1, wdt->base + WDT_RST);
-   writel(timeout, wdt->base + WDT_BITE_TIME);
-   writel(1, wdt->base + WDT_EN);
+   writel(0, wdt_addr(wdt, WDT_EN));
+   writel(1, wdt_addr(wdt, WDT_RST));
+   writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
+   writel(1, wdt_addr(wdt, WDT_EN));
 
/*
 * Actually make sure the above sequence hits hardware before sleeping.
@@ -112,14 +132,29 @@ static const struct watchdog_info qcom_wdt_info = {
.identity   = KBUILD_MODNAME,
 };
 
+static const struct of_device_id qcom_wdt_of_table[] = {
+   { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
+   { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
+   { .compatible = "qcom,kpss-standalone", .data = _offset_data_kpss},
+   { },
+};
+MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
+
 static int qcom_wdt_probe(struct platform_device *pdev)
 {
struct qcom_wdt *wdt;
struct resource *res;
struct device_node *np = pdev->dev.of_node;
+   const struct of_device_id *match;
u32 percpu_offset;
int ret;
 
+   match = of_match_node(qcom_wdt_of_table, np);
+   if (!match) {
+   dev_err(>dev, "Unsupported QCOM WDT module\n");
+   return -ENODEV;
+   }
+
wdt = devm_kzalloc(>dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
@@ -170,6 +205,7 @@ static int qcom_wdt_probe(struct platform_device *pdev)
wdt->wdd.min_timeout = 1;
wdt->wdd.max_timeout = 0x1000U / wdt->rate;
wdt->wdd.parent = >dev;
+   wdt->layout = match->data;
 
/*
 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
@@ -202,13 +238,6 @@ static int qcom_wdt_remove(struct platform_device *pdev)
return 0;
 }
 
-static const struct of_device_id qcom_wdt_of_table[] = {
-   { .compatible = "qcom,kpss-timer" },
-   { .compatible = "qcom,scss-timer" },
-   { },
-};
-MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
-
 static struct platform_driver qcom_watchdog_driver

[PATCH 13/17] qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This will allow boards to enable the I2C bus

CC: Sricharan R 
Signed-off-by: Matthew McClintock 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 99e64f4..1937edf 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,6 +25,7 @@
 
aliases {
spi0 = _0;
+   i2c0 = _0;
};
 
cpus {
@@ -126,6 +127,18 @@
status = "disabled";
};
 
+   i2c_0: i2c@78b7000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b7000 0x6000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+< GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
 acc0: clock-controller@b088000 {
 compatible = "qcom,kpss-acc-v1";
 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 10/17] qcom: ipq4019: add watchdog node to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This will allow boards to enable watchdog support

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 8 
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index fe78f3f..223da1a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -55,5 +55,9 @@
pinctrl-names = "default";
status = "ok";
};
+
+   watchdog@b017000 {
+   status = "ok";
+   };
};
 };
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index e44f5b6..00a5e9e 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -171,5 +171,13 @@
< GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
+
+   watchdog@b017000 {
+   compatible = "qcom,kpss-standalone";
+   reg = <0xb017000 0x40>;
+   clocks = <_clk>;
+   timeout-sec = <10>;
+   status = "disabled";
+   };
};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 12/17] qcom: ipq4019: add spi node to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This will allow boards to enable the SPI bus

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 37 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 18 +
 2 files changed, 55 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 223da1a..21032a8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -48,6 +48,43 @@
bias-disable;
};
};
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio55", "gpio56", "gpio57";
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio54";
+   };
+   pinconf {
+   pins = "gpio55", "gpio56", "gpio57";
+   drive-strength = <12>;
+   bias-disable;
+   };
+   pinconf_cs {
+   pins = "gpio54";
+   drive-strength = <2>;
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   spi_0: spi@78b5000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = < 54 0>;
+
+   mx25l25635e@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "mx25l25635e";
+   spi-max-frequency = <2400>;
+   };
};
 
serial@78af000 {
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index acb851d..99e64f4 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -15,12 +15,18 @@
 
 #include "skeleton.dtsi"
 #include 
+#include 
+#include 
 
 / {
model = "Qualcomm Technologies, Inc. IPQ4019";
compatible = "qcom,ipq4019";
interrupt-parent = <>;
 
+   aliases {
+   spi0 = _0;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -108,6 +114,18 @@
interrupts = <0 208 0>;
};
 
+   spi_0: spi@78b5000 {
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b5000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+< GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
 acc0: clock-controller@b088000 {
 compatible = "qcom,kpss-acc-v1";
 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 10/17] qcom: ipq4019: add watchdog node to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This will allow boards to enable watchdog support

Signed-off-by: Matthew McClintock 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 8 
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index fe78f3f..223da1a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -55,5 +55,9 @@
pinctrl-names = "default";
status = "ok";
};
+
+   watchdog@b017000 {
+   status = "ok";
+   };
};
 };
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index e44f5b6..00a5e9e 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -171,5 +171,13 @@
< GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
+
+   watchdog@b017000 {
+   compatible = "qcom,kpss-standalone";
+   reg = <0xb017000 0x40>;
+   clocks = <_clk>;
+   timeout-sec = <10>;
+   status = "disabled";
+   };
};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 12/17] qcom: ipq4019: add spi node to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This will allow boards to enable the SPI bus

Signed-off-by: Matthew McClintock 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 37 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 18 +
 2 files changed, 55 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 223da1a..21032a8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -48,6 +48,43 @@
bias-disable;
};
};
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio55", "gpio56", "gpio57";
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio54";
+   };
+   pinconf {
+   pins = "gpio55", "gpio56", "gpio57";
+   drive-strength = <12>;
+   bias-disable;
+   };
+   pinconf_cs {
+   pins = "gpio54";
+   drive-strength = <2>;
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   spi_0: spi@78b5000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = < 54 0>;
+
+   mx25l25635e@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "mx25l25635e";
+   spi-max-frequency = <2400>;
+   };
};
 
serial@78af000 {
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index acb851d..99e64f4 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -15,12 +15,18 @@
 
 #include "skeleton.dtsi"
 #include 
+#include 
+#include 
 
 / {
model = "Qualcomm Technologies, Inc. IPQ4019";
compatible = "qcom,ipq4019";
interrupt-parent = <>;
 
+   aliases {
+   spi0 = _0;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -108,6 +114,18 @@
interrupts = <0 208 0>;
};
 
+   spi_0: spi@78b5000 {
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b5000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+< GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
 acc0: clock-controller@b088000 {
 compatible = "qcom,kpss-acc-v1";
 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 16/17] qcom: ipq4019: add crypto nodes to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This adds the crypto nodes to the ipq4019 device tree, it also adds the
BAM node used by crypto as well which the driver currently requires to
operate properly

The crypto driver itself depends on some other patches to qcom_bam_dma
to function properly:

https://lkml.org/lkml/2015/12/1/113

CC: Stanimir Varbanov <svarba...@mm-sol.com>
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |  8 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 25 +
 2 files changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 21032a8..2c347ad 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -93,6 +93,14 @@
status = "ok";
};
 
+   cryptobam: dma@8e04000 {
+   status = "ok";
+   };
+
+   crypto@8e3a000 {
+   status = "ok";
+   };
+
watchdog@b017000 {
status = "ok";
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index db48fd3..3cd42c0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -147,6 +147,31 @@
status = "disabled";
};
 
+
+   cryptobam: dma@8e04000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x08e04000 0x2>;
+   interrupts = ;
+   clocks = < GCC_CRYPTO_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <1>;
+   qcom,controlled-remotely;
+   status = "disabled";
+   };
+
+   crypto@8e3a000 {
+   compatible = "qcom,crypto-v5.1";
+   reg = <0x08e3a000 0x6000>;
+   clocks = < GCC_CRYPTO_AHB_CLK>,
+< GCC_CRYPTO_AXI_CLK>,
+< GCC_CRYPTO_CLK>;
+   clock-names = "iface", "bus", "core";
+   dmas = < 2>, < 3>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
 acc0: clock-controller@b088000 {
 compatible = "qcom,kpss-acc-v1";
 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 15/17] qcom: ipq4019: add cpu operating points for cpufreq support

[Matthew McClintock]

This adds some operating points for cpu frequeny scaling

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1937edf..db48fd3 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -40,6 +40,14 @@
reg = <0x0>;
clocks = < GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
+   operating-points = <
+   /* kHz  uV (fixed) */
+   48000   110
+   20  110
+   50  110
+   666000  110
+   >;
+   clock-latency = <256000>;
};
 
cpu@1 {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 15/17] qcom: ipq4019: add cpu operating points for cpufreq support

[Matthew McClintock]

This adds some operating points for cpu frequeny scaling

Signed-off-by: Matthew McClintock 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1937edf..db48fd3 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -40,6 +40,14 @@
reg = <0x0>;
clocks = < GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
+   operating-points = <
+   /* kHz  uV (fixed) */
+   48000   110
+   20  110
+   50  110
+   666000  110
+   >;
+   clock-latency = <256000>;
};
 
cpu@1 {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 16/17] qcom: ipq4019: add crypto nodes to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This adds the crypto nodes to the ipq4019 device tree, it also adds the
BAM node used by crypto as well which the driver currently requires to
operate properly

The crypto driver itself depends on some other patches to qcom_bam_dma
to function properly:

https://lkml.org/lkml/2015/12/1/113

CC: Stanimir Varbanov 
Signed-off-by: Matthew McClintock 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |  8 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 25 +
 2 files changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 21032a8..2c347ad 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -93,6 +93,14 @@
status = "ok";
};
 
+   cryptobam: dma@8e04000 {
+   status = "ok";
+   };
+
+   crypto@8e3a000 {
+   status = "ok";
+   };
+
watchdog@b017000 {
status = "ok";
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index db48fd3..3cd42c0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -147,6 +147,31 @@
status = "disabled";
};
 
+
+   cryptobam: dma@8e04000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x08e04000 0x2>;
+   interrupts = ;
+   clocks = < GCC_CRYPTO_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <1>;
+   qcom,controlled-remotely;
+   status = "disabled";
+   };
+
+   crypto@8e3a000 {
+   compatible = "qcom,crypto-v5.1";
+   reg = <0x08e3a000 0x6000>;
+   clocks = < GCC_CRYPTO_AHB_CLK>,
+< GCC_CRYPTO_AXI_CLK>,
+< GCC_CRYPTO_CLK>;
+   clock-names = "iface", "bus", "core";
+   dmas = < 2>, < 3>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
 acc0: clock-controller@b088000 {
 compatible = "qcom,kpss-acc-v1";
 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 14/17] cpufreq: ipq4019: add cpufreq driver

[Matthew McClintock]

Add cpufreq driver for ipq4019 SoC. This driver simply instantiates
cpufreq-dt.

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 drivers/cpufreq/Kconfig.arm   |  9 +
 drivers/cpufreq/Makefile  |  1 +
 drivers/cpufreq/ipq4019-cpufreq.c | 35 +++
 3 files changed, 45 insertions(+)
 create mode 100644 drivers/cpufreq/ipq4019-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 14b1f93..187803d 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -69,6 +69,15 @@ config ARM_IMX6Q_CPUFREQ
 
  If in doubt, say N.
 
+config ARM_IPQ4019_CPUFREQ
+tristate "Qualcomm IPQ4019 cpufreq support"
+   depends on ARCH_QCOM && CPUFREQ_DT
+select PM_OPP
+help
+ This adds cpufreq driver support for Qualcomm IPQ4019 series SoCs.
+
+  If in doubt, say N.
+
 config ARM_INTEGRATOR
tristate "CPUfreq driver for ARM Integrator CPUs"
depends on ARCH_INTEGRATOR
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 9e63fb1..8ed4cdb 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ)  += exynos5440-cpufreq.o
 obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
 obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ)+= hisi-acpu-cpufreq.o
 obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
+obj-$(CONFIG_ARM_IPQ4019_CPUFREQ)  += ipq4019-cpufreq.o
 obj-$(CONFIG_ARM_INTEGRATOR)   += integrator-cpufreq.o
 obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
 obj-$(CONFIG_ARM_MT8173_CPUFREQ)   += mt8173-cpufreq.o
diff --git a/drivers/cpufreq/ipq4019-cpufreq.c 
b/drivers/cpufreq/ipq4019-cpufreq.c
new file mode 100644
index 000..6f7bba3
--- /dev/null
+++ b/drivers/cpufreq/ipq4019-cpufreq.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int __init ipq4019_cpufreq_driver_init(void)
+{
+   struct platform_device *pdev;
+
+   if (!of_machine_is_compatible("qcom,ipq4019"))
+   return -ENODEV;
+
+   pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
+   return PTR_ERR_OR_ZERO(pdev);
+}
+module_init(ipq4019_cpufreq_driver_init);
+
+MODULE_AUTHOR("Matthew McClintock <mmccl...@codeaurora.org>");
+MODULE_DESCRIPTION("ipq4019 cpufreq driver");
+MODULE_LICENSE("GPL");
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 08/17] watchdog: qcom: configure BARK time in addition to BITE time

[Matthew McClintock]

For certain parts and some versions of TZ, TZ will reset the chip
when a BARK is triggered even though it was not configured here. So
by default let's configure this BARK time as well.

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 drivers/watchdog/qcom-wdt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index e46f18d..53f57c3 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -22,18 +22,21 @@
 enum wdt_reg {
WDT_RST,
WDT_EN,
+   WDT_BARK_TIME,
WDT_BITE_TIME,
 };
 
 static const u32 reg_offset_data_apcs_tmr[] = {
[WDT_RST] = 0x38,
[WDT_EN] = 0x40,
+   [WDT_BARK_TIME] = 0x4C,
[WDT_BITE_TIME] = 0x5C,
 };
 
 static const u32 reg_offset_data_kpss[] = {
[WDT_RST] = 0x4,
[WDT_EN] = 0x8,
+   [WDT_BARK_TIME] = 0x10,
[WDT_BITE_TIME] = 0x14,
 };
 
@@ -62,6 +65,7 @@ static int qcom_wdt_start(struct watchdog_device *wdd)
 
writel(0, wdt_addr(wdt, WDT_EN));
writel(1, wdt_addr(wdt, WDT_RST));
+   writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
writel(1, wdt_addr(wdt, WDT_EN));
return 0;
@@ -104,6 +108,7 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, 
unsigned long action,
 
writel(0, wdt_addr(wdt, WDT_EN));
writel(1, wdt_addr(wdt, WDT_RST));
+   writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
writel(1, wdt_addr(wdt, WDT_EN));
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 14/17] cpufreq: ipq4019: add cpufreq driver

[Matthew McClintock]

Add cpufreq driver for ipq4019 SoC. This driver simply instantiates
cpufreq-dt.

Signed-off-by: Matthew McClintock 
---
 drivers/cpufreq/Kconfig.arm   |  9 +
 drivers/cpufreq/Makefile  |  1 +
 drivers/cpufreq/ipq4019-cpufreq.c | 35 +++
 3 files changed, 45 insertions(+)
 create mode 100644 drivers/cpufreq/ipq4019-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 14b1f93..187803d 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -69,6 +69,15 @@ config ARM_IMX6Q_CPUFREQ
 
  If in doubt, say N.
 
+config ARM_IPQ4019_CPUFREQ
+tristate "Qualcomm IPQ4019 cpufreq support"
+   depends on ARCH_QCOM && CPUFREQ_DT
+select PM_OPP
+help
+ This adds cpufreq driver support for Qualcomm IPQ4019 series SoCs.
+
+  If in doubt, say N.
+
 config ARM_INTEGRATOR
tristate "CPUfreq driver for ARM Integrator CPUs"
depends on ARCH_INTEGRATOR
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 9e63fb1..8ed4cdb 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ)  += exynos5440-cpufreq.o
 obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
 obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ)+= hisi-acpu-cpufreq.o
 obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
+obj-$(CONFIG_ARM_IPQ4019_CPUFREQ)  += ipq4019-cpufreq.o
 obj-$(CONFIG_ARM_INTEGRATOR)   += integrator-cpufreq.o
 obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
 obj-$(CONFIG_ARM_MT8173_CPUFREQ)   += mt8173-cpufreq.o
diff --git a/drivers/cpufreq/ipq4019-cpufreq.c 
b/drivers/cpufreq/ipq4019-cpufreq.c
new file mode 100644
index 000..6f7bba3
--- /dev/null
+++ b/drivers/cpufreq/ipq4019-cpufreq.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int __init ipq4019_cpufreq_driver_init(void)
+{
+   struct platform_device *pdev;
+
+   if (!of_machine_is_compatible("qcom,ipq4019"))
+   return -ENODEV;
+
+   pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
+   return PTR_ERR_OR_ZERO(pdev);
+}
+module_init(ipq4019_cpufreq_driver_init);
+
+MODULE_AUTHOR("Matthew McClintock ");
+MODULE_DESCRIPTION("ipq4019 cpufreq driver");
+MODULE_LICENSE("GPL");
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 08/17] watchdog: qcom: configure BARK time in addition to BITE time

[Matthew McClintock]

For certain parts and some versions of TZ, TZ will reset the chip
when a BARK is triggered even though it was not configured here. So
by default let's configure this BARK time as well.

Signed-off-by: Matthew McClintock 
---
 drivers/watchdog/qcom-wdt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index e46f18d..53f57c3 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -22,18 +22,21 @@
 enum wdt_reg {
WDT_RST,
WDT_EN,
+   WDT_BARK_TIME,
WDT_BITE_TIME,
 };
 
 static const u32 reg_offset_data_apcs_tmr[] = {
[WDT_RST] = 0x38,
[WDT_EN] = 0x40,
+   [WDT_BARK_TIME] = 0x4C,
[WDT_BITE_TIME] = 0x5C,
 };
 
 static const u32 reg_offset_data_kpss[] = {
[WDT_RST] = 0x4,
[WDT_EN] = 0x8,
+   [WDT_BARK_TIME] = 0x10,
[WDT_BITE_TIME] = 0x14,
 };
 
@@ -62,6 +65,7 @@ static int qcom_wdt_start(struct watchdog_device *wdd)
 
writel(0, wdt_addr(wdt, WDT_EN));
writel(1, wdt_addr(wdt, WDT_RST));
+   writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
writel(1, wdt_addr(wdt, WDT_EN));
return 0;
@@ -104,6 +108,7 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, 
unsigned long action,
 
writel(0, wdt_addr(wdt, WDT_EN));
writel(1, wdt_addr(wdt, WDT_RST));
+   writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
writel(1, wdt_addr(wdt, WDT_EN));
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 05/17] clk: qcom: ipq4019: add some fixed clocks for ddrppl and fepll

[Matthew McClintock]

Drivers for these don't exist yet so we will add them as fixed clocks
so we don't BUG() if we change clocks that reference these clocks.

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 38ada8d..f0b0a5a 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1316,6 +1316,16 @@ MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
 
 static int gcc_ipq4019_probe(struct platform_device *pdev)
 {
+   struct device *dev = >dev;
+
+   clk_register_fixed_rate(dev, "fepll125", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepll200", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepll500", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 66600);
+
return qcom_cc_probe(pdev, _ipq4019_desc);
 }
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 17/17] qcom: ipq4019: add DMA nodes to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This adds the blsp_dma node to the device tree and the required
properties for using DMA with serial

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |  4 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 15 +++
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 2c347ad..b9457dd2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -72,6 +72,10 @@
};
};
 
+   blsp_dma: dma@7884000 {
+   status = "ok";
+   };
+
spi_0: spi@78b5000 {
pinctrl-0 = <_0_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 3cd42c0..5c08d19 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -123,6 +123,17 @@
interrupts = <0 208 0>;
};
 
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x07884000 0x23000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   status = "disabled";
+   };
+
spi_0: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
@@ -224,6 +235,8 @@
clocks = < GCC_BLSP1_UART1_APPS_CLK>,
< GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   dmas = <_dma 1>, <_dma 0>;
+   dma-names = "rx", "tx";
};
 
serial@78b {
@@ -234,6 +247,8 @@
clocks = < GCC_BLSP1_UART2_APPS_CLK>,
< GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   dmas = <_dma 3>, <_dma 2>;
+   dma-names = "rx", "tx";
};
 
watchdog@b017000 {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 05/17] clk: qcom: ipq4019: add some fixed clocks for ddrppl and fepll

[Matthew McClintock]

Drivers for these don't exist yet so we will add them as fixed clocks
so we don't BUG() if we change clocks that reference these clocks.

Signed-off-by: Matthew McClintock 
---
 drivers/clk/qcom/gcc-ipq4019.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 38ada8d..f0b0a5a 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1316,6 +1316,16 @@ MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
 
 static int gcc_ipq4019_probe(struct platform_device *pdev)
 {
+   struct device *dev = >dev;
+
+   clk_register_fixed_rate(dev, "fepll125", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepll200", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "fepll500", "xo", 0, 2);
+   clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 66600);
+
return qcom_cc_probe(pdev, _ipq4019_desc);
 }
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 17/17] qcom: ipq4019: add DMA nodes to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This adds the blsp_dma node to the device tree and the required
properties for using DMA with serial

Signed-off-by: Matthew McClintock 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |  4 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 15 +++
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 2c347ad..b9457dd2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -72,6 +72,10 @@
};
};
 
+   blsp_dma: dma@7884000 {
+   status = "ok";
+   };
+
spi_0: spi@78b5000 {
pinctrl-0 = <_0_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 3cd42c0..5c08d19 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -123,6 +123,17 @@
interrupts = <0 208 0>;
};
 
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x07884000 0x23000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   status = "disabled";
+   };
+
spi_0: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
@@ -224,6 +235,8 @@
clocks = < GCC_BLSP1_UART1_APPS_CLK>,
< GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   dmas = <_dma 1>, <_dma 0>;
+   dma-names = "rx", "tx";
};
 
serial@78b {
@@ -234,6 +247,8 @@
clocks = < GCC_BLSP1_UART2_APPS_CLK>,
< GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   dmas = <_dma 3>, <_dma 2>;
+   dma-names = "rx", "tx";
};
 
watchdog@b017000 {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 01/17] pinctrl: qcom: ipq4019: set ngpios to correct value

[Matthew McClintock]

This should have been bumped to 100 when the extra pins
were added in the original pinctrl patch

CC: linus.wall...@linaro.org
CC: bjorn.anders...@linaro.org
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c 
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index b5d81ce..cb5f0a8 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -414,7 +414,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
.nfunctions = ARRAY_SIZE(ipq4019_functions),
.groups = ipq4019_groups,
.ngroups = ARRAY_SIZE(ipq4019_groups),
-   .ngpios = 70,
+   .ngpios = 100,
 };
 
 static int ipq4019_pinctrl_probe(struct platform_device *pdev)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets

[Matthew McClintock]

For this SoC the register offsets changed from previous versions to be
separated by a larger amount.

CC: linus.wall...@linaro.org
CC: bjorn.anders...@linaro.org
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c 
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index cb9f16a..b68ae42 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
qca_mux_##f14   \
},  \
.nfuncs = 15,   \
-   .ctl_reg = 0x1000 + 0x10 * id,  \
-   .io_reg = 0x1004 + 0x10 * id,   \
-   .intr_cfg_reg = 0x1008 + 0x10 * id, \
-   .intr_status_reg = 0x100c + 0x10 * id,  \
-   .intr_target_reg = 0x400 + 0x4 * id,\
+   .ctl_reg = 0x0 + 0x1000 * id,   \
+   .io_reg = 0x4 + 0x1000 * id,\
+   .intr_cfg_reg = 0x8 + 0x1000 * id,  \
+   .intr_status_reg = 0xc + 0x1000 * id,   \
+   .intr_target_reg = 0x8 + 0x1000 * id,   \
.mux_bit = 2,   \
.pull_bit = 0,  \
.drv_bit = 6,   \
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 02/17] pinctrl: qcom: ipq4019: fix the function enum for gpio mode

[Matthew McClintock]

Without this, we would fail to set the mode to gpio if trying to
configure for that mode

CC: linus.wall...@linaro.org
CC: bjorn.anders...@linaro.org
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c 
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index cb5f0a8..cb9f16a 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -237,7 +237,7 @@ DECLARE_QCA_GPIO_PINS(99);
.pins = gpio##id##_pins,\
.npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){   \
-   qca_mux_NA, /* gpio mode */ \
+   qca_mux_gpio, /* gpio mode */   \
qca_mux_##f1,   \
qca_mux_##f2,   \
qca_mux_##f3,   \
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 01/17] pinctrl: qcom: ipq4019: set ngpios to correct value

[Matthew McClintock]

This should have been bumped to 100 when the extra pins
were added in the original pinctrl patch

CC: linus.wall...@linaro.org
CC: bjorn.anders...@linaro.org
Signed-off-by: Matthew McClintock 
---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c 
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index b5d81ce..cb5f0a8 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -414,7 +414,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
.nfunctions = ARRAY_SIZE(ipq4019_functions),
.groups = ipq4019_groups,
.ngroups = ARRAY_SIZE(ipq4019_groups),
-   .ngpios = 70,
+   .ngpios = 100,
 };
 
 static int ipq4019_pinctrl_probe(struct platform_device *pdev)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets

[Matthew McClintock]

For this SoC the register offsets changed from previous versions to be
separated by a larger amount.

CC: linus.wall...@linaro.org
CC: bjorn.anders...@linaro.org
Signed-off-by: Matthew McClintock 
---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c 
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index cb9f16a..b68ae42 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
qca_mux_##f14   \
},  \
.nfuncs = 15,   \
-   .ctl_reg = 0x1000 + 0x10 * id,  \
-   .io_reg = 0x1004 + 0x10 * id,   \
-   .intr_cfg_reg = 0x1008 + 0x10 * id, \
-   .intr_status_reg = 0x100c + 0x10 * id,  \
-   .intr_target_reg = 0x400 + 0x4 * id,\
+   .ctl_reg = 0x0 + 0x1000 * id,   \
+   .io_reg = 0x4 + 0x1000 * id,\
+   .intr_cfg_reg = 0x8 + 0x1000 * id,  \
+   .intr_status_reg = 0xc + 0x1000 * id,   \
+   .intr_target_reg = 0x8 + 0x1000 * id,   \
.mux_bit = 2,   \
.pull_bit = 0,  \
.drv_bit = 6,   \
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 02/17] pinctrl: qcom: ipq4019: fix the function enum for gpio mode

[Matthew McClintock]

Without this, we would fail to set the mode to gpio if trying to
configure for that mode

CC: linus.wall...@linaro.org
CC: bjorn.anders...@linaro.org
Signed-off-by: Matthew McClintock 
---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c 
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index cb5f0a8..cb9f16a 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -237,7 +237,7 @@ DECLARE_QCA_GPIO_PINS(99);
.pins = gpio##id##_pins,\
.npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){   \
-   qca_mux_NA, /* gpio mode */ \
+   qca_mux_gpio, /* gpio mode */   \
qca_mux_##f1,   \
qca_mux_##f2,   \
qca_mux_##f3,   \
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 5/6] dts: ipq4019: Add support for IPQ4019 DK01 board

[Matthew McClintock]

On Feb 8, 2016, at 4:43 PM, Stephen Boyd <sb...@codeaurora.org> wrote:
> 
> On 11/19, Matthew McClintock wrote:
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
>> +compatible = "qcom,ipq4019";
>> +
>> +clocks {
>> +xo: xo {
>> +compatible = "fixed-clock";
>> +clock-frequency = <4800>;
>> +#clock-cells = <0>;
>> +};
>> +};
> 
> Is there a reason the xo is here and the sleep clk is in the SoC
> dtsi file? Both are board clocks so I would think they would be
> added in the same place.

I’m a little bit confused and I wanted to confirm. I can see the xo clock is on 
the board itself. However, the sleep_clk is not, can you clarify why they would 
both be in the same place?

-M

Re: [PATCH v3 5/6] dts: ipq4019: Add support for IPQ4019 DK01 board

[Matthew McClintock]

On Feb 8, 2016, at 4:43 PM, Stephen Boyd  wrote:
> 
> On 11/19, Matthew McClintock wrote:
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
>> +compatible = "qcom,ipq4019";
>> +
>> +clocks {
>> +xo: xo {
>> +compatible = "fixed-clock";
>> +clock-frequency = <4800>;
>> +#clock-cells = <0>;
>> +};
>> +};
> 
> Is there a reason the xo is here and the sleep clk is in the SoC
> dtsi file? Both are board clocks so I would think they would be
> added in the same place.

I’m a little bit confused and I wanted to confirm. I can see the xo clock is on 
the board itself. However, the sleep_clk is not, can you clarify why they would 
both be in the same place?

-M

Re: [PATCH v3 1/6] pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support

[Matthew McClintock]

> On Feb 16, 2016, at 8:54 AM, Linus Walleij <linus.wall...@linaro.org> wrote:
> 
> On Fri, Nov 20, 2015 at 12:19 AM, Matthew McClintock
> <mmccl...@qca.qualcomm.com> wrote:
> 
>> From: Varadarajan Narayanan <var...@codeaurora.org>
>> 
>> Add pinctrl driver support for IPQ4019 platform
>> 
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> Signed-off-by: Mathieu Olivari <math...@codeaurora.org>
>> Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
>> Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
>> ---
>> 
>> v3
>> - update example with actual values from dts
>> - add missing pins 71-99
>> - drop many functions and stick to basic functionality
> 
> Patch applied with all the ACKs and stuff, and dropped the .owner
> assignment as indicated by Björn in the process.

Thanks folks, do plan to add more pinctrl bits once things are validated!

Cheers,
-M

Re: [PATCH v3 1/6] pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support

[Matthew McClintock]

> On Feb 16, 2016, at 8:54 AM, Linus Walleij  wrote:
> 
> On Fri, Nov 20, 2015 at 12:19 AM, Matthew McClintock
>  wrote:
> 
>> From: Varadarajan Narayanan 
>> 
>> Add pinctrl driver support for IPQ4019 platform
>> 
>> Signed-off-by: Sricharan R 
>> Signed-off-by: Mathieu Olivari 
>> Signed-off-by: Varadarajan Narayanan 
>> Signed-off-by: Matthew McClintock 
>> ---
>> 
>> v3
>> - update example with actual values from dts
>> - add missing pins 71-99
>> - drop many functions and stick to basic functionality
> 
> Patch applied with all the ACKs and stuff, and dropped the .owner
> assignment as indicated by Björn in the process.

Thanks folks, do plan to add more pinctrl bits once things are validated!

Cheers,
-M

[PATCH v3 6/6] qcom: ipq4019: add acc and saw nodes to bring up secondary cores

[Matthew McClintock]

This adds the required device tree nodes to bring up the
secondary cores on the ipq4019 SoC.

Signed-off-by: Matthew McClintock 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index fc73822..e44f5b6 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -27,29 +27,45 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x0>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x1>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x2>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x3>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
};
 
@@ -92,6 +108,50 @@
interrupts = <0 208 0>;
};
 
+acc0: clock-controller@b088000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc1: clock-controller@b098000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc2: clock-controller@b0a8000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc3: clock-controller@b0b8000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+};
+
+saw0: regulator@b089000 {
+compatible = "qcom,saw2";
+reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw1: regulator@b099000 {
+compatible = "qcom,saw2";
+reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw2: regulator@b0a9000 {
+compatible = "qcom,saw2";
+reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw3: regulator@b0b9000 {
+compatible = "qcom,saw2";
+reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 6/6] qcom: ipq4019: add acc and saw nodes to bring up secondary cores

[Matthew McClintock]

This adds the required device tree nodes to bring up the
secondary cores on the ipq4019 SoC.

Signed-off-by: Matthew McClintock 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index fc73822..e44f5b6 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -27,29 +27,45 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x0>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x1>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x2>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x3>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
};
 
@@ -92,6 +108,50 @@
interrupts = <0 208 0>;
};
 
+acc0: clock-controller@b088000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc1: clock-controller@b098000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc2: clock-controller@b0a8000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc3: clock-controller@b0b8000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+};
+
+saw0: regulator@b089000 {
+compatible = "qcom,saw2";
+reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw1: regulator@b099000 {
+compatible = "qcom,saw2";
+reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw2: regulator@b0a9000 {
+compatible = "qcom,saw2";
+reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw3: regulator@b0b9000 {
+compatible = "qcom,saw2";
+reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 2/6] clk: qcom: Add IPQ4019 Global Clock Controller support

[Matthew McClintock]

From: Varadarajan Narayanan 

This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.

Signed-off-by: Pradeep Banavathi 
Signed-off-by: Senthilkumar N L 
Signed-off-by: Varadarajan Narayanan 
Signed-off-by: Matthew McClintock 
---

v3:
- fix unused variable from refactored code

v2:
- drop calls qcom_cc_remove, gcc_ipq4019_remove
- move defines into clk structs
- remove src,cfg in struct initializations
- make hex values lowercase
- clean up MODULE_ALIAS and MODULE_DESCRIPTION
- change tabs after define to spacein dt include files
- remove extra AUDIO_BLK_ARES define
- remove unneeded of_match_device from gcc_ipq4019_probe
- move sleep_clk and xo to soc and board level dts
- drop all the (not required) fixed-clocks for now
- combine reset dts include files into one overall dts include

 .../devicetree/bindings/clock/qcom,gcc.txt |1 +
 drivers/clk/qcom/Kconfig   |9 +
 drivers/clk/qcom/Makefile  |1 +
 drivers/clk/qcom/gcc-ipq4019.c | 1355 
 include/dt-bindings/clock/qcom,gcc-ipq4019.h   |  158 +++
 5 files changed, 1524 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-ipq4019.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 152dfaa..4c98ab3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -7,6 +7,7 @@ Required properties :
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
+   "qcom,gcc-ipq4019"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83a..085fc17 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -28,6 +28,15 @@ config APQ_MMCC_8084
  Say Y if you want to support multimedia devices such as display,
  graphics, video encode/decode, camera, etc.
 
+config IPQ_GCC_4019
+   tristate "IPQ4019 Global Clock Controller"
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the global clock controller on ipq4019 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
+
 config IPQ_GCC_806X
tristate "IPQ806x Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index fe62523..c88d92f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -13,6 +13,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
new file mode 100644
index 000..21def7f
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -0,0 +1,1355 @@
+/*
+ * Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+enum {
+   P_XO,
+   P_FEPLL200,
+   P_FEPLL500,
+   P_DDRPLL,
+   P_FEPLLWCSS2G,
+   P_FEPLLWCSS5G,
+   P_FEPLL125DLY,
+   P_DDRPLLAPSS,
+};
+
+static struct parent_map gcc_xo_200_500_map[] = {
+   { P_XO, 0 },
+   { P_FEPLL200, 1 },
+   { P_FEPLL500, 2 },
+};
+
+static const char * const gcc_xo_200_500[] = {
+   "xo",
+   "fepll200",
+   "fepll500",
+};
+
+static struct parent_map gcc_xo_200_map[] = {
+   {  P_XO, 0 },
+   {  P_FEPLL200, 1 },
+};
+
+static const char * const gcc_xo_200[] = {
+   "xo",
+   "fepll200",
+};
+
+static struct parent_map gcc_xo_200_spi_map[] = {

[PATCH v3 1/6] pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support

[Matthew McClintock]

From: Varadarajan Narayanan 

Add pinctrl driver support for IPQ4019 platform

Signed-off-by: Sricharan R 
Signed-off-by: Mathieu Olivari 
Signed-off-by: Varadarajan Narayanan 
Signed-off-by: Matthew McClintock 
---

v3
- update example with actual values from dts
- add missing pins 71-99
- drop many functions and stick to basic functionality

v2
- add a note in the device tree binding about the TLMM block

 .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt  |  74 
 drivers/pinctrl/qcom/Kconfig   |   8 +
 drivers/pinctrl/qcom/Makefile  |   1 +
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 454 +
 4 files changed, 537 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq4019.c

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
new file mode 100644
index 000..cfb8500
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
@@ -0,0 +1,74 @@
+Qualcomm Atheros IPQ4019 TLMM block
+
+This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
+platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
+
+Required properties:
+- compatible: "qcom,ipq4019-pinctrl"
+- reg: Should be the base address and length of the TLMM block.
+- interrupts: Should be the parent IRQ of the TLMM block.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells : Should be two.
+The first cell is the gpio pin number and the
+second cell is used for optional parameters.
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+ pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
+
+Non-empty subnodes must specify the 'pins' property.
+Note that not all properties are valid for all pins.
+
+
+Valid values for qcom,pins are:
+  gpio0-gpio99
+Supports mux, bias and drive-strength
+
+Valid values for qcom,function are:
+gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
+
+Example:
+
+   tlmm: pinctrl@100 {
+   compatible = "qcom,ipq4019-pinctrl";
+   reg = <0x100 0x30>;
+
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <0 208 0>;
+
+   serial_pins: serial_pinmux {
+   mux {
+   pins = "gpio60", "gpio61";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+   };
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 383263a..6b898ef 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -23,6 +23,14 @@ config PINCTRL_APQ8084
  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
  Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
 
+config PINCTRL_IPQ4019
+   tristate "Qualcomm IPQ4019 pin controller driver"
+   depends on GPIOLIB && OF
+   select PINCTRL_MSM
+   help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
+
 config PINCTRL_IPQ8064
tristate "Qualcomm I

[PATCH v3 4/6] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

[Matthew McClintock]

From: Matthew McClintock 

Add initial dts files and SoC support for IPQ4019

Signed-off-by: Varadarajan Narayanan 
---

v2
- add sleep_clk

 arch/arm/boot/dts/qcom-ipq4019.dtsi | 115 
 1 file changed, 115 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
new file mode 100644
index 000..fc73822
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019";
+   compatible = "qcom,ipq4019";
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x0>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x1>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x2>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x3>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+   };
+
+   clocks {
+   sleep_clk: sleep_clk {
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   #clock-cells = <0>;
+   };
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   compatible = "simple-bus";
+
+   intc: interrupt-controller@b00 {
+   compatible = "qcom,msm-qgic2";
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   reg = <0x0b00 0x1000>,
+   <0x0b002000 0x1000>;
+   };
+
+   gcc: clock-controller@180 {
+   compatible = "qcom,gcc-ipq4019";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   reg = <0x180 0x6>;
+   };
+
+   tlmm: pinctrl@0x0100 {
+   compatible = "qcom,ipq4019-pinctrl";
+   reg = <0x0100 0x30>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <0 208 0>;
+   };
+
+   serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = <0 107 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+
+   serial@78b {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b 0x200>;
+   interrupts = <0 108 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART2_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+   };
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 5/6] dts: ipq4019: Add support for IPQ4019 DK01 board

[Matthew McClintock]

From: Matthew McClintock 

Initial board support dts files for DK01 board.

Signed-off-by: Senthilkumar N L 
Signed-off-by: Varadarajan Narayanan 
---

v2
- add xo clock

 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   | 59 +
 3 files changed, 82 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..11b151e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -505,6 +505,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
+   qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
new file mode 100644
index 000..0d92f1b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -0,0 +1,22 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
new file mode 100644
index 000..fe78f3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -0,0 +1,59 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+   compatible = "qcom,ipq4019";
+
+   clocks {
+xo: xo {
+compatible = "fixed-clock";
+clock-frequency = <4800>;
+#clock-cells = <0>;
+};
+   };
+
+   soc {
+
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = <1 2 0xf08>,
+<1 3 0xf08>,
+<1 4 0xf08>,
+<1 1 0xf08>;
+   clock-frequency = <4800>;
+   };
+
+   pinctrl@0x0100 {
+   serial_pins: serial_pinmux {
+   mux {
+   pins = "gpio60", "gpio61";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 3/6] ARM: qcom: add IPQ4019 compatible match

[Matthew McClintock]

From: Matthew McClintock 

This will select qcom board type when the machine compatible is
qcom,ipq4019.

Signed-off-by: Matthew McClintock 
---
 arch/arm/mach-qcom/board.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index 6d8bbf7..b52a6bc 100644
--- a/arch/arm/mach-qcom/board.c
+++ b/arch/arm/mach-qcom/board.c
@@ -18,6 +18,7 @@ static const char * const qcom_dt_match[] __initconst = {
"qcom,apq8064",
"qcom,apq8074-dragonboard",
"qcom,apq8084",
+   "qcom,ipq4019",
"qcom,ipq8062",
"qcom,ipq8064",
"qcom,msm8660-surf",
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 0/6] arm: qcom: Add support for IPQ8014 family of SoCs

[Matthew McClintock]

This patch series adds basic support for IPQ8019 series of SoCs,
presently it just boots to prompt via serial but more functionality
will follow.

This is partially based off a previously submitted patch series from
Varada which can be found here:

https://patchwork.ozlabs.org/patch/509954/

The IPQ8019 has a Quad-Core ARM Cortex A7 with integrated Wifi, GMAC,
Swtich, USB, PCIe, and more..

v3 of this series adds one patch to bring up secondary cores

Changes:

pinctrl changes:
v3
- update example with actual values from dts
- add missing pins 71-99
- drop many functions and stick to basic functionality

v2
- add a note in the device tree binding about the TLMM block

gcc changes:
v3:
- fix unused variable from refactored code

v2:
- drop calls qcom_cc_remove, gcc_ipq4019_remove
- move defines into clk structs
- remove src,cfg in struct initializations
- make hex values lowercase
- clean up MODULE_ALIAS and MODULE_DESCRIPTION
- change tabs after define to spacein dt include files
- remove extra AUDIO_BLK_ARES define
- remove unneeded of_match_device from gcc_ipq4019_probe
- move sleep_clk and xo to soc and board level dts
- drop all the (not required) fixed-clocks for now
- combine reset dts include files into one overall dts include

SoC dts file:
v2
- add sleep_clk

Board dts file:
- add xo clock

Matthew McClintock (4):
  ARM: qcom: add IPQ4019 compatible match
  qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC
  dts: ipq4019: Add support for IPQ4019 DK01 board
  qcom: ipq4019: add acc and saw nodes to bring up secondary cores

Varadarajan Narayanan (2):
  pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support
  clk: qcom: Add IPQ4019 Global Clock Controller support

 .../devicetree/bindings/clock/qcom,gcc.txt |1 +
 .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt  |   74 ++
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts|   22 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi  |   59 +
 arch/arm/boot/dts/qcom-ipq4019.dtsi|  175 +++
 arch/arm/mach-qcom/board.c |1 +
 drivers/clk/qcom/Kconfig   |9 +
 drivers/clk/qcom/Makefile  |1 +
 drivers/clk/qcom/gcc-ipq4019.c | 1355 
 drivers/pinctrl/qcom/Kconfig   |8 +
 drivers/pinctrl/qcom/Makefile  |1 +
 drivers/pinctrl/qcom/pinctrl-ipq4019.c |  454 +++
 include/dt-bindings/clock/qcom,gcc-ipq4019.h   |  158 +++
 14 files changed, 2319 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi
 create mode 100644 drivers/clk/qcom/gcc-ipq4019.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq4019.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 6/6] qcom: ipq4019: add acc and saw nodes to bring up secondary cores

[Matthew McClintock]

This adds the required device tree nodes to bring up the
secondary cores on the ipq4019 SoC.

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index fc73822..e44f5b6 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -27,29 +27,45 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x0>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x1>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x2>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x3>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
};
 
@@ -92,6 +108,50 @@
interrupts = <0 208 0>;
};
 
+acc0: clock-controller@b088000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc1: clock-controller@b098000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc2: clock-controller@b0a8000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc3: clock-controller@b0b8000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+};
+
+saw0: regulator@b089000 {
+compatible = "qcom,saw2";
+reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw1: regulator@b099000 {
+compatible = "qcom,saw2";
+reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw2: regulator@b0a9000 {
+compatible = "qcom,saw2";
+reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw3: regulator@b0b9000 {
+compatible = "qcom,saw2";
+reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 6/6] qcom: ipq4019: add acc and saw nodes to bring up secondary cores

[Matthew McClintock]

This adds the required device tree nodes to bring up the
secondary cores on the ipq4019 SoC.

Signed-off-by: Matthew McClintock <mmccl...@qca.qualcomm.com>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index fc73822..e44f5b6 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -27,29 +27,45 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x0>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x1>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x2>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
 
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+   enable-method = "qcom,kpss-acc-v1";
+   qcom,acc = <>;
+   qcom,saw = <>;
reg = <0x3>;
clocks = < GCC_APPS_CLK_SRC>;
+   clock-frequency = <0>;
};
};
 
@@ -92,6 +108,50 @@
interrupts = <0 208 0>;
};
 
+acc0: clock-controller@b088000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc1: clock-controller@b098000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc2: clock-controller@b0a8000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+};
+
+acc3: clock-controller@b0b8000 {
+compatible = "qcom,kpss-acc-v1";
+reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+};
+
+saw0: regulator@b089000 {
+compatible = "qcom,saw2";
+reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw1: regulator@b099000 {
+compatible = "qcom,saw2";
+reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw2: regulator@b0a9000 {
+compatible = "qcom,saw2";
+reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
+saw3: regulator@b0b9000 {
+compatible = "qcom,saw2";
+reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
+regulator;
+};
+
serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 5/6] dts: ipq4019: Add support for IPQ4019 DK01 board

[Matthew McClintock]

From: Matthew McClintock <mmccl...@codeaurora.org>

Initial board support dts files for DK01 board.

Signed-off-by: Senthilkumar N L <snlak...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---

v2
- add xo clock

 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   | 59 +
 3 files changed, 82 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..11b151e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -505,6 +505,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
+   qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
new file mode 100644
index 000..0d92f1b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -0,0 +1,22 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
new file mode 100644
index 000..fe78f3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -0,0 +1,59 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+   compatible = "qcom,ipq4019";
+
+   clocks {
+xo: xo {
+compatible = "fixed-clock";
+clock-frequency = <4800>;
+#clock-cells = <0>;
+};
+   };
+
+   soc {
+
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = <1 2 0xf08>,
+<1 3 0xf08>,
+<1 4 0xf08>,
+<1 1 0xf08>;
+   clock-frequency = <4800>;
+   };
+
+   pinctrl@0x0100 {
+   serial_pins: serial_pinmux {
+   mux {
+   pins = "gpio60", "gpio61";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe 

[PATCH v3 4/6] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

[Matthew McClintock]

From: Matthew McClintock <mmccl...@codeaurora.org>

Add initial dts files and SoC support for IPQ4019

Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---

v2
- add sleep_clk

 arch/arm/boot/dts/qcom-ipq4019.dtsi | 115 
 1 file changed, 115 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
new file mode 100644
index 000..fc73822
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019";
+   compatible = "qcom,ipq4019";
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x0>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x1>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x2>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x3>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+   };
+
+   clocks {
+   sleep_clk: sleep_clk {
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   #clock-cells = <0>;
+   };
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   compatible = "simple-bus";
+
+   intc: interrupt-controller@b00 {
+   compatible = "qcom,msm-qgic2";
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   reg = <0x0b00 0x1000>,
+   <0x0b002000 0x1000>;
+   };
+
+   gcc: clock-controller@180 {
+   compatible = "qcom,gcc-ipq4019";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   reg = <0x180 0x6>;
+   };
+
+   tlmm: pinctrl@0x0100 {
+   compatible = "qcom,ipq4019-pinctrl";
+   reg = <0x0100 0x30>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <0 208 0>;
+   };
+
+   serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = <0 107 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+
+   serial@78b {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b 0x200>;
+   interrupts = <0 108 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART2_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+   };
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 1/6] pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support

[Matthew McClintock]

From: Varadarajan Narayanan <var...@codeaurora.org>

Add pinctrl driver support for IPQ4019 platform

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
Signed-off-by: Mathieu Olivari <math...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---

v3
- update example with actual values from dts
- add missing pins 71-99
- drop many functions and stick to basic functionality

v2
- add a note in the device tree binding about the TLMM block

 .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt  |  74 
 drivers/pinctrl/qcom/Kconfig   |   8 +
 drivers/pinctrl/qcom/Makefile  |   1 +
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 454 +
 4 files changed, 537 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq4019.c

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
new file mode 100644
index 000..cfb8500
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
@@ -0,0 +1,74 @@
+Qualcomm Atheros IPQ4019 TLMM block
+
+This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
+platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
+
+Required properties:
+- compatible: "qcom,ipq4019-pinctrl"
+- reg: Should be the base address and length of the TLMM block.
+- interrupts: Should be the parent IRQ of the TLMM block.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells : Should be two.
+The first cell is the gpio pin number and the
+second cell is used for optional parameters.
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+ pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
+
+Non-empty subnodes must specify the 'pins' property.
+Note that not all properties are valid for all pins.
+
+
+Valid values for qcom,pins are:
+  gpio0-gpio99
+Supports mux, bias and drive-strength
+
+Valid values for qcom,function are:
+gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
+
+Example:
+
+   tlmm: pinctrl@100 {
+   compatible = "qcom,ipq4019-pinctrl";
+   reg = <0x100 0x30>;
+
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <0 208 0>;
+
+   serial_pins: serial_pinmux {
+   mux {
+   pins = "gpio60", "gpio61";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+   };
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 383263a..6b898ef 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -23,6 +23,14 @@ config PINCTRL_APQ8084
  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
  Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
 
+config PINCTRL_IPQ4019
+   tristate "Qualcomm IPQ4019 pin controller driver"
+   depends on GPIOLIB && OF
+   select PINCTRL_MSM
+   help
+ This is the pinctrl, pinmux, pinconf and gpi

[PATCH v3 2/6] clk: qcom: Add IPQ4019 Global Clock Controller support

[Matthew McClintock]

From: Varadarajan Narayanan <var...@codeaurora.org>

This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.

Signed-off-by: Pradeep Banavathi <prade...@codeaurora.org>
Signed-off-by: Senthilkumar N L <snlak...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---

v3:
- fix unused variable from refactored code

v2:
- drop calls qcom_cc_remove, gcc_ipq4019_remove
- move defines into clk structs
- remove src,cfg in struct initializations
- make hex values lowercase
- clean up MODULE_ALIAS and MODULE_DESCRIPTION
- change tabs after define to spacein dt include files
- remove extra AUDIO_BLK_ARES define
- remove unneeded of_match_device from gcc_ipq4019_probe
- move sleep_clk and xo to soc and board level dts
- drop all the (not required) fixed-clocks for now
- combine reset dts include files into one overall dts include

 .../devicetree/bindings/clock/qcom,gcc.txt |1 +
 drivers/clk/qcom/Kconfig   |9 +
 drivers/clk/qcom/Makefile  |1 +
 drivers/clk/qcom/gcc-ipq4019.c | 1355 
 include/dt-bindings/clock/qcom,gcc-ipq4019.h   |  158 +++
 5 files changed, 1524 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-ipq4019.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 152dfaa..4c98ab3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -7,6 +7,7 @@ Required properties :
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
+   "qcom,gcc-ipq4019"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83a..085fc17 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -28,6 +28,15 @@ config APQ_MMCC_8084
  Say Y if you want to support multimedia devices such as display,
  graphics, video encode/decode, camera, etc.
 
+config IPQ_GCC_4019
+   tristate "IPQ4019 Global Clock Controller"
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the global clock controller on ipq4019 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
+
 config IPQ_GCC_806X
tristate "IPQ806x Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index fe62523..c88d92f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -13,6 +13,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
new file mode 100644
index 000..21def7f
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -0,0 +1,1355 @@
+/*
+ * Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+enum {
+   P_XO,
+   P_FEPLL200,
+   P_FEPLL500,
+   P_DDRPLL,
+   P_FEPLLWCSS2G,
+   P_FEPLLWCSS5G,
+   P_FEPLL125DLY,
+   P_DDRPLLAPSS,
+};
+
+static struct parent_map gcc_xo_200_500_map[] = {
+   { P_XO, 0 },
+   { P_FEPLL200, 1 },
+   { P_FEPLL500, 2 },
+};
+
+static const char * const gcc_xo_200_500[] = {
+   "xo",
+   "fepll200",
+   "fepll500",
+};
+
+static struct parent_map gcc_xo_200_map[] = {
+   {  P_XO, 0 },
+   {  P_FEPLL200, 1 },
+};
+
+static c

[PATCH v3 0/6] arm: qcom: Add support for IPQ8014 family of SoCs

[Matthew McClintock]

This patch series adds basic support for IPQ8019 series of SoCs,
presently it just boots to prompt via serial but more functionality
will follow.

This is partially based off a previously submitted patch series from
Varada which can be found here:

https://patchwork.ozlabs.org/patch/509954/

The IPQ8019 has a Quad-Core ARM Cortex A7 with integrated Wifi, GMAC,
Swtich, USB, PCIe, and more..

v3 of this series adds one patch to bring up secondary cores

Changes:

pinctrl changes:
v3
- update example with actual values from dts
- add missing pins 71-99
- drop many functions and stick to basic functionality

v2
- add a note in the device tree binding about the TLMM block

gcc changes:
v3:
- fix unused variable from refactored code

v2:
- drop calls qcom_cc_remove, gcc_ipq4019_remove
- move defines into clk structs
- remove src,cfg in struct initializations
- make hex values lowercase
- clean up MODULE_ALIAS and MODULE_DESCRIPTION
- change tabs after define to spacein dt include files
- remove extra AUDIO_BLK_ARES define
- remove unneeded of_match_device from gcc_ipq4019_probe
- move sleep_clk and xo to soc and board level dts
- drop all the (not required) fixed-clocks for now
- combine reset dts include files into one overall dts include

SoC dts file:
v2
- add sleep_clk

Board dts file:
- add xo clock

Matthew McClintock (4):
  ARM: qcom: add IPQ4019 compatible match
  qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC
  dts: ipq4019: Add support for IPQ4019 DK01 board
  qcom: ipq4019: add acc and saw nodes to bring up secondary cores

Varadarajan Narayanan (2):
  pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support
  clk: qcom: Add IPQ4019 Global Clock Controller support

 .../devicetree/bindings/clock/qcom,gcc.txt |1 +
 .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt  |   74 ++
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts|   22 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi  |   59 +
 arch/arm/boot/dts/qcom-ipq4019.dtsi|  175 +++
 arch/arm/mach-qcom/board.c |1 +
 drivers/clk/qcom/Kconfig   |9 +
 drivers/clk/qcom/Makefile  |1 +
 drivers/clk/qcom/gcc-ipq4019.c | 1355 
 drivers/pinctrl/qcom/Kconfig   |8 +
 drivers/pinctrl/qcom/Makefile  |1 +
 drivers/pinctrl/qcom/pinctrl-ipq4019.c |  454 +++
 include/dt-bindings/clock/qcom,gcc-ipq4019.h   |  158 +++
 14 files changed, 2319 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi
 create mode 100644 drivers/clk/qcom/gcc-ipq4019.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq4019.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 3/6] ARM: qcom: add IPQ4019 compatible match

[Matthew McClintock]

From: Matthew McClintock <mmccl...@codeaurora.org>

This will select qcom board type when the machine compatible is
qcom,ipq4019.

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/mach-qcom/board.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index 6d8bbf7..b52a6bc 100644
--- a/arch/arm/mach-qcom/board.c
+++ b/arch/arm/mach-qcom/board.c
@@ -18,6 +18,7 @@ static const char * const qcom_dt_match[] __initconst = {
"qcom,apq8064",
"qcom,apq8074-dragonboard",
"qcom,apq8084",
+   "qcom,ipq4019",
"qcom,ipq8062",
"qcom,ipq8064",
"qcom,msm8660-surf",
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 2/5] clk: qcom: Add IPQ4019 Global Clock Controller support

[Matthew McClintock]

From: Varadarajan Narayanan 

This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.

Signed-off-by: Pradeep Banavathi 
Signed-off-by: Senthilkumar N L 
Signed-off-by: Varadarajan Narayanan 
Signed-off-by: Matthew McClintock 
---

v2:
- drop calls qcom_cc_remove, gcc_ipq4019_remove
- move defines into clk structs
- remove src,cfg in struct initializations
- make hex values lowercase
- clean up MODULE_ALIAS and MODULE_DESCRIPTION
- change tabs after define to spacein dt include files
- remove extra AUDIO_BLK_ARES define
- remove unneeded of_match_device from gcc_ipq4019_probe
- move sleep_clk and xo to soc and board level dts
- drop all the (not required) fixed-clocks for now
- combine reset dts include files into one overall dts include

v3:
- fix unused variable from refactored code

 .../devicetree/bindings/clock/qcom,gcc.txt |1 +
 drivers/clk/qcom/Kconfig   |9 +
 drivers/clk/qcom/Makefile  |1 +
 drivers/clk/qcom/gcc-ipq4019.c | 1355 
 include/dt-bindings/clock/qcom,gcc-ipq4019.h   |  158 +++
 5 files changed, 1524 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-ipq4019.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 152dfaa..4c98ab3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -7,6 +7,7 @@ Required properties :
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
+   "qcom,gcc-ipq4019"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83a..085fc17 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -28,6 +28,15 @@ config APQ_MMCC_8084
  Say Y if you want to support multimedia devices such as display,
  graphics, video encode/decode, camera, etc.
 
+config IPQ_GCC_4019
+   tristate "IPQ4019 Global Clock Controller"
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the global clock controller on ipq4019 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
+
 config IPQ_GCC_806X
tristate "IPQ806x Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index fe62523..c88d92f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -13,6 +13,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
new file mode 100644
index 000..21def7f
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -0,0 +1,1355 @@
+/*
+ * Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+enum {
+   P_XO,
+   P_FEPLL200,
+   P_FEPLL500,
+   P_DDRPLL,
+   P_FEPLLWCSS2G,
+   P_FEPLLWCSS5G,
+   P_FEPLL125DLY,
+   P_DDRPLLAPSS,
+};
+
+static struct parent_map gcc_xo_200_500_map[] = {
+   { P_XO, 0 },
+   { P_FEPLL200, 1 },
+   { P_FEPLL500, 2 },
+};
+
+static const char * const gcc_xo_200_500[] = {
+   "xo",
+   "fepll200",
+   "fepll500",
+};
+
+static struct parent_map gcc_xo_200_map[] = {
+   {  P_XO, 0 },
+   {  P_FEPLL200, 1 },
+};
+
+static const char * const gcc_xo_200[] = {
+   "xo",
+   "fepll200",
+};
+
+static struct parent_map gcc_xo_200_spi_map[] = {

[PATCH v2 1/5] pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support

[Matthew McClintock]

From: Varadarajan Narayanan 

Add pinctrl driver support for IPQ4019 platform

Signed-off-by: Sricharan R 
Signed-off-by: Mathieu Olivari 
Signed-off-by: Varadarajan Narayanan 
Signed-off-by: Matthew McClintock 
---

v2 - add a note in the device tree binding about the TLMM block

 .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt  |  119 ++
 drivers/pinctrl/qcom/Kconfig   |8 +
 drivers/pinctrl/qcom/Makefile  |1 +
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1280 
 4 files changed, 1408 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq4019.c

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
new file mode 100644
index 000..ba8a2c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
@@ -0,0 +1,119 @@
+Qualcomm Atheros IPQ4019 TLMM block
+
+This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
+platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
+
+Required properties:
+- compatible: "qcom,ipq4019-pinctrl"
+- reg: Should be the base address and length of the TLMM block.
+- interrupts: Should be the parent IRQ of the TLMM block.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells : Should be two.
+The first cell is the gpio pin number and the
+second cell is used for optional parameters.
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+ pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
+
+Non-empty subnodes must specify the 'pins' property.
+Note that not all properties are valid for all pins.
+
+
+Valid values for qcom,pins are:
+  gpio0-gpio70
+Supports mux, bias and drive-strength
+
+sdio_cd, sdio_clk, sdio_cmd, sdio_data1, sdio_data1, sdio_data1, 
sdio_data1,
+sdio_data5, sdio_data6, sdio_data7
+
+Valid values for qcom,function are:
+smart0, jtag, audio0, mdio0, wcss0_dbg18, wcss1_dbg18, qdss_tracedata_a, mdc,
+wcss0_dbg19, wcss1_dbg19, blsp_uart1, wifi0_uart, wifi1_uart, smart1,
+wcss0_dbg20, wcss1_dbg20, wifi0_uart0, wifi1_uart0, wcss0_dbg21, wcss1_dbg21,
+blsp_i2c0, wcss0_dbg22, wcss1_dbg22, wcss0_dbg23, wcss1_dbg23, blsp_i2c1,
+wcss0_dbg24, wcss1_dbg24, wcss0_dbg25, wcss1_dbg25, pcie_rst, wcss0_dbg26,
+wcss1_dbg26, pcie_clk0, wcss0_dbg27, wcss1_dbg27, led0, blsp_uart0, led1,
+chip_irq0, wifi0_uart1, wifi1_uart1, wcss0_dbg28, wcss1_dbg28, chip_rst,
+audio_spdifout, sdio1, rgmii2, sdio2, rgmii3, sdio3, rgmii_rx, sdio_clk,
+wcss0_dbg29, wcss1_dbg29, wcss0_dbg16, wcss1_dbg16, audio1, wcss0_dbg17,
+wcss1_dbg17, sdio_cd, rgmii0, sdio0, rgmii1, rgmii_txc, audio_td1, sdio_cmd,
+audio_td2, sdio4, audio_td3, sdio5, audio_pwm0, sdio6, audio_pwm1, sdio7,
+rgmii_rxc, audio_pwm2, rgmii_tx, audio_pwm3, wcss0_dbg30, wcss1_dbg30,
+wcss0_dbg31, wcss1_dbg31, rmii00, led2, rmii01, wifi0_wci, wifi1_wci,
+rmii0_tx, rmii0_rx, pcie_clk1, led3, pcie_wakeup, rmii0_refclk,
+wifi0_rfsilient0, wifi1_rfsilient0, smart2, led4, wifi0_cal, wifi1_cal,
+wifi_wci0, rmii0_dv, wifi_wci1, rmii1_refclk, blsp_spi1, led5, rmii10,
+blsp_spi0, led6, rmii11, led7, rmii1_dv, led8, rmii1_tx, aud_pin, led9,
+rmii1_rx, led10, wifi0_rfsilient1, wifi1_rfsilient1, led11, qpic_pad,
+qdss_cti_trig_in_a0, mdio1, audio2, dbg_out, wcss0_dbg, wcss1_dbg, atest_char3,
+pmu0, wcss0_dbg0, wcss1_dbg0, atest_char2, pmu1, wcss0_dbg1, wcss1_dbg1,
+atest_char1, wcss0_dbg2, w

[PATCH v2 2/5] clk: qcom: Add IPQ4019 Global Clock Controller support

[Matthew McClintock]

From: Varadarajan Narayanan 

This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.

Signed-off-by: Pradeep Banavathi 
Signed-off-by: Senthilkumar N L 
Signed-off-by: Varadarajan Narayanan 
Signed-off-by: Matthew McClintock 
---

v2 - drop calls qcom_cc_remove, gcc_ipq4019_remove
   - move defines into clk structs
   - remove src,cfg in struct initializations
   - make hex values lowercase
   - clean up MODULE_ALIAS and MODULE_DESCRIPTION
   - change tabs after define to spacein dt include files
   - remove extra AUDIO_BLK_ARES define
   - remove unneeded of_match_device from gcc_ipq4019_probe
   - move sleep_clk and xo to soc and board level dts
   - drop all the (not required) fixed-clocks for now
   - combine reset dts include files into one overall dts include

 .../devicetree/bindings/clock/qcom,gcc.txt |1 +
 drivers/clk/qcom/Kconfig   |9 +
 drivers/clk/qcom/Makefile  |1 +
 drivers/clk/qcom/gcc-ipq4019.c | 1358 
 include/dt-bindings/clock/qcom,gcc-ipq4019.h   |  158 +++
 5 files changed, 1527 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-ipq4019.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 152dfaa..4c98ab3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -7,6 +7,7 @@ Required properties :
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
+   "qcom,gcc-ipq4019"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83a..085fc17 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -28,6 +28,15 @@ config APQ_MMCC_8084
  Say Y if you want to support multimedia devices such as display,
  graphics, video encode/decode, camera, etc.
 
+config IPQ_GCC_4019
+   tristate "IPQ4019 Global Clock Controller"
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the global clock controller on ipq4019 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
+
 config IPQ_GCC_806X
tristate "IPQ806x Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index fe62523..c88d92f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -13,6 +13,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
new file mode 100644
index 000..a2bbb91
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -0,0 +1,1358 @@
+/*
+ * Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+enum {
+   P_XO,
+   P_FEPLL200,
+   P_FEPLL500,
+   P_DDRPLL,
+   P_FEPLLWCSS2G,
+   P_FEPLLWCSS5G,
+   P_FEPLL125DLY,
+   P_DDRPLLAPSS,
+};
+
+static struct parent_map gcc_xo_200_500_map[] = {
+   { P_XO, 0 },
+   { P_FEPLL200, 1 },
+   { P_FEPLL500, 2 },
+};
+
+static const char * const gcc_xo_200_500[] = {
+   "xo",
+   "fepll200",
+   "fepll500",
+};
+
+static struct parent_map gcc_xo_200_map[] = {
+   {  P_XO, 0 },
+   {  P_FEPLL200, 1 },
+};
+
+static const char * const gcc_xo_200[] = {
+   "xo",
+   "fepll200",
+};
+
+static struct parent_map gcc_xo_200_spi_map[] = {
+   {  P_XO, 0 },

[PATCH v2 5/5] dts: ipq4019: Add support for IPQ4019 DK01 board

[Matthew McClintock]

From: Matthew McClintock 

Initial board support dts files for DK01 board.

Signed-off-by: Senthilkumar N L 
Signed-off-by: Varadarajan Narayanan 
---

v2 - add xo clock

 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   | 59 +
 3 files changed, 82 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..11b151e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -505,6 +505,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
+   qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
new file mode 100644
index 000..0d92f1b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -0,0 +1,22 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
new file mode 100644
index 000..fe78f3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -0,0 +1,59 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+   compatible = "qcom,ipq4019";
+
+   clocks {
+xo: xo {
+compatible = "fixed-clock";
+clock-frequency = <4800>;
+#clock-cells = <0>;
+};
+   };
+
+   soc {
+
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = <1 2 0xf08>,
+<1 3 0xf08>,
+<1 4 0xf08>,
+<1 1 0xf08>;
+   clock-frequency = <4800>;
+   };
+
+   pinctrl@0x0100 {
+   serial_pins: serial_pinmux {
+   mux {
+   pins = "gpio60", "gpio61";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 4/5] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

[Matthew McClintock]

From: Matthew McClintock 

Add initial dts files and SoC support for IPQ4019

Signed-off-by: Varadarajan Narayanan 
---

v2 - add sleep_clk

 arch/arm/boot/dts/qcom-ipq4019.dtsi | 115 
 1 file changed, 115 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
new file mode 100644
index 000..fc73822
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019";
+   compatible = "qcom,ipq4019";
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x0>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x1>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x2>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x3>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+   };
+
+   clocks {
+   sleep_clk: sleep_clk {
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   #clock-cells = <0>;
+   };
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   compatible = "simple-bus";
+
+   intc: interrupt-controller@b00 {
+   compatible = "qcom,msm-qgic2";
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   reg = <0x0b00 0x1000>,
+   <0x0b002000 0x1000>;
+   };
+
+   gcc: clock-controller@180 {
+   compatible = "qcom,gcc-ipq4019";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   reg = <0x180 0x6>;
+   };
+
+   tlmm: pinctrl@0x0100 {
+   compatible = "qcom,ipq4019-pinctrl";
+   reg = <0x0100 0x30>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <0 208 0>;
+   };
+
+   serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = <0 107 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+
+   serial@78b {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b 0x200>;
+   interrupts = <0 108 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART2_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+   };
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 3/5] ARM: qcom: add IPQ4019 compatible match

[Matthew McClintock]

From: Matthew McClintock 

This will select qcom board type when the machine compatible is
qcom,ipq4019.

Signed-off-by: Matthew McClintock 
---
 arch/arm/mach-qcom/board.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index 6d8bbf7..b52a6bc 100644
--- a/arch/arm/mach-qcom/board.c
+++ b/arch/arm/mach-qcom/board.c
@@ -18,6 +18,7 @@ static const char * const qcom_dt_match[] __initconst = {
"qcom,apq8064",
"qcom,apq8074-dragonboard",
"qcom,apq8084",
+   "qcom,ipq4019",
"qcom,ipq8062",
"qcom,ipq8064",
"qcom,msm8660-surf",
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 5/5] dts: ipq4019: Add support for IPQ4019 DK01 board

[Matthew McClintock]

From: Matthew McClintock <mmccl...@codeaurora.org>

Initial board support dts files for DK01 board.

Signed-off-by: Senthilkumar N L <snlak...@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
---

v2 - add xo clock

 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   | 59 +
 3 files changed, 82 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..11b151e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -505,6 +505,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
+   qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
new file mode 100644
index 000..0d92f1b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -0,0 +1,22 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
new file mode 100644
index 000..fe78f3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -0,0 +1,59 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+   compatible = "qcom,ipq4019";
+
+   clocks {
+xo: xo {
+compatible = "fixed-clock";
+clock-frequency = <4800>;
+#clock-cells = <0>;
+};
+   };
+
+   soc {
+
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = <1 2 0xf08>,
+<1 3 0xf08>,
+<1 4 0xf08>,
+<1 1 0xf08>;
+   clock-frequency = <4800>;
+   };
+
+   pinctrl@0x0100 {
+   serial_pins: serial_pinmux {
+   mux {
+   pins = "gpio60", "gpio61";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe 

[PATCH v2 3/5] ARM: qcom: add IPQ4019 compatible match

[Matthew McClintock]

From: Matthew McClintock <mmccl...@codeaurora.org>

This will select qcom board type when the machine compatible is
qcom,ipq4019.

Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
---
 arch/arm/mach-qcom/board.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index 6d8bbf7..b52a6bc 100644
--- a/arch/arm/mach-qcom/board.c
+++ b/arch/arm/mach-qcom/board.c
@@ -18,6 +18,7 @@ static const char * const qcom_dt_match[] __initconst = {
"qcom,apq8064",
"qcom,apq8074-dragonboard",
"qcom,apq8084",
+   "qcom,ipq4019",
"qcom,ipq8062",
"qcom,ipq8064",
"qcom,msm8660-surf",
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/