[v2,net-next] net:qos: police action offloading parameter 'burst' change to the original value
Since 'tcfp_burst' with TICK factor, driver side always need to recover
it to the original value, this patch moves the generic calculation and
recover to the 'burst' original value before offloading to device driver.
Signed-off-by: Po Liu
Acked-by: Vladimir Oltean
---
drivers/net/dsa/ocelot/felix.c| 4 +--
drivers/net/dsa/sja1105/sja1105_flower.c | 16 --
drivers/net/dsa/sja1105/sja1105_main.c| 4 +--
.../net/ethernet/freescale/enetc/enetc_qos.c | 8 +
drivers/net/ethernet/mscc/ocelot_flower.c | 4 +--
drivers/net/ethernet/mscc/ocelot_net.c| 4 +--
.../ethernet/netronome/nfp/flower/qos_conf.c | 6 ++--
include/net/dsa.h | 2 +-
include/net/flow_offload.h| 2 +-
include/net/tc_act/tc_police.h| 32 +--
net/sched/cls_api.c | 2 +-
11 files changed, 48 insertions(+), 36 deletions(-)
diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c
index 25046777c993..75020af7f7a4 100644
--- a/drivers/net/dsa/ocelot/felix.c
+++ b/drivers/net/dsa/ocelot/felix.c
@@ -746,9 +746,7 @@ static int felix_port_policer_add(struct dsa_switch *ds,
int port,
struct ocelot *ocelot = ds->priv;
struct ocelot_policer pol = {
.rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8,
- .burst = div_u64(policer->rate_bytes_per_sec *
-PSCHED_NS2TICKS(policer->burst),
-PSCHED_TICKS_PER_SEC),
+ .burst = policer->burst,
};
return ocelot_port_policer_add(ocelot, port, );
diff --git a/drivers/net/dsa/sja1105/sja1105_flower.c
b/drivers/net/dsa/sja1105/sja1105_flower.c
index 9ee8968610cd..12e76020bea3 100644
--- a/drivers/net/dsa/sja1105/sja1105_flower.c
+++ b/drivers/net/dsa/sja1105/sja1105_flower.c
@@ -31,7 +31,7 @@ static int sja1105_setup_bcast_policer(struct sja1105_private
*priv,
struct netlink_ext_ack *extack,
unsigned long cookie, int port,
u64 rate_bytes_per_sec,
- s64 burst)
+ u32 burst)
{
struct sja1105_rule *rule = sja1105_rule_find(priv, cookie);
struct sja1105_l2_policing_entry *policing;
@@ -79,9 +79,8 @@ static int sja1105_setup_bcast_policer(struct sja1105_private
*priv,
policing[rule->bcast_pol.sharindx].rate = div_u64(rate_bytes_per_sec *
512, 100);
- policing[rule->bcast_pol.sharindx].smax = div_u64(rate_bytes_per_sec *
-
PSCHED_NS2TICKS(burst),
- PSCHED_TICKS_PER_SEC);
+ policing[rule->bcast_pol.sharindx].smax = burst;
+
/* TODO: support per-flow MTU */
policing[rule->bcast_pol.sharindx].maxlen = VLAN_ETH_FRAME_LEN +
ETH_FCS_LEN;
@@ -103,7 +102,7 @@ static int sja1105_setup_tc_policer(struct sja1105_private
*priv,
struct netlink_ext_ack *extack,
unsigned long cookie, int port, int tc,
u64 rate_bytes_per_sec,
- s64 burst)
+ u32 burst)
{
struct sja1105_rule *rule = sja1105_rule_find(priv, cookie);
struct sja1105_l2_policing_entry *policing;
@@ -152,9 +151,8 @@ static int sja1105_setup_tc_policer(struct sja1105_private
*priv,
policing[rule->tc_pol.sharindx].rate = div_u64(rate_bytes_per_sec *
512, 100);
- policing[rule->tc_pol.sharindx].smax = div_u64(rate_bytes_per_sec *
- PSCHED_NS2TICKS(burst),
- PSCHED_TICKS_PER_SEC);
+ policing[rule->tc_pol.sharindx].smax = burst;
+
/* TODO: support per-flow MTU */
policing[rule->tc_pol.sharindx].maxlen = VLAN_ETH_FRAME_LEN +
ETH_FCS_LEN;
@@ -177,7 +175,7 @@ static int sja1105_flower_policer(struct sja1105_private
*priv, int port,
unsigned long cookie,
struct sja1105_key *key,
u64 rate_bytes_per_sec,
- s64 burst)
+ u32 burst)
{
switch (key->type) {
case SJA1105_KEY_BCAST:
diff --git a/drivers/net/dsa/sja1105/sja1105_main.c
b/drivers/net/dsa/sja1105/sja1105_main.c
index 789b288cc78b..5079e4aeef80 100644
--- a/drivers/net/dsa/sj
[v1,net-next] net:qos: police action offloading parameter 'burst' change to the original value
Since 'tcfp_burst' with TICK factor, driver side always need to recover
it to the original value, this patch moves the generic calculation and
recover to the 'burst' original value before offloading to device driver.
Signed-off-by: Po Liu
Signed-off-by: Vladimir Oltean
---
drivers/net/dsa/ocelot/felix.c| 4 +--
drivers/net/dsa/sja1105/sja1105_flower.c | 16 --
drivers/net/dsa/sja1105/sja1105_main.c| 4 +--
.../net/ethernet/freescale/enetc/enetc_qos.c | 8 +
drivers/net/ethernet/mscc/ocelot_flower.c | 4 +--
drivers/net/ethernet/mscc/ocelot_net.c| 4 +--
.../ethernet/netronome/nfp/flower/qos_conf.c | 6 ++--
include/net/dsa.h | 2 +-
include/net/flow_offload.h| 2 +-
include/net/tc_act/tc_police.h| 32 +--
net/sched/cls_api.c | 2 +-
11 files changed, 48 insertions(+), 36 deletions(-)
diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c
index 25046777c993..75020af7f7a4 100644
--- a/drivers/net/dsa/ocelot/felix.c
+++ b/drivers/net/dsa/ocelot/felix.c
@@ -746,9 +746,7 @@ static int felix_port_policer_add(struct dsa_switch *ds,
int port,
struct ocelot *ocelot = ds->priv;
struct ocelot_policer pol = {
.rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8,
- .burst = div_u64(policer->rate_bytes_per_sec *
-PSCHED_NS2TICKS(policer->burst),
-PSCHED_TICKS_PER_SEC),
+ .burst = policer->burst,
};
return ocelot_port_policer_add(ocelot, port, );
diff --git a/drivers/net/dsa/sja1105/sja1105_flower.c
b/drivers/net/dsa/sja1105/sja1105_flower.c
index 9ee8968610cd..12e76020bea3 100644
--- a/drivers/net/dsa/sja1105/sja1105_flower.c
+++ b/drivers/net/dsa/sja1105/sja1105_flower.c
@@ -31,7 +31,7 @@ static int sja1105_setup_bcast_policer(struct sja1105_private
*priv,
struct netlink_ext_ack *extack,
unsigned long cookie, int port,
u64 rate_bytes_per_sec,
- s64 burst)
+ u32 burst)
{
struct sja1105_rule *rule = sja1105_rule_find(priv, cookie);
struct sja1105_l2_policing_entry *policing;
@@ -79,9 +79,8 @@ static int sja1105_setup_bcast_policer(struct sja1105_private
*priv,
policing[rule->bcast_pol.sharindx].rate = div_u64(rate_bytes_per_sec *
512, 100);
- policing[rule->bcast_pol.sharindx].smax = div_u64(rate_bytes_per_sec *
-
PSCHED_NS2TICKS(burst),
- PSCHED_TICKS_PER_SEC);
+ policing[rule->bcast_pol.sharindx].smax = burst;
+
/* TODO: support per-flow MTU */
policing[rule->bcast_pol.sharindx].maxlen = VLAN_ETH_FRAME_LEN +
ETH_FCS_LEN;
@@ -103,7 +102,7 @@ static int sja1105_setup_tc_policer(struct sja1105_private
*priv,
struct netlink_ext_ack *extack,
unsigned long cookie, int port, int tc,
u64 rate_bytes_per_sec,
- s64 burst)
+ u32 burst)
{
struct sja1105_rule *rule = sja1105_rule_find(priv, cookie);
struct sja1105_l2_policing_entry *policing;
@@ -152,9 +151,8 @@ static int sja1105_setup_tc_policer(struct sja1105_private
*priv,
policing[rule->tc_pol.sharindx].rate = div_u64(rate_bytes_per_sec *
512, 100);
- policing[rule->tc_pol.sharindx].smax = div_u64(rate_bytes_per_sec *
- PSCHED_NS2TICKS(burst),
- PSCHED_TICKS_PER_SEC);
+ policing[rule->tc_pol.sharindx].smax = burst;
+
/* TODO: support per-flow MTU */
policing[rule->tc_pol.sharindx].maxlen = VLAN_ETH_FRAME_LEN +
ETH_FCS_LEN;
@@ -177,7 +175,7 @@ static int sja1105_flower_policer(struct sja1105_private
*priv, int port,
unsigned long cookie,
struct sja1105_key *key,
u64 rate_bytes_per_sec,
- s64 burst)
+ u32 burst)
{
switch (key->type) {
case SJA1105_KEY_BCAST:
diff --git a/drivers/net/dsa/sja1105/sja1105_main.c
b/drivers/net/dsa/sja1105/sja1105_main.c
index 789b288cc78b..5079e4aeef80 100644
--- a/drivers/net/dsa/sj
[v2,iproute2-next 2/2] action police: make 'mtu' could be set independently in police action
Current police action must set 'rate' and 'burst'. 'mtu' parameter
set the max frame size and could be set alone without 'rate' and 'burst'
in some situation. Offloading to hardware for example, 'mtu' could limit
the flow max frame size.
Signed-off-by: Po Liu
---
v1->v2 changes:
- fix the print message style and add space acked by Stephen Hemminger
tc/m_police.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tc/m_police.c b/tc/m_police.c
index 7eb47f8e..83b25db4 100644
--- a/tc/m_police.c
+++ b/tc/m_police.c
@@ -161,8 +161,8 @@ action_ctrl_ok:
return -1;
/* Must at least do late binding, use TB or ewma policing */
- if (!rate64 && !avrate && !p.index) {
- fprintf(stderr, "'rate' or 'avrate' MUST be specified.\n");
+ if (!rate64 && !avrate && !p.index && !mtu) {
+ fprintf(stderr, "'rate' or 'avrate' or 'mtu' MUST be
specified.\n");
return -1;
}
--
2.17.1
[v2,iproute2-next 1/2] action police: change the print message quotes style
Change the double quotes to single quotes in fprintf message to make it
more readable.
Signed-off-by: Po Liu
---
v1->v2 changes:
- Patch new added
tc/m_police.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tc/m_police.c b/tc/m_police.c
index a5bc20c0..7eb47f8e 100644
--- a/tc/m_police.c
+++ b/tc/m_police.c
@@ -162,23 +162,23 @@ action_ctrl_ok:
/* Must at least do late binding, use TB or ewma policing */
if (!rate64 && !avrate && !p.index) {
- fprintf(stderr, "\"rate\" or \"avrate\" MUST be specified.\n");
+ fprintf(stderr, "'rate' or 'avrate' MUST be specified.\n");
return -1;
}
/* When the TB policer is used, burst is required */
if (rate64 && !buffer && !avrate) {
- fprintf(stderr, "\"burst\" requires \"rate\".\n");
+ fprintf(stderr, "'burst' requires 'rate'.\n");
return -1;
}
if (prate64) {
if (!rate64) {
- fprintf(stderr, "\"peakrate\" requires \"rate\".\n");
+ fprintf(stderr, "'peakrate' requires 'rate'.\n");
return -1;
}
if (!mtu) {
- fprintf(stderr, "\"mtu\" is required, if \"peakrate\"
is requested.\n");
+ fprintf(stderr, "'mtu' is required, if 'peakrate' is
requested.\n");
return -1;
}
}
--
2.17.1
RE: Re: [iproute2-next] action police: make 'mtu' could be set independently in police action
Hi Stephen,
> -Original Message-
> From: Stephen Hemminger
> Sent: 2020年6月29日 4:16
> To: Po Liu
> Cc: dsah...@gmail.com; linux-kernel@vger.kernel.org;
> net...@vger.kernel.org; da...@davemloft.net; j...@mojatatu.com;
> v...@buslov.dev; Claudiu Manoil ; Vladimir
> Oltean ; Alexandru Marginean
>
> Subject: Re: [iproute2-next] action police: make 'mtu' could be set
> independently in police action
>
> On Sun, 28 Jun 2020 09:46:02 +0800
> Po Liu wrote:
>
> > Current police action must set 'rate' and 'burst'. 'mtu' parameter set
> > the max frame size and could be set alone without 'rate' and 'burst'
> > in some situation. Offloading to hardware for example, 'mtu' could
> > limit the flow max frame size.
> >
> > Signed-off-by: Po Liu
> > ---
> > tc/m_police.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/tc/m_police.c b/tc/m_police.c index a5bc20c0..89497f67
> > 100644
> > --- a/tc/m_police.c
> > +++ b/tc/m_police.c
> > @@ -161,8 +161,8 @@ action_ctrl_ok:
> > return -1;
> >
> > /* Must at least do late binding, use TB or ewma policing */
> > - if (!rate64 && !avrate && !p.index) {
> > - fprintf(stderr, "\"rate\" or \"avrate\" MUST be
> > specified.\n");
> > + if (!rate64 && !avrate && !p.index && !mtu) {
> > + fprintf(stderr, "\"rate\" or \"avrate\" or \"mtu\"MUST
> > + be specified.\n");
>
> Missing blank.
> Your message will come out as:
> "rate" or "avrate" or "mtu"MUST be specified.
Get it. Will correct.
Thanks!
>
>
> The quotes aren't adding to the readability, why not just remove them
> instead.
Will remove all quotes.
Br,
Po Liu
[iproute2-next] action police: make 'mtu' could be set independently in police action
Current police action must set 'rate' and 'burst'. 'mtu' parameter
set the max frame size and could be set alone without 'rate' and 'burst'
in some situation. Offloading to hardware for example, 'mtu' could limit
the flow max frame size.
Signed-off-by: Po Liu
---
tc/m_police.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tc/m_police.c b/tc/m_police.c
index a5bc20c0..89497f67 100644
--- a/tc/m_police.c
+++ b/tc/m_police.c
@@ -161,8 +161,8 @@ action_ctrl_ok:
return -1;
/* Must at least do late binding, use TB or ewma policing */
- if (!rate64 && !avrate && !p.index) {
- fprintf(stderr, "\"rate\" or \"avrate\" MUST be specified.\n");
+ if (!rate64 && !avrate && !p.index && !mtu) {
+ fprintf(stderr, "\"rate\" or \"avrate\" or \"mtu\"MUST be
specified.\n");
return -1;
}
--
2.17.1
RE: Re: [v1,net-next 3/4] net: qos: police action add index for tc flower offloading
Hi Jamal, > -Original Message- > From: Jamal Hadi Salim > Sent: 2020年6月26日 21:28 > To: Po Liu ; da...@davemloft.net; linux- > ker...@vger.kernel.org; net...@vger.kernel.org; ido...@idosch.org > Cc: j...@resnulli.us; vinicius.go...@intel.com; v...@buslov.dev; Claudiu > Manoil ; Vladimir Oltean > ; Alexandru Marginean > ; michael.c...@broadcom.com; > vis...@chelsio.com; sae...@mellanox.com; l...@kernel.org; > j...@mellanox.com; ido...@mellanox.com; > alexandre.bell...@bootlin.com; unglinuxdri...@microchip.com; > k...@kernel.org; xiyou.wangc...@gmail.com; > simon.hor...@netronome.com; pa...@netfilter.org; > mo...@mellanox.com; m-kariche...@ti.com; > andre.gue...@linux.intel.com; step...@networkplumber.org; Edward > Cree > Subject: Re: [v1,net-next 3/4] net: qos: police action add index for tc > flower offloading > > On 2020-06-24 8:34 p.m., Po Liu wrote: > > > > > >> -Original Message- > > >> That is the point i was trying to get to. Basically: > >> You have a counter table which is referenced by "index" > >> You also have a meter/policer table which is referenced by "index". > > > > They should be one same group and same meaning. > > > > Didnt follow. You mean the index is the same for both the stat and policer? Sorry, just ignore this reply line, hardware has this police index counter, but wasn't use in this tc command, just focus on below psfp_streamfilter_counters. I thought you thought in this way. > > >> > >> For policers, they maintain their own stats. So when i say: > >> tc ... flower ... action police ... index 5 The index referred to is > >> in the policer table > >> > > > > Sure. Means police with No. 5 entry. > > > >> But for other actions, example when i say: > >> tc ... flower ... action drop index 10 > > > > Still the question, does gact action drop could bind with index? It > doesn't meanful. > > > > Depends on your hardware. From this discussion i am trying to understand > where the constraint is for your case. > Whether it is your h/w or the TSN spec. > For a sample counting which is flexible see here: > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp4.o > rg%2Fp4-spec%2Fdocs%2FPSA.html%23sec- > countersdata=02%7C01%7Cpo.liu%40nxp.com%7C02dc8f3f60714afd > 3dab08d819d4c66e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7 > C637287748941041353sdata=9%2FS%2BAMbHV09H5VrJMwdEeiSPzg > 4w%2FmW5FxQr4ecuze4%3Dreserved=0 > > That concept is not specific to P4 but rather to newer flow-based > hardware. > > More context: > The assumption these days is we can have a _lot_ of flows with a lot of > actions. > Then you want to be able to collect the stats separately, possibly one > counter entry for each action of interest. > Why is this important?f For analytics uses cases, when you are retrieving > the stats you want to reduce the amount of data being retrieved. Typically > these stats are polled every X seconds. > For starters, you dont dump filters (which in your case seems to be the > only way to get the stats). > In current tc, you dump the actions. But that could be improved so you > can just dump the stats. The mapping of stats index to actions is known to > the entity doing the dump. > > Does that make sense? > > >> The index is in the counter/stats table. > >> It is not exactly "10" in hardware, the driver magically hides it > >> from the user - so it could be hw counter index 1234 > > > > Not exactly. Current flower offloading stats means get the chain index > for that flow filter. The other actions should bind to that chain index. > > > > So if i read correctly: You have an index per filter pointing to the counter > table. > Is this something _you_ decided to do in software or is it how the > hardware works? (note i referred to this as "legacy ACL" approach earlier. > It worked like that in old hardware because the main use case was to have > one action on a match (drop/accept kind). It is the hardware works and all registers according to the IEEE802.1Qci spec. > > >Like IEEE802.1Qci, what I am doing is bind gate action to filter > chain(mandatory). And also police action as optional. > > I cant seem to find this spec online. Is it freely available? Maybe need a register count on http://www.ieee802.org/ > Also, if i understand you correctly you are saying according to this spec > you can only have the following type of policy: > tc .. filter match-spec-here .. \ > action gate gate-action-attributes \ > action police ... > > That "action gate" MUST al
RE:Re: [v1,net-next 3/4] net: qos: police action add index for tc flower offloading
> -Original Message-
> From: Jamal Hadi Salim
> Sent: 2020年6月24日 20:45
> To: Po Liu ; da...@davemloft.net; linux-
> ker...@vger.kernel.org; net...@vger.kernel.org; ido...@idosch.org
> Cc: j...@resnulli.us; vinicius.go...@intel.com; v...@buslov.dev; Claudiu
> Manoil ; Vladimir Oltean
> ; Alexandru Marginean
> ; michael.c...@broadcom.com;
> vis...@chelsio.com; sae...@mellanox.com; l...@kernel.org;
> j...@mellanox.com; ido...@mellanox.com;
> alexandre.bell...@bootlin.com; unglinuxdri...@microchip.com;
> k...@kernel.org; xiyou.wangc...@gmail.com;
> simon.hor...@netronome.com; pa...@netfilter.org;
> mo...@mellanox.com; m-kariche...@ti.com;
> andre.gue...@linux.intel.com; step...@networkplumber.org; Edward
> Cree
> Subject: Re: [v1,net-next 3/4] net: qos: police action add index for tc
> flower offloading
> >
> On 2020-06-23 7:52 p.m., Po Liu wrote:
> > Hi Jamal,
> >
> >
>
> >>>> My question: Is this any different from how stats are structured?
> >>>
>
> [..]
> >> My question: Why cant you apply the same semantics for the counters?
> >> Does your hardware have an indexed counter/stats table? If yes then
> >> you
> >
> > Yes,
>
> That is the point i was trying to get to. Basically:
> You have a counter table which is referenced by "index"
> You also have a meter/policer table which is referenced by "index".
They should be one same group and same meaning.
>
> For policers, they maintain their own stats. So when i say:
> tc ... flower ... action police ... index 5 The index referred to is in the
> policer table
>
Sure. Means police with No. 5 entry.
> But for other actions, example when i say:
> tc ... flower ... action drop index 10
Still the question, does gact action drop could bind with index? It doesn't
meanful.
> The index is in the counter/stats table.
> It is not exactly "10" in hardware, the driver magically hides it from the
> user - so it could be hw counter index 1234
Not exactly. Current flower offloading stats means get the chain index for that
flow filter. The other actions should bind to that chain index. Like
IEEE802.1Qci, what I am doing is bind gate action to filter chain(mandatory).
And also police action as optional. There is stream counter table which summary
the counters pass gate action entry and police action entry for that chain
index(there is a bit different if two chain sharing same action list).
One chain counter which tc show stats get counter source:
struct psfp_streamfilter_counters {
u64 matching_frames_count;
u64 passing_frames_count;
u64 not_passing_frames_count;
u64 passing_sdu_count;
u64 not_passing_sdu_count;
u64 red_frames_count;
};
When pass to the user space, summarize as:
stats.pkts = counters.matching_frames_count +
counters.not_passing_sdu_count - filter->stats.pkts;
stats.drops = counters.not_passing_frames_count +
counters.not_passing_sdu_count + counters.red_frames_count -
filter->stats.drops;
But in software side, it is showing in the action list. And action gate and
police exactly showing the counters that chain index. Not the true counters of
index action gate or index police. This is the limitation of get the offloading
stats.
>
> The old approach is to assume the classifier (flower in this
> case) has a counter. The reason for this assumption is older hardware was
> designed to deal with a single action per match.
> So a counter to the filter is also the counter to the
> (single) action. I get the feeling your hardware fits in that space.
No, hardware could have gate+police actions but bind to one stream filter
counter table in IEEE 802.1Qci.
>
> Modern use cases have evolved from the ACL single match and action
> approach. Maintaining the old thought/architecture breaks in two use
> cases:
> 1) when you have multiple actions per policy filter. You need counter-per-
> action for various reasons
Action index only for set an action entry in hardware, and not get stats by
that index.
So I don't think it is problem of exposing action index to the driver break
the rule. This is the limitation of get the offloading stats, there is no
counters get by action index.
> 2) Sharing of counters across filters and action. This can be achieve
>
> tc supports the above and is sufficient to cover the old use cases.
> I am just worried, architecturally, we are restricting ourselves to the old
> scheme.
>
> Another reason this is important is for the sake of analytics.
> A user space app can poll just for the stats table in hardware (or the
> cached version in the kernel) and reduce the amount of data crossing to
> user space..
>
> cheers,
> jamal
>
>
>
>
Br,
Po Liu
[v2,net-next 3/4] net: qos: police action add index for tc flower offloading
From: Po Liu
Hardware device may include more than one police entry. Specifying the
action's index make it possible for several tc filters to share the same
police action when installing the filters.
Propagate this index to device drivers through the flow offload
intermediate representation, so that drivers could share a single
hardware policer between multiple filters.
v1->v2 changes:
- Update the commit message suggest by Ido Schimmel
Signed-off-by: Po Liu
---
include/net/flow_offload.h | 1 +
net/sched/cls_api.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
index c2ef19c6b27d..eed98075b1ae 100644
--- a/include/net/flow_offload.h
+++ b/include/net/flow_offload.h
@@ -232,6 +232,7 @@ struct flow_action_entry {
booltruncate;
} sample;
struct {/* FLOW_ACTION_POLICE */
+ u32 index;
s64 burst;
u64 rate_bytes_ps;
u32 mtu;
diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c
index 6aba7d5ba1ec..fdc4c89ca1fa 100644
--- a/net/sched/cls_api.c
+++ b/net/sched/cls_api.c
@@ -3659,6 +3659,7 @@ int tc_setup_flow_action(struct flow_action *flow_action,
entry->police.rate_bytes_ps =
tcf_police_rate_bytes_ps(act);
entry->police.mtu = tcf_police_tcfp_mtu(act);
+ entry->police.index = act->tcfa_index;
} else if (is_tcf_ct(act)) {
entry->id = FLOW_ACTION_CT;
entry->ct.action = tcf_ct_action(act);
--
2.17.1
[v2,net-next 2/4] net: enetc: add support max frame size for tc flower offload
From: Po Liu
Base on the tc flower offload police action add max frame size by the
parameter 'mtu'. Tc flower device driver working by the IEEE 802.1Qci
stream filter can implement the max frame size filtering. Add it to the
current hardware tc flower stearm filter driver.
Signed-off-by: Po Liu
---
v2:
- No update.
.../net/ethernet/freescale/enetc/enetc_qos.c | 52 +--
1 file changed, 36 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
index fb76903eca90..07f98bf7a06b 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
@@ -389,6 +389,7 @@ struct enetc_psfp_filter {
u32 index;
s32 handle;
s8 prio;
+ u32 maxsdu;
u32 gate_id;
s32 meter_id;
refcount_t refcount;
@@ -430,6 +431,12 @@ static struct actions_fwd enetc_act_fwd[] = {
BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS),
FILTER_ACTION_TYPE_PSFP
},
+ {
+ BIT(FLOW_ACTION_POLICE) |
+ BIT(FLOW_ACTION_GATE),
+ BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS),
+ FILTER_ACTION_TYPE_PSFP
+ },
/* example for ACL actions */
{
BIT(FLOW_ACTION_DROP),
@@ -594,8 +601,12 @@ static int enetc_streamfilter_hw_set(struct
enetc_ndev_priv *priv,
/* Filter Type. Identifies the contents of the MSDU/FM_INST_INDEX
* field as being either an MSDU value or an index into the Flow
* Meter Instance table.
-* TODO: no limit max sdu
*/
+ if (sfi->maxsdu) {
+ sfi_config->msdu =
+ cpu_to_le16(sfi->maxsdu);
+ sfi_config->multi |= 0x40;
+ }
if (sfi->meter_id >= 0) {
sfi_config->fm_inst_table_index = cpu_to_le16(sfi->meter_id);
@@ -872,6 +883,7 @@ static struct enetc_psfp_filter
hlist_for_each_entry(s, _filter_list, node)
if (s->gate_id == sfi->gate_id &&
s->prio == sfi->prio &&
+ s->maxsdu == sfi->maxsdu &&
s->meter_id == sfi->meter_id)
return s;
@@ -979,6 +991,7 @@ static struct actions_fwd *enetc_check_flow_actions(u64
acts,
static int enetc_psfp_parse_clsflower(struct enetc_ndev_priv *priv,
struct flow_cls_offload *f)
{
+ struct flow_action_entry *entryg = NULL, *entryp = NULL;
struct flow_rule *rule = flow_cls_offload_flow_rule(f);
struct netlink_ext_ack *extack = f->common.extack;
struct enetc_stream_filter *filter, *old_filter;
@@ -997,9 +1010,12 @@ static int enetc_psfp_parse_clsflower(struct
enetc_ndev_priv *priv,
flow_action_for_each(i, entry, >action)
if (entry->id == FLOW_ACTION_GATE)
- break;
+ entryg = entry;
+ else if (entry->id == FLOW_ACTION_POLICE)
+ entryp = entry;
- if (entry->id != FLOW_ACTION_GATE)
+ /* Not support without gate action */
+ if (!entryg)
return -EINVAL;
filter = kzalloc(sizeof(*filter), GFP_KERNEL);
@@ -1079,19 +1095,19 @@ static int enetc_psfp_parse_clsflower(struct
enetc_ndev_priv *priv,
}
/* parsing gate action */
- if (entry->gate.index >= priv->psfp_cap.max_psfp_gate) {
+ if (entryg->gate.index >= priv->psfp_cap.max_psfp_gate) {
NL_SET_ERR_MSG_MOD(extack, "No Stream Gate resource!");
err = -ENOSPC;
goto free_filter;
}
- if (entry->gate.num_entries >= priv->psfp_cap.max_psfp_gatelist) {
+ if (entryg->gate.num_entries >= priv->psfp_cap.max_psfp_gatelist) {
NL_SET_ERR_MSG_MOD(extack, "No Stream Gate resource!");
err = -ENOSPC;
goto free_filter;
}
- entries_size = struct_size(sgi, entries, entry->gate.num_entries);
+ entries_size = struct_size(sgi, entries, entryg->gate.num_entries);
sgi = kzalloc(entries_size, GFP_KERNEL);
if (!sgi) {
err = -ENOMEM;
@@ -1099,18 +1115,18 @@ static int enetc_psfp_parse_clsflower(struct
enetc_ndev_priv *priv,
}
refcount_set(>refcount, 1);
- sgi->index = entry->gate.index;
- sgi->init_ipv = entry->gate.prio;
- sgi->basetime = entry->gate.basetime;
- sgi->cycletime = entry->gate.cycletime;
- sgi->num_entries = entry->gate.num_entries;
+ sgi->index = entryg->gate.index;
+ sgi->init_ipv = entryg->gate.prio;
+ sgi->basetime = entryg->gate.basetime;
+ sgi->cycletime
[v2,net-next 4/4] net: enetc add tc flower offload flow metering policing action
From: Po Liu
Flow metering entries in IEEE 802.1Qci is an optional function for a
flow filtering module. Flow metering is two rates two buckets and three
color marker to policing the frames. This patch only enable one rate one
bucket and in color blind mode. Flow metering instance are as
specified in the algorithm in MEF 10.3 and in Bandwidth Profile
Parameters. They are:
a) Flow meter instance identifier. An integer value identifying the flow
meter instance. The patch use the police 'index' as thin value.
b) Committed Information Rate (CIR), in bits per second. This patch use
the 'rate_bytes_ps' represent this value.
c) Committed Burst Size (CBS), in octets. This patch use the 'burst'
represent this value.
d) Excess Information Rate (EIR), in bits per second.
e) Excess Burst Size per Bandwidth Profile Flow (EBS), in octets.
And plus some other parameters. This patch set EIR/EBS default disable
and color blind mode.
v1->v2 changes:
- Use div_u64() as division replace the '/' report:
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
ld: drivers/net/ethernet/freescale/enetc/enetc_qos.o: in function
`enetc_flowmeter_hw_set':
>> enetc_qos.c:(.text+0x66): undefined reference to `__udivdi3'
Signed-off-by: Po Liu
---
.../net/ethernet/freescale/enetc/enetc_hw.h | 24 +++
.../net/ethernet/freescale/enetc/enetc_qos.c | 160 --
2 files changed, 172 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
index 6314051bc6c1..f00c4382423e 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
@@ -570,6 +570,7 @@ enum bdcr_cmd_class {
BDCR_CMD_STREAM_IDENTIFY,
BDCR_CMD_STREAM_FILTER,
BDCR_CMD_STREAM_GCL,
+ BDCR_CMD_FLOW_METER,
__BDCR_CMD_MAX_LEN,
BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
};
@@ -736,10 +737,33 @@ struct sgcl_data {
struct sgce sgcl[0];
};
+#define ENETC_CBDR_FMI_MR BIT(0)
+#define ENETC_CBDR_FMI_MRENBIT(1)
+#define ENETC_CBDR_FMI_DOY BIT(2)
+#defineENETC_CBDR_FMI_CM BIT(3)
+#define ENETC_CBDR_FMI_CF BIT(4)
+#define ENETC_CBDR_FMI_NDORBIT(5)
+#define ENETC_CBDR_FMI_OALEN BIT(6)
+#define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)
+
+/* class 10: command 0/1, Flow Meter Instance Set, short Format */
+struct fmi_conf {
+ __le32 cir;
+ __le32 cbs;
+ __le32 eir;
+ __le32 ebs;
+ u8 conf;
+ u8 res1;
+ u8 ir_fpp;
+ u8 res2[4];
+ u8 en;
+};
+
struct enetc_cbd {
union{
struct sfi_conf sfi_conf;
struct sgi_table sgi_table;
+ struct fmi_conf fmi_conf;
struct {
__le32 addr[2];
union {
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
index 07f98bf7a06b..4f670cbdf186 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
@@ -408,10 +408,26 @@ struct enetc_psfp_gate {
struct action_gate_entry entries[0];
};
+/* Only enable the green color frame now
+ * Will add eir and ebs color blind, couple flag etc when
+ * policing action add more offloading parameters
+ */
+struct enetc_psfp_meter {
+ u32 index;
+ u32 cir;
+ u32 cbs;
+ refcount_t refcount;
+ struct hlist_node node;
+};
+
+#define ENETC_PSFP_FLAGS_FMI BIT(0)
+
struct enetc_stream_filter {
struct enetc_streamid sid;
u32 sfi_index;
u32 sgi_index;
+ u32 flags;
+ u32 fmi_index;
struct flow_stats stats;
struct hlist_node node;
};
@@ -422,6 +438,7 @@ struct enetc_psfp {
struct hlist_head stream_list;
struct hlist_head psfp_filter_list;
struct hlist_head psfp_gate_list;
+ struct hlist_head psfp_meter_list;
spinlock_t psfp_lock; /* spinlock for the struct enetc_psfp r/w */
};
@@ -842,6 +859,47 @@ static int enetc_streamgate_hw_set(struct enetc_ndev_priv
*priv,
return err;
}
+static int enetc_flowmeter_hw_set(struct enetc_ndev_priv *priv,
+ struct enetc_psfp_meter *fmi,
+ u8 enable)
+{
+ struct enetc_cbd cbd = { .cmd = 0 };
+ struct fmi_conf *fmi_config;
+ u64 temp = 0;
+
+ cbd.index = cpu_to_le16((u16)fmi->index);
+ cbd.cls = BDCR_CMD_FLOW_METER;
+ cbd.status_flags = 0x80;
+
+ if (!enable)
+ return enetc_send_cmd(priv->si, );
+
+ fmi_config = _conf;
+ fmi_config->en = 0x80;
+
+ if (fmi->cir) {
+ temp = (u64)8000 * fmi->cir;
+ temp = div_u64(temp, 3725);
+ }
+
+ fmi_
[v2,net-next 1/4] net: qos: add tc police offloading action with max frame size limit
From: Po Liu
Current police offloading support the 'burst'' and 'rate_bytes_ps'. Some
hardware own the capability to limit the frame size. If the frame size
larger than the setting, the frame would be dropped. For the police
action itself already accept the 'mtu' parameter in tc command. But not
extend to tc flower offloading. So extend 'mtu' to tc flower offloading.
Signed-off-by: Po Liu
---
v2:
-- No update.
include/net/flow_offload.h | 1 +
include/net/tc_act/tc_police.h | 10 ++
net/sched/cls_api.c| 1 +
3 files changed, 12 insertions(+)
diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
index 00c15f14c434..c2ef19c6b27d 100644
--- a/include/net/flow_offload.h
+++ b/include/net/flow_offload.h
@@ -234,6 +234,7 @@ struct flow_action_entry {
struct {/* FLOW_ACTION_POLICE */
s64 burst;
u64 rate_bytes_ps;
+ u32 mtu;
} police;
struct {/* FLOW_ACTION_CT */
int action;
diff --git a/include/net/tc_act/tc_police.h b/include/net/tc_act/tc_police.h
index f098ad4424be..cd973b10ae8c 100644
--- a/include/net/tc_act/tc_police.h
+++ b/include/net/tc_act/tc_police.h
@@ -69,4 +69,14 @@ static inline s64 tcf_police_tcfp_burst(const struct
tc_action *act)
return params->tcfp_burst;
}
+static inline u32 tcf_police_tcfp_mtu(const struct tc_action *act)
+{
+ struct tcf_police *police = to_police(act);
+ struct tcf_police_params *params;
+
+ params = rcu_dereference_protected(police->params,
+ lockdep_is_held(>tcf_lock));
+ return params->tcfp_mtu;
+}
+
#endif /* __NET_TC_POLICE_H */
diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c
index a00a203b2ef5..6aba7d5ba1ec 100644
--- a/net/sched/cls_api.c
+++ b/net/sched/cls_api.c
@@ -3658,6 +3658,7 @@ int tc_setup_flow_action(struct flow_action *flow_action,
entry->police.burst = tcf_police_tcfp_burst(act);
entry->police.rate_bytes_ps =
tcf_police_rate_bytes_ps(act);
+ entry->police.mtu = tcf_police_tcfp_mtu(act);
} else if (is_tcf_ct(act)) {
entry->id = FLOW_ACTION_CT;
entry->ct.action = tcf_ct_action(act);
--
2.17.1
RE: Re: [v1,net-next 3/4] net: qos: police action add index for tc flower offloading
Hi Jamal, > -Original Message- > From: Jamal Hadi Salim > Sent: 2020年6月23日 20:18 > To: Po Liu ; da...@davemloft.net; linux- > ker...@vger.kernel.org; net...@vger.kernel.org; ido...@idosch.org > Cc: j...@resnulli.us; vinicius.go...@intel.com; v...@buslov.dev; Claudiu > Manoil ; Vladimir Oltean > ; Alexandru Marginean > ; michael.c...@broadcom.com; > vis...@chelsio.com; sae...@mellanox.com; l...@kernel.org; > j...@mellanox.com; ido...@mellanox.com; > alexandre.bell...@bootlin.com; unglinuxdri...@microchip.com; > k...@kernel.org; xiyou.wangc...@gmail.com; > simon.hor...@netronome.com; pa...@netfilter.org; > mo...@mellanox.com; m-kariche...@ti.com; > andre.gue...@linux.intel.com; step...@networkplumber.org; Edward > Cree > Subject: Re: [v1,net-next 3/4] net: qos: police action add index for tc > flower offloading > > On 2020-06-23 7:55 a.m., Po Liu wrote: > > > [..] > >> My question: Is this any different from how stats are structured? > > > > I don't know I fully catch the question. Are you trying to get how many > frames for each filter chain passing one index policing action? > > If one index police action bind to multiple tc filter(they should have > differnt chain index ). All those filter should get same index police action > stats value since they are sharing the same hardware entry. But I don't > think this is the problem. > > > > This is a good thing. What is nice is i can use the same index for s/w and > h/w (and no need for a translation/remapping). > > > With index provide to device driver(map the s/w action index to a h/w > table index ), user could list the police actions list by command: > > # tc actions show action police > > Shows the police action table by index. > > This is also nice. > > My question: Why cant you apply the same semantics for the counters? > Does your hardware have an indexed counter/stats table? If yes then you Yes, but I think tc flower can only care about the counters of that chain. And action police care about how many frames for each police entry. > should be able to do similar thing for counters as you do for policer (i.e > use an index and share counters across actions). So when i say: > tc action drop index 5 Do you mean something like "tc xxx flower action police index 5 drop" since '' tc action drop index 5" is not a proper command? (there is 'action drop' follow the tc filter command but not with index assigned). > and > tc action ok index 5 > infact they use the same counter. Maybe you are saying if action police follow with 'CONTROL' (reclassify | pipe | drop | continue | ok) when offloading to hardware. With different 'CONTROL', the hardware counter won't changed since hardware never known what the 'CONTROL' is. This is still software part and will do at software part(although software seems not deal with this, I also suggest to after offloading should back to tcf_police_act() continue the action). When set to be offloading mode, the counters only showing the hardware counters(even different vendor could set different counter register.). But I don't think the index offloading could break anything. > > > cheers, > jamal Br, Po Liu
RE: Re: [v1,net-next 3/4] net: qos: police action add index for tc flower offloading
Hi Jamal,
> -Original Message-
> From: Jamal Hadi Salim
> Sent: 2020年6月23日 18:09
> To: Po Liu ; da...@davemloft.net; linux-
> ker...@vger.kernel.org; net...@vger.kernel.org; ido...@idosch.org
> Cc: j...@resnulli.us; vinicius.go...@intel.com; v...@buslov.dev; Claudiu
> Manoil ; Vladimir Oltean
> ; Alexandru Marginean
> ; michael.c...@broadcom.com;
> vis...@chelsio.com; sae...@mellanox.com; l...@kernel.org;
> j...@mellanox.com; ido...@mellanox.com;
> alexandre.bell...@bootlin.com; unglinuxdri...@microchip.com;
> k...@kernel.org; xiyou.wangc...@gmail.com;
> simon.hor...@netronome.com; pa...@netfilter.org;
> mo...@mellanox.com; m-kariche...@ti.com;
> andre.gue...@linux.intel.com; step...@networkplumber.org; Edward
> Cree
> Subject: Re: [v1,net-next 3/4] net: qos: police action add index for tc
> flower offloading
>
>
> This certainly brings an interesting point which i brought up earlier when
> Jiri was doing offloading of stats.
> In this case the action index is being used as the offloaded policer index
> (note: there'd need to be a check whether the index is infact acceptable to
> the h/w etc unless there
> 2^32 meters available in the hardware).
Yes, device should report invalid if index is out of range which means hardware
not support.
>
> My question: Is this any different from how stats are structured?
I don't know I fully catch the question. Are you trying to get how many frames
for each filter chain passing one index policing action?
If one index police action bind to multiple tc filter(they should have differnt
chain index ). All those filter should get same index police action stats value
since they are sharing the same hardware entry. But I don't think this is the
problem.
With index provide to device driver(map the s/w action index to a h/w table
index ), user could list the police actions list by command:
# tc actions show action police
Shows the police action table by index.
Thanks!
> In this case you can map the s/w action index to a h/w table index (of
> meters).
> My comment then was: hardware i have encountered (and i pointed to P4
> model as well) assumes an indexed table of stats.
>
> cheers,
> jamal
>
> On 2020-06-23 2:34 a.m., Po Liu wrote:
> > From: Po Liu
> >
> > Hardware may own many entries for police flow. So that make one(or
> > multi) flow to be policed by one hardware entry. This patch add the
> > police action index provide to the driver side make it mapping the
> > driver hardware entry index.
> >
> > Signed-off-by: Po Liu
> > ---
> > include/net/flow_offload.h | 1 +
> > net/sched/cls_api.c| 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
> > index c2ef19c6b27d..eed98075b1ae 100644
> > --- a/include/net/flow_offload.h
> > +++ b/include/net/flow_offload.h
> > @@ -232,6 +232,7 @@ struct flow_action_entry {
> > booltruncate;
> > } sample;
> > struct {/* FLOW_ACTION_POLICE
> > */
> > + u32 index;
> > s64 burst;
> > u64 rate_bytes_ps;
> > u32 mtu;
> > diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c index
> > 6aba7d5ba1ec..fdc4c89ca1fa 100644
> > --- a/net/sched/cls_api.c
> > +++ b/net/sched/cls_api.c
> > @@ -3659,6 +3659,7 @@ int tc_setup_flow_action(struct flow_action
> *flow_action,
> > entry->police.rate_bytes_ps =
> > tcf_police_rate_bytes_ps(act);
> > entry->police.mtu = tcf_police_tcfp_mtu(act);
> > + entry->police.index = act->tcfa_index;
> > } else if (is_tcf_ct(act)) {
> > entry->id = FLOW_ACTION_CT;
> > entry->ct.action = tcf_ct_action(act);
> >
Br,
Po Liu
RE:Re: [v1,net-next 3/4] net: qos: police action add index for tc flower offloading
Hi Ido,
Sorry, ignore previous email.
> -Original Message-
> From: Ido Schimmel
> Sent: 2020年6月23日 15:10
> To: Po Liu
> Cc: da...@davemloft.net; linux-kernel@vger.kernel.org;
> net...@vger.kernel.org; j...@resnulli.us; vinicius.go...@intel.com;
> v...@buslov.dev; Claudiu Manoil ; Vladimir
> Oltean ; Alexandru Marginean
> ; michael.c...@broadcom.com;
> vis...@chelsio.com; sae...@mellanox.com; l...@kernel.org;
> j...@mellanox.com; ido...@mellanox.com;
> alexandre.bell...@bootlin.com; unglinuxdri...@microchip.com;
> k...@kernel.org; j...@mojatatu.com; xiyou.wangc...@gmail.com;
> simon.hor...@netronome.com; pa...@netfilter.org;
> mo...@mellanox.com; m-kariche...@ti.com;
> andre.gue...@linux.intel.com; step...@networkplumber.org
> Subject: Re: [v1,net-next 3/4] net: qos: police action add index for tc
> flower offloading
>
> On Tue, Jun 23, 2020 at 02:34:11PM +0800, Po Liu wrote:
> > From: Po Liu
> >
> > Hardware may own many entries for police flow. So that make one(or
> > multi) flow to be policed by one hardware entry. This patch add the
> > police action index provide to the driver side make it mapping the
> > driver hardware entry index.
>
> Maybe first mention that it is possible for multiple filters in software to
> share the same policer. Something like:
>
> "
> It is possible for several tc filters to share the same police action by
> specifying the action's index when installing the filters.
>
> Propagate this index to device drivers through the flow offload
> intermediate representation, so that drivers could share a single hardware
> policer between multiple filters.
> "
>
Thanks, I would change this commit message.
> >
> > Signed-off-by: Po Liu
> > ---
> > include/net/flow_offload.h | 1 +
> > net/sched/cls_api.c| 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
> > index c2ef19c6b27d..eed98075b1ae 100644
> > --- a/include/net/flow_offload.h
> > +++ b/include/net/flow_offload.h
> > @@ -232,6 +232,7 @@ struct flow_action_entry {
> > booltruncate;
> > } sample;
> > struct {/* FLOW_ACTION_POLICE
> > */
> > + u32 index;
> > s64 burst;
> > u64 rate_bytes_ps;
> > u32 mtu;
> > diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c index
> > 6aba7d5ba1ec..fdc4c89ca1fa 100644
> > --- a/net/sched/cls_api.c
> > +++ b/net/sched/cls_api.c
> > @@ -3659,6 +3659,7 @@ int tc_setup_flow_action(struct flow_action
> *flow_action,
> > entry->police.rate_bytes_ps =
> > tcf_police_rate_bytes_ps(act);
> > entry->police.mtu = tcf_police_tcfp_mtu(act);
> > + entry->police.index = act->tcfa_index;
> > } else if (is_tcf_ct(act)) {
> > entry->id = FLOW_ACTION_CT;
> > entry->ct.action = tcf_ct_action(act);
> > --
> > 2.17.1
> >
Br,
Po Liu
RE: [EXT] Re: [v1,net-next 3/4] net: qos: police action add index for tc flower offloading
Hi Ido,
> -Original Message-
> From: Ido Schimmel
> Sent: 2020年6月23日 15:10
> To: Po Liu
> Cc: da...@davemloft.net; linux-kernel@vger.kernel.org;
> net...@vger.kernel.org; j...@resnulli.us; vinicius.go...@intel.com;
> v...@buslov.dev; Claudiu Manoil ; Vladimir
> Oltean ; Alexandru Marginean
> ; michael.c...@broadcom.com;
> vis...@chelsio.com; sae...@mellanox.com; l...@kernel.org;
> j...@mellanox.com; ido...@mellanox.com;
> alexandre.bell...@bootlin.com; unglinuxdri...@microchip.com;
> k...@kernel.org; j...@mojatatu.com; xiyou.wangc...@gmail.com;
> simon.hor...@netronome.com; pa...@netfilter.org;
> mo...@mellanox.com; m-kariche...@ti.com;
> andre.gue...@linux.intel.com; step...@networkplumber.org
> Subject: [EXT] Re: [v1,net-next 3/4] net: qos: police action add index for tc
> flower offloading
>
> Caution: EXT Email
>
> On Tue, Jun 23, 2020 at 02:34:11PM +0800, Po Liu wrote:
> > From: Po Liu
> >
> > Hardware may own many entries for police flow. So that make one(or
> > multi) flow to be policed by one hardware entry. This patch add the
> > police action index provide to the driver side make it mapping the
> > driver hardware entry index.
>
> Maybe first mention that it is possible for multiple filters in software to
> share the same policer. Something like:
>
> "
> It is possible for several tc filters to share the same police action by
> specifying the action's index when installing the filters.
>
> Propagate this index to device drivers through the flow offload
> intermediate representation, so that drivers could share a single hardware
> policer between multiple filters.
> "
>
> >
> > Signed-off-by: Po Liu
> > ---
> > include/net/flow_offload.h | 1 +
> > net/sched/cls_api.c| 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
> > index c2ef19c6b27d..eed98075b1ae 100644
> > --- a/include/net/flow_offload.h
> > +++ b/include/net/flow_offload.h
> > @@ -232,6 +232,7 @@ struct flow_action_entry {
> > booltruncate;
> > } sample;
> > struct {/* FLOW_ACTION_POLICE
> > */
> > + u32 index;
> > s64 burst;
> > u64 rate_bytes_ps;
> > u32 mtu;
> > diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c index
> > 6aba7d5ba1ec..fdc4c89ca1fa 100644
> > --- a/net/sched/cls_api.c
> > +++ b/net/sched/cls_api.c
> > @@ -3659,6 +3659,7 @@ int tc_setup_flow_action(struct flow_action
> *flow_action,
> > entry->police.rate_bytes_ps =
> > tcf_police_rate_bytes_ps(act);
> > entry->police.mtu = tcf_police_tcfp_mtu(act);
> > + entry->police.index = act->tcfa_index;
> > } else if (is_tcf_ct(act)) {
> > entry->id = FLOW_ACTION_CT;
> > entry->ct.action = tcf_ct_action(act);
> > --
> > 2.17.1
> >
[v1,net-next 4/4] net: enetc add tc flower offload flow metering policing action
From: Po Liu
Flow metering entries in IEEE 802.1Qci is an optional function for a
flow filtering module. Flow metering is two rates two buckets and three
color marker to policing the frames. This patch only enable one rate one
bucket and in color blind mode. Flow metering instance are as
specified in the algorithm in MEF 10.3 and in Bandwidth Profile
Parameters. They are:
a) Flow meter instance identifier. An integer value identifying the flow
meter instance. The patch use the police 'index' as thin value.
b) Committed Information Rate (CIR), in bits per second. This patch use
the 'rate_bytes_ps' represent this value.
c) Committed Burst Size (CBS), in octets. This patch use the 'burst'
represent this value.
d) Excess Information Rate (EIR), in bits per second.
e) Excess Burst Size per Bandwidth Profile Flow (EBS), in octets.
And plus some other parameters. This patch set EIR/EBS default disable
and color blind mode.
Signed-off-by: Po Liu
---
.../net/ethernet/freescale/enetc/enetc_hw.h | 24 +++
.../net/ethernet/freescale/enetc/enetc_qos.c | 160 --
2 files changed, 172 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
index 6314051bc6c1..f00c4382423e 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
@@ -570,6 +570,7 @@ enum bdcr_cmd_class {
BDCR_CMD_STREAM_IDENTIFY,
BDCR_CMD_STREAM_FILTER,
BDCR_CMD_STREAM_GCL,
+ BDCR_CMD_FLOW_METER,
__BDCR_CMD_MAX_LEN,
BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
};
@@ -736,10 +737,33 @@ struct sgcl_data {
struct sgce sgcl[0];
};
+#define ENETC_CBDR_FMI_MR BIT(0)
+#define ENETC_CBDR_FMI_MRENBIT(1)
+#define ENETC_CBDR_FMI_DOY BIT(2)
+#defineENETC_CBDR_FMI_CM BIT(3)
+#define ENETC_CBDR_FMI_CF BIT(4)
+#define ENETC_CBDR_FMI_NDORBIT(5)
+#define ENETC_CBDR_FMI_OALEN BIT(6)
+#define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)
+
+/* class 10: command 0/1, Flow Meter Instance Set, short Format */
+struct fmi_conf {
+ __le32 cir;
+ __le32 cbs;
+ __le32 eir;
+ __le32 ebs;
+ u8 conf;
+ u8 res1;
+ u8 ir_fpp;
+ u8 res2[4];
+ u8 en;
+};
+
struct enetc_cbd {
union{
struct sfi_conf sfi_conf;
struct sgi_table sgi_table;
+ struct fmi_conf fmi_conf;
struct {
__le32 addr[2];
union {
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
index 07f98bf7a06b..2d79962daf4a 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
@@ -408,10 +408,26 @@ struct enetc_psfp_gate {
struct action_gate_entry entries[0];
};
+/* Only enable the green color frame now
+ * Will add eir and ebs color blind, couple flag etc when
+ * policing action add more offloading parameters
+ */
+struct enetc_psfp_meter {
+ u32 index;
+ u32 cir;
+ u32 cbs;
+ refcount_t refcount;
+ struct hlist_node node;
+};
+
+#define ENETC_PSFP_FLAGS_FMI BIT(0)
+
struct enetc_stream_filter {
struct enetc_streamid sid;
u32 sfi_index;
u32 sgi_index;
+ u32 flags;
+ u32 fmi_index;
struct flow_stats stats;
struct hlist_node node;
};
@@ -422,6 +438,7 @@ struct enetc_psfp {
struct hlist_head stream_list;
struct hlist_head psfp_filter_list;
struct hlist_head psfp_gate_list;
+ struct hlist_head psfp_meter_list;
spinlock_t psfp_lock; /* spinlock for the struct enetc_psfp r/w */
};
@@ -842,6 +859,47 @@ static int enetc_streamgate_hw_set(struct enetc_ndev_priv
*priv,
return err;
}
+static int enetc_flowmeter_hw_set(struct enetc_ndev_priv *priv,
+ struct enetc_psfp_meter *fmi,
+ u8 enable)
+{
+ struct enetc_cbd cbd = { .cmd = 0 };
+ struct fmi_conf *fmi_config;
+ u64 temp = 0;
+
+ cbd.index = cpu_to_le16((u16)fmi->index);
+ cbd.cls = BDCR_CMD_FLOW_METER;
+ cbd.status_flags = 0x80;
+
+ if (!enable)
+ return enetc_send_cmd(priv->si, );
+
+ fmi_config = _conf;
+ fmi_config->en = 0x80;
+
+ if (fmi->cir) {
+ temp = (u64)8000 * fmi->cir;
+ temp = temp / 3725;
+ }
+
+ fmi_config->cir = cpu_to_le32((u32)temp);
+ fmi_config->cbs = cpu_to_le32(fmi->cbs);
+
+ /* Default for eir ebs disable */
+ fmi_config->eir = 0;
+ fmi_config->ebs = 0;
+
+ /* Default:
+* mark red disable
+* drop on yellow disable
+* color mode disable
[v1,net-next 2/4] net: enetc: add support max frame size for tc flower offload
From: Po Liu
Base on the tc flower offload police action add max frame size by the
parameter 'mtu'. Tc flower device driver working by the IEEE 802.1Qci
stream filter can implement the max frame size filtering. Add it to the
current hardware tc flower stearm filter driver.
Signed-off-by: Po Liu
---
.../net/ethernet/freescale/enetc/enetc_qos.c | 52 +--
1 file changed, 36 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
index fb76903eca90..07f98bf7a06b 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_qos.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_qos.c
@@ -389,6 +389,7 @@ struct enetc_psfp_filter {
u32 index;
s32 handle;
s8 prio;
+ u32 maxsdu;
u32 gate_id;
s32 meter_id;
refcount_t refcount;
@@ -430,6 +431,12 @@ static struct actions_fwd enetc_act_fwd[] = {
BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS),
FILTER_ACTION_TYPE_PSFP
},
+ {
+ BIT(FLOW_ACTION_POLICE) |
+ BIT(FLOW_ACTION_GATE),
+ BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS),
+ FILTER_ACTION_TYPE_PSFP
+ },
/* example for ACL actions */
{
BIT(FLOW_ACTION_DROP),
@@ -594,8 +601,12 @@ static int enetc_streamfilter_hw_set(struct
enetc_ndev_priv *priv,
/* Filter Type. Identifies the contents of the MSDU/FM_INST_INDEX
* field as being either an MSDU value or an index into the Flow
* Meter Instance table.
-* TODO: no limit max sdu
*/
+ if (sfi->maxsdu) {
+ sfi_config->msdu =
+ cpu_to_le16(sfi->maxsdu);
+ sfi_config->multi |= 0x40;
+ }
if (sfi->meter_id >= 0) {
sfi_config->fm_inst_table_index = cpu_to_le16(sfi->meter_id);
@@ -872,6 +883,7 @@ static struct enetc_psfp_filter
hlist_for_each_entry(s, _filter_list, node)
if (s->gate_id == sfi->gate_id &&
s->prio == sfi->prio &&
+ s->maxsdu == sfi->maxsdu &&
s->meter_id == sfi->meter_id)
return s;
@@ -979,6 +991,7 @@ static struct actions_fwd *enetc_check_flow_actions(u64
acts,
static int enetc_psfp_parse_clsflower(struct enetc_ndev_priv *priv,
struct flow_cls_offload *f)
{
+ struct flow_action_entry *entryg = NULL, *entryp = NULL;
struct flow_rule *rule = flow_cls_offload_flow_rule(f);
struct netlink_ext_ack *extack = f->common.extack;
struct enetc_stream_filter *filter, *old_filter;
@@ -997,9 +1010,12 @@ static int enetc_psfp_parse_clsflower(struct
enetc_ndev_priv *priv,
flow_action_for_each(i, entry, >action)
if (entry->id == FLOW_ACTION_GATE)
- break;
+ entryg = entry;
+ else if (entry->id == FLOW_ACTION_POLICE)
+ entryp = entry;
- if (entry->id != FLOW_ACTION_GATE)
+ /* Not support without gate action */
+ if (!entryg)
return -EINVAL;
filter = kzalloc(sizeof(*filter), GFP_KERNEL);
@@ -1079,19 +1095,19 @@ static int enetc_psfp_parse_clsflower(struct
enetc_ndev_priv *priv,
}
/* parsing gate action */
- if (entry->gate.index >= priv->psfp_cap.max_psfp_gate) {
+ if (entryg->gate.index >= priv->psfp_cap.max_psfp_gate) {
NL_SET_ERR_MSG_MOD(extack, "No Stream Gate resource!");
err = -ENOSPC;
goto free_filter;
}
- if (entry->gate.num_entries >= priv->psfp_cap.max_psfp_gatelist) {
+ if (entryg->gate.num_entries >= priv->psfp_cap.max_psfp_gatelist) {
NL_SET_ERR_MSG_MOD(extack, "No Stream Gate resource!");
err = -ENOSPC;
goto free_filter;
}
- entries_size = struct_size(sgi, entries, entry->gate.num_entries);
+ entries_size = struct_size(sgi, entries, entryg->gate.num_entries);
sgi = kzalloc(entries_size, GFP_KERNEL);
if (!sgi) {
err = -ENOMEM;
@@ -1099,18 +1115,18 @@ static int enetc_psfp_parse_clsflower(struct
enetc_ndev_priv *priv,
}
refcount_set(>refcount, 1);
- sgi->index = entry->gate.index;
- sgi->init_ipv = entry->gate.prio;
- sgi->basetime = entry->gate.basetime;
- sgi->cycletime = entry->gate.cycletime;
- sgi->num_entries = entry->gate.num_entries;
+ sgi->index = entryg->gate.index;
+ sgi->init_ipv = entryg->gate.prio;
+ sgi->basetime = entryg->gate.basetime;
+ sgi->cycletime = entryg->ga
[v1,net-next 3/4] net: qos: police action add index for tc flower offloading
From: Po Liu
Hardware may own many entries for police flow. So that make one(or
multi) flow to be policed by one hardware entry. This patch add the
police action index provide to the driver side make it mapping the
driver hardware entry index.
Signed-off-by: Po Liu
---
include/net/flow_offload.h | 1 +
net/sched/cls_api.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
index c2ef19c6b27d..eed98075b1ae 100644
--- a/include/net/flow_offload.h
+++ b/include/net/flow_offload.h
@@ -232,6 +232,7 @@ struct flow_action_entry {
booltruncate;
} sample;
struct {/* FLOW_ACTION_POLICE */
+ u32 index;
s64 burst;
u64 rate_bytes_ps;
u32 mtu;
diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c
index 6aba7d5ba1ec..fdc4c89ca1fa 100644
--- a/net/sched/cls_api.c
+++ b/net/sched/cls_api.c
@@ -3659,6 +3659,7 @@ int tc_setup_flow_action(struct flow_action *flow_action,
entry->police.rate_bytes_ps =
tcf_police_rate_bytes_ps(act);
entry->police.mtu = tcf_police_tcfp_mtu(act);
+ entry->police.index = act->tcfa_index;
} else if (is_tcf_ct(act)) {
entry->id = FLOW_ACTION_CT;
entry->ct.action = tcf_ct_action(act);
--
2.17.1
[v1,net-next 1/4] net: qos: add tc police offloading action with max frame size limit
From: Po Liu
Current police offloading support the 'burst'' and 'rate_bytes_ps'. Some
hardware own the capability to limit the frame size. If the frame size
larger than the setting, the frame would be dropped. For the police
action itself already accept the 'mtu' parameter in tc command. But not
extend to tc flower offloading. So extend 'mtu' to tc flower offloading.
Signed-off-by: Po Liu
---
continue the thread 20200306125608.11717-7-po@nxp.com for the police
action offloading.
include/net/flow_offload.h | 1 +
include/net/tc_act/tc_police.h | 10 ++
net/sched/cls_api.c| 1 +
3 files changed, 12 insertions(+)
diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
index 00c15f14c434..c2ef19c6b27d 100644
--- a/include/net/flow_offload.h
+++ b/include/net/flow_offload.h
@@ -234,6 +234,7 @@ struct flow_action_entry {
struct {/* FLOW_ACTION_POLICE */
s64 burst;
u64 rate_bytes_ps;
+ u32 mtu;
} police;
struct {/* FLOW_ACTION_CT */
int action;
diff --git a/include/net/tc_act/tc_police.h b/include/net/tc_act/tc_police.h
index f098ad4424be..cd973b10ae8c 100644
--- a/include/net/tc_act/tc_police.h
+++ b/include/net/tc_act/tc_police.h
@@ -69,4 +69,14 @@ static inline s64 tcf_police_tcfp_burst(const struct
tc_action *act)
return params->tcfp_burst;
}
+static inline u32 tcf_police_tcfp_mtu(const struct tc_action *act)
+{
+ struct tcf_police *police = to_police(act);
+ struct tcf_police_params *params;
+
+ params = rcu_dereference_protected(police->params,
+ lockdep_is_held(>tcf_lock));
+ return params->tcfp_mtu;
+}
+
#endif /* __NET_TC_POLICE_H */
diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c
index a00a203b2ef5..6aba7d5ba1ec 100644
--- a/net/sched/cls_api.c
+++ b/net/sched/cls_api.c
@@ -3658,6 +3658,7 @@ int tc_setup_flow_action(struct flow_action *flow_action,
entry->police.burst = tcf_police_tcfp_burst(act);
entry->police.rate_bytes_ps =
tcf_police_rate_bytes_ps(act);
+ entry->police.mtu = tcf_police_tcfp_mtu(act);
} else if (is_tcf_ct(act)) {
entry->id = FLOW_ACTION_CT;
entry->ct.action = tcf_ct_action(act);
--
2.17.1
RE: Re: [RFC,net-next 8/9] net: qos: police action add index for tc flower offloading
Hi Ido,
> -Original Message-
> From: Ido Schimmel
> Sent: 2020年6月21日 18:04
> To: Po Liu
> Cc: da...@davemloft.net; linux-kernel@vger.kernel.org;
> net...@vger.kernel.org; vinicius.go...@intel.com; Claudiu Manoil
> ; Vladimir Oltean ;
> Alexandru Marginean ; Xiaoliang Yang
> ; Roy Zang ; Mingkai Hu
> ; Jerry Huang ; Leo Li
> ; michael.c...@broadcom.com; vis...@chelsio.com;
> sae...@mellanox.com; l...@kernel.org; j...@mellanox.com;
> ido...@mellanox.com; alexandre.bell...@bootlin.com;
> unglinuxdri...@microchip.com; k...@kernel.org; j...@mojatatu.com;
> xiyou.wangc...@gmail.com; john.hur...@netronome.com;
> simon.hor...@netronome.com;
> pieter.jansenvanvuu...@netronome.com; pa...@netfilter.org;
> mo...@mellanox.com; ivan.khoronz...@linaro.org; m-kariche...@ti.com;
> andre.gue...@linux.intel.com; jakub.kicin...@netronome.com
> Subject: Re: [RFC,net-next 8/9] net: qos: police action add index for
> tc flower offloading
>
>
> On Fri, Mar 06, 2020 at 08:56:06PM +0800, Po Liu wrote:
> > Hardware may own many entries for police flow. So that make one(or
> > multi) flow to be policed by one hardware entry. This patch add the
> > police action index provide to the driver side make it mapping the
> > driver hardware entry index.
> >
> > Signed-off-by: Po Liu
>
> Hi,
>
> I started looking into tc-police offload in mlxsw and remembered your
> patch. Are you planning to formally submit it? I'm asking because in mlxsw
> it is also possible to share the same policer between multiple filters.
Yes, I am preparing the patches and push again very soon. The patches will add
mtu and index for offloading as first step.
The next step is seeking method to implement two color + two buckets mode but
seems absent one bucket in policing action. The current burst + rate_bytes_ps
only can only implement one color+ one bucket policing.
>
> Thanks
>
> > ---
> > include/net/flow_offload.h | 1 +
> > net/sched/cls_api.c| 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
> > index 54df87328edc..3b78b15ed20b 100644
> > --- a/include/net/flow_offload.h
> > +++ b/include/net/flow_offload.h
> > @@ -201,6 +201,7 @@ struct flow_action_entry {
> > booltruncate;
> > } sample;
> > struct {/* FLOW_ACTION_POLICE
> > */
> > + u32 index;
> > s64 burst;
> > u64 rate_bytes_ps;
> > u32 mtu;
> > diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c index
> > 363d3991793d..ce846a9dadc1 100644
> > --- a/net/sched/cls_api.c
> > +++ b/net/sched/cls_api.c
> > @@ -3584,6 +3584,7 @@ int tc_setup_flow_action(struct flow_action
> *flow_action,
> > entry->police.rate_bytes_ps =
> > tcf_police_rate_bytes_ps(act);
> > entry->police.mtu = tcf_police_mtu(act);
> > + entry->police.index = act->tcfa_index;
> > } else if (is_tcf_ct(act)) {
> > entry->id = FLOW_ACTION_CT;
> > entry->ct.action = tcf_ct_action(act);
> > --
> > 2.17.1
> >
Thanks a lot!
Br,
Po Liu
[v2,net-next] net: qos offload add flow status with dropped count
From: Po Liu This patch adds a drop frames counter to tc flower offloading. Reporting h/w dropped frames is necessary for some actions. Some actions like police action and the coming introduced stream gate action would produce dropped frames which is necessary for user. Status update shows how many filtered packets increasing and how many dropped in those packets. v2: Changes - Update commit comments suggest by Jiri Pirko. Signed-off-by: Po Liu --- This patch is continue the thread 20200324034745.30979-1-po@nxp.com drivers/net/dsa/sja1105/sja1105_vl.c | 2 +- drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c | 2 +- drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c | 2 +- .../net/ethernet/chelsio/cxgb4/cxgb4_tc_matchall.c| 2 +- drivers/net/ethernet/freescale/enetc/enetc_qos.c | 7 +-- drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c| 2 +- drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 4 ++-- drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c | 2 +- drivers/net/ethernet/mscc/ocelot_flower.c | 2 +- drivers/net/ethernet/netronome/nfp/flower/offload.c | 2 +- drivers/net/ethernet/netronome/nfp/flower/qos_conf.c | 2 +- include/net/act_api.h | 11 ++- include/net/flow_offload.h| 5 - include/net/pkt_cls.h | 5 +++-- net/sched/act_api.c | 10 -- net/sched/act_ct.c| 6 +++--- net/sched/act_gact.c | 7 --- net/sched/act_gate.c | 6 +++--- net/sched/act_mirred.c| 6 +++--- net/sched/act_pedit.c | 6 +++--- net/sched/act_police.c| 4 ++-- net/sched/act_skbedit.c | 5 +++-- net/sched/act_vlan.c | 6 +++--- net/sched/cls_flower.c| 1 + net/sched/cls_matchall.c | 3 ++- 25 files changed, 60 insertions(+), 50 deletions(-) diff --git a/drivers/net/dsa/sja1105/sja1105_vl.c b/drivers/net/dsa/sja1105/sja1105_vl.c index bdfd6c4e190d..9ddc49b7eb8f 100644 --- a/drivers/net/dsa/sja1105/sja1105_vl.c +++ b/drivers/net/dsa/sja1105/sja1105_vl.c @@ -771,7 +771,7 @@ int sja1105_vl_stats(struct sja1105_private *priv, int port, pkts = timingerr + unreleased + lengtherr; - flow_stats_update(stats, 0, pkts - rule->vl.stats.pkts, + flow_stats_update(stats, 0, pkts - rule->vl.stats.pkts, 0, jiffies - rule->vl.stats.lastused, FLOW_ACTION_HW_STATS_IMMEDIATE); diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c index 0eef4f5e4a46..4d482d75a20b 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c @@ -1638,7 +1638,7 @@ static int bnxt_tc_get_flow_stats(struct bnxt *bp, lastused = flow->lastused; spin_unlock(>stats_lock); - flow_stats_update(_flow_cmd->stats, stats.bytes, stats.packets, + flow_stats_update(_flow_cmd->stats, stats.bytes, stats.packets, 0, lastused, FLOW_ACTION_HW_STATS_DELAYED); return 0; } diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c index 4a5fa9eba0b6..030de20a5d27 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c @@ -902,7 +902,7 @@ int cxgb4_tc_flower_stats(struct net_device *dev, if (ofld_stats->prev_packet_count != packets) ofld_stats->last_used = jiffies; flow_stats_update(>stats, bytes - ofld_stats->byte_count, - packets - ofld_stats->packet_count, + packets - ofld_stats->packet_count, 0, ofld_stats->last_used, FLOW_ACTION_HW_STATS_IMMEDIATE); diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_matchall.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_matchall.c index c88c47a14fbb..c439b5bce9c9 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_matchall.c +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_matchall.c @@ -346,7 +346,7 @@ int cxgb4_tc_matchall_stats(struct net_device *dev, flow_stats_update(_matchall->stats, bytes - tc_port_matchall->ingress.bytes, packets - tc_port_matchall->ingress.packets, - tc_port_matchall->ingress.last_used, +
[v5,iproute2-next 1/2] iproute2-next:tc:action: add a gate control action
Introduce a ingress frame gate control flow action.
Tc gate action does the work like this:
Assume there is a gate allow specified ingress frames can pass at
specific time slot, and also drop at specific time slot. Tc filter
chooses the ingress frames, and tc gate action would specify what slot
does these frames can be passed to device and what time slot would be
dropped.
Tc gate action would provide an entry list to tell how much time gate
keep open and how much time gate keep state close. Gate action also
assign a start time to tell when the entry list start. Then driver would
repeat the gate entry list cyclically.
For the software simulation, gate action require the user assign a time
clock type.
Below is the setting example in user space. Tc filter a stream source ip
address is 192.168.0.20 and gate action own two time slots. One is last
200ms gate open let frame pass another is last 100ms gate close let
frames dropped.
# tc qdisc add dev eth0 ingress
# tc filter add dev eth0 parent : protocol ip \
flower src_ip 192.168.0.20 \
action gate index 2 clockid CLOCK_TAI \
sched-entry open 2ns -1 800b \
sched-entry close 1ns
# tc chain del dev eth0 ingress chain 0
"sched-entry" follow the name taprio style. Gate state is
"open"/"close". Follow the period nanosecond. Then next -1 is internal
priority value means which ingress queue should put to. "-1" means
wildcard. The last value optional specifies the maximum number of
MSDU octets that are permitted to pass the gate during the specified
time interval, the overlimit frames would be dropped.
Below example shows filtering a stream with destination mac address is
10:00:80:00:00:00 and ip type is ICMP, follow the action gate. The gate
action would run with one close time slot which means always keep close.
The time cycle is total 2ns. The base-time would calculate by:
13570 + (N + 1) * cycletime
When the total value is the future time, it will be the start time.
The cycletime here would be 2ns for this case.
#tc filter add dev eth0 parent : protocol ip \
flower skip_hw ip_proto icmp dst_mac 10:00:80:00:00:00 \
action gate index 12 base-time 13570ns \
sched-entry CLOSE 2ns \
clockid CLOCK_TAI
Signed-off-by: Po Liu
---
These patches continue request for support iprout2 tc command input gate
action since kernel patch applied (a51c328df310 net: qos: introduce a
gate control flow action).
Continue the version 3.
Changes from v2:
Fix flexible input for a time slot - sched-entry suggested by Vladimir
Oltean and Vinicius Gomes:
- ipv and maxoctets in a sched-entry can be ignore input default to be
wildcard(values are -1).
Changes from v3:
- Fix json 'gate state' output update json format output: add array for
'sched-entry'
- Update input for 'sched-entry' parameters absense conditions
Changes from v4:
- Add support unified tc command time and size routine suggested by
'Stephen Hemminger':
input 'base-time' 'cycle-time' could input as '100ns' '200.0ms' and also
support the default decimal number input as how many nano-seconds.
input 'maxoctets' support as tc command size routine and also support
the default decimal number input as how many byte.
- Update the commit example with input/output time and size routine
- Fix duplicate parse_action_control* action control suggested by 'Davide
Caratti'
---
include/uapi/linux/pkt_cls.h| 1 +
include/uapi/linux/tc_act/tc_gate.h | 47 +++
tc/Makefile | 1 +
tc/m_gate.c | 580
4 files changed, 629 insertions(+)
create mode 100644 include/uapi/linux/tc_act/tc_gate.h
create mode 100644 tc/m_gate.c
diff --git a/include/uapi/linux/pkt_cls.h b/include/uapi/linux/pkt_cls.h
index 9f06d29c..fc672b23 100644
--- a/include/uapi/linux/pkt_cls.h
+++ b/include/uapi/linux/pkt_cls.h
@@ -134,6 +134,7 @@ enum tca_id {
TCA_ID_CTINFO,
TCA_ID_MPLS,
TCA_ID_CT,
+ TCA_ID_GATE,
/* other actions go here */
__TCA_ID_MAX = 255
};
diff --git a/include/uapi/linux/tc_act/tc_gate.h
b/include/uapi/linux/tc_act/tc_gate.h
new file mode 100644
index ..f214b3a6
--- /dev/null
+++ b/include/uapi/linux/tc_act/tc_gate.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/* Copyright 2020 NXP */
+
+#ifndef __LINUX_TC_GATE_H
+#define __LINUX_TC_GATE_H
+
+#include
+
+struct tc_gate {
+ tc_gen;
+};
+
+enum {
+ TCA_GATE_ENTRY_UNSPEC,
+ TCA_GATE_ENTRY_INDEX,
+ TCA_GATE_ENTRY_GATE,
+ TCA_GATE_ENTRY_INTERVAL,
+ TCA_GATE_ENTRY_IPV,
+ TCA_GATE_ENTRY_MAX_OCTETS,
+ __TCA_GATE_ENTRY_MAX,
+};
+#define TCA_GATE_ENTRY_MAX (__TCA_GATE_ENTRY_MAX - 1)
+
+enum {
+ TCA_GATE_ONE_
[v5,iproute2-next 2/2] iproute2-next: add gate action man page
This patch is to add the man page for the tc gate action. Signed-off-by: Po Liu --- changes before v4: No changes. changes from v4: - Update the examples with input/output time and size routine support man/man8/tc-gate.8 | 123 + 1 file changed, 123 insertions(+) create mode 100644 man/man8/tc-gate.8 diff --git a/man/man8/tc-gate.8 b/man/man8/tc-gate.8 new file mode 100644 index ..23d93ca4 --- /dev/null +++ b/man/man8/tc-gate.8 @@ -0,0 +1,123 @@ +.TH GATE 8 "12 Mar 2020" "iproute2" "Linux" +.SH NAME +gate \- Stream Gate Action +.SH SYNOPSIS +.B tc " ... " action gate +.ti +8 +.B [ base-time +BASETIME ] +.B [ clockid +CLOCKID ] +.ti +8 +.B sched-entry + [ ] +.ti +8 +.B sched-entry + [ ] +.ti +8 +.B sched-entry + [ ] +.ti +8 +.B .. +.ti +8 +.B sched-entry + [ ] + +.SH DESCRIPTION +GATE action allows specified ingress frames can be passed at +specific time slot, or be dropped at specific time slot. Tc filter +filters the ingress frames, then tc gate action would specify which time +slot and how many bytes these frames can be passed to device and +which time slot frames would be dropped. +Gate action also assign a base-time to tell when the entry list start. +Then gate action would start to repeat the gate entry list cyclically +at the start base-time. +For the software simulation, gate action requires the user assign reference +time clock type. + +.SH PARAMETERS + +.TP +base-time +.br +Specifies the instant in nanoseconds, defining the time when the schedule +starts. If 'base-time' is a time in the past, the schedule will start at + +base-time + (N * cycle-time) + +where N is the smallest integer so the resulting time is greater than +"now", and "cycle-time" is the sum of all the intervals of the entries +in the schedule. Without base-time specified, will default to be 0. + +.TP +clockid +.br +Specifies the clock to be used by qdisc's internal timer for measuring +time and scheduling events. Not valid if gate action is used for offloading +filter. +For example, tc filter command with +.B skip_sw +parameter. + +.TP +sched-entry +.br +There may multiple +.B sched-entry +parameters in a single schedule. Each one has the format: + +sched-entry [ ] + +.br + means gate states. 'open' keep gate open, 'close' keep gate close. +.br + means how much nano seconds for this time slot. +.br + means internal priority value. Present of the +internal receiving queue for this stream. "-1" means wildcard. + and can be omit default to be "-1" which both + value to be "-1" for this . +.br + means how many octets size could pass in this time slot. Dropped +if overlimited. "-1" means wildcard. can be omit default to be +"-1" which value to be "-1" for this . +.br +Note that and are nothing meaning for gate state +is "close" in a "sched-entry". All frames are dropped when "sched-entry" with +"close" state. + +.SH EXAMPLES + +The following example shows tc filter frames source ip match to the +192.168.0.20 will keep the gate open for 200ms and limit the traffic to 8MB +in this sched-entry. Then keep the traffic gate to be close for 100ms. +Frames arrived at gate close state would be dropped. Then the cycle would +run the gate entries periodically. The schedule will start at instant 200.0s +using the reference CLOCK_TAI. The schedule is composed of two entries +each of 300ms duration. + +.EX +# tc qdisc add dev eth0 ingress +# tc filter add dev eth0 parent : protocol ip \\ + flower skip_hw src_ip 192.168.0.20 \\ + action gate index 2 clockid CLOCK_TAI \\ + base-time 2000ns \\ + sched-entry open 2ns -1 800b \\ + sched-entry close 1ns + +.EE + +Following commands is an example to filter a stream source mac match to the +10:00:80:00:00:00 icmp frames will be dropped at any time with cycle 200ms. +With a default basetime 0 and clockid is CLOCK_TAI as default. + +.EX +# tc qdisc add dev eth0 ingress +# tc filter add dev eth0 parent ffff: protocol ip \\ + flower ip_proto icmp dst_mac 10:00:80:00:00:00 \\ + action gate index 12 sched-entry close 2ns + +.EE + +.SH AUTHORS +Po Liu -- 2.17.1
RE: Re: [v4,iproute2-next 1/2] iproute2-next:tc:action: add a gate control action
Hi Stephen,
> -Original Message-
> From: Po Liu
> Sent: 2020年5月7日 10:53
> To: Stephen Hemminger
> Cc: dsah...@gmail.com; linux-kernel@vger.kernel.org;
> net...@vger.kernel.org; vinicius.go...@intel.com;
> da...@davemloft.net; v...@buslov.dev; Claudiu Manoil
> ; Vladimir Oltean ;
> Alexandru Marginean
> Subject: RE: Re: [v4,iproute2-next 1/2] iproute2-next:tc:action: add a gate
> control action
>
> Hi Stephen,
>
>
> > -Original Message-
> > From: Stephen Hemminger
> > Sent: 2020年5月6日 23:22
> > To: Po Liu
> > Cc: dsah...@gmail.com; linux-kernel@vger.kernel.org;
> > net...@vger.kernel.org; vinicius.go...@intel.com;
> da...@davemloft.net;
> > v...@buslov.dev; Claudiu Manoil ; Vladimir
> > Oltean ; Alexandru Marginean
> >
> > Subject: Re: [v4,iproute2-next 1/2] iproute2-next:tc:action: add a
> > gate control action On Wed, 6 May 2020 16:40:19 +0800 Po Liu
> > wrote:
> >
> > > } else if (matches(*argv, "base-time") == 0) {
> > > + NEXT_ARG();
> > > + if (get_u64(_time, *argv, 10)) {
> > > + invalidarg = "base-time";
> > > + goto err_arg;
> > > + }
> > > + } else if (matches(*argv, "cycle-time") == 0) {
> > > + NEXT_ARG();
> > > + if (get_u64(_time, *argv, 10)) {
> > > + invalidarg = "cycle-time";
> > > + goto err_arg;
> > > + }
> > > + } else if (matches(*argv, "cycle-time-ext") == 0) {
> > > + NEXT_ARG();
> > > + if (get_u64(_time_ext, *argv, 10)) {
> > > + invalidarg = "cycle-time-ext";
> > > + goto err_arg;
> > > + }
> >
> > Could all these time values use existing TC helper routines?
>
> I agree to keep the tc routines input.
> The names of timer input and type is more reference the taprio input.
>
Shall I support both input method. The default decimal input like 12
default to nano-second and formal time routines like 120us.
Then the tc show command shows formal time routines like 120us whatever in
non-json format. Json format shows a decimal number only which is always done
by other tc command.
So this would compatible with kernel commit commands examples. But I would
mention in the man pages supporting the timer routines input.
> > See get_time(). The way you have it makes sense for hardware but
> > stands out versus the rest of tc.
> >
> > It maybe that the kernel UAPI is wrong, and should be using same time
> > units as rest of tc. Forgot to review that part of the patch.
>
> I would also sync with kernel UAPI if needed.
I checked the gate UAPI file, there is nothing need to changed for time format.
>
>
> Br,
> Po Liu
Br,
Po Liu
[net-next] net:enetc: bug fix for qos sfi operate space after freed
'Dan Carpenter' reported: This code frees "sfi" and then dereferences it on the next line: > kfree(sfi); > clear_bit(sfi->index, epsfp.psfp_sfi_bitmap); This "sfi->index" should be "index". Reported-by: Dan Carpenter Signed-off-by: Po Liu --- drivers/net/ethernet/freescale/enetc/enetc_qos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/freescale/enetc/enetc_qos.c b/drivers/net/ethernet/freescale/enetc/enetc_qos.c index 48e589e9d0f7..77f110e24505 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_qos.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_qos.c @@ -903,7 +903,7 @@ static void stream_filter_unref(struct enetc_ndev_priv *priv, u32 index) enetc_streamfilter_hw_set(priv, sfi, false); hlist_del(>node); kfree(sfi); - clear_bit(sfi->index, epsfp.psfp_sfi_bitmap); + clear_bit(index, epsfp.psfp_sfi_bitmap); } } -- 2.17.1
RE: Re: [v4,iproute2-next 1/2] iproute2-next:tc:action: add a gate control action
Hi Stephen,
> -Original Message-
> From: Stephen Hemminger
> Sent: 2020年5月6日 23:22
> To: Po Liu
> Cc: dsah...@gmail.com; linux-kernel@vger.kernel.org;
> net...@vger.kernel.org; vinicius.go...@intel.com;
> da...@davemloft.net; v...@buslov.dev; Claudiu Manoil
> ; Vladimir Oltean ;
> Alexandru Marginean
> Subject: Re: [v4,iproute2-next 1/2] iproute2-next:tc:action: add a
> gate control action
> On Wed, 6 May 2020 16:40:19 +0800
> Po Liu wrote:
>
> > } else if (matches(*argv, "base-time") == 0) {
> > + NEXT_ARG();
> > + if (get_u64(_time, *argv, 10)) {
> > + invalidarg = "base-time";
> > + goto err_arg;
> > + }
> > + } else if (matches(*argv, "cycle-time") == 0) {
> > + NEXT_ARG();
> > + if (get_u64(_time, *argv, 10)) {
> > + invalidarg = "cycle-time";
> > + goto err_arg;
> > + }
> > + } else if (matches(*argv, "cycle-time-ext") == 0) {
> > + NEXT_ARG();
> > + if (get_u64(_time_ext, *argv, 10)) {
> > + invalidarg = "cycle-time-ext";
> > + goto err_arg;
> > + }
>
> Could all these time values use existing TC helper routines?
I agree to keep the tc routines input.
The names of timer input and type is more reference the taprio input.
> See get_time(). The way you have it makes sense for hardware but stands
> out versus the rest of tc.
>
> It maybe that the kernel UAPI is wrong, and should be using same time
> units as rest of tc. Forgot to review that part of the patch.
I would also sync with kernel UAPI if needed.
Br,
Po Liu
RE: [EXT] Re: [v4,iproute2-next 1/2] iproute2-next:tc:action: add a gate control action
Hi Davide,
> -Original Message-
> From: Davide Caratti
> Sent: 2020年5月6日 20:54
> To: Po Liu ; dsah...@gmail.com; linux-
> ker...@vger.kernel.org; net...@vger.kernel.org
> Cc: vinicius.go...@intel.com; step...@networkplumber.org;
> da...@davemloft.net; v...@buslov.dev; Claudiu Manoil
> ; Vladimir Oltean ;
> Alexandru Marginean
> Subject: [EXT] Re: [v4,iproute2-next 1/2] iproute2-next:tc:action: add a
> gate control action
>
> Caution: EXT Email
>
> On Wed, 2020-05-06 at 16:40 +0800, Po Liu wrote:
> > Introduce a ingress frame gate control flow action.
> [...]
>
> hello Po Liu,
>
> [...]
>
> > +create_entry:
> > + e = create_gate_entry(gate_state, interval,
> > + ipv, maxoctets);
> > + if (!e) {
> > + fprintf(stderr, "gate: not enough memory\n");
> > + free_entries(_entries);
> > + return -1;
> > + }
> > +
> > + list_add_tail(>list, _entries);
> > + entry_num++;
> > +
> > + } else if (matches(*argv, "reclassify") == 0 ||
> > +matches(*argv, "drop") == 0 ||
> > +matches(*argv, "shot") == 0 ||
> > +matches(*argv, "continue") == 0 ||
> > +matches(*argv, "pass") == 0 ||
> > +matches(*argv, "ok") == 0 ||
> > +matches(*argv, "pipe") == 0 ||
> > +matches(*argv, "goto") == 0) {
> > + if (parse_action_control(, ,
> > + , false)) {
> > + free_entries(_entries);
> > + return -1;
> > + }
> > + } else if (matches(*argv, "help") == 0) {
> > + usage();
> > + } else {
> > + break;
> > + }
> > +
> > + argc--;
> > + argv++;
> > + }
> > +
> > + parse_action_control_dflt(, , ,
> > + false, TC_ACT_PIPE);
>
> it seems that the control action is parsed twice, and the first time it does
> not allow "jump" and "trap". Is that intentional? IOW, are there some
> "act_gate" configurations that don't allow jump or trap?
It is allowed to jump and trap. I didn't notice it was loaded twice. I would
correct here and remove one parse_action_control()
Thanks a lot!
>
> I don't see anything similar in kernel act_gate.c, where tcf_gate_act() can
> return TC_ACT_SHOT or whatever is written in parm.action. That's why I'm
> asking, if these two control actions are forbidden you should let the kernel
> return -EINVAL with a proper extack in tcf_gate_init(). Can you please
> clarify?
>
> thank you in advance!
> --
> davide
>
Br,
Po Liu
[v4,iproute2-next 1/2] iproute2-next:tc:action: add a gate control action
Introduce a ingress frame gate control flow action.
Tc gate action does the work like this:
Assume there is a gate allow specified ingress frames can pass at
specific time slot, and also drop at specific time slot. Tc filter
chooses the ingress frames, and tc gate action would specify what slot
does these frames can be passed to device and what time slot would be
dropped.
Tc gate action would provide an entry list to tell how much time gate
keep open and how much time gate keep state close. Gate action also
assign a start time to tell when the entry list start. Then driver would
repeat the gate entry list cyclically.
For the software simulation, gate action require the user assign a time
clock type.
Below is the setting example in user space. Tc filter a stream source ip
address is 192.168.0.20 and gate action own two time slots. One is last
200ms gate open let frame pass another is last 100ms gate close let
frames dropped.
# tc qdisc add dev eth0 ingress
# tc filter add dev eth0 parent : protocol ip \
flower src_ip 192.168.0.20 \
action gate index 2 clockid CLOCK_TAI \
sched-entry open 2 -1 -1 \
sched-entry close 1
# tc chain del dev eth0 ingress chain 0
"sched-entry" follow the name taprio style. Gate state is
"open"/"close". Follow the period nanosecond. Then next -1 is internal
priority value means which ingress queue should put to. "-1" means
wildcard. The last value optional specifies the maximum number of
MSDU octets that are permitted to pass the gate during the specified
time interval.
Below example shows filtering a stream with destination mac address is
10:00:80:00:00:00 and ip type is ICMP, follow the action gate. The gate
action would run with one close time slot which means always keep close.
The time cycle is total 2ns. The base-time would calculate by:
13570 + (N + 1) * cycletime
When the total value is the future time, it will be the start time.
The cycletime here would be 2ns for this case.
#tc filter add dev eth0 parent : protocol ip \
flower skip_hw ip_proto icmp dst_mac 10:00:80:00:00:00 \
action gate index 12 base-time 13570 \
sched-entry CLOSE 2 \
clockid CLOCK_TAI
Signed-off-by: Po Liu
---
These patches continue request for support iprout2 tc command input gate
action since kernel patch applied (a51c328df310 net: qos: introduce a
gate control flow action).
Continue the version 3.
Changes from v2:
Fix flexible input for a time slot - sched-entry suggested by Vladimir
Oltean and Vinicius Gomes:
- ipv and maxoctets in a sched-entry can be ignore input default to be
wildcard(values are -1).
Changes from v3:
- Fix json 'gate state' output update json format output: add array for
'sched-entry'
- Update input for 'sched-entry' parameters absense conditions
include/uapi/linux/pkt_cls.h| 1 +
include/uapi/linux/tc_act/tc_gate.h | 47 +++
tc/Makefile | 1 +
tc/m_gate.c | 556
4 files changed, 605 insertions(+)
create mode 100644 include/uapi/linux/tc_act/tc_gate.h
create mode 100644 tc/m_gate.c
diff --git a/include/uapi/linux/pkt_cls.h b/include/uapi/linux/pkt_cls.h
index 9f06d29c..fc672b23 100644
--- a/include/uapi/linux/pkt_cls.h
+++ b/include/uapi/linux/pkt_cls.h
@@ -134,6 +134,7 @@ enum tca_id {
TCA_ID_CTINFO,
TCA_ID_MPLS,
TCA_ID_CT,
+ TCA_ID_GATE,
/* other actions go here */
__TCA_ID_MAX = 255
};
diff --git a/include/uapi/linux/tc_act/tc_gate.h
b/include/uapi/linux/tc_act/tc_gate.h
new file mode 100644
index ..f214b3a6
--- /dev/null
+++ b/include/uapi/linux/tc_act/tc_gate.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/* Copyright 2020 NXP */
+
+#ifndef __LINUX_TC_GATE_H
+#define __LINUX_TC_GATE_H
+
+#include
+
+struct tc_gate {
+ tc_gen;
+};
+
+enum {
+ TCA_GATE_ENTRY_UNSPEC,
+ TCA_GATE_ENTRY_INDEX,
+ TCA_GATE_ENTRY_GATE,
+ TCA_GATE_ENTRY_INTERVAL,
+ TCA_GATE_ENTRY_IPV,
+ TCA_GATE_ENTRY_MAX_OCTETS,
+ __TCA_GATE_ENTRY_MAX,
+};
+#define TCA_GATE_ENTRY_MAX (__TCA_GATE_ENTRY_MAX - 1)
+
+enum {
+ TCA_GATE_ONE_ENTRY_UNSPEC,
+ TCA_GATE_ONE_ENTRY,
+ __TCA_GATE_ONE_ENTRY_MAX,
+};
+#define TCA_GATE_ONE_ENTRY_MAX (__TCA_GATE_ONE_ENTRY_MAX - 1)
+
+enum {
+ TCA_GATE_UNSPEC,
+ TCA_GATE_TM,
+ TCA_GATE_PARMS,
+ TCA_GATE_PAD,
+ TCA_GATE_PRIORITY,
+ TCA_GATE_ENTRY_LIST,
+ TCA_GATE_BASE_TIME,
+ TCA_GATE_CYCLE_TIME,
+ TCA_GATE_CYCLE_TIME_EXT,
+ TCA_GATE_FLAGS,
+ TCA_GATE_CLOCKID,
+ __TCA_GATE_MAX,
+};
+#define TCA_GATE_MAX (__TCA_GATE_MAX - 1)
+
+#endif
diff --git a/tc/Makefile b/tc/Makefile
index e31cbc12..79c9c1dd 100644
--- a/tc/Makefile
+++ b/tc/Makefile
@@ -54,6
[v4,iproute2-next 2/2] iproute2-next: add gate action man page
This patch is to add the man page for the tc gate action. Signed-off-by: Po Liu --- man/man8/tc-gate.8 | 123 + 1 file changed, 123 insertions(+) create mode 100644 man/man8/tc-gate.8 diff --git a/man/man8/tc-gate.8 b/man/man8/tc-gate.8 new file mode 100644 index ..0f48d7f3 --- /dev/null +++ b/man/man8/tc-gate.8 @@ -0,0 +1,123 @@ +.TH GATE 8 "12 Mar 2020" "iproute2" "Linux" +.SH NAME +gate \- Stream Gate Action +.SH SYNOPSIS +.B tc " ... " action gate +.ti +8 +.B [ base-time +BASETIME ] +.B [ clockid +CLOCKID ] +.ti +8 +.B sched-entry + [ ] +.ti +8 +.B sched-entry + [ ] +.ti +8 +.B sched-entry + [ ] +.ti +8 +.B .. +.ti +8 +.B sched-entry + [ ] + +.SH DESCRIPTION +GATE action allows specified ingress frames can be passed at +specific time slot, or be dropped at specific time slot. Tc filter +filters the ingress frames, then tc gate action would specify which time +slot and how many bytes these frames can be passed to device and +which time slot frames would be dropped. +Gate action also assign a base-time to tell when the entry list start. +Then gate action would start to repeat the gate entry list cyclically +at the start base-time. +For the software simulation, gate action requires the user assign reference +time clock type. + +.SH PARAMETERS + +.TP +base-time +.br +Specifies the instant in nanoseconds, defining the time when the schedule +starts. If 'base-time' is a time in the past, the schedule will start at + +base-time + (N * cycle-time) + +where N is the smallest integer so the resulting time is greater than +"now", and "cycle-time" is the sum of all the intervals of the entries +in the schedule. Without base-time specified, will default to be 0. + +.TP +clockid +.br +Specifies the clock to be used by qdisc's internal timer for measuring +time and scheduling events. Not valid if gate action is used for offloading +filter. +For example, tc filter command with +.B skip_sw +parameter. + +.TP +sched-entry +.br +There may multiple +.B sched-entry +parameters in a single schedule. Each one has the format: + +sched-entry [ ] + +.br + means gate states. 'open' keep gate open, 'close' keep gate close. +.br + means how much nano seconds for this time slot. +.br + means internal priority value. Present of the +internal receiving queue for this stream. "-1" means wildcard. + and can be omit default to be "-1" which both + value to be "-1" for this . +.br + means how many octets size for this time slot. Dropped +if overlimited. "-1" means wildcard. can be omit default to be +"-1" which value to be "-1" for this . +.br +Note that and are nothing meaning for gate state +is "close" in a "sched-entry". All frames are dropped when "sched-entry" with +"close" state. + +.SH EXAMPLES + +The following example shows tc filter frames source ip match to the +192.168.0.20 will keep the gate open for 200ms and limit the traffic to 8MB +in this sched-entry. Then keep the traffic gate to be close for 100ms. +Frames arrived at gate close state would be dropped. Then the cycle would +run the gate entries periodically. The schedule will start at instant 200.0s +using the reference CLOCK_TAI. The schedule is composed of two entries +each of 300ms duration. + +.EX +# tc qdisc add dev eth0 ingress +# tc filter add dev eth0 parent : protocol ip \\ + flower skip_hw src_ip 192.168.0.20 \\ + action gate index 2 clockid CLOCK_TAI \\ + base-time 2000 \\ + sched-entry open 2 -1 800 \\ + sched-entry close 1 + +.EE + +Following commands is an example to filter a stream source mac match to the +10:00:80:00:00:00 icmp frames will be dropped at any time with cycle 200ms. +With a default basetime 0 and clockid is CLOCK_TAI as default. + +.EX +# tc qdisc add dev eth0 ingress +# tc filter add dev eth0 parent ffff: protocol ip \\ + flower ip_proto icmp dst_mac 10:00:80:00:00:00 \\ + action gate index 12 sched-entry close 2 + +.EE + +.SH AUTHORS +Po Liu -- 2.17.1
RE: Re: [v3,iproute2 1/2] iproute2:tc:action: add a gate control action
Hi Stephen, > -Original Message- > From: Stephen Hemminger > Sent: 2020年5月5日 8:07 > To: Po Liu > Cc: da...@davemloft.net; linux-kernel@vger.kernel.org; > net...@vger.kernel.org; vinicius.go...@intel.com; v...@buslov.dev; > Claudiu Manoil ; Vladimir Oltean > ; Alexandru Marginean > ; michael.c...@broadcom.com; > vis...@chelsio.com; sae...@mellanox.com; l...@kernel.org; > j...@mellanox.com; ido...@mellanox.com; > alexandre.bell...@bootlin.com; unglinuxdri...@microchip.com; > k...@kernel.org; xiyou.wangc...@gmail.com; > simon.hor...@netronome.com; pa...@netfilter.org; > mo...@mellanox.com; m-kariche...@ti.com; > andre.gue...@linux.intel.com > Subject: Re: [v3,iproute2 1/2] iproute2:tc:action: add a gate control > action > > On Sun, 3 May 2020 14:32:50 +0800 > Po Liu wrote: > > > + print_string(PRINT_ANY, "gate state", "\tgate-state %-8s", > > NAK > Space in a json tag is not valid. > > Please run a dump command and feed it into JSON validation checker like > Python. I would test json format and upload new version patch set. Thanks! Br, Po Liu
RE: Re: [v3,iproute2 1/2] iproute2:tc:action: add a gate control action
Hi Stephen, David, > -Original Message- > From: Stephen Hemminger > Sent: 2020年5月5日 8:05 > To: Po Liu > Cc: da...@davemloft.net; linux-kernel@vger.kernel.org; > net...@vger.kernel.org; vinicius.go...@intel.com; v...@buslov.dev; > Claudiu Manoil ; Vladimir Oltean > ; Alexandru Marginean > ; michael.c...@broadcom.com; > vis...@chelsio.com; sae...@mellanox.com; l...@kernel.org; > j...@mellanox.com; ido...@mellanox.com; > alexandre.bell...@bootlin.com; unglinuxdri...@microchip.com; > k...@kernel.org; xiyou.wangc...@gmail.com; > simon.hor...@netronome.com; pa...@netfilter.org; > mo...@mellanox.com; m-kariche...@ti.com; > andre.gue...@linux.intel.com > Subject: [EXT] Re: [v3,iproute2 1/2] iproute2:tc:action: add a gate control > action > > On Sun, 3 May 2020 14:32:50 +0800 > Po Liu wrote: > > > Introduce a ingress frame gate control flow action. > > Tc gate action does the work like this: > > Assume there is a gate allow specified ingress frames can pass at > > specific time slot, and also drop at specific time slot. Tc filter > > chooses the ingress frames, and tc gate action would specify what slot > > does these frames can be passed to device and what time slot would be > > dropped. > > Tc gate action would provide an entry list to tell how much time gate > > keep open and how much time gate keep state close. Gate action also > > assign a start time to tell when the entry list start. Then driver > > would repeat the gate entry list cyclically. > > For the software simulation, gate action require the user assign a > > time clock type. > > > > Below is the setting example in user space. Tc filter a stream source > > ip address is 192.168.0.20 and gate action own two time slots. One is > > last 200ms gate open let frame pass another is last 100ms gate close > > let frames dropped. > > > > # tc qdisc add dev eth0 ingress > > # tc filter add dev eth0 parent : protocol ip \ > > > > flower src_ip 192.168.0.20 \ > > action gate index 2 clockid CLOCK_TAI \ > > sched-entry open 2 -1 -1 \ > > sched-entry close 1 > > > > # tc chain del dev eth0 ingress chain 0 > > > > "sched-entry" follow the name taprio style. Gate state is > > "open"/"close". Follow the period nanosecond. Then next -1 is internal > > priority value means which ingress queue should put to. "-1" means > > wildcard. The last value optional specifies the maximum number of > MSDU > > octets that are permitted to pass the gate during the specified time > > interval. > > > > Below example shows filtering a stream with destination mac address is > > 10:00:80:00:00:00 and ip type is ICMP, follow the action gate. The > > gate action would run with one close time slot which means always keep > close. > > The time cycle is total 2ns. The base-time would calculate by: > > > > 13570 + (N + 1) * cycletime > > > > When the total value is the future time, it will be the start time. > > The cycletime here would be 2ns for this case. > > > > #tc filter add dev eth0 parent : protocol ip \ > >flower skip_hw ip_proto icmp dst_mac 10:00:80:00:00:00 \ > >action gate index 12 base-time 13570 \ > >sched-entry CLOSE 2 \ > >clockid CLOCK_TAI > > > > Signed-off-by: Po Liu > > These changes are specific to net-next should be assigned to iproute2-next. > Will change delegation. I would push request specific name with iproute2-next for version 4. Thanks! Thanks a lot! Br, Po Liu
[v3,iproute2 2/2] iproute2: add gate action man page
This patch is to add the man page for the tc gate action. Signed-off-by: Po Liu --- man/man8/tc-gate.8 | 123 + 1 file changed, 123 insertions(+) create mode 100644 man/man8/tc-gate.8 diff --git a/man/man8/tc-gate.8 b/man/man8/tc-gate.8 new file mode 100644 index ..0f48d7f3 --- /dev/null +++ b/man/man8/tc-gate.8 @@ -0,0 +1,123 @@ +.TH GATE 8 "12 Mar 2020" "iproute2" "Linux" +.SH NAME +gate \- Stream Gate Action +.SH SYNOPSIS +.B tc " ... " action gate +.ti +8 +.B [ base-time +BASETIME ] +.B [ clockid +CLOCKID ] +.ti +8 +.B sched-entry + [ ] +.ti +8 +.B sched-entry + [ ] +.ti +8 +.B sched-entry + [ ] +.ti +8 +.B .. +.ti +8 +.B sched-entry + [ ] + +.SH DESCRIPTION +GATE action allows specified ingress frames can be passed at +specific time slot, or be dropped at specific time slot. Tc filter +filters the ingress frames, then tc gate action would specify which time +slot and how many bytes these frames can be passed to device and +which time slot frames would be dropped. +Gate action also assign a base-time to tell when the entry list start. +Then gate action would start to repeat the gate entry list cyclically +at the start base-time. +For the software simulation, gate action requires the user assign reference +time clock type. + +.SH PARAMETERS + +.TP +base-time +.br +Specifies the instant in nanoseconds, defining the time when the schedule +starts. If 'base-time' is a time in the past, the schedule will start at + +base-time + (N * cycle-time) + +where N is the smallest integer so the resulting time is greater than +"now", and "cycle-time" is the sum of all the intervals of the entries +in the schedule. Without base-time specified, will default to be 0. + +.TP +clockid +.br +Specifies the clock to be used by qdisc's internal timer for measuring +time and scheduling events. Not valid if gate action is used for offloading +filter. +For example, tc filter command with +.B skip_sw +parameter. + +.TP +sched-entry +.br +There may multiple +.B sched-entry +parameters in a single schedule. Each one has the format: + +sched-entry [ ] + +.br + means gate states. 'open' keep gate open, 'close' keep gate close. +.br + means how much nano seconds for this time slot. +.br + means internal priority value. Present of the +internal receiving queue for this stream. "-1" means wildcard. + and can be omit default to be "-1" which both + value to be "-1" for this . +.br + means how many octets size for this time slot. Dropped +if overlimited. "-1" means wildcard. can be omit default to be +"-1" which value to be "-1" for this . +.br +Note that and are nothing meaning for gate state +is "close" in a "sched-entry". All frames are dropped when "sched-entry" with +"close" state. + +.SH EXAMPLES + +The following example shows tc filter frames source ip match to the +192.168.0.20 will keep the gate open for 200ms and limit the traffic to 8MB +in this sched-entry. Then keep the traffic gate to be close for 100ms. +Frames arrived at gate close state would be dropped. Then the cycle would +run the gate entries periodically. The schedule will start at instant 200.0s +using the reference CLOCK_TAI. The schedule is composed of two entries +each of 300ms duration. + +.EX +# tc qdisc add dev eth0 ingress +# tc filter add dev eth0 parent : protocol ip \\ + flower skip_hw src_ip 192.168.0.20 \\ + action gate index 2 clockid CLOCK_TAI \\ + base-time 2000 \\ + sched-entry open 2 -1 800 \\ + sched-entry close 1 + +.EE + +Following commands is an example to filter a stream source mac match to the +10:00:80:00:00:00 icmp frames will be dropped at any time with cycle 200ms. +With a default basetime 0 and clockid is CLOCK_TAI as default. + +.EX +# tc qdisc add dev eth0 ingress +# tc filter add dev eth0 parent ffff: protocol ip \\ + flower ip_proto icmp dst_mac 10:00:80:00:00:00 \\ + action gate index 12 sched-entry close 2 + +.EE + +.SH AUTHORS +Po Liu -- 2.17.1
[v3,iproute2 1/2] iproute2:tc:action: add a gate control action
Introduce a ingress frame gate control flow action.
Tc gate action does the work like this:
Assume there is a gate allow specified ingress frames can pass at
specific time slot, and also drop at specific time slot. Tc filter
chooses the ingress frames, and tc gate action would specify what slot
does these frames can be passed to device and what time slot would be
dropped.
Tc gate action would provide an entry list to tell how much time gate
keep open and how much time gate keep state close. Gate action also
assign a start time to tell when the entry list start. Then driver would
repeat the gate entry list cyclically.
For the software simulation, gate action require the user assign a time
clock type.
Below is the setting example in user space. Tc filter a stream source ip
address is 192.168.0.20 and gate action own two time slots. One is last
200ms gate open let frame pass another is last 100ms gate close let
frames dropped.
# tc qdisc add dev eth0 ingress
# tc filter add dev eth0 parent : protocol ip \
flower src_ip 192.168.0.20 \
action gate index 2 clockid CLOCK_TAI \
sched-entry open 2 -1 -1 \
sched-entry close 1
# tc chain del dev eth0 ingress chain 0
"sched-entry" follow the name taprio style. Gate state is
"open"/"close". Follow the period nanosecond. Then next -1 is internal
priority value means which ingress queue should put to. "-1" means
wildcard. The last value optional specifies the maximum number of
MSDU octets that are permitted to pass the gate during the specified
time interval.
Below example shows filtering a stream with destination mac address is
10:00:80:00:00:00 and ip type is ICMP, follow the action gate. The gate
action would run with one close time slot which means always keep close.
The time cycle is total 2ns. The base-time would calculate by:
13570 + (N + 1) * cycletime
When the total value is the future time, it will be the start time.
The cycletime here would be 2ns for this case.
#tc filter add dev eth0 parent : protocol ip \
flower skip_hw ip_proto icmp dst_mac 10:00:80:00:00:00 \
action gate index 12 base-time 13570 \
sched-entry CLOSE 2 \
clockid CLOCK_TAI
Signed-off-by: Po Liu
---
These patches continue request for support iprout2 tc command input gate
action since kernel patch applied (a51c328df310 net: qos: introduce a
gate control flow action).
Continue the version 3.
Changes from v2:
Fix flexible input for a time slot - sched-entry suggested by Vladimir
Oltean and Vinicius Gomes:
- ipv and maxoctets in a sched-entry can be ignore input default to be
wildcard(values are -1).
include/uapi/linux/pkt_cls.h| 1 +
include/uapi/linux/tc_act/tc_gate.h | 47 +++
tc/Makefile | 1 +
tc/m_gate.c | 533
4 files changed, 582 insertions(+)
create mode 100644 include/uapi/linux/tc_act/tc_gate.h
create mode 100644 tc/m_gate.c
diff --git a/include/uapi/linux/pkt_cls.h b/include/uapi/linux/pkt_cls.h
index 9f06d29c..fc672b23 100644
--- a/include/uapi/linux/pkt_cls.h
+++ b/include/uapi/linux/pkt_cls.h
@@ -134,6 +134,7 @@ enum tca_id {
TCA_ID_CTINFO,
TCA_ID_MPLS,
TCA_ID_CT,
+ TCA_ID_GATE,
/* other actions go here */
__TCA_ID_MAX = 255
};
diff --git a/include/uapi/linux/tc_act/tc_gate.h
b/include/uapi/linux/tc_act/tc_gate.h
new file mode 100644
index ..f214b3a6
--- /dev/null
+++ b/include/uapi/linux/tc_act/tc_gate.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/* Copyright 2020 NXP */
+
+#ifndef __LINUX_TC_GATE_H
+#define __LINUX_TC_GATE_H
+
+#include
+
+struct tc_gate {
+ tc_gen;
+};
+
+enum {
+ TCA_GATE_ENTRY_UNSPEC,
+ TCA_GATE_ENTRY_INDEX,
+ TCA_GATE_ENTRY_GATE,
+ TCA_GATE_ENTRY_INTERVAL,
+ TCA_GATE_ENTRY_IPV,
+ TCA_GATE_ENTRY_MAX_OCTETS,
+ __TCA_GATE_ENTRY_MAX,
+};
+#define TCA_GATE_ENTRY_MAX (__TCA_GATE_ENTRY_MAX - 1)
+
+enum {
+ TCA_GATE_ONE_ENTRY_UNSPEC,
+ TCA_GATE_ONE_ENTRY,
+ __TCA_GATE_ONE_ENTRY_MAX,
+};
+#define TCA_GATE_ONE_ENTRY_MAX (__TCA_GATE_ONE_ENTRY_MAX - 1)
+
+enum {
+ TCA_GATE_UNSPEC,
+ TCA_GATE_TM,
+ TCA_GATE_PARMS,
+ TCA_GATE_PAD,
+ TCA_GATE_PRIORITY,
+ TCA_GATE_ENTRY_LIST,
+ TCA_GATE_BASE_TIME,
+ TCA_GATE_CYCLE_TIME,
+ TCA_GATE_CYCLE_TIME_EXT,
+ TCA_GATE_FLAGS,
+ TCA_GATE_CLOCKID,
+ __TCA_GATE_MAX,
+};
+#define TCA_GATE_MAX (__TCA_GATE_MAX - 1)
+
+#endif
diff --git a/tc/Makefile b/tc/Makefile
index e31cbc12..79c9c1dd 100644
--- a/tc/Makefile
+++ b/tc/Makefile
@@ -54,6 +54,7 @@ TCMODULES += m_bpf.o
TCMODULES += m_tunnel_key.o
TCMODULES += m_sample.o
TCMODULES += m_ct.o
+TCMODULES += m_gate.o
TCMODULES += p_ip.o
TCMODULES += p_ip6.
RE: Re: [v5,net-next 0/4] Introduce a flow gate control action and apply IEEE
Hi David, Stephen, > -Original Message- > From: David Miller > Sent: 2020年5月2日 7:09 > To: Po Liu > Cc: linux-kernel@vger.kernel.org; net...@vger.kernel.org; > vinicius.go...@intel.com; v...@buslov.dev; Claudiu Manoil > ; Vladimir Oltean ; > Alexandru Marginean ; > michael.c...@broadcom.com; vis...@chelsio.com; > sae...@mellanox.com; l...@kernel.org; j...@mellanox.com; > ido...@mellanox.com; alexandre.bell...@bootlin.com; > unglinuxdri...@microchip.com; k...@kernel.org; j...@mojatatu.com; > xiyou.wangc...@gmail.com; simon.hor...@netronome.com; > pa...@netfilter.org; mo...@mellanox.com; m-kariche...@ti.com; > andre.gue...@linux.intel.com; step...@networkplumber.org > Subject: Re: [v5,net-next 0/4] Introduce a flow gate control action > and apply IEEE > > From: Po Liu > Date: Fri, 1 May 2020 08:53:14 +0800 > > ... > > These patches add stream gate action policing in IEEE802.1Qci > > (Per-Stream Filtering and Policing) software support and hardware > > offload support in tc flower, and implement the stream identify, > > stream filtering and stream gate filtering action in the NXP ENETC > ethernet driver. > ... > > Series applied, thanks. Thanks a lot. I would send the iproute2 patches on these email thread. Br, Po Liu
[v5,net-next 3/4] net: enetc: add hw tc hw offload features for PSPF capability
This patch is to let ethtool enable/disable the tc flower offload
features. Hardware ENETC has the feature of PSFP which is for per-stream
policing. When enable the tc hw offloading feature, driver would enable
the IEEE 802.1Qci feature. It is only set the register enable bit for
this feature not enable for any entry of per stream filtering and stream
gate or stream identify but get how much capabilities for each feature.
Signed-off-by: Po Liu
---
drivers/net/ethernet/freescale/enetc/enetc.c | 23 +
drivers/net/ethernet/freescale/enetc/enetc.h | 48 +++
.../net/ethernet/freescale/enetc/enetc_hw.h | 17 +++
.../net/ethernet/freescale/enetc/enetc_pf.c | 8
4 files changed, 96 insertions(+)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c
b/drivers/net/ethernet/freescale/enetc/enetc.c
index ccf2611f4a20..04aac7cbb506 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc.c
@@ -756,6 +756,9 @@ void enetc_get_si_caps(struct enetc_si *si)
if (val & ENETC_SIPCAPR0_QBV)
si->hw_features |= ENETC_SI_F_QBV;
+
+ if (val & ENETC_SIPCAPR0_PSFP)
+ si->hw_features |= ENETC_SI_F_PSFP;
}
static int enetc_dma_alloc_bdr(struct enetc_bdr *r, size_t bd_size)
@@ -1567,6 +1570,23 @@ static int enetc_set_rss(struct net_device *ndev, int en)
return 0;
}
+static int enetc_set_psfp(struct net_device *ndev, int en)
+{
+ struct enetc_ndev_priv *priv = netdev_priv(ndev);
+
+ if (en) {
+ priv->active_offloads |= ENETC_F_QCI;
+ enetc_get_max_cap(priv);
+ enetc_psfp_enable(>si->hw);
+ } else {
+ priv->active_offloads &= ~ENETC_F_QCI;
+ memset(>psfp_cap, 0, sizeof(struct psfp_cap));
+ enetc_psfp_disable(>si->hw);
+ }
+
+ return 0;
+}
+
int enetc_set_features(struct net_device *ndev,
netdev_features_t features)
{
@@ -1575,6 +1595,9 @@ int enetc_set_features(struct net_device *ndev,
if (changed & NETIF_F_RXHASH)
enetc_set_rss(ndev, !!(features & NETIF_F_RXHASH));
+ if (changed & NETIF_F_HW_TC)
+ enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
+
return 0;
}
diff --git a/drivers/net/ethernet/freescale/enetc/enetc.h
b/drivers/net/ethernet/freescale/enetc/enetc.h
index 56c43f35b633..2cfe877c3778 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc.h
@@ -151,6 +151,7 @@ enum enetc_errata {
};
#define ENETC_SI_F_QBV BIT(0)
+#define ENETC_SI_F_PSFP BIT(1)
/* PCI IEP device data */
struct enetc_si {
@@ -203,12 +204,20 @@ struct enetc_cls_rule {
};
#define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */
+struct psfp_cap {
+ u32 max_streamid;
+ u32 max_psfp_filter;
+ u32 max_psfp_gate;
+ u32 max_psfp_gatelist;
+ u32 max_psfp_meter;
+};
/* TODO: more hardware offloads */
enum enetc_active_offloads {
ENETC_F_RX_TSTAMP = BIT(0),
ENETC_F_TX_TSTAMP = BIT(1),
ENETC_F_QBV = BIT(2),
+ ENETC_F_QCI = BIT(3),
};
struct enetc_ndev_priv {
@@ -231,6 +240,8 @@ struct enetc_ndev_priv {
struct enetc_cls_rule *cls_rules;
+ struct psfp_cap psfp_cap;
+
struct device_node *phy_node;
phy_interface_t if_mode;
};
@@ -289,9 +300,46 @@ int enetc_setup_tc_taprio(struct net_device *ndev, void
*type_data);
void enetc_sched_speed_set(struct net_device *ndev);
int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data);
int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data);
+
+static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv)
+{
+ u32 reg;
+
+ reg = enetc_port_rd(>si->hw, ENETC_PSIDCAPR);
+ priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK;
+ /* Port stream filter capability */
+ reg = enetc_port_rd(>si->hw, ENETC_PSFCAPR);
+ priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK;
+ /* Port stream gate capability */
+ reg = enetc_port_rd(>si->hw, ENETC_PSGCAPR);
+ priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK);
+ priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16;
+ /* Port flow meter capability */
+ reg = enetc_port_rd(>si->hw, ENETC_PFMCAPR);
+ priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK;
+}
+
+static inline void enetc_psfp_enable(struct enetc_hw *hw)
+{
+ enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) |
+ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS |
+ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC);
+}
+
+static inline void enetc_psfp_disable(struct enetc_hw *hw)
+{
+
[v5,net-next 0/4] Introduce a flow gate control action and apply IEEE
low hardware offloading. The 0003 patch adds support control the on/off for the tc flower offloading by ethtool. The 0004 patch implement the stream identify and stream filtering and stream gate filtering action in the NXP ENETC ethernet driver. Tc filter command provide filtering keys with MAC address and VLAN id. These keys would be set to stream identify instance entry. Stream gate instance entry would refer the gate action parameters. Stream filter instance entry would refer the stream gate index and assign a stream handle value matches to the stream identify instance. Po Liu (4): net: qos: introduce a gate control flow action net: schedule: add action gate offloading net: enetc: add hw tc hw offload features for PSPF capability net: enetc: add tc flower psfp offload driver drivers/net/ethernet/freescale/enetc/enetc.c | 34 +- drivers/net/ethernet/freescale/enetc/enetc.h | 86 ++ .../net/ethernet/freescale/enetc/enetc_hw.h | 159 +++ .../net/ethernet/freescale/enetc/enetc_pf.c |6 + .../net/ethernet/freescale/enetc/enetc_qos.c | 1098 + include/net/flow_offload.h| 10 + include/net/tc_act/tc_gate.h | 146 +++ include/uapi/linux/pkt_cls.h |1 + include/uapi/linux/tc_act/tc_gate.h | 47 + net/sched/Kconfig | 12 + net/sched/Makefile|1 + net/sched/act_gate.c | 636 ++ net/sched/cls_api.c | 33 + 13 files changed, 2268 insertions(+), 1 deletion(-) create mode 100644 include/net/tc_act/tc_gate.h create mode 100644 include/uapi/linux/tc_act/tc_gate.h create mode 100644 net/sched/act_gate.c -- 2.17.1
[v5,net-next 1/4] net: qos: introduce a gate control flow action
Introduce a ingress frame gate control flow action.
Tc gate action does the work like this:
Assume there is a gate allow specified ingress frames can be passed at
specific time slot, and be dropped at specific time slot. Tc filter
chooses the ingress frames, and tc gate action would specify what slot
does these frames can be passed to device and what time slot would be
dropped.
Tc gate action would provide an entry list to tell how much time gate
keep open and how much time gate keep state close. Gate action also
assign a start time to tell when the entry list start. Then driver would
repeat the gate entry list cyclically.
For the software simulation, gate action requires the user assign a time
clock type.
Below is the setting example in user space. Tc filter a stream source ip
address is 192.168.0.20 and gate action own two time slots. One is last
200ms gate open let frame pass another is last 100ms gate close let
frames dropped. When the ingress frames have reach total frames over
800 bytes, the excessive frames will be dropped in that 2ns
time slot.
> tc qdisc add dev eth0 ingress
> tc filter add dev eth0 parent : protocol ip \
flower src_ip 192.168.0.20 \
action gate index 2 clockid CLOCK_TAI \
sched-entry open 2 -1 800 \
sched-entry close 1 -1 -1
> tc chain del dev eth0 ingress chain 0
"sched-entry" follow the name taprio style. Gate state is
"open"/"close". Follow with period nanosecond. Then next item is internal
priority value means which ingress queue should put. "-1" means
wildcard. The last value optional specifies the maximum number of
MSDU octets that are permitted to pass the gate during the specified
time interval.
Base-time is not set will be 0 as default, as result start time would
be ((N + 1) * cycletime) which is the minimal of future time.
Below example shows filtering a stream with destination mac address is
10:00:80:00:00:00 and ip type is ICMP, follow the action gate. The gate
action would run with one close time slot which means always keep close.
The time cycle is total 2ns. The base-time would calculate by:
13570 + (N + 1) * cycletime
When the total value is the future time, it will be the start time.
The cycletime here would be 2ns for this case.
> tc filter add dev eth0 parent : protocol ip \
flower skip_hw ip_proto icmp dst_mac 10:00:80:00:00:00 \
action gate index 12 base-time 13570 \
sched-entry close 2 -1 -1 \
clockid CLOCK_TAI
Signed-off-by: Po Liu
---
include/net/tc_act/tc_gate.h| 47 ++
include/uapi/linux/pkt_cls.h| 1 +
include/uapi/linux/tc_act/tc_gate.h | 47 ++
net/sched/Kconfig | 12 +
net/sched/Makefile | 1 +
net/sched/act_gate.c| 636
6 files changed, 744 insertions(+)
create mode 100644 include/net/tc_act/tc_gate.h
create mode 100644 include/uapi/linux/tc_act/tc_gate.h
create mode 100644 net/sched/act_gate.c
diff --git a/include/net/tc_act/tc_gate.h b/include/net/tc_act/tc_gate.h
new file mode 100644
index ..330ad8b02495
--- /dev/null
+++ b/include/net/tc_act/tc_gate.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright 2020 NXP */
+
+#ifndef __NET_TC_GATE_H
+#define __NET_TC_GATE_H
+
+#include
+#include
+
+struct tcfg_gate_entry {
+ int index;
+ u8 gate_state;
+ u32 interval;
+ s32 ipv;
+ s32 maxoctets;
+ struct list_headlist;
+};
+
+struct tcf_gate_params {
+ s32 tcfg_priority;
+ u64 tcfg_basetime;
+ u64 tcfg_cycletime;
+ u64 tcfg_cycletime_ext;
+ u32 tcfg_flags;
+ s32 tcfg_clockid;
+ size_t num_entries;
+ struct list_headentries;
+};
+
+#define GATE_ACT_GATE_OPEN BIT(0)
+#define GATE_ACT_PENDING BIT(1)
+
+struct tcf_gate {
+ struct tc_actioncommon;
+ struct tcf_gate_params param;
+ u8 current_gate_status;
+ ktime_t current_close_time;
+ u32 current_entry_octets;
+ s32 current_max_octets;
+ struct tcfg_gate_entry *next_entry;
+ struct hrtimer hitimer;
+ enum tk_offsets tk_offset;
+};
+
+#define to_gate(a) ((struct tcf_gate *)a)
+
+#endif
diff --git a/include/uapi/linux/pkt_cls.h b/include/uapi/linux/pkt_cls.h
index 9f06d29cab70..fc672b232437 100644
--- a/include/uapi/linux/pkt_cls.h
+++ b/include/uapi/linux/pkt_cls.h
@@ -134,6 +134,7 @@ enum tca_id {
TCA_ID_CTINFO,
[v5,net-next 2/4] net: schedule: add action gate offloading
Add the gate action to the flow action entry. Add the gate parameters to
the tc_setup_flow_action() queueing to the entries of flow_action_entry
array provide to the driver.
Signed-off-by: Po Liu
---
include/net/flow_offload.h | 10
include/net/tc_act/tc_gate.h | 99
net/sched/cls_api.c | 33
3 files changed, 142 insertions(+)
diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
index 3619c6acf60f..94a30fe02e6d 100644
--- a/include/net/flow_offload.h
+++ b/include/net/flow_offload.h
@@ -147,6 +147,7 @@ enum flow_action_id {
FLOW_ACTION_MPLS_PUSH,
FLOW_ACTION_MPLS_POP,
FLOW_ACTION_MPLS_MANGLE,
+ FLOW_ACTION_GATE,
NUM_FLOW_ACTIONS,
};
@@ -255,6 +256,15 @@ struct flow_action_entry {
u8 bos;
u8 ttl;
} mpls_mangle;
+ struct {
+ u32 index;
+ s32 prio;
+ u64 basetime;
+ u64 cycletime;
+ u64 cycletimeext;
+ u32 num_entries;
+ struct action_gate_entry *entries;
+ } gate;
};
struct flow_action_cookie *cookie; /* user defined action cookie */
};
diff --git a/include/net/tc_act/tc_gate.h b/include/net/tc_act/tc_gate.h
index 330ad8b02495..8bc6be81a7ad 100644
--- a/include/net/tc_act/tc_gate.h
+++ b/include/net/tc_act/tc_gate.h
@@ -7,6 +7,13 @@
#include
#include
+struct action_gate_entry {
+ u8 gate_state;
+ u32 interval;
+ s32 ipv;
+ s32 maxoctets;
+};
+
struct tcfg_gate_entry {
int index;
u8 gate_state;
@@ -44,4 +51,96 @@ struct tcf_gate {
#define to_gate(a) ((struct tcf_gate *)a)
+static inline bool is_tcf_gate(const struct tc_action *a)
+{
+#ifdef CONFIG_NET_CLS_ACT
+ if (a->ops && a->ops->id == TCA_ID_GATE)
+ return true;
+#endif
+ return false;
+}
+
+static inline u32 tcf_gate_index(const struct tc_action *a)
+{
+ return a->tcfa_index;
+}
+
+static inline s32 tcf_gate_prio(const struct tc_action *a)
+{
+ s32 tcfg_prio;
+
+ tcfg_prio = to_gate(a)->param.tcfg_priority;
+
+ return tcfg_prio;
+}
+
+static inline u64 tcf_gate_basetime(const struct tc_action *a)
+{
+ u64 tcfg_basetime;
+
+ tcfg_basetime = to_gate(a)->param.tcfg_basetime;
+
+ return tcfg_basetime;
+}
+
+static inline u64 tcf_gate_cycletime(const struct tc_action *a)
+{
+ u64 tcfg_cycletime;
+
+ tcfg_cycletime = to_gate(a)->param.tcfg_cycletime;
+
+ return tcfg_cycletime;
+}
+
+static inline u64 tcf_gate_cycletimeext(const struct tc_action *a)
+{
+ u64 tcfg_cycletimeext;
+
+ tcfg_cycletimeext = to_gate(a)->param.tcfg_cycletime_ext;
+
+ return tcfg_cycletimeext;
+}
+
+static inline u32 tcf_gate_num_entries(const struct tc_action *a)
+{
+ u32 num_entries;
+
+ num_entries = to_gate(a)->param.num_entries;
+
+ return num_entries;
+}
+
+static inline struct action_gate_entry
+ *tcf_gate_get_list(const struct tc_action *a)
+{
+ struct action_gate_entry *oe;
+ struct tcf_gate_params *p;
+ struct tcfg_gate_entry *entry;
+ u32 num_entries;
+ int i = 0;
+
+ p = _gate(a)->param;
+ num_entries = p->num_entries;
+
+ list_for_each_entry(entry, >entries, list)
+ i++;
+
+ if (i != num_entries)
+ return NULL;
+
+ oe = kcalloc(num_entries, sizeof(*oe), GFP_ATOMIC);
+ if (!oe)
+ return NULL;
+
+ i = 0;
+ list_for_each_entry(entry, >entries, list) {
+ oe[i].gate_state = entry->gate_state;
+ oe[i].interval = entry->interval;
+ oe[i].ipv = entry->ipv;
+ oe[i].maxoctets = entry->maxoctets;
+ i++;
+ }
+
+ return oe;
+}
#endif
diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c
index 11b683c45c28..7e85c91d0752 100644
--- a/net/sched/cls_api.c
+++ b/net/sched/cls_api.c
@@ -39,6 +39,7 @@
#include
#include
#include
+#include
#include
extern const struct nla_policy rtm_tca_policy[TCA_MAX + 1];
@@ -3526,6 +3527,27 @@ static void tcf_sample_get_group(struct
flow_action_entry *entry,
#endif
}
+static void tcf_gate_entry_destructor(void *priv)
+{
+ struct action_gate_entry *oe = priv;
+
+ kfree(oe);
+}
+
+static int tcf_gate_get_entries(struct flow_action_entry *entry,
+ const struct tc_action *act)
+{
+ entry->gate.entries = tcf_gate_get_list(act);
+
+ if (!entry-
[v5,net-next 4/4] net: enetc: add tc flower psfp offload driver
This patch is to add tc flower offload for the enetc IEEE 802.1Qci(PSFP)
function. There are four main feature parts to implement the flow
policing and filtering for ingress flow with IEEE 802.1Qci features.
They are stream identify(this is defined in the P802.1cb exactly but
needed for 802.1Qci), stream filtering, stream gate and flow metering.
Each function block includes many entries by index to assign parameters.
So for one frame would be filtered by stream identify first, then
flow into stream filter block by the same handle between stream identify
and stream filtering. Then flow into stream gate control which assigned
by the stream filtering entry. And then policing by the gate and limited
by the max sdu in the filter block(optional). At last, policing by the
flow metering block, index choosing at the fitering block.
So you can see that each entry of block may link to many upper entries
since they can be assigned same index means more streams want to share
the same feature in the stream filtering or stream gate or flow
metering.
To implement such features, each stream filtered by source/destination
mac address, some stream maybe also plus the vlan id value would be
treated as one flow chain. This would be identified by the chain_index
which already in the tc filter concept. Driver would maintain this chain
and also with gate modules. The stream filter entry create by the gate
index and flow meter(optional) entry id and also one priority value.
Offloading only transfer the gate action and flow filtering parameters.
Driver would create (or search same gate id and flow meter id and
priority) one stream filter entry to set to the hardware. So stream
filtering do not need transfer by the action offloading.
This architecture is same with tc filter and actions relationship. tc
filter maintain the list for each flow feature by keys. And actions
maintain by the action list.
Below showing a example commands by tc:
> tc qdisc add dev eth0 ingress
> ip link set eth0 address 10:00:80:00:00:00
> tc filter add dev eth0 parent : protocol ip chain 11 \
flower skip_sw dst_mac 10:00:80:00:00:00 \
action gate index 10 \
sched-entry open 2 1 800 \
sched-entry close 1 -1 -1
Command means to set the dst_mac 10:00:80:00:00:00 to index 11 of stream
identify module. Then setting the gate index 10 of stream gate module.
Keep the gate open for 200ms and limit the traffic volume to 8MB in this
sched-entry. Then direct the frames to the ingress queue 1.
Signed-off-by: Po Liu
---
drivers/net/ethernet/freescale/enetc/enetc.c | 25 +-
drivers/net/ethernet/freescale/enetc/enetc.h | 46 +-
.../net/ethernet/freescale/enetc/enetc_hw.h | 142 +++
.../net/ethernet/freescale/enetc/enetc_pf.c |4 +-
.../net/ethernet/freescale/enetc/enetc_qos.c | 1098 +
5 files changed, 1300 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c
b/drivers/net/ethernet/freescale/enetc/enetc.c
index 04aac7cbb506..298c55786fd9 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc.c
@@ -1521,6 +1521,8 @@ int enetc_setup_tc(struct net_device *ndev, enum
tc_setup_type type,
return enetc_setup_tc_cbs(ndev, type_data);
case TC_SETUP_QDISC_ETF:
return enetc_setup_tc_txtime(ndev, type_data);
+ case TC_SETUP_BLOCK:
+ return enetc_setup_tc_psfp(ndev, type_data);
default:
return -EOPNOTSUPP;
}
@@ -1573,17 +1575,23 @@ static int enetc_set_rss(struct net_device *ndev, int
en)
static int enetc_set_psfp(struct net_device *ndev, int en)
{
struct enetc_ndev_priv *priv = netdev_priv(ndev);
+ int err;
if (en) {
+ err = enetc_psfp_enable(priv);
+ if (err)
+ return err;
+
priv->active_offloads |= ENETC_F_QCI;
- enetc_get_max_cap(priv);
- enetc_psfp_enable(>si->hw);
- } else {
- priv->active_offloads &= ~ENETC_F_QCI;
- memset(>psfp_cap, 0, sizeof(struct psfp_cap));
- enetc_psfp_disable(>si->hw);
+ return 0;
}
+ err = enetc_psfp_disable(priv);
+ if (err)
+ return err;
+
+ priv->active_offloads &= ~ENETC_F_QCI;
+
return 0;
}
@@ -1591,14 +1599,15 @@ int enetc_set_features(struct net_device *ndev,
netdev_features_t features)
{
netdev_features_t changed = ndev->features ^ features;
+ int err = 0;
if (changed & NETIF_F_RXHASH)
enetc_set_rss(ndev, !!(features & NETIF_F_RXHASH));
if (changed & NETIF_F_HW_TC)
- enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
+ err = enetc_set_psfp(ndev, !!(features & NETIF
RE: Re: [v4,net-next 2/4] net: schedule: add action gate offloading
Hi Vlad,
> -Original Message-
> From: Vlad Buslov
> Sent: 2020年4月30日 1:41
> To: Po Liu
> Cc: da...@davemloft.net; linux-kernel@vger.kernel.org;
> net...@vger.kernel.org; vinicius.go...@intel.com; Claudiu Manoil
> ; Vladimir Oltean ;
> Alexandru Marginean ;
> michael.c...@broadcom.com; vis...@chelsio.com;
> sae...@mellanox.com; l...@kernel.org; j...@mellanox.com;
> ido...@mellanox.com; alexandre.bell...@bootlin.com;
> unglinuxdri...@microchip.com; k...@kernel.org; j...@mojatatu.com;
> xiyou.wangc...@gmail.com; simon.hor...@netronome.com;
> pa...@netfilter.org; mo...@mellanox.com; m-kariche...@ti.com;
> andre.gue...@linux.intel.com; step...@networkplumber.org
> Subject: Re: [v4,net-next 2/4] net: schedule: add action gate
> offloading
>
>
> On Tue 28 Apr 2020 at 06:34, Po Liu wrote:
> > Add the gate action to the flow action entry. Add the gate parameters
> > to the tc_setup_flow_action() queueing to the entries of
> > flow_action_entry array provide to the driver.
> >
> > Signed-off-by: Po Liu
> > ---
> > include/net/flow_offload.h | 10
> > include/net/tc_act/tc_gate.h | 113
> +++
> > net/sched/cls_api.c | 33 ++
> > 3 files changed, 156 insertions(+)
> >
> > diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
> > index 3619c6acf60f..94a30fe02e6d 100644
> > --- a/include/net/flow_offload.h
> > +++ b/include/net/flow_offload.h
> > @@ -147,6 +147,7 @@ enum flow_action_id {
> > FLOW_ACTION_MPLS_PUSH,
> > FLOW_ACTION_MPLS_POP,
> > FLOW_ACTION_MPLS_MANGLE,
> > + FLOW_ACTION_GATE,
> > NUM_FLOW_ACTIONS,
> > };
> >
> > @@ -255,6 +256,15 @@ struct flow_action_entry {
> > u8 bos;
> > u8 ttl;
> > } mpls_mangle;
> > + struct {
> > + u32 index;
> > + s32 prio;
> > + u64 basetime;
> > + u64 cycletime;
> > + u64 cycletimeext;
> > + u32 num_entries;
> > + struct action_gate_entry *entries;
> > + } gate;
> > };
> > struct flow_action_cookie *cookie; /* user defined action cookie
> > */ }; diff --git a/include/net/tc_act/tc_gate.h
> > b/include/net/tc_act/tc_gate.h index 330ad8b02495..9e698c7d64cd
> 100644
> > --- a/include/net/tc_act/tc_gate.h
> > +++ b/include/net/tc_act/tc_gate.h
> > @@ -7,6 +7,13 @@
> > #include
> > #include
> >
> > +struct action_gate_entry {
> > + u8 gate_state;
> > + u32 interval;
> > + s32 ipv;
> > + s32 maxoctets;
> > +};
> > +
> > struct tcfg_gate_entry {
> > int index;
> > u8 gate_state;
> > @@ -44,4 +51,110 @@ struct tcf_gate {
> >
> > #define to_gate(a) ((struct tcf_gate *)a)
> >
> > +static inline bool is_tcf_gate(const struct tc_action *a) { #ifdef
> > +CONFIG_NET_CLS_ACT
> > + if (a->ops && a->ops->id == TCA_ID_GATE)
> > + return true;
> > +#endif
> > + return false;
> > +}
> > +
> > +static inline u32 tcf_gate_index(const struct tc_action *a) {
> > + return a->tcfa_index;
> > +}
> > +
> > +static inline s32 tcf_gate_prio(const struct tc_action *a) {
> > + s32 tcfg_prio;
> > +
> > + rcu_read_lock();
>
> This action no longer uses rcu, so you don't need protect with
> rcu_read_lock() in all these helpers.
I would remove all the rcu_read_lock() here in this patch.
>
> > + tcfg_prio = to_gate(a)->param.tcfg_priority;
> > + rcu_read_unlock();
> > +
> > + return tcfg_prio;
> > +}
> > +
> > +static inline u64 tcf_gate_basetime(const struct tc_action *a) {
> > + u64 tcfg_basetime;
> > +
> > + rcu_read_lock();
> > + tcfg_basetime = to_gate(a)->param.tcfg_basetime;
> > + rcu_read_unlock();
> > +
> > + return tcfg_basetime;
> > +}
> > +
> > +static inline u64 tcf_gate_cycletime(const struct tc_action *a) {
> > + u64 tcfg_cycletime;
> > +
> > + rcu_read_lock();
> > + tcfg_cycletime = to_gate(a)->param.tcfg_cycl
RE: [EXT] Re: [v4,net-next 1/4] net: qos: introduce a gate control flow action
Hi Vlad, > -Original Message- > From: Vlad Buslov > Sent: 2020年4月30日 1:04 > To: Po Liu > Cc: da...@davemloft.net; linux-kernel@vger.kernel.org; > net...@vger.kernel.org; vinicius.go...@intel.com; Claudiu Manoil > ; Vladimir Oltean ; > Alexandru Marginean ; > michael.c...@broadcom.com; vis...@chelsio.com; > sae...@mellanox.com; l...@kernel.org; j...@mellanox.com; > ido...@mellanox.com; alexandre.bell...@bootlin.com; > unglinuxdri...@microchip.com; k...@kernel.org; j...@mojatatu.com; > xiyou.wangc...@gmail.com; simon.hor...@netronome.com; > pa...@netfilter.org; mo...@mellanox.com; m-kariche...@ti.com; > andre.gue...@linux.intel.com; step...@networkplumber.org > Subject: [EXT] Re: [v4,net-next 1/4] net: qos: introduce a gate control flow > action > > Caution: EXT Email > > Hi Po, > > On Tue 28 Apr 2020 at 06:34, Po Liu wrote: > > Introduce a ingress frame gate control flow action. > > Tc gate action does the work like this: > > Assume there is a gate allow specified ingress frames can be passed at > > specific time slot, and be dropped at specific time slot. Tc filter > > chooses the ingress frames, and tc gate action would specify what slot > > does these frames can be passed to device and what time slot would be > > dropped. > > Tc gate action would provide an entry list to tell how much time gate > > keep open and how much time gate keep state close. Gate action also > > assign a start time to tell when the entry list start. Then driver > > would repeat the gate entry list cyclically. > > For the software simulation, gate action requires the user assign a > > time clock type. > > > > Below is the setting example in user space. Tc filter a stream source > > ip address is 192.168.0.20 and gate action own two time slots. One is > > last 200ms gate open let frame pass another is last 100ms gate close > > let frames dropped. When the ingress frames have reach total frames > > over > > 800 bytes, the excessive frames will be dropped in that > > 2ns time slot. > > > >> tc qdisc add dev eth0 ingress > > > >> tc filter add dev eth0 parent : protocol ip \ > > flower src_ip 192.168.0.20 \ > > action gate index 2 clockid CLOCK_TAI \ > > sched-entry open 2 -1 800 \ > > sched-entry close 1 -1 -1 > > > >> tc chain del dev eth0 ingress chain 0 > > > > "sched-entry" follow the name taprio style. Gate state is > > "open"/"close". Follow with period nanosecond. Then next item is > > internal priority value means which ingress queue should put. "-1" > > means wildcard. The last value optional specifies the maximum number > > of MSDU octets that are permitted to pass the gate during the > > specified time interval. > > Base-time is not set will be 0 as default, as result start time would > > be ((N + 1) * cycletime) which is the minimal of future time. > > > > Below example shows filtering a stream with destination mac address is > > 10:00:80:00:00:00 and ip type is ICMP, follow the action gate. The > > gate action would run with one close time slot which means always keep > close. > > The time cycle is total 2ns. The base-time would calculate by: > > > > 13570 + (N + 1) * cycletime > > > > When the total value is the future time, it will be the start time. > > The cycletime here would be 2ns for this case. > > > >> tc filter add dev eth0 parent : protocol ip \ > > flower skip_hw ip_proto icmp dst_mac 10:00:80:00:00:00 \ > > action gate index 12 base-time 13570 \ > > sched-entry close 2 -1 -1 \ > > clockid CLOCK_TAI > > > > Signed-off-by: Po Liu > > --- > > include/net/tc_act/tc_gate.h| 47 ++ > > include/uapi/linux/pkt_cls.h| 1 + > > include/uapi/linux/tc_act/tc_gate.h | 47 ++ > > net/sched/Kconfig | 12 + > > net/sched/Makefile | 1 + > > net/sched/act_gate.c| 638 > > 6 files changed, 746 insertions(+) > > create mode 100644 include/net/tc_act/tc_gate.h create mode 100644 > > include/uapi/linux/tc_act/tc_gate.h > > create mode 100644 net/sched/act_gate.c > > > > diff --git a/include/net/tc_act/tc_gate.h > > b/include/net/tc_act/tc_gate.h new file mode 100644 index > > ..330ad8b02495 > > --- /dev/null > > +++ b/include/net/tc_act/tc_gate.h > > @@ -0,0 +1,47 @@
RE: [PATCH] net: tsn: add an netlink interface between kernel and application layer
Hi Ilias, > -Original Message- > From: Ilias Apalodimas [mailto:ilias.apalodi...@linaro.org] > Sent: 2019年1月3日 19:39 > To: Po Liu > Cc: Vinicius Costa Gomes ; net...@vger.kernel.org; > linux-kernel@vger.kernel.org; da...@davemloft.net; haus...@cisco.com; > nicolas.fe...@microchip.com; gre...@linuxfoundation.org; Mingkai Hu > ; Roy Zang > Subject: Re: [PATCH] net: tsn: add an netlink interface between kernel and > application layer > > Hi Po, > > > > > > Some protocols target to configure the traffic class(like Qav CBS). > > > > > Some to config the port(like Qbv). But some for the whole > > > > > ethernet controller(like Qci, the control entries for the whole > > > > > controller, which input ports and which output ports). > > > > > > > > Reading your email, now I understand your point a little better. > > > > You are interested in multi-port devices. I admit that I am not > > > > too familiar with how multi-port devices are exposed in Linux, I > > > > was only focused on the end-station use cases, until now. > > > > > > Have you considered a switchdev-based driver for multi-port devices? > > [Po] Yes, the patch is including the switchdev-based driver. In fact, we > > have > driver examples for ls1028 which include end-station IP and switch ports IP, > with this interface driver, it is working. But we need to add base ethernet > driver > of ENETC(end station) and FELIX(switch) upstream first, then add the TSN > driver > upstream. > > > > > What you ask of TSN configuration is currently doable with switch > > > switchdev for VLANs and other similar networking functionality. > > [Po] I think the VLAN configure is not conflict with the TSN. TSN is > > extending > the 8021Q. TSN configure the setting of filter frame or scheduling between TC. > But maybe need to consider as whole as you said. > > VLAN was an example of devices already performing complex configuration > using switchdev and configurating 'switch' ports and 'cpu' port(s) > individually. > It wasn't related to TSN or its 802.1Qbv importance in any way. > > > > > > > Instead of rewriting this from scratch, we not extend the currect TC > > > and switchdev functionality for that ? > > > > [Po] Ya, there are operations of switchdev. You may think that to add the > > TSN > configurations ops into switchdev operations. But we need to consider the > end- > station devices and switch all in the devices or in the TSN domain. The TSN > domain is the devices include TSN capabilities ports, for up layer, we need to > provide a formal interface. So tsn configure can be standalone. > > In this patch, we treat two kinds of ports when registering the ports, end- > station or switch. This may treat them in some minor differences in TSN spec > and drivers. > > > > Why are switches different than end-stations configuration wise? Minor differences but still have mentioned in spec. > I understand that you may need to support different TSN IEEE standards per > device, but adding support for different capabilities shouldn't affect a > 'common' > configuration path. > That's the actual advantage of switchdev based drivers. switches and end > stations will have a very similar way of confiration via iproute2/bridge/tc > utils. > Am i missing something? > I guess I start to getting your advise. Do you mean to add operations in struct switchdev_ops ? Is it proper include end station? I used to add structure tsn_ops in net_device. But I think there are some information and status of devices maintain in the kernel from drivers. So I create structure tsn_port standalone. Yes, iproute2/bridge/tc is one choice for user space. I would think of the possible. But the too many parameters are still the problem. For example to create Qbv gate list. > /Ilias
RE: [PATCH] net: tsn: add an netlink interface between kernel and application layer
Hi Ilias, Br, Po Liu > -Original Message- > From: Ilias Apalodimas [mailto:ilias.apalodi...@linaro.org] > Sent: 2019年1月3日 17:16 > To: Vinicius Costa Gomes > Cc: Po Liu ; net...@vger.kernel.org; linux- > ker...@vger.kernel.org; da...@davemloft.net; haus...@cisco.com; > nicolas.fe...@microchip.com; gre...@linuxfoundation.org; Mingkai Hu > ; Roy Zang > Subject: Re: [PATCH] net: tsn: add an netlink interface between kernel and > application layer > > Hi Po, > > > > Hi Vinicius, > > > > > > Thank you very much for your feedback. > > > > > > I know the CBS is used to be most important part of AVB. And qdiscs is > > > good > tool to configure qos. > > > > > > But as you know, the TSN family is a cluster of protocols and much > extending the AVB. The protocols have different functionalities and they may > have more than hundred parameters. For example NXP ls1028a support > Qbv/Qci/Qbu/Qav and also the 8021CB (not included in this patch yet). > > > > > > Some protocols target to configure the traffic class(like Qav CBS). > > > Some to config the port(like Qbv). But some for the whole ethernet > > > controller(like Qci, the control entries for the whole controller, > > > which input ports and which output ports). > > > > Reading your email, now I understand your point a little better. You > > are interested in multi-port devices. I admit that I am not too > > familiar with how multi-port devices are exposed in Linux, I was only > > focused on the end-station use cases, until now. > > Have you considered a switchdev-based driver for multi-port devices? [Po] Yes, the patch is including the switchdev-based driver. In fact, we have driver examples for ls1028 which include end-station IP and switch ports IP, with this interface driver, it is working. But we need to add base ethernet driver of ENETC(end station) and FELIX(switch) upstream first, then add the TSN driver upstream. > What you ask of TSN configuration is currently doable with switch switchdev > for VLANs and other similar networking functionality. [Po] I think the VLAN configure is not conflict with the TSN. TSN is extending the 8021Q. TSN configure the setting of filter frame or scheduling between TC. But maybe need to consider as whole as you said. > > Instead of rewriting this from scratch, we not extend the currect TC and > switchdev functionality for that ? [Po] Ya, there are operations of switchdev. You may think that to add the TSN configurations ops into switchdev operations. But we need to consider the end-station devices and switch all in the devices or in the TSN domain. The TSN domain is the devices include TSN capabilities ports, for up layer, we need to provide a formal interface. So tsn configure can be standalone. In this patch, we treat two kinds of ports when registering the ports, end-station or switch. This may treat them in some minor differences in TSN spec and drivers. > > > Regards > /Ilias
RE: [PATCH] net: tsn: add an netlink interface between kernel and application layer
Hi Vinicius, Thanks! As comments below. Br, Po Liu > -Original Message- > From: Vinicius Costa Gomes [mailto:vinicius.go...@intel.com] > Sent: 2019年1月3日 3:02 > To: Po Liu ; net...@vger.kernel.org; linux- > ker...@vger.kernel.org > Cc: da...@davemloft.net; haus...@cisco.com; nicolas.fe...@microchip.com; > gre...@linuxfoundation.org; Mingkai Hu ; Roy Zang > > Subject: RE: [PATCH] net: tsn: add an netlink interface between kernel and > application layer > > Hi Po Liu, > > PO LIU writes: > > > Hi Vinicius, > > > > Thank you very much for your feedback. > > > > I know the CBS is used to be most important part of AVB. And qdiscs is good > tool to configure qos. > > > > But as you know, the TSN family is a cluster of protocols and much extending > the AVB. The protocols have different functionalities and they may have more > than hundred parameters. For example NXP ls1028a support > Qbv/Qci/Qbu/Qav and also the 8021CB (not included in this patch yet). > > > > Some protocols target to configure the traffic class(like Qav CBS). > > Some to config the port(like Qbv). But some for the whole ethernet > > controller(like Qci, the control entries for the whole controller, > > which input ports and which output ports). > > Reading your email, now I understand your point a little better. You are > interested in multi-port devices. I admit that I am not too familiar with how > multi-port devices are exposed in Linux, I was only focused on the end-station > use cases, until now. > > > > > So I do think all the TSN configuration should not mix in the ethernet > > driver itself. I mean the driver should separate a xxx_tsn.c(for I210, > > may igb_tsn.c) to maintain the tsn operations. > > > As far as using qdiscs or the interface of generic netlink. I think > > both could configuring the TSN protocols interface layer. Just what I > > provided the patch net/tsn/genl_tsn.c. But I do believe it is better > > using a standalone TSN middle layer to maintain the TSN capability > > ports. Because the TSN ports include not only the end station and also > > the switch. LS1028 is such a kind of device. > > I think this is the "interesting" part of the discussion. From my point of > view the > question now is: > > "We already have an acceptable way to expoose TSN features for end stations. > What can we do for multi-port devices?" [Po Liu] correct, that is what we expect to do. There could be with more than one ethernet controllers(or switch) with TSN capability. Ether pci plug in, or SOC chips. This patch try to manage all. > > What are the options here? From a quick look, it seems that extending > switchdev is a possible solution. What else? [Po Liu] that's it. Could extend it. > > Thinking a little more, if all the ports have netdevices associated with them, > then it could be that exposing those features via qdiscs could be considered > still. > Perhaps taking a look at how tc-flower offloading is done can give some ideas. [Po Liu] I did using the tc-flower at application layer to filter the frames to different queue. I avoid to using the qos but only using the multiq to make all traffic classes to be exposed to user space. I am trying to understand what your patch working on the qdisc and how it help for TSN. > > And about the process, usually when a new interface is proposed, the patches > are directed to net-next and have the RFC tag, so the readers (and their > tools) > know what to expect. [Po Liu] thanks for the mention, I would update. > > > > > And your advises are precious for us. Let's make out an easy and > > flexible interface for TSN. > > > > Br, > > Po Liu > > > > Cheers, > -- > Vinicius
RE: [PATCH] net: tsn: add an netlink interface between kernel and application layer
Hi Vinicius, Thank you very much for your feedback. I know the CBS is used to be most important part of AVB. And qdiscs is good tool to configure qos. But as you know, the TSN family is a cluster of protocols and much extending the AVB. The protocols have different functionalities and they may have more than hundred parameters. For example NXP ls1028a support Qbv/Qci/Qbu/Qav and also the 8021CB (not included in this patch yet). Some protocols target to configure the traffic class(like Qav CBS). Some to config the port(like Qbv). But some for the whole ethernet controller(like Qci, the control entries for the whole controller, which input ports and which output ports). So I do think all the TSN configuration should not mix in the ethernet driver itself. I mean the driver should separate a xxx_tsn.c(for I210, may igb_tsn.c) to maintain the tsn operations. As far as using qdiscs or the interface of generic netlink. I think both could configuring the TSN protocols interface layer. Just what I provided the patch net/tsn/genl_tsn.c. But I do believe it is better using a standalone TSN middle layer to maintain the TSN capability ports. Because the TSN ports include not only the end station and also the switch. LS1028 is such a kind of device. And your advises are precious for us. Let's make out an easy and flexible interface for TSN. Br, Po Liu > -Original Message- > From: Vinicius Costa Gomes [mailto:vinicius.go...@intel.com] > Sent: 2018年12月29日 3:30 > To: PO LIU ; net...@vger.kernel.org; linux- > ker...@vger.kernel.org > Cc: da...@davemloft.net; haus...@cisco.com; nicolas.fe...@microchip.com; > gre...@linuxfoundation.org; Mingkai Hu ; Roy Zang > ; PO LIU ; PO LIU > Subject: Re: [PATCH] net: tsn: add an netlink interface between kernel and > application layer > > Hi, > > PO LIU writes: > > > This patch provids netlink method to configure the TSN protocols hardwares. > > TSN guaranteed packet transport with bounded low latency, low packet > > delay variation, and low packet loss by hardware and software methods. > > I don't think having another way to configure TSN features is a good idea. We > already have the CBS/ETF/taprio family of qdiscs, that provide (or will in the > near future, more on this later) a way to configure the hardware. > > A little background on the choice of qdiscs as an interface (and why we came > to > believe they are a good abstraction), they already provide a way to map > packets into traffic classes (it isn't clear in our proposal how you do that, > but I > think you are using something like mqprio), they provide a neat way to > "compose" (by installing one under another), they already have a user facing > API with various counters, and very importantly for TSN they have mecanisms > to offload some of their work to the hardware. > > I suggest is for you to take a look at how CBS offloading was implemented for > the Intel i210: > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch > work.ozlabs.org%2Fcover%2F824626%2Fdata=02%7C01%7Cpo.liu%40n > xp.com%7C107e693326214900cf0708d66cfadace%7C686ea1d3bc2b4c6fa92c > d99c5c301635%7C0%7C0%7C636816222009310445sdata=6O1s%2Bd% > 2BbNek1Ko7a5ev0txiw8S6TiVeUrUWZlOXDnAw%3Dreserved=0 > > Patches 4 and 5 should be the interesting ones. I think you can use them as > inspiration for enabling CBS offload in your driver. > > If you did take a look at those patches (and the current work that has been > upstreamed), my question then becomes, what are the reasons that it might > not work for your use cases? > > > > > The three basic components of TSN are: > > > > 1. Time synchronization: This was implement by 8021AS which base on the > >IEEE1588 precision Time Protocol. This is configured by the other way > >in kernel. > >8021AS not included in this patch. > > > > 2. Scheduling and traffic shaping and per-stream filter policing: > >This patch support Qbv/Qci. > > I am working on a proposal for the API for Qbv (and Qbu) offloading using > taprio. I should send it soon-ish. Your feedback would be very welcome. > > Also, how to expose in the qdiscs the per-stream filtering and policing parts > (Qci) > is something that I don't know how to do right now, any suggestions would be > nice. > > In short, take a look at what's there and see what's missing for the stuff > that > you care about, then we can work on that. > > > > > 3. Selection of communication paths: > >This patch not support the pure software only TSN protocols(like Qcc) > >but hardware related configuration. > > > > TSN Protocols supports by this patch: Qbv/Qci/Qbu/Credit-base Shaper(Qav). > > This patch verified on NXP ls1028ardb board. > > > > Will add more protocols in the future. > > > > Signed-off-by: Po Liu > > > Cheers, > -- > Vinicius
[PATCH] net: tsn: add an netlink interface between kernel and application layer
This patch provids netlink method to configure the TSN protocols hardwares.
TSN guaranteed packet transport with bounded low latency, low packet delay
variation, and low packet loss by hardware and software methods.
The three basic components of TSN are:
1. Time synchronization: This was implement by 8021AS which base on the
IEEE1588 precision Time Protocol. This is configured by the other way
in kernel.
8021AS not included in this patch.
2. Scheduling and traffic shaping and per-stream filter policing:
This patch support Qbv/Qci.
3. Selection of communication paths:
This patch not support the pure software only TSN protocols(like Qcc)
but hardware related configuration.
TSN Protocols supports by this patch: Qbv/Qci/Qbu/Credit-base Shaper(Qav).
This patch verified on NXP ls1028ardb board.
Will add more protocols in the future.
Signed-off-by: Po Liu
---
MAINTAINERS |6 +
include/net/tsn.h| 76 ++
include/uapi/linux/tsn.h | 958 +
net/Kconfig |1 +
net/Makefile |3 +
net/tsn/Kconfig | 15 +
net/tsn/Makefile |1 +
net/tsn/genl_tsn.c | 2626 ++
8 files changed, 3686 insertions(+)
create mode 100644 include/net/tsn.h
create mode 100644 include/uapi/linux/tsn.h
create mode 100644 net/tsn/Kconfig
create mode 100644 net/tsn/Makefile
create mode 100644 net/tsn/genl_tsn.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a9804a..bc037e3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15385,6 +15385,12 @@ F: sound/soc/codecs/tscs*.c
F: sound/soc/codecs/tscs*.h
F: Documentation/devicetree/bindings/sound/tscs*.txt
+TSN NETLINK INTERFACE DRVIER
+M: Po Liu
+F: net/tsn/genl_tsn.c
+F: include/net/tsn.h
+F: include/uapi/linux/tsn.h
+
TTY LAYER
M: Greg Kroah-Hartman
M: Jiri Slaby
diff --git a/include/net/tsn.h b/include/net/tsn.h
new file mode 100644
index 000..008360c
--- /dev/null
+++ b/include/net/tsn.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/* Copyright 2017-2018 NXP */
+
+#ifndef __TSN_H__
+#define __TSN_H__
+
+#include
+
+struct tsn_ops {
+ void (*device_init)(struct net_device *ndev);
+ void (*device_deinit)(struct net_device *ndev);
+ u32 (*get_capability)(struct net_device *ndev);
+ /* Qbv standard */
+ int (*qbv_set)(struct net_device *ndev, struct tsn_qbv_conf *qbvconf);
+ int (*qbv_get)(struct net_device *ndev, struct tsn_qbv_conf *qbvconf);
+ int (*qbv_get_status)(struct net_device *ndev,
+ struct tsn_qbv_status *qbvstat);
+ int (*cb_streamid_set)(struct net_device *ndev, u32 index,
+ bool enable, struct tsn_cb_streamid *sid);
+ int (*cb_streamid_get)(struct net_device *ndev, u32 index,
+ struct tsn_cb_streamid *sid);
+ int (*cb_streamid_counters_get)(struct net_device *ndev, u32 index,
+ struct tsn_cb_streamid_counters *sidcounter);
+ int (*qci_get_maxcap)(struct net_device *ndev,
+ struct tsn_qci_psfp_stream_param *qcicapa);
+ int (*qci_sfi_set)(struct net_device *ndev, u32 index, bool enable,
+ struct tsn_qci_psfp_sfi_conf *sficonf);
+ /* return: 0 stream filter instance not valid
+* 1 stream filter instance valid
+* -1 error happened
+*/
+ int (*qci_sfi_get)(struct net_device *ndev, u32 index,
+ struct tsn_qci_psfp_sfi_conf *sficonf);
+ int (*qci_sfi_counters_get)(struct net_device *ndev, u32 index,
+ struct tsn_qci_psfp_sfi_counters *sficounter);
+ int (*qci_sgi_set)(struct net_device *ndev, u32 index,
+ struct tsn_qci_psfp_sgi_conf *sgiconf);
+ int (*qci_sgi_get)(struct net_device *ndev, u32 index,
+ struct tsn_qci_psfp_sgi_conf *sgiconf);
+ int (*qci_sgi_status_get)(struct net_device *ndev, u16 index,
+ struct tsn_psfp_sgi_status *sgistat);
+ int (*qci_fmi_set)(struct net_device *ndev, u32 index, bool enable,
+ struct tsn_qci_psfp_fmi *fmi);
+ int (*qci_fmi_get)(struct net_device *ndev, u32 index,
+ struct tsn_qci_psfp_fmi *fmi,
+ struct tsn_qci_psfp_fmi_counters *counters);
+ int (*cbs_set)(struct net_device *ndev, u8 tc, u8 bw);
+ int (*cbs_get)(struct net_device *ndev, u8 tc);
+ /* To set a 8 bits vector shows 8 traffic classes
+* preemtable(1) or express(0)
+*/
+ int (*qbu_set)(struct net_device *ndev, u8 ptvector);
+ /* To get port preemtion status */
+ int (*qbu_get)(struct net_device *ndev,
+ struct
RE: [PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode
Hi Rob, Best regards, Liu Po > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Sunday, October 09, 2016 4:50 AM > To: Po Liu > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas; > Shawn Guo; Marc Zyngier; Roy Zang; Mingkai Hu; Stuart Yoder; Leo Li; > Arnd Bergmann; M.H. Lian; Murali Karicheri > Subject: Re: [PATCH v6 3/3] pci:add support aer/pme interrupts with none > MSI/MSI-X/INTx mode > > On Fri, Sep 30, 2016 at 05:11:37PM +0800, Po Liu wrote: > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode. > > When chip support the aer/pme interrupts with none MSI/MSI-X/INTx > > mode, maybe there is interrupt line for aer pme etc. Search the > > interrupt number in the fdt file. Then fixup the dev->irq with it. > > Again, explain why you are breaking compatibility. Will an old dtb using > "intr" still work with this change? It should normally. There are some > exceptions, but you need to say what they are. > Ok, understand. > > > > Signed-off-by: Po Liu <po@nxp.com> > > --- > > changes for v6: > >- modify bindings for "aer""pme"; > >- changing to the hood method to implement the aer pme interrupt; > >- add pme interrupt in the same way; > > > > .../devicetree/bindings/pci/layerscape-pci.txt | 13 +-- > > arch/arm/kernel/bios32.c | 43 > ++ > > arch/arm64/kernel/pci.c| 43 > ++ > > drivers/pci/pcie/portdrv_core.c| 31 > +++- > > include/linux/pci.h| 1 + > > 5 files changed, 126 insertions(+), 5 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > index 41e9f55..51ed49e 100644 > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > @@ -18,8 +18,12 @@ Required properties: > > - reg: base addresses and lengths of the PCIe controller > > - interrupts: A list of interrupt outputs of the controller. Must > contain an > >entry for each entry in the interrupt-names property. > > -- interrupt-names: Must include the following entries: > > - "intr": The interrupt that is asserted for controller interrupts > > +- interrupt-names: It could include the following entries: > > "Could" is not strong enough. Every valid combination of interrupts > should correspond to a specific compatible string. A given version of > h/w either has these interrupts or not. Ok, will change to 'must'. > > > + "aer": Asserted for aer interrupt when chip support the aer > interrupt with > > + none MSI/MSI-X/INTx mode,but there is interrupt line for > aer. > > + "pme": Asserted for pme interrupt when chip support the pme > interrupt with > > + none MSI/MSI-X/INTx mode,but there is interrupt line for > pme. > > + .. > > - fsl,pcie-scfg: Must include two entries. > >The first entry must be a link to the SCFG device node > >The second entry must be '0' or '1' based on physical PCIe > controller index.
RE: [PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode
Hi Rob, Best regards, Liu Po > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Sunday, October 09, 2016 4:50 AM > To: Po Liu > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas; > Shawn Guo; Marc Zyngier; Roy Zang; Mingkai Hu; Stuart Yoder; Leo Li; > Arnd Bergmann; M.H. Lian; Murali Karicheri > Subject: Re: [PATCH v6 3/3] pci:add support aer/pme interrupts with none > MSI/MSI-X/INTx mode > > On Fri, Sep 30, 2016 at 05:11:37PM +0800, Po Liu wrote: > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode. > > When chip support the aer/pme interrupts with none MSI/MSI-X/INTx > > mode, maybe there is interrupt line for aer pme etc. Search the > > interrupt number in the fdt file. Then fixup the dev->irq with it. > > Again, explain why you are breaking compatibility. Will an old dtb using > "intr" still work with this change? It should normally. There are some > exceptions, but you need to say what they are. > Ok, understand. > > > > Signed-off-by: Po Liu > > --- > > changes for v6: > >- modify bindings for "aer""pme"; > >- changing to the hood method to implement the aer pme interrupt; > >- add pme interrupt in the same way; > > > > .../devicetree/bindings/pci/layerscape-pci.txt | 13 +-- > > arch/arm/kernel/bios32.c | 43 > ++ > > arch/arm64/kernel/pci.c| 43 > ++ > > drivers/pci/pcie/portdrv_core.c| 31 > +++- > > include/linux/pci.h| 1 + > > 5 files changed, 126 insertions(+), 5 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > index 41e9f55..51ed49e 100644 > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > @@ -18,8 +18,12 @@ Required properties: > > - reg: base addresses and lengths of the PCIe controller > > - interrupts: A list of interrupt outputs of the controller. Must > contain an > >entry for each entry in the interrupt-names property. > > -- interrupt-names: Must include the following entries: > > - "intr": The interrupt that is asserted for controller interrupts > > +- interrupt-names: It could include the following entries: > > "Could" is not strong enough. Every valid combination of interrupts > should correspond to a specific compatible string. A given version of > h/w either has these interrupts or not. Ok, will change to 'must'. > > > + "aer": Asserted for aer interrupt when chip support the aer > interrupt with > > + none MSI/MSI-X/INTx mode,but there is interrupt line for > aer. > > + "pme": Asserted for pme interrupt when chip support the pme > interrupt with > > + none MSI/MSI-X/INTx mode,but there is interrupt line for > pme. > > + .. > > - fsl,pcie-scfg: Must include two entries. > >The first entry must be a link to the SCFG device node > >The second entry must be '0' or '1' based on physical PCIe > controller index.
[PATCH v6 2/3] arm64/dts-ls1043-ls2080: add pcie aer/pme interrupt-name property in the dts
Some platforms(NXP Layerscape for example) aer/pme interrupts was not MSI/MSI-X/INTx but using interrupt line independently. This patch add "aer", "pme" interrupt-names for aer/pme interrupt. With the interrupt-names "aer", "pme" code could probe aer/pme interrupt line for pcie root port, replace the aer/pme interrupt service irqs. This is intend to fixup the Layerscape platforms which aer/pmes interrupts was not MSI/MSI-X/INTx, but using interrupt line independently. Since the interrupt-names "intr" never been used. Remove it. Signed-off-by: Po Liu <po@nxp.com> --- changes for v6: - add remove "intr" interrupt reason. - add "pme" interrupt. arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index e669fbd..654071d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -527,9 +527,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -552,9 +552,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +<0 128 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -577,9 +577,9 @@ reg = <0x00 0x0360 0x0 0x0010 /* controller registers */ 0x50 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 162 0x4>, -<0 161 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 161 0x4>, +<0 162 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 21023a3..58844e8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -583,8 +583,8 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x10 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 108 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -607,8 +607,8 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x12 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; -
[PATCH v6 2/3] arm64/dts-ls1043-ls2080: add pcie aer/pme interrupt-name property in the dts
Some platforms(NXP Layerscape for example) aer/pme interrupts was not MSI/MSI-X/INTx but using interrupt line independently. This patch add "aer", "pme" interrupt-names for aer/pme interrupt. With the interrupt-names "aer", "pme" code could probe aer/pme interrupt line for pcie root port, replace the aer/pme interrupt service irqs. This is intend to fixup the Layerscape platforms which aer/pmes interrupts was not MSI/MSI-X/INTx, but using interrupt line independently. Since the interrupt-names "intr" never been used. Remove it. Signed-off-by: Po Liu --- changes for v6: - add remove "intr" interrupt reason. - add "pme" interrupt. arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index e669fbd..654071d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -527,9 +527,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -552,9 +552,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +<0 128 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -577,9 +577,9 @@ reg = <0x00 0x0360 0x0 0x0010 /* controller registers */ 0x50 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 162 0x4>, -<0 161 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 161 0x4>, +<0 162 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 21023a3..58844e8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -583,8 +583,8 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x10 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 108 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -607,8 +607,8 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x12 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts =
[PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu <po@nxp.com>
---
changes for v6:
- modify bindings for "aer""pme";
- changing to the hood method to implement the aer pme interrupt;
- add pme interrupt in the same way;
.../devicetree/bindings/pci/layerscape-pci.txt | 13 +--
arch/arm/kernel/bios32.c | 43 ++
arch/arm64/kernel/pci.c| 43 ++
drivers/pci/pcie/portdrv_core.c| 31 +++-
include/linux/pci.h| 1 +
5 files changed, 126 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..51ed49e 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -18,8 +18,12 @@ Required properties:
- reg: base addresses and lengths of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
- "intr": The interrupt that is asserted for controller interrupts
+- interrupt-names: It could include the following entries:
+ "aer": Asserted for aer interrupt when chip support the aer interrupt with
+none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
+ "pme": Asserted for pme interrupt when chip support the pme interrupt with
+none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
+ ..
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -35,8 +39,9 @@ Example:
reg = <0x00 0x0340 0x0 0x0001 /* controller registers
*/
0x40 0x 0x0 0x2000>; /* configuration space
*/
reg-names = "regs", "config";
- interrupts = ; /* controller
interrupt */
- interrupt-names = "intr";
+ interrupts = , /* aer
interrupt */
+ ; /* pme interrupt */
+ interrupt-names = "aer", "pme";
fsl,pcie-scfg = < 0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 2f0e077..d2f4869 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -11,6 +11,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -64,6 +66,47 @@ void pcibios_report_status(u_int status_mask, int warn)
}
/*
+ * Check device tree if the service interrupts are there
+ */
+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
+{
+ int ret, count = 0;
+ struct device_node *np = NULL;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ if (np == NULL)
+ return 0;
+
+ if (!IS_ENABLED(CONFIG_OF_IRQ))
+ return 0;
+
+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+* request irq for aer
+*/
+ if (mask & PCIE_PORT_SERVICE_AER) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+ count++;
+ }
+ }
+
+ if (mask & PCIE_PORT_SERVICE_PME) {
+ ret = of_irq_get_byname(np, "pme");
+ if (ret > 0) {
+ irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
+ count++;
+ }
+ }
+
+ /* TODO: add more service interrupts if there it is in the device tree*/
+
+ return count;
+}
+
+/*
* We don't use this to fix the device, but initialisation of it.
* It's not the correct use for this, but it works.
* Note that the arbiter/ISA bridge appears to be buggy, specifically in
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index acf3872..4a3c61a 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -17,6 +17,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -55,6 +57,47 @@ int pcibios_alloc_irq(struct pci_dev *dev)
}
/*
+ * Check device tree if the service interrupts are there
+ */
+int pcibios_check_service_irqs
[PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu
---
changes for v6:
- modify bindings for "aer""pme";
- changing to the hood method to implement the aer pme interrupt;
- add pme interrupt in the same way;
.../devicetree/bindings/pci/layerscape-pci.txt | 13 +--
arch/arm/kernel/bios32.c | 43 ++
arch/arm64/kernel/pci.c| 43 ++
drivers/pci/pcie/portdrv_core.c| 31 +++-
include/linux/pci.h| 1 +
5 files changed, 126 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..51ed49e 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -18,8 +18,12 @@ Required properties:
- reg: base addresses and lengths of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
- "intr": The interrupt that is asserted for controller interrupts
+- interrupt-names: It could include the following entries:
+ "aer": Asserted for aer interrupt when chip support the aer interrupt with
+none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
+ "pme": Asserted for pme interrupt when chip support the pme interrupt with
+none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
+ ..
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -35,8 +39,9 @@ Example:
reg = <0x00 0x0340 0x0 0x0001 /* controller registers
*/
0x40 0x 0x0 0x2000>; /* configuration space
*/
reg-names = "regs", "config";
- interrupts = ; /* controller
interrupt */
- interrupt-names = "intr";
+ interrupts = , /* aer
interrupt */
+ ; /* pme interrupt */
+ interrupt-names = "aer", "pme";
fsl,pcie-scfg = < 0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 2f0e077..d2f4869 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -11,6 +11,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -64,6 +66,47 @@ void pcibios_report_status(u_int status_mask, int warn)
}
/*
+ * Check device tree if the service interrupts are there
+ */
+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
+{
+ int ret, count = 0;
+ struct device_node *np = NULL;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ if (np == NULL)
+ return 0;
+
+ if (!IS_ENABLED(CONFIG_OF_IRQ))
+ return 0;
+
+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+* request irq for aer
+*/
+ if (mask & PCIE_PORT_SERVICE_AER) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+ count++;
+ }
+ }
+
+ if (mask & PCIE_PORT_SERVICE_PME) {
+ ret = of_irq_get_byname(np, "pme");
+ if (ret > 0) {
+ irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
+ count++;
+ }
+ }
+
+ /* TODO: add more service interrupts if there it is in the device tree*/
+
+ return count;
+}
+
+/*
* We don't use this to fix the device, but initialisation of it.
* It's not the correct use for this, but it works.
* Note that the arbiter/ISA bridge appears to be buggy, specifically in
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index acf3872..4a3c61a 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -17,6 +17,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -55,6 +57,47 @@ int pcibios_alloc_irq(struct pci_dev *dev)
}
/*
+ * Check device tree if the service interrupts are there
+ */
+int pcibios_check_service_irqs(struct pci_dev *de
[PATCH v6 1/3] arm/dts-ls1021: add pcie aer/pme interrupt-name property in the dts
NXP arm aer/pme interrupts was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" "pme" interrupt-names for aer/pme interrupts. With the interrupt-names "aer","pme" code could probe aer/pme interrupt line for pcie root port, replace the aer/pme interrupt service irqs. This patch is intend to fixup the Layerscape platforms which aer/pme interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Since the interrupt-names "intr" never been used. Remove it. Signed-off-by: Po Liu <po@nxp.com> --- changes for v6: - add remove "intr" reason; - add "pme" interrupt; arch/arm/boot/dts/ls1021a.dtsi | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..9b3cb3b 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -634,7 +634,9 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = , + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -657,7 +659,9 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = , + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; -- 2.1.0.27.g96db324
[PATCH v6 1/3] arm/dts-ls1021: add pcie aer/pme interrupt-name property in the dts
NXP arm aer/pme interrupts was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" "pme" interrupt-names for aer/pme interrupts. With the interrupt-names "aer","pme" code could probe aer/pme interrupt line for pcie root port, replace the aer/pme interrupt service irqs. This patch is intend to fixup the Layerscape platforms which aer/pme interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Since the interrupt-names "intr" never been used. Remove it. Signed-off-by: Po Liu --- changes for v6: - add remove "intr" reason; - add "pme" interrupt; arch/arm/boot/dts/ls1021a.dtsi | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..9b3cb3b 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -634,7 +634,9 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = , + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -657,7 +659,9 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = , + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; -- 2.1.0.27.g96db324
RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Rob, > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Friday, September 23, 2016 9:06 PM > To: Po Liu > Cc: Shawn Guo; linux-...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; > devicet...@vger.kernel.org; Roy Zang; Arnd Bergmann; Marc Zyngier; > Stuart Yoder; Leo Li; M.H. Lian; Murali Karicheri; Bjorn Helgaas; > Mingkai Hu > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none > MSI/MSI-X/INTx mode > > On Sun, Sep 18, 2016 at 03:37:27AM +, Po Liu wrote: > > Hi Shawn, > > > > > > > -Original Message- > > > From: Shawn Guo [mailto:shawn...@kernel.org] > > > Sent: Sunday, September 18, 2016 8:52 AM > > > To: Po Liu > > > Cc: linux-...@vger.kernel.org; > > > linux-arm-ker...@lists.infradead.org; > > > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; > > > Arnd Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; > > > Murali Karicheri; Bjorn Helgaas; Mingkai Hu > > > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with > > > none MSI/MSI-X/INTx mode > > > > > > On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote: > > > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC > mode. > > > > When chip support the aer interrupt with none MSI/MSI-X/INTx > > > mode, > maybe there is interrupt line for aer pme etc. Search the > > > interrupt > number in the fdt file. Then fixup the dev->irq with it. > > > > > > > > Signed-off-by: Po Liu <po@nxp.com> > > > > > > Will the new kernel work with existing/old DTB? I'm trying to > > > understand the dependency between driver and DTS changes. > > > > Yes, We've never use name 'intr' before. So we remove it is ok. > > 'aer' is a dts name for researching it's true interrupt number by > > kernel. This patch is first time to use name 'aer'. So it must be > > compatible with existing/old DTB. > > Please explain why you are not breaking compatibility in the commit > message. I asked for this on v2. Sorry, I didn't really catch what your means. Do you mean I should add why I remove the 'intr'? > > > > > --- > > > > changes for v5: > > > > - Add clear 'aer' interrup-names description > > > > > > > > .../devicetree/bindings/pci/layerscape-pci.txt | 11 +--- > > > > drivers/pci/pcie/portdrv_core.c| 31 > > > +++--- > > > > 2 files changed, 35 insertions(+), 7 deletions(-) > > diff > > > --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > index 41e9f55..101d0a7 100644 > > > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > @@ -18,8 +18,10 @@ Required properties: > > > > - reg: base addresses and lengths of the PCIe controller > - > > > interrupts: A list of interrupt outputs of the controller. Must > > > contain an > > > >entry for each entry in the interrupt-names property. > > > > -- interrupt-names: Must include the following entries: > > > > - "intr": The interrupt that is asserted for controller > > > interrupts > +- interrupt-names: It may be include the following > entries: > > "may be" is not okay. It should be "must" or explain when an interrupt > would not be present. Really, differences in interrupts means you need > different compatible strings. How about changing "must" to "should" or "could" and also add when to add after "aer": to explain when to add it? Thanks! > > Rob > > > > > + "aer": The interrupt that is asserted for aer interrupt > + > > > "pme": The interrupt that is asserted for pme interrupt > + ..
RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Rob, > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Friday, September 23, 2016 9:06 PM > To: Po Liu > Cc: Shawn Guo; linux-...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; > devicet...@vger.kernel.org; Roy Zang; Arnd Bergmann; Marc Zyngier; > Stuart Yoder; Leo Li; M.H. Lian; Murali Karicheri; Bjorn Helgaas; > Mingkai Hu > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none > MSI/MSI-X/INTx mode > > On Sun, Sep 18, 2016 at 03:37:27AM +, Po Liu wrote: > > Hi Shawn, > > > > > > > -Original Message- > > > From: Shawn Guo [mailto:shawn...@kernel.org] > > > Sent: Sunday, September 18, 2016 8:52 AM > > > To: Po Liu > > > Cc: linux-...@vger.kernel.org; > > > linux-arm-ker...@lists.infradead.org; > > > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; > > > Arnd Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; > > > Murali Karicheri; Bjorn Helgaas; Mingkai Hu > > > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with > > > none MSI/MSI-X/INTx mode > > > > > > On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote: > > > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC > mode. > > > > When chip support the aer interrupt with none MSI/MSI-X/INTx > > > mode, > maybe there is interrupt line for aer pme etc. Search the > > > interrupt > number in the fdt file. Then fixup the dev->irq with it. > > > > > > > > Signed-off-by: Po Liu > > > > > > Will the new kernel work with existing/old DTB? I'm trying to > > > understand the dependency between driver and DTS changes. > > > > Yes, We've never use name 'intr' before. So we remove it is ok. > > 'aer' is a dts name for researching it's true interrupt number by > > kernel. This patch is first time to use name 'aer'. So it must be > > compatible with existing/old DTB. > > Please explain why you are not breaking compatibility in the commit > message. I asked for this on v2. Sorry, I didn't really catch what your means. Do you mean I should add why I remove the 'intr'? > > > > > --- > > > > changes for v5: > > > > - Add clear 'aer' interrup-names description > > > > > > > > .../devicetree/bindings/pci/layerscape-pci.txt | 11 +--- > > > > drivers/pci/pcie/portdrv_core.c| 31 > > > +++--- > > > > 2 files changed, 35 insertions(+), 7 deletions(-) > > diff > > > --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > index 41e9f55..101d0a7 100644 > > > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > @@ -18,8 +18,10 @@ Required properties: > > > > - reg: base addresses and lengths of the PCIe controller > - > > > interrupts: A list of interrupt outputs of the controller. Must > > > contain an > > > >entry for each entry in the interrupt-names property. > > > > -- interrupt-names: Must include the following entries: > > > > - "intr": The interrupt that is asserted for controller > > > interrupts > +- interrupt-names: It may be include the following > entries: > > "may be" is not okay. It should be "must" or explain when an interrupt > would not be present. Really, differences in interrupts means you need > different compatible strings. How about changing "must" to "should" or "could" and also add when to add after "aer": to explain when to add it? Thanks! > > Rob > > > > > + "aer": The interrupt that is asserted for aer interrupt > + > > > "pme": The interrupt that is asserted for pme interrupt > + ..
RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Bjorn,
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Thursday, September 22, 2016 6:38 AM
> To: Po Liu
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd
> Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
> Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
> MSI/MSI-X/INTx mode
>
> On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu <po@nxp.com>
> > ---
> > changes for v5:
> >- Add clear 'aer' interrup-names description
> >
> > .../devicetree/bindings/pci/layerscape-pci.txt | 11 +---
> > drivers/pci/pcie/portdrv_core.c| 31
> +++---
> > 2 files changed, 35 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 41e9f55..101d0a7 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -18,8 +18,10 @@ Required properties:
> > - reg: base addresses and lengths of the PCIe controller
> > - interrupts: A list of interrupt outputs of the controller. Must
> contain an
> >entry for each entry in the interrupt-names property.
> > -- interrupt-names: Must include the following entries:
> > - "intr": The interrupt that is asserted for controller interrupts
> > +- interrupt-names: It may be include the following entries:
> > + "aer": The interrupt that is asserted for aer interrupt
> > + "pme": The interrupt that is asserted for pme interrupt
> > + ..
> > - fsl,pcie-scfg: Must include two entries.
> >The first entry must be a link to the SCFG device node
> >The second entry must be '0' or '1' based on physical PCIe
> controller index.
> > @@ -35,8 +37,9 @@ Example:
> >reg = <0x00 0x0340 0x0 0x0001 /* controller
> registers */
> > 0x40 0x 0x0 0x2000>; /* configuration
> space */
> >reg-names = "regs", "config";
> > - interrupts = ; /*
> controller interrupt */
> > - interrupt-names = "intr";
> > + interrupts = , /* aer
> interrupt */
> > + ; /* pme interrupt */
> > + interrupt-names = "aer", "pme";
> >fsl,pcie-scfg = < 0>;
> >#address-cells = <3>;
> >#size-cells = <2>;
> > diff --git a/drivers/pci/pcie/portdrv_core.c
> > b/drivers/pci/pcie/portdrv_core.c index e9270b4..7c4943d 100644
> > --- a/drivers/pci/pcie/portdrv_core.c
> > +++ b/drivers/pci/pcie/portdrv_core.c
> > @@ -16,6 +16,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include "../pci.h"
> > #include "portdrv.h"
> > @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev
> > *dev, int *vectors, int mask) static int init_service_irqs(struct
> > pci_dev *dev, int *irqs, int mask) {
> >int i, irq = -1;
> > + int ret;
> > + struct device_node *np = NULL;
> > +
> > + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> > + irqs[i] = 0;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * request irq for aer
> > + */
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> > + (mask & PCIE_PORT_SERVICE_PME)) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> > + if (dev->irq)
> > + irq = dev->irq;
> > + goto no_msi;
> > + }
> >
RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Bjorn,
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Thursday, September 22, 2016 6:38 AM
> To: Po Liu
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd
> Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
> Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
> MSI/MSI-X/INTx mode
>
> On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu
> > ---
> > changes for v5:
> >- Add clear 'aer' interrup-names description
> >
> > .../devicetree/bindings/pci/layerscape-pci.txt | 11 +---
> > drivers/pci/pcie/portdrv_core.c| 31
> +++---
> > 2 files changed, 35 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 41e9f55..101d0a7 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -18,8 +18,10 @@ Required properties:
> > - reg: base addresses and lengths of the PCIe controller
> > - interrupts: A list of interrupt outputs of the controller. Must
> contain an
> >entry for each entry in the interrupt-names property.
> > -- interrupt-names: Must include the following entries:
> > - "intr": The interrupt that is asserted for controller interrupts
> > +- interrupt-names: It may be include the following entries:
> > + "aer": The interrupt that is asserted for aer interrupt
> > + "pme": The interrupt that is asserted for pme interrupt
> > + ..
> > - fsl,pcie-scfg: Must include two entries.
> >The first entry must be a link to the SCFG device node
> >The second entry must be '0' or '1' based on physical PCIe
> controller index.
> > @@ -35,8 +37,9 @@ Example:
> >reg = <0x00 0x0340 0x0 0x0001 /* controller
> registers */
> > 0x40 0x 0x0 0x2000>; /* configuration
> space */
> >reg-names = "regs", "config";
> > - interrupts = ; /*
> controller interrupt */
> > - interrupt-names = "intr";
> > + interrupts = , /* aer
> interrupt */
> > + ; /* pme interrupt */
> > + interrupt-names = "aer", "pme";
> >fsl,pcie-scfg = < 0>;
> >#address-cells = <3>;
> >#size-cells = <2>;
> > diff --git a/drivers/pci/pcie/portdrv_core.c
> > b/drivers/pci/pcie/portdrv_core.c index e9270b4..7c4943d 100644
> > --- a/drivers/pci/pcie/portdrv_core.c
> > +++ b/drivers/pci/pcie/portdrv_core.c
> > @@ -16,6 +16,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include "../pci.h"
> > #include "portdrv.h"
> > @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev
> > *dev, int *vectors, int mask) static int init_service_irqs(struct
> > pci_dev *dev, int *irqs, int mask) {
> >int i, irq = -1;
> > + int ret;
> > + struct device_node *np = NULL;
> > +
> > + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> > + irqs[i] = 0;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * request irq for aer
> > + */
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> > + (mask & PCIE_PORT_SERVICE_PME)) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> > + if (dev->irq)
> > + irq = dev->irq;
> > + goto no_msi;
> > + }
> > + }
>
> We def
RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Shawn, > -Original Message- > From: Shawn Guo [mailto:shawn...@kernel.org] > Sent: Tuesday, September 20, 2016 8:39 PM > To: Po Liu > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd > Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali > Karicheri; Bjorn Helgaas; Mingkai Hu > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none > MSI/MSI-X/INTx mode > > On Sun, Sep 18, 2016 at 03:37:27AM +, Po Liu wrote: > > Hi Shawn, > > > > > > > -Original Message- > > > From: Shawn Guo [mailto:shawn...@kernel.org] > > > Sent: Sunday, September 18, 2016 8:52 AM > > > To: Po Liu > > > Cc: linux-...@vger.kernel.org; > > > linux-arm-ker...@lists.infradead.org; > > > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; > > > Arnd Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; > > > Murali Karicheri; Bjorn Helgaas; Mingkai Hu > > > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with > > > none MSI/MSI-X/INTx mode > > > > > > On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote: > > > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC > mode. > > > > When chip support the aer interrupt with none MSI/MSI-X/INTx > > > mode, > maybe there is interrupt line for aer pme etc. Search the > > > interrupt > number in the fdt file. Then fixup the dev->irq with it. > > > > > > > > Signed-off-by: Po Liu <po@nxp.com> > > > > > > Will the new kernel work with existing/old DTB? I'm trying to > > > understand the dependency between driver and DTS changes. > > > > Yes, We've never use name 'intr' before. So we remove it is ok. > > 'aer' is a dts name for researching it's true interrupt number by > kernel. This patch is first time to use name 'aer'. So it must be > compatible with existing/old DTB. > > Does that mean driver and DTS changes can go through separate trees, i.e. > PCI and arm-soc, without introducing regressions on either tree? > Or does the patch series needs to go in as a whole? Should be as a whole. The driver base on the dts. Or else, the driver would not found the 'aer' point. Thanks! Po > > Shawn
RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Shawn, > -Original Message- > From: Shawn Guo [mailto:shawn...@kernel.org] > Sent: Tuesday, September 20, 2016 8:39 PM > To: Po Liu > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd > Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali > Karicheri; Bjorn Helgaas; Mingkai Hu > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none > MSI/MSI-X/INTx mode > > On Sun, Sep 18, 2016 at 03:37:27AM +, Po Liu wrote: > > Hi Shawn, > > > > > > > -Original Message- > > > From: Shawn Guo [mailto:shawn...@kernel.org] > > > Sent: Sunday, September 18, 2016 8:52 AM > > > To: Po Liu > > > Cc: linux-...@vger.kernel.org; > > > linux-arm-ker...@lists.infradead.org; > > > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; > > > Arnd Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; > > > Murali Karicheri; Bjorn Helgaas; Mingkai Hu > > > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with > > > none MSI/MSI-X/INTx mode > > > > > > On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote: > > > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC > mode. > > > > When chip support the aer interrupt with none MSI/MSI-X/INTx > > > mode, > maybe there is interrupt line for aer pme etc. Search the > > > interrupt > number in the fdt file. Then fixup the dev->irq with it. > > > > > > > > Signed-off-by: Po Liu > > > > > > Will the new kernel work with existing/old DTB? I'm trying to > > > understand the dependency between driver and DTS changes. > > > > Yes, We've never use name 'intr' before. So we remove it is ok. > > 'aer' is a dts name for researching it's true interrupt number by > kernel. This patch is first time to use name 'aer'. So it must be > compatible with existing/old DTB. > > Does that mean driver and DTS changes can go through separate trees, i.e. > PCI and arm-soc, without introducing regressions on either tree? > Or does the patch series needs to go in as a whole? Should be as a whole. The driver base on the dts. Or else, the driver would not found the 'aer' point. Thanks! Po > > Shawn
RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
Hi Bjorn,
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Wednesday, September 21, 2016 4:47 AM
> To: Po Liu
> Cc: Roy Zang; Arnd Bergmann; devicet...@vger.kernel.org; Marc Zyngier;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Stuart Yoder;
> M.H. Lian; Murali Karicheri; Mingkai Hu; Bjorn Helgaas; Leo Li; Shawn
> Guo; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>
> On Mon, Aug 22, 2016 at 10:09:18AM +, Po Liu wrote:
> > Hi Bjorn,
> >
> > Sorry for late reply.
> >
> > I checked the updated kernel with Dongdong mentioned ACPI patch which
> was truly affected my quirk patch uploaded. So I suppose the quirk patch
> is not qualify to fix the bug.
>
> I don't understand what you're saying here.
>
> The quirk worked on your machine. It apparently didn't work on
> Dongdong's machine because of_irq_parse_and_map_pci() is run after the
> quirk in this path:
>
>pci_device_probe
> pcibios_alloc_irq # arm64
>dev->irq = of_irq_parse_and_map_pci
>
> and of_irq_parse_and_map_pci() returned zero, probably because
> of_irq_parse_pci() failed. My guess is that the reason it works on your
> machine but not Dongdong's is that your DTs are different such that
> of_irq_parse_pci() works for you but not for Dongdong.
>
> I think the idea of of_irq_parse_and_map_pci() is to set up a device's
> INTx line. But that doesn't quite apply here because your device
> doesn't actually *use* INTx. So I don't know why of_irq_parse_pci()
> works for you. Maybe that's a symptom of a problem in your DT.
>
> Or maybe you're saying that the quirk *didn't* work on your machine when
> you tested it in a kernel that included d8ed75d59332 ("ARM64:
> PCI: ACPI support for legacy IRQs parsing and consolidation with DT
> code").
Yes, this point is what I mean. After this patch my quirk patch would not work.
Since I discussed with Dongdong, the patches d8ed75d59332 ACPI related were not
be merged yet.
> But that doesn't make sense either, because prior to
> d8ed75d59332, we *always* set
>
>dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
>
> and after the patch we only do it if "acpi_disabled". I guess I just
> don't understand what you're saying.
Before the patch merged. pcibios_add_device()(which run the ->irq =
of_irq_parse_and_map_pci(dev, 0, 0);) was loaded before the
pci_fixup_device(pci_fixup_final).
But after the patch d8ed75d59332("ARM64: PCI: ACPI support for legacy IRQs
parsing and consolidation with DT code") merged, the
pci_fixup_device(pci_fixup_final) run BEFORE the pcibios_alloc_irq()(which run
the ->irq = of_irq_parse_and_map_pci(dev, 0, 0);). So the dev->irq were
overwhelm by the pcibios_alloc_irq().
When I test, the acpi_disabled is '1' although my kernel config default is
CONFIG_ACPI=y. And no setting in the uboot with apci=xxx. But this is another
issue, I didn't deep to check it.
>
> > I were keep thinking what your "explicitly checking for a root port
> device" meaning. Do you mean I should upload again the first version
> patch which fix it in the portdrv_core.c ? I would upload again if yes.
>
> No, I did not mean you should go back to the first version of the patch.
> If we *can* do this in a quirk, I think that would be much better than
> doing it in the PCIe port driver. I meant that Dongdong's suggestion of
> adding this:
>
>if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
> return;
>
> to your quirk made sense to me.
If the quirk patch could make workaround. It should be the better way.
Po Liu
>
> > > -Original Message-
> > > From: Bjorn Helgaas [mailto:helg...@kernel.org]
> > > Sent: Saturday, July 30, 2016 6:42 AM
> > > To: Po Liu
> > > Cc: linux-...@vger.kernel.org;
> > > linux-arm-ker...@lists.infradead.org;
> > > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang;
> > > Arnd Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan
> > > Lian; Murali Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> > > Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
> > >
> > > On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
> > > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
> mode.
> > > > When chip support the aer interrupt with none MSI/MSI-X/INTx
> > > mode, > maybe there is interrupt line for aer pme etc. Search the
> > > interrupt > number
RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
Hi Bjorn,
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Wednesday, September 21, 2016 4:47 AM
> To: Po Liu
> Cc: Roy Zang; Arnd Bergmann; devicet...@vger.kernel.org; Marc Zyngier;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Stuart Yoder;
> M.H. Lian; Murali Karicheri; Mingkai Hu; Bjorn Helgaas; Leo Li; Shawn
> Guo; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>
> On Mon, Aug 22, 2016 at 10:09:18AM +, Po Liu wrote:
> > Hi Bjorn,
> >
> > Sorry for late reply.
> >
> > I checked the updated kernel with Dongdong mentioned ACPI patch which
> was truly affected my quirk patch uploaded. So I suppose the quirk patch
> is not qualify to fix the bug.
>
> I don't understand what you're saying here.
>
> The quirk worked on your machine. It apparently didn't work on
> Dongdong's machine because of_irq_parse_and_map_pci() is run after the
> quirk in this path:
>
>pci_device_probe
> pcibios_alloc_irq # arm64
>dev->irq = of_irq_parse_and_map_pci
>
> and of_irq_parse_and_map_pci() returned zero, probably because
> of_irq_parse_pci() failed. My guess is that the reason it works on your
> machine but not Dongdong's is that your DTs are different such that
> of_irq_parse_pci() works for you but not for Dongdong.
>
> I think the idea of of_irq_parse_and_map_pci() is to set up a device's
> INTx line. But that doesn't quite apply here because your device
> doesn't actually *use* INTx. So I don't know why of_irq_parse_pci()
> works for you. Maybe that's a symptom of a problem in your DT.
>
> Or maybe you're saying that the quirk *didn't* work on your machine when
> you tested it in a kernel that included d8ed75d59332 ("ARM64:
> PCI: ACPI support for legacy IRQs parsing and consolidation with DT
> code").
Yes, this point is what I mean. After this patch my quirk patch would not work.
Since I discussed with Dongdong, the patches d8ed75d59332 ACPI related were not
be merged yet.
> But that doesn't make sense either, because prior to
> d8ed75d59332, we *always* set
>
>dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
>
> and after the patch we only do it if "acpi_disabled". I guess I just
> don't understand what you're saying.
Before the patch merged. pcibios_add_device()(which run the ->irq =
of_irq_parse_and_map_pci(dev, 0, 0);) was loaded before the
pci_fixup_device(pci_fixup_final).
But after the patch d8ed75d59332("ARM64: PCI: ACPI support for legacy IRQs
parsing and consolidation with DT code") merged, the
pci_fixup_device(pci_fixup_final) run BEFORE the pcibios_alloc_irq()(which run
the ->irq = of_irq_parse_and_map_pci(dev, 0, 0);). So the dev->irq were
overwhelm by the pcibios_alloc_irq().
When I test, the acpi_disabled is '1' although my kernel config default is
CONFIG_ACPI=y. And no setting in the uboot with apci=xxx. But this is another
issue, I didn't deep to check it.
>
> > I were keep thinking what your "explicitly checking for a root port
> device" meaning. Do you mean I should upload again the first version
> patch which fix it in the portdrv_core.c ? I would upload again if yes.
>
> No, I did not mean you should go back to the first version of the patch.
> If we *can* do this in a quirk, I think that would be much better than
> doing it in the PCIe port driver. I meant that Dongdong's suggestion of
> adding this:
>
>if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
> return;
>
> to your quirk made sense to me.
If the quirk patch could make workaround. It should be the better way.
Po Liu
>
> > > -Original Message-
> > > From: Bjorn Helgaas [mailto:helg...@kernel.org]
> > > Sent: Saturday, July 30, 2016 6:42 AM
> > > To: Po Liu
> > > Cc: linux-...@vger.kernel.org;
> > > linux-arm-ker...@lists.infradead.org;
> > > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang;
> > > Arnd Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan
> > > Lian; Murali Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> > > Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
> > >
> > > On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
> > > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
> mode.
> > > > When chip support the aer interrupt with none MSI/MSI-X/INTx
> > > mode, > maybe there is interrupt line for aer pme etc. Search the
> > > interru
RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Shawn,
> -Original Message-
> From: Shawn Guo [mailto:shawn...@kernel.org]
> Sent: Sunday, September 18, 2016 8:52 AM
> To: Po Liu
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd
> Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
> Karicheri; Bjorn Helgaas; Mingkai Hu
> Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
> MSI/MSI-X/INTx mode
>
> On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu <po@nxp.com>
>
> Will the new kernel work with existing/old DTB? I'm trying to
> understand the dependency between driver and DTS changes.
Yes, We've never use name 'intr' before. So we remove it is ok.
'aer' is a dts name for researching it's true interrupt number by kernel. This
patch is first time to use name 'aer'. So it must be compatible with
existing/old DTB.
>
> Shawn
>
> > ---
> > changes for v5:
> >- Add clear 'aer' interrup-names description
> >
> > .../devicetree/bindings/pci/layerscape-pci.txt | 11 +---
> > drivers/pci/pcie/portdrv_core.c| 31
> +++---
> > 2 files changed, 35 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 41e9f55..101d0a7 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -18,8 +18,10 @@ Required properties:
> > - reg: base addresses and lengths of the PCIe controller
> > - interrupts: A list of interrupt outputs of the controller. Must
> contain an
> >entry for each entry in the interrupt-names property.
> > -- interrupt-names: Must include the following entries:
> > - "intr": The interrupt that is asserted for controller interrupts
> > +- interrupt-names: It may be include the following entries:
> > + "aer": The interrupt that is asserted for aer interrupt
> > + "pme": The interrupt that is asserted for pme interrupt
> > + ..
> > - fsl,pcie-scfg: Must include two entries.
> >The first entry must be a link to the SCFG device node
> >The second entry must be '0' or '1' based on physical PCIe
> controller index.
> > @@ -35,8 +37,9 @@ Example:
> >reg = <0x00 0x0340 0x0 0x0001 /* controller
> registers */
> > 0x40 0x 0x0 0x2000>; /* configuration
> space */
> >reg-names = "regs", "config";
> > - interrupts = ; /*
> controller interrupt */
> > - interrupt-names = "intr";
> > + interrupts = , /* aer
> interrupt */
> > + ; /* pme interrupt */
> > + interrupt-names = "aer", "pme";
> >fsl,pcie-scfg = < 0>;
> >#address-cells = <3>;
> >#size-cells = <2>;
> > diff --git a/drivers/pci/pcie/portdrv_core.c
> > b/drivers/pci/pcie/portdrv_core.c index e9270b4..7c4943d 100644
> > --- a/drivers/pci/pcie/portdrv_core.c
> > +++ b/drivers/pci/pcie/portdrv_core.c
> > @@ -16,6 +16,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include "../pci.h"
> > #include "portdrv.h"
> > @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev
> > *dev, int *vectors, int mask) static int init_service_irqs(struct
> > pci_dev *dev, int *irqs, int mask) {
> >int i, irq = -1;
> > + int ret;
> > + struct device_node *np = NULL;
> > +
> > + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> > + irqs[i] = 0;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * request irq for aer
> > + */
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> > + (mask
RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Shawn,
> -Original Message-
> From: Shawn Guo [mailto:shawn...@kernel.org]
> Sent: Sunday, September 18, 2016 8:52 AM
> To: Po Liu
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd
> Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
> Karicheri; Bjorn Helgaas; Mingkai Hu
> Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
> MSI/MSI-X/INTx mode
>
> On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu
>
> Will the new kernel work with existing/old DTB? I'm trying to
> understand the dependency between driver and DTS changes.
Yes, We've never use name 'intr' before. So we remove it is ok.
'aer' is a dts name for researching it's true interrupt number by kernel. This
patch is first time to use name 'aer'. So it must be compatible with
existing/old DTB.
>
> Shawn
>
> > ---
> > changes for v5:
> >- Add clear 'aer' interrup-names description
> >
> > .../devicetree/bindings/pci/layerscape-pci.txt | 11 +---
> > drivers/pci/pcie/portdrv_core.c| 31
> +++---
> > 2 files changed, 35 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 41e9f55..101d0a7 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -18,8 +18,10 @@ Required properties:
> > - reg: base addresses and lengths of the PCIe controller
> > - interrupts: A list of interrupt outputs of the controller. Must
> contain an
> >entry for each entry in the interrupt-names property.
> > -- interrupt-names: Must include the following entries:
> > - "intr": The interrupt that is asserted for controller interrupts
> > +- interrupt-names: It may be include the following entries:
> > + "aer": The interrupt that is asserted for aer interrupt
> > + "pme": The interrupt that is asserted for pme interrupt
> > + ..
> > - fsl,pcie-scfg: Must include two entries.
> >The first entry must be a link to the SCFG device node
> >The second entry must be '0' or '1' based on physical PCIe
> controller index.
> > @@ -35,8 +37,9 @@ Example:
> >reg = <0x00 0x0340 0x0 0x0001 /* controller
> registers */
> > 0x40 0x 0x0 0x2000>; /* configuration
> space */
> >reg-names = "regs", "config";
> > - interrupts = ; /*
> controller interrupt */
> > - interrupt-names = "intr";
> > + interrupts = , /* aer
> interrupt */
> > + ; /* pme interrupt */
> > + interrupt-names = "aer", "pme";
> >fsl,pcie-scfg = < 0>;
> >#address-cells = <3>;
> >#size-cells = <2>;
> > diff --git a/drivers/pci/pcie/portdrv_core.c
> > b/drivers/pci/pcie/portdrv_core.c index e9270b4..7c4943d 100644
> > --- a/drivers/pci/pcie/portdrv_core.c
> > +++ b/drivers/pci/pcie/portdrv_core.c
> > @@ -16,6 +16,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include "../pci.h"
> > #include "portdrv.h"
> > @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev
> > *dev, int *vectors, int mask) static int init_service_irqs(struct
> > pci_dev *dev, int *irqs, int mask) {
> >int i, irq = -1;
> > + int ret;
> > + struct device_node *np = NULL;
> > +
> > + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> > + irqs[i] = 0;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * request irq for aer
> > + */
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> > + (mask &
RE: [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
Hi Bjorn, Shawn, Rob, Thanks for reply. I'll upload new patches: - separate the patches with arm and arm64 dts for new version. - Modify the binding comments to make it clear for explain the 'aer' property. Best regards, Liu Po -Original Message- From: Bjorn Helgaas [mailto:helg...@kernel.org] Sent: Tuesday, September 13, 2016 6:14 AM To: Po Liu Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Vincent Hu; Stuart Yoder; Leo Li; Arnd Bergmann; M.H. Lian; Murali Karicheri Subject: Re: [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts On Wed, Aug 31, 2016 at 02:37:21PM +0800, Po Liu wrote: > NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using > interrupt line independently. This patch add a "aer" > interrupt-names for aer interrupt. > With the interrupt-names "aer", code could probe aer interrupt line > for pcie root port, replace the aer interrupt service irq. > This is intend to fixup the Layerscape platforms which aer interrupt > was not MSI/MSI-X/INTx, but using interrupt line independently. > > Signed-off-by: Po Liu <po@nxp.com> Rob and Shawn had comments here, and I'm not sure they ever got resolved. > --- > changes for V4: > - Add comments explain why to add this patch > - Move the binding changes to pci code patch > > arch/arm/boot/dts/ls1021a.dtsi | 6 -- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 > +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | > 16 > 3 files changed, 21 insertions(+), 19 deletions(-) > > diff --git a/arch/arm/boot/dts/ls1021a.dtsi > b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..443e50b 100644 > --- a/arch/arm/boot/dts/ls1021a.dtsi > +++ b/arch/arm/boot/dts/ls1021a.dtsi > @@ -634,7 +634,8 @@ > reg = <0x00 0x0340 0x0 0x0001 /* controller > registers */ > 0x40 0x 0x0 0x2000>; /* > configuration space */ > reg-names = "regs", "config"; > - interrupts = ; /* > controller interrupt */ > + interrupts = ; /* aer > interrupt */ > + interrupt-names = "aer"; > fsl,pcie-scfg = < 0>; > #address-cells = <3>; > #size-cells = <2>; > @@ -657,7 +658,8 @@ > reg = <0x00 0x0350 0x0 0x0001 /* controller > registers */ > 0x48 0x 0x0 0x2000>; /* > configuration space */ > reg-names = "regs", "config"; > - interrupts = ; > + interrupts = ; /* aer > interrupt */ > + interrupt-names = "aer"; > fsl,pcie-scfg = < 1>; > #address-cells = <3>; > #size-cells = <2>; > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > index e669fbd..654071d 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > @@ -527,9 +527,9 @@ > reg = <0x00 0x0340 0x0 0x0010 /* controller > registers */ > 0x40 0x 0x0 0x2000>; /* > configuration space */ > reg-names = "regs", "config"; > - interrupts = <0 118 0x4>, /* controller interrupt */ > - <0 117 0x4>; /* PME interrupt */ > - interrupt-names = "intr", "pme"; > + interrupts = <0 117 0x4>, /* PME interrupt */ > + <0 118 0x4>; /* aer interrupt */ > + interrupt-names = "pme", "aer"; > #address-cells = <3>; > #size-cells = <2>; > device_type = "pci"; > @@ -552,9 +552,9 @@ > reg = <0x00 0x0350 0x0 0x0010 /* controller > registers */ > 0x48 0x 0x0 0x2000>; /* > configuration space */ > reg-names = "regs", "config"; > - interrupts = <0 128 0x4>, > - <0 127 0x4>; > -
RE: [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
Hi Bjorn, Shawn, Rob, Thanks for reply. I'll upload new patches: - separate the patches with arm and arm64 dts for new version. - Modify the binding comments to make it clear for explain the 'aer' property. Best regards, Liu Po -Original Message- From: Bjorn Helgaas [mailto:helg...@kernel.org] Sent: Tuesday, September 13, 2016 6:14 AM To: Po Liu Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Vincent Hu; Stuart Yoder; Leo Li; Arnd Bergmann; M.H. Lian; Murali Karicheri Subject: Re: [PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts On Wed, Aug 31, 2016 at 02:37:21PM +0800, Po Liu wrote: > NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using > interrupt line independently. This patch add a "aer" > interrupt-names for aer interrupt. > With the interrupt-names "aer", code could probe aer interrupt line > for pcie root port, replace the aer interrupt service irq. > This is intend to fixup the Layerscape platforms which aer interrupt > was not MSI/MSI-X/INTx, but using interrupt line independently. > > Signed-off-by: Po Liu Rob and Shawn had comments here, and I'm not sure they ever got resolved. > --- > changes for V4: > - Add comments explain why to add this patch > - Move the binding changes to pci code patch > > arch/arm/boot/dts/ls1021a.dtsi | 6 -- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 > +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | > 16 > 3 files changed, 21 insertions(+), 19 deletions(-) > > diff --git a/arch/arm/boot/dts/ls1021a.dtsi > b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..443e50b 100644 > --- a/arch/arm/boot/dts/ls1021a.dtsi > +++ b/arch/arm/boot/dts/ls1021a.dtsi > @@ -634,7 +634,8 @@ > reg = <0x00 0x0340 0x0 0x0001 /* controller > registers */ > 0x40 0x 0x0 0x2000>; /* > configuration space */ > reg-names = "regs", "config"; > - interrupts = ; /* > controller interrupt */ > + interrupts = ; /* aer > interrupt */ > + interrupt-names = "aer"; > fsl,pcie-scfg = < 0>; > #address-cells = <3>; > #size-cells = <2>; > @@ -657,7 +658,8 @@ > reg = <0x00 0x0350 0x0 0x0001 /* controller > registers */ > 0x48 0x 0x0 0x2000>; /* > configuration space */ > reg-names = "regs", "config"; > - interrupts = ; > + interrupts = ; /* aer > interrupt */ > + interrupt-names = "aer"; > fsl,pcie-scfg = < 1>; > #address-cells = <3>; > #size-cells = <2>; > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > index e669fbd..654071d 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > @@ -527,9 +527,9 @@ > reg = <0x00 0x0340 0x0 0x0010 /* controller > registers */ > 0x40 0x 0x0 0x2000>; /* > configuration space */ > reg-names = "regs", "config"; > - interrupts = <0 118 0x4>, /* controller interrupt */ > - <0 117 0x4>; /* PME interrupt */ > - interrupt-names = "intr", "pme"; > + interrupts = <0 117 0x4>, /* PME interrupt */ > + <0 118 0x4>; /* aer interrupt */ > + interrupt-names = "pme", "aer"; > #address-cells = <3>; > #size-cells = <2>; > device_type = "pci"; > @@ -552,9 +552,9 @@ > reg = <0x00 0x0350 0x0 0x0010 /* controller > registers */ > 0x48 0x 0x0 0x2000>; /* > configuration space */ > reg-names = "regs", "config"; > - interrupts = <0 128 0x4>, > - <0 127 0x4>; > - interrup
[PATCH v5 1/3] arm/dts: add pcie aer interrupt-name property in the dts
NXP arm aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. With the interrupt-names "aer", code could probe aer interrupt line for pcie root port, replace the aer interrupt service irq. This patch is intend to fixup the Layerscape platforms which aer interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Signed-off-by: Po Liu <po@nxp.com> --- changes for v5: - Seperate arm arm64 dts changes arch/arm/boot/dts/ls1021a.dtsi | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..443e50b 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -634,7 +634,8 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -657,7 +658,8 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; -- 2.1.0.27.g96db324
[PATCH v5 1/3] arm/dts: add pcie aer interrupt-name property in the dts
NXP arm aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. With the interrupt-names "aer", code could probe aer interrupt line for pcie root port, replace the aer interrupt service irq. This patch is intend to fixup the Layerscape platforms which aer interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Signed-off-by: Po Liu --- changes for v5: - Seperate arm arm64 dts changes arch/arm/boot/dts/ls1021a.dtsi | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..443e50b 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -634,7 +634,8 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -657,7 +658,8 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; -- 2.1.0.27.g96db324
[PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu <po@nxp.com>
---
changes for v5:
- Add clear 'aer' interrup-names description
.../devicetree/bindings/pci/layerscape-pci.txt | 11 +---
drivers/pci/pcie/portdrv_core.c| 31 +++---
2 files changed, 35 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..101d0a7 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -18,8 +18,10 @@ Required properties:
- reg: base addresses and lengths of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
- "intr": The interrupt that is asserted for controller interrupts
+- interrupt-names: It may be include the following entries:
+ "aer": The interrupt that is asserted for aer interrupt
+ "pme": The interrupt that is asserted for pme interrupt
+ ..
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -35,8 +37,9 @@ Example:
reg = <0x00 0x0340 0x0 0x0001 /* controller registers
*/
0x40 0x 0x0 0x2000>; /* configuration space
*/
reg-names = "regs", "config";
- interrupts = ; /* controller
interrupt */
- interrupt-names = "intr";
+ interrupts = , /* aer
interrupt */
+ ; /* pme interrupt */
+ interrupt-names = "aer", "pme";
fsl,pcie-scfg = < 0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e9270b4..7c4943d 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include "../pci.h"
#include "portdrv.h"
@@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int
*vectors, int mask)
static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
{
int i, irq = -1;
+ int ret;
+ struct device_node *np = NULL;
+
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+ irqs[i] = 0;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+* request irq for aer
+*/
+ if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
+ (mask & PCIE_PORT_SERVICE_PME)) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+ if (dev->irq)
+ irq = dev->irq;
+ goto no_msi;
+ }
+ }
/*
* If MSI cannot be used for PCIe PME or hotplug, we have to use
@@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int
*irqs, int mask)
irq = dev->irq;
no_msi:
- for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
- irqs[i] = irq;
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
+ if (!irqs[i])
+ irqs[i] = irq;
+ }
irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
- if (irq < 0)
+ if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
return -ENODEV;
return 0;
}
--
2.1.0.27.g96db324
[PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu
---
changes for v5:
- Add clear 'aer' interrup-names description
.../devicetree/bindings/pci/layerscape-pci.txt | 11 +---
drivers/pci/pcie/portdrv_core.c| 31 +++---
2 files changed, 35 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..101d0a7 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -18,8 +18,10 @@ Required properties:
- reg: base addresses and lengths of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
- "intr": The interrupt that is asserted for controller interrupts
+- interrupt-names: It may be include the following entries:
+ "aer": The interrupt that is asserted for aer interrupt
+ "pme": The interrupt that is asserted for pme interrupt
+ ..
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -35,8 +37,9 @@ Example:
reg = <0x00 0x0340 0x0 0x0001 /* controller registers
*/
0x40 0x 0x0 0x2000>; /* configuration space
*/
reg-names = "regs", "config";
- interrupts = ; /* controller
interrupt */
- interrupt-names = "intr";
+ interrupts = , /* aer
interrupt */
+ ; /* pme interrupt */
+ interrupt-names = "aer", "pme";
fsl,pcie-scfg = < 0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e9270b4..7c4943d 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include "../pci.h"
#include "portdrv.h"
@@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int
*vectors, int mask)
static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
{
int i, irq = -1;
+ int ret;
+ struct device_node *np = NULL;
+
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+ irqs[i] = 0;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+* request irq for aer
+*/
+ if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
+ (mask & PCIE_PORT_SERVICE_PME)) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+ if (dev->irq)
+ irq = dev->irq;
+ goto no_msi;
+ }
+ }
/*
* If MSI cannot be used for PCIe PME or hotplug, we have to use
@@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int
*irqs, int mask)
irq = dev->irq;
no_msi:
- for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
- irqs[i] = irq;
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
+ if (!irqs[i])
+ irqs[i] = irq;
+ }
irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
- if (irq < 0)
+ if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
return -ENODEV;
return 0;
}
--
2.1.0.27.g96db324
[PATCH v5 2/3] arm64/dts: add pcie aer interrupt-name property in the dts
Some platforms(NXP Layerscape for example) aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. With the interrupt-names "aer", code could probe aer interrupt line for pcie root port, replace the aer interrupt service irq. This is intend to fixup the Layerscape platforms which aer interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Signed-off-by: Po Liu <po@nxp.com> --- changes for v5: - Seperate arm and arm64 dts modification into two patches arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index e669fbd..654071d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -527,9 +527,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -552,9 +552,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +<0 128 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -577,9 +577,9 @@ reg = <0x00 0x0360 0x0 0x0010 /* controller registers */ 0x50 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 162 0x4>, -<0 161 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 161 0x4>, +<0 162 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 21023a3..58844e8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -583,8 +583,8 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x10 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 108 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -607,8 +607,8 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x12 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 113 0x4>; /* Level high type */ - interrupt-names = "intr"; +
[PATCH v5 2/3] arm64/dts: add pcie aer interrupt-name property in the dts
Some platforms(NXP Layerscape for example) aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. With the interrupt-names "aer", code could probe aer interrupt line for pcie root port, replace the aer interrupt service irq. This is intend to fixup the Layerscape platforms which aer interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Signed-off-by: Po Liu --- changes for v5: - Seperate arm and arm64 dts modification into two patches arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index e669fbd..654071d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -527,9 +527,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -552,9 +552,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +<0 128 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -577,9 +577,9 @@ reg = <0x00 0x0360 0x0 0x0010 /* controller registers */ 0x50 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 162 0x4>, -<0 161 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 161 0x4>, +<0 162 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 21023a3..58844e8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -583,8 +583,8 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x10 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 108 0x4>; /* aer interrupt */ + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -607,8 +607,8 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x12 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 113 0x4>; /* Level high type */ - interrupt-names = "intr"; + inter
RE: [PATCH v4 2/2] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Rob, Best regards, Liu Po > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Friday, September 02, 2016 11:17 PM > To: Po Liu > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas; > Shawn Guo; Marc Zyngier; Roy Zang; Mingkai Hu; Stuart Yoder; Yang-Leo Li; > Arnd Bergmann; Minghuan Lian; Murali Karicheri > Subject: Re: [PATCH v4 2/2] pci:aer: add support aer interrupt with none > MSI/MSI-X/INTx mode > > On Wed, Aug 31, 2016 at 02:37:22PM +0800, Po Liu wrote: > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode. > > When chip support the aer interrupt with none MSI/MSI-X/INTx mode, > > maybe there is interrupt line for aer pme etc. Search the interrupt > > number in the fdt file. Then fixup the dev->irq with it. > > > > Signed-off-by: Po Liu <po@nxp.com> > > --- > > Changes for v4: > >- re-use the patch changes in the root port driver; > >- add binding information; > > > > .../devicetree/bindings/pci/layerscape-pci.txt | 4 +-- > > drivers/pci/pcie/portdrv_core.c| 31 > +++--- > > 2 files changed, 30 insertions(+), 5 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > index 41e9f55..1dfb1da 100644 > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > @@ -19,7 +19,7 @@ Required properties: > > - interrupts: A list of interrupt outputs of the controller. Must > contain an > >entry for each entry in the interrupt-names property. > > - interrupt-names: Must include the following entries: > > - "intr": The interrupt that is asserted for controller interrupts > > + "aer": The interrupt that is asserted for aer interrupts > > You can't just change this. That breaks compatibility with old dts files. > Plus, it is just a name. Why does it even matter? Not to mention having > the name for a single irq is a bit pointless. Sorry, this binding comments maybe not clear. "aer" is just one of the interrupt names from host controller. There are "aer" "pme" and so on for further applications. This patch is to fix the Layerscape owning independent aer irq issue. So the 'aer' is used for this patch. The 'intr' will never be used, so removed. I may remove the 'must include' for mis-understanding. Thanks! Po Liu > > Rob
RE: [PATCH v4 2/2] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Rob, Best regards, Liu Po > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Friday, September 02, 2016 11:17 PM > To: Po Liu > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas; > Shawn Guo; Marc Zyngier; Roy Zang; Mingkai Hu; Stuart Yoder; Yang-Leo Li; > Arnd Bergmann; Minghuan Lian; Murali Karicheri > Subject: Re: [PATCH v4 2/2] pci:aer: add support aer interrupt with none > MSI/MSI-X/INTx mode > > On Wed, Aug 31, 2016 at 02:37:22PM +0800, Po Liu wrote: > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode. > > When chip support the aer interrupt with none MSI/MSI-X/INTx mode, > > maybe there is interrupt line for aer pme etc. Search the interrupt > > number in the fdt file. Then fixup the dev->irq with it. > > > > Signed-off-by: Po Liu > > --- > > Changes for v4: > >- re-use the patch changes in the root port driver; > >- add binding information; > > > > .../devicetree/bindings/pci/layerscape-pci.txt | 4 +-- > > drivers/pci/pcie/portdrv_core.c| 31 > +++--- > > 2 files changed, 30 insertions(+), 5 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > index 41e9f55..1dfb1da 100644 > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > @@ -19,7 +19,7 @@ Required properties: > > - interrupts: A list of interrupt outputs of the controller. Must > contain an > >entry for each entry in the interrupt-names property. > > - interrupt-names: Must include the following entries: > > - "intr": The interrupt that is asserted for controller interrupts > > + "aer": The interrupt that is asserted for aer interrupts > > You can't just change this. That breaks compatibility with old dts files. > Plus, it is just a name. Why does it even matter? Not to mention having > the name for a single irq is a bit pointless. Sorry, this binding comments maybe not clear. "aer" is just one of the interrupt names from host controller. There are "aer" "pme" and so on for further applications. This patch is to fix the Layerscape owning independent aer irq issue. So the 'aer' is used for this patch. The 'intr' will never be used, so removed. I may remove the 'must include' for mis-understanding. Thanks! Po Liu > > Rob
[PATCH v4 2/2] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu <po@nxp.com>
---
Changes for v4:
- re-use the patch changes in the root port driver;
- add binding information;
.../devicetree/bindings/pci/layerscape-pci.txt | 4 +--
drivers/pci/pcie/portdrv_core.c| 31 +++---
2 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..1dfb1da 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -19,7 +19,7 @@ Required properties:
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
- "intr": The interrupt that is asserted for controller interrupts
+ "aer": The interrupt that is asserted for aer interrupts
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -36,7 +36,7 @@ Example:
0x40 0x 0x0 0x2000>; /* configuration space
*/
reg-names = "regs", "config";
interrupts = ; /* controller
interrupt */
- interrupt-names = "intr";
+ interrupt-names = "aer";
fsl,pcie-scfg = < 0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e9270b4..7c4943d 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include "../pci.h"
#include "portdrv.h"
@@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int
*vectors, int mask)
static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
{
int i, irq = -1;
+ int ret;
+ struct device_node *np = NULL;
+
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+ irqs[i] = 0;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+* request irq for aer
+*/
+ if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
+ (mask & PCIE_PORT_SERVICE_PME)) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+ if (dev->irq)
+ irq = dev->irq;
+ goto no_msi;
+ }
+ }
/*
* If MSI cannot be used for PCIe PME or hotplug, we have to use
@@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int
*irqs, int mask)
irq = dev->irq;
no_msi:
- for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
- irqs[i] = irq;
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
+ if (!irqs[i])
+ irqs[i] = irq;
+ }
irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
- if (irq < 0)
+ if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
return -ENODEV;
return 0;
}
--
2.1.0.27.g96db324
[PATCH v4 2/2] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu
---
Changes for v4:
- re-use the patch changes in the root port driver;
- add binding information;
.../devicetree/bindings/pci/layerscape-pci.txt | 4 +--
drivers/pci/pcie/portdrv_core.c| 31 +++---
2 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..1dfb1da 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -19,7 +19,7 @@ Required properties:
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
- "intr": The interrupt that is asserted for controller interrupts
+ "aer": The interrupt that is asserted for aer interrupts
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -36,7 +36,7 @@ Example:
0x40 0x 0x0 0x2000>; /* configuration space
*/
reg-names = "regs", "config";
interrupts = ; /* controller
interrupt */
- interrupt-names = "intr";
+ interrupt-names = "aer";
fsl,pcie-scfg = < 0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e9270b4..7c4943d 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include "../pci.h"
#include "portdrv.h"
@@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int
*vectors, int mask)
static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
{
int i, irq = -1;
+ int ret;
+ struct device_node *np = NULL;
+
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+ irqs[i] = 0;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+* request irq for aer
+*/
+ if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
+ (mask & PCIE_PORT_SERVICE_PME)) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
+ if (dev->irq)
+ irq = dev->irq;
+ goto no_msi;
+ }
+ }
/*
* If MSI cannot be used for PCIe PME or hotplug, we have to use
@@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int
*irqs, int mask)
irq = dev->irq;
no_msi:
- for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
- irqs[i] = irq;
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
+ if (!irqs[i])
+ irqs[i] = irq;
+ }
irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
- if (irq < 0)
+ if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
return -ENODEV;
return 0;
}
--
2.1.0.27.g96db324
[PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. With the interrupt-names "aer", code could probe aer interrupt line for pcie root port, replace the aer interrupt service irq. This is intend to fixup the Layerscape platforms which aer interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Signed-off-by: Po Liu <po@nxp.com> --- changes for V4: - Add comments explain why to add this patch - Move the binding changes to pci code patch arch/arm/boot/dts/ls1021a.dtsi | 6 -- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..443e50b 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -634,7 +634,8 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -657,7 +658,8 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index e669fbd..654071d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -527,9 +527,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -552,9 +552,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +<0 128 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -577,9 +577,9 @@ reg = <0x00 0x0360 0x0 0x0010 /* controller registers */ 0x50 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 162 0x4>, -<0 161 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 161 0x4>, +<0 162 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <
[PATCH v4 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. With the interrupt-names "aer", code could probe aer interrupt line for pcie root port, replace the aer interrupt service irq. This is intend to fixup the Layerscape platforms which aer interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Signed-off-by: Po Liu --- changes for V4: - Add comments explain why to add this patch - Move the binding changes to pci code patch arch/arm/boot/dts/ls1021a.dtsi | 6 -- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..443e50b 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -634,7 +634,8 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -657,7 +658,8 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index e669fbd..654071d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -527,9 +527,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -552,9 +552,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +<0 128 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -577,9 +577,9 @@ reg = <0x00 0x0360 0x0 0x0010 /* controller registers */ 0x50 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 162 0x4>, -<0 161 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 161 0x4>, +<0 162 0x4>; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>;
RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
Hi Bjorn,
Sorry for late reply.
I checked the updated kernel with Dongdong mentioned ACPI patch which was truly
affected my quirk patch uploaded. So I suppose the quirk patch is not qualify
to fix the bug.
I were keep thinking what your "explicitly checking for a root port device"
meaning. Do you mean I should upload again the first version patch which fix it
in the portdrv_core.c ? I would upload again if yes.
Thanks!
Best regards,
Liu Po
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Saturday, July 30, 2016 6:42 AM
> To: Po Liu
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd
> Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Murali
> Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>
> On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu <po@nxp.com>
>
> I'm not sure where we're at with this. Dongdong had some issue
> (possibly with a version of the quirk on a different platform?), and I
> think the suggestion of explicitly checking for a root port device was a
> good one.
>
> So please update and repost this for next cycle.
>
> > ---
> > changes for V3:
> >- Move to quirk;
> >- Only correct the irq in RC mode;
> >
> > drivers/pci/quirks.c | 29 +
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > ee72ebe..8b39cce 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -25,6 +25,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include /* isa_dma_bridge_buggy */
> > #include "pci.h"
> >
> > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> pci_dev *pdev)
> >}
> > }
> > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
> > quirk_intel_qat_vf_cap);
> > +
> > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * but use standalone irq. Read the device tree for the aer
> > + * interrupt number.
> > + */
> > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > + int ret;
> > + u8 header_type;
> > + struct device_node *np = NULL;
> > +
> > + /* Only for the RC mode device */
> > + pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
> > + if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> > + return;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + dev->no_msi = 1;
> > + dev->irq = ret;
> > + }
> > + }
> > +}
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> > +quirk_aer_interrupt);
> > --
> > 2.1.0.27.g96db324
> >
> >
> > ___
> > linux-arm-kernel mailing list
> > linux-arm-ker...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
Hi Bjorn,
Sorry for late reply.
I checked the updated kernel with Dongdong mentioned ACPI patch which was truly
affected my quirk patch uploaded. So I suppose the quirk patch is not qualify
to fix the bug.
I were keep thinking what your "explicitly checking for a root port device"
meaning. Do you mean I should upload again the first version patch which fix it
in the portdrv_core.c ? I would upload again if yes.
Thanks!
Best regards,
Liu Po
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Saturday, July 30, 2016 6:42 AM
> To: Po Liu
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd
> Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Murali
> Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>
> On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu
>
> I'm not sure where we're at with this. Dongdong had some issue
> (possibly with a version of the quirk on a different platform?), and I
> think the suggestion of explicitly checking for a root port device was a
> good one.
>
> So please update and repost this for next cycle.
>
> > ---
> > changes for V3:
> >- Move to quirk;
> >- Only correct the irq in RC mode;
> >
> > drivers/pci/quirks.c | 29 +
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > ee72ebe..8b39cce 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -25,6 +25,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include /* isa_dma_bridge_buggy */
> > #include "pci.h"
> >
> > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> pci_dev *pdev)
> >}
> > }
> > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
> > quirk_intel_qat_vf_cap);
> > +
> > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * but use standalone irq. Read the device tree for the aer
> > + * interrupt number.
> > + */
> > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > + int ret;
> > + u8 header_type;
> > + struct device_node *np = NULL;
> > +
> > + /* Only for the RC mode device */
> > + pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
> > + if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> > + return;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + dev->no_msi = 1;
> > + dev->irq = ret;
> > + }
> > + }
> > +}
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> > +quirk_aer_interrupt);
> > --
> > 2.1.0.27.g96db324
> >
> >
> > ___
> > linux-arm-kernel mailing list
> > linux-arm-ker...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
Hi Dongdong,
The patch were intend to fixup the NXP layerscape serial SOC and were tested ok.
I am not clear what platform are you trying to fix.
The problem on your board may be as below comments:
> -Original Message-
> From: Dongdong Liu [mailto:liudongdo...@huawei.com]
> Sent: Monday, July 04, 2016 4:44 PM
> To: Po Liu; linux-...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org
> Cc: Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang;
> Mingkai Hu; Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian;
> Murali Karicheri; Linuxarm
> Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>
> Hi Po
>
> I found a problem with the similar patch. as the below log.
>
> [4.287060] pci :80:00.0: quirk_aer_interrupt dev->irq 416
> [4.293778] pcieport :80:00.0: pci_device_probe in
> [4.299605] pcieport :80:00.0: of_irq_parse_pci() failed with
> rc=-22
> [4.307209] pcieport :80:00.0: init_service_irqs dev->irq 0
>
> The fucntions are called as below sequence.
> 1. quirk_aer_interrupt, get the aer dev->irq 416.
This code quirk_aer_interrupt() should be run at
pci_fixup_device(pci_fixup_final) which is in the pci_bus_add_devices()
> 2. pci_device_probe->of_irq_parse_pci, of_irq_parse_pci() failed, then
> dev->irq changed to 0.
pci_device_probe->of_irq_parse_pci which in the pci_scan_child_bus() run before
pci_bus_add_devices(). See dw_pcie_host_init().
Apparently , your quirk_aer_interrupt() is running before the dev->irq
assignment in the of_irq_parse_pci().
So make sure your configure the quirk_aer_interrupt() run in the FINAL stage in
the quirk.c OR check your host driver which you are using.
>
> So this patch could not work with aer.
>
> Thanks
> Dongdong
> 在 2016/6/14 16:24, Po Liu 写道:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu <po@nxp.com>
> > ---
> > changes for V3:
> >- Move to quirk;
> >- Only correct the irq in RC mode;
> >
> > drivers/pci/quirks.c | 29 +
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > ee72ebe..8b39cce 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -25,6 +25,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include /* isa_dma_bridge_buggy */
> > #include "pci.h"
> >
> > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> pci_dev *pdev)
> >}
> > }
> > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
> > quirk_intel_qat_vf_cap);
> > +
> > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * but use standalone irq. Read the device tree for the aer
> > + * interrupt number.
> > + */
> > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > + int ret;
> > + u8 header_type;
> > + struct device_node *np = NULL;
> > +
> > + /* Only for the RC mode device */
> > + pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
> > + if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> > + return;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + dev->no_msi = 1;
> > + dev->irq = ret;
> > + }
> > + }
> > +}
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> > +quirk_aer_interrupt);
> >
>
RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
Hi Dongdong,
The patch were intend to fixup the NXP layerscape serial SOC and were tested ok.
I am not clear what platform are you trying to fix.
The problem on your board may be as below comments:
> -Original Message-
> From: Dongdong Liu [mailto:liudongdo...@huawei.com]
> Sent: Monday, July 04, 2016 4:44 PM
> To: Po Liu; linux-...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org
> Cc: Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang;
> Mingkai Hu; Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian;
> Murali Karicheri; Linuxarm
> Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>
> Hi Po
>
> I found a problem with the similar patch. as the below log.
>
> [4.287060] pci :80:00.0: quirk_aer_interrupt dev->irq 416
> [4.293778] pcieport :80:00.0: pci_device_probe in
> [4.299605] pcieport :80:00.0: of_irq_parse_pci() failed with
> rc=-22
> [4.307209] pcieport :80:00.0: init_service_irqs dev->irq 0
>
> The fucntions are called as below sequence.
> 1. quirk_aer_interrupt, get the aer dev->irq 416.
This code quirk_aer_interrupt() should be run at
pci_fixup_device(pci_fixup_final) which is in the pci_bus_add_devices()
> 2. pci_device_probe->of_irq_parse_pci, of_irq_parse_pci() failed, then
> dev->irq changed to 0.
pci_device_probe->of_irq_parse_pci which in the pci_scan_child_bus() run before
pci_bus_add_devices(). See dw_pcie_host_init().
Apparently , your quirk_aer_interrupt() is running before the dev->irq
assignment in the of_irq_parse_pci().
So make sure your configure the quirk_aer_interrupt() run in the FINAL stage in
the quirk.c OR check your host driver which you are using.
>
> So this patch could not work with aer.
>
> Thanks
> Dongdong
> 在 2016/6/14 16:24, Po Liu 写道:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu
> > ---
> > changes for V3:
> >- Move to quirk;
> >- Only correct the irq in RC mode;
> >
> > drivers/pci/quirks.c | 29 +
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > ee72ebe..8b39cce 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -25,6 +25,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include /* isa_dma_bridge_buggy */
> > #include "pci.h"
> >
> > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> pci_dev *pdev)
> >}
> > }
> > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
> > quirk_intel_qat_vf_cap);
> > +
> > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * but use standalone irq. Read the device tree for the aer
> > + * interrupt number.
> > + */
> > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > + int ret;
> > + u8 header_type;
> > + struct device_node *np = NULL;
> > +
> > + /* Only for the RC mode device */
> > + pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
> > + if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> > + return;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + dev->no_msi = 1;
> > + dev->irq = ret;
> > + }
> > + }
> > +}
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> > +quirk_aer_interrupt);
> >
>
RE: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
Hi Bjorn,
So could we keep it in the pci/quirk.c ?
If yes, I would only move the binding description in the documentation into
this driver the next version.
> -Original Message-
> From: Po Liu
> Sent: Friday, June 17, 2016 11:31 AM
> To: 'Bjorn Helgaas'
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas;
> Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Mingkai Hu; Stuart Yoder;
> Yang-Leo Li; Arnd Bergmann; Minghuan Lian; Murali Karicheri
> Subject: RE: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
>
>
>
> > -Original Message-
> > From: Bjorn Helgaas [mailto:helg...@kernel.org]
> > Sent: Thursday, June 16, 2016 9:54 PM
> > To: Po Liu
> > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn
> > Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Mingkai Hu;
> > Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian; Murali
> > Karicheri
> > Subject: Re: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
> >
> > On Tue, Jun 14, 2016 at 02:12:27PM +0800, Po Liu wrote:
> > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
> mode.
> > > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > > maybe there is interrupt line for aer pme etc. Search the interrupt
> > > number in the fdt file. Then fixup the dev->irq with it.
> > >
> > > Signed-off-by: Po Liu <po@nxp.com> > --- > changes for V2:
> > > - Move to the quirk file
> > >
> > > drivers/pci/quirks.c | 23 +++ > 1 file
> > changed, 23 insertions(+) > > diff --git a/drivers/pci/quirks.c
> > b/drivers/pci/quirks.c index > ee72ebe..909d479 100644 > ---
> > a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c
> >
> > Is there any possibility of this part being used on different arches,
> > or will it only ever be on arm64 (or whatever it is)? If the latter,
> > it could go somewhere like arch/arm64/kernel/quirks.c (which doesn't
> > exist yet).
>
> NXP Layerscape1 is base on the arm 32bit design. Also need the fixup.
>
> >
> > > @@ -25,6 +25,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include/* isa_dma_bridge_buggy */
> > > #include "pci.h"
> > >
> > > @@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct
> > pci_dev *pdev)
> > > }
> > > }
> > > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, >
> > quirk_intel_qat_vf_cap); > + > +/* If root port doesn't support
> > MSI/MSI-X/INTx in RC mode, > + * but use standalone irq. Read the
> > device tree for the aer > + * interrupt number.
> > > + */
> > > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > > + int ret;
> > > + struct device_node *np = NULL;
> > > +
> > > + if (dev->bus->dev.of_node)
> > > + np = dev->bus->dev.of_node;
> > > +
> > > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > > + ret = of_irq_get_byname(np, "aer");
> > > + if (ret > 0) {
> > > + dev->no_msi = 1;
> > > + dev->irq = ret;
> > > + }
> > > + }
> >
> > What does this mean for the other PCIe services, e.g., PME? I guess
> > this makes the existing AER code work unchanged. But I thought PME
> > had a similar situation and was connected up to a different interrupt
> > than AER was.
>
> Yes, PME is similar, HP is not support. I think better to disable the
> PME service irq in the quirk.
> But seems it is no use because quirk fixup is only running in init phase
> time(except suspend, resume).
>
> >
> > > +}
> > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, >
> > +quirk_aer_interrupt); > -- > 2.1.0.27.g96db324 > > -- > To
> > unsubscribe from this list: send the line "unsubscribe linux-pci"
> > > in the body of a message to majord...@vger.kernel.org More
> > majordomo > info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
Hi Bjorn,
So could we keep it in the pci/quirk.c ?
If yes, I would only move the binding description in the documentation into
this driver the next version.
> -Original Message-
> From: Po Liu
> Sent: Friday, June 17, 2016 11:31 AM
> To: 'Bjorn Helgaas'
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas;
> Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Mingkai Hu; Stuart Yoder;
> Yang-Leo Li; Arnd Bergmann; Minghuan Lian; Murali Karicheri
> Subject: RE: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
>
>
>
> > -Original Message-
> > From: Bjorn Helgaas [mailto:helg...@kernel.org]
> > Sent: Thursday, June 16, 2016 9:54 PM
> > To: Po Liu
> > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn
> > Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Mingkai Hu;
> > Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian; Murali
> > Karicheri
> > Subject: Re: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
> >
> > On Tue, Jun 14, 2016 at 02:12:27PM +0800, Po Liu wrote:
> > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
> mode.
> > > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > > maybe there is interrupt line for aer pme etc. Search the interrupt
> > > number in the fdt file. Then fixup the dev->irq with it.
> > >
> > > Signed-off-by: Po Liu > --- > changes for V2:
> > > - Move to the quirk file
> > >
> > > drivers/pci/quirks.c | 23 +++ > 1 file
> > changed, 23 insertions(+) > > diff --git a/drivers/pci/quirks.c
> > b/drivers/pci/quirks.c index > ee72ebe..909d479 100644 > ---
> > a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c
> >
> > Is there any possibility of this part being used on different arches,
> > or will it only ever be on arm64 (or whatever it is)? If the latter,
> > it could go somewhere like arch/arm64/kernel/quirks.c (which doesn't
> > exist yet).
>
> NXP Layerscape1 is base on the arm 32bit design. Also need the fixup.
>
> >
> > > @@ -25,6 +25,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include/* isa_dma_bridge_buggy */
> > > #include "pci.h"
> > >
> > > @@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct
> > pci_dev *pdev)
> > > }
> > > }
> > > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, >
> > quirk_intel_qat_vf_cap); > + > +/* If root port doesn't support
> > MSI/MSI-X/INTx in RC mode, > + * but use standalone irq. Read the
> > device tree for the aer > + * interrupt number.
> > > + */
> > > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > > + int ret;
> > > + struct device_node *np = NULL;
> > > +
> > > + if (dev->bus->dev.of_node)
> > > + np = dev->bus->dev.of_node;
> > > +
> > > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > > + ret = of_irq_get_byname(np, "aer");
> > > + if (ret > 0) {
> > > + dev->no_msi = 1;
> > > + dev->irq = ret;
> > > + }
> > > + }
> >
> > What does this mean for the other PCIe services, e.g., PME? I guess
> > this makes the existing AER code work unchanged. But I thought PME
> > had a similar situation and was connected up to a different interrupt
> > than AER was.
>
> Yes, PME is similar, HP is not support. I think better to disable the
> PME service irq in the quirk.
> But seems it is no use because quirk fixup is only running in init phase
> time(except suspend, resume).
>
> >
> > > +}
> > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, >
> > +quirk_aer_interrupt); > -- > 2.1.0.27.g96db324 > > -- > To
> > unsubscribe from this list: send the line "unsubscribe linux-pci"
> > > in the body of a message to majord...@vger.kernel.org More
> > majordomo > info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
Hi Dongdong,
> -Original Message-
> From: Dongdong Liu [mailto:liudongdo...@huawei.com]
> Sent: Thursday, June 23, 2016 1:44 PM
> To: Po Liu; linux-...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org
> Cc: Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang;
> Mingkai Hu; Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian;
> Murali Karicheri
> Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>
>
>
> 在 2016/6/14 16:24, Po Liu 写道:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu <po@nxp.com>
> > ---
> > changes for V3:
> >- Move to quirk;
> >- Only correct the irq in RC mode;
> >
> > drivers/pci/quirks.c | 29 +
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > ee72ebe..8b39cce 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -25,6 +25,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include /* isa_dma_bridge_buggy */
> > #include "pci.h"
> >
> > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> pci_dev *pdev)
> >}
> > }
> > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
> > quirk_intel_qat_vf_cap);
> > +
> > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * but use standalone irq. Read the device tree for the aer
> > + * interrupt number.
> > + */
> > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > + int ret;
> > + u8 header_type;
> > + struct device_node *np = NULL;
> > +
> > + /* Only for the RC mode device */
> > + pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
> > + if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> > + return;
>
> How about that it is changed as below.
>
> /* Only for the RC mode device */
> if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
> return;
>
> Dongdong
> Thanks
Yes, it is also ok to read the capability register.
We see it is common used to read the header type register that is why we use in
this way.
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + dev->no_msi = 1;
> > + dev->irq = ret;
> > + }
> > + }
> > +}
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> > +quirk_aer_interrupt);
> >
RE: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
Hi Dongdong,
> -Original Message-
> From: Dongdong Liu [mailto:liudongdo...@huawei.com]
> Sent: Thursday, June 23, 2016 1:44 PM
> To: Po Liu; linux-...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org
> Cc: Bjorn Helgaas; Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang;
> Mingkai Hu; Stuart Yoder; Yang-Leo Li; Arnd Bergmann; Minghuan Lian;
> Murali Karicheri
> Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>
>
>
> 在 2016/6/14 16:24, Po Liu 写道:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu
> > ---
> > changes for V3:
> >- Move to quirk;
> >- Only correct the irq in RC mode;
> >
> > drivers/pci/quirks.c | 29 +
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > ee72ebe..8b39cce 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -25,6 +25,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include /* isa_dma_bridge_buggy */
> > #include "pci.h"
> >
> > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> pci_dev *pdev)
> >}
> > }
> > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
> > quirk_intel_qat_vf_cap);
> > +
> > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * but use standalone irq. Read the device tree for the aer
> > + * interrupt number.
> > + */
> > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > + int ret;
> > + u8 header_type;
> > + struct device_node *np = NULL;
> > +
> > + /* Only for the RC mode device */
> > + pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
> > + if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> > + return;
>
> How about that it is changed as below.
>
> /* Only for the RC mode device */
> if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
> return;
>
> Dongdong
> Thanks
Yes, it is also ok to read the capability register.
We see it is common used to read the header type register that is why we use in
this way.
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + dev->no_msi = 1;
> > + dev->irq = ret;
> > + }
> > + }
> > +}
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> > +quirk_aer_interrupt);
> >
RE: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Thursday, June 16, 2016 9:54 PM
> To: Po Liu
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas;
> Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Mingkai Hu; Stuart Yoder;
> Yang-Leo Li; Arnd Bergmann; Minghuan Lian; Murali Karicheri
> Subject: Re: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
>
> On Tue, Jun 14, 2016 at 02:12:27PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu <po@nxp.com>
> > ---
> > changes for V2:
> >- Move to the quirk file
> >
> > drivers/pci/quirks.c | 23 +++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > ee72ebe..909d479 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
>
> Is there any possibility of this part being used on different arches, or
> will it only ever be on arm64 (or whatever it is)? If the latter, it
> could go somewhere like arch/arm64/kernel/quirks.c (which doesn't exist
> yet).
NXP Layerscape1 is base on the arm 32bit design. Also need the fixup.
>
> > @@ -25,6 +25,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include /* isa_dma_bridge_buggy */
> > #include "pci.h"
> >
> > @@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct
> pci_dev *pdev)
> >}
> > }
> > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
> > quirk_intel_qat_vf_cap);
> > +
> > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * but use standalone irq. Read the device tree for the aer
> > + * interrupt number.
> > + */
> > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > + int ret;
> > + struct device_node *np = NULL;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + dev->no_msi = 1;
> > + dev->irq = ret;
> > + }
> > + }
>
> What does this mean for the other PCIe services, e.g., PME? I guess
> this makes the existing AER code work unchanged. But I thought PME had
> a similar situation and was connected up to a different interrupt than
> AER was.
Yes, PME is similar, HP is not support. I think better to disable the PME
service irq in the quirk.
But seems it is no use because quirk fixup is only running in init phase
time(except suspend, resume).
>
> > +}
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> > +quirk_aer_interrupt);
> > --
> > 2.1.0.27.g96db324
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-pci"
> > in the body of a message to majord...@vger.kernel.org More majordomo
> > info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Thursday, June 16, 2016 9:54 PM
> To: Po Liu
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Bjorn Helgaas;
> Shawn Guo; Marc Zyngier; Rob Herring; Roy Zang; Mingkai Hu; Stuart Yoder;
> Yang-Leo Li; Arnd Bergmann; Minghuan Lian; Murali Karicheri
> Subject: Re: [PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
>
> On Tue, Jun 14, 2016 at 02:12:27PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu
> > ---
> > changes for V2:
> >- Move to the quirk file
> >
> > drivers/pci/quirks.c | 23 +++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > ee72ebe..909d479 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
>
> Is there any possibility of this part being used on different arches, or
> will it only ever be on arm64 (or whatever it is)? If the latter, it
> could go somewhere like arch/arm64/kernel/quirks.c (which doesn't exist
> yet).
NXP Layerscape1 is base on the arm 32bit design. Also need the fixup.
>
> > @@ -25,6 +25,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include /* isa_dma_bridge_buggy */
> > #include "pci.h"
> >
> > @@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct
> pci_dev *pdev)
> >}
> > }
> > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,
> > quirk_intel_qat_vf_cap);
> > +
> > +/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * but use standalone irq. Read the device tree for the aer
> > + * interrupt number.
> > + */
> > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > + int ret;
> > + struct device_node *np = NULL;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + dev->no_msi = 1;
> > + dev->irq = ret;
> > + }
> > + }
>
> What does this mean for the other PCIe services, e.g., PME? I guess
> this makes the existing AER code work unchanged. But I thought PME had
> a similar situation and was connected up to a different interrupt than
> AER was.
Yes, PME is similar, HP is not support. I think better to disable the PME
service irq in the quirk.
But seems it is no use because quirk fixup is only running in init phase
time(except suspend, resume).
>
> > +}
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> > +quirk_aer_interrupt);
> > --
> > 2.1.0.27.g96db324
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-pci"
> > in the body of a message to majord...@vger.kernel.org More majordomo
> > info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
Hi Shawn, > -Original Message- > From: Shawn Guo [mailto:shawn...@kernel.org] > Sent: Thursday, June 16, 2016 8:36 AM > To: Po Liu > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd > Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Murali > Karicheri; Bjorn Helgaas; Mingkai Hu > Subject: Re: [PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name > property in the dts > > On Tue, Jun 14, 2016 at 04:24:04PM +0800, Po Liu wrote: > > NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using > > interrupt line independently. This patch add a "aer" > > interrupt-names for aer interrupt. > > > > Signed-off-by: Po Liu <po@nxp.com> > > --- > > changes for v3: > >- None; > > > > .../devicetree/bindings/pci/layerscape-pci.txt | 4 ++-- > > The bindings shouldn't be part of dts patch but the driver patch who is > actually using it. > > Shawn Ok, I'll move the doc part to the driver patch. Po Liu From NXP > > > arch/arm/boot/dts/ls1021a.dtsi | 6 -- > > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 > +- > > arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 - > --- > > 4 files changed, 23 insertions(+), 21 deletions(-)
RE: [PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
Hi Shawn, > -Original Message- > From: Shawn Guo [mailto:shawn...@kernel.org] > Sent: Thursday, June 16, 2016 8:36 AM > To: Po Liu > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; Roy Zang; Arnd > Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan Lian; Murali > Karicheri; Bjorn Helgaas; Mingkai Hu > Subject: Re: [PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name > property in the dts > > On Tue, Jun 14, 2016 at 04:24:04PM +0800, Po Liu wrote: > > NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using > > interrupt line independently. This patch add a "aer" > > interrupt-names for aer interrupt. > > > > Signed-off-by: Po Liu > > --- > > changes for v3: > >- None; > > > > .../devicetree/bindings/pci/layerscape-pci.txt | 4 ++-- > > The bindings shouldn't be part of dts patch but the driver patch who is > actually using it. > > Shawn Ok, I'll move the doc part to the driver patch. Po Liu From NXP > > > arch/arm/boot/dts/ls1021a.dtsi | 6 -- > > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 > +- > > arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 - > --- > > 4 files changed, 23 insertions(+), 21 deletions(-)
[PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu <po@nxp.com>
---
changes for V3:
- Move to quirk;
- Only correct the irq in RC mode;
drivers/pci/quirks.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..8b39cce 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include/* isa_dma_bridge_buggy */
#include "pci.h"
@@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+ int ret;
+ u8 header_type;
+ struct device_node *np = NULL;
+
+ /* Only for the RC mode device */
+ pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
+ if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
+ return;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ dev->no_msi = 1;
+ dev->irq = ret;
+ }
+ }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
quirk_aer_interrupt);
--
2.1.0.27.g96db324
[PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. Signed-off-by: Po Liu <po@nxp.com> --- changes for v3: - None; .../devicetree/bindings/pci/layerscape-pci.txt | 4 ++-- arch/arm/boot/dts/ls1021a.dtsi | 6 -- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index ef683b2..d27973a 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -19,7 +19,7 @@ Required properties: - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. - interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts + "aer" : The interrupt that is asserted for aer interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. @@ -33,7 +33,7 @@ Example: 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 5ae8e92..b638697 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -633,7 +633,8 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -656,7 +657,8 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index de0323b..4beb760 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -473,9 +473,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -497,9 +497,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +
[PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu
---
changes for V3:
- Move to quirk;
- Only correct the irq in RC mode;
drivers/pci/quirks.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..8b39cce 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include/* isa_dma_bridge_buggy */
#include "pci.h"
@@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+ int ret;
+ u8 header_type;
+ struct device_node *np = NULL;
+
+ /* Only for the RC mode device */
+ pci_read_config_byte(dev, PCI_HEADER_TYPE, _type);
+ if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
+ return;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ dev->no_msi = 1;
+ dev->irq = ret;
+ }
+ }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
quirk_aer_interrupt);
--
2.1.0.27.g96db324
[PATCH v3 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. Signed-off-by: Po Liu --- changes for v3: - None; .../devicetree/bindings/pci/layerscape-pci.txt | 4 ++-- arch/arm/boot/dts/ls1021a.dtsi | 6 -- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index ef683b2..d27973a 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -19,7 +19,7 @@ Required properties: - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. - interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts + "aer" : The interrupt that is asserted for aer interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. @@ -33,7 +33,7 @@ Example: 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 5ae8e92..b638697 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -633,7 +633,8 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -656,7 +657,8 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index de0323b..4beb760 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -473,9 +473,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -497,9 +497,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +
[PATCH v2 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. Signed-off-by: Po Liu <po@nxp.com> --- Changes for V2: - None. .../devicetree/bindings/pci/layerscape-pci.txt | 4 ++-- arch/arm/boot/dts/ls1021a.dtsi | 6 -- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index ef683b2..d27973a 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -19,7 +19,7 @@ Required properties: - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. - interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts + "aer" : The interrupt that is asserted for aer interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. @@ -33,7 +33,7 @@ Example: 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 5ae8e92..b638697 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -633,7 +633,8 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -656,7 +657,8 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index de0323b..4beb760 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -473,9 +473,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -497,9 +497,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +
[PATCH v2 1/2] nxp/dts: add pcie aer interrupt-name property in the dts
NXP some platforms aer interrupt was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" interrupt-names for aer interrupt. Signed-off-by: Po Liu --- Changes for V2: - None. .../devicetree/bindings/pci/layerscape-pci.txt | 4 ++-- arch/arm/boot/dts/ls1021a.dtsi | 6 -- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index ef683b2..d27973a 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -19,7 +19,7 @@ Required properties: - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. - interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts + "aer" : The interrupt that is asserted for aer interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. @@ -33,7 +33,7 @@ Example: 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 5ae8e92..b638697 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -633,7 +633,8 @@ reg = <0x00 0x0340 0x0 0x0001 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 0>; #address-cells = <3>; #size-cells = <2>; @@ -656,7 +657,8 @@ reg = <0x00 0x0350 0x0 0x0001 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = ; /* aer interrupt */ + interrupt-names = "aer"; fsl,pcie-scfg = < 1>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index de0323b..4beb760 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -473,9 +473,9 @@ reg = <0x00 0x0340 0x0 0x0010 /* controller registers */ 0x40 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ -<0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; + interrupts = <0 117 0x4>, /* PME interrupt */ +<0 118 0x4>; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -497,9 +497,9 @@ reg = <0x00 0x0350 0x0 0x0010 /* controller registers */ 0x48 0x 0x0 0x2000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 128 0x4>, -<0 127 0x4>; - interrupt-names = "intr", "pme"; + interrupts = <0 127 0x4>, +
[PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu <po@nxp.com>
---
changes for V2:
- Move to the quirk file
drivers/pci/quirks.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..909d479 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include/* isa_dma_bridge_buggy */
#include "pci.h"
@@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+ int ret;
+ struct device_node *np = NULL;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ dev->no_msi = 1;
+ dev->irq = ret;
+ }
+ }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
quirk_aer_interrupt);
--
2.1.0.27.g96db324
[PATCH v2 2/2] pci/aer: interrupt fixup in the quirk
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu
---
changes for V2:
- Move to the quirk file
drivers/pci/quirks.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ee72ebe..909d479 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include/* isa_dma_bridge_buggy */
#include "pci.h"
@@ -4419,3 +4420,25 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
+ * but use standalone irq. Read the device tree for the aer
+ * interrupt number.
+ */
+static void quirk_aer_interrupt(struct pci_dev *dev)
+{
+ int ret;
+ struct device_node *np = NULL;
+
+ if (dev->bus->dev.of_node)
+ np = dev->bus->dev.of_node;
+
+ if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
+ ret = of_irq_get_byname(np, "aer");
+ if (ret > 0) {
+ dev->no_msi = 1;
+ dev->irq = ret;
+ }
+ }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
quirk_aer_interrupt);
--
2.1.0.27.g96db324
RE: [PATCH 2/2] aer: add support aer interrupt with none MSI/MSI-X/INTx mode
Hi Bjorn, Thanks for the kindly reply. All these are helpful. > From: Bjorn Helgaas [mailto:helg...@kernel.org] > On Wed, June 08, 2016 6:47 AM > > On Tue, Jun 07, 2016 at 10:07:40AM +, Po Liu wrote: > > Hi Bjorn, > > > > > -Original Message- > > > > > > On Mon, Jun 06, 2016 at 10:01:44AM -0400, Murali Karicheri wrote: > > > > On 06/06/2016 03:32 AM, Po Liu wrote: > > > > > Hi Bjorn, > > > > > I confirm we met same problem with KeyStone base on DesignWare > > > design. > > > > > > > > > > > > > > > Best regards, > > > > > Liu Po > > > > > > > > > >> -Original Message- > > > > >> From: Bjorn Helgaas [mailto:helg...@kernel.org] > >> Sent: > > > Saturday, June 04, 2016 11:49 AM > >> To: Murali Karicheri > >> > > > Cc: Po Liu; linux-...@vger.kernel.org; linux-arm- > >> > > > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; > >> > > > devicet...@vger.kernel.org; Arnd Bergmann; Roy Zang; Marc Zyngier; > > > > >> Stuart Yoder; Yang-Leo Li; Minghuan Lian; Bjorn Helgaas; Shawn > > > Guo; > >> Mingkai Hu; Rob Herring > >> Subject: Re: [PATCH 2/2] > > > aer: add support aer interrupt with none > >> MSI/MSI-X/INTx mode > > > > >> > >> On Fri, Jun 03, 2016 at 01:31:11PM -0400, Murali > > > Karicheri wrote: > > > > >> > Po, > > > > >> > > > > > >> > Sorry to hijack your discussion, but the problem seems to > > > be > >> same for > Keystone PCI controller which is also > > > designware (old > > > version) based. > > > > >> > > > > > >> > On 06/03/2016 12:09 AM, Bjorn Helgaas wrote: > > > > >> > > On Thu, Jun 02, 2016 at 11:37:28AM -0400, Murali > > > Karicheri > > > wrote: > > > > >> > >> On 06/02/2016 09:55 AM, Bjorn Helgaas wrote: > > > > >> > >>> On Thu, Jun 02, 2016 at 05:01:19AM +, Po Liu wrote: > > > > >> > >>>>> -Original Message- > >>>>> From: Bjorn > > > Helgaas > >> [mailto:helg...@kernel.org] > >>>>> Sent: Thursday, > > > June 02, 2016 > >> 11:48 AM > >>>>> To: Po Liu > >>>>> Cc: > > > > >> linux-...@vger.kernel.org; > >>>>> > >> > > > linux-arm-ker...@lists.infradead.org; > > > > >> > >>>>> linux-kernel@vger.kernel.org; > > > devicet...@vger.kernel.org; > >> Arnd > >>>>> Bergmann; Roy Zang; > > > Marc Zyngier; Stuart Yoder; > >> Yang-Leo Li; > >>>>> Minghuan > > > Lian; Bjorn Helgaas; Shawn Guo; > >> Mingkai Hu; Rob > >>>>> > > > Herring > >>>>> Subject: Re: [PATCH 2/2] > >> aer: add support > > > aer interrupt with > >>>>> none MSI/MSI-X/INTx > >> mode > >>>>> > > > > >>>>> [+cc Rob] > >>>>> > >>>>> Hi Po, > > >> >>>>> > >>>>> > > > On Thu, May 26, 2016 at 02:00:06PM +0800, Po Liu > >> wrote: > > > > >> > >>>>> > On some platforms, root port doesn't support > >> > > > MSI/MSI-X/INTx in RC mode. > > > > >> > >>>>> > When chip support the aer interrupt with none > > > > >> MSI/MSI-X/INTx > >>>>> mode, > maybe there is interrupt line > > > for > >> aer pme etc. Search > >>>>> the interrupt > number in > > > the fdt file. > > > > >> > >>>>> > > > > >> > >>>>> My understanding is that AER interrupt signaling can > > > be > >> done > >>>>> via INTx, MSI, or MSI-X (PCIe spec r3.0, sec > > > 6.2.4.1.2). > > > > >> > >>>>> Apparently your device doesn't support MSI or MSI-X. > > > Are > >> you > >>>>> saying it doesn't sup
