RE: [EXT] Re: [next, v2] dmaengine: fsl-dpaa2-qdma: export the symbols
>-Original Message- >From: Vinod Koul >Sent: 2019年10月23日 13:09 >To: Peng Ma >Cc: dan.j.willi...@intel.com; Leo Li ; >anders.rox...@linaro.org; linux-kernel@vger.kernel.org; >dmaeng...@vger.kernel.org >Subject: [EXT] Re: [next, v2] dmaengine: fsl-dpaa2-qdma: export the symbols > >Caution: EXT Email > >On 23-10-19, 12:56, Peng Ma wrote: >> The symbols were not exported leading to error: >> >> WARNING: modpost: missing MODULE_LICENSE() in >drivers/dma/fsl-dpaa2-qdma/dpdmai.o >> see include/linux/module.h for more information >> GZIParch/arm64/boot/Image.gz >> ERROR: "dpdmai_enable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >> ERROR: "dpdmai_set_rx_queue" >[drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! >> ERROR: "dpdmai_get_tx_queue" >[drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! >> ERROR: "dpdmai_get_rx_queue" >[drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! >> ERROR: "dpdmai_get_attributes" >[drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! >> ERROR: "dpdmai_open" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >> ERROR: "dpdmai_close" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >> ERROR: "dpdmai_disable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >> ERROR: "dpdmai_reset" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >> WARNING: "HYPERVISOR_platform_op" [vmlinux] is a static >EXPORT_SYMBOL_GPL >> make[2]: *** [__modpost] Error 1 >> make[1]: *** [modules] Error 2 >> make[1]: *** Waiting for unfinished jobs >> make: *** [sub-make] Error 2 >> >> So export it. > >Applied, thanks [Peng Ma] Got it. Thanks, Peng > >-- >~Vinod
[next, v2] dmaengine: fsl-dpaa2-qdma: export the symbols
The symbols were not exported leading to error:
WARNING: modpost: missing MODULE_LICENSE() in
drivers/dma/fsl-dpaa2-qdma/dpdmai.o
see include/linux/module.h for more information
GZIParch/arm64/boot/Image.gz
ERROR: "dpdmai_enable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
ERROR: "dpdmai_set_rx_queue" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko]
undefined!
ERROR: "dpdmai_get_tx_queue" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko]
undefined!
ERROR: "dpdmai_get_rx_queue" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko]
undefined!
ERROR: "dpdmai_get_attributes" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko]
undefined!
ERROR: "dpdmai_open" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
ERROR: "dpdmai_close" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
ERROR: "dpdmai_disable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
ERROR: "dpdmai_reset" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
WARNING: "HYPERVISOR_platform_op" [vmlinux] is a static EXPORT_SYMBOL_GPL
make[2]: *** [__modpost] Error 1
make[1]: *** [modules] Error 2
make[1]: *** Waiting for unfinished jobs
make: *** [sub-make] Error 2
So export it.
Signed-off-by: Peng Ma
Reported-by: Anders Roxell
---
Changed for v2:
- Rewrite the title and subject
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
index fbc2b2f..f8a1f66 100644
--- a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
+++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright 2019 NXP
+#include
#include
#include
#include
@@ -90,6 +91,7 @@ int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags,
return 0;
}
+EXPORT_SYMBOL_GPL(dpdmai_open);
/**
* dpdmai_close() - Close the control session of the object
@@ -113,6 +115,7 @@ int dpdmai_close(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token)
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_close);
/**
* dpdmai_create() - Create the DPDMAI object
@@ -177,6 +180,7 @@ int dpdmai_enable(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token)
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_enable);
/**
* dpdmai_disable() - Disable the DPDMAI, stop sending and receiving frames.
@@ -197,6 +201,7 @@ int dpdmai_disable(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token)
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_disable);
/**
* dpdmai_reset() - Reset the DPDMAI, returns the object to initial state.
@@ -217,6 +222,7 @@ int dpdmai_reset(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token)
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_reset);
/**
* dpdmai_get_attributes() - Retrieve DPDMAI attributes.
@@ -252,6 +258,7 @@ int dpdmai_get_attributes(struct fsl_mc_io *mc_io, u32
cmd_flags,
return 0;
}
+EXPORT_SYMBOL_GPL(dpdmai_get_attributes);
/**
* dpdmai_set_rx_queue() - Set Rx queue configuration
@@ -285,6 +292,7 @@ int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32
cmd_flags, u16 token,
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_set_rx_queue);
/**
* dpdmai_get_rx_queue() - Retrieve Rx queue attributes.
@@ -325,6 +333,7 @@ int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32
cmd_flags, u16 token,
return 0;
}
+EXPORT_SYMBOL_GPL(dpdmai_get_rx_queue);
/**
* dpdmai_get_tx_queue() - Retrieve Tx queue attributes.
@@ -364,3 +373,6 @@ int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, u32
cmd_flags,
return 0;
}
+EXPORT_SYMBOL_GPL(dpdmai_get_tx_queue);
+
+MODULE_LICENSE("GPL v2");
--
2.9.5
RE: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
Hi Anders, The fixed patch link as follows: https://lore.kernel.org/lkml/20191023021959.35596-1-peng...@nxp.com/ Please check it. Best Regards, Peng >-Original Message- >From: Anders Roxell >Sent: 2019年10月22日 19:11 >To: Peng Ma >Cc: Vinod Koul ; dan.j.willi...@intel.com; Leo Li >; linux-kernel@vger.kernel.org; >dmaeng...@vger.kernel.org >Subject: Re: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the >DPDMAI(Data Path DMA Interface) support > >Caution: EXT Email > >On 2019-10-22 10:19, Peng Ma wrote: >> Hi Anders && Viod, >> >> I sent v6 patch to fix the build error, please check. > >oh I will check, didn't see them when I sent out my email. =/ > >Cheers, >Anders > >> Patchwork link: >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc >> >hwork.kernel.org%2Fproject%2Flinux-dmaengine%2Flist%2F%3Fseries%3D191 >3 >> >97&data=02%7C01%7Cpeng.ma%40nxp.com%7C7f201966dd744703dd4 >c08d756e8 >> >19a2%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637073427176 >654617&a >> >mp;sdata=%2Fsg0iOhBDCqrTzDxS0WPmQoEmq%2BrvbpZd7xytloH484%3D&a >mp;reserv >> ed=0 >> >> Best Regards, >> Peng >> >-Original Message- >> >From: Anders Roxell >> >Sent: 2019年10月22日 17:27 >> >To: Peng Ma >> >Cc: Vinod Koul ; dan.j.willi...@intel.com; Leo Li >> >; linux-kernel@vger.kernel.org; >> >dmaeng...@vger.kernel.org >> >Subject: Re: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the >> >DPDMAI(Data Path DMA Interface) support >> > >> >Caution: EXT Email >> > >> >On Thu, 17 Oct 2019 at 08:16, Peng Ma wrote: >> >> >> >> Hi Vinod, >> >> >> >> Thanks very much for your reply. >> >> >> >> Best Regards, >> >> Peng >> >> >-----Original Message- >> >> >From: Vinod Koul >> >> >Sent: 2019年10月17日 12:11 >> >> >To: Peng Ma >> >> >Cc: dan.j.willi...@intel.com; Leo Li ; >> >> >linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org >> >> >Subject: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the >> >> >DPDMAI(Data Path DMA Interface) support >> >> > >> >> >Caution: EXT Email >> >> > >> >> >On 30-09-19, 02:04, Peng Ma wrote: >> >> >> The MC(Management Complex) exports the DPDMAI(Data Path DMA >> >> >Interface) >> >> >> object as an interface to operate the DPAA2(Data Path >> >> >> Acceleration Architecture 2) qDMA Engine. The DPDMAI enables >> >> >> sending frame-based requests to qDMA and receiving back >> >> >> confirmation response on transaction completion, utilizing the >> >> >> DPAA2 QBMan(Queue Manager and Buffer Manager >> >> >> hardware) infrastructure. DPDMAI object provides up to two >> >> >> priorities for processing qDMA requests. >> >> >> The following list summarizes the DPDMAI main features and >capabilities: >> >> >> 1. Supports up to two scheduling priorities for processing >> >> >> service requests. >> >> >> - Each DPDMAI transmit queue is mapped to one of two >service >> >> >> priorities, allowing further prioritization in hardware between >> >> >> requests from different DPDMAI objects. >> >> >> 2. Supports up to two receive queues for incoming transaction >> >> >> completion confirmations. >> >> >> - Each DPDMAI receive queue is mapped to one of two receive >> >> >> priorities, allowing further prioritization between other >> >> >> interfaces when associating the DPDMAI receive queues to >DPIO >> >> >> or DPCON(Data Path Concentrator) objects. >> >> >> 3. Supports different scheduling options for processing >received >> >> >> packets: >> >> >> - Queues can be configured either in 'parked' mode (default), >> >> >> or attached to a DPIO object, or attached to DPCON object. >> >> >> 4. Allows interaction with one or more DPIO objects for >> >> >> dequeueing/enqueueing frame descriptors(FD) and for >> >> >> acquiring/releasing buffers. >> >> >> 5. Supports enable, disable, and reset
RE: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
Hi Vinod, >-Original Message- >From: Vinod Koul >Sent: 2019年10月23日 0:10 >To: Peng Ma >Cc: Anders Roxell ; dan.j.willi...@intel.com; Leo Li >; linux-kernel@vger.kernel.org; >dmaeng...@vger.kernel.org >Subject: Re: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the >DPDMAI(Data Path DMA Interface) support > >Caution: EXT Email > >Please *do* *not* top post! > >On 22-10-19, 10:19, Peng Ma wrote: >> Hi Anders && Viod, > >Its Vinod! > [Peng Ma] I am very sorry to spell your name wrong, I will pay attention to from now! >> >> I sent v6 patch to fix the build error, please check. >> Patchwork link: >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc >> >hwork.kernel.org%2Fproject%2Flinux-dmaengine%2Flist%2F%3Fseries%3D191 >3 >> >97&data=02%7C01%7Cpeng.ma%40nxp.com%7C19ac47d605bf44aa99d >e08d7570a >> >5e64%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637073574351 >786723&a >> >mp;sdata=%2B%2FazVuPMJZUonfvz8gLWGVeakKW0tRFYyjj344IbDg4%3D&am >p;reserv >> ed=0 > >No I have already applied v5, please send fixes on top on dmaengine-next! >Would also make sense to give credit to Anders using Reported-by tag > [Peng Ma] Ok, Got it. The patchwork link: https://patchwork.kernel.org/patch/11205611/ >> >> Best Regards, >> Peng >> >-Original Message- >> >From: Anders Roxell >> >Sent: 2019年10月22日 17:27 >> >To: Peng Ma >> >Cc: Vinod Koul ; dan.j.willi...@intel.com; Leo Li >> >; linux-kernel@vger.kernel.org; >> >dmaeng...@vger.kernel.org >> >Subject: Re: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the >> >DPDMAI(Data Path DMA Interface) support >> > >> >Caution: EXT Email >> > >> >On Thu, 17 Oct 2019 at 08:16, Peng Ma wrote: >> >> >> >> Hi Vinod, >> >> >> >> Thanks very much for your reply. >> >> >> >> Best Regards, >> >> Peng >> >> >-Original Message- >> >> >From: Vinod Koul >> >> >Sent: 2019年10月17日 12:11 >> >> >To: Peng Ma >> >> >Cc: dan.j.willi...@intel.com; Leo Li ; >> >> >linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org >> >> >Subject: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the >> >> >DPDMAI(Data Path DMA Interface) support >> >> > >> >> >Caution: EXT Email >> >> > >> >> >On 30-09-19, 02:04, Peng Ma wrote: >> >> >> The MC(Management Complex) exports the DPDMAI(Data Path DMA >> >> >Interface) >> >> >> object as an interface to operate the DPAA2(Data Path >> >> >> Acceleration Architecture 2) qDMA Engine. The DPDMAI enables >> >> >> sending frame-based requests to qDMA and receiving back >> >> >> confirmation response on transaction completion, utilizing the >> >> >> DPAA2 QBMan(Queue Manager and Buffer Manager >> >> >> hardware) infrastructure. DPDMAI object provides up to two >> >> >> priorities for processing qDMA requests. >> >> >> The following list summarizes the DPDMAI main features and >capabilities: >> >> >> 1. Supports up to two scheduling priorities for processing >> >> >> service requests. >> >> >> - Each DPDMAI transmit queue is mapped to one of two >service >> >> >> priorities, allowing further prioritization in hardware between >> >> >> requests from different DPDMAI objects. >> >> >> 2. Supports up to two receive queues for incoming transaction >> >> >> completion confirmations. >> >> >> - Each DPDMAI receive queue is mapped to one of two receive >> >> >> priorities, allowing further prioritization between other >> >> >> interfaces when associating the DPDMAI receive queues to >DPIO >> >> >> or DPCON(Data Path Concentrator) objects. >> >> >> 3. Supports different scheduling options for processing >received >> >> >> packets: >> >> >> - Queues can be configured either in 'parked' mode (default), >> >> >> or attached to a DPIO object, or attached to DPCON object. >> >> >> 4. Allows interaction with one or more DPIO objects for >> >> >> dequeueing/enqueueing frame descriptors
[PATCH] dmaengine: fsl-dpaa2-qdma: Fixed build error when enable dpaa2 qdma module driver
Fixed the following error:
WARNING: modpost: missing MODULE_LICENSE() in
drivers/dma/fsl-dpaa2-qdma/dpdmai.o
see include/linux/module.h for more information
GZIParch/arm64/boot/Image.gz
ERROR: "dpdmai_enable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
ERROR: "dpdmai_set_rx_queue" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko]
undefined!
ERROR: "dpdmai_get_tx_queue" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko]
undefined!
ERROR: "dpdmai_get_rx_queue" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko]
undefined!
ERROR: "dpdmai_get_attributes" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko]
undefined!
ERROR: "dpdmai_open" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
ERROR: "dpdmai_close" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
ERROR: "dpdmai_disable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
ERROR: "dpdmai_reset" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined!
WARNING: "HYPERVISOR_platform_op" [vmlinux] is a static EXPORT_SYMBOL_GPL
make[2]: *** [__modpost] Error 1
make[1]: *** [modules] Error 2
make[1]: *** Waiting for unfinished jobs
make: *** [sub-make] Error 2
Signed-off-by: Peng Ma
Reported-by: Anders Roxell
---
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
index fbc2b2f..f8a1f66 100644
--- a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
+++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright 2019 NXP
+#include
#include
#include
#include
@@ -90,6 +91,7 @@ int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags,
return 0;
}
+EXPORT_SYMBOL_GPL(dpdmai_open);
/**
* dpdmai_close() - Close the control session of the object
@@ -113,6 +115,7 @@ int dpdmai_close(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token)
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_close);
/**
* dpdmai_create() - Create the DPDMAI object
@@ -177,6 +180,7 @@ int dpdmai_enable(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token)
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_enable);
/**
* dpdmai_disable() - Disable the DPDMAI, stop sending and receiving frames.
@@ -197,6 +201,7 @@ int dpdmai_disable(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token)
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_disable);
/**
* dpdmai_reset() - Reset the DPDMAI, returns the object to initial state.
@@ -217,6 +222,7 @@ int dpdmai_reset(struct fsl_mc_io *mc_io, u32 cmd_flags,
u16 token)
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_reset);
/**
* dpdmai_get_attributes() - Retrieve DPDMAI attributes.
@@ -252,6 +258,7 @@ int dpdmai_get_attributes(struct fsl_mc_io *mc_io, u32
cmd_flags,
return 0;
}
+EXPORT_SYMBOL_GPL(dpdmai_get_attributes);
/**
* dpdmai_set_rx_queue() - Set Rx queue configuration
@@ -285,6 +292,7 @@ int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32
cmd_flags, u16 token,
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
+EXPORT_SYMBOL_GPL(dpdmai_set_rx_queue);
/**
* dpdmai_get_rx_queue() - Retrieve Rx queue attributes.
@@ -325,6 +333,7 @@ int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32
cmd_flags, u16 token,
return 0;
}
+EXPORT_SYMBOL_GPL(dpdmai_get_rx_queue);
/**
* dpdmai_get_tx_queue() - Retrieve Tx queue attributes.
@@ -364,3 +373,6 @@ int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, u32
cmd_flags,
return 0;
}
+EXPORT_SYMBOL_GPL(dpdmai_get_tx_queue);
+
+MODULE_LICENSE("GPL v2");
--
2.9.5
RE: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
Hi Anders && Viod, I sent v6 patch to fix the build error, please check. Patchwork link: https://patchwork.kernel.org/project/linux-dmaengine/list/?series=191397 Best Regards, Peng >-Original Message- >From: Anders Roxell >Sent: 2019年10月22日 17:27 >To: Peng Ma >Cc: Vinod Koul ; dan.j.willi...@intel.com; Leo Li >; linux-kernel@vger.kernel.org; >dmaeng...@vger.kernel.org >Subject: Re: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the >DPDMAI(Data Path DMA Interface) support > >Caution: EXT Email > >On Thu, 17 Oct 2019 at 08:16, Peng Ma wrote: >> >> Hi Vinod, >> >> Thanks very much for your reply. >> >> Best Regards, >> Peng >> >-Original Message- >> >From: Vinod Koul >> >Sent: 2019年10月17日 12:11 >> >To: Peng Ma >> >Cc: dan.j.willi...@intel.com; Leo Li ; >> >linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org >> >Subject: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the >> >DPDMAI(Data Path DMA Interface) support >> > >> >Caution: EXT Email >> > >> >On 30-09-19, 02:04, Peng Ma wrote: >> >> The MC(Management Complex) exports the DPDMAI(Data Path DMA >> >Interface) >> >> object as an interface to operate the DPAA2(Data Path Acceleration >> >> Architecture 2) qDMA Engine. The DPDMAI enables sending frame-based >> >> requests to qDMA and receiving back confirmation response on >> >> transaction completion, utilizing the DPAA2 QBMan(Queue Manager and >> >> Buffer Manager >> >> hardware) infrastructure. DPDMAI object provides up to two >> >> priorities for processing qDMA requests. >> >> The following list summarizes the DPDMAI main features and capabilities: >> >> 1. Supports up to two scheduling priorities for processing >> >> service requests. >> >> - Each DPDMAI transmit queue is mapped to one of two service >> >> priorities, allowing further prioritization in hardware between >> >> requests from different DPDMAI objects. >> >> 2. Supports up to two receive queues for incoming transaction >> >> completion confirmations. >> >> - Each DPDMAI receive queue is mapped to one of two receive >> >> priorities, allowing further prioritization between other >> >> interfaces when associating the DPDMAI receive queues to DPIO >> >> or DPCON(Data Path Concentrator) objects. >> >> 3. Supports different scheduling options for processing received >> >> packets: >> >> - Queues can be configured either in 'parked' mode (default), >> >> or attached to a DPIO object, or attached to DPCON object. >> >> 4. Allows interaction with one or more DPIO objects for >> >> dequeueing/enqueueing frame descriptors(FD) and for >> >> acquiring/releasing buffers. >> >> 5. Supports enable, disable, and reset operations. >> >> >> >> Add dpdmai to support some platforms with dpaa2 qdma engine. >> > >> >Applied both, thanks > >I see this error when I'm building. > >WARNING: modpost: missing MODULE_LICENSE() in >drivers/dma/fsl-dpaa2-qdma/dpdmai.o >see include/linux/module.h for more information >ERROR: "dpdmai_enable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >ERROR: "dpdmai_set_rx_queue" >[drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! >ERROR: "dpdmai_get_tx_queue" >[drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! >ERROR: "dpdmai_get_rx_queue" >[drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! >ERROR: "dpdmai_get_attributes" >[drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! >ERROR: "dpdmai_open" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >ERROR: "dpdmai_close" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >ERROR: "dpdmai_disable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >ERROR: "dpdmai_reset" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] >undefined! >make[2]: *** [../scripts/Makefile.modpost:95: __modpost] Error 1 >make[1]: *** [/srv/src/kernel/next/Makefile:1282: modules] Error 2 >make: *** [Makefile:179: sub-make] Error 2 >make: Target 'Image' not remade because of errors. >make: Target 'modules' not remade because of errors. > >any other that see the same ? > >Cheers, >Anders
[v6] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
The MC(Management Complex) exports the DPDMAI(Data Path DMA Interface)
object as an interface to operate the DPAA2(Data Path Acceleration
Architecture 2) qDMA Engine. The DPDMAI enables sending frame-based
requests to qDMA and receiving back confirmation response on transaction
completion, utilizing the DPAA2 QBMan(Queue Manager and Buffer Manager
hardware) infrastructure. DPDMAI object provides up to two priorities for
processing qDMA requests.
The following list summarizes the DPDMAI main features and capabilities:
1. Supports up to two scheduling priorities for processing
service requests.
- Each DPDMAI transmit queue is mapped to one of two service
priorities, allowing further prioritization in hardware between
requests from different DPDMAI objects.
2. Supports up to two receive queues for incoming transaction
completion confirmations.
- Each DPDMAI receive queue is mapped to one of two receive
priorities, allowing further prioritization between other
interfaces when associating the DPDMAI receive queues to DPIO
or DPCON(Data Path Concentrator) objects.
3. Supports different scheduling options for processing received
packets:
- Queues can be configured either in 'parked' mode (default),
or attached to a DPIO object, or attached to DPCON object.
4. Allows interaction with one or more DPIO objects for
dequeueing/enqueueing frame descriptors(FD) and for
acquiring/releasing buffers.
5. Supports enable, disable, and reset operations.
Add dpdmai to support some platforms with dpaa2 qdma engine.
Signed-off-by: Peng Ma
---
Changed for v6:
- Fixed build error when enable dpaa2 qdma module driver
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 378
drivers/dma/fsl-dpaa2-qdma/dpdmai.h | 177 +
2 files changed, 555 insertions(+)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.h
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
new file mode 100644
index 000..f8a1f66
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+#include
+#include
+#include
+#include
+#include "dpdmai.h"
+
+struct dpdmai_rsp_get_attributes {
+ __le32 id;
+ u8 num_of_priorities;
+ u8 pad0[3];
+ __le16 major;
+ __le16 minor;
+};
+
+struct dpdmai_cmd_queue {
+ __le32 dest_id;
+ u8 priority;
+ u8 queue;
+ u8 dest_type;
+ u8 pad;
+ __le64 user_ctx;
+ union {
+ __le32 options;
+ __le32 fqid;
+ };
+};
+
+struct dpdmai_rsp_get_tx_queue {
+ __le64 pad;
+ __le32 fqid;
+};
+
+#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
+ ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPDMAI_CMD_CREATE(_cmd, _cfg) \
+do { \
+ typeof(_cmd) (cmd) = (_cmd); \
+ typeof(_cfg) (cfg) = (_cfg); \
+ MC_CMD_OP(cmd, 0, 8, 8, u8, (cfg)->priorities[0]);\
+ MC_CMD_OP(cmd, 0, 16, 8, u8, (cfg)->priorities[1]);\
+} while (0)
+
+static inline u64 mc_enc(int lsoffset, int width, u64 val)
+{
+ return (val & MAKE_UMASK64(width)) << lsoffset;
+}
+
+/**
+ * dpdmai_open() - Open a control session for the specified object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpdmai_id: DPDMAI unique ID
+ * @token: Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpdmai_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags,
+ int dpdmai_id, u16 *token)
+{
+ struct fsl_mc_command cmd = { 0 };
+ __le64 *cmd_dpdmai_id;
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
+ cmd_flags, 0);
+
+ cmd_dpdmai_id = cmd.params;
+ *cmd_dpdmai_id = cpu_to_le32(dpdmai_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = mc_cmd_hdr_read_token(&cmd);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(dpdmai_open);
+
+/**
+
[v6 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
DPPA2(Data Path Acceleration Architecture 2) qDMA supports
virtualized channel by allowing DMA jobs to be enqueued into
different work queues. Core can initiate a DMA transaction by
preparing a frame descriptor(FD) for each DMA job and enqueuing
this job through a hardware portal. DPAA2 components can also
prepare a FD and enqueue a DMA job through a hardware portal.
The qDMA prefetches DMA jobs through DPAA2 hardware portal. It
then schedules and dispatches to internal DMA hardware engines,
which generate read and write requests. Both qDMA source data and
destination data can be either contiguous or non-contiguous using
one or more scatter/gather tables.
The qDMA supports global bandwidth flow control where all DMA
transactions are stalled if the bandwidth threshold has been reached.
Also supported are transaction based read throttling.
Add NXP dppa2 qDMA to support some of Layerscape SoCs.
such as: LS1088A, LS208xA, LX2, etc.
Signed-off-by: Peng Ma
---
Changed for v6:
- No changed
drivers/dma/Kconfig | 2 +
drivers/dma/Makefile| 1 +
drivers/dma/fsl-dpaa2-qdma/Kconfig | 9 +
drivers/dma/fsl-dpaa2-qdma/Makefile | 3 +
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 825
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 153 ++
6 files changed, 993 insertions(+)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Kconfig
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Makefile
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 7af874b..f5decdc 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -669,6 +669,8 @@ source "drivers/dma/sh/Kconfig"
source "drivers/dma/ti/Kconfig"
+source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
+
# clients
comment "DMA Clients"
depends on DMA_ENGINE
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index f5ce866..b3d48f9 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
+obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
obj-y += mediatek/
obj-y += qcom/
diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig
b/drivers/dma/fsl-dpaa2-qdma/Kconfig
new file mode 100644
index 000..258ed6b
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig
@@ -0,0 +1,9 @@
+menuconfig FSL_DPAA2_QDMA
+ tristate "NXP DPAA2 QDMA"
+ depends on ARM64
+ depends on FSL_MC_BUS && FSL_MC_DPIO
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ NXP Data Path Acceleration Architecture 2 QDMA driver,
+ using the NXP MC bus driver.
diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile
b/drivers/dma/fsl-dpaa2-qdma/Makefile
new file mode 100644
index 000..c1d0226
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# Makefile for the NXP DPAA2 qDMA controllers
+obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
new file mode 100644
index 000..c70a796
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
@@ -0,0 +1,825 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+#include "dpdmai.h"
+#include "dpaa2-qdma.h"
+
+static bool smmu_disable = true;
+
+static struct dpaa2_qdma_chan *to_dpaa2_qdma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct dpaa2_qdma_chan, vchan.chan);
+}
+
+static struct dpaa2_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct dpaa2_qdma_comp, vdesc);
+}
+
+static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma;
+ struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev;
+
+ dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev,
+ sizeof(struct dpaa2_fd),
+ sizeof(struct dpaa2_fd), 0);
+ if (!dpaa2_chan->fd_pool)
+ goto err;
+
+ dpaa2_chan->fl_pool = dma_pool_create("fl_pool", dev,
+ sizeof(struct dpaa2_fl_entry),
+ sizeof(struct dpaa2_fl_entry), 0);
+ if (!dpaa2_chan->fl_pool)
+ goto err_fd;
+
+ dpaa2_chan->sdd_pool =
+
RE: [EXT] [RFT] dmaengine: fsl-qdma: Handle invalid qdma-queue0 IRQ
Hi Krzysztof, Thanks for your patch. Reviewed-by: Peng Ma Tested-by: Peng Ma Best Regards, Peng >-Original Message- >From: Krzysztof Kozlowski >Sent: 2019年10月4日 23:08 >To: Vinod Koul ; Dan Williams ; >Peng Ma ; Wen He ; Jiaheng Fan >; Krzysztof Kozlowski ; >dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org >Subject: [EXT] [RFT] dmaengine: fsl-qdma: Handle invalid qdma-queue0 IRQ > >Caution: EXT Email > >platform_get_irq_byname() might return -errno which later would be cast to an >unsigned int and used in IRQ handling code leading to usage of wrong ID and >errors about wrong irq_base. > >Signed-off-by: Krzysztof Kozlowski > >--- > >Not marking as cc-stable as this was not reproduced and not tested. >--- > drivers/dma/fsl-qdma.c | 3 +++ > 1 file changed, 3 insertions(+) > >diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c index >06664fbd2d91..89792083d62c 100644 >--- a/drivers/dma/fsl-qdma.c >+++ b/drivers/dma/fsl-qdma.c >@@ -1155,6 +1155,9 @@ static int fsl_qdma_probe(struct platform_device >*pdev) >return ret; > >fsl_qdma->irq_base = platform_get_irq_byname(pdev, >"qdma-queue0"); >+ if (fsl_qdma->irq_base < 0) >+ return fsl_qdma->irq_base; >+ >fsl_qdma->feature = of_property_read_bool(np, "big-endian"); >INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels); > >-- >2.17.1
[V2] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A platform
Our platforms(such as LS1021A, LS1012A, LS1043A, LS1046A, LS1028A) with below
registers(CHCFG0 - CHCFG15) of eDMA as follows:
*---*
| Offset |OTHERS | LS1028A |
|--||---|
| 0x0 |CHCFG0 | CHCFG3 |
|--||---|
| 0x1 |CHCFG1 | CHCFG2 |
|--||---|
| 0x2 |CHCFG2 | CHCFG1 |
|--||---|
| 0x3 |CHCFG3 | CHCFG0 |
|--||---|
| ... |.. | .. |
|--||---|
| 0xC |CHCFG12 | CHCFG15 |
|--||---|
| 0xD |CHCFG13 | CHCFG14 |
|--||---|
| 0xE |CHCFG14 | CHCFG13 |
|--||---|
| 0xF |CHCFG15 | CHCFG12 |
*---*
This patch is to improve edma driver to fit LS1028A platform.
Signed-off-by: Peng Ma
---
Changed for V2:
- Explaining what's the "Our platforms"
drivers/dma/fsl-edma-common.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index b1a7ca9..611186b 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include "fsl-edma-common.h"
@@ -42,6 +43,11 @@
#define EDMA_TCD 0x1000
+static struct soc_device_attribute soc_fixup_tuning[] = {
+ { .family = "QorIQ LS1028A"},
+ { },
+};
+
static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
{
struct edma_regs *regs = &fsl_chan->edma->regs;
@@ -109,10 +115,16 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
u32 ch = fsl_chan->vchan.chan.chan_id;
void __iomem *muxaddr;
unsigned int chans_per_mux, ch_off;
+ int endian_diff[4] = {3, 1, -1, -3};
u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs;
chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr;
ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
+
+ if (!fsl_chan->edma->big_endian &&
+ soc_device_match(soc_fixup_tuning))
+ ch_off += endian_diff[ch_off % 4];
+
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
slot = EDMAMUX_CHCFG_SOURCE(slot);
--
2.9.5
RE: [EXT] Re: [PATCH] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A platform
Hi Fabio, >-Original Message- >From: Fabio Estevam >Sent: 2019年10月18日 22:40 >To: Peng Ma >Cc: Vinod ; Dan Williams ; Leo >Li ; Krzysztof Kozłowski ; >Fabio Estevam ; dmaeng...@vger.kernel.org; >linux-kernel >Subject: Re: [EXT] Re: [PATCH] dmaengine: fsl-edma: Add eDMA support for >QorIQ LS1028A platform > >Caution: EXT Email > >Hi Peng, > >On Fri, Oct 18, 2019 at 11:28 AM Peng Ma wrote: >> >> Hi Fabio, >> >> Thanks for your comments. >> Do you mean I explain "Our platforms" here or in patch? > >It would be better to send a v2 with an improved commit log, which explains >what "Our platforms" mean. > >Thanks [Peng Ma] God it ,thanks. Best Regards, Peng
RE: [EXT] Re: [PATCH] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A platform
Hi Fabio, Thanks for your comments. Do you mean I explain "Our platforms" here or in patch? Best Regards, Peng >-Original Message- >From: Fabio Estevam >Sent: 2019年10月18日 22:25 >To: Peng Ma >Cc: Vinod ; Dan Williams ; Leo >Li ; Krzysztof Kozłowski ; >Fabio Estevam ; dmaeng...@vger.kernel.org; >linux-kernel >Subject: [EXT] Re: [PATCH] dmaengine: fsl-edma: Add eDMA support for QorIQ >LS1028A platform > >Caution: EXT Email > >Hi Peng, > >On Fri, Oct 18, 2019 at 7:08 AM Peng Ma wrote: >> >> Our platforms with below registers(CHCFG0 - CHCFG15) of eDMA as follows: > >Please be more specific: what does "Our platforms" mean?
[PATCH] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A platform
Our platforms with below registers(CHCFG0 - CHCFG15) of eDMA as follows:
*---*
| Offset |OTHERS | LS1028A |
|--||---|
| 0x0 |CHCFG0 | CHCFG3 |
|--||---|
| 0x1 |CHCFG1 | CHCFG2 |
|--||---|
| 0x2 |CHCFG2 | CHCFG1 |
|--||---|
| 0x3 |CHCFG3 | CHCFG0 |
|--||---|
| ... |.. | .. |
|--||---|
| 0xC |CHCFG12 | CHCFG15 |
|--||---|
| 0xD |CHCFG13 | CHCFG14 |
|--||---|
| 0xE |CHCFG14 | CHCFG13 |
|--||---|
| 0xF |CHCFG15 | CHCFG12 |
*---*
This patch is to improve edma driver to fit LS1028A platform.
Signed-off-by: Peng Ma
---
drivers/dma/fsl-edma-common.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index b1a7ca9..611186b 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include "fsl-edma-common.h"
@@ -42,6 +43,11 @@
#define EDMA_TCD 0x1000
+static struct soc_device_attribute soc_fixup_tuning[] = {
+ { .family = "QorIQ LS1028A"},
+ { },
+};
+
static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
{
struct edma_regs *regs = &fsl_chan->edma->regs;
@@ -109,10 +115,16 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
u32 ch = fsl_chan->vchan.chan.chan_id;
void __iomem *muxaddr;
unsigned int chans_per_mux, ch_off;
+ int endian_diff[4] = {3, 1, -1, -3};
u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs;
chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr;
ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
+
+ if (!fsl_chan->edma->big_endian &&
+ soc_device_match(soc_fixup_tuning))
+ ch_off += endian_diff[ch_off % 4];
+
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
slot = EDMAMUX_CHCFG_SOURCE(slot);
--
2.9.5
RE: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
Hi Vinod, Thanks very much for your reply. Best Regards, Peng >-Original Message- >From: Vinod Koul >Sent: 2019年10月17日 12:11 >To: Peng Ma >Cc: dan.j.willi...@intel.com; Leo Li ; >linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org >Subject: [EXT] Re: [V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data >Path DMA Interface) support > >Caution: EXT Email > >On 30-09-19, 02:04, Peng Ma wrote: >> The MC(Management Complex) exports the DPDMAI(Data Path DMA >Interface) >> object as an interface to operate the DPAA2(Data Path Acceleration >> Architecture 2) qDMA Engine. The DPDMAI enables sending frame-based >> requests to qDMA and receiving back confirmation response on >> transaction completion, utilizing the DPAA2 QBMan(Queue Manager and >> Buffer Manager >> hardware) infrastructure. DPDMAI object provides up to two priorities >> for processing qDMA requests. >> The following list summarizes the DPDMAI main features and capabilities: >> 1. Supports up to two scheduling priorities for processing >> service requests. >> - Each DPDMAI transmit queue is mapped to one of two service >> priorities, allowing further prioritization in hardware between >> requests from different DPDMAI objects. >> 2. Supports up to two receive queues for incoming transaction >> completion confirmations. >> - Each DPDMAI receive queue is mapped to one of two receive >> priorities, allowing further prioritization between other >> interfaces when associating the DPDMAI receive queues to DPIO >> or DPCON(Data Path Concentrator) objects. >> 3. Supports different scheduling options for processing received >> packets: >> - Queues can be configured either in 'parked' mode (default), >> or attached to a DPIO object, or attached to DPCON object. >> 4. Allows interaction with one or more DPIO objects for >> dequeueing/enqueueing frame descriptors(FD) and for >> acquiring/releasing buffers. >> 5. Supports enable, disable, and reset operations. >> >> Add dpdmai to support some platforms with dpaa2 qdma engine. > >Applied both, thanks > >-- >~Vinod
[V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
The MC(Management Complex) exports the DPDMAI(Data Path DMA Interface)
object as an interface to operate the DPAA2(Data Path Acceleration
Architecture 2) qDMA Engine. The DPDMAI enables sending frame-based
requests to qDMA and receiving back confirmation response on transaction
completion, utilizing the DPAA2 QBMan(Queue Manager and Buffer Manager
hardware) infrastructure. DPDMAI object provides up to two priorities for
processing qDMA requests.
The following list summarizes the DPDMAI main features and capabilities:
1. Supports up to two scheduling priorities for processing
service requests.
- Each DPDMAI transmit queue is mapped to one of two service
priorities, allowing further prioritization in hardware between
requests from different DPDMAI objects.
2. Supports up to two receive queues for incoming transaction
completion confirmations.
- Each DPDMAI receive queue is mapped to one of two receive
priorities, allowing further prioritization between other
interfaces when associating the DPDMAI receive queues to DPIO
or DPCON(Data Path Concentrator) objects.
3. Supports different scheduling options for processing received
packets:
- Queues can be configured either in 'parked' mode (default),
or attached to a DPIO object, or attached to DPCON object.
4. Allows interaction with one or more DPIO objects for
dequeueing/enqueueing frame descriptors(FD) and for
acquiring/releasing buffers.
5. Supports enable, disable, and reset operations.
Add dpdmai to support some platforms with dpaa2 qdma engine.
Signed-off-by: Peng Ma
---
changed for v5:
- Clean up the format.
- Delete some useless struct and macro.
- Fix spell.
- Move the description of function from header to C file.
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 366 +++
drivers/dma/fsl-dpaa2-qdma/dpdmai.h | 177 +
2 files changed, 543 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.h
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
new file mode 100644
index 000..fbc2b2f
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+#include
+#include
+#include
+#include "dpdmai.h"
+
+struct dpdmai_rsp_get_attributes {
+ __le32 id;
+ u8 num_of_priorities;
+ u8 pad0[3];
+ __le16 major;
+ __le16 minor;
+};
+
+struct dpdmai_cmd_queue {
+ __le32 dest_id;
+ u8 priority;
+ u8 queue;
+ u8 dest_type;
+ u8 pad;
+ __le64 user_ctx;
+ union {
+ __le32 options;
+ __le32 fqid;
+ };
+};
+
+struct dpdmai_rsp_get_tx_queue {
+ __le64 pad;
+ __le32 fqid;
+};
+
+#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
+ ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPDMAI_CMD_CREATE(_cmd, _cfg) \
+do { \
+ typeof(_cmd) (cmd) = (_cmd); \
+ typeof(_cfg) (cfg) = (_cfg); \
+ MC_CMD_OP(cmd, 0, 8, 8, u8, (cfg)->priorities[0]);\
+ MC_CMD_OP(cmd, 0, 16, 8, u8, (cfg)->priorities[1]);\
+} while (0)
+
+static inline u64 mc_enc(int lsoffset, int width, u64 val)
+{
+ return (val & MAKE_UMASK64(width)) << lsoffset;
+}
+
+/**
+ * dpdmai_open() - Open a control session for the specified object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpdmai_id: DPDMAI unique ID
+ * @token: Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpdmai_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags,
+ int dpdmai_id, u16 *token)
+{
+ struct fsl_mc_command cmd = { 0 };
+ __le64 *cmd_dpdmai_id;
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
+ cmd_flags, 0);
+
+ cmd_dpdmai_id = cmd.params;
+ *cmd_dpdmai_id = cpu_to_le32(dpdmai_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
[V5 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
DPPA2(Data Path Acceleration Architecture 2) qDMA supports
virtualized channel by allowing DMA jobs to be enqueued into
different work queues. Core can initiate a DMA transaction by
preparing a frame descriptor(FD) for each DMA job and enqueuing
this job through a hardware portal. DPAA2 components can also
prepare a FD and enqueue a DMA job through a hardware portal.
The qDMA prefetches DMA jobs through DPAA2 hardware portal. It
then schedules and dispatches to internal DMA hardware engines,
which generate read and write requests. Both qDMA source data and
destination data can be either contiguous or non-contiguous using
one or more scatter/gather tables.
The qDMA supports global bandwidth flow control where all DMA
transactions are stalled if the bandwidth threshold has been reached.
Also supported are transaction based read throttling.
Add NXP dppa2 qDMA to support some of Layerscape SoCs.
such as: LS1088A, LS208xA, LX2, etc.
Signed-off-by: Peng Ma
---
changed for v5:
- Clean up the format and code.
- Update comments.
- Add error logs.
drivers/dma/Kconfig |2 +
drivers/dma/Makefile|1 +
drivers/dma/fsl-dpaa2-qdma/Kconfig |9 +
drivers/dma/fsl-dpaa2-qdma/Makefile |3 +
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 825 +++
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 153 ++
6 files changed, 993 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Kconfig
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Makefile
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 76859aa..e4dd9c6 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -673,6 +673,8 @@ source "drivers/dma/sh/Kconfig"
source "drivers/dma/ti/Kconfig"
+source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
+
# clients
comment "DMA Clients"
depends on DMA_ENGINE
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 5bddf6f..15a318d 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
+obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
obj-y += mediatek/
obj-y += qcom/
diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig
b/drivers/dma/fsl-dpaa2-qdma/Kconfig
new file mode 100644
index 000..258ed6b
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig
@@ -0,0 +1,9 @@
+menuconfig FSL_DPAA2_QDMA
+ tristate "NXP DPAA2 QDMA"
+ depends on ARM64
+ depends on FSL_MC_BUS && FSL_MC_DPIO
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ NXP Data Path Acceleration Architecture 2 QDMA driver,
+ using the NXP MC bus driver.
diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile
b/drivers/dma/fsl-dpaa2-qdma/Makefile
new file mode 100644
index 000..c1d0226
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# Makefile for the NXP DPAA2 qDMA controllers
+obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
new file mode 100644
index 000..c70a796
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
@@ -0,0 +1,825 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+#include "dpdmai.h"
+#include "dpaa2-qdma.h"
+
+static bool smmu_disable = true;
+
+static struct dpaa2_qdma_chan *to_dpaa2_qdma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct dpaa2_qdma_chan, vchan.chan);
+}
+
+static struct dpaa2_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct dpaa2_qdma_comp, vdesc);
+}
+
+static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma;
+ struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev;
+
+ dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev,
+ sizeof(struct dpaa2_fd),
+ sizeof(struct dpaa2_fd), 0);
+ if (!dpaa2_chan->fd_pool)
+ goto err;
+
+ dpaa2_chan->fl_pool = dma_pool_create("fl_pool", dev,
+ sizeof(struct dpaa2_fl_entry),
+ sizeof(struct dpaa2_fl_entry), 0);
+ if
RE: [EXT] Re: [V4 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
Hi Vinod, Ok, thanks. I will resend them after next Monday. Best Regards, Peng >-Original Message- >From: Vinod Koul >Sent: 2019年9月26日 0:34 >To: Peng Ma >Cc: dan.j.willi...@intel.com; Leo Li ; >linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org >Subject: Re: [EXT] Re: [V4 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 >qDMA controller driver for Layerscape SoCs > >Caution: EXT Email > >On 25-09-19, 02:27, Peng Ma wrote: > >> >Can you please resend me after rc1 is out and I will review it and do >> >the needful >> [Peng Ma] Got it. By the way, when will rc1 out? > >It is supposed to be out on coming monday! > >-- >~Vinod
RE: [EXT] Re: [V4 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
Hi Vinod, >-Original Message- >From: Vinod Koul >Sent: 2019年9月25日 3:35 >To: Peng Ma >Cc: dan.j.willi...@intel.com; Leo Li ; >linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org >Subject: Re: [EXT] Re: [V4 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 >qDMA controller driver for Layerscape SoCs > >Caution: EXT Email > >Hey Peng, > >On 11-09-19, 02:01, Peng Ma wrote: >> Hi Vinod, >> >> I send those series patchs(V5) on June 25, 2019. I haven't received >> any comments yet. Their current state is "Not Applicable", so please let me >know what I need to do next. >> Thanks very much for your comments. >> >> Patch link: >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc >> >hwork.kernel.org%2Fpatch%2F11015035%2F&data=02%7C01%7Cpeng.m >a%40nx >> >p.com%7Cfe0293a83eb8472787d308d74126682c%7C686ea1d3bc2b4c6fa92c >d99c5c3 >> >01635%7C0%7C0%7C637049505521024467&sdata=qkij6By7Hku4eN7zo >CnIkCK96 >> 7WnwE21W%2FVkWKibIBw%3D&reserved=0 >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc >> >hwork.kernel.org%2Fpatch%2F11015033%2F&data=02%7C01%7Cpeng.m >a%40nx >> >p.com%7Cfe0293a83eb8472787d308d74126682c%7C686ea1d3bc2b4c6fa92c >d99c5c3 >> >01635%7C0%7C0%7C637049505521024467&sdata=OeL5OfMJggMS3K7I >Z1yu9WWZ9 >> zSOSyWojr%2Bv7BL5BpU%3D&reserved=0 > >Am sorry this looks to have missed by me and my script updated the status. > >Can you please resend me after rc1 is out and I will review it and do the >needful [Peng Ma] Got it. By the way, when will rc1 out? Best Regards, Peng > >-- >~Vinod
RE: [EXT] Re: [V4 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
Hi Vinod,
I send those series patchs(V5) on June 25, 2019. I haven't received any
comments yet. Their current state
is "Not Applicable", so please let me know what I need to do next.
Thanks very much for your comments.
Patch link:
https://patchwork.kernel.org/patch/11015035/
https://patchwork.kernel.org/patch/11015033/
Best Regards,
Peng
>-Original Message-
>From: Vinod Koul
>Sent: 2019年6月25日 0:46
>To: Peng Ma
>Cc: dan.j.willi...@intel.com; Leo Li ;
>linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org
>Subject: [EXT] Re: [V4 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA
>controller driver for Layerscape SoCs
>
>Caution: EXT Email
>
>On 13-06-19, 10:13, Peng Ma wrote:
>> DPPA2(Data Path Acceleration Architecture 2) qDMA supports channel
>> virtualization by allowing DMA
>
>typo virtualization
>
>> jobs to be enqueued into different frame queues.
>> Core can initiate a DMA transaction by preparing a frame
>> descriptor(FD) for each DMA job and enqueuing this job to a frame
>> queue. through a hardware portal. The qDMA
> ^^^
>why this full stop?
>
>> +static struct dpaa2_qdma_comp *
>> +dpaa2_qdma_request_desc(struct dpaa2_qdma_chan *dpaa2_chan) {
>> + struct dpaa2_qdma_comp *comp_temp = NULL;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&dpaa2_chan->queue_lock, flags);
>> + if (list_empty(&dpaa2_chan->comp_free)) {
>> + spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags);
>> + comp_temp = kzalloc(sizeof(*comp_temp), GFP_NOWAIT);
>> + if (!comp_temp)
>> + goto err;
>> + comp_temp->fd_virt_addr =
>> + dma_pool_alloc(dpaa2_chan->fd_pool,
>GFP_NOWAIT,
>> +&comp_temp->fd_bus_addr);
>> + if (!comp_temp->fd_virt_addr)
>> + goto err_comp;
>> +
>> + comp_temp->fl_virt_addr =
>> + dma_pool_alloc(dpaa2_chan->fl_pool,
>GFP_NOWAIT,
>> +&comp_temp->fl_bus_addr);
>> + if (!comp_temp->fl_virt_addr)
>> + goto err_fd_virt;
>> +
>> + comp_temp->desc_virt_addr =
>> + dma_pool_alloc(dpaa2_chan->sdd_pool,
>GFP_NOWAIT,
>> +
>&comp_temp->desc_bus_addr);
>> + if (!comp_temp->desc_virt_addr)
>> + goto err_fl_virt;
>> +
>> + comp_temp->qchan = dpaa2_chan;
>> + return comp_temp;
>> + }
>> +
>> + comp_temp = list_first_entry(&dpaa2_chan->comp_free,
>> + struct dpaa2_qdma_comp, list);
>> + list_del(&comp_temp->list);
>> + spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags);
>> +
>> + comp_temp->qchan = dpaa2_chan;
>> +
>> + return comp_temp;
>> +
>> +err_fl_virt:
>
>no err logs? how will you know what went wrong?
>
>> +static enum
>> +dma_status dpaa2_qdma_tx_status(struct dma_chan *chan,
>> + dma_cookie_t cookie,
>> + struct dma_tx_state *txstate) {
>> + return dma_cookie_status(chan, cookie, txstate);
>
>why not set dma_cookie_status as this callback?
>
>> +static int __cold dpaa2_qdma_setup(struct fsl_mc_device *ls_dev) {
>> + struct dpaa2_qdma_priv_per_prio *ppriv;
>> + struct device *dev = &ls_dev->dev;
>> + struct dpaa2_qdma_priv *priv;
>> + u8 prio_def = DPDMAI_PRIO_NUM;
>> + int err = -EINVAL;
>> + int i;
>> +
>> + priv = dev_get_drvdata(dev);
>> +
>> + priv->dev = dev;
>> + priv->dpqdma_id = ls_dev->obj_desc.id;
>> +
>> + /* Get the handle for the DPDMAI this interface is associate with */
>> + err = dpdmai_open(priv->mc_io, 0, priv->dpqdma_id,
>&ls_dev->mc_handle);
>> + if (err) {
>> + dev_err(dev, "dpdmai_open() failed\n");
>> + return err;
>> + }
>> + dev_info(dev, "Opened dpdmai object successfully\n");
>
>this is noise in kernel, consider debug level
>
>> +static int __cold dpaa2_dpdmai_bind(struct dpaa2_qdma_priv *priv) {
>> + int err;
>> + int i, num;
>> + struct device *dev = priv->dev;
>> + struct dpaa2_qdma_priv_per_prio *ppriv;
>> + struct dpdmai_rx_queue_cfg rx_queue_cfg;
>> + struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
>
>the order is reverse than used in other fn, please stick to one style!
>--
>~Vinod
RE: [EXT] [BUG BISECT] Net boot fails on VF50 after "dmaengine: fsl-edma: support little endian for edma driver"
Hi Krzysztof, Got it. Thanks for your help Best Regards, Peng >-Original Message- >From: Krzysztof Kozlowski >Sent: 2019年7月4日 20:57 >To: Peng Ma >Cc: Vinod Koul ; dmaeng...@vger.kernel.org; >linux-kernel@vger.kernel.org; Fabio Estevam ; Leo >Li ; Andy Tang >Subject: Re: [EXT] [BUG BISECT] Net boot fails on VF50 after "dmaengine: >fsl-edma: support little endian for edma driver" > >Caution: EXT Email > >On Thu, 4 Jul 2019 at 04:10, Peng Ma wrote: >> >> Hi Krzysztof, >> >> I am sorry, It is my mistake to forget about VF50 used EDMA IP with little >endian. >> The Register(CHCFG0 - CHCFG15) of our platform designed as follows: >> *- >> --* >> | Offset | Big endian Register| Little endian Register| >> |-|--|-| >> | 0x0 | CHCFG0| CHCFG3 | >> |-|--|-| >> | 0x1 | CHCFG1| CHCFG2 | >> |-|--|-| >> | 0x2 | CHCFG2| CHCFG1 | >> |-|--|-| >> | 0x3 | CHCFG3| CHCFG0 | >> |-|--|-| >> | ... |.. | .. | >> |-|--|-| >> | 0xC | CHCFG12 | CHCFG15 | >> |-|--|-| >> | 0xD | CHCFG13 | CHCFG14 | >> |-|--|-| >> | 0xE | CHCFG14 | CHCFG13 | >> |-|--|-| >> | 0xF | CHCFG15 | CHCFG12 | >> *- >> --* >> >> So we need this patch, I make some changes,Please help me to test >> attatchment on VF50 board, Thanks. > >With the patch VF50 boots fine. > >BTW, Colibri VF50 nicely boots from network almost out of the box so it is easy >to add it to automated tests for simple boot tests. This way you do not have to >manually test it on such platform... > >Best regards, >Krzysztof
RE: [EXT] [BUG BISECT] Net boot fails on VF50 after "dmaengine: fsl-edma: support little endian for edma driver"
Hi Fabio, Thanks very much for your suggestion, I will do some changes then to Send upstream review. Best Regards, Peng >-Original Message- >From: Fabio Estevam >Sent: 2019年7月4日 20:07 >To: Peng Ma >Cc: Krzysztof Kozłowski ; Vinod Koul >; dmaeng...@vger.kernel.org; >linux-kernel@vger.kernel.org; Fabio Estevam ; Leo >Li ; Andy Tang >Subject: Re: [EXT] [BUG BISECT] Net boot fails on VF50 after "dmaengine: >fsl-edma: support little endian for edma driver" > >Caution: EXT Email > >Hi Peng, > >On Wed, Jul 3, 2019 at 11:10 PM Peng Ma wrote: > >> So we need this patch, I make some changes,Please help me to test >attatchment on VF50 board, > >You need to change the Subject to something like: > >Subject: [PATCH] dmaengine: fsl-edma: Add support for LS1028A > >Also, in the commit log, please change "Our platforms" to "LS1028A" > >Please remove this part: "Current eDMA driver does not support Little endian" > >,which is not correct.
RE: [EXT] [BUG BISECT] Net boot fails on VF50 after "dmaengine: fsl-edma: support little endian for edma driver"
Hi Krzysztof, I am sorry, It is my mistake to forget about VF50 used EDMA IP with little endian. The Register(CHCFG0 - CHCFG15) of our platform designed as follows: *---* | Offset | Big endian Register| Little endian Register| |-|--|-| | 0x0 | CHCFG0| CHCFG3 | |-|--|-| | 0x1 | CHCFG1| CHCFG2 | |-|--|-| | 0x2 | CHCFG2| CHCFG1 | |-|--|-| | 0x3 | CHCFG3| CHCFG0 | |-|--|-| | ... |.. | .. | |-|--|-| | 0xC | CHCFG12 | CHCFG15 | |-|--|-| | 0xD | CHCFG13 | CHCFG14 | |-|--|-| | 0xE | CHCFG14 | CHCFG13 | |-|--|-| | 0xF | CHCFG15 | CHCFG12 | *---* So we need this patch, I make some changes,Please help me to test attatchment on VF50 board, Thanks. Best Regards, Peng >-Original Message- >From: Krzysztof Kozłowski >Sent: 2019年7月2日 20:13 >To: Peng Ma ; Vinod Koul ; >dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org >Subject: [EXT] [BUG BISECT] Net boot fails on VF50 after "dmaengine: >fsl-edma: support little endian for edma driver" > >Caution: EXT Email > >Hi, > >Bisect pointed commit: >commit 002905eca5bedab08bafd9e32541670c7712 >Author: Peng Ma >Date: Thu Jun 13 10:27:08 2019 + >dmaengine: fsl-edma: support little endian for edma driver > >as a reason of NFSv4 root boot failures. Toradex Colibri VF50 (Cortex >A5) on Toradex Iris board. > >The user-space starts but hangs - a lot of messages are missing or seriously >delayed. > >Please revert the patch of fix it. If needed I can provide more details about >test >system - let me know. > >Full log attached. > >Best regards, >Krzysztof 0001-dmaengine-fsl-edma-support-little-endian-for-edma-dr.patch Description: 0001-dmaengine-fsl-edma-support-little-endian-for-edma-dr.patch
[V5 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
DPPA2(Data Path Acceleration Architecture 2) qDMA supports
virtualized channel by allowing DMA jobs to be enqueued into
different work queues. Core can initiate a DMA transaction by
preparing a frame descriptor(FD) for each DMA job and enqueuing
this job through a hardware portal. DPAA2 components can also
prepare a FD and enqueue a DMA job through a hardware portal.
The qDMA prefetches DMA jobs through DPAA2 hardware portal. It
then schedules and dispatches to internal DMA hardware engines,
which generate read and write requests. Both qDMA source data and
destination data can be either contiguous or non-contiguous using
one or more scatter/gather tables.
The qDMA supports global bandwidth flow control where all DMA
transactions are stalled if the bandwidth threshold has been reached.
Also supported are transaction based read throttling.
Add NXP dppa2 qDMA to support some of Layerscape SoCs.
such as: LS1088A, LS208xA, LX2, etc.
Signed-off-by: Peng Ma
---
changed for v5:
- Clean up the format and code.
- Update comments.
- Add error logs.
drivers/dma/Kconfig |2 +
drivers/dma/Makefile|1 +
drivers/dma/fsl-dpaa2-qdma/Kconfig |9 +
drivers/dma/fsl-dpaa2-qdma/Makefile |3 +
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 825 +++
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 153 ++
6 files changed, 993 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Kconfig
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Makefile
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 76859aa..e4dd9c6 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -673,6 +673,8 @@ source "drivers/dma/sh/Kconfig"
source "drivers/dma/ti/Kconfig"
+source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
+
# clients
comment "DMA Clients"
depends on DMA_ENGINE
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 5bddf6f..15a318d 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
+obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
obj-y += mediatek/
obj-y += qcom/
diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig
b/drivers/dma/fsl-dpaa2-qdma/Kconfig
new file mode 100644
index 000..258ed6b
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig
@@ -0,0 +1,9 @@
+menuconfig FSL_DPAA2_QDMA
+ tristate "NXP DPAA2 QDMA"
+ depends on ARM64
+ depends on FSL_MC_BUS && FSL_MC_DPIO
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ NXP Data Path Acceleration Architecture 2 QDMA driver,
+ using the NXP MC bus driver.
diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile
b/drivers/dma/fsl-dpaa2-qdma/Makefile
new file mode 100644
index 000..c1d0226
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# Makefile for the NXP DPAA2 qDMA controllers
+obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
new file mode 100644
index 000..c70a796
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
@@ -0,0 +1,825 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+#include "dpdmai.h"
+#include "dpaa2-qdma.h"
+
+static bool smmu_disable = true;
+
+static struct dpaa2_qdma_chan *to_dpaa2_qdma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct dpaa2_qdma_chan, vchan.chan);
+}
+
+static struct dpaa2_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct dpaa2_qdma_comp, vdesc);
+}
+
+static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma;
+ struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev;
+
+ dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev,
+ sizeof(struct dpaa2_fd),
+ sizeof(struct dpaa2_fd), 0);
+ if (!dpaa2_chan->fd_pool)
+ goto err;
+
+ dpaa2_chan->fl_pool = dma_pool_create("fl_pool", dev,
+ sizeof(struct dpaa2_fl_entry),
+ sizeof(struct dpaa2_fl_entry), 0);
+ if
[V5 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
The MC(Management Complex) exports the DPDMAI(Data Path DMA Interface)
object as an interface to operate the DPAA2(Data Path Acceleration
Architecture 2) qDMA Engine. The DPDMAI enables sending frame-based
requests to qDMA and receiving back confirmation response on transaction
completion, utilizing the DPAA2 QBMan(Queue Manager and Buffer Manager
hardware) infrastructure. DPDMAI object provides up to two priorities for
processing qDMA requests.
The following list summarizes the DPDMAI main features and capabilities:
1. Supports up to two scheduling priorities for processing
service requests.
- Each DPDMAI transmit queue is mapped to one of two service
priorities, allowing further prioritization in hardware between
requests from different DPDMAI objects.
2. Supports up to two receive queues for incoming transaction
completion confirmations.
- Each DPDMAI receive queue is mapped to one of two receive
priorities, allowing further prioritization between other
interfaces when associating the DPDMAI receive queues to DPIO
or DPCON(Data Path Concentrator) objects.
3. Supports different scheduling options for processing received
packets:
- Queues can be configured either in 'parked' mode (default),
or attached to a DPIO object, or attached to DPCON object.
4. Allows interaction with one or more DPIO objects for
dequeueing/enqueueing frame descriptors(FD) and for
acquiring/releasing buffers.
5. Supports enable, disable, and reset operations.
Add dpdmai to support some platforms with dpaa2 qdma engine.
Signed-off-by: Peng Ma
---
changed for v5:
- Clean up the format.
- Delete some useless struct and macro.
- Fix spell.
- Move the description of function from header to C file.
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 366 +++
drivers/dma/fsl-dpaa2-qdma/dpdmai.h | 177 +
2 files changed, 543 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.h
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
new file mode 100644
index 000..fbc2b2f
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+#include
+#include
+#include
+#include "dpdmai.h"
+
+struct dpdmai_rsp_get_attributes {
+ __le32 id;
+ u8 num_of_priorities;
+ u8 pad0[3];
+ __le16 major;
+ __le16 minor;
+};
+
+struct dpdmai_cmd_queue {
+ __le32 dest_id;
+ u8 priority;
+ u8 queue;
+ u8 dest_type;
+ u8 pad;
+ __le64 user_ctx;
+ union {
+ __le32 options;
+ __le32 fqid;
+ };
+};
+
+struct dpdmai_rsp_get_tx_queue {
+ __le64 pad;
+ __le32 fqid;
+};
+
+#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
+ ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPDMAI_CMD_CREATE(_cmd, _cfg) \
+do { \
+ typeof(_cmd) (cmd) = (_cmd); \
+ typeof(_cfg) (cfg) = (_cfg); \
+ MC_CMD_OP(cmd, 0, 8, 8, u8, (cfg)->priorities[0]);\
+ MC_CMD_OP(cmd, 0, 16, 8, u8, (cfg)->priorities[1]);\
+} while (0)
+
+static inline u64 mc_enc(int lsoffset, int width, u64 val)
+{
+ return (val & MAKE_UMASK64(width)) << lsoffset;
+}
+
+/**
+ * dpdmai_open() - Open a control session for the specified object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpdmai_id: DPDMAI unique ID
+ * @token: Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpdmai_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags,
+ int dpdmai_id, u16 *token)
+{
+ struct fsl_mc_command cmd = { 0 };
+ __le64 *cmd_dpdmai_id;
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
+ cmd_flags, 0);
+
+ cmd_dpdmai_id = cmd.params;
+ *cmd_dpdmai_id = cpu_to_le32(dpdmai_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
RE: [EXT] Re: [PATCH 2/4] arm64: dts: fsl: ls1028a: Add eDMA node
>-Original Message-
>From: Shawn Guo
>Sent: 2019年6月18日 21:13
>To: Peng Ma
>Cc: vk...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Leo Li
>; dan.j.willi...@intel.com; dmaeng...@vger.kernel.org;
>devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
>linux-arm-ker...@lists.infradead.org
>Subject: [EXT] Re: [PATCH 2/4] arm64: dts: fsl: ls1028a: Add eDMA node
>
>Caution: EXT Email
>
>On Mon, May 06, 2019 at 09:03:42AM +, Peng Ma wrote:
>> Add the eDMA device tree nodes for LS1028A devices
>>
>> Signed-off-by: Peng Ma
>> ---
>> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 +++
>> 1 files changed, 15 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
>b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
>> index 8116fb3..71b87cb 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
>> @@ -235,6 +235,21 @@
>> status = "disabled";
>> };
>>
>> + edma0: edma@22c {
>> + #dma-cells = <2>;
>> + compatible = "fsl,vf610-edma";
>> + reg = <0x0 0x22c 0x0 0x1>,
>> + <0x0 0x22d 0x0 0x1>,
>> + <0x0 0x22e 0x0 0x1>;
>> + interrupts = IRQ_TYPE_LEVEL_HIGH>,
>> + IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "edma-tx", "edma-err";
>> + dma-channels = <32>;
>> + clock-names = "dmamux0", "dmamux1";
>> + clocks = <&clockgen 4 1>,
>> + <&clockgen 4 1>;
>> + };
>> +
>
>The edma@22c node had already been added by commit below:
>
> f54f7be5c5ac ("arm64: dts: ls1028a: Add Audio DT nodes")
>
[Peng Ma] OK, got it, thanks.
Best Regards,
Peng
>Shawn
>
>> gpio1: gpio@230 {
>> compatible = "fsl,qoriq-gpio";
>> reg = <0x0 0x230 0x0 0x1>;
>> --
>> 1.7.1
>>
RE: [EXT] Re: [V3 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
Hi Vinod, >-Original Message- >From: Vinod Koul >Sent: 2019年6月13日 19:03 >To: Peng Ma >Cc: dan.j.willi...@intel.com; Leo Li ; >linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org >Subject: Re: [EXT] Re: [V3 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 >qDMA controller driver for Layerscape SoCs > >Caution: EXT Email > >On 10-06-19, 09:51, Peng Ma wrote: > >> >> + goto err; >> >> + >> >> + comp_temp->fl_virt_addr = >> >> + (void *)((struct dpaa2_fd *) >> >> + comp_temp->fd_virt_addr + 1); >> > >> >casts and pointer math, what could go wrong!! This doesnt smell right! >> > >> >> + comp_temp->fl_bus_addr = comp_temp->fd_bus_addr + >> >> + sizeof(struct dpaa2_fd); >> > >> >why not use fl_virt_addr and get the bus_address? >> What you mean is I should use virt_to_phys to get the bus_address? > >Yes instead of maintaining both pointers, just use one and then when required >use one to get other. For bus address I would prefer dma_map_single rather >than virt_to_phys() [Peng Ma] ok, thanks, I have already send V4 for this series patch, Please review it in your spare time. Patchwork link: https://patchwork.kernel.org/project/linux-dmaengine/list/?series=131767 Best Regars, Peng >-- >~Vinod
RE: [V4 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
Hi Vkoul,
>+int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags,
>+ u16 token, u8 priority,
>+ const struct dpdmai_rx_queue_cfg *cfg) {
>+ struct fsl_mc_command cmd = { 0 };
>+ struct dpdmai_cmd_queue *cmd_params;
>+
>+ /* prepare command */
>+ cmd.header =
>mc_encode_cmd_header(DPDMAI_CMDID_SET_RX_QUEUE,
>+cmd_flags,
>+token);
>+
>+ cmd_params = (struct dpdmai_cmd_queue *)cmd.params;
The MC(Management Complex) has may objects like DPDMAI, DPNI, DPIO, DPCON etc.
They have the same size command structure defined by struct fsl_mc_command
(include/linux/fsl/mc.h):
struct fsl_mc_command {
__le64 header;
__le64 params[7];
};
But different object and different operation(open , close, enable etc ) of
object with different command params, when we used DPDMAI,
the cmd_params should use cast to fit it. This makes it easy to program.
>+ cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id);
>+ cmd_params->priority = cfg->dest_cfg.priority;
>+ cmd_params->queue = priority;
>+ cmd_params->dest_type = cfg->dest_cfg.dest_type;
>+ cmd_params->user_ctx = cpu_to_le64(cfg->user_ctx);
>+ cmd_params->options = cpu_to_le32(cfg->options);
>+
>+ /* send command to mc*/
>+ return mc_send_command(mc_io, &cmd);
>+}
Best Regards,
Peng
>-Original Message-
>From: Peng Ma
>Sent: 2019年6月13日 18:14
>To: vk...@kernel.org; dan.j.willi...@intel.com; Leo Li
>Cc: linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org; Peng Ma
>
>Subject: [V4 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path
>DMA Interface) support
>
>The MC(Management Complex) exports the DPDMAI(Data Path DMA Interface)
>object as an interface to operate the DPAA2(Data Path Acceleration
>Architecture 2) qDMA Engine. The DPDMAI enables sending frame-based
>requests to qDMA and receiving back confirmation response on transaction
>completion, utilizing the DPAA2 QBMan(Queue Manager and Buffer Manager
>hardware) infrastructure. DPDMAI object provides up to two priorities for
>processing qDMA requests.
>The following list summarizes the DPDMAI main features and capabilities:
> 1. Supports up to two scheduling priorities for processing
> service requests.
> - Each DPDMAI transmit queue is mapped to one of two service
> priorities, allowing further prioritization in hardware between
> requests from different DPDMAI objects.
> 2. Supports up to two receive queues for incoming transaction
> completion confirmations.
> - Each DPDMAI receive queue is mapped to one of two receive
> priorities, allowing further prioritization between other
> interfaces when associating the DPDMAI receive queues to DPIO
> or DPCON(Data Path Concentrator) objects.
> 3. Supports different scheduling options for processing received
> packets:
> - Queues can be configured either in 'parked' mode (default),
> oattached to a DPIO object, or attached to DPCON object.
> 4. Allows interaction with one or more DPIO objects for
> dequeueing/enqueueing frame descriptors(FD) and for
> acquiring/releasing buffers.
> 5. Supports enable, disable, and reset operations.
>
>Add dpdmai to support some platforms with dpaa2 qdma engine.
>
>Signed-off-by: Peng Ma
>---
>changed for v4:
> - Delete dpdmai_cmd.h.
> - Remove some useless functions.
> - Clean up the format.
> - Update Copyright.
>
> drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 275
>++
>drivers/dma/fsl-dpaa2-qdma/dpdmai.h | 318
>+++
> 2 files changed, 593 insertions(+), 0 deletions(-) create mode 100644
>drivers/dma/fsl-dpaa2-qdma/dpdmai.c
> create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.h
>
>diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
>b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
>new file mode 100644
>index 000..4dba154
>--- /dev/null
>+++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
>@@ -0,0 +1,275 @@
>+// SPDX-License-Identifier: GPL-2.0
>+// Copyright 2019 NXP
>+
>+#include
>+#include
>+#include
>+#include "dpdmai.h"
>+
>+struct dpdmai_cmd_open {
>+ __le32 dpdmai_id;
>+};
>+
>+struct dpdmai_rsp_get_attributes {
>+ __le32 id;
>+ u8 num_of_priorities;
>+ u8 pad0[3];
>+ __le16 major;
>+ __le16 minor;
>+};
>+
>+struct dpdmai_cmd_queue {
>+ __le32 dest_id;
>+ u8 priority;
>+ u8 queue;
>+ u8 dest_type;
>+
[V4 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
The MC(Management Complex) exports the DPDMAI(Data Path DMA Interface)
object as an interface to operate the DPAA2(Data Path Acceleration
Architecture 2) qDMA Engine. The DPDMAI enables sending frame-based
requests to qDMA and receiving back confirmation response on transaction
completion, utilizing the DPAA2 QBMan(Queue Manager and Buffer Manager
hardware) infrastructure. DPDMAI object provides up to two priorities for
processing qDMA requests.
The following list summarizes the DPDMAI main features and capabilities:
1. Supports up to two scheduling priorities for processing
service requests.
- Each DPDMAI transmit queue is mapped to one of two service
priorities, allowing further prioritization in hardware between
requests from different DPDMAI objects.
2. Supports up to two receive queues for incoming transaction
completion confirmations.
- Each DPDMAI receive queue is mapped to one of two receive
priorities, allowing further prioritization between other
interfaces when associating the DPDMAI receive queues to DPIO
or DPCON(Data Path Concentrator) objects.
3. Supports different scheduling options for processing received
packets:
- Queues can be configured either in 'parked' mode (default),
oattached to a DPIO object, or attached to DPCON object.
4. Allows interaction with one or more DPIO objects for
dequeueing/enqueueing frame descriptors(FD) and for
acquiring/releasing buffers.
5. Supports enable, disable, and reset operations.
Add dpdmai to support some platforms with dpaa2 qdma engine.
Signed-off-by: Peng Ma
---
changed for v4:
- Delete dpdmai_cmd.h.
- Remove some useless functions.
- Clean up the format.
- Update Copyright.
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 275 ++
drivers/dma/fsl-dpaa2-qdma/dpdmai.h | 318 +++
2 files changed, 593 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.h
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
new file mode 100644
index 000..4dba154
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+#include
+#include
+#include
+#include "dpdmai.h"
+
+struct dpdmai_cmd_open {
+ __le32 dpdmai_id;
+};
+
+struct dpdmai_rsp_get_attributes {
+ __le32 id;
+ u8 num_of_priorities;
+ u8 pad0[3];
+ __le16 major;
+ __le16 minor;
+};
+
+struct dpdmai_cmd_queue {
+ __le32 dest_id;
+ u8 priority;
+ u8 queue;
+ u8 dest_type;
+ u8 pad;
+ __le64 user_ctx;
+ union {
+ __le32 options;
+ __le32 fqid;
+ };
+};
+
+struct dpdmai_rsp_get_tx_queue {
+ __le64 pad;
+ __le32 fqid;
+};
+
+#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
+ ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
+
+#define MC_CMD_HDR_READ_TOKEN(_hdr) \
+ ((u16)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S))
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPDMAI_CMD_CREATE(_cmd, _cfg) \
+do { \
+ typeof(_cmd) (cmd) = (_cmd); \
+ typeof(_cfg) (cfg) = (_cfg); \
+ MC_CMD_OP(cmd, 0, 8, 8, u8, (cfg)->priorities[0]);\
+ MC_CMD_OP(cmd, 0, 16, 8, u8, (cfg)->priorities[1]);\
+} while (0)
+
+static inline u64 mc_enc(int lsoffset, int width, u64 val)
+{
+ return (u64)(((u64)val & MAKE_UMASK64(width)) << lsoffset);
+}
+
+static inline u64 mc_dec(u64 val, int lsoffset, int width)
+{
+ return (u64)((val >> lsoffset) & MAKE_UMASK64(width));
+}
+
+int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags,
+ int dpdmai_id, u16 *token)
+{
+ struct fsl_mc_command cmd = { 0 };
+ struct dpdmai_cmd_open *cmd_params;
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
+ cmd_flags, 0);
+
+ cmd_params = (struct dpdmai_cmd_open *)cmd.params;
+ cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = mc_cmd_hdr_read_token(&cmd);
+ return 0;
+}
+
+int dpdmai_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
+{
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLOSE,
+ cmd_flags, token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+
[V4 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
DPPA2(Data Path Acceleration Architecture 2) qDMA
supports channel virtualization by allowing DMA
jobs to be enqueued into different frame queues.
Core can initiate a DMA transaction by preparing a frame
descriptor(FD) for each DMA job and enqueuing this job to
a frame queue. through a hardware portal. The qDMA
prefetches DMA jobs from the frame queues. It then
schedules and dispatches to internal DMA hardware engines,
which generate read and write requests. Both qDMA source
data and destination data can be either contiguous or
non-contiguous using one or more scatter/gather tables.
The qDMA supports global bandwidth flow control where all
DMA transactions are stalled if the bandwidth threshold
has been reached. Also supported are transaction based
read throttling.
Add NXP dppa2 qDMA to support some of Layerscape SoCs.
such as: LS1088A, LS208xA, LX2, etc.
Signed-off-by: Peng Ma
---
changed for v4:
- Delete casts.
- Add dma pool for each descriptor.
- Improve clean up for qdma init.
- Update Copyright.
drivers/dma/Kconfig |2 +
drivers/dma/Makefile|1 +
drivers/dma/fsl-dpaa2-qdma/Kconfig |9 +
drivers/dma/fsl-dpaa2-qdma/Makefile |3 +
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 826 +++
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 153 ++
6 files changed, 994 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Kconfig
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Makefile
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index eaf78f4..08aae01 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -671,6 +671,8 @@ source "drivers/dma/sh/Kconfig"
source "drivers/dma/ti/Kconfig"
+source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
+
# clients
comment "DMA Clients"
depends on DMA_ENGINE
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 6126e1c..2499ed8 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
+obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
obj-y += mediatek/
obj-y += qcom/
diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig
b/drivers/dma/fsl-dpaa2-qdma/Kconfig
new file mode 100644
index 000..258ed6b
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig
@@ -0,0 +1,9 @@
+menuconfig FSL_DPAA2_QDMA
+ tristate "NXP DPAA2 QDMA"
+ depends on ARM64
+ depends on FSL_MC_BUS && FSL_MC_DPIO
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ NXP Data Path Acceleration Architecture 2 QDMA driver,
+ using the NXP MC bus driver.
diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile
b/drivers/dma/fsl-dpaa2-qdma/Makefile
new file mode 100644
index 000..c1d0226
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# Makefile for the NXP DPAA2 qDMA controllers
+obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
new file mode 100644
index 000..a5fbf55
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
@@ -0,0 +1,826 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+#include "dpdmai.h"
+#include "dpaa2-qdma.h"
+
+static bool smmu_disable = true;
+
+static struct dpaa2_qdma_chan *to_dpaa2_qdma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct dpaa2_qdma_chan, vchan.chan);
+}
+
+static struct dpaa2_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct dpaa2_qdma_comp, vdesc);
+}
+
+static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma;
+ struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev;
+
+ dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev,
+ sizeof(struct dpaa2_fd),
+ sizeof(struct dpaa2_fd), 0);
+ if (!dpaa2_chan->fd_pool)
+ goto err;
+
+ dpaa2_chan->fl_pool = dma_pool_create("fl_pool", dev,
+ sizeof(struct dpaa2_fl_entry),
+ sizeof(struct dpaa2_fl_entry), 0);
+ if (!dpaa2_chan->fl_pool)
+
[V2] dmaengine: fsl-edma: support little endian for edma driver
Our platforms with below registers(CHCFG0 - CHCFG15) of eDMA
*---*
| Offset | Big endian Register| Little endian Register|
|--||---|
| 0x0 |CHCFG0 | CHCFG3 |
|--||---|
| 0x1 |CHCFG1 | CHCFG2 |
|--||---|
| 0x2 |CHCFG2 | CHCFG1 |
|--||---|
| 0x3 |CHCFG3 | CHCFG0 |
|--||---|
| ... |.. | .. |
|--||---|
| 0xC |CHCFG12 | CHCFG15 |
|--||---|
| 0xD |CHCFG13 | CHCFG14 |
|--||---|
| 0xE |CHCFG14 | CHCFG13 |
|--||---|
| 0xF |CHCFG15 | CHCFG12 |
*---*
Current eDMA driver does not support Little endian, so this
patch is to improve edma driver to support little endian.
Signed-off-by: Peng Ma
---
Changed fo v2:
- Add details fo comments.
drivers/dma/fsl-edma-common.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 680b2a0..6bf238e 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -83,9 +83,14 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
u32 ch = fsl_chan->vchan.chan.chan_id;
void __iomem *muxaddr;
unsigned int chans_per_mux, ch_off;
+ int endian_diff[4] = {3, 1, -1, -3};
chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
+
+ if (!fsl_chan->edma->big_endian)
+ ch_off += endian_diff[ch_off % 4];
+
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
slot = EDMAMUX_CHCFG_SOURCE(slot);
--
1.7.1
RE: [EXT] Re: [V3 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
Hi, Vinod, Please see my comments inline, thanks very much. Best Regards, Peng >-Original Message- >From: Vinod Koul >Sent: 2019年4月29日 13:32 >To: Peng Ma >Cc: dan.j.willi...@intel.com; Leo Li ; >linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org >Subject: [EXT] Re: [V3 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA >controller driver for Layerscape SoCs > >Caution: EXT Email > >On 09-04-19, 15:22, Peng Ma wrote: >> DPPA2(Data Path Acceleration Architecture 2) qDMA The qDMA supports >> channel virtualization by allowing DMA jobs to be enqueued into >> different frame queues. Core can initiate a DMA transaction by >> preparing a frame descriptor(FD) for each DMA job and enqueuing this job to >a frame queue. >> through a hardware portal. The qDMA prefetches DMA jobs from the frame >queues. >> It then schedules and dispatches to internal DMA hardware engines, >> which generate read and write requests. Both qDMA source data and >> destination data can be either contiguous or non-contiguous using one or >more scatter/gather tables. >> The qDMA supports global bandwidth flow control where all DMA >> transactions are stalled if the bandwidth threshold has been reached. >> Also supported are transaction based read throttling. >> >> Add NXP dppa2 qDMA to support some of Layerscape SoCs. >> such as: LS1088A, LS208xA, LX2, etc. >> >> Signed-off-by: Peng Ma >> --- >> changed for v3: >> - Add depends on arm64 for dpaa2 qdma driver >> - The dpaa2_io_service_[de]register functions have a new >parameter >> So update all calls to some functions >> >> drivers/dma/Kconfig |2 + >> drivers/dma/Makefile|1 + >> drivers/dma/fsl-dpaa2-qdma/Kconfig |9 + >> drivers/dma/fsl-dpaa2-qdma/Makefile |3 + >> drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 782 >> +++ >> drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 152 ++ >> 6 files changed, 949 insertions(+), 0 deletions(-) create mode >> 100644 drivers/dma/fsl-dpaa2-qdma/Kconfig >> create mode 100644 drivers/dma/fsl-dpaa2-qdma/Makefile >> create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c >> create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h >> >> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index >> eaf78f4..08aae01 100644 >> --- a/drivers/dma/Kconfig >> +++ b/drivers/dma/Kconfig >> @@ -671,6 +671,8 @@ source "drivers/dma/sh/Kconfig" >> >> source "drivers/dma/ti/Kconfig" >> >> +source "drivers/dma/fsl-dpaa2-qdma/Kconfig" >> + >> # clients >> comment "DMA Clients" >> depends on DMA_ENGINE >> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index >> 6126e1c..2499ed8 100644 >> --- a/drivers/dma/Makefile >> +++ b/drivers/dma/Makefile >> @@ -75,6 +75,7 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += >uniphier-mdmac.o >> obj-$(CONFIG_XGENE_DMA) += xgene-dma.o >> obj-$(CONFIG_ZX_DMA) += zx_dma.o >> obj-$(CONFIG_ST_FDMA) += st_fdma.o >> +obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/ >> >> obj-y += mediatek/ >> obj-y += qcom/ >> diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig >> b/drivers/dma/fsl-dpaa2-qdma/Kconfig >> new file mode 100644 >> index 000..258ed6b >> --- /dev/null >> +++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig >> @@ -0,0 +1,9 @@ >> +menuconfig FSL_DPAA2_QDMA >> + tristate "NXP DPAA2 QDMA" >> + depends on ARM64 >> + depends on FSL_MC_BUS && FSL_MC_DPIO >> + select DMA_ENGINE >> + select DMA_VIRTUAL_CHANNELS >> + help >> + NXP Data Path Acceleration Architecture 2 QDMA driver, >> + using the NXP MC bus driver. >> diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile >> b/drivers/dma/fsl-dpaa2-qdma/Makefile >> new file mode 100644 >> index 000..c1d0226 >> --- /dev/null >> +++ b/drivers/dma/fsl-dpaa2-qdma/Makefile >> @@ -0,0 +1,3 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> +# Makefile for the NXP DPAA2 qDMA controllers >> +obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o >> diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c >> b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c >> new file mode 100644 >> index 000..0cdde0f >> --- /dev/null >> +++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c >> @@ -0,0 +1,782 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +// Copyright 2014-2018 NXP >> + >> +/* >> +
RE: [EXT] Re: [V3 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
Hi Vinod
Sorry to replay so late.
The dpaa2 qdma driver is based on FSL_MC_BUS and FSL_MC_DPIO, so It will used
those two drivers
Functions or structs. This patch provides some necessary functions and structs
for qdma driver(next patch: dpaa2-qdma.c)
The dpaa2 driver is not only to write some register on driver side but also
need enable FSL_MC_BUS and FSL_MC_DPIO to
call some functions provided by them. Such as: mc_encode_cmd_header,
mc_send_command etc. I will clear up this driver
again. And send V4 to review, thanks for your review.
Best Regards,
Peng
>-Original Message-
>From: Vinod Koul
>Sent: 2019年4月26日 20:46
>To: Peng Ma
>Cc: dan.j.willi...@intel.com; Leo Li ;
>linux-kernel@vger.kernel.org; dmaeng...@vger.kernel.org
>Subject: [EXT] Re: [V3 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data
>Path DMA Interface) support
>
>Caution: EXT Email
>
>On 09-04-19, 15:22, Peng Ma wrote:
>
>Subject missed PATCH tag!
>
>> The MC exports the DPDMAI object as an interface to operate the DPAA2
>> QDMA
>
>whats MC, DPDMAI, DPAA2
>
[Peng Ma] MC: Management Complex
DPDMAI: Data Path DMA Interface
DPAA2: Data Path Acceleration Architecture, Second Generation
I will explain them on next version.
>> Engine. The DPDMAI enables sending frame-based requests to QDMA and
>> receiving back confirmation response on transaction completion,
>> utilizing the DPAA2 QBMan infrastructure. DPDMAI object provides up to
>> two priorities for processing QDMA requests.
>
>> +int dpdmai_open(struct fsl_mc_io *mc_io,
>> + u32 cmd_flags,
>> + int dpdmai_id,
>> + u16 *token)
>
>could be written as:
>
>int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags,
>int dpdmai_id, u16 *token)
>
>Looks neater, right? It would be to reread coding guidelines and run checkpatch
>with --strict on this
>
[Peng Ma] Ok, got it.
>
>> +{
>> + struct fsl_mc_command cmd = { 0 };
>
>where is this defined?
[Peng Ma] include/linux/fsl/mc.h
>
>> + struct dpdmai_cmd_open *cmd_params;
>> + int err;
>> +
>> + /* prepare command */
>> + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
>> + cmd_flags,
>> + 0);
>> +
>> + cmd_params = (struct dpdmai_cmd_open *)cmd.params;
>
>I dont like casts, can you explain
[Peng Ma] If I didn't use the casts, There are two case:
1: struct fsl_mc_command cmd_org = { 0 };
Struct fsl_mc_command *cmd = &cmd_org;
In this case, we will define one more temporary variable in the stack.
2: Struct fsl_mc_command *cmd = kmalloc();
In this case, we will alloc some memory, It may be produce memory
Fragmentation. Those functions will be called on driver init It is not
necessary
use this case to those function.
>
>> + cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id);
>> +
>> + /* send command to mc*/
>> + err = mc_send_command(mc_io, &cmd);
>> + if (err)
>> + return err;
>> +
>> + /* retrieve response parameters */
>> + *token = mc_cmd_hdr_read_token(&cmd);
>> + return 0;
>> +}
>
>who will call this API?
>
[Peng Ma] This file is not a driver, some of functions define in this file, the
dma driver(dpaa2-qdma.c) will call some of those API and I will
delete unuseless API in the future.
>> +int dpdmai_create(struct fsl_mc_io *mc_io,
>> + u32 cmd_flags,
>> + const struct dpdmai_cfg *cfg,
>> + u16 *token)
>> +{
>> + struct fsl_mc_command cmd = { 0 };
>> + int err;
>> +
>> + /* prepare command */
>> + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CREATE,
>> + cmd_flags,
>> + 0);
>
>why waste a line, last arg can be in previous line!
>
[Peng Ma] sorry, I will remove it.
>> +int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io,
>> + u32 cmd_flags,
>> + u16 token,
>> + u8 priority,
>> + struct dpdmai_tx_queue_attr *attr) {
>> + struct fsl_mc_command cmd = { 0 };
>> + struct dpdmai_cmd_queue *cmd_params;
>> + struct dpdmai_rsp_get_tx_queue *rsp_params;
>> + int err;
>> +
>> + /* prepare command */
>> + cmd.header =
>mc_encode_cmd_header(DPDMAI_CMDID_GET_TX_QUEUE,
>> + cmd_flags,
>> + token);
>> +
>> + cmd_params = (struct dpdmai_cmd_queue *
[PATCH] arm64: dts: ls1028a: Enable sata.
Change the sata node to enable sata.
Signed-off-by: Peng Ma
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |4
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts |4
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index b359068..4ed1828 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -153,3 +153,7 @@
&sai1 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f9c272f..4a203f7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -151,3 +151,7 @@
&sai4 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
--
1.7.1
RE: [EXT] Re: [PATCH 3/4] dmaengine: fsl-edma: support little endian for edma driver
Hi Vinod,
Thank for you reply.
the registers (CHCFG0 - CHCFG15) on big endian socs as fallows:
CHCFG0 0x0
CHCFG1 0x1
CHCFG2 0x2
CHCFG3 0x3
..
CHCFG12 0xC
CHCFG13 0xD
CHCFG14 0xE
CHCFG15 0xF
On little endian socs as fallows:
CHCFG3 0x0
CHCFG2 0x1
CHCFG1 0x2
CHCFG0 0x3
..
CHCFG15 0xC
CHCFG14 0xD
CHCFG13 0xE
CHCFG12 0xF
To fit this map we should add this patch.
Best Regards,
Peng
>-Original Message-
>From: Vinod Koul
>Sent: 2019年5月21日 12:38
>To: Peng Ma
>Cc: robh...@kernel.org; shawn...@kernel.org; mark.rutl...@arm.com; Leo
>Li ; dan.j.willi...@intel.com;
>dmaeng...@vger.kernel.org; devicet...@vger.kernel.org;
>linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org
>Subject: [EXT] Re: [PATCH 3/4] dmaengine: fsl-edma: support little endian for
>edma driver
>
>Caution: EXT Email
>
>On 06-05-19, 09:03, Peng Ma wrote:
>> improve edma driver to support little endian.
>
>Can you explain a bit more how adding the below lines adds little endian
>support...
>
>>
>> Signed-off-by: Peng Ma
>> ---
>> drivers/dma/fsl-edma-common.c |5 +
>> 1 files changed, 5 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/dma/fsl-edma-common.c
>> b/drivers/dma/fsl-edma-common.c index 680b2a0..6bf238e 100644
>> --- a/drivers/dma/fsl-edma-common.c
>> +++ b/drivers/dma/fsl-edma-common.c
>> @@ -83,9 +83,14 @@ void fsl_edma_chan_mux(struct fsl_edma_chan
>*fsl_chan,
>> u32 ch = fsl_chan->vchan.chan.chan_id;
>> void __iomem *muxaddr;
>> unsigned int chans_per_mux, ch_off;
>> + int endian_diff[4] = {3, 1, -1, -3};
>>
>> chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
>> ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
>> +
>> + if (!fsl_chan->edma->big_endian)
>> + ch_off += endian_diff[ch_off % 4];
>> +
>> muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
>> slot = EDMAMUX_CHCFG_SOURCE(slot);
>>
>> --
>> 1.7.1
>
>--
>~Vinod
[V3 1/2] dmaengine: fsl-qdma: fixed the source/destination descriptor format
CMD of Source/Destination descriptor format should be lower of
struct fsl_qdma_engine number data address.
Signed-off-by: Peng Ma
---
changed for V3:
- Delete macro to simplify code.
drivers/dma/fsl-qdma.c | 18 ++
1 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
index aa1d0ae..da8fdf5 100644
--- a/drivers/dma/fsl-qdma.c
+++ b/drivers/dma/fsl-qdma.c
@@ -113,6 +113,7 @@
/* Field definition for Descriptor offset */
#define QDMA_CCDF_STATUS 20
#define QDMA_CCDF_OFFSET 20
+#define QDMA_SDDF_CMD(x) (((u64)(x)) << 32)
/* Field definition for safe loop count*/
#define FSL_QDMA_HALT_COUNT1500
@@ -341,6 +342,7 @@ static void fsl_qdma_free_chan_resources(struct dma_chan
*chan)
static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
dma_addr_t dst, dma_addr_t src, u32 len)
{
+ u32 cmd;
struct fsl_qdma_format *sdf, *ddf;
struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
@@ -369,14 +371,14 @@ static void fsl_qdma_comp_fill_memcpy(struct
fsl_qdma_comp *fsl_comp,
/* This entry is the last entry. */
qdma_csgf_set_f(csgf_dest, len);
/* Descriptor Buffer */
- sdf->data =
- cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
- FSL_QDMA_CMD_RWTTYPE_OFFSET);
- ddf->data =
- cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
- FSL_QDMA_CMD_RWTTYPE_OFFSET);
- ddf->data |=
- cpu_to_le64(FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET);
+ cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
+ FSL_QDMA_CMD_RWTTYPE_OFFSET);
+ sdf->data = QDMA_SDDF_CMD(cmd);
+
+ cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
+ FSL_QDMA_CMD_RWTTYPE_OFFSET);
+ cmd |= cpu_to_le32(FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET);
+ ddf->data = QDMA_SDDF_CMD(cmd);
}
/*
--
1.7.1
[V3 2/2] dmaengine: fsl-qdma: Add improvement
When an error occurs we should clean the error register then to return
Signed-off-by: Peng Ma
---
changed for V3:
- no changed.
drivers/dma/fsl-qdma.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
index da8fdf5..8e341c0 100644
--- a/drivers/dma/fsl-qdma.c
+++ b/drivers/dma/fsl-qdma.c
@@ -703,10 +703,8 @@ static irqreturn_t fsl_qdma_error_handler(int irq, void
*dev_id)
intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
- if (intr) {
+ if (intr)
dev_err(fsl_qdma->dma_dev.dev, "DMA transaction error!\n");
- return IRQ_NONE;
- }
qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
return IRQ_HANDLED;
--
1.7.1
[PATCH 3/4] dmaengine: fsl-edma: support little endian for edma driver
improve edma driver to support little endian.
Signed-off-by: Peng Ma
---
drivers/dma/fsl-edma-common.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 680b2a0..6bf238e 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -83,9 +83,14 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
u32 ch = fsl_chan->vchan.chan.chan_id;
void __iomem *muxaddr;
unsigned int chans_per_mux, ch_off;
+ int endian_diff[4] = {3, 1, -1, -3};
chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
+
+ if (!fsl_chan->edma->big_endian)
+ ch_off += endian_diff[ch_off % 4];
+
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
slot = EDMAMUX_CHCFG_SOURCE(slot);
--
1.7.1
[PATCH 2/4] arm64: dts: fsl: ls1028a: Add eDMA node
Add the eDMA device tree nodes for LS1028A devices
Signed-off-by: Peng Ma
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 8116fb3..71b87cb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -235,6 +235,21 @@
status = "disabled";
};
+ edma0: edma@22c {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x22c 0x0 0x1>,
+ <0x0 0x22d 0x0 0x1>,
+ <0x0 0x22e 0x0 0x1>;
+ interrupts = ,
+;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen 4 1>,
+<&clockgen 4 1>;
+ };
+
gpio1: gpio@230 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x230 0x0 0x1>;
--
1.7.1
[PATCH 4/4] dt-bindings: fsl-qdma: Add LS1028A qDMA bindings
Add LS1028A qDMA controller bindings to fsl-qdma bindings. Signed-off-by: Peng Ma --- Documentation/devicetree/bindings/dma/fsl-qdma.txt |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt index 6a0ff90..da371c4 100644 --- a/Documentation/devicetree/bindings/dma/fsl-qdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt @@ -7,6 +7,7 @@ Required properties: - compatible: Must be one of "fsl,ls1021a-qdma": for LS1021A Board +"fsl,ls1028a-qdma": for LS1028A Board "fsl,ls1043a-qdma": for ls1043A Board "fsl,ls1046a-qdma": for ls1046A Board - reg: Should contain the register's base address and length. -- 1.7.1
[PATCH 1/4] arm64: dts: fsl: ls1028a: Add qDMA node
Add the qDMA device tree nodes for LS1028A devices
Signed-off-by: Peng Ma
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2896bbc..8116fb3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -336,6 +336,26 @@
,
;
};
+ qdma: dma-controller@838 {
+ compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
+ reg = <0x0 0x838 0x0 0x1000>, /* Controller regs */
+ <0x0 0x839 0x0 0x1>, /* Status regs */
+ <0x0 0x83a 0x0 0x4>; /* Block regs */
+ interrupts = ,
+,
+,
+,
+;
+ interrupt-names = "qdma-error", "qdma-queue0",
+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
+ dma-channels = <8>;
+ block-number = <1>;
+ block-offset = <0x1>;
+ fsl,dma-queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ };
+
pcie@1f000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
reg = <0x01 0xf000 0x0 0x10>;
--
1.7.1
[V2 2/2] dmaengine: fsl-qdma: Add improvement
When an error occurs we should clean the error register then to return
Signed-off-by: Peng Ma
---
changed for V2:
- Separate one patch to two patchs
drivers/dma/fsl-qdma.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
index 2e8b46b..542765a 100644
--- a/drivers/dma/fsl-qdma.c
+++ b/drivers/dma/fsl-qdma.c
@@ -710,10 +710,8 @@ static irqreturn_t fsl_qdma_error_handler(int irq, void
*dev_id)
intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
- if (intr) {
+ if (intr)
dev_err(fsl_qdma->dma_dev.dev, "DMA transaction error!\n");
- return IRQ_NONE;
- }
qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
return IRQ_HANDLED;
--
1.7.1
[V2 1/2] dmaengine: fsl-qdma: fixed the source/destination descriptor format
CMD of Source/Destination descriptor format should be lower of
struct fsl_qdma_engine number data address.
Signed-off-by: Peng Ma
---
changed for V2:
- Fix descriptor spelling
drivers/dma/fsl-qdma.c | 25 +
1 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
index aa1d0ae..2e8b46b 100644
--- a/drivers/dma/fsl-qdma.c
+++ b/drivers/dma/fsl-qdma.c
@@ -113,6 +113,7 @@
/* Field definition for Descriptor offset */
#define QDMA_CCDF_STATUS 20
#define QDMA_CCDF_OFFSET 20
+#define QDMA_SDDF_CMD(x) (((u64)(x)) << 32)
/* Field definition for safe loop count*/
#define FSL_QDMA_HALT_COUNT1500
@@ -214,6 +215,12 @@ struct fsl_qdma_engine {
};
+static inline void
+qdma_sddf_set_cmd(struct fsl_qdma_format *sddf, u32 val)
+{
+ sddf->data = QDMA_SDDF_CMD(val);
+}
+
static inline u64
qdma_ccdf_addr_get64(const struct fsl_qdma_format *ccdf)
{
@@ -341,6 +348,7 @@ static void fsl_qdma_free_chan_resources(struct dma_chan
*chan)
static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
dma_addr_t dst, dma_addr_t src, u32 len)
{
+ u32 cmd;
struct fsl_qdma_format *sdf, *ddf;
struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
@@ -353,6 +361,7 @@ static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp
*fsl_comp,
memset(fsl_comp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE);
memset(fsl_comp->desc_virt_addr, 0, FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
+
/* Head Command Descriptor(Frame Descriptor) */
qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(ccdf));
@@ -369,14 +378,14 @@ static void fsl_qdma_comp_fill_memcpy(struct
fsl_qdma_comp *fsl_comp,
/* This entry is the last entry. */
qdma_csgf_set_f(csgf_dest, len);
/* Descriptor Buffer */
- sdf->data =
- cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
- FSL_QDMA_CMD_RWTTYPE_OFFSET);
- ddf->data =
- cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
- FSL_QDMA_CMD_RWTTYPE_OFFSET);
- ddf->data |=
- cpu_to_le64(FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET);
+ cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
+ FSL_QDMA_CMD_RWTTYPE_OFFSET);
+ qdma_sddf_set_cmd(sdf, cmd);
+
+ cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
+ FSL_QDMA_CMD_RWTTYPE_OFFSET);
+ cmd |= cpu_to_le32(FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET);
+ qdma_sddf_set_cmd(ddf, cmd);
}
/*
--
1.7.1
RE: [EXT] Re: [PATCH] dmaengine: fsl-qdma: fixed the source/destination descriptior format
>-Original Message-
>From: Vinod Koul
>Sent: 2019年4月29日 13:16
>To: Peng Ma
>Cc: dan.j.willi...@intel.com; Leo Li ;
>dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org
>Subject: Re: [EXT] Re: [PATCH] dmaengine: fsl-qdma: fixed the
>source/destination descriptior format
>
>Caution: EXT Email
>
>On 28-04-19, 02:00, Peng Ma wrote:
>> Hi Vinod,
>>
>> Thanks your comments.
>> Please see my comments inline.
>>
>> Best Regards,
>> Peng
>>
>> >-Original Message-
>> >From: Vinod Koul
>> >Sent: 2019年4月26日 19:51
>> >To: Peng Ma
>> >Cc: dan.j.willi...@intel.com; Leo Li ;
>> >dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org
>> >Subject: [EXT] Re: [PATCH] dmaengine: fsl-qdma: fixed the
>> >source/destination descriptior format
>> >
>> >Caution: EXT Email
>> >
>> >On 19-04-19, 08:46, Peng Ma wrote:
>> >> CMD of Source/Destination descriptior format should be lower of
>> >
>> >s/descriptior/descriptor
>> >
>> [Peng Ma] Got it.
>> >> struct fsl_qdma_engine number data address.
>> >>
>> >> Signed-off-by: Peng Ma
>> >> ---
>> >> drivers/dma/fsl-qdma.c | 29 ++---
>> >> 1 files changed, 18 insertions(+), 11 deletions(-)
>> >>
>> >> diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c index
>> >> aa1d0ae..542765a 100644
>> >> --- a/drivers/dma/fsl-qdma.c
>> >> +++ b/drivers/dma/fsl-qdma.c
>> >> @@ -113,6 +113,7 @@
>> >> /* Field definition for Descriptor offset */
>> >> #define QDMA_CCDF_STATUS 20
>> >> #define QDMA_CCDF_OFFSET 20
>> >> +#define QDMA_SDDF_CMD(x) (((u64)(x)) << 32)
>> >>
>> >> /* Field definition for safe loop count*/
>> >> #define FSL_QDMA_HALT_COUNT 1500
>> >> @@ -214,6 +215,12 @@ struct fsl_qdma_engine {
>> >>
>> >> };
>> >>
>> >> +static inline void
>> >> +qdma_sddf_set_cmd(struct fsl_qdma_format *sddf, u32 val) {
>> >> + sddf->data = QDMA_SDDF_CMD(val); }
>> >> +
>> >> static inline u64
>> >> qdma_ccdf_addr_get64(const struct fsl_qdma_format *ccdf) { @@
>> >-341,6
>> >> +348,7 @@ static void fsl_qdma_free_chan_resources(struct dma_chan
>> >> *chan) static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp
>> >*fsl_comp,
>> >> dma_addr_t dst,
>dma_addr_t
>> >src,
>> >> u32 len) {
>> >> + u32 cmd;
>> >> struct fsl_qdma_format *sdf, *ddf;
>> >> struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src,
>> >> *csgf_dest;
>> >>
>> >> @@ -353,6 +361,7 @@ static void fsl_qdma_comp_fill_memcpy(struct
>> >> fsl_qdma_comp *fsl_comp,
>> >>
>> >> memset(fsl_comp->virt_addr, 0,
>> >FSL_QDMA_COMMAND_BUFFER_SIZE);
>> >> memset(fsl_comp->desc_virt_addr, 0,
>> >> FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
>> >> +
>> >> /* Head Command Descriptor(Frame Descriptor) */
>> >> qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
>> >> qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(ccdf)); @@
>> >> -369,14 +378,14 @@ static void fsl_qdma_comp_fill_memcpy(struct
>> >fsl_qdma_comp *fsl_comp,
>> >> /* This entry is the last entry. */
>> >> qdma_csgf_set_f(csgf_dest, len);
>> >> /* Descriptor Buffer */
>> >> - sdf->data =
>> >> - cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
>> >> - FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> >> - ddf->data =
>> >> - cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
>> >> - FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> >> - ddf->data |=
>> >> - cpu_to_le64(FSL_QDMA_CMD_LWC <<
>> >FSL_QDMA_CMD_LWC_OFFSET);
>> >> + cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
>> >> + FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> >> + qdma_sddf_set_cmd(sdf, cmd);
>> >> +
>> >> + cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
>> >> + FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> >> + cmd |= cpu_to_le32(FSL_QDMA_CMD_LWC <<
>> >FSL_QDMA_CMD_LWC_OFFSET);
>> >> + qdma_sddf_set_cmd(ddf, cmd);
>> >> }
>> >>
>> >> /*
>> >> @@ -701,10 +710,8 @@ static irqreturn_t fsl_qdma_error_handler(int
>> >> irq, void *dev_id)
>> >>
>> >> intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
>> >>
>> >> - if (intr) {
>> >> + if (intr)
>> >> dev_err(fsl_qdma->dma_dev.dev, "DMA transaction
>> >error!\n");
>> >> - return IRQ_NONE;
>> >> - }
>> >
>> >this seems unrelated can you explain?
>> >
>> [Peng Ma] This is an added improvement. When an error occurs we should
>clean the error reg then to return.
>> I forgot to explain it on comments. Should I add this changed to the
>comments?
>
>Yes and you should make it a separate patch. A patch should do only 1 thing!
>
[Peng Ma] OK, Got it, thanks.
Best Regards,
Peng
>--
>~Vinod
RE: [EXT] Re: [PATCH] dmaengine: fsl-qdma: fixed the source/destination descriptior format
Hi Vinod,
Thanks your comments.
Please see my comments inline.
Best Regards,
Peng
>-Original Message-
>From: Vinod Koul
>Sent: 2019年4月26日 19:51
>To: Peng Ma
>Cc: dan.j.willi...@intel.com; Leo Li ;
>dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org
>Subject: [EXT] Re: [PATCH] dmaengine: fsl-qdma: fixed the source/destination
>descriptior format
>
>Caution: EXT Email
>
>On 19-04-19, 08:46, Peng Ma wrote:
>> CMD of Source/Destination descriptior format should be lower of
>
>s/descriptior/descriptor
>
[Peng Ma] Got it.
>> struct fsl_qdma_engine number data address.
>>
>> Signed-off-by: Peng Ma
>> ---
>> drivers/dma/fsl-qdma.c | 29 ++---
>> 1 files changed, 18 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c index
>> aa1d0ae..542765a 100644
>> --- a/drivers/dma/fsl-qdma.c
>> +++ b/drivers/dma/fsl-qdma.c
>> @@ -113,6 +113,7 @@
>> /* Field definition for Descriptor offset */
>> #define QDMA_CCDF_STATUS 20
>> #define QDMA_CCDF_OFFSET 20
>> +#define QDMA_SDDF_CMD(x) (((u64)(x)) << 32)
>>
>> /* Field definition for safe loop count*/
>> #define FSL_QDMA_HALT_COUNT 1500
>> @@ -214,6 +215,12 @@ struct fsl_qdma_engine {
>>
>> };
>>
>> +static inline void
>> +qdma_sddf_set_cmd(struct fsl_qdma_format *sddf, u32 val) {
>> + sddf->data = QDMA_SDDF_CMD(val); }
>> +
>> static inline u64
>> qdma_ccdf_addr_get64(const struct fsl_qdma_format *ccdf) { @@
>-341,6
>> +348,7 @@ static void fsl_qdma_free_chan_resources(struct dma_chan
>> *chan) static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp
>*fsl_comp,
>> dma_addr_t dst, dma_addr_t
>src,
>> u32 len) {
>> + u32 cmd;
>> struct fsl_qdma_format *sdf, *ddf;
>> struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
>>
>> @@ -353,6 +361,7 @@ static void fsl_qdma_comp_fill_memcpy(struct
>> fsl_qdma_comp *fsl_comp,
>>
>> memset(fsl_comp->virt_addr, 0,
>FSL_QDMA_COMMAND_BUFFER_SIZE);
>> memset(fsl_comp->desc_virt_addr, 0,
>> FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
>> +
>> /* Head Command Descriptor(Frame Descriptor) */
>> qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
>> qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(ccdf)); @@
>> -369,14 +378,14 @@ static void fsl_qdma_comp_fill_memcpy(struct
>fsl_qdma_comp *fsl_comp,
>> /* This entry is the last entry. */
>> qdma_csgf_set_f(csgf_dest, len);
>> /* Descriptor Buffer */
>> - sdf->data =
>> - cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
>> - FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> - ddf->data =
>> - cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
>> - FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> - ddf->data |=
>> - cpu_to_le64(FSL_QDMA_CMD_LWC <<
>FSL_QDMA_CMD_LWC_OFFSET);
>> + cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
>> + FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> + qdma_sddf_set_cmd(sdf, cmd);
>> +
>> + cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
>> + FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> + cmd |= cpu_to_le32(FSL_QDMA_CMD_LWC <<
>FSL_QDMA_CMD_LWC_OFFSET);
>> + qdma_sddf_set_cmd(ddf, cmd);
>> }
>>
>> /*
>> @@ -701,10 +710,8 @@ static irqreturn_t fsl_qdma_error_handler(int
>> irq, void *dev_id)
>>
>> intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
>>
>> - if (intr) {
>> + if (intr)
>> dev_err(fsl_qdma->dma_dev.dev, "DMA transaction
>error!\n");
>> - return IRQ_NONE;
>> - }
>
>this seems unrelated can you explain?
>
[Peng Ma] This is an added improvement. When an error occurs we should clean
the error reg then to return.
I forgot to explain it on comments. Should I add this changed to the comments?
>>
>> qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status +
>FSL_QDMA_DEDR);
>> return IRQ_HANDLED;
>> --
>> 1.7.1
>
>--
>~Vinod
[PATCH] dmaengine: fsl-qdma: fixed the source/destination descriptior format
CMD of Source/Destination descriptior format should be lower of
struct fsl_qdma_engine number data address.
Signed-off-by: Peng Ma
---
drivers/dma/fsl-qdma.c | 29 ++---
1 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
index aa1d0ae..542765a 100644
--- a/drivers/dma/fsl-qdma.c
+++ b/drivers/dma/fsl-qdma.c
@@ -113,6 +113,7 @@
/* Field definition for Descriptor offset */
#define QDMA_CCDF_STATUS 20
#define QDMA_CCDF_OFFSET 20
+#define QDMA_SDDF_CMD(x) (((u64)(x)) << 32)
/* Field definition for safe loop count*/
#define FSL_QDMA_HALT_COUNT1500
@@ -214,6 +215,12 @@ struct fsl_qdma_engine {
};
+static inline void
+qdma_sddf_set_cmd(struct fsl_qdma_format *sddf, u32 val)
+{
+ sddf->data = QDMA_SDDF_CMD(val);
+}
+
static inline u64
qdma_ccdf_addr_get64(const struct fsl_qdma_format *ccdf)
{
@@ -341,6 +348,7 @@ static void fsl_qdma_free_chan_resources(struct dma_chan
*chan)
static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
dma_addr_t dst, dma_addr_t src, u32 len)
{
+ u32 cmd;
struct fsl_qdma_format *sdf, *ddf;
struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
@@ -353,6 +361,7 @@ static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp
*fsl_comp,
memset(fsl_comp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE);
memset(fsl_comp->desc_virt_addr, 0, FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
+
/* Head Command Descriptor(Frame Descriptor) */
qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(ccdf));
@@ -369,14 +378,14 @@ static void fsl_qdma_comp_fill_memcpy(struct
fsl_qdma_comp *fsl_comp,
/* This entry is the last entry. */
qdma_csgf_set_f(csgf_dest, len);
/* Descriptor Buffer */
- sdf->data =
- cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
- FSL_QDMA_CMD_RWTTYPE_OFFSET);
- ddf->data =
- cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
- FSL_QDMA_CMD_RWTTYPE_OFFSET);
- ddf->data |=
- cpu_to_le64(FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET);
+ cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
+ FSL_QDMA_CMD_RWTTYPE_OFFSET);
+ qdma_sddf_set_cmd(sdf, cmd);
+
+ cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
+ FSL_QDMA_CMD_RWTTYPE_OFFSET);
+ cmd |= cpu_to_le32(FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET);
+ qdma_sddf_set_cmd(ddf, cmd);
}
/*
@@ -701,10 +710,8 @@ static irqreturn_t fsl_qdma_error_handler(int irq, void
*dev_id)
intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
- if (intr) {
+ if (intr)
dev_err(fsl_qdma->dma_dev.dev, "DMA transaction error!\n");
- return IRQ_NONE;
- }
qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
return IRQ_HANDLED;
--
1.7.1
RE: [EXT] Re: [PATCH 1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip name to the list
Hi Shawn, OK, thanks. Best Regards, Peng >-Original Message- >From: Shawn Guo >Sent: 2019年4月11日 9:37 >To: Peng Ma >Cc: ax...@kernel.dk; robh...@kernel.org; mark.rutl...@arm.com; Leo Li >; linux-...@vger.kernel.org; devicet...@vger.kernel.org; >Andy Tang ; linux-kernel@vger.kernel.org; >linux-arm-ker...@lists.infradead.org >Subject: [EXT] Re: [PATCH 1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip >name to the list > >WARNING: This email was created outside of NXP. DO NOT CLICK links or >attachments unless you recognize the sender and know the content is safe. > > > >On Mon, Mar 11, 2019 at 03:20:12PM +0800, Peng Ma wrote: >> Add ls1028a compatible to bindings documentation. >> >> Signed-off-by: Peng Ma > >I assume that the bindings will be picked up by Axboe. Otherwise, please let >me know. > >Shawn
RE: [EXT] Re: [v7 3/3] ahci: qoriq: add lx2160 platforms support
Hi Axboe, Thanks very much. Best Regards, Peng >-Original Message- >From: Jens Axboe >Sent: 2019年4月9日 22:17 >To: Peng Ma ; robh...@kernel.org; >mark.rutl...@arm.com; shawn...@kernel.org; Leo Li >Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; >linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Andy Tang >; Jianchao Wang >Subject: Re: [EXT] Re: [v7 3/3] ahci: qoriq: add lx2160 platforms support > >WARNING: This email was created outside of NXP. DO NOT CLICK links or >attachments unless you recognize the sender and know the content is safe. > > > >On 4/9/19 12:44 AM, Peng Ma wrote: >> Hi Axboe, >> >> Patch link: >> >> >https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchwo >rk.ozlabs.org%2Fpatch%2F1055028%2F&data=02%7C01%7Cpeng.ma%40 >nxp.com%7Ce76be539c24a4733cf3f08d6bcf618de%7C686ea1d3bc2b4c6fa92 >cd99c5c301635%7C0%7C1%7C636904162505501500&sdata=Am7QEJ2Y >sqkNLXUtIMXU%2Fs5Mt4QhzYYa1FjbhWaAXiw%3D&reserved=0 >> >> >https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchwo >rk.ozlabs.org%2Fpatch%2F1054189%2F&data=02%7C01%7Cpeng.ma%40 >nxp.com%7Ce76be539c24a4733cf3f08d6bcf618de%7C686ea1d3bc2b4c6fa92 >cd99c5c301635%7C0%7C1%7C636904162505501500&sdata=ikpNC4M% >2BDq3%2FPYsXLHbPDcDu2KfgIRXs%2BjDDXWtp2jk%3D&reserved=0 > >Applied, thanks. > >-- >Jens Axboe
[V3 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
DPPA2(Data Path Acceleration Architecture 2) qDMA
The qDMA supports channel virtualization by allowing DMA jobs to be enqueued
into different frame queues. Core can initiate a DMA transaction by preparing
a frame descriptor(FD) for each DMA job and enqueuing this job to a frame queue.
through a hardware portal. The qDMA prefetches DMA jobs from the frame queues.
It then schedules and dispatches to internal DMA hardware engines, which
generate read and write requests. Both qDMA source data and destination data can
be either contiguous or non-contiguous using one or more scatter/gather tables.
The qDMA supports global bandwidth flow control where all DMA transactions are
stalled if the bandwidth threshold has been reached. Also supported are
transaction based read throttling.
Add NXP dppa2 qDMA to support some of Layerscape SoCs.
such as: LS1088A, LS208xA, LX2, etc.
Signed-off-by: Peng Ma
---
changed for v3:
- Add depends on arm64 for dpaa2 qdma driver
- The dpaa2_io_service_[de]register functions have a new parameter
So update all calls to some functions
drivers/dma/Kconfig |2 +
drivers/dma/Makefile|1 +
drivers/dma/fsl-dpaa2-qdma/Kconfig |9 +
drivers/dma/fsl-dpaa2-qdma/Makefile |3 +
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 782 +++
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 152 ++
6 files changed, 949 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Kconfig
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Makefile
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index eaf78f4..08aae01 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -671,6 +671,8 @@ source "drivers/dma/sh/Kconfig"
source "drivers/dma/ti/Kconfig"
+source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
+
# clients
comment "DMA Clients"
depends on DMA_ENGINE
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 6126e1c..2499ed8 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
+obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
obj-y += mediatek/
obj-y += qcom/
diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig
b/drivers/dma/fsl-dpaa2-qdma/Kconfig
new file mode 100644
index 000..258ed6b
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig
@@ -0,0 +1,9 @@
+menuconfig FSL_DPAA2_QDMA
+ tristate "NXP DPAA2 QDMA"
+ depends on ARM64
+ depends on FSL_MC_BUS && FSL_MC_DPIO
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ NXP Data Path Acceleration Architecture 2 QDMA driver,
+ using the NXP MC bus driver.
diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile
b/drivers/dma/fsl-dpaa2-qdma/Makefile
new file mode 100644
index 000..c1d0226
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# Makefile for the NXP DPAA2 qDMA controllers
+obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
new file mode 100644
index 000..0cdde0f
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
@@ -0,0 +1,782 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2014-2018 NXP
+
+/*
+ * Author: Changming Huang
+ *
+ * Driver for the NXP QDMA engine with QMan mode.
+ * Channel virtualization is supported through enqueuing of DMA jobs to,
+ * or dequeuing DMA jobs from different work queues with QMan portal.
+ * This module can be found on NXP LS2 SoCs.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+#include "dpdmai_cmd.h"
+#include "dpdmai.h"
+#include "dpaa2-qdma.h"
+
+static bool smmu_disable = true;
+
+static struct dpaa2_qdma_chan *to_dpaa2_qdma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct dpaa2_qdma_chan, vchan.chan);
+}
+
+static struct dpaa2_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct dpaa2_qdma_comp, vdesc);
+}
+
+static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma;
+ struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev;
+
+ dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev,
+ FD_POOL_SIZE, 32, 0);
+ if (!dpaa2_chan->fd_pool)
+
[V3 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
The MC exports the DPDMAI object as an interface to operate the DPAA2 QDMA
Engine. The DPDMAI enables sending frame-based requests to QDMA and receiving
back confirmation response on transaction completion, utilizing the DPAA2 QBMan
infrastructure. DPDMAI object provides up to two priorities for processing QDMA
requests.
The following list summarizes the DPDMAI main features and capabilities:
1. Supports up to two scheduling priorities for processing service
requests.
- Each DPDMAI transmit queue is mapped to one of two service priorities,
allowing further prioritization in hardware between requests from
different DPDMAI objects.
2. Supports up to two receive queues for incoming transaction completion
confirmations.
- Each DPDMAI receive queue is mapped to one of two receive priorities,
allowing further prioritization between other interfaces when
associating
the DPDMAI receive queues to DPIO or DPCON objects.
3. Supports different scheduling options for processing received
packets:
- Queues can be configured either in 'parked' mode (default), oattached
to a DPIO object, or attached to DPCON object.
4. Allows interaction with one or more DPIO objects for
dequeueing/enqueueing
frame descriptors(FD) and for acquiring/releasing buffers.
5. Supports enable, disable, and reset operations.
Add dpdmai to support some platforms with dpaa2 qdma engine.
Signed-off-by: Peng Ma
---
changed for v3:
- no changed
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 483
drivers/dma/fsl-dpaa2-qdma/dpdmai.h | 524 +++
drivers/dma/fsl-dpaa2-qdma/dpdmai_cmd.h | 197
3 files changed, 1204 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.h
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai_cmd.h
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
new file mode 100644
index 000..685eabe
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
@@ -0,0 +1,483 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2014-2018 NXP
+
+#include
+#include
+#include "dpdmai.h"
+#include "dpdmai_cmd.h"
+#include
+
+struct dpdmai_cmd_open {
+ __le32 dpdmai_id;
+};
+
+struct dpdmai_rsp_get_attributes {
+ __le32 id;
+ u8 num_of_priorities;
+ u8 pad0[3];
+ __le16 major;
+ __le16 minor;
+};
+
+struct dpdmai_cmd_queue {
+ __le32 dest_id;
+ u8 priority;
+ u8 queue;
+ u8 dest_type;
+ u8 pad;
+ __le64 user_ctx;
+ union {
+ __le32 options;
+ __le32 fqid;
+ };
+};
+
+struct dpdmai_rsp_get_tx_queue {
+ __le64 pad;
+ __le32 fqid;
+};
+
+int dpdmai_open(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ int dpdmai_id,
+ u16 *token)
+{
+ struct fsl_mc_command cmd = { 0 };
+ struct dpdmai_cmd_open *cmd_params;
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
+ cmd_flags,
+ 0);
+
+ cmd_params = (struct dpdmai_cmd_open *)cmd.params;
+ cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = mc_cmd_hdr_read_token(&cmd);
+ return 0;
+}
+
+int dpdmai_close(struct fsl_mc_io *mc_io,
+u32 cmd_flags,
+u16 token)
+{
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLOSE,
+ cmd_flags, token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpdmai_create(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ const struct dpdmai_cfg *cfg,
+ u16 *token)
+{
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CREATE,
+ cmd_flags,
+ 0);
+ DPDMAI_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpdmai_destroy(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 token)
+{
+ struct fsl_mc_command cmd = { 0 };
+
RE: [EXT] Re: [v7 3/3] ahci: qoriq: add lx2160 platforms support
Hi Axboe, Patch link: http://patchwork.ozlabs.org/patch/1055028/ http://patchwork.ozlabs.org/patch/1054189/ Best Regards, Peng >-Original Message- >From: Jens Axboe >Sent: 2019年4月8日 23:21 >To: Peng Ma ; robh...@kernel.org; >mark.rutl...@arm.com; shawn...@kernel.org; Leo Li >Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; >linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Andy Tang > >Subject: [EXT] Re: [v7 3/3] ahci: qoriq: add lx2160 platforms support > >WARNING: This email was created outside of NXP. DO NOT CLICK links or >attachments unless you recognize the sender and know the content is safe. > > > >On 4/8/19 4:06 AM, Peng Ma wrote: >> Hi axboe, >> >> If you have no comments on these paths, please merge. >> Thank you very much. >> Patch link: >> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch >> >work.ozlabs.org%2Fpatch%2F1055028%2F&data=02%7C01%7Cpeng.ma >%40nxp. >> >com%7C40e859676606431ce84908d6bc35bf3d%7C686ea1d3bc2b4c6fa92cd9 >9c5c301 >> >635%7C0%7C1%7C636903336364109322&sdata=Q8vElMkaDmHvphhVo >12BtFUvqXp >> T%2BDBrnvdjV%2FFizfs%3D&reserved=0 >> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch >> >work.ozlabs.org%2Fpatch%2F1054189%2F&data=02%7C01%7Cpeng.ma >%40nxp. >> >com%7C40e859676606431ce84908d6bc35bf3d%7C686ea1d3bc2b4c6fa92cd9 >9c5c301 >> >635%7C0%7C1%7C636903336364109322&sdata=HNuiGz%2BhfegcgNQ7 >T%2BPqGPI >> bS3ch%2FUqtxmHBfL6MoRo%3D&reserved=0 > >Can you resend, it's not clear which is which here, and what parts of the >series >goes where. > >-- >Jens Axboe
RE: [v7 3/3] ahci: qoriq: add lx2160 platforms support
Hi axboe,
If you have no comments on these paths, please merge.
Thank you very much.
Patch link:
http://patchwork.ozlabs.org/patch/1055028/
http://patchwork.ozlabs.org/patch/1054189/
Best Regards,
Peng
>-Original Message-
>From: Peng Ma
>Sent: 2019年3月12日 9:50
>To: ax...@kernel.dk; robh...@kernel.org; mark.rutl...@arm.com;
>shawn...@kernel.org; Leo Li
>Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org;
>linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Peng Ma
>
>Subject: [v7 3/3] ahci: qoriq: add lx2160 platforms support
>
>Lx2160a is a new introduced soc which supports ATA3.0
>
>Signed-off-by: Peng Ma
>---
>changed for V7:
> - no changed.
>
> drivers/ata/ahci_qoriq.c | 52
>+++---
> 1 files changed, 35 insertions(+), 17 deletions(-)
>
>diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index
>ce59253..08dbb86 100644
>--- a/drivers/ata/ahci_qoriq.c
>+++ b/drivers/ata/ahci_qoriq.c
>@@ -58,6 +58,7 @@ enum ahci_qoriq_type {
> AHCI_LS1046A,
> AHCI_LS1088A,
> AHCI_LS2088A,
>+ AHCI_LX2160A,
> };
>
> struct ahci_qoriq_priv {
>@@ -67,6 +68,8 @@ struct ahci_qoriq_priv {
> bool is_dmacoherent;
> };
>
>+static bool ecc_initialized;
>+
> static const struct of_device_id ahci_qoriq_of_match[] = {
> { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
> { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A}, @@
>-74,6 +77,7 @@ struct ahci_qoriq_priv {
> { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
> { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
> { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
>+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
> {},
> };
> MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); @@ -165,9 +169,10 @@
>static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
>
> switch (qpriv->type) {
> case AHCI_LS1021A:
>- if (!qpriv->ecc_addr)
>+ if (!(qpriv->ecc_addr || ecc_initialized))
> return -EINVAL;
>- writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
>+ else if (qpriv->ecc_addr && !ecc_initialized)
>+ writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
> writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); @@ -180,10
>+185,12 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> break;
>
> case AHCI_LS1043A:
>- if (!qpriv->ecc_addr)
>+ if (!(qpriv->ecc_addr || ecc_initialized))
> return -EINVAL;
>- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
>- qpriv->ecc_addr);
>+ else if (qpriv->ecc_addr && !ecc_initialized)
>+ writel(readl(qpriv->ecc_addr) |
>+ ECC_DIS_ARMV8_CH2,
>+ qpriv->ecc_addr);
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); @@
>-202,10 +209,12 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
>*hpriv)
> break;
>
> case AHCI_LS1046A:
>- if (!qpriv->ecc_addr)
>+ if (!(qpriv->ecc_addr || ecc_initialized))
> return -EINVAL;
>- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
>- qpriv->ecc_addr);
>+ else if (qpriv->ecc_addr && !ecc_initialized)
>+ writel(readl(qpriv->ecc_addr) |
>+ ECC_DIS_ARMV8_CH2,
>+ qpriv->ecc_addr);
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); @@
>-215,10 +224,13 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
>*hpriv)
> break;
>
> case AHCI_LS1088A:
>- if (!qpriv->ecc_addr)
>+ case AHCI_LX2160A:
>+ if (!(qpriv->ecc_addr || ecc_initialized))
> return -EINVAL;
>- writel(readl(qpriv->ecc_addr)
[v7 2/3] arm64: dts: lx2160a: add sata node support
Add SATA device nodes for fsl-lx2160a and enable support
for QDS and RDB boards.
Signed-off-by: Peng Ma
---
changed for V7:
- no changed
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44 +
3 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 99a22ab..1a5acf6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -95,6 +95,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f..5b6799e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -102,6 +102,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1..592034b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -671,6 +671,50 @@
status = "disabled";
};
+ sata0: sata@320 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x320 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata1: sata@321 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x321 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata2: sata@322 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x322 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata3: sata@323 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x323 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
smmu: iommu@500 {
compatible = "arm,mmu-500";
reg = <0 0x500 0 0x80>;
--
1.7.1
[v7 1/3] dt-bindings: ahci-fsl-qoriq: add lx2160a chip name to the list
Add lx2160a compatible to bindings documentation. Signed-off-by: Peng Ma Reviewed-by: Rob Herring --- changed for V7: - add Reviewed by tag. .../devicetree/bindings/ata/ahci-fsl-qoriq.txt |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt index 7c3ca0e..9ecc019 100644 --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt @@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller Required properties: - reg: Physical base address and size of the controller's register area. - compatible: Compatibility string. Must be 'fsl,-ahci', where -chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc. +chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a, lx2160a, etc. - clocks: Input clock specifier. Refer to common clock bindings. - interrupts: Interrupt specifier. Refer to interrupt binding. -- 1.7.1
[v7 3/3] ahci: qoriq: add lx2160 platforms support
Lx2160a is a new introduced soc which supports ATA3.0
Signed-off-by: Peng Ma
---
changed for V7:
- no changed.
drivers/ata/ahci_qoriq.c | 52 +++---
1 files changed, 35 insertions(+), 17 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index ce59253..08dbb86 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -58,6 +58,7 @@ enum ahci_qoriq_type {
AHCI_LS1046A,
AHCI_LS1088A,
AHCI_LS2088A,
+ AHCI_LX2160A,
};
struct ahci_qoriq_priv {
@@ -67,6 +68,8 @@ struct ahci_qoriq_priv {
bool is_dmacoherent;
};
+static bool ecc_initialized;
+
static const struct of_device_id ahci_qoriq_of_match[] = {
{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
@@ -74,6 +77,7 @@ struct ahci_qoriq_priv {
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
@@ -165,9 +169,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
switch (qpriv->type) {
case AHCI_LS1021A:
- if (!qpriv->ecc_addr)
+ if (!(qpriv->ecc_addr || ecc_initialized))
return -EINVAL;
- writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
+ else if (qpriv->ecc_addr && !ecc_initialized)
+ writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
@@ -180,10 +185,12 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
break;
case AHCI_LS1043A:
- if (!qpriv->ecc_addr)
+ if (!(qpriv->ecc_addr || ecc_initialized))
return -EINVAL;
- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
- qpriv->ecc_addr);
+ else if (qpriv->ecc_addr && !ecc_initialized)
+ writel(readl(qpriv->ecc_addr) |
+ ECC_DIS_ARMV8_CH2,
+ qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
@@ -202,10 +209,12 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
break;
case AHCI_LS1046A:
- if (!qpriv->ecc_addr)
+ if (!(qpriv->ecc_addr || ecc_initialized))
return -EINVAL;
- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
- qpriv->ecc_addr);
+ else if (qpriv->ecc_addr && !ecc_initialized)
+ writel(readl(qpriv->ecc_addr) |
+ ECC_DIS_ARMV8_CH2,
+ qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
@@ -215,10 +224,13 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
break;
case AHCI_LS1088A:
- if (!qpriv->ecc_addr)
+ case AHCI_LX2160A:
+ if (!(qpriv->ecc_addr || ecc_initialized))
return -EINVAL;
- writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
- qpriv->ecc_addr);
+ else if (qpriv->ecc_addr && !ecc_initialized)
+ writel(readl(qpriv->ecc_addr) |
+ ECC_DIS_LS1088A,
+ qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
@@ -237,6 +249,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
break;
}
+ ecc_initialized = true;
return 0;
}
@@ -264,13 +277,18 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "sata-ec
[PATCH 2/3] arm64: dts: ls1028a: Corrected the SATA ecc address.
Ls1028a SATA ecc address with more than 32 bit, so we should corrrect the
address.
Signed-off-by: Peng Ma
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index a8cf92a..3fcbd0a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -277,7 +277,7 @@
sata: sata@320 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x320 0x0 0x1>,
- <0x0 0x20140520 0x0 0x4>;
+ <0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = ;
clocks = <&clockgen 4 1>;
--
1.7.1
[PATCH 3/3] ahci: qoriq: add ls1028a platforms support
Ls1028a is a new introduced soc which supports ATA3.0
Signed-off-by: Peng Ma
---
depends on:
- http://patchwork.ozlabs.org/patch/1045218/
drivers/ata/ahci_qoriq.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 08dbb86..ea1175f 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -53,6 +53,7 @@
enum ahci_qoriq_type {
AHCI_LS1021A,
+ AHCI_LS1028A,
AHCI_LS1043A,
AHCI_LS2080A,
AHCI_LS1046A,
@@ -72,6 +73,7 @@ struct ahci_qoriq_priv {
static const struct of_device_id ahci_qoriq_of_match[] = {
{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
+ { .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
@@ -223,6 +225,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
+ case AHCI_LS1028A:
case AHCI_LS1088A:
case AHCI_LX2160A:
if (!(qpriv->ecc_addr || ecc_initialized))
--
1.7.1
[PATCH 1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip name to the list
Add ls1028a compatible to bindings documentation. Signed-off-by: Peng Ma --- depends on: - http://patchwork.ozlabs.org/patch/1045217/ .../devicetree/bindings/ata/ahci-fsl-qoriq.txt |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt index 9ecc019..72fdeef 100644 --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt @@ -3,7 +3,8 @@ Binding for Freescale QorIQ AHCI SATA Controller Required properties: - reg: Physical base address and size of the controller's register area. - compatible: Compatibility string. Must be 'fsl,-ahci', where -chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a, lx2160a, etc. +chip could be ls1021a, ls1028a, ls1043a, ls1046a, ls1088a, ls2080a, +lx2160a, etc. - clocks: Input clock specifier. Refer to common clock bindings. - interrupts: Interrupt specifier. Refer to interrupt binding. -- 1.7.1
RE: [v6 1/3] dt-bindings: ahci-fsl-qoriq: add lx2160a chip name to the list
Hi Rob, Thanks for your comments, I don't understand what you said. This patch is one of the series patchs(http://patchwork.ozlabs.org/project/linux-ide/list/?series=93099&archive=both&state=*) for review. There is not changed for 6th version of this patch. Best Regards, Peng >-Original Message- >From: Rob Herring >Sent: 2019年2月22日 22:40 >To: Peng Ma >Cc: ax...@kernel.dk; robh...@kernel.org; mark.rutl...@arm.com; >shawn...@kernel.org; Leo Li ; Andy Tang >; linux-...@vger.kernel.org; devicet...@vger.kernel.org; >linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Mian >Yousaf Kaukab ; Peng Ma >Subject: Re: [v6 1/3] dt-bindings: ahci-fsl-qoriq: add lx2160a chip name to the >list > >On Wed, 20 Feb 2019 08:56:05 +, Peng Ma wrote: >> Add lx2160a compatible to bindings documentation. >> >> Signed-off-by: Peng Ma >> --- >> changed for V6: >> - no changed >> >> .../devicetree/bindings/ata/ahci-fsl-qoriq.txt |2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> > >Please add Acked-by/Reviewed-by tags when posting new versions. However, >there's no need to repost patches *only* to add the tags. The upstream >maintainer will do that for acks received on the version they apply. > >If a tag was not added on purpose, please state why and what changed.
[v2 2/2] dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
DPPA2(Data Path Acceleration Architecture 2) qDMA
The qDMA supports channel virtualization by allowing DMA jobs to be enqueued
into different frame queues. Core can initiate a DMA transaction by preparing
a frame descriptor(FD) for each DMA job and enqueuing this job to a frame queue.
through a hardware portal. The qDMA prefetches DMA jobs from the frame queues.
It then schedules and dispatches to internal DMA hardware engines, which
generate read and write requests. Both qDMA source data and destination data can
be either contiguous or non-contiguous using one or more scatter/gather tables.
The qDMA supports global bandwidth flow control where all DMA transactions are
stalled if the bandwidth threshold has been reached. Also supported are
transaction based read throttling.
Add NXP dppa2 qDMA to support some of Layerscape SoCs.
such as: LS1088A, LS208xA, LX2, etc.
Signed-off-by: Peng Ma
---
change for v2:
- split the v1 patch to two patchs
- add detail comments
drivers/dma/Kconfig |2 +
drivers/dma/Makefile|1 +
drivers/dma/fsl-dpaa2-qdma/Kconfig |8 +
drivers/dma/fsl-dpaa2-qdma/Makefile |3 +
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 781 +++
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 152 ++
6 files changed, 947 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Kconfig
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Makefile
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 0b1dfb5..d590412 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -671,6 +671,8 @@ source "drivers/dma/sh/Kconfig"
source "drivers/dma/ti/Kconfig"
+source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
+
# clients
comment "DMA Clients"
depends on DMA_ENGINE
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 6126e1c..2499ed8 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
+obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
obj-y += mediatek/
obj-y += qcom/
diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig
b/drivers/dma/fsl-dpaa2-qdma/Kconfig
new file mode 100644
index 000..ec591fc
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig
@@ -0,0 +1,8 @@
+menuconfig FSL_DPAA2_QDMA
+ tristate "NXP DPAA2 QDMA"
+ depends on FSL_MC_BUS && FSL_MC_DPIO
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ NXP Data Path Acceleration Architecture 2 QDMA driver,
+ using the NXP MC bus driver.
diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile
b/drivers/dma/fsl-dpaa2-qdma/Makefile
new file mode 100644
index 000..c1d0226
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# Makefile for the NXP DPAA2 qDMA controllers
+obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
new file mode 100644
index 000..80e851f
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
@@ -0,0 +1,781 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2014-2018 NXP
+
+/*
+ * Author: Changming Huang
+ *
+ * Driver for the NXP QDMA engine with QMan mode.
+ * Channel virtualization is supported through enqueuing of DMA jobs to,
+ * or dequeuing DMA jobs from different work queues with QMan portal.
+ * This module can be found on NXP LS2 SoCs.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+#include "dpdmai_cmd.h"
+#include "dpdmai.h"
+#include "dpaa2-qdma.h"
+
+static bool smmu_disable = true;
+
+static struct dpaa2_qdma_chan *to_dpaa2_qdma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct dpaa2_qdma_chan, vchan.chan);
+}
+
+static struct dpaa2_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct dpaa2_qdma_comp, vdesc);
+}
+
+static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma;
+ struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev;
+
+ dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev,
+ FD_POOL_SIZE, 32, 0);
+ if (!dpaa2_chan->fd_pool)
+ return -ENOMEM;
+
+ return dpaa2_qdma->desc_allocated++;
+}
+
+static void dpaa2_qdma_free_chan_resources(struct d
[v2 1/2] dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support
The MC exports the DPDMAI object as an interface to operate the DPAA2 QDMA
Engine. The DPDMAI enables sending frame-based requests to QDMA and receiving
back confirmation response on transaction completion, utilizing the DPAA2 QBMan
infrastructure. DPDMAI object provides up to two priorities for processing QDMA
requests.
The following list summarizes the DPDMAI main features and capabilities:
1. Supports up to two scheduling priorities for processing service
requests.
- Each DPDMAI transmit queue is mapped to one of two service priorities,
allowing further prioritization in hardware between requests from
different DPDMAI objects.
2. Supports up to two receive queues for incoming transaction completion
confirmations.
- Each DPDMAI receive queue is mapped to one of two receive priorities,
allowing further prioritization between other interfaces when
associating
the DPDMAI receive queues to DPIO or DPCON objects.
3. Supports different scheduling options for processing received
packets:
- Queues can be configured either in 'parked' mode (default), oattached
to a DPIO object, or attached to DPCON object.
4. Allows interaction with one or more DPIO objects for
dequeueing/enqueueing
frame descriptors(FD) and for acquiring/releasing buffers.
5. Supports enable, disable, and reset operations.
Add DPDMAI to support some platforms with dpaa2 qdma engine.
Signed-off-by: Peng Ma
---
change for v2:
- split the v1 patch to two patchs
- add detail comments
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 483
drivers/dma/fsl-dpaa2-qdma/dpdmai.h | 524 +++
drivers/dma/fsl-dpaa2-qdma/dpdmai_cmd.h | 197
3 files changed, 1204 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.h
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai_cmd.h
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
new file mode 100644
index 000..685eabe
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c
@@ -0,0 +1,483 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2014-2018 NXP
+
+#include
+#include
+#include "dpdmai.h"
+#include "dpdmai_cmd.h"
+#include
+
+struct dpdmai_cmd_open {
+ __le32 dpdmai_id;
+};
+
+struct dpdmai_rsp_get_attributes {
+ __le32 id;
+ u8 num_of_priorities;
+ u8 pad0[3];
+ __le16 major;
+ __le16 minor;
+};
+
+struct dpdmai_cmd_queue {
+ __le32 dest_id;
+ u8 priority;
+ u8 queue;
+ u8 dest_type;
+ u8 pad;
+ __le64 user_ctx;
+ union {
+ __le32 options;
+ __le32 fqid;
+ };
+};
+
+struct dpdmai_rsp_get_tx_queue {
+ __le64 pad;
+ __le32 fqid;
+};
+
+int dpdmai_open(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ int dpdmai_id,
+ u16 *token)
+{
+ struct fsl_mc_command cmd = { 0 };
+ struct dpdmai_cmd_open *cmd_params;
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
+ cmd_flags,
+ 0);
+
+ cmd_params = (struct dpdmai_cmd_open *)cmd.params;
+ cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = mc_cmd_hdr_read_token(&cmd);
+ return 0;
+}
+
+int dpdmai_close(struct fsl_mc_io *mc_io,
+u32 cmd_flags,
+u16 token)
+{
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLOSE,
+ cmd_flags, token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpdmai_create(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ const struct dpdmai_cfg *cfg,
+ u16 *token)
+{
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CREATE,
+ cmd_flags,
+ 0);
+ DPDMAI_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpdmai_destroy(struct fsl_mc_io *mc_io,
+ u32 cmd_flags,
+ u16 token)
+{
+ struct
RE: [v5 2/2] arm64: dts: lx2160a: add sata node support
Hi Yousaf,
To set sata bit of ecc-addr will affect all sata controllers, The v6 patch has
been sent will fixed the remap error when two or more sata controllers be
probed, please review.
Thanks.
Best Regards,
Peng
>-Original Message-
>From: Peng Ma
>Sent: 2019年2月14日 17:19
>To: 'Mian Yousaf Kaukab'
>Cc: ax...@kernel.dk; shawn...@kernel.org; robh...@kernel.org;
>mark.rutl...@arm.com; Leo Li ;
>linux-...@vger.kernel.org; devicet...@vger.kernel.org;
>linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Andy Tang
>
>Subject: RE: [v5 2/2] arm64: dts: lx2160a: add sata node support
>
>
>
>>-Original Message-
>>From: Mian Yousaf Kaukab
>>Sent: 2019年2月13日 3:01
>>To: Peng Ma
>>Cc: ax...@kernel.dk; shawn...@kernel.org; robh...@kernel.org;
>>mark.rutl...@arm.com; Leo Li ;
>>linux-...@vger.kernel.org; devicet...@vger.kernel.org;
>>linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
>>Andy Tang
>>Subject: Re: [v5 2/2] arm64: dts: lx2160a: add sata node support
>>
>>On Fri, Jan 25, 2019 at 08:10:13AM +, Peng Ma wrote:
>>> Add SATA device nodes for fsl-lx2160a and enable support for QDS and
>>> RDB boards.
>>>
>>> Signed-off-by: Peng Ma
>>> ---
>>> changed for V5:
>>> - no change
>>>
>>> arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
>>> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
>>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44
>>+
>>> 3 files changed, 76 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>>> index 99a22ab..1a5acf6 100644
>>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>>> @@ -95,6 +95,22 @@
>>> };
>>> };
>>>
>>> +&sata0 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&sata1 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&sata2 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&sata3 {
>>> + status = "okay";
>>> +};
>>> +
>>> &uart0 {
>>> status = "okay";
>>> };
>>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>>> index 6481e5f..5b6799e 100644
>>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>>> @@ -102,6 +102,22 @@
>>> };
>>> };
>>>
>>> +&sata0 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&sata1 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&sata2 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&sata3 {
>>> + status = "okay";
>>> +};
>>> +
>>> &uart0 {
>>> status = "okay";
>>> };
>>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>> index a79f5c1..592034b 100644
>>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>> @@ -671,6 +671,50 @@
>>> status = "disabled";
>>> };
>>>
>>> + sata0: sata@320 {
>>> + compatible = "fsl,lx2160a-ahci";
>>> + reg = <0x0 0x320 0x0 0x1>,
>>> + <0x7 0x100520 0x0 0x4>;
>>> + reg-names = "ahci", "sata-ecc";
>>> + interrupts = ;
>>> + clocks = <&clockgen 4 3>;
>>> + dma-coherent;
>>> + status = "disabled";
>>> + };
>>> +
>>> + sata1: sata@321 {
>>> + compatible = "fsl,lx2160a-ahci";
>>> + reg = <0x0 0x321 0x0 0x1>,
>>> + <0x7 0x100520 0x0 0x4>;
>>> + reg-names = "ahci", &quo
[v6 1/3] dt-bindings: ahci-fsl-qoriq: add lx2160a chip name to the list
Add lx2160a compatible to bindings documentation. Signed-off-by: Peng Ma --- changed for V6: - no changed .../devicetree/bindings/ata/ahci-fsl-qoriq.txt |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt index 7c3ca0e..9ecc019 100644 --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt @@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller Required properties: - reg: Physical base address and size of the controller's register area. - compatible: Compatibility string. Must be 'fsl,-ahci', where -chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc. +chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a, lx2160a, etc. - clocks: Input clock specifier. Refer to common clock bindings. - interrupts: Interrupt specifier. Refer to interrupt binding. -- 1.7.1
[v6 2/3] arm64: dts: lx2160a: add sata node support
Add SATA device nodes for fsl-lx2160a and enable support
for QDS and RDB boards.
Signed-off-by: Peng Ma
---
changed for V6:
- no change
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44 +
3 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 99a22ab..1a5acf6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -95,6 +95,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f..5b6799e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -102,6 +102,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1..592034b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -671,6 +671,50 @@
status = "disabled";
};
+ sata0: sata@320 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x320 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata1: sata@321 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x321 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata2: sata@322 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x322 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata3: sata@323 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x323 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
smmu: iommu@500 {
compatible = "arm,mmu-500";
reg = <0 0x500 0 0x80>;
--
1.7.1
[v6 3/3] ahci: qoriq: add lx2160 platforms support
Lx2160a is a new introduced soc which supports ATA3.0
Signed-off-by: Peng Ma
---
changed for V6:
- Add ecc_initialized to ensure set sata bit once of
ECC error register
- Recovery AHCI_LS2088A platform
drivers/ata/ahci_qoriq.c | 52 +++---
1 files changed, 35 insertions(+), 17 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index ce59253..08dbb86 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -58,6 +58,7 @@ enum ahci_qoriq_type {
AHCI_LS1046A,
AHCI_LS1088A,
AHCI_LS2088A,
+ AHCI_LX2160A,
};
struct ahci_qoriq_priv {
@@ -67,6 +68,8 @@ struct ahci_qoriq_priv {
bool is_dmacoherent;
};
+static bool ecc_initialized;
+
static const struct of_device_id ahci_qoriq_of_match[] = {
{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
@@ -74,6 +77,7 @@ struct ahci_qoriq_priv {
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
@@ -165,9 +169,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
switch (qpriv->type) {
case AHCI_LS1021A:
- if (!qpriv->ecc_addr)
+ if (!(qpriv->ecc_addr || ecc_initialized))
return -EINVAL;
- writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
+ else if (qpriv->ecc_addr && !ecc_initialized)
+ writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
@@ -180,10 +185,12 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
break;
case AHCI_LS1043A:
- if (!qpriv->ecc_addr)
+ if (!(qpriv->ecc_addr || ecc_initialized))
return -EINVAL;
- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
- qpriv->ecc_addr);
+ else if (qpriv->ecc_addr && !ecc_initialized)
+ writel(readl(qpriv->ecc_addr) |
+ ECC_DIS_ARMV8_CH2,
+ qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
@@ -202,10 +209,12 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
break;
case AHCI_LS1046A:
- if (!qpriv->ecc_addr)
+ if (!(qpriv->ecc_addr || ecc_initialized))
return -EINVAL;
- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
- qpriv->ecc_addr);
+ else if (qpriv->ecc_addr && !ecc_initialized)
+ writel(readl(qpriv->ecc_addr) |
+ ECC_DIS_ARMV8_CH2,
+ qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
@@ -215,10 +224,13 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
break;
case AHCI_LS1088A:
- if (!qpriv->ecc_addr)
+ case AHCI_LX2160A:
+ if (!(qpriv->ecc_addr || ecc_initialized))
return -EINVAL;
- writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
- qpriv->ecc_addr);
+ else if (qpriv->ecc_addr && !ecc_initialized)
+ writel(readl(qpriv->ecc_addr) |
+ ECC_DIS_LS1088A,
+ qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
@@ -237,6 +249,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
break;
}
+ ecc_initialized = true;
return 0;
}
@@ -264,13 +277,18 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
qoriq_priv->type = (enum ahci_qoriq_t
RE: [v5 2/2] arm64: dts: lx2160a: add sata node support
>-Original Message-
>From: Mian Yousaf Kaukab
>Sent: 2019年2月13日 3:01
>To: Peng Ma
>Cc: ax...@kernel.dk; shawn...@kernel.org; robh...@kernel.org;
>mark.rutl...@arm.com; Leo Li ;
>linux-...@vger.kernel.org; devicet...@vger.kernel.org;
>linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Andy Tang
>
>Subject: Re: [v5 2/2] arm64: dts: lx2160a: add sata node support
>
>On Fri, Jan 25, 2019 at 08:10:13AM +, Peng Ma wrote:
>> Add SATA device nodes for fsl-lx2160a and enable support for QDS and
>> RDB boards.
>>
>> Signed-off-by: Peng Ma
>> ---
>> changed for V5:
>> - no change
>>
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44
>+
>> 3 files changed, 76 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> index 99a22ab..1a5acf6 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> @@ -95,6 +95,22 @@
>> };
>> };
>>
>> +&sata0 {
>> +status = "okay";
>> +};
>> +
>> +&sata1 {
>> +status = "okay";
>> +};
>> +
>> +&sata2 {
>> +status = "okay";
>> +};
>> +
>> +&sata3 {
>> +status = "okay";
>> +};
>> +
>> &uart0 {
>> status = "okay";
>> };
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> index 6481e5f..5b6799e 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> @@ -102,6 +102,22 @@
>> };
>> };
>>
>> +&sata0 {
>> +status = "okay";
>> +};
>> +
>> +&sata1 {
>> +status = "okay";
>> +};
>> +
>> +&sata2 {
>> +status = "okay";
>> +};
>> +
>> +&sata3 {
>> +status = "okay";
>> +};
>> +
>> &uart0 {
>> status = "okay";
>> };
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> index a79f5c1..592034b 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> @@ -671,6 +671,50 @@
>> status = "disabled";
>> };
>>
>> +sata0: sata@320 {
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x320 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +status = "disabled";
>> +};
>> +
>> +sata1: sata@321 {
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x321 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +status = "disabled";
>> +};
>> +
>> +sata2: sata@322 {
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x322 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +status = "disabled";
>> +};
>> +
>> +sata3: sata@323 {
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x323 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>You are using same reg values for sata-ecc in all sata instances. Does this
>actually work? No errors when the ahci_qoriq driver do ioremap on it while
>probing second instance and onward?
>
Thanks for you point out the problem. I will fixed it with two or more sata
enable.
>fsl-ls208xa.dtsi is the only other file here with multiple sata instances and
>it
>doesn’t care about sata-ecc.
>
The ls208xa platforms is not necessary to set sata-ecc addr.
BR,
Peng
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +status = "disabled";
>> +};
>> +
>> smmu: iommu@500 {
>> compatible = "arm,mmu-500";
>> reg = <0 0x500 0 0x80>;
>
>BR,
>Yousaf
RE: [v5 2/2] arm64: dts: lx2160a: add sata node support
>-Original Message-
>From: Shawn Guo
>Sent: 2019年2月11日 13:39
>To: Peng Ma
>Cc: ax...@kernel.dk; mark.rutl...@arm.com; Andy Tang
>; devicet...@vger.kernel.org;
>linux-kernel@vger.kernel.org; Leo Li ;
>linux-...@vger.kernel.org; robh...@kernel.org;
>linux-arm-ker...@lists.infradead.org
>Subject: Re: [v5 2/2] arm64: dts: lx2160a: add sata node support
>
>On Mon, Feb 11, 2019 at 02:53:18AM +, Peng Ma wrote:
>>
>>
>> >-Original Message-
>> >From: Shawn Guo
>> >Sent: 2019年2月1日 14:30
>> >To: Peng Ma
>> >Cc: ax...@kernel.dk; robh...@kernel.org; mark.rutl...@arm.com; Leo Li
>> >; linux-...@vger.kernel.org;
>> >devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
>> >linux-arm-ker...@lists.infradead.org; Andy Tang
>> >Subject: Re: [v5 2/2] arm64: dts: lx2160a: add sata node support
>> >
>> >On Fri, Jan 25, 2019 at 08:10:13AM +0000, Peng Ma wrote:
>> >> Add SATA device nodes for fsl-lx2160a and enable support for QDS
>> >> and RDB boards.
>> >>
>> >> Signed-off-by: Peng Ma
>> >> ---
>> >> changed for V5:
>> >> - no change
>> >>
>> >> arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
>> >> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
>> >> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44
>> >+
>> >> 3 files changed, 76 insertions(+), 0 deletions(-)
>> >>
>> >> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> >> b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> >> index 99a22ab..1a5acf6 100644
>> >> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> >> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> >> @@ -95,6 +95,22 @@
>> >> };
>> >> };
>> >>
>> >> +&sata0 {
>> >> + status = "okay";
>> >> +};
>> >> +
>> >> +&sata1 {
>> >> + status = "okay";
>> >> +};
>> >> +
>> >> +&sata2 {
>> >> + status = "okay";
>> >> +};
>> >> +
>> >> +&sata3 {
>> >> + status = "okay";
>> >> +};
>> >> +
>> >> &uart0 {
>> >> status = "okay";
>> >> };
>> >> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> >> b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> >> index 6481e5f..5b6799e 100644
>> >> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> >> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> >> @@ -102,6 +102,22 @@
>> >> };
>> >> };
>> >>
>> >> +&sata0 {
>> >> + status = "okay";
>> >> +};
>> >> +
>> >> +&sata1 {
>> >> + status = "okay";
>> >> +};
>> >> +
>> >> +&sata2 {
>> >> + status = "okay";
>> >> +};
>> >> +
>> >> +&sata3 {
>> >> + status = "okay";
>> >> +};
>> >> +
>> >> &uart0 {
>> >> status = "okay";
>> >> };
>> >> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> >> b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> >> index a79f5c1..592034b 100644
>> >> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> >> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> >> @@ -671,6 +671,50 @@
>> >> status = "disabled";
>> >> };
>> >>
>> >> + sata0: sata@320 {
>> >> + compatible = "fsl,lx2160a-ahci";
>> >
>> >Has the kernel driver been patched to probe the compatible?
>> >
>> >Shawn
>> Yes, the driver patch is
>> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatc
>>
>hwork.ozlabs.org%2Fpatch%2F1034083%2F&data=02%7C01%7Cpeng.ma
>%40nxp
>> .com%7C8daea4e4b2ea419cb2a008d68fe34f51%7C686ea1d3bc2b4c6fa92c
>d99c5c30
>>
>1635%7C0%7C0%7C636854603794170576&sdata=z3ic8%2FAS10NcFjdP
>eJFpnFoo
>> R2Yo4oYO%2FAASr7r2Lhg%3D&reserved=0
>
>Ping me when the driver patch is accepted. Ideally, we only accept dts
>changes after the driver counterpart lands on mainline.
>
>Shawn
[Peng Ma] got it, thanks.
BR
Peng
RE: [v5 2/2] arm64: dts: lx2160a: add sata node support
>-Original Message-
>From: Shawn Guo
>Sent: 2019年2月1日 14:30
>To: Peng Ma
>Cc: ax...@kernel.dk; robh...@kernel.org; mark.rutl...@arm.com; Leo Li
>; linux-...@vger.kernel.org; devicet...@vger.kernel.org;
>linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Andy Tang
>
>Subject: Re: [v5 2/2] arm64: dts: lx2160a: add sata node support
>
>On Fri, Jan 25, 2019 at 08:10:13AM +, Peng Ma wrote:
>> Add SATA device nodes for fsl-lx2160a and enable support for QDS and
>> RDB boards.
>>
>> Signed-off-by: Peng Ma
>> ---
>> changed for V5:
>> - no change
>>
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44
>+
>> 3 files changed, 76 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> index 99a22ab..1a5acf6 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
>> @@ -95,6 +95,22 @@
>> };
>> };
>>
>> +&sata0 {
>> +status = "okay";
>> +};
>> +
>> +&sata1 {
>> +status = "okay";
>> +};
>> +
>> +&sata2 {
>> +status = "okay";
>> +};
>> +
>> +&sata3 {
>> +status = "okay";
>> +};
>> +
>> &uart0 {
>> status = "okay";
>> };
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> index 6481e5f..5b6799e 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> @@ -102,6 +102,22 @@
>> };
>> };
>>
>> +&sata0 {
>> +status = "okay";
>> +};
>> +
>> +&sata1 {
>> +status = "okay";
>> +};
>> +
>> +&sata2 {
>> +status = "okay";
>> +};
>> +
>> +&sata3 {
>> +status = "okay";
>> +};
>> +
>> &uart0 {
>> status = "okay";
>> };
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> index a79f5c1..592034b 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> @@ -671,6 +671,50 @@
>> status = "disabled";
>> };
>>
>> +sata0: sata@320 {
>> +compatible = "fsl,lx2160a-ahci";
>
>Has the kernel driver been patched to probe the compatible?
>
>Shawn
Yes, the driver patch is http://patchwork.ozlabs.org/patch/1034083/
BR
Peng
>
>> +reg = <0x0 0x320 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +status = "disabled";
>> +};
>> +
>> +sata1: sata@321 {
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x321 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +status = "disabled";
>> +};
>> +
>> +sata2: sata@322 {
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x322 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +status = "disabled";
>> +};
>> +
>> +sata3: sata@323 {
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x323 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +status = "disabled";
>> +};
>> +
>> smmu: iommu@500 {
>> compatible = "arm,mmu-500";
>> reg = <0 0x500 0 0x80>;
>> --
>> 1.7.1
>>
[PATCH RESEND] ahci: qoriq: add lx2160 platforms support
Lx2160a is a new introduced soc which supports ATA3.0
Clean up some code
Signed-off-by: Peng Ma
---
drivers/ata/ahci_qoriq.c | 44
1 files changed, 12 insertions(+), 32 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index ce59253..1994bf2 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -57,7 +57,7 @@ enum ahci_qoriq_type {
AHCI_LS2080A,
AHCI_LS1046A,
AHCI_LS1088A,
- AHCI_LS2088A,
+ AHCI_LX2160A,
};
struct ahci_qoriq_priv {
@@ -73,7 +73,7 @@ struct ahci_qoriq_priv {
{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
- { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
@@ -174,12 +174,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG,
- reg_base + LS1021A_AXICC_ADDR);
break;
case AHCI_LS1043A:
+ case AHCI_LS1046A:
if (!qpriv->ecc_addr)
return -EINVAL;
writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
@@ -188,8 +186,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS2080A:
@@ -197,24 +193,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
- break;
-
- case AHCI_LS1046A:
- if (!qpriv->ecc_addr)
- return -EINVAL;
- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
- qpriv->ecc_addr);
- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS1088A:
+ case AHCI_LX2160A:
if (!qpriv->ecc_addr)
return -EINVAL;
writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
@@ -223,18 +205,16 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
+ }
- case AHCI_LS2088A:
- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
- break;
+ if (qpriv->is_dmacoherent) {
+ if (qpriv->type == AHCI_LS1021A)
+ writel(AHCI_PORT_AXICC_CFG,
+ reg_base + LS1021A_AXICC_ADDR);
+ else
+ writel(AHCI_PORT_AXICC_CFG,
+ reg_base + PORT_AXICC);
}
return 0;
--
1.7.1
[v5 2/2] arm64: dts: lx2160a: add sata node support
Add SATA device nodes for fsl-lx2160a and enable support
for QDS and RDB boards.
Signed-off-by: Peng Ma
---
changed for V5:
- no change
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44 +
3 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 99a22ab..1a5acf6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -95,6 +95,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f..5b6799e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -102,6 +102,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1..592034b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -671,6 +671,50 @@
status = "disabled";
};
+ sata0: sata@320 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x320 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata1: sata@321 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x321 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata2: sata@322 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x322 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata3: sata@323 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x323 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
smmu: iommu@500 {
compatible = "arm,mmu-500";
reg = <0 0x500 0 0x80>;
--
1.7.1
[v5 1/2] dt-bindings: ahci-fsl-qoriq: add lx2160a chip name to the list
Add lx2160a compatible to bindings documentation. Signed-off-by: Peng Ma --- changed for V5: - change the lxx2160a to lx2160a .../devicetree/bindings/ata/ahci-fsl-qoriq.txt |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt index 7c3ca0e..9ecc019 100644 --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt @@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller Required properties: - reg: Physical base address and size of the controller's register area. - compatible: Compatibility string. Must be 'fsl,-ahci', where -chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc. +chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a, lx2160a, etc. - clocks: Input clock specifier. Refer to common clock bindings. - interrupts: Interrupt specifier. Refer to interrupt binding. -- 1.7.1
RE: [v4] dt-bindings: ahci-fsl-qoriq: add lx2160a chip name to the list
>-Original Message- >From: Sergei Shtylyov >Sent: 2019年1月25日 15:46 >To: Peng Ma ; shawn...@kernel.org; ax...@kernel.dk >Cc: robh...@kernel.org; mark.rutl...@arm.com; Leo Li >; linux-...@vger.kernel.org; devicet...@vger.kernel.org; >linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Andy Tang > >Subject: Re: [v4] dt-bindings: ahci-fsl-qoriq: add lx2160a chip name to the >list > >Hello! > >On 25.01.2019 6:32, Peng Ma wrote: > >> Add lxx2160a compatible to bindings documentation. > >lx2160a? > [Peng Ma] Yes, it is should be lx2160a, thanks very much. I will change it as soon as possible. Best Regards, Peng >> Signed-off-by: Peng Ma >> --- >> changed for V4: >> - add lx2160a compatible to bindings doc >> >> .../devicetree/bindings/ata/ahci-fsl-qoriq.txt |2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt >b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt >> index 7c3ca0e..9ecc019 100644 >> --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt >> +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt >> @@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller >> Required properties: >> - reg: Physical base address and size of the controller's register area. >> - compatible: Compatibility string. Must be 'fsl,-ahci', where >> -chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc. >> +chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a, lx2160a, etc. >> - clocks: Input clock specifier. Refer to common clock bindings. >> - interrupts: Interrupt specifier. Refer to interrupt binding. >> > >MBR, Sergei
[v4] dt-bindings: ahci-fsl-qoriq: add lx2160a chip name to the list
Add lxx2160a compatible to bindings documentation. Signed-off-by: Peng Ma --- changed for V4: - add lx2160a compatible to bindings doc .../devicetree/bindings/ata/ahci-fsl-qoriq.txt |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt index 7c3ca0e..9ecc019 100644 --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt @@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller Required properties: - reg: Physical base address and size of the controller's register area. - compatible: Compatibility string. Must be 'fsl,-ahci', where -chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc. +chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a, lx2160a, etc. - clocks: Input clock specifier. Refer to common clock bindings. - interrupts: Interrupt specifier. Refer to interrupt binding. -- 1.7.1
[v4] arm64: dts: lx2160a: add sata node support
Add SATA device nodes for fsl-lx2160a and enable support
for QDS and RDB boards.
Signed-off-by: Peng Ma
---
changed for V4:
- no change
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44 +
3 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 99a22ab..1a5acf6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -95,6 +95,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f..5b6799e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -102,6 +102,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1..592034b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -671,6 +671,50 @@
status = "disabled";
};
+ sata0: sata@320 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x320 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata1: sata@321 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x321 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata2: sata@322 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x322 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata3: sata@323 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x323 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
smmu: iommu@500 {
compatible = "arm,mmu-500";
reg = <0 0x500 0 0x80>;
--
1.7.1
[v3] arm64: dts: lx2160a: add sata node support
Add SATA device nodes for fsl-lx2160a and enable support
for QDS and RDB boards.
Signed-off-by: Peng Ma
---
changed for V3:
- updated the commit log
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44 +
3 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 99a22ab..1a5acf6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -95,6 +95,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f..5b6799e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -102,6 +102,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1..592034b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -671,6 +671,50 @@
status = "disabled";
};
+ sata0: sata@320 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x320 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata1: sata@321 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x321 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata2: sata@322 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x322 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata3: sata@323 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x323 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
smmu: iommu@500 {
compatible = "arm,mmu-500";
reg = <0 0x500 0 0x80>;
--
1.7.1
[v2] arm64: dts: lx2160a: add sata node support
Add sata node support and Enable sata support
Signed-off-by: Peng Ma
---
changed for V2:
- put the 'status' at the end of property list
- add lx2160aqds sata support
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44 +
3 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 99a22ab..0289955 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -110,3 +110,19 @@
&usb1 {
status = "okay";
};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f..aacca27 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -117,3 +117,19 @@
&usb1 {
status = "okay";
};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1..4390aea 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -762,5 +762,49 @@
;
dma-coherent;
};
+
+ sata0: sata@320 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x320 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata1: sata@321 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x321 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata2: sata@322 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x322 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata3: sata@323 {
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x323 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ status = "disabled";
+ };
};
};
--
1.7.1
RE: [PATCH 2/2] arm64: dts: lx2160a: add sata node support
>-Original Message-
>From: Shawn Guo
>Sent: 2019年1月13日 12:06
>To: Peng Ma
>Cc: ax...@kernel.dk; Leo Li ; robh...@kernel.org;
>mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
>devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
>linux-...@vger.kernel.org
>Subject: Re: [PATCH 2/2] arm64: dts: lx2160a: add sata node support
>
>On Thu, Jan 10, 2019 at 06:05:33PM +0800, Peng Ma wrote:
>> Add sata node support and Enable sata support
>>
>> Signed-off-by: Peng Ma
>> ---
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44
>+
>> 2 files changed, 60 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> index 6481e5f..aacca27 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> @@ -117,3 +117,19 @@
>> &usb1 {
>> status = "okay";
>> };
>> +
>> +&sata0 {
>> +status = "okay";
>> +};
>> +
>> +&sata1 {
>> +status = "okay";
>> +};
>> +
>> +&sata2 {
>> +status = "okay";
>> +};
>> +
>> +&sata3 {
>> +status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> index a79f5c1..e857a14 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> @@ -762,5 +762,49 @@
>> ;
>> dma-coherent;
>> };
>> +
>> +sata0: sata@320 {
>> +status = "disabled";
>
>We usually have 'status' at the end of property list.
>
>Shawn
[Peng Ma]
Ok, got it, thanks yure quick reply.
Regards,
Peng
>
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x320 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +};
>> +
>> +sata1: sata@321 {
>> +status = "disabled";
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x321 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +};
>> +
>> +sata2: sata@322 {
>> +status = "disabled";
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x322 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +};
>> +
>> +sata3: sata@323 {
>> +status = "disabled";
>> +compatible = "fsl,lx2160a-ahci";
>> +reg = <0x0 0x323 0x0 0x1>,
>> + <0x7 0x100520 0x0 0x4>;
>> +reg-names = "ahci", "sata-ecc";
>> +interrupts = ;
>> +clocks = <&clockgen 4 3>;
>> +dma-coherent;
>> +};
>> };
>> };
>> --
>> 1.7.1
>>
RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>-Original Message-
>From: Leo Li
>Sent: 2019年1月11日 4:30
>To: Peng Ma ; shawn...@kernel.org; ax...@kernel.dk
>Cc: robh...@kernel.org; mark.rutl...@arm.com;
>linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
>linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; Andy Tang
>
>Subject: RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>
>
>
>> -Original Message-
>> From: Peng Ma
>> Sent: Thursday, January 10, 2019 4:32 AM
>> To: Peng Ma ; shawn...@kernel.org; ax...@kernel.dk
>> Cc: Leo Li ; robh...@kernel.org;
>> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
>> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
>> i...@vger.kernel.org; Andy Tang
>> Subject: RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>>
>> Hi Jens，
>>
>> I send the sata patchs to the upstream patchwork with
>> ./scripts/get_maintainer.pl, but I find my patch on
>> http://patchwork.ozlabs.org/project/linux-ide/list/ , I saw the
>> MAINTAINERS, the driver/ata/* should be on
>> https://patchwork.kernel.org/project/linux-
>> block/list/ . could you please help me what the patchwork is right.
>
>Peng,
>
>The patchwork used is related to the mailing list which you send the patch to
>not the maintainer's git tree used. Since the MAINTAINERS file says
>drivers/ata should use linux-ide mailing list, patches will appear in linux-ide
>patchwork.
>
>Regards,
>Leo
>
[Peng Ma] got it, thanks.
Best Regards,
Peng
>> Thanks a lot.
>>
>> Best Regards,
>> Peng
>>
>> >-Original Message-
>> >From: Peng Ma
>> >Sent: 2019年1月10日 18:06
>> >To: shawn...@kernel.org; ax...@kernel.dk
>> >Cc: Leo Li ; robh...@kernel.org;
>> >mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
>> >devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
>> >linux-...@vger.kernel.org; Peng Ma
>> >Subject: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>> >
>> >Lx2160a is a new introduced soc which supports ATA3.0 and Clean up
>> >some code
>> >
>> >Signed-off-by: Peng Ma
>> >---
>> > drivers/ata/ahci_qoriq.c | 44
>> >
>> > 1 files changed, 12 insertions(+), 32 deletions(-)
>> >
>> >diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
>> >index
>> >ce59253..1994bf2 100644
>> >--- a/drivers/ata/ahci_qoriq.c
>> >+++ b/drivers/ata/ahci_qoriq.c
>> >@@ -57,7 +57,7 @@ enum ahci_qoriq_type {
>> >AHCI_LS2080A,
>> >AHCI_LS1046A,
>> >AHCI_LS1088A,
>> >- AHCI_LS2088A,
>> >+ AHCI_LX2160A,
>> > };
>> >
>> > struct ahci_qoriq_priv {
>> >@@ -73,7 +73,7 @@ struct ahci_qoriq_priv {
>> >{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
>> >{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
>> >{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
>> >- { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
>> >+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
>> >{},
>> > };
>> > MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); @@ -174,12 +174,10
>> @@
>> >static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
>> >writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
>> >writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
>> >writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>> >- if (qpriv->is_dmacoherent)
>> >- writel(AHCI_PORT_AXICC_CFG,
>> >- reg_base + LS1021A_AXICC_ADDR);
>> >break;
>> >
>> >case AHCI_LS1043A:
>> >+ case AHCI_LS1046A:
>> >if (!qpriv->ecc_addr)
>> >return -EINVAL;
>> >writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, @@ -
>> 188,8
>> >+186,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
>> >+*hpriv)
>> >writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
>> >writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
>> >writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>> >- if (qpriv->is_dmacoherent)
>> >- writel(AHCI_PO
RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
Hi Jens，
I send the sata patchs to the upstream patchwork with
./scripts/get_maintainer.pl, but I find my patch on
http://patchwork.ozlabs.org/project/linux-ide/list/ , I saw the MAINTAINERS,
the driver/ata/* should be on
https://patchwork.kernel.org/project/linux-block/list/ . could you please help
me what the patchwork is right.
Thanks a lot.
Best Regards,
Peng
>-Original Message-
>From: Peng Ma
>Sent: 2019年1月10日 18:06
>To: shawn...@kernel.org; ax...@kernel.dk
>Cc: Leo Li ; robh...@kernel.org;
>mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
>devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
>linux-...@vger.kernel.org; Peng Ma
>Subject: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>
>Lx2160a is a new introduced soc which supports ATA3.0 and Clean up some
>code
>
>Signed-off-by: Peng Ma
>---
> drivers/ata/ahci_qoriq.c | 44
> 1 files changed, 12 insertions(+), 32 deletions(-)
>
>diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index
>ce59253..1994bf2 100644
>--- a/drivers/ata/ahci_qoriq.c
>+++ b/drivers/ata/ahci_qoriq.c
>@@ -57,7 +57,7 @@ enum ahci_qoriq_type {
> AHCI_LS2080A,
> AHCI_LS1046A,
> AHCI_LS1088A,
>- AHCI_LS2088A,
>+ AHCI_LX2160A,
> };
>
> struct ahci_qoriq_priv {
>@@ -73,7 +73,7 @@ struct ahci_qoriq_priv {
> { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
> { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
> { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
>- { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
>+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
> {},
> };
> MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); @@ -174,12 +174,10
>@@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
> writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG,
>- reg_base + LS1021A_AXICC_ADDR);
> break;
>
> case AHCI_LS1043A:
>+ case AHCI_LS1046A:
> if (!qpriv->ecc_addr)
> return -EINVAL;
> writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, @@ -188,8
>+186,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
>
> case AHCI_LS2080A:
>@@ -197,24 +193,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
>*hpriv)
> writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
>- break;
>-
>- case AHCI_LS1046A:
>- if (!qpriv->ecc_addr)
>- return -EINVAL;
>- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
>- qpriv->ecc_addr);
>- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
>- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
>- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
>- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
>
> case AHCI_LS1088A:
>+ case AHCI_LX2160A:
> if (!qpriv->ecc_addr)
> return -EINVAL;
> writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A, @@ -223,18
>+205,16 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXIC
[PATCH 2/2] arm64: dts: lx2160a: add sata node support
Add sata node support and Enable sata support
Signed-off-by: Peng Ma
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 44 +
2 files changed, 60 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f..aacca27 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -117,3 +117,19 @@
&usb1 {
status = "okay";
};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1..e857a14 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -762,5 +762,49 @@
;
dma-coherent;
};
+
+ sata0: sata@320 {
+ status = "disabled";
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x320 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ };
+
+ sata1: sata@321 {
+ status = "disabled";
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x321 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ };
+
+ sata2: sata@322 {
+ status = "disabled";
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x322 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ };
+
+ sata3: sata@323 {
+ status = "disabled";
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x323 0x0 0x1>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = ;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ };
};
};
--
1.7.1
[PATCH 1/2] ahci: qoriq: add lx2160 platforms support
Lx2160a is a new introduced soc which supports ATA3.0 and
Clean up some code
Signed-off-by: Peng Ma
---
drivers/ata/ahci_qoriq.c | 44
1 files changed, 12 insertions(+), 32 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index ce59253..1994bf2 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -57,7 +57,7 @@ enum ahci_qoriq_type {
AHCI_LS2080A,
AHCI_LS1046A,
AHCI_LS1088A,
- AHCI_LS2088A,
+ AHCI_LX2160A,
};
struct ahci_qoriq_priv {
@@ -73,7 +73,7 @@ struct ahci_qoriq_priv {
{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
- { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
@@ -174,12 +174,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG,
- reg_base + LS1021A_AXICC_ADDR);
break;
case AHCI_LS1043A:
+ case AHCI_LS1046A:
if (!qpriv->ecc_addr)
return -EINVAL;
writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
@@ -188,8 +186,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS2080A:
@@ -197,24 +193,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
- break;
-
- case AHCI_LS1046A:
- if (!qpriv->ecc_addr)
- return -EINVAL;
- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
- qpriv->ecc_addr);
- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS1088A:
+ case AHCI_LX2160A:
if (!qpriv->ecc_addr)
return -EINVAL;
writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
@@ -223,18 +205,16 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
*hpriv)
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
+ }
- case AHCI_LS2088A:
- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
- break;
+ if (qpriv->is_dmacoherent) {
+ if (qpriv->type == AHCI_LS1021A)
+ writel(AHCI_PORT_AXICC_CFG,
+ reg_base + LS1021A_AXICC_ADDR);
+ else
+ writel(AHCI_PORT_AXICC_CFG,
+ reg_base + PORT_AXICC);
}
return 0;
--
1.7.1
[PATCH] dmaengine: fsl-dpaa2-qdma: Add qDMA controller driver for Layerscape SoCs
Add NXP Data Path Acceleration Architecture 2 (dpaa2) queue direct
memory(qDMA) controller driver support.
This module can be found on NXP LS2 SoCs.
Signed-off-by: Peng Ma
---
drivers/dma/Kconfig |2 +
drivers/dma/Makefile|1 +
drivers/dma/fsl-dpaa2-qdma/Kconfig |8 +
drivers/dma/fsl-dpaa2-qdma/Makefile |8 +
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 781 +++
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 152 ++
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 483 +
drivers/dma/fsl-dpaa2-qdma/fsl_dpdmai.h | 524 ++
drivers/dma/fsl-dpaa2-qdma/fsl_dpdmai_cmd.h | 197 +++
9 files changed, 2156 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Kconfig
create mode 100644 drivers/dma/fsl-dpaa2-qdma/Makefile
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h
create mode 100644 drivers/dma/fsl-dpaa2-qdma/dpdmai.c
create mode 100644 drivers/dma/fsl-dpaa2-qdma/fsl_dpdmai.h
create mode 100644 drivers/dma/fsl-dpaa2-qdma/fsl_dpdmai_cmd.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index de511db..f0d8125 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -646,6 +646,8 @@ source "drivers/dma/sh/Kconfig"
source "drivers/dma/ti/Kconfig"
+source drivers/dma/fsl-dpaa2-qdma/Kconfig
+
# clients
comment "DMA Clients"
depends on DMA_ENGINE
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 7fcc4d8..f542823 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
+obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
obj-y += mediatek/
obj-y += qcom/
diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig
b/drivers/dma/fsl-dpaa2-qdma/Kconfig
new file mode 100644
index 000..ec591fc
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig
@@ -0,0 +1,8 @@
+menuconfig FSL_DPAA2_QDMA
+ tristate "NXP DPAA2 QDMA"
+ depends on FSL_MC_BUS && FSL_MC_DPIO
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ NXP Data Path Acceleration Architecture 2 QDMA driver,
+ using the NXP MC bus driver.
diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile
b/drivers/dma/fsl-dpaa2-qdma/Makefile
new file mode 100644
index 000..4990282
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the NXP DPAA2 qDMA controllers
+#
+ccflags-y += -DVERSION=\"\"
+
+obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma.o
+
+fsl-dpaa2-qdma-objs:= dpaa2-qdma.o dpdmai.o
diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
new file mode 100644
index 000..1347281
--- /dev/null
+++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c
@@ -0,0 +1,781 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2014-2018 NXP
+
+/*
+ * Author: Changming Huang
+ *
+ * Driver for the NXP QDMA engine with QMan mode.
+ * Channel virtualization is supported through enqueuing of DMA jobs to,
+ * or dequeuing DMA jobs from different work queues with QMan portal.
+ * This module can be found on NXP LS2 SoCs.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+#include "fsl_dpdmai_cmd.h"
+#include "fsl_dpdmai.h"
+#include "dpaa2-qdma.h"
+
+static bool smmu_disable = true;
+
+static struct dpaa2_qdma_chan *to_dpaa2_qdma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct dpaa2_qdma_chan, vchan.chan);
+}
+
+static struct dpaa2_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct dpaa2_qdma_comp, vdesc);
+}
+
+static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma;
+ struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev;
+
+ dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev,
+ FD_POOL_SIZE, 32, 0);
+ if (!dpaa2_chan->fd_pool)
+ return -ENOMEM;
+
+ return dpaa2_qdma->desc_allocated++;
+}
+
+static void dpaa2_qdma_free_chan_resources(struct dma_chan *chan)
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma;
+ unsigned long flags;
+
+ LIST_HEAD(head);
+
+ spin_lock_irqsave(&dpaa2_chan->vchan.lock, flags);
+ vchan_get_all_descriptors(&dpaa2_chan->vchan, &head);
+ spin_unl
RE: [PATCH 3/3] arm64: dts: ls1046a: add qdma device tree nodes
Hi shawnguo,
I send this series patch to
http://patchwork.ozlabs.org/project/devicetree-bindings/list/
But I did not find patchs on devicetree patchwork, could I send patchs again.
Thanks.
Best Regards,
Peng
>-Original Message-
>From: Peng Ma
>Sent: 2018年12月6日 19:18
>To: vk...@kernel.org; shawn...@kernel.org
>Cc: Leo Li ; robh...@kernel.org;
>mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
>devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Peng Ma
>; Wen He
>Subject: [PATCH 3/3] arm64: dts: ls1046a: add qdma device tree nodes
>
>add the qDMA device tree nodes for LS1046A devices.
>
>Signed-off-by: Wen He
>Signed-off-by: Peng Ma
>---
>change in v12:
> - used GIC_SPI and IRQ_TYPE_LEVEL_HIGH to instead immediate
> number
>
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 21
>+
> 1 files changed, 21 insertions(+), 0 deletions(-)
>
>diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>index 51cbd50..8fcce79 100644
>--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>@@ -704,6 +704,27 @@
> < 0 0 4 &gic GIC_SPI 154
>IRQ_TYPE_LEVEL_HIGH>;
> };
>
>+ qdma: dma-controller@838 {
>+ compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
>+ reg = <0x0 0x838 0x0 0x1000>, /* Controller regs */
>+<0x0 0x839 0x0 0x1>, /* Status regs */
>+<0x0 0x83a 0x0 0x4>; /* Block regs */
>+ interrupts = ,
>+ ,
>+ ,
>+ ,
>+ ;
>+ interrupt-names = "qdma-error", "qdma-queue0",
>+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
>+ dma-channels = <8>;
>+ block-number = <1>;
>+ block-offset = <0x1>;
>+ fsl,dma-queues = <2>;
>+ status-sizes = <64>;
>+ queue-sizes = <64 64>;
>+ big-endian;
>+ };
>+
> };
>
> reserved-memory {
>--
>1.7.1
[v12 1/3] arm: dts: ls1021a: add qdma device tree nodes
add the qDMA device tree nodes for LS1021A devices.
Signed-off-by: Wen He
Signed-off-by: Peng Ma
---
change in v12:
- no
arch/arm/boot/dts/ls1021a.dtsi | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index bdd6e66..b3d7807 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -812,5 +812,25 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x1001 0x1>;
};
+
+ qdma: dma-controller@839 {
+ compatible = "fsl,ls1021a-qdma";
+ reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
+ <0x0 0x8389000 0x0 0x1000>, /* Status regs */
+ <0x0 0x838a000 0x0 0x2000>; /* Block regs */
+ interrupts = ,
+,
+;
+ interrupt-names = "qdma-error",
+ "qdma-queue0", "qdma-queue1";
+ dma-channels = <8>;
+ block-number = <1>;
+ block-offset = <0x1000>;
+ fsl,dma-queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
+
};
};
--
1.7.1
[PATCH 3/3] arm64: dts: ls1046a: add qdma device tree nodes
add the qDMA device tree nodes for LS1046A devices.
Signed-off-by: Wen He
Signed-off-by: Peng Ma
---
change in v12:
- used GIC_SPI and IRQ_TYPE_LEVEL_HIGH to instead immediate
number
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 51cbd50..8fcce79 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -704,6 +704,27 @@
< 0 0 4 &gic GIC_SPI 154
IRQ_TYPE_LEVEL_HIGH>;
};
+ qdma: dma-controller@838 {
+ compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
+ reg = <0x0 0x838 0x0 0x1000>, /* Controller regs */
+ <0x0 0x839 0x0 0x1>, /* Status regs */
+ <0x0 0x83a 0x0 0x4>; /* Block regs */
+ interrupts = ,
+,
+,
+,
+;
+ interrupt-names = "qdma-error", "qdma-queue0",
+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
+ dma-channels = <8>;
+ block-number = <1>;
+ block-offset = <0x1>;
+ fsl,dma-queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
+
};
reserved-memory {
--
1.7.1
[PATCH 2/3] arm64: dts: ls1043a: add qdma device tree nodes
add the qDMA device tree nodes for LS1043A devices.
Signed-off-by: Wen He
Signed-off-by: Peng Ma
---
change in v12:
- used GIC_SPI and IRQ_TYPE_LEVEL_HIGH to instead immediate
number
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 3fed504..23b78df 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -734,6 +734,28 @@
< 0 0 3 &gic 0 156 0x4>,
< 0 0 4 &gic 0 157 0x4>;
};
+
+ qdma: dma-controller@838 {
+ compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
+ reg = <0x0 0x838 0x0 0x1000>, /* Controller regs */
+ <0x0 0x839 0x0 0x1>, /* Status regs */
+ <0x0 0x83a 0x0 0x4>; /* Block regs */
+ interrupts = ,
+,
+,
+,
+;
+ interrupt-names = "qdma-error", "qdma-queue0",
+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
+ dma-channels = <8>;
+ block-number = <1>;
+ block-offset = <0x1>;
+ fsl,dma-queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
+
};
firmware {
--
1.7.1
[PATCH 1/7] dmaengine: fsldma: Replace DMA_IN/OUT by FSL_DMA_IN/OUT
From: Wen He
This patch implement a standard macro call functions is
used to NXP dma drivers.
Signed-off-by: Wen He
Signed-off-by: Peng Ma
---
change in v10:
- no
drivers/dma/fsldma.c | 16
drivers/dma/fsldma.h |4 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 1117b51..39871e0 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -53,42 +53,42 @@
static void set_sr(struct fsldma_chan *chan, u32 val)
{
- DMA_OUT(chan, &chan->regs->sr, val, 32);
+ FSL_DMA_OUT(chan, &chan->regs->sr, val, 32);
}
static u32 get_sr(struct fsldma_chan *chan)
{
- return DMA_IN(chan, &chan->regs->sr, 32);
+ return FSL_DMA_IN(chan, &chan->regs->sr, 32);
}
static void set_mr(struct fsldma_chan *chan, u32 val)
{
- DMA_OUT(chan, &chan->regs->mr, val, 32);
+ FSL_DMA_OUT(chan, &chan->regs->mr, val, 32);
}
static u32 get_mr(struct fsldma_chan *chan)
{
- return DMA_IN(chan, &chan->regs->mr, 32);
+ return FSL_DMA_IN(chan, &chan->regs->mr, 32);
}
static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
{
- DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
+ FSL_DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
}
static dma_addr_t get_cdar(struct fsldma_chan *chan)
{
- return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
+ return FSL_DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
}
static void set_bcr(struct fsldma_chan *chan, u32 val)
{
- DMA_OUT(chan, &chan->regs->bcr, val, 32);
+ FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32);
}
static u32 get_bcr(struct fsldma_chan *chan)
{
- return DMA_IN(chan, &chan->regs->bcr, 32);
+ return FSL_DMA_IN(chan, &chan->regs->bcr, 32);
}
/*
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 4787d48..982845b 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -223,10 +223,10 @@ static void out_le64(u64 __iomem *addr, u64 val)
}
#endif
-#define DMA_IN(fsl_chan, addr, width) \
+#define FSL_DMA_IN(fsl_chan, addr, width) \
(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
in_be##width(addr) : in_le##width(addr))
-#define DMA_OUT(fsl_chan, addr, val, width)\
+#define FSL_DMA_OUT(fsl_chan, addr, val, width)\
(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
out_be##width(addr, val) : out_le##width(addr, val))
--
1.7.1
[PATCH 7/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings
Document the devicetree bindings for NXP Layerscape qDMA controller
which could be found on NXP QorIQ Layerscape SoCs.
Signed-off-by: Wen He
Signed-off-by: Peng Ma
Reviewed-by: Rob Herring
---
change in v10:
- no
Documentation/devicetree/bindings/dma/fsl-qdma.txt | 57
1 files changed, 57 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt
b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
new file mode 100644
index 000..6a0ff90
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
@@ -0,0 +1,57 @@
+NXP Layerscape SoC qDMA Controller
+==
+
+This device follows the generic DMA bindings defined in dma/dma.txt.
+
+Required properties:
+
+- compatible: Must be one of
+"fsl,ls1021a-qdma": for LS1021A Board
+"fsl,ls1043a-qdma": for ls1043A Board
+"fsl,ls1046a-qdma": for ls1046A Board
+- reg: Should contain the register's base address and length.
+- interrupts: Should contain a reference to the interrupt used by this
+ device.
+- interrupt-names: Should contain interrupt names:
+"qdma-queue0": the block0 interrupt
+"qdma-queue1": the block1 interrupt
+"qdma-queue2": the block2 interrupt
+"qdma-queue3": the block3 interrupt
+"qdma-error": the error interrupt
+- fsl,dma-queues: Should contain number of queues supported.
+- dma-channels:Number of DMA channels supported
+- block-number:the virtual block number
+- block-offset:the offset of different virtual block
+- status-sizes:status queue size of per virtual block
+- queue-sizes: command queue size of per virtual block, the size number
+ based on queues
+
+Optional properties:
+
+- dma-channels:Number of DMA channels supported by the
controller.
+- big-endian: If present registers and hardware scatter/gather
descriptors
+ of the qDMA are implemented in big endian mode,
otherwise in little
+ mode.
+
+Examples:
+
+ qdma: dma-controller@839 {
+ compatible = "fsl,ls1021a-qdma";
+ reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
+ <0x0 0x8389000 0x0 0x1000>, /* Status regs */
+ <0x0 0x838a000 0x0 0x2000>; /* Block regs */
+ interrupts = ,
+,
+;
+ interrupt-names = "qdma-error",
+ "qdma-queue0", "qdma-queue1";
+ dma-channels = <8>;
+ block-number = <2>;
+ block-offset = <0x1000>;
+ fsl,dma-queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.1
[PATCH 3/7] dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs
NXP Queue DMA controller(qDMA) on Layerscape SoCs supports channel virtuallization by allowing DMA jobs to be enqueued into different command queues. Note that this module depends on NXP DPAA. Signed-off-by: Wen He Signed-off-by: Jiaheng Fan Signed-off-by: Peng Ma --- change in v10: - no drivers/dma/Kconfig| 13 + drivers/dma/Makefile |1 + drivers/dma/fsl-qdma.c | 1257 3 files changed, 1271 insertions(+), 0 deletions(-) create mode 100644 drivers/dma/fsl-qdma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index dacf3f4..50e19d7 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -218,6 +218,19 @@ config FSL_EDMA multiplexing capability for DMA request sources(slot). This module can be found on Freescale Vybrid and LS-1 SoCs. +config FSL_QDMA + tristate "NXP Layerscape qDMA engine support" + depends on ARM || ARM64 + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + select DMA_ENGINE_RAID + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Support the NXP Layerscape qDMA engine with command queue and legacy mode. + Channel virtualization is supported through enqueuing of DMA jobs to, + or dequeuing DMA jobs from, different work queues. + This module can be found on NXP Layerscape SoCs. + config FSL_RAID tristate "Freescale RAID engine Support" depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index c91702d..2d1b586 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o +obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o obj-$(CONFIG_HSU_DMA) += hsu/ obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c new file mode 100644 index 000..404869e --- /dev/null +++ b/drivers/dma/fsl-qdma.c @@ -0,0 +1,1257 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright 2018 NXP + +/* + * Driver for NXP Layerscape Queue Direct Memory Access Controller + * + * Author: + * Wen He + * Jiaheng Fan + * + */ + +#include +#include +#include +#include +#include +#include + +#include "virt-dma.h" +#include "fsldma.h" + +/* Register related definition */ +#define FSL_QDMA_DMR 0x0 +#define FSL_QDMA_DSR 0x4 +#define FSL_QDMA_DEIER 0xe00 +#define FSL_QDMA_DEDR 0xe04 +#define FSL_QDMA_DECFDW0R 0xe10 +#define FSL_QDMA_DECFDW1R 0xe14 +#define FSL_QDMA_DECFDW2R 0xe18 +#define FSL_QDMA_DECFDW3R 0xe1c +#define FSL_QDMA_DECFQIDR 0xe30 +#define FSL_QDMA_DECBR 0xe34 + +#define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x)) +#define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x)) +#define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x)) +#define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x)) +#define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x)) +#define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x)) +#define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x)) +#define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x)) + +#define FSL_QDMA_SQDPAR0x80c +#define FSL_QDMA_SQEPAR0x814 +#define FSL_QDMA_BSQMR 0x800 +#define FSL_QDMA_BSQSR 0x804 +#define FSL_QDMA_BSQICR0x828 +#define FSL_QDMA_CQMR 0xa00 +#define FSL_QDMA_CQDSCR1 0xa08 +#define FSL_QDMA_CQDSCR20xa0c +#define FSL_QDMA_CQIER 0xa10 +#define FSL_QDMA_CQEDR 0xa14 +#define FSL_QDMA_SQCCMR0xa20 + +/* Registers for bit and genmask */ +#define FSL_QDMA_CQIDR_SQT BIT(15) +#define QDMA_CCDF_FOTMAT BIT(29) +#define QDMA_CCDF_SER BIT(30) +#define QDMA_SG_FINBIT(30) +#define QDMA_SG_LEN_MASK GENMASK(29, 0) +#define QDMA_CCDF_MASK GENMASK(28, 20) + +#define FSL_QDMA_DEDR_CLEARGENMASK(31, 0) +#define FSL_QDMA_BCQIDR_CLEAR GENMASK(31, 0) +#define FSL_QDMA_DEIER_CLEAR GENMASK(31, 0) + +#define FSL_QDMA_BCQIER_CQTIE BIT(15) +#define FSL_QDMA_BCQIER_CQPEIE BIT(23) +#define FSL_QDMA_BSQICR_ICEN BIT(31) + +#define FSL_QDMA_BSQICR_ICST(x)((x) << 16) +#define FSL_QDMA_CQIER_MEIEBIT(31) +#define FSL_QDMA_CQIER_TEIEBIT(0) +#define FSL_QDMA_SQCCMR_ENTER_WM BIT(21) + +#define FSL_QDMA_BCQMR_EN BIT(31) +#define FSL_QDMA_BCQMR_EI BIT(
[PATCH 6/7] arm64: dts: ls1046a: add qdma device tree nodes
add the qDMA device tree nodes for LS1046A devices.
Signed-off-by: Wen He
Signed-off-by: Peng Ma
---
change in v10:
- no
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index ef83786..dc65318 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -704,6 +704,27 @@
< 0 0 4 &gic GIC_SPI 154
IRQ_TYPE_LEVEL_HIGH>;
};
+ qdma: dma-controller@838 {
+ compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
+ reg = <0x0 0x838 0x0 0x1000>, /* Controller regs */
+ <0x0 0x839 0x0 0x1>, /* Status regs */
+ <0x0 0x83a 0x0 0x4>; /* Block regs */
+ interrupts = <0 153 0x4>,
+<0 39 0x4>,
+<0 40 0x4>,
+<0 41 0x4>,
+<0 42 0x4>;
+ interrupt-names = "qdma-error", "qdma-queue0",
+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
+ dma-channels = <8>;
+ block-number = <1>;
+ block-offset = <0x1>;
+ fsl,dma-queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
+
};
reserved-memory {
--
1.7.1
[PATCH 5/7] arm64: dts: ls1043a: add qdma device tree nodes
add the qDMA device tree nodes for LS1043A devices.
Signed-off-by: Wen He
Signed-off-by: Peng Ma
---
change in v10:
- no
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 7881e3d..d560141 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -734,6 +734,28 @@
< 0 0 3 &gic 0 156 0x4>,
< 0 0 4 &gic 0 157 0x4>;
};
+
+ qdma: dma-controller@838 {
+ compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
+ reg = <0x0 0x838 0x0 0x1000>, /* Controller regs */
+ <0x0 0x839 0x0 0x1>, /* Status regs */
+ <0x0 0x83a 0x0 0x4>; /* Block regs */
+ interrupts = <0 153 0x4>,
+<0 39 0x4>,
+<0 40 0x4>,
+<0 41 0x4>,
+<0 42 0x4>;
+ interrupt-names = "qdma-error", "qdma-queue0",
+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
+ dma-channels = <8>;
+ block-number = <1>;
+ block-offset = <0x1>;
+ fsl,dma-queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
+
};
firmware {
--
1.7.1
[PATCH 4/7] arm: dts: ls1021a: add qdma device tree nodes
add the qDMA device tree nodes for LS1021A devices.
Signed-off-by: Peng Ma
---
arch/arm/boot/dts/ls1021a.dtsi | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index f184905..abc50da 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -806,5 +806,21 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x1001 0x1>;
};
+
+ qdma: qdma@839 {
+ compatible = "fsl,ls1021a-qdma";
+ reg = <0x0 0x8398000 0x0 0x1000>, /* Controller regs */
+ <0x0 0x8399000 0x0 0x1000>, /* Status regs */
+ <0x0 0x839a000 0x0 0x2000>; /* Block regs */
+ interrupts = ,
+;
+ interrupt-names = "qdma-error", "qdma-queue";
+ channels = <8>;
+ queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
+
};
};
--
1.7.1
[PATCH 3/7] dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs
NXP Queue DMA controller(qDMA) on Layerscape SoCs supports channel virtuallization by allowing DMA jobs to be enqueued into different command queues. Signed-off-by: Peng Ma --- drivers/dma/Kconfig| 13 + drivers/dma/Makefile |1 + drivers/dma/fsl-qdma.c | 1282 3 files changed, 1296 insertions(+), 0 deletions(-) create mode 100644 drivers/dma/fsl-qdma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index dacf3f4..50e19d7 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -218,6 +218,19 @@ config FSL_EDMA multiplexing capability for DMA request sources(slot). This module can be found on Freescale Vybrid and LS-1 SoCs. +config FSL_QDMA + tristate "NXP Layerscape qDMA engine support" + depends on ARM || ARM64 + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + select DMA_ENGINE_RAID + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Support the NXP Layerscape qDMA engine with command queue and legacy mode. + Channel virtualization is supported through enqueuing of DMA jobs to, + or dequeuing DMA jobs from, different work queues. + This module can be found on NXP Layerscape SoCs. + config FSL_RAID tristate "Freescale RAID engine Support" depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index c91702d..2d1b586 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o +obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o obj-$(CONFIG_HSU_DMA) += hsu/ obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c new file mode 100644 index 000..71a4f2c --- /dev/null +++ b/drivers/dma/fsl-qdma.c @@ -0,0 +1,1282 @@ +/* + * Driver for NXP Layerscape Queue direct memory access controller (qDMA) + * + * Copyright 2018 NXP + * + * Author: + * Jiaheng Fan + * Wen He + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "virt-dma.h" +#include "fsldma.h" + +/* Register related definition */ +#define FSL_QDMA_DMR 0x0 +#define FSL_QDMA_DSR 0x4 +#define FSL_QDMA_DEIER 0xe00 +#define FSL_QDMA_DEDR 0xe04 +#define FSL_QDMA_DECFDW0R 0xe10 +#define FSL_QDMA_DECFDW1R 0xe14 +#define FSL_QDMA_DECFDW2R 0xe18 +#define FSL_QDMA_DECFDW3R 0xe1c +#define FSL_QDMA_DECFQIDR 0xe30 +#define FSL_QDMA_DECBR 0xe34 + +#define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x)) +#define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x)) +#define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x)) +#define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x)) +#define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x)) +#define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x)) +#define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x)) +#define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x)) + +#define FSL_QDMA_SQDPAR0x80c +#define FSL_QDMA_SQEPAR0x814 +#define FSL_QDMA_BSQMR 0x800 +#define FSL_QDMA_BSQSR 0x804 +#define FSL_QDMA_BSQICR0x828 +#define FSL_QDMA_CQMR 0xa00 +#define FSL_QDMA_CQDSCR1 0xa08 +#define FSL_QDMA_CQDSCR20xa0c +#define FSL_QDMA_CQIER 0xa10 +#define FSL_QDMA_CQEDR 0xa14 +#define FSL_QDMA_SQCCMR0xa20 + +/* Registers for bit and genmask */ +#define FSL_QDMA_CQIDR_SQT BIT(15) +#define QDMA_CCDF_FOTMAT BIT(29) +#define QDMA_CCDF_SER BIT(30) +#define QDMA_SG_FINBIT(30) +#define QDMA_SG_LEN_MASK GENMASK(29, 0) +#define QDMA_CCDF_MASK GENMASK(28, 20) + +#define FSL_QDMA_BCQIER_CQTIE BIT(15) +#define FSL_QDMA_BCQIER_CQPEIE BIT(23) +#define FSL_QDMA_BSQICR_ICEN BIT(31) + +#define FSL_QDMA_BSQICR_ICST(x)((x) << 16) +#define FSL_QDMA_CQIER_MEIEBIT(31) +#define FSL_QDMA_CQIER_TEIEBIT(0) +#define FSL_QDMA_SQCCMR_ENTER_WM BIT(21) + +#define FSL_QDMA_BCQMR_EN BIT(31) +#define FSL_QDMA_BCQMR_EI BIT(30) +#define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20) +#define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16) + +#define FSL_QDMA_BCQSR_QF BIT(16) +#define FSL_QDMA_BCQSR_XOFF
[PATCH 7/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings
Document the devicetree bindings for NXP Layerscape qDMA controller
which could be found on NXP QorIQ Layerscape SoCs.
Signed-off-by: Peng Ma
---
Documentation/devicetree/bindings/dma/fsl-qdma.txt | 53
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt
b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
new file mode 100644
index 000..7e2160b
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
@@ -0,0 +1,53 @@
+NXP Layerscape SoC qDMA Controller
+==
+
+The qDMA supports channel virtualization by allowing DMA jobs to be enqueued
into
+different command queues. Core can initiate a DMA transaction by preparing a
command
+descriptor for each DMA job and enqueuing this job to a command queue.
+
+Required properties:
+- compatible: Must be one of
+ "fsl,ls1021a-qdma": for LS1021A Board
+ "fsl,ls1043a-qdma": for ls1043A Board
+ "fsl,ls1046a-qdma": for ls1046A Board
+- reg : Specifies base physical address(s) and size of the qDMA registers.
+ The 1st region is qDMA control register's address and size.
+ The 2nd region is status queue control register's address and size.
+ The 3rd region is virtual block control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+ interrupt-names.
+- interrupt-names : Should contain:
+ "qdma-queue0" - the block0 interrupt
+ "qdma-queue1" - the block1 interrupt
+ "qdma-queue2" - the block2 interrupt
+ "qdma-queue3" - the block3 interrupt
+ "qdma-error" - the error interrupt
+- channels : Number of DMA channels supported
+- block-number : the virtual block number
+- block-offset : the offset of different virtual block
+- queues : the number of command queue per virtual block
+- status-sizes : status queue size of per virtual block
+- queue-sizes : command queue size of per virtual block, the size number based
on queues
+- big-endian: If present registers and hardware scatter/gather descriptors
+ of the qDMA are implemented in big endian mode, otherwise in little
+ mode.
+
+Examples:
+ qdma: qdma@839 {
+ compatible = "fsl,ls1021a-qdma";
+ reg = <0x0 0x8388000 0x0 0x1000>, /* Controller
regs */
+ <0x0 0x8389000 0x0 0x1000>, /* Status
regs */
+ <0x0 0x838a000 0x0 0x2000>; /* Block regs
*/
+ interrupts = ,
+,
+;
+ interrupt-names = "qdma-error",
+ "qdma-queue0", "qdma-queue1";
+ channels = <8>;
+ block-number = <2>;
+ block-offset = <0x1000>;
+ queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
--
1.7.1
[PATCH 6/7] arm64: dts: ls1046a: add qdma device tree nodes
add the qDMA device tree nodes for LS1046A devices.
Signed-off-by: Peng Ma
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index ef83786..9f36293 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -704,6 +704,27 @@
< 0 0 4 &gic GIC_SPI 154
IRQ_TYPE_LEVEL_HIGH>;
};
+ qdma: qdma@838 {
+ compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
+ reg = <0x0 0x838 0x0 0x1000>, /* Controller regs */
+ <0x0 0x839 0x0 0x1>, /* Status regs */
+ <0x0 0x83a 0x0 0x4>; /* Block regs */
+ interrupts = <0 153 0x4>,
+<0 39 0x4>,
+<0 40 0x4>,
+<0 41 0x4>,
+<0 42 0x4>;
+ interrupt-names = "qdma-error", "qdma-queue0",
+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
+ channels = <8>;
+ block-number = <1>;
+ block-offset = <0x1>;
+ queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
+
};
reserved-memory {
--
1.7.1
[PATCH 1/7] dmaengine: fsldma: Replace DMA_IN/OUT by FSL_DMA_IN/OUT
From: Wen He
This patch implement a standard macro call functions is
used to NXP dma drivers.
Signed-off-by: Wen He
---
drivers/dma/fsldma.c | 16
drivers/dma/fsldma.h |4 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 1117b51..39871e0 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -53,42 +53,42 @@
static void set_sr(struct fsldma_chan *chan, u32 val)
{
- DMA_OUT(chan, &chan->regs->sr, val, 32);
+ FSL_DMA_OUT(chan, &chan->regs->sr, val, 32);
}
static u32 get_sr(struct fsldma_chan *chan)
{
- return DMA_IN(chan, &chan->regs->sr, 32);
+ return FSL_DMA_IN(chan, &chan->regs->sr, 32);
}
static void set_mr(struct fsldma_chan *chan, u32 val)
{
- DMA_OUT(chan, &chan->regs->mr, val, 32);
+ FSL_DMA_OUT(chan, &chan->regs->mr, val, 32);
}
static u32 get_mr(struct fsldma_chan *chan)
{
- return DMA_IN(chan, &chan->regs->mr, 32);
+ return FSL_DMA_IN(chan, &chan->regs->mr, 32);
}
static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
{
- DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
+ FSL_DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
}
static dma_addr_t get_cdar(struct fsldma_chan *chan)
{
- return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
+ return FSL_DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
}
static void set_bcr(struct fsldma_chan *chan, u32 val)
{
- DMA_OUT(chan, &chan->regs->bcr, val, 32);
+ FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32);
}
static u32 get_bcr(struct fsldma_chan *chan)
{
- return DMA_IN(chan, &chan->regs->bcr, 32);
+ return FSL_DMA_IN(chan, &chan->regs->bcr, 32);
}
/*
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 4787d48..982845b 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -223,10 +223,10 @@ static void out_le64(u64 __iomem *addr, u64 val)
}
#endif
-#define DMA_IN(fsl_chan, addr, width) \
+#define FSL_DMA_IN(fsl_chan, addr, width) \
(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
in_be##width(addr) : in_le##width(addr))
-#define DMA_OUT(fsl_chan, addr, val, width)\
+#define FSL_DMA_OUT(fsl_chan, addr, val, width)\
(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
out_be##width(addr, val) : out_le##width(addr, val))
--
1.7.1
[PATCH 2/7] dmaengine: fsldma: Adding macro FSL_DMA_IN/OUT implement for ARM platform
From: Wen He
This patch add the macro FSL_DMA_IN/OUT implement for ARM platform.
Signed-off-by: Wen He
---
drivers/dma/fsldma.h | 57 +
1 files changed, 38 insertions(+), 19 deletions(-)
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 982845b..1dc64c9 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -196,39 +196,58 @@ struct fsldma_chan {
#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
+#ifdef CONFIG_PPC
+#define fsl_ioread32(p)in_le32(p)
+#define fsl_ioread32be(p) in_be32(p)
+#define fsl_iowrite32(v, p)out_le32(p, v)
+#define fsl_iowrite32be(v, p) out_be32(p, v)
+
#ifndef __powerpc64__
-static u64 in_be64(const u64 __iomem *addr)
+static u64 fsl_ioread64(const u64 __iomem *addr)
{
- return ((u64)in_be32((u32 __iomem *)addr) << 32) |
- (in_be32((u32 __iomem *)addr + 1));
+ return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
+ (in_le32((u32 __iomem *)addr));
}
-static void out_be64(u64 __iomem *addr, u64 val)
+static void fsl_iowrite64(u64 val, u64 __iomem *addr)
{
- out_be32((u32 __iomem *)addr, val >> 32);
- out_be32((u32 __iomem *)addr + 1, (u32)val);
+ out_le32((u32 __iomem *)addr + 1, val >> 32);
+ out_le32((u32 __iomem *)addr, (u32)val);
}
-/* There is no asm instructions for 64 bits reverse loads and stores */
-static u64 in_le64(const u64 __iomem *addr)
+static u64 fsl_ioread64be(const u64 __iomem *addr)
{
- return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
- (in_le32((u32 __iomem *)addr));
+ return ((u64)in_be32((u32 __iomem *)addr) << 32) |
+ (in_be32((u32 __iomem *)addr + 1));
}
-static void out_le64(u64 __iomem *addr, u64 val)
+static void fsl_iowrite64be(u64 val, u64 __iomem *addr)
{
- out_le32((u32 __iomem *)addr + 1, val >> 32);
- out_le32((u32 __iomem *)addr, (u32)val);
+ out_be32((u32 __iomem *)addr, val >> 32);
+ out_be32((u32 __iomem *)addr + 1, (u32)val);
}
#endif
+#endif
-#define FSL_DMA_IN(fsl_chan, addr, width) \
- (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
- in_be##width(addr) : in_le##width(addr))
-#define FSL_DMA_OUT(fsl_chan, addr, val, width)\
- (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
- out_be##width(addr, val) : out_le##width(addr, val))
+#if defined(CONFIG_ARM64) || defined(CONFIG_ARM)
+#define fsl_ioread32(p)ioread32(p)
+#define fsl_ioread32be(p) ioread32be(p)
+#define fsl_iowrite32(v, p)iowrite32(v, p)
+#define fsl_iowrite32be(v, p) iowrite32be(v, p)
+#define fsl_ioread64(p)ioread64(p)
+#define fsl_ioread64be(p) ioread64be(p)
+#define fsl_iowrite64(v, p)iowrite64(v, p)
+#define fsl_iowrite64be(v, p) iowrite64be(v, p)
+#endif
+
+#define FSL_DMA_IN(fsl_dma, addr, width) \
+ (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ?\
+ fsl_ioread##width##be(addr) : fsl_ioread##width(addr))
+
+#define FSL_DMA_OUT(fsl_dma, addr, val, width) \
+ (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ?\
+ fsl_iowrite##width##be(val, addr) : fsl_iowrite \
+ ##width(val, addr))
#define DMA_TO_CPU(fsl_chan, d, width) \
(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
--
1.7.1
[PATCH 5/7] arm64: dts: ls1043a: add qdma device tree nodes
add the qDMA device tree nodes for LS1043A devices.
Signed-off-by: Peng Ma
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 7881e3d..49c6655 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -734,6 +734,28 @@
< 0 0 3 &gic 0 156 0x4>,
< 0 0 4 &gic 0 157 0x4>;
};
+
+ qdma: qdma@838 {
+ compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
+ reg = <0x0 0x838 0x0 0x1000>, /* Controller regs */
+ <0x0 0x839 0x0 0x1>, /* Status regs */
+ <0x0 0x83a 0x0 0x4>; /* Block regs */
+ interrupts = <0 153 0x4>,
+<0 39 0x4>,
+<0 40 0x4>,
+<0 41 0x4>,
+<0 42 0x4>;
+ interrupt-names = "qdma-error", "qdma-queue0",
+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
+ channels = <8>;
+ block-number = <1>;
+ block-offset = <0x1>;
+ queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
+
};
firmware {
--
1.7.1
