Re: [PATCH 1/3] cpuidle: coupled: disable interrupts after entering safe state

[Prashant Gaikwad]

On Saturday 24 August 2013 01:15 AM, Colin Cross wrote:

Calling cpuidle_enter_state is expected to return with interrupts
enabled, but interrupts must be disabled before starting the
ready loop synchronization stage.  Call local_irq_disable after
each call to cpuidle_enter_state for the safe state.

CC: sta...@vger.kernel.org
Signed-off-by: Colin Cross 
---
  drivers/cpuidle/coupled.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
index 2a297f8..db92bcb 100644
--- a/drivers/cpuidle/coupled.c
+++ b/drivers/cpuidle/coupled.c
@@ -460,6 +460,7 @@ int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
}
entered_state = cpuidle_enter_state(dev, drv,
dev->safe_state_index);
+   local_irq_disable();


Colin,

There is still some window where irq remains enabled after exiting safe 
state. It may introduce some corner case.
Instead of this can we pass a parameter to cpuidle_enter_state 
indicating that irq has to be enabled or not after exit from idle state, 
which would be false when entering safe state from coupled idle.



}
  
  	/* Read barrier ensures online_count is read after prevent is cleared */

@@ -485,6 +486,7 @@ retry:
  
  		entered_state = cpuidle_enter_state(dev, drv,

dev->safe_state_index);
+   local_irq_disable();
}
  
  	if (cpuidle_coupled_clear_pokes(dev->cpu)) {


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Re: [PATCH 1/3] cpuidle: coupled: disable interrupts after entering safe state

[Prashant Gaikwad]

On Saturday 24 August 2013 01:15 AM, Colin Cross wrote:

Calling cpuidle_enter_state is expected to return with interrupts
enabled, but interrupts must be disabled before starting the
ready loop synchronization stage.  Call local_irq_disable after
each call to cpuidle_enter_state for the safe state.

CC: sta...@vger.kernel.org
Signed-off-by: Colin Cross ccr...@android.com
---
  drivers/cpuidle/coupled.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
index 2a297f8..db92bcb 100644
--- a/drivers/cpuidle/coupled.c
+++ b/drivers/cpuidle/coupled.c
@@ -460,6 +460,7 @@ int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
}
entered_state = cpuidle_enter_state(dev, drv,
dev-safe_state_index);
+   local_irq_disable();


Colin,

There is still some window where irq remains enabled after exiting safe 
state. It may introduce some corner case.
Instead of this can we pass a parameter to cpuidle_enter_state 
indicating that irq has to be enabled or not after exit from idle state, 
which would be false when entering safe state from coupled idle.



}
  
  	/* Read barrier ensures online_count is read after prevent is cleared */

@@ -485,6 +486,7 @@ retry:
  
  		entered_state = cpuidle_enter_state(dev, drv,

dev-safe_state_index);
+   local_irq_disable();
}
  
  	if (cpuidle_coupled_clear_pokes(dev-cpu)) {


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Re: [PATCH] clk: tegra30: Don't wait for PLL_U lock bit

[Prashant Gaikwad]

On Thursday 01 August 2013 02:34 AM, Stephen Warren wrote:

On 07/31/2013 11:42 AM, Tuomas Tynkkynen wrote:

The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.

Peter, Prashant,

I think you said that the lock bits should work on Tegra30 (albeit they
don't on Tegra20)? Can you remind me if the do/don't?

If Peter and Prashant are OK with this patch, feel free to take my ack.


Hi Tuomas,

Sorry for the delayed response. Please make sure that avdd_usb_pll 
regulator is enabled before enabling PLLU and utmip parameters are 
configured properly.
If this this regulator is not enabled then you will get this kind of 
timeout when enabling PLLU.


Thanks,
Prashant


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Re: [PATCH] clk: tegra30: Don't wait for PLL_U lock bit

[Prashant Gaikwad]

On Thursday 01 August 2013 02:34 AM, Stephen Warren wrote:

On 07/31/2013 11:42 AM, Tuomas Tynkkynen wrote:

The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.

Peter, Prashant,

I think you said that the lock bits should work on Tegra30 (albeit they
don't on Tegra20)? Can you remind me if the do/don't?

If Peter and Prashant are OK with this patch, feel free to take my ack.


Hi Tuomas,

Sorry for the delayed response. Please make sure that avdd_usb_pll 
regulator is enabled before enabling PLLU and utmip parameters are 
configured properly.
If this this regulator is not enabled then you will get this kind of 
timeout when enabling PLLU.


Thanks,
Prashant


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Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Prashant Gaikwad]

On Friday 07 June 2013 10:36 PM, Paul Walmsley wrote:

Hi Stephen,

On Fri, 7 Jun 2013, Stephen Warren wrote:


On 06/07/2013 06:19 AM, Paul Walmsley wrote:

Add DFLL DVCO reset line control functions to the CAR IP block driver.

The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block.  This reset line is asserted upon SoC
reset.  Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.

Thanks to Aleksandr Frid  for identifying this and
saving hours of debugging time.
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
  void tegra114_clock_tune_cpu_trimmers_high(void);
  void tegra114_clock_tune_cpu_trimmers_low(void);
  void tegra114_clock_tune_cpu_trimmers_init(void);
+void tegra114_clock_assert_dfll_dvco_reset(void);
+void tegra114_clock_deassert_dfll_dvco_reset(void);

Where/what is the code that will call these new APIs? If it's going to
be something in drivers/clk, that seems fine.

That's correct - they'll be used by the DFLL clocksource code, which will
live in drivers/clk/tegra.  You've seen the patches already ;-)


Why not implement these APIs in DFLL clock driver itself and pass RST 
address register to driver?



The reset assert/de-assert functions at least might be worth exposing
using the new generic module reset API. I believe Prashant Gaikwad is
working on converting the Tegra clock driver to be a module reset
provider, hence removing the existing custom
tegra_periph_reset_{de,}assert() APIs.

OK, will take a look to see if this can be done without getting in the way
of Prashant's work.  I'd naïvely assume that it might be best to convert
these as part of his series - that way we won't duplicate effort.

Prashant, what stage are you at in the conversion?  If you're close to
completion, maybe we can just add this functionality in with your patches?



You can continue with this patch. I do not see any need to add this 
reset control to generic reset module.



- Paul


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Re: [PATCH v2] clk: tegra: Use common of_clk_init function

[Prashant Gaikwad]

On Tuesday 28 May 2013 08:46 PM, Stephen Warren wrote:

On 05/27/2013 01:40 AM, Prashant Gaikwad wrote:

Use common of_clk_init() function for clocks initialization.


Mike,

Please merge this patch in your tree.

Thanks,
PrashantG

Acked-by: Stephen Warren 


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Re: [PATCH v2] clk: tegra: Use common of_clk_init function

[Prashant Gaikwad]

On Tuesday 28 May 2013 08:46 PM, Stephen Warren wrote:

On 05/27/2013 01:40 AM, Prashant Gaikwad wrote:

Use common of_clk_init() function for clocks initialization.


Mike,

Please merge this patch in your tree.

Thanks,
PrashantG

Acked-by: Stephen Warren swar...@nvidia.com


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Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Prashant Gaikwad]

On Friday 07 June 2013 10:36 PM, Paul Walmsley wrote:

Hi Stephen,

On Fri, 7 Jun 2013, Stephen Warren wrote:


On 06/07/2013 06:19 AM, Paul Walmsley wrote:

Add DFLL DVCO reset line control functions to the CAR IP block driver.

The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block.  This reset line is asserted upon SoC
reset.  Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.

Thanks to Aleksandr Frid af...@nvidia.com for identifying this and
saving hours of debugging time.
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
  void tegra114_clock_tune_cpu_trimmers_high(void);
  void tegra114_clock_tune_cpu_trimmers_low(void);
  void tegra114_clock_tune_cpu_trimmers_init(void);
+void tegra114_clock_assert_dfll_dvco_reset(void);
+void tegra114_clock_deassert_dfll_dvco_reset(void);

Where/what is the code that will call these new APIs? If it's going to
be something in drivers/clk, that seems fine.

That's correct - they'll be used by the DFLL clocksource code, which will
live in drivers/clk/tegra.  You've seen the patches already ;-)


Why not implement these APIs in DFLL clock driver itself and pass RST 
address register to driver?



The reset assert/de-assert functions at least might be worth exposing
using the new generic module reset API. I believe Prashant Gaikwad is
working on converting the Tegra clock driver to be a module reset
provider, hence removing the existing custom
tegra_periph_reset_{de,}assert() APIs.

OK, will take a look to see if this can be done without getting in the way
of Prashant's work.  I'd naïvely assume that it might be best to convert
these as part of his series - that way we won't duplicate effort.

Prashant, what stage are you at in the conversion?  If you're close to
completion, maybe we can just add this functionality in with your patches?



You can continue with this patch. I do not see any need to add this 
reset control to generic reset module.



- Paul


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[PATCH v2] clk: tegra: Use common of_clk_init function

[Prashant Gaikwad]

Use common of_clk_init() function for clocks initialization.

Signed-off-by: Prashant Gaikwad 
---

Included initialization for T114 in V2.

---
 arch/arm/mach-tegra/common.c |4 ++--
 drivers/clk/tegra/clk-tegra114.c |3 ++-
 drivers/clk/tegra/clk-tegra20.c  |3 ++-
 drivers/clk/tegra/clk-tegra30.c  |3 ++-
 drivers/clk/tegra/clk.c  |   12 
 drivers/clk/tegra/clk.h  |   18 --
 include/linux/clk/tegra.h|1 -
 7 files changed, 8 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6..95ce2a0 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -23,7 +23,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #include 
 
@@ -59,7 +59,7 @@ u32 tegra_uart_config[4] = {
 #ifdef CONFIG_OF
 void __init tegra_dt_init_irq(void)
 {
-   tegra_clocks_init();
+   of_clk_init(NULL);
tegra_pmc_init();
tegra_init_irq();
irqchip_init();
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16e..e0ee077 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -2030,7 +2030,7 @@ static void __init tegra114_clock_apply_init_table(void)
tegra_init_from_table(init_table, clks, clk_max);
 }
 
-void __init tegra114_clock_init(struct device_node *np)
+static void __init tegra114_clock_init(struct device_node *np)
 {
struct device_node *node;
int i;
@@ -2083,3 +2083,4 @@ void __init tegra114_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = _cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 8292a00..a25e07c 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1282,7 +1282,7 @@ static const struct of_device_id pmc_match[] __initconst 
= {
{},
 };
 
-void __init tegra20_clock_init(struct device_node *np)
+static void __init tegra20_clock_init(struct device_node *np)
 {
int i;
struct device_node *node;
@@ -1334,3 +1334,4 @@ void __init tegra20_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = _cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c6921f5..985ad69 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1953,7 +1953,7 @@ static const struct of_device_id pmc_match[] __initconst 
= {
{},
 };
 
-void __init tegra30_clock_init(struct device_node *np)
+static void __init tegra30_clock_init(struct device_node *np)
 {
struct device_node *node;
int i;
@@ -2004,3 +2004,4 @@ void __init tegra30_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = _cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 923ca7e..86581ac 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -74,18 +74,6 @@ void __init tegra_init_from_table(struct 
tegra_clk_init_table *tbl,
}
 }
 
-static const struct of_device_id tegra_dt_clk_match[] = {
-   { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
-   { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
-   { .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
-   { }
-};
-
-void __init tegra_clocks_init(void)
-{
-   of_clk_init(tegra_dt_clk_match);
-}
-
 tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 
 void __init tegra_clocks_apply_init_table(void)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e056562..11278a8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -571,24 +571,6 @@ void tegra_init_from_table(struct tegra_clk_init_table 
*tbl,
 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
struct clk *clks[], int clk_max);
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void tegra20_clock_init(struct device_node *np);
-#else
-static inline void tegra20_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_2x_SOC */
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void tegra30_clock_init(struct device_node *np);
-#else
-static inline void tegra30_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
-void tegra114_clock_init(struct device_node *np);
-#else
-static inline void tegra114_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA114_SOC */
-
 typedef void (*tegra_clk_apply_init_table_func)(void);
 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
i

[PATCH v2] clk: tegra: Use common of_clk_init function

[Prashant Gaikwad]

Use common of_clk_init() function for clocks initialization.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Included initialization for T114 in V2.

---
 arch/arm/mach-tegra/common.c |4 ++--
 drivers/clk/tegra/clk-tegra114.c |3 ++-
 drivers/clk/tegra/clk-tegra20.c  |3 ++-
 drivers/clk/tegra/clk-tegra30.c  |3 ++-
 drivers/clk/tegra/clk.c  |   12 
 drivers/clk/tegra/clk.h  |   18 --
 include/linux/clk/tegra.h|1 -
 7 files changed, 8 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6..95ce2a0 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -23,7 +23,7 @@
 #include linux/clk.h
 #include linux/delay.h
 #include linux/irqchip.h
-#include linux/clk/tegra.h
+#include linux/clk-provider.h
 
 #include asm/hardware/cache-l2x0.h
 
@@ -59,7 +59,7 @@ u32 tegra_uart_config[4] = {
 #ifdef CONFIG_OF
 void __init tegra_dt_init_irq(void)
 {
-   tegra_clocks_init();
+   of_clk_init(NULL);
tegra_pmc_init();
tegra_init_irq();
irqchip_init();
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16e..e0ee077 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -2030,7 +2030,7 @@ static void __init tegra114_clock_apply_init_table(void)
tegra_init_from_table(init_table, clks, clk_max);
 }
 
-void __init tegra114_clock_init(struct device_node *np)
+static void __init tegra114_clock_init(struct device_node *np)
 {
struct device_node *node;
int i;
@@ -2083,3 +2083,4 @@ void __init tegra114_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = tegra114_cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra114, nvidia,tegra114-car, tegra114_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 8292a00..a25e07c 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1282,7 +1282,7 @@ static const struct of_device_id pmc_match[] __initconst 
= {
{},
 };
 
-void __init tegra20_clock_init(struct device_node *np)
+static void __init tegra20_clock_init(struct device_node *np)
 {
int i;
struct device_node *node;
@@ -1334,3 +1334,4 @@ void __init tegra20_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = tegra20_cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra20, nvidia,tegra20-car, tegra20_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c6921f5..985ad69 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1953,7 +1953,7 @@ static const struct of_device_id pmc_match[] __initconst 
= {
{},
 };
 
-void __init tegra30_clock_init(struct device_node *np)
+static void __init tegra30_clock_init(struct device_node *np)
 {
struct device_node *node;
int i;
@@ -2004,3 +2004,4 @@ void __init tegra30_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = tegra30_cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra30, nvidia,tegra30-car, tegra30_clock_init);
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 923ca7e..86581ac 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -74,18 +74,6 @@ void __init tegra_init_from_table(struct 
tegra_clk_init_table *tbl,
}
 }
 
-static const struct of_device_id tegra_dt_clk_match[] = {
-   { .compatible = nvidia,tegra20-car, .data = tegra20_clock_init },
-   { .compatible = nvidia,tegra30-car, .data = tegra30_clock_init },
-   { .compatible = nvidia,tegra114-car, .data = tegra114_clock_init },
-   { }
-};
-
-void __init tegra_clocks_init(void)
-{
-   of_clk_init(tegra_dt_clk_match);
-}
-
 tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 
 void __init tegra_clocks_apply_init_table(void)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e056562..11278a8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -571,24 +571,6 @@ void tegra_init_from_table(struct tegra_clk_init_table 
*tbl,
 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
struct clk *clks[], int clk_max);
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void tegra20_clock_init(struct device_node *np);
-#else
-static inline void tegra20_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_2x_SOC */
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void tegra30_clock_init(struct device_node *np);
-#else
-static inline void tegra30_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
-void tegra114_clock_init(struct device_node *np);
-#else
-static inline void tegra114_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA114_SOC */
-
 typedef void (*tegra_clk_apply_init_table_func)(void);
 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table

[PATCH] clk: tegra: Use common of_clk_init() function

[Prashant Gaikwad]

Use common of_clk_init() function for clocks initialization.

Signed-off-by: Prashant Gaikwad 
---

Stephen, if T114 clock series is not going to make in 3.10 then I would
like Mike to take this patch. If T114 clock series makes it then I have
to rebase this patch on top of it.

---
 arch/arm/mach-tegra/common.c|4 ++--
 drivers/clk/tegra/clk-tegra20.c |3 ++-
 drivers/clk/tegra/clk-tegra30.c |3 ++-
 drivers/clk/tegra/clk.c |   11 ---
 drivers/clk/tegra/clk.h |   12 
 include/linux/clk/tegra.h   |1 -
 6 files changed, 6 insertions(+), 28 deletions(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 7cc7563..1947de8 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -23,7 +23,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #include 
 
@@ -58,7 +58,7 @@ u32 tegra_uart_config[4] = {
 #ifdef CONFIG_OF
 void __init tegra_dt_init_irq(void)
 {
-   tegra_clocks_init();
+   of_clk_init(NULL);
tegra_init_irq();
irqchip_init();
 }
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index b324d3f..e0565e6 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1270,7 +1270,7 @@ static const struct of_device_id pmc_match[] __initconst 
= {
{},
 };
 
-void __init tegra20_clock_init(struct device_node *np)
+static void __init tegra20_clock_init(struct device_node *np)
 {
int i;
struct device_node *node;
@@ -1322,3 +1322,4 @@ void __init tegra20_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = _cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 0e362ea..77dd080 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1959,7 +1959,7 @@ static const struct of_device_id pmc_match[] __initconst 
= {
{},
 };
 
-void __init tegra30_clock_init(struct device_node *np)
+static void __init tegra30_clock_init(struct device_node *np)
 {
struct device_node *node;
int i;
@@ -2010,3 +2010,4 @@ void __init tegra30_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = _cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a603b9a..ce4441a 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -72,14 +72,3 @@ void __init tegra_init_from_table(struct 
tegra_clk_init_table *tbl,
}
}
 }
-
-static const struct of_device_id tegra_dt_clk_match[] = {
-   { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
-   { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
-   { }
-};
-
-void __init tegra_clocks_init(void)
-{
-   of_clk_init(tegra_dt_clk_match);
-}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index a09d7dc..35a04d8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -498,16 +498,4 @@ void tegra_init_from_table(struct tegra_clk_init_table 
*tbl,
 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
struct clk *clks[], int clk_max);
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void tegra20_clock_init(struct device_node *np);
-#else
-static inline void tegra20_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_2x_SOC */
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void tegra30_clock_init(struct device_node *np);
-#else
-static inline void tegra30_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
-
 #endif /* TEGRA_CLK_H */
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 404d6f9..2e8b399 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -122,6 +122,5 @@ static inline void tegra_cpu_clock_resume(void)
 
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
-void tegra_clocks_init(void);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
-- 
1.7.4.1

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[PATCH] clk: tegra: Add missing cdev1 and cdev2 clocks

[Prashant Gaikwad]

Register cdev1 and cdev2 peripheral clocks.

Signed-off-by: Prashant Gaikwad 
---
 drivers/clk/tegra/clk-tegra30.c |   18 ++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 0681935..0e362ea 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1591,6 +1591,24 @@ static void __init tegra30_periph_clk_init(void)
clk_register_clkdev(clk, "afi", "tegra-pcie");
clks[afi] = clk;
 
+   /* cdev1 */
+   clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
+ 2600);
+   clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
+   clk_base, 0, 94, _u_regs,
+   periph_clk_enb_refcnt);
+   clk_register_clkdev(clk, "cdev1", NULL);
+   clks[cdev1] = clk;
+
+   /* cdev2 */
+   clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
+ 2600);
+   clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
+   clk_base, 0, 93, _u_regs,
+   periph_clk_enb_refcnt);
+   clk_register_clkdev(clk, "cdev2", NULL);
+   clks[cdev2] = clk;
+
/* kfuse */
clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
TEGRA_PERIPH_ON_APB,
-- 
1.7.4.1

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[PATCH] clk: tegra: Fix cdev1 and cdev2 IDs

[Prashant Gaikwad]

Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.

Signed-off-by: Prashant Gaikwad 
---

Stephen, tested this patch on Ventana and Cardhu, please verify if
I am not missing any platform which uses cdev1/cdev2.

---
 .../bindings/clock/nvidia,tegra20-car.txt  |4 ++--
 arch/arm/boot/dts/tegra20-colibri-512.dtsi |2 +-
 arch/arm/boot/dts/tegra20-harmony.dts  |2 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts  |2 +-
 arch/arm/boot/dts/tegra20-paz00.dts|2 +-
 arch/arm/boot/dts/tegra20-plutux.dts   |2 +-
 arch/arm/boot/dts/tegra20-seaboard.dts |2 +-
 arch/arm/boot/dts/tegra20-tec.dts  |2 +-
 arch/arm/boot/dts/tegra20-trimslice.dts|2 +-
 arch/arm/boot/dts/tegra20-ventana.dts  |2 +-
 arch/arm/boot/dts/tegra20-whistler.dts |2 +-
 arch/arm/boot/dts/tegra20.dtsi |2 +-
 drivers/clk/tegra/clk-tegra20.c|2 +-
 drivers/clk/tegra/clk-tegra30.c|2 +-
 14 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt 
b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 0921fac..e885680 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -120,8 +120,8 @@ Required properties :
   90   clk_d
   91   unassigned
   92   sus
-  93   cdev1
-  94   cdev2
+  93   cdev2
+  94   cdev1
   95   unassigned
 
   96   uart2
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi 
b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 79af149..7e96750 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -461,7 +461,7 @@
 
nvidia,ac97-controller = <>;
 
-   clocks = <_car 112>, <_car 113>, <_car 93>;
+   clocks = <_car 112>, <_car 113>, <_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
 
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts 
b/arch/arm/boot/dts/tegra20-harmony.dts
index 5fb0888..c108dc8 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -657,7 +657,7 @@
nvidia,int-mic-en-gpios = < 184 0>; /*gpio PX0 */
nvidia,ext-mic-en-gpios = < 185 0>; /* gpio PX1 */
 
-   clocks = <_car 112>, <_car 113>, <_car 93>;
+   clocks = <_car 112>, <_car 113>, <_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
 };
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts 
b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 740ba7c..ace2343 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -59,7 +59,7 @@
nvidia,spkr-en-gpios = < 2 0>;
nvidia,hp-det-gpios = < 178 0>; /* gpio PW2 */
 
-   clocks = <_car 112>, <_car 113>, <_car 93>;
+   clocks = <_car 112>, <_car 113>, <_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
 };
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts 
b/arch/arm/boot/dts/tegra20-paz00.dts
index 43fd28b..59bd476 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -502,7 +502,7 @@
nvidia,i2s-controller = <_i2s1>;
nvidia,hp-det-gpios = < 178 0>; /* gpio PW2 */
 
-   clocks = <_car 112>, <_car 113>, <_car 93>;
+   clocks = <_car 112>, <_car 113>, <_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
 };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts 
b/arch/arm/boot/dts/tegra20-plutux.dts
index 7085ae5..1a17cc3 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -53,7 +53,7 @@
nvidia,spkr-en-gpios = < 2 0>;
nvidia,hp-det-gpios = < 178 0>; /* gpio PW2 */
 
-   clocks = <_car 112>, <_car 113>, <_car 93>;
+   clocks = <_car 112>, <_car 113>, <_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts 
b/arch/arm/boot/dts/tegra20-seaboard.dts
index 4f810a5..926cc6c 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -809,7 +809,7 @@
nvidia,spkr-en-gpios = < 2 0>;

Re: [PATCH v8 10/14] ARM: tegra: Define Tegra114 CAR binding

[Prashant Gaikwad]

On Wednesday 03 April 2013 07:49 PM, Peter De Schrijver wrote:

On Mon, Mar 25, 2013 at 12:15:47PM +0100, Prashant Gaikwad wrote:

On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:

The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.

Signed-off-by: Peter De Schrijver 
---




+  263  cclk_lp
+  264  dfll_ref
+  265  dfll_soc
+

Peter,

Please remove following clock IDs from binding.


+Mux clocks
+

...

+  306  clk_out_1_mux

Is at least used by the init list. So we can't remove that?


Init list is internal to driver and does not use device tree, so we can 
keep that ID in enum but remove from DT binding so that we don't have to 
change the binding later.




Cheers,

Peter.


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Re: [PATCH v8 10/14] ARM: tegra: Define Tegra114 CAR binding

[Prashant Gaikwad]

On Wednesday 03 April 2013 07:49 PM, Peter De Schrijver wrote:

On Mon, Mar 25, 2013 at 12:15:47PM +0100, Prashant Gaikwad wrote:

On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:

The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---

snip


+  263  cclk_lp
+  264  dfll_ref
+  265  dfll_soc
+

Peter,

Please remove following clock IDs from binding.


+Mux clocks
+

...

+  306  clk_out_1_mux

Is at least used by the init list. So we can't remove that?


Init list is internal to driver and does not use device tree, so we can 
keep that ID in enum but remove from DT binding so that we don't have to 
change the binding later.




Cheers,

Peter.


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[PATCH] clk: tegra: Fix cdev1 and cdev2 IDs

[Prashant Gaikwad]

Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Stephen, tested this patch on Ventana and Cardhu, please verify if
I am not missing any platform which uses cdev1/cdev2.

---
 .../bindings/clock/nvidia,tegra20-car.txt  |4 ++--
 arch/arm/boot/dts/tegra20-colibri-512.dtsi |2 +-
 arch/arm/boot/dts/tegra20-harmony.dts  |2 +-
 arch/arm/boot/dts/tegra20-medcom-wide.dts  |2 +-
 arch/arm/boot/dts/tegra20-paz00.dts|2 +-
 arch/arm/boot/dts/tegra20-plutux.dts   |2 +-
 arch/arm/boot/dts/tegra20-seaboard.dts |2 +-
 arch/arm/boot/dts/tegra20-tec.dts  |2 +-
 arch/arm/boot/dts/tegra20-trimslice.dts|2 +-
 arch/arm/boot/dts/tegra20-ventana.dts  |2 +-
 arch/arm/boot/dts/tegra20-whistler.dts |2 +-
 arch/arm/boot/dts/tegra20.dtsi |2 +-
 drivers/clk/tegra/clk-tegra20.c|2 +-
 drivers/clk/tegra/clk-tegra30.c|2 +-
 14 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt 
b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 0921fac..e885680 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -120,8 +120,8 @@ Required properties :
   90   clk_d
   91   unassigned
   92   sus
-  93   cdev1
-  94   cdev2
+  93   cdev2
+  94   cdev1
   95   unassigned
 
   96   uart2
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi 
b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 79af149..7e96750 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -461,7 +461,7 @@
 
nvidia,ac97-controller = ac97;
 
-   clocks = tegra_car 112, tegra_car 113, tegra_car 93;
+   clocks = tegra_car 112, tegra_car 113, tegra_car 94;
clock-names = pll_a, pll_a_out0, mclk;
};
 
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts 
b/arch/arm/boot/dts/tegra20-harmony.dts
index 5fb0888..c108dc8 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -657,7 +657,7 @@
nvidia,int-mic-en-gpios = gpio 184 0; /*gpio PX0 */
nvidia,ext-mic-en-gpios = gpio 185 0; /* gpio PX1 */
 
-   clocks = tegra_car 112, tegra_car 113, tegra_car 93;
+   clocks = tegra_car 112, tegra_car 113, tegra_car 94;
clock-names = pll_a, pll_a_out0, mclk;
};
 };
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts 
b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 740ba7c..ace2343 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -59,7 +59,7 @@
nvidia,spkr-en-gpios = wm8903 2 0;
nvidia,hp-det-gpios = gpio 178 0; /* gpio PW2 */
 
-   clocks = tegra_car 112, tegra_car 113, tegra_car 93;
+   clocks = tegra_car 112, tegra_car 113, tegra_car 94;
clock-names = pll_a, pll_a_out0, mclk;
};
 };
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts 
b/arch/arm/boot/dts/tegra20-paz00.dts
index 43fd28b..59bd476 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -502,7 +502,7 @@
nvidia,i2s-controller = tegra_i2s1;
nvidia,hp-det-gpios = gpio 178 0; /* gpio PW2 */
 
-   clocks = tegra_car 112, tegra_car 113, tegra_car 93;
+   clocks = tegra_car 112, tegra_car 113, tegra_car 94;
clock-names = pll_a, pll_a_out0, mclk;
};
 };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts 
b/arch/arm/boot/dts/tegra20-plutux.dts
index 7085ae5..1a17cc3 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -53,7 +53,7 @@
nvidia,spkr-en-gpios = wm8903 2 0;
nvidia,hp-det-gpios = gpio 178 0; /* gpio PW2 */
 
-   clocks = tegra_car 112, tegra_car 113, tegra_car 93;
+   clocks = tegra_car 112, tegra_car 113, tegra_car 94;
clock-names = pll_a, pll_a_out0, mclk;
};
 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts 
b/arch/arm/boot/dts/tegra20-seaboard.dts
index 4f810a5..926cc6c 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -809,7 +809,7 @@
nvidia,spkr-en-gpios = wm8903 2 0;
nvidia,hp-det-gpios = gpio 185 0; /* gpio PX1 */
 
-   clocks = tegra_car 112, tegra_car 113, tegra_car 93;
+   clocks = tegra_car 112, tegra_car 113, tegra_car 94;
clock-names = pll_a, pll_a_out0, mclk;
};
 };
diff --git a/arch/arm/boot

[PATCH] clk: tegra: Add missing cdev1 and cdev2 clocks

[Prashant Gaikwad]

Register cdev1 and cdev2 peripheral clocks.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
 drivers/clk/tegra/clk-tegra30.c |   18 ++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 0681935..0e362ea 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1591,6 +1591,24 @@ static void __init tegra30_periph_clk_init(void)
clk_register_clkdev(clk, afi, tegra-pcie);
clks[afi] = clk;
 
+   /* cdev1 */
+   clk = clk_register_fixed_rate(NULL, cdev1_fixed, NULL, CLK_IS_ROOT,
+ 2600);
+   clk = tegra_clk_register_periph_gate(cdev1, cdev1_fixed, 0,
+   clk_base, 0, 94, periph_u_regs,
+   periph_clk_enb_refcnt);
+   clk_register_clkdev(clk, cdev1, NULL);
+   clks[cdev1] = clk;
+
+   /* cdev2 */
+   clk = clk_register_fixed_rate(NULL, cdev2_fixed, NULL, CLK_IS_ROOT,
+ 2600);
+   clk = tegra_clk_register_periph_gate(cdev2, cdev2_fixed, 0,
+   clk_base, 0, 93, periph_u_regs,
+   periph_clk_enb_refcnt);
+   clk_register_clkdev(clk, cdev2, NULL);
+   clks[cdev2] = clk;
+
/* kfuse */
clk = tegra_clk_register_periph_gate(kfuse, clk_m,
TEGRA_PERIPH_ON_APB,
-- 
1.7.4.1

--
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[PATCH] clk: tegra: Use common of_clk_init() function

[Prashant Gaikwad]

Use common of_clk_init() function for clocks initialization.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Stephen, if T114 clock series is not going to make in 3.10 then I would
like Mike to take this patch. If T114 clock series makes it then I have
to rebase this patch on top of it.

---
 arch/arm/mach-tegra/common.c|4 ++--
 drivers/clk/tegra/clk-tegra20.c |3 ++-
 drivers/clk/tegra/clk-tegra30.c |3 ++-
 drivers/clk/tegra/clk.c |   11 ---
 drivers/clk/tegra/clk.h |   12 
 include/linux/clk/tegra.h   |1 -
 6 files changed, 6 insertions(+), 28 deletions(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 7cc7563..1947de8 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -23,7 +23,7 @@
 #include linux/clk.h
 #include linux/delay.h
 #include linux/irqchip.h
-#include linux/clk/tegra.h
+#include linux/clk-provider.h
 
 #include asm/hardware/cache-l2x0.h
 
@@ -58,7 +58,7 @@ u32 tegra_uart_config[4] = {
 #ifdef CONFIG_OF
 void __init tegra_dt_init_irq(void)
 {
-   tegra_clocks_init();
+   of_clk_init(NULL);
tegra_init_irq();
irqchip_init();
 }
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index b324d3f..e0565e6 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1270,7 +1270,7 @@ static const struct of_device_id pmc_match[] __initconst 
= {
{},
 };
 
-void __init tegra20_clock_init(struct device_node *np)
+static void __init tegra20_clock_init(struct device_node *np)
 {
int i;
struct device_node *node;
@@ -1322,3 +1322,4 @@ void __init tegra20_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = tegra20_cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra20, nvidia,tegra20-car, tegra20_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 0e362ea..77dd080 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1959,7 +1959,7 @@ static const struct of_device_id pmc_match[] __initconst 
= {
{},
 };
 
-void __init tegra30_clock_init(struct device_node *np)
+static void __init tegra30_clock_init(struct device_node *np)
 {
struct device_node *node;
int i;
@@ -2010,3 +2010,4 @@ void __init tegra30_clock_init(struct device_node *np)
 
tegra_cpu_car_ops = tegra30_cpu_car_ops;
 }
+CLK_OF_DECLARE(tegra30, nvidia,tegra30-car, tegra30_clock_init);
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a603b9a..ce4441a 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -72,14 +72,3 @@ void __init tegra_init_from_table(struct 
tegra_clk_init_table *tbl,
}
}
 }
-
-static const struct of_device_id tegra_dt_clk_match[] = {
-   { .compatible = nvidia,tegra20-car, .data = tegra20_clock_init },
-   { .compatible = nvidia,tegra30-car, .data = tegra30_clock_init },
-   { }
-};
-
-void __init tegra_clocks_init(void)
-{
-   of_clk_init(tegra_dt_clk_match);
-}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index a09d7dc..35a04d8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -498,16 +498,4 @@ void tegra_init_from_table(struct tegra_clk_init_table 
*tbl,
 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
struct clk *clks[], int clk_max);
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void tegra20_clock_init(struct device_node *np);
-#else
-static inline void tegra20_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_2x_SOC */
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void tegra30_clock_init(struct device_node *np);
-#else
-static inline void tegra30_clock_init(struct device_node *np) {}
-#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
-
 #endif /* TEGRA_CLK_H */
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 404d6f9..2e8b399 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -122,6 +122,5 @@ static inline void tegra_cpu_clock_resume(void)
 
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
-void tegra_clocks_init(void);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
-- 
1.7.4.1

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Re: [PATCH V3] clk: Add composite clock type

[Prashant Gaikwad]

Mike,

Please merge this patch.

Thanks & Regards,
PrashantG

On Wednesday 20 March 2013 05:30 PM, Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad 
---

Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.

---
  drivers/clk/Makefile |1 +
  drivers/clk/clk-composite.c  |  201 ++
  include/linux/clk-provider.h |   31 +++
  3 files changed, 233 insertions(+), 0 deletions(-)
  create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0147022..097ed01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
  obj-$(CONFIG_COMMON_CLK)  += clk-fixed-rate.o
  obj-$(CONFIG_COMMON_CLK)  += clk-gate.o
  obj-$(CONFIG_COMMON_CLK)  += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
  
  # SoCs specific

  obj-$(CONFIG_ARCH_BCM2835)+= clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..097dee4
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite->gate_ops;
+   struct clk_hw *gate_hw = composite->gate_hw;
+
+   gate_hw->clk = hw->clk;
+
+   return gate_ops->is_enabled(gat

Re: [PATCH v8 10/14] ARM: tegra: Define Tegra114 CAR binding

[Prashant Gaikwad]

On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:

The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.

Signed-off-by: Peter De Schrijver 
---





+  263  cclk_lp
+  264  dfll_ref
+  265  dfll_soc
+


Peter,

Please remove following clock IDs from binding.


+Mux clocks
+
+  300  audio0_mux
+  301  audio1_mux
+  302  audio2_mux
+  303  audio3_mux
+  304  audio4_mux
+  305  spdif_mux
+  306  clk_out_1_mux
+  307  clk_out_2_mux
+  308  clk_out_3_mux
+  309  dsia_mux
+  310  dsib_mux
+
+Example SoC include file:
+
+/ {
+   tegra_car: clock {
+   compatible = "nvidia,tegra114-car";
+   reg = <0x60006000 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   usb@c5004000 {
+   clocks = <_car 58>; /* usb2 */
+   };
+};
+
+Example board file:
+
+/ {
+   clocks {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   osc: clock@0 {
+   compatible = "fixed-clock";
+   reg = <0>;
+   #clock-cells = <0>;
+   clock-frequency = <1200>;
+   };
+
+   clk_32k: clock@1 {
+   compatible = "fixed-clock";
+   reg = <1>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+   };
+
+   _car {
+   clocks = <_32k> <>;
+   };
+};


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Re: [PATCH] clk: tegra: Don't enable PLLs during early boot

[Prashant Gaikwad]

On Monday 25 March 2013 03:45 PM, Peter De Schrijver wrote:

On Fri, Mar 22, 2013 at 04:48:11PM +0100, Stephen Warren wrote:

On 03/22/2013 05:54 AM, Peter De Schrijver wrote:

The PLL code relies on udelay() which is not available when CCF is
initialized. Hence we can't enable any PLL during this phase.

Signed-off-by: Peter De Schrijver 

--

Stephen,

Can you confirm this is ok for the audio drivers?

We used to be lucky that this has worked up to now, but I will introduce some
changes to the pll lock check code which cause this to fail due to the
slight differences in timing.

No, this won't work for the audio drivers; they assume the clock is
enabled when they start.

This assumption was made long ago. I know drivers are supposed to assume
that clocks are disabled when they're probed, but historically that
wasn't always the case, so if the audio drivers assumed that, and then
did clk_enable() as the first thing, they got a warning due to the
enabling an already enabled clock and/or later attempts to disable the

That should be ok. You can enable a clock more than once.


clocks wouldn't actually disable them. Perhaps this has changed now, but
either way, audio driver changes would be needed to support this change.


But indeed, the clock won't be disabled then when the driver does
clk_disable(). The reference count will just be decremented. That's however
not a functional problem, just not optimal from a power consumption point of
view. So we could change the drivers first and keep the clocks disabled at
boottime in a second phase.


Perhaps this is due to initializing the Tegra clock driver in the
machine descriptor's init_irq function, rather than in the init_machine
function? Can this be moved?

Maybe. But we need the clockframework before the timers are initialized...
So I have to check the dependencies.


I have moved the initialization after slab allocator is initialized and 
before timer initialization.
This is later that it used to happen with our legacy framework or which 
happens in our downstream kernel.


Isn't this problem observed in downstream kernel?

May be we can split the clock initialization and move clock init from 
table to some later stage.



Cheers,

Peter.


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Re: [PATCH] clk: tegra: Don't enable PLLs during early boot

[Prashant Gaikwad]

On Monday 25 March 2013 03:45 PM, Peter De Schrijver wrote:

On Fri, Mar 22, 2013 at 04:48:11PM +0100, Stephen Warren wrote:

On 03/22/2013 05:54 AM, Peter De Schrijver wrote:

The PLL code relies on udelay() which is not available when CCF is
initialized. Hence we can't enable any PLL during this phase.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com

--

Stephen,

Can you confirm this is ok for the audio drivers?

We used to be lucky that this has worked up to now, but I will introduce some
changes to the pll lock check code which cause this to fail due to the
slight differences in timing.

No, this won't work for the audio drivers; they assume the clock is
enabled when they start.

This assumption was made long ago. I know drivers are supposed to assume
that clocks are disabled when they're probed, but historically that
wasn't always the case, so if the audio drivers assumed that, and then
did clk_enable() as the first thing, they got a warning due to the
enabling an already enabled clock and/or later attempts to disable the

That should be ok. You can enable a clock more than once.


clocks wouldn't actually disable them. Perhaps this has changed now, but
either way, audio driver changes would be needed to support this change.


But indeed, the clock won't be disabled then when the driver does
clk_disable(). The reference count will just be decremented. That's however
not a functional problem, just not optimal from a power consumption point of
view. So we could change the drivers first and keep the clocks disabled at
boottime in a second phase.


Perhaps this is due to initializing the Tegra clock driver in the
machine descriptor's init_irq function, rather than in the init_machine
function? Can this be moved?

Maybe. But we need the clockframework before the timers are initialized...
So I have to check the dependencies.


I have moved the initialization after slab allocator is initialized and 
before timer initialization.
This is later that it used to happen with our legacy framework or which 
happens in our downstream kernel.


Isn't this problem observed in downstream kernel?

May be we can split the clock initialization and move clock init from 
table to some later stage.



Cheers,

Peter.


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Re: [PATCH v8 10/14] ARM: tegra: Define Tegra114 CAR binding

[Prashant Gaikwad]

On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:

The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---


snip


+  263  cclk_lp
+  264  dfll_ref
+  265  dfll_soc
+


Peter,

Please remove following clock IDs from binding.


+Mux clocks
+
+  300  audio0_mux
+  301  audio1_mux
+  302  audio2_mux
+  303  audio3_mux
+  304  audio4_mux
+  305  spdif_mux
+  306  clk_out_1_mux
+  307  clk_out_2_mux
+  308  clk_out_3_mux
+  309  dsia_mux
+  310  dsib_mux
+
+Example SoC include file:
+
+/ {
+   tegra_car: clock {
+   compatible = nvidia,tegra114-car;
+   reg = 0x60006000 0x1000;
+   #clock-cells = 1;
+   };
+
+   usb@c5004000 {
+   clocks = tegra_car 58; /* usb2 */
+   };
+};
+
+Example board file:
+
+/ {
+   clocks {
+   compatible = simple-bus;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   osc: clock@0 {
+   compatible = fixed-clock;
+   reg = 0;
+   #clock-cells = 0;
+   clock-frequency = 1200;
+   };
+
+   clk_32k: clock@1 {
+   compatible = fixed-clock;
+   reg = 1;
+   #clock-cells = 0;
+   clock-frequency = 32768;
+   };
+   };
+
+   tegra_car {
+   clocks = clk_32k osc;
+   };
+};


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Re: [PATCH V3] clk: Add composite clock type

[Prashant Gaikwad]

Mike,

Please merge this patch.

Thanks  Regards,
PrashantG

On Wednesday 20 March 2013 05:30 PM, Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux - Div - Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.

---
  drivers/clk/Makefile |1 +
  drivers/clk/clk-composite.c  |  201 ++
  include/linux/clk-provider.h |   31 +++
  3 files changed, 233 insertions(+), 0 deletions(-)
  create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0147022..097ed01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
  obj-$(CONFIG_COMMON_CLK)  += clk-fixed-rate.o
  obj-$(CONFIG_COMMON_CLK)  += clk-gate.o
  obj-$(CONFIG_COMMON_CLK)  += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
  
  # SoCs specific

  obj-$(CONFIG_ARCH_BCM2835)+= clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..097dee4
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/err.h
+#include linux/slab.h
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite-gate_ops;
+   struct clk_hw *gate_hw = composite-gate_hw;
+
+   gate_hw-clk = hw-clk;
+
+   return gate_ops-is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw

[PATCH V3] clk: Add composite clock type

[Prashant Gaikwad]

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad 
---

Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.

---
 drivers/clk/Makefile |1 +
 drivers/clk/clk-composite.c  |  201 ++
 include/linux/clk-provider.h |   31 +++
 3 files changed, 233 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0147022..097ed01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
 obj-$(CONFIG_COMMON_CLK)   += clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
 
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..097dee4
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite->gate_ops;
+   struct clk_hw *gate_hw = composite->gate_hw;
+
+   gate_hw->clk = hw->clk;
+
+   return gate_ops->is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+ 

[PATCH V3] clk: Add composite clock type

[Prashant Gaikwad]

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux - Div - Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.

---
 drivers/clk/Makefile |1 +
 drivers/clk/clk-composite.c  |  201 ++
 include/linux/clk-provider.h |   31 +++
 3 files changed, 233 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0147022..097ed01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
 obj-$(CONFIG_COMMON_CLK)   += clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
 
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..097dee4
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/err.h
+#include linux/slab.h
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite-gate_ops;
+   struct clk_hw *gate_hw = composite-gate_hw;
+
+   gate_hw-clk = hw-clk;
+
+   return gate_ops-is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite-gate_ops

Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Wednesday 13 March 2013 10:00 PM, Tomasz Figa wrote:

Hi Prashant,

On Thursday 28 of February 2013 11:20:31 Stephen Warren wrote:

On 02/28/2013 12:58 AM, Prashant Gaikwad wrote:

On Wednesday 06 February 2013 03:36 PM, Tomasz Figa wrote:

On Wednesday 06 of February 2013 08:34:32 Prashant Gaikwad wrote:

On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:

Hi Prashant,

Thank you for your patch. Please see some comments inline.

On Monday 04 of February 2013 13:41:22 Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

diff --git a/drivers/clk/clk-composite.c

+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite->mux_ops;
+ struct clk_hw *mux_hw = composite->mux_hw;
+
+ mux_hw->clk = hw->clk;

Why is this needed? Looks like this filed is already being initialized
in clk_register_composite.

Some ops will get called during clk_init where this clk is not populated
hence doing here. I have done it for all ops to make sure that any
future change in clock framework don't break this clock.
Now, why duplicate it in clk_register_composite? It is possible that
none of these ops get called in clk_init.
For example, recalc_rate is called during init and this ops is supported
by div clock type, but what if div clock is not added.

I hope this explains the need.

Sorry, I don't understand your explanation.

I have asked why mux_hw->clk field has to be reinitialized in all the
ops.

In other words, is it even possible that this clk pointer changes since
calling clk_register from clk_register_composite and if yes, why?

Tomasz,

calling sequence is as

clk_register(struct clk_hw *hw)

 clk_init(struct clk_hw *hw)
 
 .

 .
 hw->clk = clk;
 clk->ops.recalc_rate(hw) => clk_composite_recalc_rate(hw) =>

composite->div_ops.recalc_rate(div_hw) => clk_divider_recalc_rate(hw)

Now if clk_divider_recalc_rate tries to access clk from hw then it will
get NULL since this is not assigned yet and that is what I am doing in
clk_composite_recalc_rate.

I am doing it in all ops because I can not assume which one will get
called first and always. If in future something changes the calling
sequence in ccf framework then it will break this clock.

Surely the CCF core should be taking care of this as part of
clk_register() or clk_init()?

Any news on this? It would be nice if this patch could be merged soon, because
we'd like to rework Exynos clock code to use composite clocks before merge
window, to have that merged for 3.10.

If you don't have time to work on this, would you mind if I made any necessary
fixes, added my sign-off next to yours and posted next version myself?


Tomasz,

Sorry for delayed reply. I will send the updated patch in next 2-3 days. 
After that if any rework required you can make the changes and add your 
sign-off.


Thanks for the patience!!

Regards,
PrashantG


Best regards,


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Wednesday 13 March 2013 10:00 PM, Tomasz Figa wrote:

Hi Prashant,

On Thursday 28 of February 2013 11:20:31 Stephen Warren wrote:

On 02/28/2013 12:58 AM, Prashant Gaikwad wrote:

On Wednesday 06 February 2013 03:36 PM, Tomasz Figa wrote:

On Wednesday 06 of February 2013 08:34:32 Prashant Gaikwad wrote:

On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:

Hi Prashant,

Thank you for your patch. Please see some comments inline.

On Monday 04 of February 2013 13:41:22 Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux - Div - Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

diff --git a/drivers/clk/clk-composite.c

+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite-mux_ops;
+ struct clk_hw *mux_hw = composite-mux_hw;
+
+ mux_hw-clk = hw-clk;

Why is this needed? Looks like this filed is already being initialized
in clk_register_composite.

Some ops will get called during clk_init where this clk is not populated
hence doing here. I have done it for all ops to make sure that any
future change in clock framework don't break this clock.
Now, why duplicate it in clk_register_composite? It is possible that
none of these ops get called in clk_init.
For example, recalc_rate is called during init and this ops is supported
by div clock type, but what if div clock is not added.

I hope this explains the need.

Sorry, I don't understand your explanation.

I have asked why mux_hw-clk field has to be reinitialized in all the
ops.

In other words, is it even possible that this clk pointer changes since
calling clk_register from clk_register_composite and if yes, why?

Tomasz,

calling sequence is as

clk_register(struct clk_hw *hw)

 clk_init(struct clk_hw *hw)
 
 .

 .
 hw-clk = clk;
 clk-ops.recalc_rate(hw) = clk_composite_recalc_rate(hw) =

composite-div_ops.recalc_rate(div_hw) = clk_divider_recalc_rate(hw)

Now if clk_divider_recalc_rate tries to access clk from hw then it will
get NULL since this is not assigned yet and that is what I am doing in
clk_composite_recalc_rate.

I am doing it in all ops because I can not assume which one will get
called first and always. If in future something changes the calling
sequence in ccf framework then it will break this clock.

Surely the CCF core should be taking care of this as part of
clk_register() or clk_init()?

Any news on this? It would be nice if this patch could be merged soon, because
we'd like to rework Exynos clock code to use composite clocks before merge
window, to have that merged for 3.10.

If you don't have time to work on this, would you mind if I made any necessary
fixes, added my sign-off next to yours and posted next version myself?


Tomasz,

Sorry for delayed reply. I will send the updated patch in next 2-3 days. 
After that if any rework required you can make the changes and add your 
sign-off.


Thanks for the patience!!

Regards,
PrashantG


Best regards,


--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Wednesday 06 February 2013 03:36 PM, Tomasz Figa wrote:

On Wednesday 06 of February 2013 08:34:32 Prashant Gaikwad wrote:

On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:

Hi Prashant,

Thank you for your patch. Please see some comments inline.

On Monday 04 of February 2013 13:41:22 Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad 
---

Changes from V1:
- 2nd patch dropped as the concept is acked by Mike.
- Fixed comments from Stephen.

---

   drivers/clk/Makefile |1 +
   drivers/clk/clk-composite.c  |  208

++
include/linux/clk-provider.h

|   30 ++

   3 files changed, 239 insertions(+), 0 deletions(-)
   create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ce77077..2287848 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)  += clk-fixed-factor.o

   obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
   obj-$(CONFIG_COMMON_CLK) += clk-gate.o
   obj-$(CONFIG_COMMON_CLK) += clk-mux.o

+obj-$(CONFIG_COMMON_CLK) += clk-composite.o

   # SoCs specific
   obj-$(CONFIG_ARCH_BCM2835)   += clk-bcm2835.o

diff --git a/drivers/clk/clk-composite.c
b/drivers/clk/clk-composite.c
new file mode 100644
index 000..5a6587f
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
modify it + * under the terms and conditions of the GNU General
Public License, + * version 2, as published by the Free Software
Foundation. + *
+ * This program is distributed in the hope it will be useful, but
WITHOUT + * ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
General Public License for + * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see
<http://www.gnu.org/licenses/>. + */
+
+#include 
+#include 
+#include 
+#include 
+
+#define to_clk_composite(_hw) container_of(_hw, struct
clk_composite,
hw) +
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite->mux_ops;
+ struct clk_hw *mux_hw = composite->mux_hw;
+
+ mux_hw->clk = hw->clk;

Why is this needed? Looks like this filed is already being initialized
in clk_register_composite.

Some ops will get called during clk_init where this clk is not populated
hence doing here. I have done it for all ops to make sure that any
future change in clock framework don't break this clock.
Now, why duplicate it in clk_register_composite? It is possible that
none of these ops get called in clk_init.
For example, recalc_rate is called during init and this ops is supported
by div clock type, but what if div clock is not added.

I hope this explains the need.


Sorry, I don't understand your explanation.

I have asked why mux_hw->clk field has to be reinitialized in all the ops.

In other words, is it even possible that this clk pointer changes since
calling clk_register from clk_register_composite and if yes, why?


Tomasz,

calling sequence is as

clk_register(struct clk_hw *hw)
clk_init(struct clk_hw *hw)
.
.
hw->clk = clk;
clk->ops.recalc_rate(hw) => clk_composite_recalc_rate(hw) => 
composite->div_ops.recalc_rate(div_hw) => clk_divider_recalc_rate(hw)


Now if clk_divider_recalc_rate tries to access clk from hw then it will 
get NULL since this is not assigned yet and that is what I am doing in 
clk_composite_recalc_rate.


I am doing it in all ops because I can not assume which one will get 
called first and always. If in future something changes the calling 
sequence in ccf framework then it will break this clock.



Best regards,
--
Tomasz Figa
Samsung Poland R Center
SW Solution Development, Linux Platform


+
+ return mux_ops->get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk

Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Wednesday 06 February 2013 03:36 PM, Tomasz Figa wrote:

On Wednesday 06 of February 2013 08:34:32 Prashant Gaikwad wrote:

On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:

Hi Prashant,

Thank you for your patch. Please see some comments inline.

On Monday 04 of February 2013 13:41:22 Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux - Div - Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Changes from V1:
- 2nd patch dropped as the concept is acked by Mike.
- Fixed comments from Stephen.

---

   drivers/clk/Makefile |1 +
   drivers/clk/clk-composite.c  |  208

++
include/linux/clk-provider.h

|   30 ++

   3 files changed, 239 insertions(+), 0 deletions(-)
   create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ce77077..2287848 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)  += clk-fixed-factor.o

   obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
   obj-$(CONFIG_COMMON_CLK) += clk-gate.o
   obj-$(CONFIG_COMMON_CLK) += clk-mux.o

+obj-$(CONFIG_COMMON_CLK) += clk-composite.o

   # SoCs specific
   obj-$(CONFIG_ARCH_BCM2835)   += clk-bcm2835.o

diff --git a/drivers/clk/clk-composite.c
b/drivers/clk/clk-composite.c
new file mode 100644
index 000..5a6587f
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
modify it + * under the terms and conditions of the GNU General
Public License, + * version 2, as published by the Free Software
Foundation. + *
+ * This program is distributed in the hope it will be useful, but
WITHOUT + * ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
General Public License for + * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see
http://www.gnu.org/licenses/. + */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/err.h
+#include linux/slab.h
+
+#define to_clk_composite(_hw) container_of(_hw, struct
clk_composite,
hw) +
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite-mux_ops;
+ struct clk_hw *mux_hw = composite-mux_hw;
+
+ mux_hw-clk = hw-clk;

Why is this needed? Looks like this filed is already being initialized
in clk_register_composite.

Some ops will get called during clk_init where this clk is not populated
hence doing here. I have done it for all ops to make sure that any
future change in clock framework don't break this clock.
Now, why duplicate it in clk_register_composite? It is possible that
none of these ops get called in clk_init.
For example, recalc_rate is called during init and this ops is supported
by div clock type, but what if div clock is not added.

I hope this explains the need.


Sorry, I don't understand your explanation.

I have asked why mux_hw-clk field has to be reinitialized in all the ops.

In other words, is it even possible that this clk pointer changes since
calling clk_register from clk_register_composite and if yes, why?


Tomasz,

calling sequence is as

clk_register(struct clk_hw *hw)
clk_init(struct clk_hw *hw)
.
.
hw-clk = clk;
clk-ops.recalc_rate(hw) = clk_composite_recalc_rate(hw) = 
composite-div_ops.recalc_rate(div_hw) = clk_divider_recalc_rate(hw)


Now if clk_divider_recalc_rate tries to access clk from hw then it will 
get NULL since this is not assigned yet and that is what I am doing in 
clk_composite_recalc_rate.


I am doing it in all ops because I can not assume which one will get 
called first and always. If in future something changes the calling 
sequence in ccf framework then it will break this clock.



Best regards,
--
Tomasz Figa
Samsung Poland RD Center
SW Solution Development, Linux Platform


+
+ return mux_ops-get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const

Re: [PATCH v7 00/12] Tegra114 clockframework

[Prashant Gaikwad]

On Wednesday 20 February 2013 12:09 AM, Stephen Warren wrote:

On 02/15/2013 05:36 AM, Peter De Schrijver wrote:

This is the seventh version of the Tegra114 clockframework. It is based on the
for-next branch of
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git and
http://www.spinics.net/lists/arm-kernel/msg220452.html.

Mike,

I think it'd be prudent to take this series through the Tegra tree again
for 3.10; patch 11 needs to go in as part of the series due to internal
dependencies, and I'm slightly worried that other Tegra DT changes might
conflict with that patch (if only for context). Taking this series (and
any other Tegra clk driver changes for 3.10) through the Tegra tree
could resolve that easily. Do you have a problem with that?

If that's OK, can you stage the dependency Peter mentioned:
http://www.spinics.net/lists/arm-kernel/msg220452.html
into a stable branch for me to merge, obviously after 3.9-rc1 is out.

Thanks.

Prashant, could you provide a review/ack for this series too.


For the series

Reviewed-by: Prashant Gaikwad 


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Re: [PATCH v7 00/12] Tegra114 clockframework

[Prashant Gaikwad]

On Wednesday 20 February 2013 12:09 AM, Stephen Warren wrote:

On 02/15/2013 05:36 AM, Peter De Schrijver wrote:

This is the seventh version of the Tegra114 clockframework. It is based on the
for-next branch of
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git and
http://www.spinics.net/lists/arm-kernel/msg220452.html.

Mike,

I think it'd be prudent to take this series through the Tegra tree again
for 3.10; patch 11 needs to go in as part of the series due to internal
dependencies, and I'm slightly worried that other Tegra DT changes might
conflict with that patch (if only for context). Taking this series (and
any other Tegra clk driver changes for 3.10) through the Tegra tree
could resolve that easily. Do you have a problem with that?

If that's OK, can you stage the dependency Peter mentioned:
http://www.spinics.net/lists/arm-kernel/msg220452.html
into a stable branch for me to merge, obviously after 3.9-rc1 is out.

Thanks.

Prashant, could you provide a review/ack for this series too.


For the series

Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


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Re: [PATCH] clk: tegra: Add missing spinlock for hclk and pclk

[Prashant Gaikwad]

On Thursday 07 February 2013 10:07 PM, Peter De Schrijver wrote:

The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.

Signed-off-by: Peter De Schrijver 


Reviewed-by: Prashant Gaikwad 


---
  drivers/clk/tegra/clk-tegra20.c |   11 +++
  drivers/clk/tegra/clk-tegra30.c |   11 +++
  2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 5d41569..4612b2e 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -194,6 +194,7 @@ static void __iomem *clk_base;
  static void __iomem *pmc_base;
  
  static DEFINE_SPINLOCK(pll_div_lock);

+static DEFINE_SPINLOCK(sysrate_lock);
  
  #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset,	\

_clk_num, _regs, _gate_flags, _clk_id)  \
@@ -768,19 +769,21 @@ static void tegra20_super_clk_init(void)
  
  	/* HCLK */

clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
-  clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL);
+  clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
+  _lock);
clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
clk_base + CLK_SYSTEM_RATE, 7,
-   CLK_GATE_SET_TO_DISABLE, NULL);
+   CLK_GATE_SET_TO_DISABLE, _lock);
clk_register_clkdev(clk, "hclk", NULL);
clks[hclk] = clk;
  
  	/* PCLK */

clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
-  clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL);
+  clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
+  _lock);
clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
clk_base + CLK_SYSTEM_RATE, 3,
-   CLK_GATE_SET_TO_DISABLE, NULL);
+   CLK_GATE_SET_TO_DISABLE, _lock);
clk_register_clkdev(clk, "pclk", NULL);
clks[pclk] = clk;
  
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c

index d169ef0..c5415ce 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -275,6 +275,7 @@ static DEFINE_SPINLOCK(clk_out_lock);
  static DEFINE_SPINLOCK(pll_div_lock);
  static DEFINE_SPINLOCK(cml_lock);
  static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(sysrate_lock);
  
  #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset,	\

_clk_num, _regs, _gate_flags, _clk_id)  \
@@ -1348,19 +1349,21 @@ static void __init tegra30_super_clk_init(void)
  
  	/* HCLK */

clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
-  clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL);
+  clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
+  _lock);
clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
clk_base + SYSTEM_CLK_RATE, 7,
-   CLK_GATE_SET_TO_DISABLE, NULL);
+   CLK_GATE_SET_TO_DISABLE, _lock);
clk_register_clkdev(clk, "hclk", NULL);
clks[hclk] = clk;
  
  	/* PCLK */

clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
-  clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL);
+  clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
+  _lock);
clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
clk_base + SYSTEM_CLK_RATE, 3,
-   CLK_GATE_SET_TO_DISABLE, NULL);
+   CLK_GATE_SET_TO_DISABLE, _lock);
clk_register_clkdev(clk, "pclk", NULL);
clks[pclk] = clk;
  


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Re: [PATCH] clk: tegra: local arrays should be static

[Prashant Gaikwad]

On Thursday 07 February 2013 10:00 PM, Peter De Schrijver wrote:

cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within
clk-tegra30.c. Declare them static to avoid namespace polution.

Signed-off-by: Peter De Schrijver 


Reviewed-by: Prashant Gaikwad 


---
  drivers/clk/tegra/clk-tegra30.c |   20 ++--
  1 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index a163812..d169ef0 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1249,16 +1249,16 @@ static void __init tegra30_pmc_clk_init(void)
  
  }
  
-const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",

-"pll_p_cclkg", "pll_p_out4_cclkg",
-"pll_p_out3_cclkg", "unused", "pll_x" };
-const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
- "pll_p_cclklp", "pll_p_out4_cclklp",
- "pll_p_out3_cclklp", "unused", "pll_x",
- "pll_x_out0" };
-const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
-  "pll_p_out3", "pll_p_out2", "unused",
-  "clk_32k", "pll_m_out1" };
+static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
+   "pll_p_cclkg", "pll_p_out4_cclkg",
+   "pll_p_out3_cclkg", "unused", "pll_x" };
+static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
+"pll_p_cclklp", "pll_p_out4_cclklp",
+"pll_p_out3_cclklp", "unused", "pll_x",
+"pll_x_out0" };
+static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
+ "pll_p_out3", "pll_p_out2", "unused",
+ "clk_32k", "pll_m_out1" };
  
  static void __init tegra30_super_clk_init(void)

  {


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Re: [PATCH] clk: tegra: Implement locking for super clock

[Prashant Gaikwad]

On Thursday 07 February 2013 09:54 PM, Peter De Schrijver wrote:

Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.

Signed-off-by: Peter De Schrijver 


Reviewed-by: Prashant Gaikwad 


---
  drivers/clk/tegra/clk-super.c |   18 +++---
  1 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 7ad48a8..2fd924d 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
  {
struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
u32 val, state;
+   int err = 0;
u8 parent_index, shift;
+   unsigned long flags = 0;
+
+   if (mux->lock)
+   spin_lock_irqsave(mux->lock, flags);
  
  	val = readl_relaxed(mux->reg);

state = val & SUPER_STATE_MASK;
@@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
   (index == mux->pllx_index))) {
parent_index = clk_super_get_parent(hw);
if ((parent_index == mux->div2_index) ||
-   (parent_index == mux->pllx_index))
-   return -EINVAL;
+   (parent_index == mux->pllx_index)) {
+   err = -EINVAL;
+   goto out;
+   }
  
  		val ^= SUPER_LP_DIV2_BYPASS;

writel_relaxed(val, mux->reg);
@@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 
index)
  
  	writel_relaxed(val, mux->reg);

udelay(2);
-   return 0;
+
+out:
+   if (mux->lock)
+   spin_unlock_irqrestore(mux->lock, flags);
+
+   return err;
  }
  
  const struct clk_ops tegra_clk_super_ops = {


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Re: [PATCH] clk: tegra: Implement locking for super clock

[Prashant Gaikwad]

On Thursday 07 February 2013 09:54 PM, Peter De Schrijver wrote:

Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com


Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


---
  drivers/clk/tegra/clk-super.c |   18 +++---
  1 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 7ad48a8..2fd924d 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
  {
struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
u32 val, state;
+   int err = 0;
u8 parent_index, shift;
+   unsigned long flags = 0;
+
+   if (mux-lock)
+   spin_lock_irqsave(mux-lock, flags);
  
  	val = readl_relaxed(mux-reg);

state = val  SUPER_STATE_MASK;
@@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
   (index == mux-pllx_index))) {
parent_index = clk_super_get_parent(hw);
if ((parent_index == mux-div2_index) ||
-   (parent_index == mux-pllx_index))
-   return -EINVAL;
+   (parent_index == mux-pllx_index)) {
+   err = -EINVAL;
+   goto out;
+   }
  
  		val ^= SUPER_LP_DIV2_BYPASS;

writel_relaxed(val, mux-reg);
@@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 
index)
  
  	writel_relaxed(val, mux-reg);

udelay(2);
-   return 0;
+
+out:
+   if (mux-lock)
+   spin_unlock_irqrestore(mux-lock, flags);
+
+   return err;
  }
  
  const struct clk_ops tegra_clk_super_ops = {


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Re: [PATCH] clk: tegra: local arrays should be static

[Prashant Gaikwad]

On Thursday 07 February 2013 10:00 PM, Peter De Schrijver wrote:

cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within
clk-tegra30.c. Declare them static to avoid namespace polution.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com


Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


---
  drivers/clk/tegra/clk-tegra30.c |   20 ++--
  1 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index a163812..d169ef0 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1249,16 +1249,16 @@ static void __init tegra30_pmc_clk_init(void)
  
  }
  
-const char *cclk_g_parents[] = { clk_m, pll_c, clk_32k, pll_m,

-pll_p_cclkg, pll_p_out4_cclkg,
-pll_p_out3_cclkg, unused, pll_x };
-const char *cclk_lp_parents[] = { clk_m, pll_c, clk_32k, pll_m,
- pll_p_cclklp, pll_p_out4_cclklp,
- pll_p_out3_cclklp, unused, pll_x,
- pll_x_out0 };
-const char *sclk_parents[] = { clk_m, pll_c_out1, pll_p_out4,
-  pll_p_out3, pll_p_out2, unused,
-  clk_32k, pll_m_out1 };
+static const char *cclk_g_parents[] = { clk_m, pll_c, clk_32k, pll_m,
+   pll_p_cclkg, pll_p_out4_cclkg,
+   pll_p_out3_cclkg, unused, pll_x };
+static const char *cclk_lp_parents[] = { clk_m, pll_c, clk_32k, pll_m,
+pll_p_cclklp, pll_p_out4_cclklp,
+pll_p_out3_cclklp, unused, pll_x,
+pll_x_out0 };
+static const char *sclk_parents[] = { clk_m, pll_c_out1, pll_p_out4,
+ pll_p_out3, pll_p_out2, unused,
+ clk_32k, pll_m_out1 };
  
  static void __init tegra30_super_clk_init(void)

  {


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Re: [PATCH] clk: tegra: Add missing spinlock for hclk and pclk

[Prashant Gaikwad]

On Thursday 07 February 2013 10:07 PM, Peter De Schrijver wrote:

The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com


Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


---
  drivers/clk/tegra/clk-tegra20.c |   11 +++
  drivers/clk/tegra/clk-tegra30.c |   11 +++
  2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 5d41569..4612b2e 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -194,6 +194,7 @@ static void __iomem *clk_base;
  static void __iomem *pmc_base;
  
  static DEFINE_SPINLOCK(pll_div_lock);

+static DEFINE_SPINLOCK(sysrate_lock);
  
  #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset,	\

_clk_num, _regs, _gate_flags, _clk_id)  \
@@ -768,19 +769,21 @@ static void tegra20_super_clk_init(void)
  
  	/* HCLK */

clk = clk_register_divider(NULL, hclk_div, sclk, 0,
-  clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL);
+  clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
+  sysrate_lock);
clk = clk_register_gate(NULL, hclk, hclk_div, CLK_SET_RATE_PARENT,
clk_base + CLK_SYSTEM_RATE, 7,
-   CLK_GATE_SET_TO_DISABLE, NULL);
+   CLK_GATE_SET_TO_DISABLE, sysrate_lock);
clk_register_clkdev(clk, hclk, NULL);
clks[hclk] = clk;
  
  	/* PCLK */

clk = clk_register_divider(NULL, pclk_div, hclk, 0,
-  clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL);
+  clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
+  sysrate_lock);
clk = clk_register_gate(NULL, pclk, pclk_div, CLK_SET_RATE_PARENT,
clk_base + CLK_SYSTEM_RATE, 3,
-   CLK_GATE_SET_TO_DISABLE, NULL);
+   CLK_GATE_SET_TO_DISABLE, sysrate_lock);
clk_register_clkdev(clk, pclk, NULL);
clks[pclk] = clk;
  
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c

index d169ef0..c5415ce 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -275,6 +275,7 @@ static DEFINE_SPINLOCK(clk_out_lock);
  static DEFINE_SPINLOCK(pll_div_lock);
  static DEFINE_SPINLOCK(cml_lock);
  static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(sysrate_lock);
  
  #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset,	\

_clk_num, _regs, _gate_flags, _clk_id)  \
@@ -1348,19 +1349,21 @@ static void __init tegra30_super_clk_init(void)
  
  	/* HCLK */

clk = clk_register_divider(NULL, hclk_div, sclk, 0,
-  clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL);
+  clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
+  sysrate_lock);
clk = clk_register_gate(NULL, hclk, hclk_div, CLK_SET_RATE_PARENT,
clk_base + SYSTEM_CLK_RATE, 7,
-   CLK_GATE_SET_TO_DISABLE, NULL);
+   CLK_GATE_SET_TO_DISABLE, sysrate_lock);
clk_register_clkdev(clk, hclk, NULL);
clks[hclk] = clk;
  
  	/* PCLK */

clk = clk_register_divider(NULL, pclk_div, hclk, 0,
-  clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL);
+  clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
+  sysrate_lock);
clk = clk_register_gate(NULL, pclk, pclk_div, CLK_SET_RATE_PARENT,
clk_base + SYSTEM_CLK_RATE, 3,
-   CLK_GATE_SET_TO_DISABLE, NULL);
+   CLK_GATE_SET_TO_DISABLE, sysrate_lock);
clk_register_clkdev(clk, pclk, NULL);
clks[pclk] = clk;
  


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Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Wednesday 06 February 2013 11:40 AM, Hiroshi Doyu wrote:

Prashant Gaikwad  wrote @ Wed, 6 Feb 2013 03:55:00 +0100:


No, clk_ops depends on the clocks you are using. There could be a clock
with mux and gate while another one with mux and div.

You are right. What about the following? We don't have to have similar
copy of clk_composite_ops for each instances.

Clock framework takes decision depending on the ops availability and it
does not know if the clock is mux or gate.

For example,

  if (clk->ops->enable) {
  ret = clk->ops->enable(clk->hw);
  if (ret) {
  __clk_disable(clk->parent);
  return ret;
  }
  }

in above case if clk_composite does not have gate clock then as per your
suggestion if it returns error value then it will fail and it is wrong.

Ok, now I understand. Thank you for explanation.

We always need to allocate clk_composite_ops for each clk_composite,
right? If so what about having "struct clk_ops ops" in "struct
clk_composite"?

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index f30fb4b..5240e24 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -129,20 +129,13 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
 pr_err("%s: could not allocate composite clk\n", __func__);
 return ERR_PTR(-ENOMEM);
 }
+   clk_composite_ops = >ops;
  
 init.name = name;

 init.flags = flags | CLK_IS_BASIC;
 init.parent_names = parent_names;
 init.num_parents = num_parents;
  
-   /* allocate the clock ops */

-   clk_composite_ops = kzalloc(sizeof(*clk_composite_ops), GFP_KERNEL);
-   if (!clk_composite_ops) {
-   pr_err("%s: could not allocate clk ops\n", __func__);
-   kfree(composite);
-   return ERR_PTR(-ENOMEM);
-   }
-
 if (mux_hw && mux_ops) {
 if (!mux_ops->get_parent || !mux_ops->set_parent) {
 clk = ERR_PTR(-EINVAL);
@@ -202,7 +195,6 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
 return clk;
  
  err:

-   kfree(clk_composite_ops);
 kfree(composite);
 return clk;
  }
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f0ac818..bb5d36a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -346,6 +346,8 @@ struct clk_composite {
 const struct clk_ops*mux_ops;
 const struct clk_ops*div_ops;
 const struct clk_ops*gate_ops;
+
+   const struct clk_opsops;
  };
  
  struct clk *clk_register_composite(struct device *dev, const char *name,


This will work, but there is no harm in allocating dynamically. What is 
preferred?





diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index f30fb4b..8f88805 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -27,6 +27,9 @@ static u8 clk_composite_get_parent(struct clk_hw *hw)
  const struct clk_ops *mux_ops = composite->mux_ops;
  struct clk_hw *mux_hw = composite->mux_hw;
   
+   if (!mux_hw->clk)

+  return -EINVAL;
+
  mux_hw->clk = hw->clk;

It is wrong.

Will the above "mux_hw->clk = hw->clk" be removed from the original?


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Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Wednesday 06 February 2013 11:40 AM, Hiroshi Doyu wrote:

Prashant Gaikwad pgaik...@nvidia.com wrote @ Wed, 6 Feb 2013 03:55:00 +0100:


No, clk_ops depends on the clocks you are using. There could be a clock
with mux and gate while another one with mux and div.

You are right. What about the following? We don't have to have similar
copy of clk_composite_ops for each instances.

Clock framework takes decision depending on the ops availability and it
does not know if the clock is mux or gate.

For example,

  if (clk-ops-enable) {
  ret = clk-ops-enable(clk-hw);
  if (ret) {
  __clk_disable(clk-parent);
  return ret;
  }
  }

in above case if clk_composite does not have gate clock then as per your
suggestion if it returns error value then it will fail and it is wrong.

Ok, now I understand. Thank you for explanation.

We always need to allocate clk_composite_ops for each clk_composite,
right? If so what about having struct clk_ops ops in struct
clk_composite?

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index f30fb4b..5240e24 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -129,20 +129,13 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
 pr_err(%s: could not allocate composite clk\n, __func__);
 return ERR_PTR(-ENOMEM);
 }
+   clk_composite_ops = composite-ops;
  
 init.name = name;

 init.flags = flags | CLK_IS_BASIC;
 init.parent_names = parent_names;
 init.num_parents = num_parents;
  
-   /* allocate the clock ops */

-   clk_composite_ops = kzalloc(sizeof(*clk_composite_ops), GFP_KERNEL);
-   if (!clk_composite_ops) {
-   pr_err(%s: could not allocate clk ops\n, __func__);
-   kfree(composite);
-   return ERR_PTR(-ENOMEM);
-   }
-
 if (mux_hw  mux_ops) {
 if (!mux_ops-get_parent || !mux_ops-set_parent) {
 clk = ERR_PTR(-EINVAL);
@@ -202,7 +195,6 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
 return clk;
  
  err:

-   kfree(clk_composite_ops);
 kfree(composite);
 return clk;
  }
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f0ac818..bb5d36a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -346,6 +346,8 @@ struct clk_composite {
 const struct clk_ops*mux_ops;
 const struct clk_ops*div_ops;
 const struct clk_ops*gate_ops;
+
+   const struct clk_opsops;
  };
  
  struct clk *clk_register_composite(struct device *dev, const char *name,


This will work, but there is no harm in allocating dynamically. What is 
preferred?





diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index f30fb4b..8f88805 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -27,6 +27,9 @@ static u8 clk_composite_get_parent(struct clk_hw *hw)
  const struct clk_ops *mux_ops = composite-mux_ops;
  struct clk_hw *mux_hw = composite-mux_hw;
   
+   if (!mux_hw-clk)

+  return -EINVAL;
+
  mux_hw-clk = hw-clk;

It is wrong.

Will the above mux_hw-clk = hw-clk be removed from the original?


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Re: [PATCH] clk: Fix build for Allwinner A1X SoCs

[Prashant Gaikwad]

On Tuesday 05 February 2013 08:35 PM, Thierry Reding wrote:

Commit 85a1819 (clk: sunxi: Use common of_clk_init() function) removed
the source file but didn't update the Makefile, therefore causing the
build to break on Allwinner A1X SoCs.

Signed-off-by: Thierry Reding 


Thanks Thierry!!


---
  drivers/clk/Makefile | 1 -
  1 file changed, 1 deletion(-)

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ce77077..be9392e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -25,7 +25,6 @@ endif
  obj-$(CONFIG_MACH_LOONGSON1)  += clk-ls1x.o
  obj-$(CONFIG_ARCH_U8500)  += ux500/
  obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
-obj-$(CONFIG_ARCH_SUNXI)   += clk-sunxi.o
  obj-$(CONFIG_ARCH_ZYNQ)   += clk-zynq.o
  obj-$(CONFIG_X86) += x86/
  obj-$(CONFIG_ARCH_TEGRA)  += tegra/


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Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:

Hi Prashant,

Thank you for your patch. Please see some comments inline.

On Monday 04 of February 2013 13:41:22 Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad 
---

Changes from V1:
- 2nd patch dropped as the concept is acked by Mike.
- Fixed comments from Stephen.

---
  drivers/clk/Makefile |1 +
  drivers/clk/clk-composite.c  |  208
++ include/linux/clk-provider.h
|   30 ++
  3 files changed, 239 insertions(+), 0 deletions(-)
  create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ce77077..2287848 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)  += clk-fixed-factor.o
  obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
  obj-$(CONFIG_COMMON_CLK) += clk-gate.o
  obj-$(CONFIG_COMMON_CLK) += clk-mux.o
+obj-$(CONFIG_COMMON_CLK) += clk-composite.o

  # SoCs specific
  obj-$(CONFIG_ARCH_BCM2835)   += clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..5a6587f
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
it + * under the terms and conditions of the GNU General Public
License, + * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but
WITHOUT + * ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
General Public License for + * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see
<http://www.gnu.org/licenses/>. + */
+
+#include 
+#include 
+#include 
+#include 
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite,
hw) +
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite->mux_ops;
+ struct clk_hw *mux_hw = composite->mux_hw;
+
+ mux_hw->clk = hw->clk;

Why is this needed? Looks like this filed is already being initialized in
clk_register_composite.


Some ops will get called during clk_init where this clk is not populated 
hence doing here. I have done it for all ops to make sure that any 
future change in clock framework don't break this clock.
Now, why duplicate it in clk_register_composite? It is possible that 
none of these ops get called in clk_init.
For example, recalc_rate is called during init and this ops is supported 
by div clock type, but what if div clock is not added.


I hope this explains the need.


+
+ return mux_ops->get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite->mux_ops;
+ struct clk_hw *mux_hw = composite->mux_hw;
+
+ mux_hw->clk = hw->clk;

Ditto.


+
+ return mux_ops->set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *div_ops = composite->div_ops;
+ struct clk_hw *div_hw = composite->div_hw;
+
+ div_hw->clk = hw->clk;

Ditto.


+
+ return div_ops->recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long
rate, + unsigned long *prate)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *div_ops = composite->div_ops;
+ struct clk_hw *div_hw = composite->div_hw;
+
+ div_hw->clk = hw->clk;

Ditto.


+
+ return div_ops->round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long
rate, +  unsigned long par

Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Tuesday 05 February 2013 03:52 PM, Hiroshi Doyu wrote:

Prashant Gaikwad  wrote @ Tue, 5 Feb 2013 09:33:41 +0100:


The members of "clk_composite_ops" seems to be always assigned
statically. Istead of dynamically allocating/assigning, can't we just
have "clk_composite_ops" statically as below?

static struct clk_ops clk_composite_ops = {
.get_parent = clk_composite_get_parent;
.set_parent = clk_composite_set_parent;
.recalc_rate = clk_composite_recalc_rate;
.round_rate = clk_composite_round_rate;
.set_rate = clk_composite_set_rate;
.is_enabled = clk_composite_is_enabled;
.enable = clk_composite_enable;
.disable = clk_composite_disable;
};

struct clk *clk_register_composite(struct device *dev, const char *name,
   const char **parent_names, int num_parents,
   struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
   struct clk_hw *div_hw, const struct clk_ops *div_ops,
   struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
   unsigned long flags)
{
.

init.ops = _composite_ops;

No, clk_ops depends on the clocks you are using. There could be a clock
with mux and gate while another one with mux and div.

You are right. What about the following? We don't have to have similar
copy of clk_composite_ops for each instances.


Clock framework takes decision depending on the ops availability and it 
does not know if the clock is mux or gate.


For example,

if (clk->ops->enable) {
ret = clk->ops->enable(clk->hw);
if (ret) {
__clk_disable(clk->parent);
return ret;
}
}

in above case if clk_composite does not have gate clock then as per your 
suggestion if it returns error value then it will fail and it is wrong.


Hence clock ops are populated depending on the clock types.


diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index f30fb4b..8f88805 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -27,6 +27,9 @@ static u8 clk_composite_get_parent(struct clk_hw *hw)
 const struct clk_ops *mux_ops = composite->mux_ops;
 struct clk_hw *mux_hw = composite->mux_hw;
  
+   if (!mux_hw->clk)

+  return -EINVAL;
+
 mux_hw->clk = hw->clk;
  


It is wrong.


 return mux_ops->get_parent(mux_hw);
@@ -38,6 +41,9 @@ static int clk_composite_set_parent(struct clk_hw *hw, u8 
index)
 const struct clk_ops *mux_ops = composite->mux_ops;
 struct clk_hw *mux_hw = composite->mux_hw;
  
+   if (!mux_hw->clk)

+  return -EINVAL;
+
 mux_hw->clk = hw->clk;
  
 return mux_ops->set_parent(mux_hw, index);

@@ -50,6 +56,9 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw 
*hw,
 const struct clk_ops *div_ops = composite->div_ops;
 struct clk_hw *div_hw = composite->div_hw;
  
+   if (!div_hw->clk)

+  return -EINVAL;
+
 div_hw->clk = hw->clk;
  
 return div_ops->recalc_rate(div_hw, parent_rate);

@@ -62,6 +71,9 @@ static long clk_composite_round_rate(struct clk_hw *hw, 
unsigned long rate,
 const struct clk_ops *div_ops = composite->div_ops;
 struct clk_hw *div_hw = composite->div_hw;
  
+   if (!div_hw->clk)

+  return -EINVAL;
+
 div_hw->clk = hw->clk;
  
 return div_ops->round_rate(div_hw, rate, prate);

@@ -74,6 +86,9 @@ static int clk_composite_set_rate(struct clk_hw *hw, unsigned 
long rate,
 const struct clk_ops *div_ops = composite->div_ops;
 struct clk_hw *div_hw = composite->div_hw;
  
+   if (!div_hw->clk)

+  return -EINVAL;
+
 div_hw->clk = hw->clk;
  
 return div_ops->set_rate(div_hw, rate, parent_rate);

@@ -85,6 +100,9 @@ static int clk_composite_is_enabled(struct clk_hw *hw)
 const struct clk_ops *gate_ops = composite->gate_ops;
 struct clk_hw *gate_hw = composite->gate_hw;
  
+   if (!gate_hw->clk)

+  return -EINVAL;
+
 gate_hw->clk = hw->clk;
  
 return gate_ops->is_enabled(gate_hw);

@@ -96,6 +114,9 @@ static int clk_composite_enable(struct clk_hw *hw)
 const struct clk_ops *gate_ops = composite->gate_ops;
 struct clk_hw *gate_hw = composite->gate_hw;
  
+   if (!gate_hw->clk)

+  return -EINVAL;
+
 gate_hw->clk = hw->clk;
  
 return gate_ops->enable(gate_hw);

@@ -107,11 +128,25 @@ static void clk_composite_disable(struct clk_hw *hw)
 const struct clk_ops *gate_ops = composite->gate_ops;
 stru

Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Monday 04 February 2013 03:07 PM, Hiroshi Doyu wrote:

Hi Prashant,

Prashant Gaikwad  wrote @ Mon, 4 Feb 2013 09:11:22 +0100:


+struct clk *clk_register_composite(struct device *dev, const char *name,
+   const char **parent_names, int num_parents,
+   struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+   struct clk_hw *div_hw, const struct clk_ops *div_ops,
+   struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+   unsigned long flags)
+{
+   struct clk *clk;
+   struct clk_init_data init;
+   struct clk_composite *composite;
+   struct clk_ops *clk_composite_ops;
+
+   composite = kzalloc(sizeof(*composite), GFP_KERNEL);
+   if (!composite) {
+   pr_err("%s: could not allocate composite clk\n", __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = parent_names;
+   init.num_parents = num_parents;
+
+   /* allocate the clock ops */
+   clk_composite_ops = kzalloc(sizeof(*clk_composite_ops), GFP_KERNEL);

The members of "clk_composite_ops" seems to be always assigned
statically. Istead of dynamically allocating/assigning, can't we just
have "clk_composite_ops" statically as below?

static struct clk_ops clk_composite_ops = {
.get_parent = clk_composite_get_parent;
.set_parent = clk_composite_set_parent;
.recalc_rate = clk_composite_recalc_rate;
.round_rate = clk_composite_round_rate;
.set_rate = clk_composite_set_rate;
.is_enabled = clk_composite_is_enabled;
.enable = clk_composite_enable;
.disable = clk_composite_disable;
};

struct clk *clk_register_composite(struct device *dev, const char *name,
   const char **parent_names, int num_parents,
   struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
   struct clk_hw *div_hw, const struct clk_ops *div_ops,
   struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
   unsigned long flags)
{
.

init.ops = _composite_ops;


No, clk_ops depends on the clocks you are using. There could be a clock 
with mux and gate while another one with mux and div.



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Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Monday 04 February 2013 03:07 PM, Hiroshi Doyu wrote:

Hi Prashant,

Prashant Gaikwad pgaik...@nvidia.com wrote @ Mon, 4 Feb 2013 09:11:22 +0100:


+struct clk *clk_register_composite(struct device *dev, const char *name,
+   const char **parent_names, int num_parents,
+   struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+   struct clk_hw *div_hw, const struct clk_ops *div_ops,
+   struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+   unsigned long flags)
+{
+   struct clk *clk;
+   struct clk_init_data init;
+   struct clk_composite *composite;
+   struct clk_ops *clk_composite_ops;
+
+   composite = kzalloc(sizeof(*composite), GFP_KERNEL);
+   if (!composite) {
+   pr_err(%s: could not allocate composite clk\n, __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = parent_names;
+   init.num_parents = num_parents;
+
+   /* allocate the clock ops */
+   clk_composite_ops = kzalloc(sizeof(*clk_composite_ops), GFP_KERNEL);

The members of clk_composite_ops seems to be always assigned
statically. Istead of dynamically allocating/assigning, can't we just
have clk_composite_ops statically as below?

static struct clk_ops clk_composite_ops = {
.get_parent = clk_composite_get_parent;
.set_parent = clk_composite_set_parent;
.recalc_rate = clk_composite_recalc_rate;
.round_rate = clk_composite_round_rate;
.set_rate = clk_composite_set_rate;
.is_enabled = clk_composite_is_enabled;
.enable = clk_composite_enable;
.disable = clk_composite_disable;
};

struct clk *clk_register_composite(struct device *dev, const char *name,
   const char **parent_names, int num_parents,
   struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
   struct clk_hw *div_hw, const struct clk_ops *div_ops,
   struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
   unsigned long flags)
{
.

init.ops = clk_composite_ops;


No, clk_ops depends on the clocks you are using. There could be a clock 
with mux and gate while another one with mux and div.



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Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Tuesday 05 February 2013 03:52 PM, Hiroshi Doyu wrote:

Prashant Gaikwad pgaik...@nvidia.com wrote @ Tue, 5 Feb 2013 09:33:41 +0100:


The members of clk_composite_ops seems to be always assigned
statically. Istead of dynamically allocating/assigning, can't we just
have clk_composite_ops statically as below?

static struct clk_ops clk_composite_ops = {
.get_parent = clk_composite_get_parent;
.set_parent = clk_composite_set_parent;
.recalc_rate = clk_composite_recalc_rate;
.round_rate = clk_composite_round_rate;
.set_rate = clk_composite_set_rate;
.is_enabled = clk_composite_is_enabled;
.enable = clk_composite_enable;
.disable = clk_composite_disable;
};

struct clk *clk_register_composite(struct device *dev, const char *name,
   const char **parent_names, int num_parents,
   struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
   struct clk_hw *div_hw, const struct clk_ops *div_ops,
   struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
   unsigned long flags)
{
.

init.ops = clk_composite_ops;

No, clk_ops depends on the clocks you are using. There could be a clock
with mux and gate while another one with mux and div.

You are right. What about the following? We don't have to have similar
copy of clk_composite_ops for each instances.


Clock framework takes decision depending on the ops availability and it 
does not know if the clock is mux or gate.


For example,

if (clk-ops-enable) {
ret = clk-ops-enable(clk-hw);
if (ret) {
__clk_disable(clk-parent);
return ret;
}
}

in above case if clk_composite does not have gate clock then as per your 
suggestion if it returns error value then it will fail and it is wrong.


Hence clock ops are populated depending on the clock types.


diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index f30fb4b..8f88805 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -27,6 +27,9 @@ static u8 clk_composite_get_parent(struct clk_hw *hw)
 const struct clk_ops *mux_ops = composite-mux_ops;
 struct clk_hw *mux_hw = composite-mux_hw;
  
+   if (!mux_hw-clk)

+  return -EINVAL;
+
 mux_hw-clk = hw-clk;
  


It is wrong.


 return mux_ops-get_parent(mux_hw);
@@ -38,6 +41,9 @@ static int clk_composite_set_parent(struct clk_hw *hw, u8 
index)
 const struct clk_ops *mux_ops = composite-mux_ops;
 struct clk_hw *mux_hw = composite-mux_hw;
  
+   if (!mux_hw-clk)

+  return -EINVAL;
+
 mux_hw-clk = hw-clk;
  
 return mux_ops-set_parent(mux_hw, index);

@@ -50,6 +56,9 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw 
*hw,
 const struct clk_ops *div_ops = composite-div_ops;
 struct clk_hw *div_hw = composite-div_hw;
  
+   if (!div_hw-clk)

+  return -EINVAL;
+
 div_hw-clk = hw-clk;
  
 return div_ops-recalc_rate(div_hw, parent_rate);

@@ -62,6 +71,9 @@ static long clk_composite_round_rate(struct clk_hw *hw, 
unsigned long rate,
 const struct clk_ops *div_ops = composite-div_ops;
 struct clk_hw *div_hw = composite-div_hw;
  
+   if (!div_hw-clk)

+  return -EINVAL;
+
 div_hw-clk = hw-clk;
  
 return div_ops-round_rate(div_hw, rate, prate);

@@ -74,6 +86,9 @@ static int clk_composite_set_rate(struct clk_hw *hw, unsigned 
long rate,
 const struct clk_ops *div_ops = composite-div_ops;
 struct clk_hw *div_hw = composite-div_hw;
  
+   if (!div_hw-clk)

+  return -EINVAL;
+
 div_hw-clk = hw-clk;
  
 return div_ops-set_rate(div_hw, rate, parent_rate);

@@ -85,6 +100,9 @@ static int clk_composite_is_enabled(struct clk_hw *hw)
 const struct clk_ops *gate_ops = composite-gate_ops;
 struct clk_hw *gate_hw = composite-gate_hw;
  
+   if (!gate_hw-clk)

+  return -EINVAL;
+
 gate_hw-clk = hw-clk;
  
 return gate_ops-is_enabled(gate_hw);

@@ -96,6 +114,9 @@ static int clk_composite_enable(struct clk_hw *hw)
 const struct clk_ops *gate_ops = composite-gate_ops;
 struct clk_hw *gate_hw = composite-gate_hw;
  
+   if (!gate_hw-clk)

+  return -EINVAL;
+
 gate_hw-clk = hw-clk;
  
 return gate_ops-enable(gate_hw);

@@ -107,11 +128,25 @@ static void clk_composite_disable(struct clk_hw *hw)
 const struct clk_ops *gate_ops = composite-gate_ops;
 struct clk_hw *gate_hw = composite-gate_hw;
  
+   if (!gate_hw-clk)

+  return -EINVAL;
+
 gate_hw-clk = hw-clk;
  
 gate_ops-disable(gate_hw);

  }
  
+static struct clk_ops

Re: [PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:

Hi Prashant,

Thank you for your patch. Please see some comments inline.

On Monday 04 of February 2013 13:41:22 Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux - Div - Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Changes from V1:
- 2nd patch dropped as the concept is acked by Mike.
- Fixed comments from Stephen.

---
  drivers/clk/Makefile |1 +
  drivers/clk/clk-composite.c  |  208
++ include/linux/clk-provider.h
|   30 ++
  3 files changed, 239 insertions(+), 0 deletions(-)
  create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ce77077..2287848 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)  += clk-fixed-factor.o
  obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
  obj-$(CONFIG_COMMON_CLK) += clk-gate.o
  obj-$(CONFIG_COMMON_CLK) += clk-mux.o
+obj-$(CONFIG_COMMON_CLK) += clk-composite.o

  # SoCs specific
  obj-$(CONFIG_ARCH_BCM2835)   += clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..5a6587f
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
it + * under the terms and conditions of the GNU General Public
License, + * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but
WITHOUT + * ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
General Public License for + * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see
http://www.gnu.org/licenses/. + */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/err.h
+#include linux/slab.h
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite,
hw) +
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite-mux_ops;
+ struct clk_hw *mux_hw = composite-mux_hw;
+
+ mux_hw-clk = hw-clk;

Why is this needed? Looks like this filed is already being initialized in
clk_register_composite.


Some ops will get called during clk_init where this clk is not populated 
hence doing here. I have done it for all ops to make sure that any 
future change in clock framework don't break this clock.
Now, why duplicate it in clk_register_composite? It is possible that 
none of these ops get called in clk_init.
For example, recalc_rate is called during init and this ops is supported 
by div clock type, but what if div clock is not added.


I hope this explains the need.


+
+ return mux_ops-get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite-mux_ops;
+ struct clk_hw *mux_hw = composite-mux_hw;
+
+ mux_hw-clk = hw-clk;

Ditto.


+
+ return mux_ops-set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *div_ops = composite-div_ops;
+ struct clk_hw *div_hw = composite-div_hw;
+
+ div_hw-clk = hw-clk;

Ditto.


+
+ return div_ops-recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long
rate, + unsigned long *prate)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *div_ops = composite-div_ops;
+ struct clk_hw *div_hw = composite-div_hw;
+
+ div_hw-clk = hw-clk;

Ditto.


+
+ return div_ops-round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long
rate, +  unsigned long parent_rate)
+{
+ struct

Re: [PATCH] clk: Fix build for Allwinner A1X SoCs

[Prashant Gaikwad]

On Tuesday 05 February 2013 08:35 PM, Thierry Reding wrote:

Commit 85a1819 (clk: sunxi: Use common of_clk_init() function) removed
the source file but didn't update the Makefile, therefore causing the
build to break on Allwinner A1X SoCs.

Signed-off-by: Thierry Reding thierry.red...@avionic-design.de


Thanks Thierry!!


---
  drivers/clk/Makefile | 1 -
  1 file changed, 1 deletion(-)

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ce77077..be9392e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -25,7 +25,6 @@ endif
  obj-$(CONFIG_MACH_LOONGSON1)  += clk-ls1x.o
  obj-$(CONFIG_ARCH_U8500)  += ux500/
  obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
-obj-$(CONFIG_ARCH_SUNXI)   += clk-sunxi.o
  obj-$(CONFIG_ARCH_ZYNQ)   += clk-zynq.o
  obj-$(CONFIG_X86) += x86/
  obj-$(CONFIG_ARCH_TEGRA)  += tegra/


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Re: [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114

[Prashant Gaikwad]

On Monday 04 February 2013 08:04 PM, Peter De Schrijver wrote:

On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

...


+   /* xusb_hs_src */
+   val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+   val |= BIT(25); /* always select PLLU_60M */
+   writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
+
+   clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
+   1, 1);
+   clks[xusb_hs_src] = clk;
+

With device tree we can directly use pll_u_60M, no need to register
clock with fixed factor 1.
Same comment for dis1-fixed, dsi2-fixed and mipi-cal-fast clocks.


Does it make sense to have separate DT IDs at all then?


We can use same DT ID.


Cheers,

Peter.


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Re: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code

[Prashant Gaikwad]

On Monday 04 February 2013 08:02 PM, Peter De Schrijver wrote:

On Mon, Feb 04, 2013 at 07:06:47AM +0100, Prashant Gaikwad wrote:

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

...


-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
-void __iomem *lock_addr, u32 lock_bit_idx)
+static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
   {
  int i;
-   u32 val;
+   u32 val, lock_bit;
+   void __iomem *lock_addr;

  if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
  udelay(pll->params->lock_delay);
  return 0;
  }

+   lock_addr = pll->clk_base + pll->params->base_reg;

This will not work for PLLE. Lock bit for PLLE is in misc register.


+   lock_bit = BIT(pll->params->lock_bit_idx);
+
  for (i = 0; i < pll->params->lock_delay; i++) {
  val = readl_relaxed(lock_addr);
-   if (val & BIT(lock_bit_idx)) {
+   if (val & lock_bit) {

Need to change the lock bit idx parameter for Tegra20 and Tegra30 PLLs
else this patch will break those.


Looking at commit 37c26a906527b8a6a252614ca83d21ad318c4e84 and commit
b08e8c0ecc42afa3a2e1019851af741980dd5a6b, these fields seem correctly
initialized for both Tegra20 and Tegra30? Or am I missing something?


Ohh, I missed to read

lock_bit = BIT(pll->params->lock_bit_idx);


Am I missing something about PLLE lock_addr also?


Thanks,

Peter.


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[PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad 
---

Changes from V1:
- 2nd patch dropped as the concept is acked by Mike.
- Fixed comments from Stephen.

---
 drivers/clk/Makefile |1 +
 drivers/clk/clk-composite.c  |  208 ++
 include/linux/clk-provider.h |   30 ++
 3 files changed, 239 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ce77077..2287848 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
 obj-$(CONFIG_COMMON_CLK)   += clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
 
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..5a6587f
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite->gate_ops;
+   struct clk_hw *gate_hw = composite->gate_hw;
+
+   gate_hw->clk = hw->clk;
+
+   return gate_ops->is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_compo

[PATCH V2] clk: Add composite clock type

[Prashant Gaikwad]

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux - Div - Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Changes from V1:
- 2nd patch dropped as the concept is acked by Mike.
- Fixed comments from Stephen.

---
 drivers/clk/Makefile |1 +
 drivers/clk/clk-composite.c  |  208 ++
 include/linux/clk-provider.h |   30 ++
 3 files changed, 239 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ce77077..2287848 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
 obj-$(CONFIG_COMMON_CLK)   += clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
 
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..5a6587f
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/err.h
+#include linux/slab.h
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite-gate_ops;
+   struct clk_hw *gate_hw = composite-gate_hw;
+
+   gate_hw-clk = hw-clk;
+
+   return gate_ops-is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite

Re: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code

[Prashant Gaikwad]

On Monday 04 February 2013 08:02 PM, Peter De Schrijver wrote:

On Mon, Feb 04, 2013 at 07:06:47AM +0100, Prashant Gaikwad wrote:

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

...


-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
-void __iomem *lock_addr, u32 lock_bit_idx)
+static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
   {
  int i;
-   u32 val;
+   u32 val, lock_bit;
+   void __iomem *lock_addr;

  if (!(pll-flags  TEGRA_PLL_USE_LOCK)) {
  udelay(pll-params-lock_delay);
  return 0;
  }

+   lock_addr = pll-clk_base + pll-params-base_reg;

This will not work for PLLE. Lock bit for PLLE is in misc register.


+   lock_bit = BIT(pll-params-lock_bit_idx);
+
  for (i = 0; i  pll-params-lock_delay; i++) {
  val = readl_relaxed(lock_addr);
-   if (val  BIT(lock_bit_idx)) {
+   if (val  lock_bit) {

Need to change the lock bit idx parameter for Tegra20 and Tegra30 PLLs
else this patch will break those.


Looking at commit 37c26a906527b8a6a252614ca83d21ad318c4e84 and commit
b08e8c0ecc42afa3a2e1019851af741980dd5a6b, these fields seem correctly
initialized for both Tegra20 and Tegra30? Or am I missing something?


Ohh, I missed to read

lock_bit = BIT(pll-params-lock_bit_idx);


Am I missing something about PLLE lock_addr also?


Thanks,

Peter.


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Re: [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114

[Prashant Gaikwad]

On Monday 04 February 2013 08:04 PM, Peter De Schrijver wrote:

On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

...


+   /* xusb_hs_src */
+   val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+   val |= BIT(25); /* always select PLLU_60M */
+   writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
+
+   clk = clk_register_fixed_factor(NULL, xusb_hs_src, pll_u_60M, 0,
+   1, 1);
+   clks[xusb_hs_src] = clk;
+

With device tree we can directly use pll_u_60M, no need to register
clock with fixed factor 1.
Same comment for dis1-fixed, dsi2-fixed and mipi-cal-fast clocks.


Does it make sense to have separate DT IDs at all then?


We can use same DT ID.


Cheers,

Peter.


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Re: [PATCH v5 10/10] clk: tegra: devicetree match for nvidia,tegra114-car

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Signed-off-by: Peter De Schrijver 
---


Reviewed-by: Prashant Gaikwad 


  drivers/clk/tegra/clk.c |1 +
  drivers/clk/tegra/clk.h |7 +++
  2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a603b9a..a328365 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -76,6 +76,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table 
*tbl,
  static const struct of_device_id tegra_dt_clk_match[] = {
{ .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
{ .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
+   { .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
{ }
  };
  
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h

index 8756d9f..8097850 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -576,4 +576,11 @@ void tegra30_clock_init(struct device_node *np);
  static inline void tegra30_clock_init(struct device_node *np) {}
  #endif /* CONFIG_ARCH_TEGRA_3x_SOC */
  
+#ifdef CONFIG_ARCH_TEGRA_114_SOC

+void tegra114_clock_init(struct device_node *np);
+#else
+static inline void tegra114_clock_init(struct device_node *np) {}
+#endif /* CONFIG_ARCH_TEGRA114_SOC */
+
+
  #endif /* TEGRA_CLK_H */



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Re: [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Implement most clocks for Tegra114. The super clocks for the CPU complex
are still missing and will be implemented in a future version.

Signed-off-by: Peter De Schrijver 
---
  drivers/clk/tegra/Makefile   |1 +
  drivers/clk/tegra/clk-tegra114.c | 2002 ++
  2 files changed, 2003 insertions(+), 0 deletions(-)
  create mode 100644 drivers/clk/tegra/clk-tegra114.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 2b41b0f..f49fac2 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -9,3 +9,4 @@ obj-y   += clk-super.o

  obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
  obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)   += clk-tegra114.o
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
new file mode 100644
index 000..f8165d2
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -0,0 +1,2002 @@
+/*
+ * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define RST_DEVICES_L  0x004
+#define RST_DEVICES_H  0x008
+#define RST_DEVICES_U  0x00C
+#define RST_DEVICES_V  0x358
+#define RST_DEVICES_W  0x35C
+#define RST_DEVICES_X  0x28C
+#define RST_DEVICES_SET_L  0x300
+#define RST_DEVICES_CLR_L  0x304
+#define RST_DEVICES_SET_H  0x308
+#define RST_DEVICES_CLR_H  0x30c
+#define RST_DEVICES_SET_U  0x310
+#define RST_DEVICES_CLR_U  0x314
+#define RST_DEVICES_SET_V  0x430
+#define RST_DEVICES_CLR_V  0x434
+#define RST_DEVICES_SET_W  0x438
+#define RST_DEVICES_CLR_W  0x43c
+#define RST_DEVICES_NUM5


RST_DEVICES_SET/CLR_X?


+
+#define CLK_OUT_ENB_L  0x010
+#define CLK_OUT_ENB_H  0x014
+#define CLK_OUT_ENB_U  0x018
+#define CLK_OUT_ENB_V  0x360
+#define CLK_OUT_ENB_W  0x364
+#define CLK_OUT_ENB_X  0x280
+#define CLK_OUT_ENB_SET_L  0x320
+#define CLK_OUT_ENB_CLR_L  0x324
+#define CLK_OUT_ENB_SET_H  0x328
+#define CLK_OUT_ENB_CLR_H  0x32c
+#define CLK_OUT_ENB_SET_U  0x330
+#define CLK_OUT_ENB_CLR_U  0x334
+#define CLK_OUT_ENB_SET_V  0x440
+#define CLK_OUT_ENB_CLR_V  0x444
+#define CLK_OUT_ENB_SET_W  0x448
+#define CLK_OUT_ENB_CLR_W  0x44c
+#define CLK_OUT_ENB_SET_X  0x284
+#define CLK_OUT_ENB_CLR_X  0x288
+#define CLK_OUT_ENB_NUM6





+
+   /* dsia */
+   clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
+  ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+  clk_base + PLLD_BASE, 25, 1, 0, _d_lock);
+   clks[dsia_mux] = clk;
+   clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
+   0, 48, _h_regs,
+   periph_clk_enb_refcnt);
+   clk_register_clkdev(clk, "dsia", "tegradc.0");
+   clks[dsia] = clk;
+
+   /* dsib */
+   clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
+  ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+  clk_base + PLLD2_BASE, 25, 1, 0, _d2_lock);
+   clks[dsib_mux] = clk;
+   clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
+   0, 82, _u_regs,
+   periph_clk_enb_refcnt);
+   clk_register_clkdev(clk, "dsib", "tegradc.1");
+   clks[dsib] = clk;
+


Can we use periph no div clock here for dsia and dsib?


+   /* xusb_hs_src */
+   val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+   val |= BIT(25); /* always select PLLU_60M */
+   writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
+
+   clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 

Re: [PATCH v5 08/10] ARM: dt: Add references to tegra_car clocks

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Add references to tegra_car clocks for the basic device nodes.

Signed-off-by: Peter De Schrijver 
---


Reviewed-by: Prashant Gaikwad 


  arch/arm/boot/dts/tegra114.dtsi |7 ++-
  1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 96a8235..1dec620 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -27,7 +27,7 @@
};
  
  	tegra_car: clock {

-   compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+   compatible = "nvidia,tegra114-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
};
@@ -43,6 +43,7 @@
reg-shift = <2>;
interrupts = <0 36 0x04>;
status = "disabled";
+   clocks = <_car 6>;
};
  
  	serial@70006040 {

@@ -51,6 +52,7 @@
reg-shift = <2>;
interrupts = <0 37 0x04>;
status = "disabled";
+   clocks = <_car 192>;
};
  
  	serial@70006200 {

@@ -59,6 +61,7 @@
reg-shift = <2>;
interrupts = <0 46 0x04>;
status = "disabled";
+   clocks = <_car 55>;
};
  
  	serial@70006300 {

@@ -67,12 +70,14 @@
reg-shift = <2>;
interrupts = <0 90 0x04>;
status = "disabled";
+   clocks = <_car 65>;
};
  
  	rtc {

compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>;
+   clocks = <_car 4>;
};
  
  	pmc {




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Re: [PATCH v5 06/10] clk: tegra: Workaround for Tegra114 MSENC problem

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Workaround a hardware bug in MSENC during clock enable.

Signed-off-by: Peter De Schrijver 
---
  drivers/clk/tegra/clk-periph-gate.c |9 +
  drivers/clk/tegra/clk.h |1 +
  2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph-gate.c 
b/drivers/clk/tegra/clk-periph-gate.c
index 6dd5332..c9083fb 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -43,6 +43,8 @@ static DEFINE_SPINLOCK(periph_ref_lock);
  
  #define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
  
+#define LVL2_CLK_GATE_OVRE 0x554

+
  /* Peripheral gate clock ops */
  static int clk_periph_is_enabled(struct clk_hw *hw)
  {
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
}
}
  
+	if (gate->flags & TEGRA_PERIPH_WAR_1005168) {

+   writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+   writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
+   udelay(1);
+   writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+   }
+
spin_unlock_irqrestore(_ref_lock, flags);
  
  	return 0;

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 79f5e2a..8756d9f 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -371,6 +371,7 @@ struct tegra_clk_periph_gate {
  #define TEGRA_PERIPH_NO_RESET BIT(0)
  #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
  #define TEGRA_PERIPH_ON_APB BIT(2)
+#define TEGRA_PERIPH_WAR_1005168 BIT(3)
  


Comment for this flag, otherwise

Reviewed-by: Prashant Gaikwad 


  void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
  extern const struct clk_ops tegra_clk_periph_gate_ops;



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Re: [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114

[Prashant Gaikwad]

On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote:

On 2/1/2013 5:18 AM, Peter De Schrijver wrote:

Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.

Signed-off-by: Peter De Schrijver 
---
   drivers/clk/tegra/clk-pll.c |  719 
+++
   drivers/clk/tegra/clk.h |   47 +++
   2 files changed, 766 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 87d2f34..50114b7 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
[snip]
+struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
+ void __iomem *clk_base, void __iomem *pmc,
+ unsigned long flags, unsigned long fixed_rate,
+ struct tegra_clk_pll_params *pll_params,
+ u32 pll_flags,
+ struct tegra_clk_pll_freq_table *freq_table,
+ spinlock_t *lock)
+{
+   if (!pll_params->pdiv_tohw)
+   return -EINVAL;
+

This will cause the following warning:
warning: return makes pointer from integer without a cast

Same with occurrences in tegra_clk_register_pllm and
tegra_clk_register_pllc.

Should this instead be returning NULL?


return ERR_PTR(-EINVAL)



-rhyland



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Re: [PATCH v5 05/10] clk: tegra: Add flags to tegra_clk_periph()

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.

Signed-off-by: Peter De Schrijver 
---


Looks good to me.

Reviewed-by: Prashant Gaikwad 


  drivers/clk/tegra/clk-periph.c  |   11 ++-
  drivers/clk/tegra/clk-tegra20.c |2 +-
  drivers/clk/tegra/clk-tegra30.c |2 +-
  drivers/clk/tegra/clk.h |9 ++---
  4 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 788486e..067abb3 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -170,14 +170,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
  static struct clk *_tegra_clk_register_periph(const char *name,
const char **parent_names, int num_parents,
struct tegra_clk_periph *periph,
-   void __iomem *clk_base, u32 offset, bool div)
+   void __iomem *clk_base, u32 offset, bool div,
+   unsigned long flags)
  {
struct clk *clk;
struct clk_init_data init;
  
  	init.name = name;

init.ops = div ? _clk_periph_ops : _clk_periph_nodiv_ops;
-   init.flags = div ? 0 : CLK_SET_RATE_PARENT;
+   init.flags = flags;
init.parent_names = parent_names;
init.num_parents = num_parents;
  
@@ -202,10 +203,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,

  struct clk *tegra_clk_register_periph(const char *name,
const char **parent_names, int num_parents,
struct tegra_clk_periph *periph, void __iomem *clk_base,
-   u32 offset)
+   u32 offset, unsigned long flags)
  {
return _tegra_clk_register_periph(name, parent_names, num_parents,
-   periph, clk_base, offset, true);
+   periph, clk_base, offset, true, flags);
  }
  
  struct clk *tegra_clk_register_periph_nodiv(const char *name,

@@ -214,5 +215,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char 
*name,
u32 offset)
  {
return _tegra_clk_register_periph(name, parent_names, num_parents,
-   periph, clk_base, offset, false);
+   periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
  }
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 54c6777..870349e 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1048,7 +1048,7 @@ static void __init tegra20_periph_clk_init(void)
data = _periph_clk_list[i];
clk = tegra_clk_register_periph(data->name, data->parent_names,
data->num_parents, >periph,
-   clk_base, data->offset);
+   clk_base, data->offset, data->flags);
clk_register_clkdev(clk, data->con_id, data->dev_id);
clks[data->clk_id] = clk;
}
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 078f9b8..126747b 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1665,7 +1665,7 @@ static void __init tegra30_periph_clk_init(void)
data = _periph_clk_list[i];
clk = tegra_clk_register_periph(data->name, data->parent_names,
data->num_parents, >periph,
-   clk_base, data->offset);
+   clk_base, data->offset, data->flags);
clk_register_clkdev(clk, data->con_id, data->dev_id);
clks[data->clk_id] = clk;
}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 4d0f556..79f5e2a 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -411,7 +411,7 @@ extern const struct clk_ops tegra_clk_periph_ops;
  struct clk *tegra_clk_register_periph(const char *name,
const char **parent_names, int num_parents,
struct tegra_clk_periph *periph, void __iomem *clk_base,
-   u32 offset);
+   u32 offset, unsigned long flags);
  struct clk *tegra_clk_register_periph_nodiv(const char *name,
const char **parent_names, int num_parents,
struct tegra_clk_periph *periph, void __iomem *clk_base,
@@ -454,12 +454,14 @@ struct tegra_periph_init_data {
u32 offset;
const char *con_id;
const char *dev_id;
+   unsigned long flags;
  };
  
  #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\

_mux_shift, _mux_mask, _mux_flags, _div_shift,  \
_div_width, _div_frac_width, _div_flags, _regs, \
-  

Re: [PATCH v5 03/10] clk: tegra: Add PLL post divider table

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.

Signed-off-by: Peter De Schrijver 
---


Looks good to me.

Reviewed-by: Prashant Gaikwad 


  drivers/clk/tegra/clk-pll.c |   38 --
  drivers/clk/tegra/clk-tegra20.c |7 +++
  drivers/clk/tegra/clk-tegra30.c |7 +++
  drivers/clk/tegra/clk.h |   13 +
  4 files changed, 59 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 3c3a25e..87d2f34 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -258,6 +258,7 @@ static int _calc_rate(struct clk_hw *hw, struct 
tegra_clk_pll_freq_table *cfg,
  unsigned long rate, unsigned long parent_rate)
  {
struct tegra_clk_pll *pll = to_clk_pll(hw);
+   struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
unsigned long cfreq;
u32 p_div = 0;
  
@@ -291,7 +292,6 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,

 cfg->output_rate <<= 1)
p_div++;
  
-	cfg->p = p_div;

cfg->m = parent_rate / cfreq;
cfg->n = cfg->output_rate / cfreq;
cfg->cpcon = OUT_OF_TABLE_CPCON;
@@ -304,8 +304,19 @@ static int _calc_rate(struct clk_hw *hw, struct 
tegra_clk_pll_freq_table *cfg,
return -EINVAL;
}
  
-	if (pll->flags & TEGRA_PLLU)

-   cfg->p ^= 1;
+   if (p_tohw) {
+   p_div = 1 << p_div;
+   while (p_tohw->pdiv) {
+   if (p_div <= p_tohw->pdiv) {
+   cfg->p = p_tohw->hw_val;
+   break;
+   }
+   p_tohw++;
+   }
+   if (!p_tohw->pdiv)
+   return -EINVAL;
+   } else
+   cfg->p = p_div;
  
  	return 0;

  }
@@ -452,8 +463,10 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
  {
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct tegra_clk_pll_freq_table cfg;
+   struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
u32 val;
u64 rate = parent_rate;
+   int pdiv;
  
  	val = pll_readl_base(pll);
  
@@ -472,10 +485,23 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
  
  	_get_pll_mnp(pll, );
  
-	if (pll->flags & TEGRA_PLLU)

-   cfg.p ^= 1;
+   if (p_tohw) {
+   while (p_tohw->pdiv) {
+   if (cfg.p == p_tohw->hw_val) {
+   pdiv = p_tohw->pdiv;
+   break;
+   }
+   p_tohw++;
+   }
+
+   if (!p_tohw->pdiv) {
+   WARN_ON(1);
+   pdiv = 1;
+   }
+   } else
+   pdiv = 1 << cfg.p;
  
-	cfg.m *= 1 << cfg.p;

+   cfg.m *= pdiv;
  
  	rate *= cfg.n;

do_div(rate, cfg.m);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 30bd3fd..54c6777 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -440,6 +440,12 @@ static struct tegra_clk_pll_params pll_d_params = {
.lock_delay = 1000,
  };
  
+static struct pdiv_map pllu_p[] = {

+   { .pdiv = 1, .hw_val = 1 },
+   { .pdiv = 2, .hw_val = 0 },
+   { .pdiv = 0, .hw_val = 0 },
+};
+
  static struct tegra_clk_pll_params pll_u_params = {
.input_min = 200,
.input_max = 4000,
@@ -452,6 +458,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+   .pdiv_tohw = pllu_p,
  };
  
  static struct tegra_clk_pll_params pll_x_params = {

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 28a2997..078f9b8 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -466,6 +466,12 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] 
= {
{ 0, 0, 0, 0, 0, 0 },
  };
  
+static struct pdiv_map pllu_p[] = {

+   { .pdiv = 1, .hw_val = 1 },
+   { .pdiv = 2, .hw_val = 0 },
+   { .pdiv = 0, .hw_val = 0 },
+};
+
  static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
{ 1200, 48000, 960, 12, 0, 12},
{ 1300, 48000, 960, 13, 0, 12},
@@ -639,6 +645,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+   .pdiv_tohw = pllu_p,
  };
  
  static struct tegra_clk_pll_params pll_x_

Re: [PATCH v5 02/10] clk: tegra: Add TEGRA_PLL_BYPASS flag

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.

Signed-off-by: Peter De Schrijver 
---


Looks good to me.

Reviewed-by: Prashant Gaikwad 


  drivers/clk/tegra/clk-pll.c |   15 ++-
  drivers/clk/tegra/clk.h |8 +---
  2 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 912c977..3c3a25e 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -166,7 +166,8 @@ static void _clk_pll_enable(struct clk_hw *hw)
clk_pll_enable_lock(pll);
  
  	val = pll_readl_base(pll);

-   val &= ~PLL_BASE_BYPASS;
+   if (pll->flags & TEGRA_PLL_BYPASS)
+   val &= ~PLL_BASE_BYPASS;
val |= PLL_BASE_ENABLE;
pll_writel_base(val, pll);
  
@@ -183,7 +184,9 @@ static void _clk_pll_disable(struct clk_hw *hw)

u32 val;
  
  	val = pll_readl_base(pll);

-   val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+   if (pll->flags & TEGRA_PLL_BYPASS)
+   val &= ~PLL_BASE_BYPASS;
+   val &= ~PLL_BASE_ENABLE;
pll_writel_base(val, pll);
  
  	if (pll->flags & TEGRA_PLLM) {

@@ -454,7 +457,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
  
  	val = pll_readl_base(pll);
  
-	if (val & PLL_BASE_BYPASS)

+   if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
return parent_rate;
  
  	if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {

@@ -660,9 +663,10 @@ static struct clk *_tegra_clk_register_pll(const char 
*name,
  struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
-   struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+   struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
  {
+   pll_flags |= TEGRA_PLL_BYPASS;
return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
flags, fixed_rate, pll_params, pll_flags, freq_table,
lock, _clk_pll_ops);
@@ -671,9 +675,10 @@ struct clk *tegra_clk_register_pll(const char *name, const 
char *parent_name,
  struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
-   struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+   struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
  {
+   pll_flags |= TEGRA_PLL_BYPASS;
return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
flags, fixed_rate, pll_params, pll_flags, freq_table,
lock, _clk_plle_ops);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index a09d7dc..3cff1df 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -182,12 +182,13 @@ struct tegra_clk_pll_params {
   * TEGRA_PLL_FIXED - We are not supposed to change output frequency
   * of some plls.
   * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
+ * TEGRA_PLL_BYPASS - PLL has bypass bit
   */
  struct tegra_clk_pll {
struct clk_hw   hw;
void __iomem*clk_base;
void __iomem*pmc;
-   u8  flags;
+   u32 flags;
unsigned long   fixed_rate;
spinlock_t  *lock;
u8  divn_shift;
@@ -210,18 +211,19 @@ struct tegra_clk_pll {
  #define TEGRA_PLLM BIT(5)
  #define TEGRA_PLL_FIXED BIT(6)
  #define TEGRA_PLLE_CONFIGURE BIT(7)
+#define TEGRA_PLL_BYPASS BIT(8)
  
  extern const struct clk_ops tegra_clk_pll_ops;

  extern const struct clk_ops tegra_clk_plle_ops;
  struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
-   struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+   struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
  struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
-   struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+   struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock

Re: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.

The following changes were done:

* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
   by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()

Signed-off-by: Peter De Schrijver 
---
  drivers/clk/tegra/clk-pll.c |  178 +
  drivers/clk/tegra/clk-tegra20.c |  144 
  drivers/clk/tegra/clk-tegra30.c |  234 +++---
  3 files changed, 294 insertions(+), 262 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 165f247..912c977 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1,5 +1,5 @@
  /*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   *
   * This program is free software; you can redistribute it and/or modify it
   * under the terms and conditions of the GNU General Public License,
@@ -113,20 +113,23 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 pll_writel_misc(val, pll);
  }

-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
-void __iomem *lock_addr, u32 lock_bit_idx)
+static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
  {
 int i;
-   u32 val;
+   u32 val, lock_bit;
+   void __iomem *lock_addr;

 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
 udelay(pll->params->lock_delay);
 return 0;
 }

+   lock_addr = pll->clk_base + pll->params->base_reg;


This will not work for PLLE. Lock bit for PLLE is in misc register.


+   lock_bit = BIT(pll->params->lock_bit_idx);
+
 for (i = 0; i < pll->params->lock_delay; i++) {
 val = readl_relaxed(lock_addr);
-   if (val & BIT(lock_bit_idx)) {
+   if (val & lock_bit) {


Need to change the lock bit idx parameter for Tegra20 and Tegra30 PLLs 
else this patch will break those.



 udelay(PLL_POST_LOCK_DELAY);
 return 0;
 }
@@ -155,7 +158,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
 return val & PLL_BASE_ENABLE ? 1 : 0;
  }





@@ -538,8 +570,8 @@ static int clk_plle_enable(struct clk_hw *hw)
 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 pll_writel_base(val, pll);

-   clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
- pll->params->lock_bit_idx);
+   clk_pll_wait_for_lock(pll);
+
 return 0;
  }





  static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 /* 1.7 GHz */
-   { 1200, 17, 850,  6,  1, 8},
-   { 1300, 17, 915,  7,  1, 8},/* actual: 1699.2 MHz */
-   { 1680, 17, 708,  7,  1, 8},/* actual: 1699.2 MHz */
-   { 1920, 17, 885,  10, 1, 8},/* actual: 1699.2 MHz */
-   { 2600, 17, 850,  13, 1, 8},
+   { 1200, 17, 850,  6,  0, 8},
+   { 1300, 17, 915,  7,  0, 8},/* actual: 1699.2 MHz */
+   { 1680, 17, 708,  7,  0, 8},/* actual: 1699.2 MHz */
+   { 1920, 17, 885,  10, 0, 8},/* actual: 1699.2 MHz */
+   { 2600, 17, 850,  13, 0, 8},

 /* 1.6 GHz */
-   { 1200, 16, 800,  6,  1, 8},
-   { 1300, 16, 738,  6,  1, 8},/* actual: 1599.0 MHz */
-   { 1680, 16, 857,  9,  1, 8},/* actual: 1599.7 MHz */
-   { 1920, 16, 500,  6,  1, 8},
-   { 2600, 16, 800,  13, 1, 8},
+   { 1200, 16, 800,  6,  0, 8},
+   { 1300, 16, 738,  6,  0, 8},/* actual: 1599.0 MHz */
+   { 1680, 16, 857,  9,  0, 8},/* actual: 1599.7 MHz */
+   { 1920, 16, 500,  6,  0, 8},
+   { 2600, 16, 800,  13, 0, 8},

 /* 1.5 GHz */
-   { 1200, 15, 750,  6,  1, 8},
-   { 1300, 15, 923,  8,  1, 8},/* actual: 1499.8 MHz */
-   { 1680, 15, 625,  7,  1, 8},
-   { 1920, 15, 625,  8,  1, 8},
-   { 2600, 15, 750,  13, 1, 8},
+   { 1200, 15, 750,  6,  0, 8},
+   { 1300, 15, 923,  8,  0, 8},/* actual: 1499.8 MHz */
+   { 1680, 15, 625,  7,  0, 8},
+   { 1920, 15, 625,  8,  0, 8},
+   { 2600, 15, 750,  13, 0, 8},

 /* 

Re: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.

The following changes were done:

* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
   by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
  drivers/clk/tegra/clk-pll.c |  178 +
  drivers/clk/tegra/clk-tegra20.c |  144 
  drivers/clk/tegra/clk-tegra30.c |  234 +++---
  3 files changed, 294 insertions(+), 262 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 165f247..912c977 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1,5 +1,5 @@
  /*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   *
   * This program is free software; you can redistribute it and/or modify it
   * under the terms and conditions of the GNU General Public License,
@@ -113,20 +113,23 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 pll_writel_misc(val, pll);
  }

-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
-void __iomem *lock_addr, u32 lock_bit_idx)
+static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
  {
 int i;
-   u32 val;
+   u32 val, lock_bit;
+   void __iomem *lock_addr;

 if (!(pll-flags  TEGRA_PLL_USE_LOCK)) {
 udelay(pll-params-lock_delay);
 return 0;
 }

+   lock_addr = pll-clk_base + pll-params-base_reg;


This will not work for PLLE. Lock bit for PLLE is in misc register.


+   lock_bit = BIT(pll-params-lock_bit_idx);
+
 for (i = 0; i  pll-params-lock_delay; i++) {
 val = readl_relaxed(lock_addr);
-   if (val  BIT(lock_bit_idx)) {
+   if (val  lock_bit) {


Need to change the lock bit idx parameter for Tegra20 and Tegra30 PLLs 
else this patch will break those.



 udelay(PLL_POST_LOCK_DELAY);
 return 0;
 }
@@ -155,7 +158,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
 return val  PLL_BASE_ENABLE ? 1 : 0;
  }


snip


@@ -538,8 +570,8 @@ static int clk_plle_enable(struct clk_hw *hw)
 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 pll_writel_base(val, pll);

-   clk_pll_wait_for_lock(pll, pll-clk_base + pll-params-misc_reg,
- pll-params-lock_bit_idx);
+   clk_pll_wait_for_lock(pll);
+
 return 0;
  }


snip


  static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 /* 1.7 GHz */
-   { 1200, 17, 850,  6,  1, 8},
-   { 1300, 17, 915,  7,  1, 8},/* actual: 1699.2 MHz */
-   { 1680, 17, 708,  7,  1, 8},/* actual: 1699.2 MHz */
-   { 1920, 17, 885,  10, 1, 8},/* actual: 1699.2 MHz */
-   { 2600, 17, 850,  13, 1, 8},
+   { 1200, 17, 850,  6,  0, 8},
+   { 1300, 17, 915,  7,  0, 8},/* actual: 1699.2 MHz */
+   { 1680, 17, 708,  7,  0, 8},/* actual: 1699.2 MHz */
+   { 1920, 17, 885,  10, 0, 8},/* actual: 1699.2 MHz */
+   { 2600, 17, 850,  13, 0, 8},

 /* 1.6 GHz */
-   { 1200, 16, 800,  6,  1, 8},
-   { 1300, 16, 738,  6,  1, 8},/* actual: 1599.0 MHz */
-   { 1680, 16, 857,  9,  1, 8},/* actual: 1599.7 MHz */
-   { 1920, 16, 500,  6,  1, 8},
-   { 2600, 16, 800,  13, 1, 8},
+   { 1200, 16, 800,  6,  0, 8},
+   { 1300, 16, 738,  6,  0, 8},/* actual: 1599.0 MHz */
+   { 1680, 16, 857,  9,  0, 8},/* actual: 1599.7 MHz */
+   { 1920, 16, 500,  6,  0, 8},
+   { 2600, 16, 800,  13, 0, 8},

 /* 1.5 GHz */
-   { 1200, 15, 750,  6,  1, 8},
-   { 1300, 15, 923,  8,  1, 8},/* actual: 1499.8 MHz */
-   { 1680, 15, 625,  7,  1, 8},
-   { 1920, 15, 625,  8,  1, 8},
-   { 2600, 15, 750,  13, 1, 8},
+   { 1200, 15, 750,  6,  0, 8},
+   { 1300, 15, 923,  8,  0, 8},/* actual: 1499.8 MHz */
+   { 1680, 15, 625,  7,  0, 8},
+   { 1920, 15, 625,  8,  0, 8},
+   { 2600, 15, 750,  13, 0, 8},

  

Re: [PATCH v5 02/10] clk: tegra: Add TEGRA_PLL_BYPASS flag

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---


Looks good to me.

Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


  drivers/clk/tegra/clk-pll.c |   15 ++-
  drivers/clk/tegra/clk.h |8 +---
  2 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 912c977..3c3a25e 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -166,7 +166,8 @@ static void _clk_pll_enable(struct clk_hw *hw)
clk_pll_enable_lock(pll);
  
  	val = pll_readl_base(pll);

-   val = ~PLL_BASE_BYPASS;
+   if (pll-flags  TEGRA_PLL_BYPASS)
+   val = ~PLL_BASE_BYPASS;
val |= PLL_BASE_ENABLE;
pll_writel_base(val, pll);
  
@@ -183,7 +184,9 @@ static void _clk_pll_disable(struct clk_hw *hw)

u32 val;
  
  	val = pll_readl_base(pll);

-   val = ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+   if (pll-flags  TEGRA_PLL_BYPASS)
+   val = ~PLL_BASE_BYPASS;
+   val = ~PLL_BASE_ENABLE;
pll_writel_base(val, pll);
  
  	if (pll-flags  TEGRA_PLLM) {

@@ -454,7 +457,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
  
  	val = pll_readl_base(pll);
  
-	if (val  PLL_BASE_BYPASS)

+   if ((pll-flags  TEGRA_PLL_BYPASS)  (val  PLL_BASE_BYPASS))
return parent_rate;
  
  	if ((pll-flags  TEGRA_PLL_FIXED)  !(val  PLL_BASE_OVERRIDE)) {

@@ -660,9 +663,10 @@ static struct clk *_tegra_clk_register_pll(const char 
*name,
  struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
-   struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+   struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
  {
+   pll_flags |= TEGRA_PLL_BYPASS;
return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
flags, fixed_rate, pll_params, pll_flags, freq_table,
lock, tegra_clk_pll_ops);
@@ -671,9 +675,10 @@ struct clk *tegra_clk_register_pll(const char *name, const 
char *parent_name,
  struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
-   struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+   struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
  {
+   pll_flags |= TEGRA_PLL_BYPASS;
return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
flags, fixed_rate, pll_params, pll_flags, freq_table,
lock, tegra_clk_plle_ops);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index a09d7dc..3cff1df 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -182,12 +182,13 @@ struct tegra_clk_pll_params {
   * TEGRA_PLL_FIXED - We are not supposed to change output frequency
   * of some plls.
   * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
+ * TEGRA_PLL_BYPASS - PLL has bypass bit
   */
  struct tegra_clk_pll {
struct clk_hw   hw;
void __iomem*clk_base;
void __iomem*pmc;
-   u8  flags;
+   u32 flags;
unsigned long   fixed_rate;
spinlock_t  *lock;
u8  divn_shift;
@@ -210,18 +211,19 @@ struct tegra_clk_pll {
  #define TEGRA_PLLM BIT(5)
  #define TEGRA_PLL_FIXED BIT(6)
  #define TEGRA_PLLE_CONFIGURE BIT(7)
+#define TEGRA_PLL_BYPASS BIT(8)
  
  extern const struct clk_ops tegra_clk_pll_ops;

  extern const struct clk_ops tegra_clk_plle_ops;
  struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
-   struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+   struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
  struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
-   struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+   struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
  
  /**



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Re: [PATCH v5 03/10] clk: tegra: Add PLL post divider table

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---


Looks good to me.

Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


  drivers/clk/tegra/clk-pll.c |   38 --
  drivers/clk/tegra/clk-tegra20.c |7 +++
  drivers/clk/tegra/clk-tegra30.c |7 +++
  drivers/clk/tegra/clk.h |   13 +
  4 files changed, 59 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 3c3a25e..87d2f34 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -258,6 +258,7 @@ static int _calc_rate(struct clk_hw *hw, struct 
tegra_clk_pll_freq_table *cfg,
  unsigned long rate, unsigned long parent_rate)
  {
struct tegra_clk_pll *pll = to_clk_pll(hw);
+   struct pdiv_map *p_tohw = pll-params-pdiv_tohw;
unsigned long cfreq;
u32 p_div = 0;
  
@@ -291,7 +292,6 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,

 cfg-output_rate = 1)
p_div++;
  
-	cfg-p = p_div;

cfg-m = parent_rate / cfreq;
cfg-n = cfg-output_rate / cfreq;
cfg-cpcon = OUT_OF_TABLE_CPCON;
@@ -304,8 +304,19 @@ static int _calc_rate(struct clk_hw *hw, struct 
tegra_clk_pll_freq_table *cfg,
return -EINVAL;
}
  
-	if (pll-flags  TEGRA_PLLU)

-   cfg-p ^= 1;
+   if (p_tohw) {
+   p_div = 1  p_div;
+   while (p_tohw-pdiv) {
+   if (p_div = p_tohw-pdiv) {
+   cfg-p = p_tohw-hw_val;
+   break;
+   }
+   p_tohw++;
+   }
+   if (!p_tohw-pdiv)
+   return -EINVAL;
+   } else
+   cfg-p = p_div;
  
  	return 0;

  }
@@ -452,8 +463,10 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
  {
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct tegra_clk_pll_freq_table cfg;
+   struct pdiv_map *p_tohw = pll-params-pdiv_tohw;
u32 val;
u64 rate = parent_rate;
+   int pdiv;
  
  	val = pll_readl_base(pll);
  
@@ -472,10 +485,23 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
  
  	_get_pll_mnp(pll, cfg);
  
-	if (pll-flags  TEGRA_PLLU)

-   cfg.p ^= 1;
+   if (p_tohw) {
+   while (p_tohw-pdiv) {
+   if (cfg.p == p_tohw-hw_val) {
+   pdiv = p_tohw-pdiv;
+   break;
+   }
+   p_tohw++;
+   }
+
+   if (!p_tohw-pdiv) {
+   WARN_ON(1);
+   pdiv = 1;
+   }
+   } else
+   pdiv = 1  cfg.p;
  
-	cfg.m *= 1  cfg.p;

+   cfg.m *= pdiv;
  
  	rate *= cfg.n;

do_div(rate, cfg.m);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 30bd3fd..54c6777 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -440,6 +440,12 @@ static struct tegra_clk_pll_params pll_d_params = {
.lock_delay = 1000,
  };
  
+static struct pdiv_map pllu_p[] = {

+   { .pdiv = 1, .hw_val = 1 },
+   { .pdiv = 2, .hw_val = 0 },
+   { .pdiv = 0, .hw_val = 0 },
+};
+
  static struct tegra_clk_pll_params pll_u_params = {
.input_min = 200,
.input_max = 4000,
@@ -452,6 +458,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+   .pdiv_tohw = pllu_p,
  };
  
  static struct tegra_clk_pll_params pll_x_params = {

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 28a2997..078f9b8 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -466,6 +466,12 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] 
= {
{ 0, 0, 0, 0, 0, 0 },
  };
  
+static struct pdiv_map pllu_p[] = {

+   { .pdiv = 1, .hw_val = 1 },
+   { .pdiv = 2, .hw_val = 0 },
+   { .pdiv = 0, .hw_val = 0 },
+};
+
  static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
{ 1200, 48000, 960, 12, 0, 12},
{ 1300, 48000, 960, 13, 0, 12},
@@ -639,6 +645,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+   .pdiv_tohw = pllu_p,
  };
  
  static struct tegra_clk_pll_params pll_x_params = {

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 3cff1df..1b9cbcd 100644

Re: [PATCH v5 05/10] clk: tegra: Add flags to tegra_clk_periph()

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---


Looks good to me.

Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


  drivers/clk/tegra/clk-periph.c  |   11 ++-
  drivers/clk/tegra/clk-tegra20.c |2 +-
  drivers/clk/tegra/clk-tegra30.c |2 +-
  drivers/clk/tegra/clk.h |9 ++---
  4 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 788486e..067abb3 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -170,14 +170,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
  static struct clk *_tegra_clk_register_periph(const char *name,
const char **parent_names, int num_parents,
struct tegra_clk_periph *periph,
-   void __iomem *clk_base, u32 offset, bool div)
+   void __iomem *clk_base, u32 offset, bool div,
+   unsigned long flags)
  {
struct clk *clk;
struct clk_init_data init;
  
  	init.name = name;

init.ops = div ? tegra_clk_periph_ops : tegra_clk_periph_nodiv_ops;
-   init.flags = div ? 0 : CLK_SET_RATE_PARENT;
+   init.flags = flags;
init.parent_names = parent_names;
init.num_parents = num_parents;
  
@@ -202,10 +203,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,

  struct clk *tegra_clk_register_periph(const char *name,
const char **parent_names, int num_parents,
struct tegra_clk_periph *periph, void __iomem *clk_base,
-   u32 offset)
+   u32 offset, unsigned long flags)
  {
return _tegra_clk_register_periph(name, parent_names, num_parents,
-   periph, clk_base, offset, true);
+   periph, clk_base, offset, true, flags);
  }
  
  struct clk *tegra_clk_register_periph_nodiv(const char *name,

@@ -214,5 +215,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char 
*name,
u32 offset)
  {
return _tegra_clk_register_periph(name, parent_names, num_parents,
-   periph, clk_base, offset, false);
+   periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
  }
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 54c6777..870349e 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1048,7 +1048,7 @@ static void __init tegra20_periph_clk_init(void)
data = tegra_periph_clk_list[i];
clk = tegra_clk_register_periph(data-name, data-parent_names,
data-num_parents, data-periph,
-   clk_base, data-offset);
+   clk_base, data-offset, data-flags);
clk_register_clkdev(clk, data-con_id, data-dev_id);
clks[data-clk_id] = clk;
}
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 078f9b8..126747b 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1665,7 +1665,7 @@ static void __init tegra30_periph_clk_init(void)
data = tegra_periph_clk_list[i];
clk = tegra_clk_register_periph(data-name, data-parent_names,
data-num_parents, data-periph,
-   clk_base, data-offset);
+   clk_base, data-offset, data-flags);
clk_register_clkdev(clk, data-con_id, data-dev_id);
clks[data-clk_id] = clk;
}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 4d0f556..79f5e2a 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -411,7 +411,7 @@ extern const struct clk_ops tegra_clk_periph_ops;
  struct clk *tegra_clk_register_periph(const char *name,
const char **parent_names, int num_parents,
struct tegra_clk_periph *periph, void __iomem *clk_base,
-   u32 offset);
+   u32 offset, unsigned long flags);
  struct clk *tegra_clk_register_periph_nodiv(const char *name,
const char **parent_names, int num_parents,
struct tegra_clk_periph *periph, void __iomem *clk_base,
@@ -454,12 +454,14 @@ struct tegra_periph_init_data {
u32 offset;
const char *con_id;
const char *dev_id;
+   unsigned long flags;
  };
  
  #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\

_mux_shift, _mux_mask, _mux_flags, _div_shift,  \
_div_width, _div_frac_width, _div_flags, _regs

Re: [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114

[Prashant Gaikwad]

On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote:

On 2/1/2013 5:18 AM, Peter De Schrijver wrote:

Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
   drivers/clk/tegra/clk-pll.c |  719 
+++
   drivers/clk/tegra/clk.h |   47 +++
   2 files changed, 766 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 87d2f34..50114b7 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
[snip]
+struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
+ void __iomem *clk_base, void __iomem *pmc,
+ unsigned long flags, unsigned long fixed_rate,
+ struct tegra_clk_pll_params *pll_params,
+ u32 pll_flags,
+ struct tegra_clk_pll_freq_table *freq_table,
+ spinlock_t *lock)
+{
+   if (!pll_params-pdiv_tohw)
+   return -EINVAL;
+

This will cause the following warning:
warning: return makes pointer from integer without a cast

Same with occurrences in tegra_clk_register_pllm and
tegra_clk_register_pllc.

Should this instead be returning NULL?


return ERR_PTR(-EINVAL)



-rhyland



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Re: [PATCH v5 06/10] clk: tegra: Workaround for Tegra114 MSENC problem

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Workaround a hardware bug in MSENC during clock enable.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
  drivers/clk/tegra/clk-periph-gate.c |9 +
  drivers/clk/tegra/clk.h |1 +
  2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph-gate.c 
b/drivers/clk/tegra/clk-periph-gate.c
index 6dd5332..c9083fb 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -43,6 +43,8 @@ static DEFINE_SPINLOCK(periph_ref_lock);
  
  #define periph_clk_to_bit(periph) (1  (gate-clk_num % 32))
  
+#define LVL2_CLK_GATE_OVRE 0x554

+
  /* Peripheral gate clock ops */
  static int clk_periph_is_enabled(struct clk_hw *hw)
  {
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
}
}
  
+	if (gate-flags  TEGRA_PERIPH_WAR_1005168) {

+   writel_relaxed(0, gate-clk_base + LVL2_CLK_GATE_OVRE);
+   writel_relaxed(BIT(22), gate-clk_base + LVL2_CLK_GATE_OVRE);
+   udelay(1);
+   writel_relaxed(0, gate-clk_base + LVL2_CLK_GATE_OVRE);
+   }
+
spin_unlock_irqrestore(periph_ref_lock, flags);
  
  	return 0;

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 79f5e2a..8756d9f 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -371,6 +371,7 @@ struct tegra_clk_periph_gate {
  #define TEGRA_PERIPH_NO_RESET BIT(0)
  #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
  #define TEGRA_PERIPH_ON_APB BIT(2)
+#define TEGRA_PERIPH_WAR_1005168 BIT(3)
  


Comment for this flag, otherwise

Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


  void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
  extern const struct clk_ops tegra_clk_periph_gate_ops;



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Re: [PATCH v5 08/10] ARM: dt: Add references to tegra_car clocks

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Add references to tegra_car clocks for the basic device nodes.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---


Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


  arch/arm/boot/dts/tegra114.dtsi |7 ++-
  1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 96a8235..1dec620 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -27,7 +27,7 @@
};
  
  	tegra_car: clock {

-   compatible = nvidia,tegra114-car, nvidia,tegra30-car;
+   compatible = nvidia,tegra114-car;
reg = 0x60006000 0x1000;
#clock-cells = 1;
};
@@ -43,6 +43,7 @@
reg-shift = 2;
interrupts = 0 36 0x04;
status = disabled;
+   clocks = tegra_car 6;
};
  
  	serial@70006040 {

@@ -51,6 +52,7 @@
reg-shift = 2;
interrupts = 0 37 0x04;
status = disabled;
+   clocks = tegra_car 192;
};
  
  	serial@70006200 {

@@ -59,6 +61,7 @@
reg-shift = 2;
interrupts = 0 46 0x04;
status = disabled;
+   clocks = tegra_car 55;
};
  
  	serial@70006300 {

@@ -67,12 +70,14 @@
reg-shift = 2;
interrupts = 0 90 0x04;
status = disabled;
+   clocks = tegra_car 65;
};
  
  	rtc {

compatible = nvidia,tegra114-rtc, nvidia,tegra20-rtc;
reg = 0x7000e000 0x100;
interrupts = 0 2 0x04;
+   clocks = tegra_car 4;
};
  
  	pmc {




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Re: [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Implement most clocks for Tegra114. The super clocks for the CPU complex
are still missing and will be implemented in a future version.

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
  drivers/clk/tegra/Makefile   |1 +
  drivers/clk/tegra/clk-tegra114.c | 2002 ++
  2 files changed, 2003 insertions(+), 0 deletions(-)
  create mode 100644 drivers/clk/tegra/clk-tegra114.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 2b41b0f..f49fac2 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -9,3 +9,4 @@ obj-y   += clk-super.o

  obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
  obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)   += clk-tegra114.o
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
new file mode 100644
index 000..f8165d2
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -0,0 +1,2002 @@
+/*
+ * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/io.h
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/delay.h
+#include linux/clk/tegra.h
+
+#include clk.h
+
+#define RST_DEVICES_L  0x004
+#define RST_DEVICES_H  0x008
+#define RST_DEVICES_U  0x00C
+#define RST_DEVICES_V  0x358
+#define RST_DEVICES_W  0x35C
+#define RST_DEVICES_X  0x28C
+#define RST_DEVICES_SET_L  0x300
+#define RST_DEVICES_CLR_L  0x304
+#define RST_DEVICES_SET_H  0x308
+#define RST_DEVICES_CLR_H  0x30c
+#define RST_DEVICES_SET_U  0x310
+#define RST_DEVICES_CLR_U  0x314
+#define RST_DEVICES_SET_V  0x430
+#define RST_DEVICES_CLR_V  0x434
+#define RST_DEVICES_SET_W  0x438
+#define RST_DEVICES_CLR_W  0x43c
+#define RST_DEVICES_NUM5


RST_DEVICES_SET/CLR_X?


+
+#define CLK_OUT_ENB_L  0x010
+#define CLK_OUT_ENB_H  0x014
+#define CLK_OUT_ENB_U  0x018
+#define CLK_OUT_ENB_V  0x360
+#define CLK_OUT_ENB_W  0x364
+#define CLK_OUT_ENB_X  0x280
+#define CLK_OUT_ENB_SET_L  0x320
+#define CLK_OUT_ENB_CLR_L  0x324
+#define CLK_OUT_ENB_SET_H  0x328
+#define CLK_OUT_ENB_CLR_H  0x32c
+#define CLK_OUT_ENB_SET_U  0x330
+#define CLK_OUT_ENB_CLR_U  0x334
+#define CLK_OUT_ENB_SET_V  0x440
+#define CLK_OUT_ENB_CLR_V  0x444
+#define CLK_OUT_ENB_SET_W  0x448
+#define CLK_OUT_ENB_CLR_W  0x44c
+#define CLK_OUT_ENB_SET_X  0x284
+#define CLK_OUT_ENB_CLR_X  0x288
+#define CLK_OUT_ENB_NUM6


snip


+
+   /* dsia */
+   clk = clk_register_mux(NULL, dsia_mux, mux_plld_out0_plld2_out0,
+  ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+  clk_base + PLLD_BASE, 25, 1, 0, pll_d_lock);
+   clks[dsia_mux] = clk;
+   clk = tegra_clk_register_periph_gate(dsia, dsia_mux, 0, clk_base,
+   0, 48, periph_h_regs,
+   periph_clk_enb_refcnt);
+   clk_register_clkdev(clk, dsia, tegradc.0);
+   clks[dsia] = clk;
+
+   /* dsib */
+   clk = clk_register_mux(NULL, dsib_mux, mux_plld_out0_plld2_out0,
+  ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+  clk_base + PLLD2_BASE, 25, 1, 0, pll_d2_lock);
+   clks[dsib_mux] = clk;
+   clk = tegra_clk_register_periph_gate(dsib, dsib_mux, 0, clk_base,
+   0, 82, periph_u_regs,
+   periph_clk_enb_refcnt);
+   clk_register_clkdev(clk, dsib, tegradc.1);
+   clks[dsib] = clk;
+


Can we use periph no div clock here for dsia and dsib?


+   /* xusb_hs_src */
+   val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+   val |= BIT(25); /* always select PLLU_60M 

Re: [PATCH v5 10/10] clk: tegra: devicetree match for nvidia,tegra114-car

[Prashant Gaikwad]

On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:

Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---


Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com


  drivers/clk/tegra/clk.c |1 +
  drivers/clk/tegra/clk.h |7 +++
  2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a603b9a..a328365 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -76,6 +76,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table 
*tbl,
  static const struct of_device_id tegra_dt_clk_match[] = {
{ .compatible = nvidia,tegra20-car, .data = tegra20_clock_init },
{ .compatible = nvidia,tegra30-car, .data = tegra30_clock_init },
+   { .compatible = nvidia,tegra114-car, .data = tegra114_clock_init },
{ }
  };
  
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h

index 8756d9f..8097850 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -576,4 +576,11 @@ void tegra30_clock_init(struct device_node *np);
  static inline void tegra30_clock_init(struct device_node *np) {}
  #endif /* CONFIG_ARCH_TEGRA_3x_SOC */
  
+#ifdef CONFIG_ARCH_TEGRA_114_SOC

+void tegra114_clock_init(struct device_node *np);
+#else
+static inline void tegra114_clock_init(struct device_node *np) {}
+#endif /* CONFIG_ARCH_TEGRA114_SOC */
+
+
  #endif /* TEGRA_CLK_H */



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Re: [PATCH 2/7] clk: tegra: Use common of_clk_init() function

[Prashant Gaikwad]

On Friday 25 January 2013 10:14 AM, Stephen Warren wrote:

On 01/24/2013 04:57 PM, Mike Turquette wrote:

Quoting Stephen Warren (2013-01-24 11:32:37)

On 01/24/2013 11:20 AM, Mike Turquette wrote:

Quoting Prashant Gaikwad (2013-01-04 18:44:48)

On Friday 04 January 2013 10:00 PM, Stephen Warren wrote:

On 01/04/2013 12:00 AM, Prashant Gaikwad wrote:

Use common of_clk_init() function for clocks initialization.
   drivers/clk/tegra/clk-tegra20.c |3 ++-
   drivers/clk/tegra/clk-tegra30.c |3 ++-

Oh, so this series is written assuming that the Tegra CCF rework is
already applied then? That makes the dependencies quite painful, since I
think we'll end up with the following order being needed:

1) clk: Add composite clock type
 -> This would usually go through the clk tree.
2) The Tegra CCF rework series
 -> This must go through the Tegra tree due to lots of dependencies
 and merge conflicts with other Tegra patches.
3) This series
 -> This would usually go through the clk tree.

Is it possible to re-order the dependencies as (1) (3) (2), so that Mike
can apply (1) and (3) to the clock tree, then I can use the clk tree as
the basis for a branch in the Tegra tree to apply (2) and all the other
Tegra patches that will conflict with (2)?

If Mike approves the concept and implementation in (1) and (3) then I
will repost (2) and (3) with dependencies re-ordered.

Patch (1) still has some unaddressed comments, and is not a real
dependency for this series.

I assume "Patch (1)" refers to the list of series a couple emails above,
not the first patch in the series you're replying to; that threw me for
a moment.


Since all of the patches have received their
Tested-by's then I propose to merge all patches from this series into
clk-next, which exception of patch 2/7 (the Tegra patch).

This reduces your Tegra CCF conversion dependencies and you can role the
necessary of_clk_init change into your Tegra CCF conversion branch (it
has my implicit Ack and can be taken through your tree).

Let me know if this is OK for you.

OK, I'm happy to merge your clock tree into the Tegra tree and then
apply 2/7 on top of the Tegra CCF work.

Hmm, maybe the clk tree needs to be a dependency branch of arm-soc
again, as it has in the past.  Would that help with any Tegra merge
pain?

Yes, I think that's what would end up happening if I merge the clk tree
into the Tegra tree anyway.


Hi Mike,

Have you merged these patches for 3.9?


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Re: [PATCH 2/7] clk: tegra: Use common of_clk_init() function

[Prashant Gaikwad]

On Friday 25 January 2013 10:14 AM, Stephen Warren wrote:

On 01/24/2013 04:57 PM, Mike Turquette wrote:

Quoting Stephen Warren (2013-01-24 11:32:37)

On 01/24/2013 11:20 AM, Mike Turquette wrote:

Quoting Prashant Gaikwad (2013-01-04 18:44:48)

On Friday 04 January 2013 10:00 PM, Stephen Warren wrote:

On 01/04/2013 12:00 AM, Prashant Gaikwad wrote:

Use common of_clk_init() function for clocks initialization.
   drivers/clk/tegra/clk-tegra20.c |3 ++-
   drivers/clk/tegra/clk-tegra30.c |3 ++-

Oh, so this series is written assuming that the Tegra CCF rework is
already applied then? That makes the dependencies quite painful, since I
think we'll end up with the following order being needed:

1) clk: Add composite clock type
 - This would usually go through the clk tree.
2) The Tegra CCF rework series
 - This must go through the Tegra tree due to lots of dependencies
 and merge conflicts with other Tegra patches.
3) This series
 - This would usually go through the clk tree.

Is it possible to re-order the dependencies as (1) (3) (2), so that Mike
can apply (1) and (3) to the clock tree, then I can use the clk tree as
the basis for a branch in the Tegra tree to apply (2) and all the other
Tegra patches that will conflict with (2)?

If Mike approves the concept and implementation in (1) and (3) then I
will repost (2) and (3) with dependencies re-ordered.

Patch (1) still has some unaddressed comments, and is not a real
dependency for this series.

I assume Patch (1) refers to the list of series a couple emails above,
not the first patch in the series you're replying to; that threw me for
a moment.


Since all of the patches have received their
Tested-by's then I propose to merge all patches from this series into
clk-next, which exception of patch 2/7 (the Tegra patch).

This reduces your Tegra CCF conversion dependencies and you can role the
necessary of_clk_init change into your Tegra CCF conversion branch (it
has my implicit Ack and can be taken through your tree).

Let me know if this is OK for you.

OK, I'm happy to merge your clock tree into the Tegra tree and then
apply 2/7 on top of the Tegra CCF work.

Hmm, maybe the clk tree needs to be a dependency branch of arm-soc
again, as it has in the past.  Would that help with any Tegra merge
pain?

Yes, I think that's what would end up happening if I merge the clk tree
into the Tegra tree anyway.


Hi Mike,

Have you merged these patches for 3.9?


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[PATCH v4 4/9] ARM: tegra: Define Tegra20 CAR binding

[Prashant Gaikwad]

From: Stephen Warren 

The Tegra20 CAR (Clock And Reset) Controller controls most aspects of
most clocks within Tegra20. The device tree binding models this as a
single monolithic clock provider, which exports many clocks. This reduces
the number of nodes needed in device tree to represent these clocks.

This binding is only useful for Tegra20; the set of clocks that exists on
Tegra30 is sufficiently different to merit its own binding.

Signed-off-by: Stephen Warren 
Acked-by: Simon Glass 
[pgaikwad: Added mux clk ids and sorted CAR node]
Signed-off-by: Prashant Gaikwad 
---
 .../bindings/clock/nvidia,tegra20-car.txt  |  205 
 arch/arm/boot/dts/tegra20.dtsi |6 +
 2 files changed, 211 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt 
b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
new file mode 100644
index 000..0921fac
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -0,0 +1,205 @@
+NVIDIA Tegra20 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be "nvidia,tegra20-car"
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+  the 32 KHz "32k_in", and the board-specific oscillator "osc".
+- #clock-cells : Should be 1.
+  In clock consumers, this cell represents the clock ID exposed by the CAR.
+
+  The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  registers. These IDs often match those in the CAR's RST_DEVICES registers,
+  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+  this case, those clocks are assigned IDs above 95 in order to highlight
+  this issue. Implementations that interpret these clock IDs as bit values
+  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+  explicitly handle these special cases.
+
+  The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+  above.
+
+  0cpu
+  1unassigned
+  2unassigned
+  3ac97
+  4rtc
+  5tmr
+  6uart1
+  7unassigned  (register bit affects uart2 and vfir)
+  8gpio
+  9sdmmc2
+  10   unassigned  (register bit affects spdif_in and spdif_out)
+  11   i2s1
+  12   i2c1
+  13   ndflash
+  14   sdmmc1
+  15   sdmmc4
+  16   twc
+  17   pwm
+  18   i2s2
+  19   epp
+  20   unassigned  (register bit affects vi and vi_sensor)
+  21   2d
+  22   usbd
+  23   isp
+  24   3d
+  25   ide
+  26   disp2
+  27   disp1
+  28   host1x
+  29   vcp
+  30   unassigned
+  31   cache2
+
+  32   mem
+  33   ahbdma
+  34   apbdma
+  35   unassigned
+  36   kbc
+  37   stat_mon
+  38   pmc
+  39   fuse
+  40   kfuse
+  41   sbc1
+  42   snor
+  43   spi1
+  44   sbc2
+  45   xio
+  46   sbc3
+  47   dvc
+  48   dsi
+  49   unassigned  (register bit affects tvo and cve)
+  50   mipi
+  51   hdmi
+  52   csi
+  53   tvdac
+  54   i2c2
+  55   uart3
+  56   unassigned
+  57   emc
+  58   usb2
+  59   usb3
+  60   mpe
+  61   vde
+  62   bsea
+  63   bsev
+
+  64   speedo
+  65   uart4
+  66   uart5
+  67   i2c3
+  68   sbc4
+  69   sdmmc3
+  70   pcie
+  71   owr
+  72   afi
+  73   csite
+  74   unassigned
+  75   avpucq
+  76   la
+  77   unassigned
+  78   unassigned
+  79   unassigned
+  80   unassigned
+  81   unassigned
+  82   unassigned
+  83   unassigned
+  84   irama
+  85   iramb
+  86   iramc
+  87   iramd
+  88   cram2
+  89   audio_2xa/k/a audio_2x_sync_clk
+  90   clk_d
+  91   unassigned
+  92   sus
+  93   cdev1
+  94   cdev2
+  95   unassigned
+
+  96   uart2
+  97   vfir
+  98   spdif_in
+  99   spdif_out
+  100  vi
+  101  vi_sensor
+  102  tvo
+  103  cve
+  104  osc
+  105  clk_32k a/k/a clk_s
+  106  clk_m
+  107  sclk
+  108  cclk
+  109  hclk
+  110  pclk
+  111  blink
+  112  pll_a
+  113  pll_a_out0
+  114  pll_c
+  115  pll_c_out1
+  116  pll_d
+  117  pll_d_out0
+  118  pll_e
+  119  pll_m
+  120  pll_m_out1
+  121  pll_p
+  122  pll_p_out1
+  123  pll_p_out2
+  124  pll_p_out3
+  125  pll_p_out4
+  126  pll_s
+  127  pll_u
+  128  pll_x
+  129  cop a/k/a avp
+  130  audio   a/k/a audio_sync_clk
+  131  pll_ref
+  132  twd
+
+Example SoC include file:
+
+/ {
+   tegra_car: clock {
+   compatible = "nvidia,tegra20-car";
+   reg = <0x60006000 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   usb@c5004000 {
+   clocks = <_car 58>; /* usb2 */
+   };
+};
+
+Example boar

[PATCH v4 6/9] clk: tegra: add clock support for tegra20

[Prashant Gaikwad]

Add tegra20 clock support based on common clock framework.

Signed-off-by: Prashant Gaikwad 
---
 drivers/clk/tegra/Makefile  |2 +
 drivers/clk/tegra/clk-tegra20.c | 1255 +++
 drivers/clk/tegra/clk.h |6 +
 3 files changed, 1263 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/tegra/clk-tegra20.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 68bd353..00484fd 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -6,3 +6,5 @@ obj-y   += clk-periph-gate.o
 obj-y  += clk-pll.o
 obj-y  += clk-pll-out.o
 obj-y  += clk-super.o
+
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
new file mode 100644
index 000..4875261
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -0,0 +1,1255 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define RST_DEVICES_L 0x004
+#define RST_DEVICES_H 0x008
+#define RST_DEVICES_U 0x00c
+#define RST_DEVICES_SET_L 0x300
+#define RST_DEVICES_CLR_L 0x304
+#define RST_DEVICES_SET_H 0x308
+#define RST_DEVICES_CLR_H 0x30c
+#define RST_DEVICES_SET_U 0x310
+#define RST_DEVICES_CLR_U 0x314
+#define RST_DEVICES_NUM 3
+
+#define CLK_OUT_ENB_L 0x010
+#define CLK_OUT_ENB_H 0x014
+#define CLK_OUT_ENB_U 0x018
+#define CLK_OUT_ENB_SET_L 0x320
+#define CLK_OUT_ENB_CLR_L 0x324
+#define CLK_OUT_ENB_SET_H 0x328
+#define CLK_OUT_ENB_CLR_H 0x32c
+#define CLK_OUT_ENB_SET_U 0x330
+#define CLK_OUT_ENB_CLR_U 0x334
+#define CLK_OUT_ENB_NUM 3
+
+#define OSC_CTRL 0x50
+#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
+#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
+#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
+#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
+#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
+
+#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
+#define OSC_CTRL_PLL_REF_DIV_1 (0<<28)
+#define OSC_CTRL_PLL_REF_DIV_2 (1<<28)
+#define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
+
+#define OSC_FREQ_DET 0x58
+#define OSC_FREQ_DET_TRIG (1<<31)
+
+#define OSC_FREQ_DET_STATUS 0x5c
+#define OSC_FREQ_DET_BUSY (1<<31)
+#define OSC_FREQ_DET_CNT_MASK 0x
+
+#define PLLS_BASE 0xf0
+#define PLLS_MISC 0xf4
+#define PLLC_BASE 0x80
+#define PLLC_MISC 0x8c
+#define PLLM_BASE 0x90
+#define PLLM_MISC 0x9c
+#define PLLP_BASE 0xa0
+#define PLLP_MISC 0xac
+#define PLLA_BASE 0xb0
+#define PLLA_MISC 0xbc
+#define PLLU_BASE 0xc0
+#define PLLU_MISC 0xcc
+#define PLLD_BASE 0xd0
+#define PLLD_MISC 0xdc
+#define PLLX_BASE 0xe0
+#define PLLX_MISC 0xe4
+#define PLLE_BASE 0xe8
+#define PLLE_MISC 0xec
+
+#define PLL_BASE_LOCK 27
+#define PLLE_MISC_LOCK 11
+
+#define PLL_MISC_LOCK_ENABLE 18
+#define PLLDU_MISC_LOCK_ENABLE 22
+#define PLLE_MISC_LOCK_ENABLE 9
+
+#define PLLC_OUT 0x84
+#define PLLM_OUT 0x94
+#define PLLP_OUTA 0xa4
+#define PLLP_OUTB 0xa8
+#define PLLA_OUT 0xb4
+
+#define CCLK_BURST_POLICY 0x20
+#define SUPER_CCLK_DIVIDER 0x24
+#define SCLK_BURST_POLICY 0x28
+#define SUPER_SCLK_DIVIDER 0x2c
+#define CLK_SYSTEM_RATE 0x30
+
+#define CLK_SOURCE_I2S1 0x100
+#define CLK_SOURCE_I2S2 0x104
+#define CLK_SOURCE_SPDIF_OUT 0x108
+#define CLK_SOURCE_SPDIF_IN 0x10c
+#define CLK_SOURCE_PWM 0x110
+#define CLK_SOURCE_SPI 0x114
+#define CLK_SOURCE_SBC1 0x134
+#define CLK_SOURCE_SBC2 0x118
+#define CLK_SOURCE_SBC3 0x11c
+#define CLK_SOURCE_SBC4 0x1b4
+#define CLK_SOURCE_XIO 0x120
+#define CLK_SOURCE_TWC 0x12c
+#define CLK_SOURCE_IDE 0x144
+#define CLK_SOURCE_NDFLASH 0x160
+#define CLK_SOURCE_VFIR 0x168
+#define CLK_SOURCE_SDMMC1 0x150
+#define CLK_SOURCE_SDMMC2 0x154
+#define CLK_SOURCE_SDMMC3 0x1bc
+#define CLK_SOURCE_SDMMC4 0x164
+#define CLK_SOURCE_CVE 0x140
+#define CLK_SOURCE_TVO 0x188
+#define CLK_SOURCE_TVDAC 0x194
+#define CLK_SOURCE_HDMI 0x18c
+#define CLK_SOURCE_DISP1 0x138
+#define CLK_SOURCE_DISP2 0x13c
+#define CLK_SOURCE_CSITE 0x1d4
+#define CLK_SOURCE_LA 0x1f8
+#define CLK_SOURCE_OWR 0x1cc
+#define CLK_SOURCE_NOR 0x1d0
+#define CLK_SOURCE_MIPI 0x174
+#define C

[PATCH v4 3/9] arm: tegra: Move tegra_cpu_car.h to linux/clk/tegra.h

[Prashant Gaikwad]

tegra_cpu_car_ops struct is going to be accessed from drivers/clk/tegra.
Move the tegra_cpu_car_ops to include/linux/clk/tegra.h.

Signed-off-by: Prashant Gaikwad 
---
 arch/arm/mach-tegra/clock.c|2 +-
 arch/arm/mach-tegra/cpuidle-tegra30.c  |2 +-
 arch/arm/mach-tegra/hotplug.c  |2 +-
 arch/arm/mach-tegra/platsmp.c  |2 +-
 arch/arm/mach-tegra/pm.c   |2 +-
 arch/arm/mach-tegra/tegra20_clocks.c   |2 +-
 arch/arm/mach-tegra/tegra20_clocks_data.c  |2 +-
 arch/arm/mach-tegra/tegra30_clocks.c   |2 +-
 arch/arm/mach-tegra/tegra30_clocks_data.c  |2 +-
 .../tegra_cpu_car.h => include/linux/clk/tegra.h   |6 +++---
 10 files changed, 12 insertions(+), 12 deletions(-)
 rename arch/arm/mach-tegra/tegra_cpu_car.h => include/linux/clk/tegra.h (96%)

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 867bf8b..8c0ff06 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -26,10 +26,10 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "board.h"
 #include "clock.h"
-#include "tegra_cpu_car.h"
 
 /* Global data of Tegra CPU CAR ops */
 struct tegra_cpu_car_ops *tegra_cpu_car_ops;
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c 
b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 82530bd..8b50cf4 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -32,7 +33,6 @@
 
 #include "pm.h"
 #include "sleep.h"
-#include "tegra_cpu_car.h"
 
 #ifdef CONFIG_PM_SLEEP
 static int tegra30_idle_lp2(struct cpuidle_device *dev,
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 6a27de4..a599f6e 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -10,12 +10,12 @@
  */
 #include 
 #include 
+#include 
 
 #include 
 #include 
 
 #include "sleep.h"
-#include "tegra_cpu_car.h"
 
 static void (*tegra_hotplug_shutdown)(void);
 
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 6867030..3ec7fc4 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -30,7 +31,6 @@
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
-#include "tegra_cpu_car.h"
 
 #include "common.h"
 #include "iomap.h"
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 498d70b..abfe9b9 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -36,7 +37,6 @@
 #include "reset.h"
 #include "flowctrl.h"
 #include "sleep.h"
-#include "tegra_cpu_car.h"
 
 #define TEGRA_POWER_CPU_PWRREQ_OE  (1 << 16)  /* CPU pwr req enable */
 
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c 
b/arch/arm/mach-tegra/tegra20_clocks.c
index 4eb6bc8..1a80ff6 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -26,12 +26,12 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "clock.h"
 #include "fuse.h"
 #include "iomap.h"
 #include "tegra2_emc.h"
-#include "tegra_cpu_car.h"
 
 #define RST_DEVICES0x004
 #define RST_DEVICES_SET0x300
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c 
b/arch/arm/mach-tegra/tegra20_clocks_data.c
index a23a073..022cdae 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -26,12 +26,12 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "clock.h"
 #include "fuse.h"
 #include "tegra2_emc.h"
 #include "tegra20_clocks.h"
-#include "tegra_cpu_car.h"
 
 /* Clock definitions */
 
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c 
b/arch/arm/mach-tegra/tegra30_clocks.c
index d714777..4330787 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -36,7 +37,6 @@
 #include "clock.h"
 #include "fuse.h"
 #include "iomap.h"
-#include "tegra_cpu_car.h"
 
 #define USE_PLL_LOCK_BITS 0
 
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c 
b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 741d264..9bfaa49 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -28,11 +28,11 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "clock.h&quo

[PATCH v4 8/9] arm: tegra: Migrate to new clock code

[Prashant Gaikwad]

Migrate tegra clock support to drivers/clk/tegra, this involves
moving
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h

Signed-off-by: Prashant Gaikwad 
---
 arch/arm/mach-tegra/board-dt-tegra20.c |   30 -
 arch/arm/mach-tegra/board-dt-tegra30.c |   31 --
 arch/arm/mach-tegra/clock.c|   19 -
 arch/arm/mach-tegra/common.c   |   44 +--
 arch/arm/mach-tegra/cpu-tegra.c|2 +-
 arch/arm/mach-tegra/include/mach/clk.h |3 --
 arch/arm/mach-tegra/pcie.c |2 +-
 arch/arm/mach-tegra/powergate.c|2 +-
 drivers/clk/tegra/clk-periph.c |   38 +++
 drivers/clk/tegra/clk.c|   16 +++
 drivers/dma/tegra20-apb-dma.c  |2 +-
 drivers/gpu/drm/tegra/dc.c |3 +-
 drivers/gpu/drm/tegra/drm.c|1 -
 drivers/gpu/drm/tegra/hdmi.c   |3 +-
 drivers/i2c/busses/i2c-tegra.c |3 +-
 drivers/input/keyboard/tegra-kbc.c |2 +-
 drivers/spi/spi-tegra20-sflash.c   |2 +-
 drivers/spi/spi-tegra20-slink.c|2 +-
 drivers/staging/nvec/nvec.c|3 +-
 include/linux/clk/tegra.h  |5 +++
 sound/soc/tegra/tegra30_ahub.c |2 +-
 21 files changed, 73 insertions(+), 142 deletions(-)

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c 
b/arch/arm/mach-tegra/board-dt-tegra20.c
index e1f87dd..0c11b8a 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -42,7 +42,6 @@
 #include 
 
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "iomap.h"
 
@@ -104,37 +103,8 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] 
__initdata = {
{}
 };
 
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-   /* name parent  rateenabled */
-   { "uarta",  "pll_p",21600,  true },
-   { "uartd",  "pll_p",21600,  true },
-   { "usbd",   "clk_m",1200,   false },
-   { "usb2",   "clk_m",1200,   false },
-   { "usb3",   "clk_m",1200,   false },
-   { "pll_a",  "pll_p_out1",   56448000,   true },
-   { "pll_a_out0", "pll_a",11289600,   true },
-   { "cdev1",  NULL,   0,  true },
-   { "blink",  "clk_32k",  32768,  true },
-   { "i2s1",   "pll_a_out0",   11289600,   false},
-   { "i2s2",   "pll_a_out0",   11289600,   false},
-   { "sdmmc1", "pll_p",4800,   false},
-   { "sdmmc3", "pll_p",4800,   false},
-   { "sdmmc4", "pll_p",4800,   false},
-   { "spi","pll_p",2000,   false },
-   { "sbc1",   "pll_p",1,  false },
-   { "sbc2",   "pll_p",1,  false },
-   { "sbc3",   "pll_p",1,  false },
-   { "sbc4",   "pll_p",1,  false },
-   { "host1x", "pll_c",15000,  false },
-   { "disp1",  "pll_p",6,  false },
-   { "disp2",  "pll_p",6,  false },
-   { NULL, NULL,   0,  0},
-};
-
 static void __init tegra_dt_init(void)
 {
-   tegra_clk_init_from_table(tegra_dt_clk_init_table);
-
/*
 * Finished with the static registrations now; fill in the missing
 * devices
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c 
b/arch/arm/mach-tegra/board-dt-tegra30.c
index cfe5fc0..92f6014 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -35,7 +35,6 @@
 #include 
 
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "iomap.h"
 
@@ -67,38 +66,8 @@ static struct of_dev_auxdata tegra30_auxdata_lookup[] 
__initdata = {
{}
 };
 
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-   /* name parent  rateenabled */
-   { "uarta",  "pll_p",408

[PATCH v4 5/9] ARM: Tegra: Define Tegra30 CAR binding

[Prashant Gaikwad]

The device tree binding models Tegra30 CAR (Clock And Reset)
as a single monolithic clock provider.

Signed-off-by: Prashant Gaikwad 
---
 .../bindings/clock/nvidia,tegra30-car.txt  |  262 
 arch/arm/boot/dts/tegra30.dtsi |6 +
 2 files changed, 268 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt 
b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
new file mode 100644
index 000..121d203
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -0,0 +1,262 @@
+NVIDIA Tegra30 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be "nvidia,tegra30-car"
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+  the 32 KHz "32k_in", and the board-specific oscillator "osc".
+- #clock-cells : Should be 1.
+  In clock consumers, this cell represents the clock ID exposed by the CAR.
+
+  The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  registers. These IDs often match those in the CAR's RST_DEVICES registers,
+  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+  this case, those clocks are assigned IDs above 160 in order to highlight
+  this issue. Implementations that interpret these clock IDs as bit values
+  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+  explicitly handle these special cases.
+
+  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+  above.
+
+  0cpu
+  1unassigned
+  2unassigned
+  3unassigned
+  4rtc
+  5timer
+  6uarta
+  7unassigned  (register bit affects uartb and vfir)
+  8gpio
+  9sdmmc2
+  10   unassigned  (register bit affects spdif_in and spdif_out)
+  11   i2s1
+  12   i2c1
+  13   ndflash
+  14   sdmmc1
+  15   sdmmc4
+  16   unassigned
+  17   pwm
+  18   i2s2
+  19   epp
+  20   unassigned  (register bit affects vi and vi_sensor)
+  21   2d
+  22   usbd
+  23   isp
+  24   3d
+  25   unassigned
+  26   disp2
+  27   disp1
+  28   host1x
+  29   vcp
+  30   i2s0
+  31   cop_cache
+
+  32   mc
+  33   ahbdma
+  34   apbdma
+  35   unassigned
+  36   kbc
+  37   statmon
+  38   pmc
+  39   unassigned  (register bit affects fuse and fuse_burn)
+  40   kfuse
+  41   sbc1
+  42   nor
+  43   unassigned
+  44   sbc2
+  45   unassigned
+  46   sbc3
+  47   i2c5
+  48   dsia
+  49   unassigned  (register bit affects cve and tvo)
+  50   mipi
+  51   hdmi
+  52   csi
+  53   tvdac
+  54   i2c2
+  55   uartc
+  56   unassigned
+  57   emc
+  58   usb2
+  59   usb3
+  60   mpe
+  61   vde
+  62   bsea
+  63   bsev
+
+  64   speedo
+  65   uartd
+  66   uarte
+  67   i2c3
+  68   sbc4
+  69   sdmmc3
+  70   pcie
+  71   owr
+  72   afi
+  73   csite
+  74   pciex
+  75   avpucq
+  76   la
+  77   unassigned
+  78   unassigned
+  79   dtv
+  80   ndspeed
+  81   i2cslow
+  82   dsib
+  83   unassigned
+  84   irama
+  85   iramb
+  86   iramc
+  87   iramd
+  88   cram2
+  89   unassigned
+  90   audio_2xa/k/a audio_2x_sync_clk
+  91   unassigned
+  92   csus
+  93   cdev2
+  94   cdev1
+  95   unassigned
+
+  96   cpu_g
+  97   cpu_lp
+  98   3d2
+  99   mselect
+  100  tsensor
+  101  i2s3
+  102  i2s4
+  103  i2c4
+  104  sbc5
+  105  sbc6
+  106  d_audio
+  107  apbif
+  108  dam0
+  109  dam1
+  110  dam2
+  111  hda2codec_2x
+  112  atomics
+  113  audio0_2x
+  114  audio1_2x
+  115  audio2_2x
+  116  audio3_2x
+  117  audio4_2x
+  118  audio5_2x
+  119  actmon
+  120  extern1
+  121  extern2
+  122  extern3
+  123  sata_oob
+  124  sata
+  125  hda
+  127  se
+  128  hda2hdmi
+  129  sata_cold
+
+  160  uartb
+  161  vfir
+  162  spdif_in
+  163  spdif_out
+  164  vi
+  165  vi_sensor
+  166  fuse
+  167  fuse_burn
+  168  cve
+  169  tvo
+
+  170  clk_32k
+  171  clk_m
+  172  clk_m_div2
+  173  clk_m_div4
+  174  pll_ref
+  175  pll_c
+  176  pll_c_out1
+  177  pll_m
+  178  pll_m_out1
+  179  pll_p
+  180  pll_p_out1
+  181  pll_p_out2
+  182  pll_p_out3
+  183  pll_p_out4
+  184  pll_a
+  185  pll_a_out0
+  186  pll_d
+  187  pll_d_out0
+  188  pll_d2
+  189  pll_d2_out0
+  190  pll_u
+  191  pll_x
+  192  pll_x_out0
+  193  pll_e
+  194  spdif_in_sync
+  195  i2s0_sync
+  196  i2s1_sync
+  197  i2s2_sync
+  198  i2s3_sync
+  199  i2s4_sync
+  200  vimclk
+  201  audio0
+  202  audio1
+  203  audio2
+  204  audio3
+  205  audio4
+  206  audio5
+  207  clk_out_1 (extern1)
+  208  clk_out_2 (extern2)
+  209  cl

[PATCH v4 0/9] Migrate Tegra to common clock framework

[Prashant Gaikwad]

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Tested on Tegra30 (Cardhu) and Tegra20 (Ventana).

This patch series is rebased on Tegra's for-3.9/soc and for-3.9/cleanup branch.

Changes from V3:
Fixed issued reported by Stephen Warren.

Changes from v2:
Removed APB MISC node.
Fixed some issues reported by Joseph Lo.
Added function to read chip id revision register.

Changes from v1:
Rebased on linux-next for 20121224.

Prashant Gaikwad (8):
  ARM: tegra: Add function to read chipid
  clk: tegra: Add tegra specific clocks
  arm: tegra: Move tegra_cpu_car.h to linux/clk/tegra.h
  ARM: Tegra: Define Tegra30 CAR binding
  clk: tegra: add clock support for tegra20
  clk: tegra: add clock support for tegra30
  arm: tegra: Migrate to new clock code
  arm: tegra: Remove legacy clock code

Stephen Warren (1):
  ARM: tegra: Define Tegra20 CAR binding

 .../bindings/clock/nvidia,tegra20-car.txt  |  205 ++
 .../bindings/clock/nvidia,tegra30-car.txt  |  262 ++
 arch/arm/boot/dts/tegra20.dtsi |6 +
 arch/arm/boot/dts/tegra30.dtsi |6 +
 arch/arm/mach-tegra/Makefile   |5 -
 arch/arm/mach-tegra/board-dt-tegra20.c |   30 -
 arch/arm/mach-tegra/board-dt-tegra30.c |   31 -
 arch/arm/mach-tegra/clock.c|  166 --
 arch/arm/mach-tegra/clock.h|  153 --
 arch/arm/mach-tegra/common.c   |   44 +-
 arch/arm/mach-tegra/cpu-tegra.c|2 +-
 arch/arm/mach-tegra/cpuidle-tegra30.c  |2 +-
 arch/arm/mach-tegra/fuse.c |8 +-
 arch/arm/mach-tegra/hotplug.c  |2 +-
 arch/arm/mach-tegra/include/mach/clk.h |   44 -
 arch/arm/mach-tegra/pcie.c |2 +-
 arch/arm/mach-tegra/platsmp.c  |2 +-
 arch/arm/mach-tegra/pm.c   |2 +-
 arch/arm/mach-tegra/powergate.c|2 +-
 arch/arm/mach-tegra/tegra20_clocks.c   | 1623 -
 arch/arm/mach-tegra/tegra20_clocks.h   |   42 -
 arch/arm/mach-tegra/tegra20_clocks_data.c  | 1143 -
 arch/arm/mach-tegra/tegra30_clocks.c   | 2506 
 arch/arm/mach-tegra/tegra30_clocks.h   |   54 -
 arch/arm/mach-tegra/tegra30_clocks_data.c  | 1425 ---
 drivers/clk/Makefile   |1 +
 drivers/clk/tegra/Makefile |   11 +
 drivers/clk/tegra/clk-audio-sync.c |   89 +
 drivers/clk/tegra/clk-divider.c|  188 ++
 drivers/clk/tegra/clk-periph-gate.c|  182 ++
 drivers/clk/tegra/clk-periph.c |  228 ++
 drivers/clk/tegra/clk-pll-out.c|  124 +
 drivers/clk/tegra/clk-pll.c|  676 ++
 drivers/clk/tegra/clk-super.c  |  154 ++
 drivers/clk/tegra/clk-tegra20.c| 1255 ++
 drivers/clk/tegra/clk-tegra30.c| 2041 
 drivers/clk/tegra/clk.c|   85 +
 drivers/clk/tegra/clk.h|  488 
 drivers/dma/tegra20-apb-dma.c  |2 +-
 drivers/gpu/drm/tegra/dc.c |3 +-
 drivers/gpu/drm/tegra/drm.c|1 -
 drivers/gpu/drm/tegra/hdmi.c   |3 +-
 drivers/i2c/busses/i2c-tegra.c |3 +-
 drivers/input/keyboard/tegra-kbc.c |2 +-
 drivers/spi/spi-tegra20-sflash.c   |2 +-
 drivers/spi/spi-tegra20-slink.c|2 +-
 drivers/staging/nvec/nvec.c|3 +-
 .../tegra_cpu_car.h => include/linux/clk/tegra.h   |   13 +-
 include/linux/tegra-soc.h  |   22 +
 sound/soc/tegra/tegra30_ahub.c |2 +-
 50 files changed, 6056 insertions(+), 7291 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
 create mode 100644 
Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
 delete mode 100644 arch/arm/mach-tegra/clock.c
 delete mode 100644 arch/arm/mach-tegra/clock.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/clk.h
 delete mode 100644 arch/arm/mach-tegra/tegra20_clocks.c
 delete mode 100644 arch/arm/mach-tegra/tegra20_clocks.h
 delete mode 100644 arch/arm/mach-tegra/tegra20_clocks_data.c
 delete mode 100644 arch/arm/mach-tegra/tegra30_clocks.c
 delete mode 100644 arch/arm/mach-te

[PATCH v4 1/9] ARM: tegra: Add function to read chipid

[Prashant Gaikwad]

Add function to read chip id from APB MISC registers. This function
will also get called from clock driver to flush write operations on
apb bus.

Signed-off-by: Prashant Gaikwad 
---
 arch/arm/mach-tegra/fuse.c |8 +++-
 include/linux/tegra-soc.h  |   22 ++
 2 files changed, 29 insertions(+), 1 deletions(-)
 create mode 100644 include/linux/tegra-soc.h

diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 8121742..f7db078 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "fuse.h"
 #include "iomap.h"
@@ -105,6 +106,11 @@ static void tegra_get_process_id(void)
tegra_core_process_id = (reg >> 12) & 3;
 }
 
+u32 tegra_read_chipid(void)
+{
+   return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
+}
+
 void tegra_init_fuse(void)
 {
u32 id;
@@ -119,7 +125,7 @@ void tegra_init_fuse(void)
reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
 
-   id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
+   id = tegra_read_chipid();
tegra_chip_id = (id >> 8) & 0xff;
 
switch (tegra_chip_id) {
diff --git a/include/linux/tegra-soc.h b/include/linux/tegra-soc.h
new file mode 100644
index 000..95f611d
--- /dev/null
+++ b/include/linux/tegra-soc.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __LINUX_TEGRA_SOC_H_
+#define __LINUX_TEGRA_SOC_H_
+
+u32 tegra_read_chipid(void);
+
+#endif /* __LINUX_TEGRA_SOC_H_ */
-- 
1.7.4.1

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Re: [PATCH 1/7] clk: add common of_clk_init() function

[Prashant Gaikwad]

On Friday 11 January 2013 01:23 AM, Josh Cartwright wrote:

* PGP Signed by an unknown key

On Fri, Jan 04, 2013 at 12:30:52PM +0530, Prashant Gaikwad wrote:

Modify of_clk_init function so that it will determine which
driver to initialize based on device tree instead of each driver
registering to it.

Based on a similar patch for drivers/irqchip by Thomas Petazzoni and
drivers/clocksource by Stephen Warren.

Signed-off-by: Prashant Gaikwad 
---

Prashant-

Sorry for the late response, but I finally got a chance to give this
patchset a spin on Zynq.  For patches 1 and 6:

Reviewed-by: Josh Cartwright 
Tested-by: Josh Cartwright 

   Josh


Thanks Josh!!


* Unknown Key
* 0x846F0FA5


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Re: [PATCH 1/7] clk: add common of_clk_init() function

[Prashant Gaikwad]

On Friday 11 January 2013 01:23 AM, Josh Cartwright wrote:

* PGP Signed by an unknown key

On Fri, Jan 04, 2013 at 12:30:52PM +0530, Prashant Gaikwad wrote:

Modify of_clk_init function so that it will determine which
driver to initialize based on device tree instead of each driver
registering to it.

Based on a similar patch for drivers/irqchip by Thomas Petazzoni and
drivers/clocksource by Stephen Warren.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Prashant-

Sorry for the late response, but I finally got a chance to give this
patchset a spin on Zynq.  For patches 1 and 6:

Reviewed-by: Josh Cartwright josh.cartwri...@ni.com
Tested-by: Josh Cartwright josh.cartwri...@ni.com

   Josh


Thanks Josh!!


* Unknown Key
* 0x846F0FA5


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[PATCH v4 0/9] Migrate Tegra to common clock framework

[Prashant Gaikwad]

This patchset does following:
1. Decompose single tegra clock structure into multiple clocks.
2. Try to use standard clock types supported by common clock framework.
3. Use dynamic initialization.
4. Move all clock code to drivers/clk/tegra from mach-tegra.
5. Add device tree support for Tegra20 and Tegra30 clocks.
6. Remove all legacy clock code from mach-tegra.

Tested on Tegra30 (Cardhu) and Tegra20 (Ventana).

This patch series is rebased on Tegra's for-3.9/soc and for-3.9/cleanup branch.

Changes from V3:
Fixed issued reported by Stephen Warren.

Changes from v2:
Removed APB MISC node.
Fixed some issues reported by Joseph Lo.
Added function to read chip id revision register.

Changes from v1:
Rebased on linux-next for 20121224.

Prashant Gaikwad (8):
  ARM: tegra: Add function to read chipid
  clk: tegra: Add tegra specific clocks
  arm: tegra: Move tegra_cpu_car.h to linux/clk/tegra.h
  ARM: Tegra: Define Tegra30 CAR binding
  clk: tegra: add clock support for tegra20
  clk: tegra: add clock support for tegra30
  arm: tegra: Migrate to new clock code
  arm: tegra: Remove legacy clock code

Stephen Warren (1):
  ARM: tegra: Define Tegra20 CAR binding

 .../bindings/clock/nvidia,tegra20-car.txt  |  205 ++
 .../bindings/clock/nvidia,tegra30-car.txt  |  262 ++
 arch/arm/boot/dts/tegra20.dtsi |6 +
 arch/arm/boot/dts/tegra30.dtsi |6 +
 arch/arm/mach-tegra/Makefile   |5 -
 arch/arm/mach-tegra/board-dt-tegra20.c |   30 -
 arch/arm/mach-tegra/board-dt-tegra30.c |   31 -
 arch/arm/mach-tegra/clock.c|  166 --
 arch/arm/mach-tegra/clock.h|  153 --
 arch/arm/mach-tegra/common.c   |   44 +-
 arch/arm/mach-tegra/cpu-tegra.c|2 +-
 arch/arm/mach-tegra/cpuidle-tegra30.c  |2 +-
 arch/arm/mach-tegra/fuse.c |8 +-
 arch/arm/mach-tegra/hotplug.c  |2 +-
 arch/arm/mach-tegra/include/mach/clk.h |   44 -
 arch/arm/mach-tegra/pcie.c |2 +-
 arch/arm/mach-tegra/platsmp.c  |2 +-
 arch/arm/mach-tegra/pm.c   |2 +-
 arch/arm/mach-tegra/powergate.c|2 +-
 arch/arm/mach-tegra/tegra20_clocks.c   | 1623 -
 arch/arm/mach-tegra/tegra20_clocks.h   |   42 -
 arch/arm/mach-tegra/tegra20_clocks_data.c  | 1143 -
 arch/arm/mach-tegra/tegra30_clocks.c   | 2506 
 arch/arm/mach-tegra/tegra30_clocks.h   |   54 -
 arch/arm/mach-tegra/tegra30_clocks_data.c  | 1425 ---
 drivers/clk/Makefile   |1 +
 drivers/clk/tegra/Makefile |   11 +
 drivers/clk/tegra/clk-audio-sync.c |   89 +
 drivers/clk/tegra/clk-divider.c|  188 ++
 drivers/clk/tegra/clk-periph-gate.c|  182 ++
 drivers/clk/tegra/clk-periph.c |  228 ++
 drivers/clk/tegra/clk-pll-out.c|  124 +
 drivers/clk/tegra/clk-pll.c|  676 ++
 drivers/clk/tegra/clk-super.c  |  154 ++
 drivers/clk/tegra/clk-tegra20.c| 1255 ++
 drivers/clk/tegra/clk-tegra30.c| 2041 
 drivers/clk/tegra/clk.c|   85 +
 drivers/clk/tegra/clk.h|  488 
 drivers/dma/tegra20-apb-dma.c  |2 +-
 drivers/gpu/drm/tegra/dc.c |3 +-
 drivers/gpu/drm/tegra/drm.c|1 -
 drivers/gpu/drm/tegra/hdmi.c   |3 +-
 drivers/i2c/busses/i2c-tegra.c |3 +-
 drivers/input/keyboard/tegra-kbc.c |2 +-
 drivers/spi/spi-tegra20-sflash.c   |2 +-
 drivers/spi/spi-tegra20-slink.c|2 +-
 drivers/staging/nvec/nvec.c|3 +-
 .../tegra_cpu_car.h = include/linux/clk/tegra.h   |   13 +-
 include/linux/tegra-soc.h  |   22 +
 sound/soc/tegra/tegra30_ahub.c |2 +-
 50 files changed, 6056 insertions(+), 7291 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
 create mode 100644 
Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
 delete mode 100644 arch/arm/mach-tegra/clock.c
 delete mode 100644 arch/arm/mach-tegra/clock.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/clk.h
 delete mode 100644 arch/arm/mach-tegra/tegra20_clocks.c
 delete mode 100644 arch/arm/mach-tegra/tegra20_clocks.h
 delete mode 100644 arch/arm/mach-tegra/tegra20_clocks_data.c
 delete mode 100644 arch/arm/mach-tegra/tegra30_clocks.c
 delete mode 100644 arch/arm/mach-tegra

[PATCH v4 1/9] ARM: tegra: Add function to read chipid

[Prashant Gaikwad]

Add function to read chip id from APB MISC registers. This function
will also get called from clock driver to flush write operations on
apb bus.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
 arch/arm/mach-tegra/fuse.c |8 +++-
 include/linux/tegra-soc.h  |   22 ++
 2 files changed, 29 insertions(+), 1 deletions(-)
 create mode 100644 include/linux/tegra-soc.h

diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 8121742..f7db078 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -20,6 +20,7 @@
 #include linux/kernel.h
 #include linux/io.h
 #include linux/export.h
+#include linux/tegra-soc.h
 
 #include fuse.h
 #include iomap.h
@@ -105,6 +106,11 @@ static void tegra_get_process_id(void)
tegra_core_process_id = (reg  12)  3;
 }
 
+u32 tegra_read_chipid(void)
+{
+   return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
+}
+
 void tegra_init_fuse(void)
 {
u32 id;
@@ -119,7 +125,7 @@ void tegra_init_fuse(void)
reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
tegra_bct_strapping = (reg  RAM_ID_MASK)  RAM_CODE_SHIFT;
 
-   id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
+   id = tegra_read_chipid();
tegra_chip_id = (id  8)  0xff;
 
switch (tegra_chip_id) {
diff --git a/include/linux/tegra-soc.h b/include/linux/tegra-soc.h
new file mode 100644
index 000..95f611d
--- /dev/null
+++ b/include/linux/tegra-soc.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+#ifndef __LINUX_TEGRA_SOC_H_
+#define __LINUX_TEGRA_SOC_H_
+
+u32 tegra_read_chipid(void);
+
+#endif /* __LINUX_TEGRA_SOC_H_ */
-- 
1.7.4.1

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[PATCH v4 5/9] ARM: Tegra: Define Tegra30 CAR binding

[Prashant Gaikwad]

The device tree binding models Tegra30 CAR (Clock And Reset)
as a single monolithic clock provider.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
 .../bindings/clock/nvidia,tegra30-car.txt  |  262 
 arch/arm/boot/dts/tegra30.dtsi |6 +
 2 files changed, 268 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt 
b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
new file mode 100644
index 000..121d203
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -0,0 +1,262 @@
+NVIDIA Tegra30 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be nvidia,tegra30-car
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+  the 32 KHz 32k_in, and the board-specific oscillator osc.
+- #clock-cells : Should be 1.
+  In clock consumers, this cell represents the clock ID exposed by the CAR.
+
+  The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  registers. These IDs often match those in the CAR's RST_DEVICES registers,
+  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+  this case, those clocks are assigned IDs above 160 in order to highlight
+  this issue. Implementations that interpret these clock IDs as bit values
+  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+  explicitly handle these special cases.
+
+  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+  above.
+
+  0cpu
+  1unassigned
+  2unassigned
+  3unassigned
+  4rtc
+  5timer
+  6uarta
+  7unassigned  (register bit affects uartb and vfir)
+  8gpio
+  9sdmmc2
+  10   unassigned  (register bit affects spdif_in and spdif_out)
+  11   i2s1
+  12   i2c1
+  13   ndflash
+  14   sdmmc1
+  15   sdmmc4
+  16   unassigned
+  17   pwm
+  18   i2s2
+  19   epp
+  20   unassigned  (register bit affects vi and vi_sensor)
+  21   2d
+  22   usbd
+  23   isp
+  24   3d
+  25   unassigned
+  26   disp2
+  27   disp1
+  28   host1x
+  29   vcp
+  30   i2s0
+  31   cop_cache
+
+  32   mc
+  33   ahbdma
+  34   apbdma
+  35   unassigned
+  36   kbc
+  37   statmon
+  38   pmc
+  39   unassigned  (register bit affects fuse and fuse_burn)
+  40   kfuse
+  41   sbc1
+  42   nor
+  43   unassigned
+  44   sbc2
+  45   unassigned
+  46   sbc3
+  47   i2c5
+  48   dsia
+  49   unassigned  (register bit affects cve and tvo)
+  50   mipi
+  51   hdmi
+  52   csi
+  53   tvdac
+  54   i2c2
+  55   uartc
+  56   unassigned
+  57   emc
+  58   usb2
+  59   usb3
+  60   mpe
+  61   vde
+  62   bsea
+  63   bsev
+
+  64   speedo
+  65   uartd
+  66   uarte
+  67   i2c3
+  68   sbc4
+  69   sdmmc3
+  70   pcie
+  71   owr
+  72   afi
+  73   csite
+  74   pciex
+  75   avpucq
+  76   la
+  77   unassigned
+  78   unassigned
+  79   dtv
+  80   ndspeed
+  81   i2cslow
+  82   dsib
+  83   unassigned
+  84   irama
+  85   iramb
+  86   iramc
+  87   iramd
+  88   cram2
+  89   unassigned
+  90   audio_2xa/k/a audio_2x_sync_clk
+  91   unassigned
+  92   csus
+  93   cdev2
+  94   cdev1
+  95   unassigned
+
+  96   cpu_g
+  97   cpu_lp
+  98   3d2
+  99   mselect
+  100  tsensor
+  101  i2s3
+  102  i2s4
+  103  i2c4
+  104  sbc5
+  105  sbc6
+  106  d_audio
+  107  apbif
+  108  dam0
+  109  dam1
+  110  dam2
+  111  hda2codec_2x
+  112  atomics
+  113  audio0_2x
+  114  audio1_2x
+  115  audio2_2x
+  116  audio3_2x
+  117  audio4_2x
+  118  audio5_2x
+  119  actmon
+  120  extern1
+  121  extern2
+  122  extern3
+  123  sata_oob
+  124  sata
+  125  hda
+  127  se
+  128  hda2hdmi
+  129  sata_cold
+
+  160  uartb
+  161  vfir
+  162  spdif_in
+  163  spdif_out
+  164  vi
+  165  vi_sensor
+  166  fuse
+  167  fuse_burn
+  168  cve
+  169  tvo
+
+  170  clk_32k
+  171  clk_m
+  172  clk_m_div2
+  173  clk_m_div4
+  174  pll_ref
+  175  pll_c
+  176  pll_c_out1
+  177  pll_m
+  178  pll_m_out1
+  179  pll_p
+  180  pll_p_out1
+  181  pll_p_out2
+  182  pll_p_out3
+  183  pll_p_out4
+  184  pll_a
+  185  pll_a_out0
+  186  pll_d
+  187  pll_d_out0
+  188  pll_d2
+  189  pll_d2_out0
+  190  pll_u
+  191  pll_x
+  192  pll_x_out0
+  193  pll_e
+  194  spdif_in_sync
+  195  i2s0_sync
+  196  i2s1_sync
+  197  i2s2_sync
+  198  i2s3_sync
+  199  i2s4_sync
+  200  vimclk
+  201  audio0
+  202  audio1
+  203  audio2
+  204  audio3
+  205  audio4
+  206  audio5
+  207  clk_out_1 (extern1)
+  208  clk_out_2 (extern2)
+  209  clk_out_3 (extern3

[PATCH v4 8/9] arm: tegra: Migrate to new clock code

[Prashant Gaikwad]

Migrate tegra clock support to drivers/clk/tegra, this involves
moving
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
 arch/arm/mach-tegra/board-dt-tegra20.c |   30 -
 arch/arm/mach-tegra/board-dt-tegra30.c |   31 --
 arch/arm/mach-tegra/clock.c|   19 -
 arch/arm/mach-tegra/common.c   |   44 +--
 arch/arm/mach-tegra/cpu-tegra.c|2 +-
 arch/arm/mach-tegra/include/mach/clk.h |3 --
 arch/arm/mach-tegra/pcie.c |2 +-
 arch/arm/mach-tegra/powergate.c|2 +-
 drivers/clk/tegra/clk-periph.c |   38 +++
 drivers/clk/tegra/clk.c|   16 +++
 drivers/dma/tegra20-apb-dma.c  |2 +-
 drivers/gpu/drm/tegra/dc.c |3 +-
 drivers/gpu/drm/tegra/drm.c|1 -
 drivers/gpu/drm/tegra/hdmi.c   |3 +-
 drivers/i2c/busses/i2c-tegra.c |3 +-
 drivers/input/keyboard/tegra-kbc.c |2 +-
 drivers/spi/spi-tegra20-sflash.c   |2 +-
 drivers/spi/spi-tegra20-slink.c|2 +-
 drivers/staging/nvec/nvec.c|3 +-
 include/linux/clk/tegra.h  |5 +++
 sound/soc/tegra/tegra30_ahub.c |2 +-
 21 files changed, 73 insertions(+), 142 deletions(-)

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c 
b/arch/arm/mach-tegra/board-dt-tegra20.c
index e1f87dd..0c11b8a 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -42,7 +42,6 @@
 #include asm/setup.h
 
 #include board.h
-#include clock.h
 #include common.h
 #include iomap.h
 
@@ -104,37 +103,8 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] 
__initdata = {
{}
 };
 
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-   /* name parent  rateenabled */
-   { uarta,  pll_p,21600,  true },
-   { uartd,  pll_p,21600,  true },
-   { usbd,   clk_m,1200,   false },
-   { usb2,   clk_m,1200,   false },
-   { usb3,   clk_m,1200,   false },
-   { pll_a,  pll_p_out1,   56448000,   true },
-   { pll_a_out0, pll_a,11289600,   true },
-   { cdev1,  NULL,   0,  true },
-   { blink,  clk_32k,  32768,  true },
-   { i2s1,   pll_a_out0,   11289600,   false},
-   { i2s2,   pll_a_out0,   11289600,   false},
-   { sdmmc1, pll_p,4800,   false},
-   { sdmmc3, pll_p,4800,   false},
-   { sdmmc4, pll_p,4800,   false},
-   { spi,pll_p,2000,   false },
-   { sbc1,   pll_p,1,  false },
-   { sbc2,   pll_p,1,  false },
-   { sbc3,   pll_p,1,  false },
-   { sbc4,   pll_p,1,  false },
-   { host1x, pll_c,15000,  false },
-   { disp1,  pll_p,6,  false },
-   { disp2,  pll_p,6,  false },
-   { NULL, NULL,   0,  0},
-};
-
 static void __init tegra_dt_init(void)
 {
-   tegra_clk_init_from_table(tegra_dt_clk_init_table);
-
/*
 * Finished with the static registrations now; fill in the missing
 * devices
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c 
b/arch/arm/mach-tegra/board-dt-tegra30.c
index cfe5fc0..92f6014 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -35,7 +35,6 @@
 #include asm/hardware/gic.h
 
 #include board.h
-#include clock.h
 #include common.h
 #include iomap.h
 
@@ -67,38 +66,8 @@ static struct of_dev_auxdata tegra30_auxdata_lookup[] 
__initdata = {
{}
 };
 
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-   /* name parent  rateenabled */
-   { uarta,  pll_p,40800,  true },
-   { pll_a,  pll_p_out1,   56448,  true },
-   { pll_a_out0, pll_a,11289600,   true },
-   { extern1,pll_a_out0,   0,  true },
-   { clk_out_1,  extern1,  0,  true },
-   { blink,  clk_32k,  32768,  true },
-   { i2s0,   pll_a_out0,   11289600,   false},
-   { i2s1,   pll_a_out0,   11289600,   false},
-   { i2s2,   pll_a_out0,   11289600,   false},
-   { i2s3,   pll_a_out0,   11289600,   false},
-   { i2s4,   pll_a_out0

[PATCH v4 3/9] arm: tegra: Move tegra_cpu_car.h to linux/clk/tegra.h

[Prashant Gaikwad]

tegra_cpu_car_ops struct is going to be accessed from drivers/clk/tegra.
Move the tegra_cpu_car_ops to include/linux/clk/tegra.h.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
 arch/arm/mach-tegra/clock.c|2 +-
 arch/arm/mach-tegra/cpuidle-tegra30.c  |2 +-
 arch/arm/mach-tegra/hotplug.c  |2 +-
 arch/arm/mach-tegra/platsmp.c  |2 +-
 arch/arm/mach-tegra/pm.c   |2 +-
 arch/arm/mach-tegra/tegra20_clocks.c   |2 +-
 arch/arm/mach-tegra/tegra20_clocks_data.c  |2 +-
 arch/arm/mach-tegra/tegra30_clocks.c   |2 +-
 arch/arm/mach-tegra/tegra30_clocks_data.c  |2 +-
 .../tegra_cpu_car.h = include/linux/clk/tegra.h   |6 +++---
 10 files changed, 12 insertions(+), 12 deletions(-)
 rename arch/arm/mach-tegra/tegra_cpu_car.h = include/linux/clk/tegra.h (96%)

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 867bf8b..8c0ff06 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -26,10 +26,10 @@
 #include linux/sched.h
 #include linux/seq_file.h
 #include linux/slab.h
+#include linux/clk/tegra.h
 
 #include board.h
 #include clock.h
-#include tegra_cpu_car.h
 
 /* Global data of Tegra CPU CAR ops */
 struct tegra_cpu_car_ops *tegra_cpu_car_ops;
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c 
b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 82530bd..8b50cf4 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -24,6 +24,7 @@
 #include linux/cpuidle.h
 #include linux/cpu_pm.h
 #include linux/clockchips.h
+#include linux/clk/tegra.h
 
 #include asm/cpuidle.h
 #include asm/proc-fns.h
@@ -32,7 +33,6 @@
 
 #include pm.h
 #include sleep.h
-#include tegra_cpu_car.h
 
 #ifdef CONFIG_PM_SLEEP
 static int tegra30_idle_lp2(struct cpuidle_device *dev,
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 6a27de4..a599f6e 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -10,12 +10,12 @@
  */
 #include linux/kernel.h
 #include linux/smp.h
+#include linux/clk/tegra.h
 
 #include asm/cacheflush.h
 #include asm/smp_plat.h
 
 #include sleep.h
-#include tegra_cpu_car.h
 
 static void (*tegra_hotplug_shutdown)(void);
 
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 6867030..3ec7fc4 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -18,6 +18,7 @@
 #include linux/jiffies.h
 #include linux/smp.h
 #include linux/io.h
+#include linux/clk/tegra.h
 
 #include asm/cacheflush.h
 #include asm/hardware/gic.h
@@ -30,7 +31,6 @@
 #include fuse.h
 #include flowctrl.h
 #include reset.h
-#include tegra_cpu_car.h
 
 #include common.h
 #include iomap.h
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 498d70b..abfe9b9 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -24,6 +24,7 @@
 #include linux/cpu_pm.h
 #include linux/clk.h
 #include linux/err.h
+#include linux/clk/tegra.h
 
 #include asm/smp_plat.h
 #include asm/cacheflush.h
@@ -36,7 +37,6 @@
 #include reset.h
 #include flowctrl.h
 #include sleep.h
-#include tegra_cpu_car.h
 
 #define TEGRA_POWER_CPU_PWRREQ_OE  (1  16)  /* CPU pwr req enable */
 
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c 
b/arch/arm/mach-tegra/tegra20_clocks.c
index 4eb6bc8..1a80ff6 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -26,12 +26,12 @@
 #include linux/io.h
 #include linux/clkdev.h
 #include linux/clk.h
+#include linux/clk/tegra.h
 
 #include clock.h
 #include fuse.h
 #include iomap.h
 #include tegra2_emc.h
-#include tegra_cpu_car.h
 
 #define RST_DEVICES0x004
 #define RST_DEVICES_SET0x300
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c 
b/arch/arm/mach-tegra/tegra20_clocks_data.c
index a23a073..022cdae 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -26,12 +26,12 @@
 #include linux/delay.h
 #include linux/io.h
 #include linux/clk.h
+#include linux/clk/tegra.h
 
 #include clock.h
 #include fuse.h
 #include tegra2_emc.h
 #include tegra20_clocks.h
-#include tegra_cpu_car.h
 
 /* Clock definitions */
 
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c 
b/arch/arm/mach-tegra/tegra30_clocks.c
index d714777..4330787 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -28,6 +28,7 @@
 #include linux/clk.h
 #include linux/cpufreq.h
 #include linux/syscore_ops.h
+#include linux/clk/tegra.h
 
 #include asm/clkdev.h
 
@@ -36,7 +37,6 @@
 #include clock.h
 #include fuse.h
 #include iomap.h
-#include tegra_cpu_car.h
 
 #define USE_PLL_LOCK_BITS 0
 
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c 
b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 741d264..9bfaa49 100644
--- a/arch/arm

[PATCH v4 6/9] clk: tegra: add clock support for tegra20

[Prashant Gaikwad]

Add tegra20 clock support based on common clock framework.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
 drivers/clk/tegra/Makefile  |2 +
 drivers/clk/tegra/clk-tegra20.c | 1255 +++
 drivers/clk/tegra/clk.h |6 +
 3 files changed, 1263 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/tegra/clk-tegra20.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 68bd353..00484fd 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -6,3 +6,5 @@ obj-y   += clk-periph-gate.o
 obj-y  += clk-pll.o
 obj-y  += clk-pll-out.o
 obj-y  += clk-super.o
+
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
new file mode 100644
index 000..4875261
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -0,0 +1,1255 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/io.h
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/clk/tegra.h
+
+#include clk.h
+
+#define RST_DEVICES_L 0x004
+#define RST_DEVICES_H 0x008
+#define RST_DEVICES_U 0x00c
+#define RST_DEVICES_SET_L 0x300
+#define RST_DEVICES_CLR_L 0x304
+#define RST_DEVICES_SET_H 0x308
+#define RST_DEVICES_CLR_H 0x30c
+#define RST_DEVICES_SET_U 0x310
+#define RST_DEVICES_CLR_U 0x314
+#define RST_DEVICES_NUM 3
+
+#define CLK_OUT_ENB_L 0x010
+#define CLK_OUT_ENB_H 0x014
+#define CLK_OUT_ENB_U 0x018
+#define CLK_OUT_ENB_SET_L 0x320
+#define CLK_OUT_ENB_CLR_L 0x324
+#define CLK_OUT_ENB_SET_H 0x328
+#define CLK_OUT_ENB_CLR_H 0x32c
+#define CLK_OUT_ENB_SET_U 0x330
+#define CLK_OUT_ENB_CLR_U 0x334
+#define CLK_OUT_ENB_NUM 3
+
+#define OSC_CTRL 0x50
+#define OSC_CTRL_OSC_FREQ_MASK (330)
+#define OSC_CTRL_OSC_FREQ_13MHZ (030)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ (130)
+#define OSC_CTRL_OSC_FREQ_12MHZ (230)
+#define OSC_CTRL_OSC_FREQ_26MHZ (330)
+#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
+
+#define OSC_CTRL_PLL_REF_DIV_MASK (328)
+#define OSC_CTRL_PLL_REF_DIV_1 (028)
+#define OSC_CTRL_PLL_REF_DIV_2 (128)
+#define OSC_CTRL_PLL_REF_DIV_4 (228)
+
+#define OSC_FREQ_DET 0x58
+#define OSC_FREQ_DET_TRIG (131)
+
+#define OSC_FREQ_DET_STATUS 0x5c
+#define OSC_FREQ_DET_BUSY (131)
+#define OSC_FREQ_DET_CNT_MASK 0x
+
+#define PLLS_BASE 0xf0
+#define PLLS_MISC 0xf4
+#define PLLC_BASE 0x80
+#define PLLC_MISC 0x8c
+#define PLLM_BASE 0x90
+#define PLLM_MISC 0x9c
+#define PLLP_BASE 0xa0
+#define PLLP_MISC 0xac
+#define PLLA_BASE 0xb0
+#define PLLA_MISC 0xbc
+#define PLLU_BASE 0xc0
+#define PLLU_MISC 0xcc
+#define PLLD_BASE 0xd0
+#define PLLD_MISC 0xdc
+#define PLLX_BASE 0xe0
+#define PLLX_MISC 0xe4
+#define PLLE_BASE 0xe8
+#define PLLE_MISC 0xec
+
+#define PLL_BASE_LOCK 27
+#define PLLE_MISC_LOCK 11
+
+#define PLL_MISC_LOCK_ENABLE 18
+#define PLLDU_MISC_LOCK_ENABLE 22
+#define PLLE_MISC_LOCK_ENABLE 9
+
+#define PLLC_OUT 0x84
+#define PLLM_OUT 0x94
+#define PLLP_OUTA 0xa4
+#define PLLP_OUTB 0xa8
+#define PLLA_OUT 0xb4
+
+#define CCLK_BURST_POLICY 0x20
+#define SUPER_CCLK_DIVIDER 0x24
+#define SCLK_BURST_POLICY 0x28
+#define SUPER_SCLK_DIVIDER 0x2c
+#define CLK_SYSTEM_RATE 0x30
+
+#define CLK_SOURCE_I2S1 0x100
+#define CLK_SOURCE_I2S2 0x104
+#define CLK_SOURCE_SPDIF_OUT 0x108
+#define CLK_SOURCE_SPDIF_IN 0x10c
+#define CLK_SOURCE_PWM 0x110
+#define CLK_SOURCE_SPI 0x114
+#define CLK_SOURCE_SBC1 0x134
+#define CLK_SOURCE_SBC2 0x118
+#define CLK_SOURCE_SBC3 0x11c
+#define CLK_SOURCE_SBC4 0x1b4
+#define CLK_SOURCE_XIO 0x120
+#define CLK_SOURCE_TWC 0x12c
+#define CLK_SOURCE_IDE 0x144
+#define CLK_SOURCE_NDFLASH 0x160
+#define CLK_SOURCE_VFIR 0x168
+#define CLK_SOURCE_SDMMC1 0x150
+#define CLK_SOURCE_SDMMC2 0x154
+#define CLK_SOURCE_SDMMC3 0x1bc
+#define CLK_SOURCE_SDMMC4 0x164
+#define CLK_SOURCE_CVE 0x140
+#define CLK_SOURCE_TVO 0x188
+#define CLK_SOURCE_TVDAC 0x194
+#define CLK_SOURCE_HDMI 0x18c
+#define CLK_SOURCE_DISP1 0x138
+#define CLK_SOURCE_DISP2 0x13c
+#define CLK_SOURCE_CSITE 0x1d4
+#define CLK_SOURCE_LA 0x1f8
+#define CLK_SOURCE_OWR 0x1cc
+#define CLK_SOURCE_NOR 0x1d0
+#define CLK_SOURCE_MIPI 0x174

[PATCH v4 4/9] ARM: tegra: Define Tegra20 CAR binding

[Prashant Gaikwad]

From: Stephen Warren swar...@nvidia.com

The Tegra20 CAR (Clock And Reset) Controller controls most aspects of
most clocks within Tegra20. The device tree binding models this as a
single monolithic clock provider, which exports many clocks. This reduces
the number of nodes needed in device tree to represent these clocks.

This binding is only useful for Tegra20; the set of clocks that exists on
Tegra30 is sufficiently different to merit its own binding.

Signed-off-by: Stephen Warren swar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
[pgaikwad: Added mux clk ids and sorted CAR node]
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
 .../bindings/clock/nvidia,tegra20-car.txt  |  205 
 arch/arm/boot/dts/tegra20.dtsi |6 +
 2 files changed, 211 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt 
b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
new file mode 100644
index 000..0921fac
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -0,0 +1,205 @@
+NVIDIA Tegra20 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be nvidia,tegra20-car
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+  the 32 KHz 32k_in, and the board-specific oscillator osc.
+- #clock-cells : Should be 1.
+  In clock consumers, this cell represents the clock ID exposed by the CAR.
+
+  The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  registers. These IDs often match those in the CAR's RST_DEVICES registers,
+  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+  this case, those clocks are assigned IDs above 95 in order to highlight
+  this issue. Implementations that interpret these clock IDs as bit values
+  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+  explicitly handle these special cases.
+
+  The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+  above.
+
+  0cpu
+  1unassigned
+  2unassigned
+  3ac97
+  4rtc
+  5tmr
+  6uart1
+  7unassigned  (register bit affects uart2 and vfir)
+  8gpio
+  9sdmmc2
+  10   unassigned  (register bit affects spdif_in and spdif_out)
+  11   i2s1
+  12   i2c1
+  13   ndflash
+  14   sdmmc1
+  15   sdmmc4
+  16   twc
+  17   pwm
+  18   i2s2
+  19   epp
+  20   unassigned  (register bit affects vi and vi_sensor)
+  21   2d
+  22   usbd
+  23   isp
+  24   3d
+  25   ide
+  26   disp2
+  27   disp1
+  28   host1x
+  29   vcp
+  30   unassigned
+  31   cache2
+
+  32   mem
+  33   ahbdma
+  34   apbdma
+  35   unassigned
+  36   kbc
+  37   stat_mon
+  38   pmc
+  39   fuse
+  40   kfuse
+  41   sbc1
+  42   snor
+  43   spi1
+  44   sbc2
+  45   xio
+  46   sbc3
+  47   dvc
+  48   dsi
+  49   unassigned  (register bit affects tvo and cve)
+  50   mipi
+  51   hdmi
+  52   csi
+  53   tvdac
+  54   i2c2
+  55   uart3
+  56   unassigned
+  57   emc
+  58   usb2
+  59   usb3
+  60   mpe
+  61   vde
+  62   bsea
+  63   bsev
+
+  64   speedo
+  65   uart4
+  66   uart5
+  67   i2c3
+  68   sbc4
+  69   sdmmc3
+  70   pcie
+  71   owr
+  72   afi
+  73   csite
+  74   unassigned
+  75   avpucq
+  76   la
+  77   unassigned
+  78   unassigned
+  79   unassigned
+  80   unassigned
+  81   unassigned
+  82   unassigned
+  83   unassigned
+  84   irama
+  85   iramb
+  86   iramc
+  87   iramd
+  88   cram2
+  89   audio_2xa/k/a audio_2x_sync_clk
+  90   clk_d
+  91   unassigned
+  92   sus
+  93   cdev1
+  94   cdev2
+  95   unassigned
+
+  96   uart2
+  97   vfir
+  98   spdif_in
+  99   spdif_out
+  100  vi
+  101  vi_sensor
+  102  tvo
+  103  cve
+  104  osc
+  105  clk_32k a/k/a clk_s
+  106  clk_m
+  107  sclk
+  108  cclk
+  109  hclk
+  110  pclk
+  111  blink
+  112  pll_a
+  113  pll_a_out0
+  114  pll_c
+  115  pll_c_out1
+  116  pll_d
+  117  pll_d_out0
+  118  pll_e
+  119  pll_m
+  120  pll_m_out1
+  121  pll_p
+  122  pll_p_out1
+  123  pll_p_out2
+  124  pll_p_out3
+  125  pll_p_out4
+  126  pll_s
+  127  pll_u
+  128  pll_x
+  129  cop a/k/a avp
+  130  audio   a/k/a audio_sync_clk
+  131  pll_ref
+  132  twd
+
+Example SoC include file:
+
+/ {
+   tegra_car: clock {
+   compatible = nvidia,tegra20-car;
+   reg = 0x60006000 0x1000;
+   #clock-cells = 1;
+   };
+
+   usb@c5004000 {
+   clocks = tegra_car 58; /* usb2 */
+   };
+};
+
+Example

Re: [PATCH 2/2] clk: tegra30: Convert clk out to composite clk

[Prashant Gaikwad]

On Friday 04 January 2013 09:55 PM, Stephen Warren wrote:

On 01/03/2013 10:51 PM, Prashant Gaikwad wrote:

Convert clk out to composite clock type which removes
the mux clock.

Signed-off-by: Prashant Gaikwad 
---
This patch is rebased on ccf-rework for Tegra patch series. It is just to show
how clk-composite can be used, not to be merged. If patch 1 is accepted then
I would like to merge this patch to ccf-rework series.

Just so I'm clear, is the intent that patch 1 of this series gets
reviewed/accepted, and then you'll repost an updated version of the
Tegra CCF rework series that relies on patch 1? If so, patch 1 would
need to be either taken through the Tegra tree, or put into a separate
branch in the clock tree, so the Tegra tree can merge it as a dependency
of the Tegra CCF rework branch.


Yes, that is my plan but you can tell whatever you are comfortable with. 
I will re-order the dependencies.



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Re: [PATCH 1/2] clk: Add composite clock type

[Prashant Gaikwad]

On Saturday 05 January 2013 03:48 AM, Stephen Boyd wrote:

On 01/03/13 21:51, Prashant Gaikwad wrote:

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f0b269a..baf7608 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -2,7 +2,8 @@
  obj-$(CONFIG_HAVE_CLK)+= clk-devres.o
  obj-$(CONFIG_CLKDEV_LOOKUP)   += clkdev.o
  obj-$(CONFIG_COMMON_CLK)  += clk.o clk-fixed-rate.o clk-gate.o \
-  clk-mux.o clk-divider.o clk-fixed-factor.o
+  clk-mux.o clk-divider.o clk-fixed-factor.o \
+  clk-composite.o

This list is getting a little out of hand. Should we sort it
alphabetically and put each file on one line?


Do you want me to do it in this patch?




  # SoCs specific
  obj-$(CONFIG_ARCH_BCM2835)+= clk-bcm2835.o
  obj-$(CONFIG_ARCH_NOMADIK)+= clk-nomadik.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..8634dbf
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;

Looks like this is already done down in the register function. Why are
we doing it again here and in each op?


Some ops gets called during clk_init which is before clk_register returns.



+
+   return mux_ops->get_parent(mux_hw);
+}

[snip]

+struct clk *clk_register_composite(struct device *dev, const char *name,
+   const char **parent_names, int num_parents,
+   struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+   struct clk_hw *div_hw, const struct clk_ops *div_ops,
+   struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+   unsigned long flags)
+{
+   struct clk *clk;
+   struct clk_init_data init;
+   struct clk_composite *composite;
+   struct clk_ops *clk_composite_ops;
+
+   composite = kzalloc(sizeof(struct clk_ops), GFP_KERNEL);

sizeof(*composite) != sizeof(struct clk_ops)


Thanks.


+   if (!composite) {
+   pr_err("%s: could not allocate composite clk\n", __func__);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   init.name = name;
+   init.flags = flags | CLK_IS_BASIC;
+   init.parent_names = parent_names;
+   init.num_parents = num_parents;
+
+   /* allocate the clock ops */
+   clk_composite_ops = kzalloc(sizeof(struct clk_ops), GFP_KERNEL);

This one looks right though. Perhaps you should change style to use
sizeof(*clk_composite_ops) so that the above mistake doesn't happen.


Sure.


+   if (!clk_composite_ops) {
+   pr_err("%s: could not allocate clk ops\n", __func__);
+   kfree(composite);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   if (mux_hw && mux_ops) {
+   if (!mux_ops->get_parent || !mux_ops->set_parent) {
+   clk = ERR_PTR(-EINVAL);
+   goto err;
+   }
+
+   composite->mux_hw = mux_hw;
+   composite->mux_ops = mux_ops;
+   clk_composite_ops->get_parent = clk_composite_get_parent;
+   clk_composite_ops->set_parent = clk_composite_set_parent;
+   }
+
+   if (div_hw && div_ops) {
+   if (!div_ops->recalc_rate || !div_ops->round_rate ||
+   !div_ops->set_rate) {
+   clk = ERR_PTR(-EINVAL);
+   goto err;
+   }
+
+   composite->div_hw = div_hw;
+   composite->div_ops = div_ops;
+   clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
+   clk_composite_ops->round_rate = clk_composite_round_rate;
+   clk_composite_ops->set_rate = clk_composite_set_rate;
+   }

Re: [PATCH 2/7] clk: tegra: Use common of_clk_init() function

[Prashant Gaikwad]

On Friday 04 January 2013 10:00 PM, Stephen Warren wrote:

On 01/04/2013 12:00 AM, Prashant Gaikwad wrote:

Use common of_clk_init() function for clocks initialization.
  drivers/clk/tegra/clk-tegra20.c |3 ++-
  drivers/clk/tegra/clk-tegra30.c |3 ++-

Oh, so this series is written assuming that the Tegra CCF rework is
already applied then? That makes the dependencies quite painful, since I
think we'll end up with the following order being needed:

1) clk: Add composite clock type
-> This would usually go through the clk tree.
2) The Tegra CCF rework series
-> This must go through the Tegra tree due to lots of dependencies
and merge conflicts with other Tegra patches.
3) This series
-> This would usually go through the clk tree.

Is it possible to re-order the dependencies as (1) (3) (2), so that Mike
can apply (1) and (3) to the clock tree, then I can use the clk tree as
the basis for a branch in the Tegra tree to apply (2) and all the other
Tegra patches that will conflict with (2)?


If Mike approves the concept and implementation in (1) and (3) then I 
will repost (2) and (3) with dependencies re-ordered.



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[PATCH 3/7] ASoC: tegra: remove auxdata

[Prashant Gaikwad]

Configlink clock information is added to device tree. Get the clocks
using device node. Remove AUXDATA.

Signed-off-by: Prashant Gaikwad 
---
 sound/soc/tegra/tegra30_ahub.c |   14 ++
 1 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index bb31c41..2355630 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -299,15 +299,6 @@ static const char * const configlink_clocks[] = {
"spdif_in",
 };
 
-struct of_dev_auxdata ahub_auxdata[] = {
-   OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080300, "tegra30-i2s.0", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080400, "tegra30-i2s.1", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080500, "tegra30-i2s.2", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080600, "tegra30-i2s.3", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080700, "tegra30-i2s.4", NULL),
-   {}
-};
-
 #define LAST_REG(name) \
(TEGRA30_AHUB_##name + \
 (TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4)
@@ -451,7 +442,7 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
 * Ensure that here.
 */
for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) {
-   clk = clk_get_sys(NULL, configlink_clocks[i]);
+   clk = clk_get(>dev, configlink_clocks[i]);
if (IS_ERR(clk)) {
dev_err(>dev, "Can't get clock %s\n",
configlink_clocks[i]);
@@ -569,8 +560,7 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
goto err_pm_disable;
}
 
-   of_platform_populate(pdev->dev.of_node, NULL, ahub_auxdata,
->dev);
+   of_platform_populate(pdev->dev.of_node, NULL, NULL, >dev);
 
return 0;
 
-- 
1.7.4.1

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[PATCH 7/7] clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s

[Prashant Gaikwad]

With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.

Signed-off-by: Prashant Gaikwad 
---
 drivers/clk/tegra/clk-tegra30.c |   34 --
 1 files changed, 0 insertions(+), 34 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 2b3b4f7..57db77d 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1932,18 +1932,9 @@ static __initdata struct tegra_clk_init_table 
init_table[] = {
  * table under two names.
  */
 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
-   TEGRA_CLK_DUPLICATE(uarta,  "serial8250.0", NULL),
-   TEGRA_CLK_DUPLICATE(uartb,  "serial8250.1", NULL),
-   TEGRA_CLK_DUPLICATE(uartc,  "serial8250.2", NULL),
-   TEGRA_CLK_DUPLICATE(uartd,  "serial8250.3", NULL),
-   TEGRA_CLK_DUPLICATE(uarte,  "serial8250.4", NULL),
TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL),
TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL),
TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL),
-   TEGRA_CLK_DUPLICATE(hdmi, "tegradc.0", "hdmi"),
-   TEGRA_CLK_DUPLICATE(hdmi, "tegradc.1", "hdmi"),
-   TEGRA_CLK_DUPLICATE(dsib, "tegradc.0", "dsib"),
-   TEGRA_CLK_DUPLICATE(dsia, "tegradc.1", "dsia"),
TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"),
TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"),
TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"),
@@ -1952,33 +1943,8 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] 
= {
TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL),
TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"),
TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"),
-   TEGRA_CLK_DUPLICATE(i2c1, "tegra-i2c-slave.0", NULL),
-   TEGRA_CLK_DUPLICATE(i2c2, "tegra-i2c-slave.1", NULL),
-   TEGRA_CLK_DUPLICATE(i2c3, "tegra-i2c-slave.2", NULL),
-   TEGRA_CLK_DUPLICATE(i2c4, "tegra-i2c-slave.3", NULL),
-   TEGRA_CLK_DUPLICATE(i2c5, "tegra-i2c-slave.4", NULL),
-   TEGRA_CLK_DUPLICATE(sbc1, "spi_slave_tegra.0", NULL),
-   TEGRA_CLK_DUPLICATE(sbc2, "spi_slave_tegra.1", NULL),
-   TEGRA_CLK_DUPLICATE(sbc3, "spi_slave_tegra.2", NULL),
-   TEGRA_CLK_DUPLICATE(sbc4, "spi_slave_tegra.3", NULL),
-   TEGRA_CLK_DUPLICATE(sbc5, "spi_slave_tegra.4", NULL),
-   TEGRA_CLK_DUPLICATE(sbc6, "spi_slave_tegra.5", NULL),
TEGRA_CLK_DUPLICATE(twd, "smp_twd", NULL),
TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"),
-   TEGRA_CLK_DUPLICATE(i2s0, NULL, "i2s0"),
-   TEGRA_CLK_DUPLICATE(i2s1, NULL, "i2s1"),
-   TEGRA_CLK_DUPLICATE(i2s2, NULL, "i2s2"),
-   TEGRA_CLK_DUPLICATE(i2s3, NULL, "i2s3"),
-   TEGRA_CLK_DUPLICATE(i2s4, NULL, "i2s4"),
-   TEGRA_CLK_DUPLICATE(dam0, NULL, "dam0"),
-   TEGRA_CLK_DUPLICATE(dam1, NULL, "dam1"),
-   TEGRA_CLK_DUPLICATE(dam2, NULL, "dam2"),
-   TEGRA_CLK_DUPLICATE(spdif_in, NULL, "spdif_in"),
-   TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.0", "fast-clk"),
-   TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.1", "fast-clk"),
-   TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.2", "fast-clk"),
-   TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.3", "fast-clk"),
-   TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.4", "fast-clk"),
TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */
 };
 
-- 
1.7.4.1

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[PATCH 5/7] arm: tegra30: remove auxdata

[Prashant Gaikwad]

Remove AUXDATA as clocks are initialized from device node.

Signed-off-by: Prashant Gaikwad 
---
 arch/arm/mach-tegra/board-dt-tegra30.c |   31 +--
 1 files changed, 1 insertions(+), 30 deletions(-)

diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c 
b/arch/arm/mach-tegra/board-dt-tegra30.c
index 35ddf72..5b58b64 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -38,38 +38,9 @@
 #include "common.h"
 #include "iomap.h"
 
-struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
-   OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x7800, "sdhci-tegra.0", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x7008, "tegra30-ahub", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x5000, "host1x", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x5420, "tegradc.0", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x5424, "tegradc.1", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x5428, "hdmi", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x5430, "dsi", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c, "tvo", NULL),
-   {}
-};
-
 static void __init tegra30_dt_init(void)
 {
-   of_platform_populate(NULL, of_default_bus_match_table,
-   tegra30_auxdata_lookup, NULL);
+   of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char *tegra30_dt_board_compat[] = {
-- 
1.7.4.1

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[PATCH 2/7] ARM: dt: tegra30: Add clock information

[Prashant Gaikwad]

Add clock information to device nodes.

Signed-off-by: Prashant Gaikwad 
---
 arch/arm/boot/dts/tegra30.dtsi |   52 +++-
 1 files changed, 51 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index e254d59..758962e 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -17,6 +17,7 @@
reg = <0x5000 0x00024000>;
interrupts = <0 65 0x04   /* mpcore syncpt */
  0 67 0x04>; /* mpcore general */
+   clocks = <_car 28>;
 
#address-cells = <1>;
#size-cells = <1>;
@@ -27,41 +28,48 @@
compatible = "nvidia,tegra30-mpe";
reg = <0x5404 0x0004>;
interrupts = <0 68 0x04>;
+   clocks = <_car 60>;
};
 
vi {
compatible = "nvidia,tegra30-vi";
reg = <0x5408 0x0004>;
interrupts = <0 69 0x04>;
+   clocks = <_car 164>;
};
 
epp {
compatible = "nvidia,tegra30-epp";
reg = <0x540c 0x0004>;
interrupts = <0 70 0x04>;
+   clocks = <_car 19>;
};
 
isp {
compatible = "nvidia,tegra30-isp";
reg = <0x5410 0x0004>;
interrupts = <0 71 0x04>;
+   clocks = <_car 23>;
};
 
gr2d {
compatible = "nvidia,tegra30-gr2d";
reg = <0x5414 0x0004>;
interrupts = <0 72 0x04>;
+   clocks = <_car 21>;
};
 
gr3d {
compatible = "nvidia,tegra30-gr3d";
reg = <0x5418 0x0004>;
+   clocks = <_car 24>;
};
 
dc@5420 {
compatible = "nvidia,tegra30-dc";
reg = <0x5420 0x0004>;
interrupts = <0 73 0x04>;
+   clocks = <_car 27>;
 
rgb {
status = "disabled";
@@ -72,6 +80,7 @@
compatible = "nvidia,tegra30-dc";
reg = <0x5424 0x0004>;
interrupts = <0 74 0x04>;
+   clocks = <_car 26>;
 
rgb {
status = "disabled";
@@ -83,6 +92,7 @@
reg = <0x5428 0x0004>;
interrupts = <0 75 0x04>;
status = "disabled";
+   clocks = <_car 51>;
};
 
tvo {
@@ -90,12 +100,14 @@
reg = <0x542c 0x0004>;
interrupts = <0 76 0x04>;
status = "disabled";
+   clocks = <_car 169>;
};
 
dsi {
compatible = "nvidia,tegra30-dsi";
reg = <0x5430 0x0004>;
status = "disabled";
+   clocks = <_car 48>;
};
};
 
@@ -174,6 +186,7 @@
  0 141 0x04
  0 142 0x04
  0 143 0x04>;
+   clocks = <_car 34>;
};
 
ahb: ahb {
@@ -219,6 +232,7 @@
interrupts = <0 36 0x04>;
nvidia,dma-request-selector = < 8>;
status = "disabled";
+   clocks = <_car 6>;
};
 
uartb: serial@70006040 {
@@ -228,6 +242,7 @@
interrupts = <0 37 0x04>;
nvidia,dma-request-selector = < 9>;
status = "disabled";
+   clocks = <_car 160>;
};
 
uartc: serial@70006200 {
@@ -237,6 +252,7 @@
interrupts = <0 46 0x04>;
nvidia,dma-request-selector = < 10>;
status = "disabled";
+   clocks = <_car 55>;
};
 
uartd: serial@70006300 {
@@ -246,6 +262,7 @@
interrupts = <0 90 0x04>;
nvidia,dma-requ

[PATCH 6/7] clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s

[Prashant Gaikwad]

With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.

Signed-off-by: Prashant Gaikwad 
---
 drivers/clk/tegra/clk-tegra20.c |   17 -
 1 files changed, 0 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index bb94556..92c1190 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1164,28 +1164,11 @@ static __initdata struct tegra_clk_init_table 
init_table[] = {
  * table under two names.
  */
 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
-   TEGRA_CLK_DUPLICATE(uarta,  "serial8250.0", NULL),
-   TEGRA_CLK_DUPLICATE(uartb,  "serial8250.1", NULL),
-   TEGRA_CLK_DUPLICATE(uartc,  "serial8250.2", NULL),
-   TEGRA_CLK_DUPLICATE(uartd,  "serial8250.3", NULL),
-   TEGRA_CLK_DUPLICATE(uarte,  "serial8250.4", NULL),
TEGRA_CLK_DUPLICATE(usbd,   "utmip-pad",NULL),
TEGRA_CLK_DUPLICATE(usbd,   "tegra-ehci.0", NULL),
TEGRA_CLK_DUPLICATE(usbd,   "tegra-otg",NULL),
-   TEGRA_CLK_DUPLICATE(hdmi,   "tegradc.0","hdmi"),
-   TEGRA_CLK_DUPLICATE(hdmi,   "tegradc.1","hdmi"),
-   TEGRA_CLK_DUPLICATE(host1x, "tegra_grhost", "host1x"),
-   TEGRA_CLK_DUPLICATE(gr2d,   "tegra_grhost", "gr2d"),
-   TEGRA_CLK_DUPLICATE(gr3d,   "tegra_grhost", "gr3d"),
-   TEGRA_CLK_DUPLICATE(epp,"tegra_grhost", "epp"),
-   TEGRA_CLK_DUPLICATE(mpe,"tegra_grhost", "mpe"),
-   TEGRA_CLK_DUPLICATE(vde,"tegra-aes","vde"),
TEGRA_CLK_DUPLICATE(cclk,   NULL,   "cpu"),
TEGRA_CLK_DUPLICATE(twd,"smp_twd",  NULL),
-   TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.0", "fast-clk"),
-   TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.1", "fast-clk"),
-   TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.2", "fast-clk"),
-   TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.3", "fast-clk"),
TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */
 };
 
-- 
1.7.4.1

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[PATCH 4/7] arm: tegra20: remove auxdata

[Prashant Gaikwad]

Remove AUXDATA as clock are initialized from device node.

Signed-off-by: Prashant Gaikwad 
---
 arch/arm/mach-tegra/board-dt-tegra20.c |   24 
 1 files changed, 0 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c 
b/arch/arm/mach-tegra/board-dt-tegra20.c
index c774a80..2b5fed7 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -70,36 +70,12 @@ struct tegra_ehci_platform_data tegra_ehci3_pdata = {
 };
 
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
-   OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, 
"sdhci-tegra.0", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, 
"sdhci-tegra.1", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, 
"sdhci-tegra.2", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, 
"sdhci-tegra.3", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, 
"tegra20-das", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
   _ehci1_pdata),
OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
   _ehci2_pdata),
OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
   _ehci3_pdata),
-   OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, 
"tegra-apbdma", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", 
NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x5000, "host1x", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x5420, "tegradc.0", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x5424, "tegradc.1", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x5428, "hdmi", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x5430, "dsi", NULL),
-   OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c, "tvo", NULL),
{}
 };
 
-- 
1.7.4.1

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[PATCH 1/7] ARM: dt: tegra20: Add clock information

[Prashant Gaikwad]

Add clock information to device nodes.

Signed-off-by: Prashant Gaikwad 
---
Tested on Ventana (Tegra20) and Cardhu (Tegra30).
This series depends on ccf-rework patch series.
---
 arch/arm/boot/dts/tegra20.dtsi |   41 
 1 files changed, 41 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index be3421d..8cc5295 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -17,6 +17,7 @@
reg = <0x5000 0x00024000>;
interrupts = <0 65 0x04   /* mpcore syncpt */
  0 67 0x04>; /* mpcore general */
+   clocks = <_car 28>;
 
#address-cells = <1>;
#size-cells = <1>;
@@ -27,41 +28,48 @@
compatible = "nvidia,tegra20-mpe";
reg = <0x5404 0x0004>;
interrupts = <0 68 0x04>;
+   clocks = <_car 60>;
};
 
vi {
compatible = "nvidia,tegra20-vi";
reg = <0x5408 0x0004>;
interrupts = <0 69 0x04>;
+   clocks = <_car 100>;
};
 
epp {
compatible = "nvidia,tegra20-epp";
reg = <0x540c 0x0004>;
interrupts = <0 70 0x04>;
+   clocks = <_car 19>;
};
 
isp {
compatible = "nvidia,tegra20-isp";
reg = <0x5410 0x0004>;
interrupts = <0 71 0x04>;
+   clocks = <_car 23>;
};
 
gr2d {
compatible = "nvidia,tegra20-gr2d";
reg = <0x5414 0x0004>;
interrupts = <0 72 0x04>;
+   clocks = <_car 21>;
};
 
gr3d {
compatible = "nvidia,tegra20-gr3d";
reg = <0x5418 0x0004>;
+   clocks = <_car 24>;
};
 
dc@5420 {
compatible = "nvidia,tegra20-dc";
reg = <0x5420 0x0004>;
interrupts = <0 73 0x04>;
+   clocks = <_car 27>;
 
rgb {
status = "disabled";
@@ -72,6 +80,7 @@
compatible = "nvidia,tegra20-dc";
reg = <0x5424 0x0004>;
interrupts = <0 74 0x04>;
+   clocks = <_car 26>;
 
rgb {
status = "disabled";
@@ -83,6 +92,7 @@
reg = <0x5428 0x0004>;
interrupts = <0 75 0x04>;
status = "disabled";
+   clocks = <_car 51>;
};
 
tvo {
@@ -90,12 +100,14 @@
reg = <0x542c 0x0004>;
interrupts = <0 76 0x04>;
status = "disabled";
+   clocks = <_car 102>;
};
 
dsi {
compatible = "nvidia,tegra20-dsi";
reg = <0x5430 0x0004>;
status = "disabled";
+   clocks = <_car 48>;
};
};
 
@@ -156,6 +168,7 @@
  0 117 0x04
  0 118 0x04
  0 119 0x04>;
+   clocks = <_car 34>;
};
 
ahb {
@@ -198,6 +211,7 @@
interrupts = <0 13 0x04>;
nvidia,dma-request-selector = < 2>;
status = "disabled";
+   clocks = <_car 11>;
};
 
tegra_i2s2: i2s@70002a00 {
@@ -206,6 +220,7 @@
interrupts = <0 3 0x04>;
nvidia,dma-request-selector = < 1>;
status = "disabled";
+   clocks = <_car 18>;
};
 
/*
@@ -222,6 +237,7 @@
interrupts = <0 36 0x04>;
nvidia,dma-request-selector = < 8>;
status = "disabled";
+   clocks = <_car 6>;
};
 
uartb: serial@70006040 {
@@ -231,6 +247,7 @@