from:"Rahul Tanwar"

Re: [PATCH] PCI: dwc/intel-gw: Fix enabling the legacy PCI interrupt lines

2021-04-09 Thread Rahul Tanwar

On 9/4/2021 4:40 am, Martin Blumenstingl wrote:
> This email was sent from outside of MaxLinear.
> 
> Hi Lorenzo,
> 
> On Tue, Mar 23, 2021 at 12:36 PM Lorenzo Pieralisi
>  wrote:
>  >
>  > On Wed, Jan 06, 2021 at 02:55:40PM +0100, Martin Blumenstingl wrote:
>  > > The legacy PCI interrupt lines need to be enabled using PCIE_APP_IRNEN
>  > > bits 13 (INTA), 14 (INTB), 15 (INTC) and 16 (INTD). The old code 
> however
>  > > was taking (for example) "13" as raw value instead of taking BIT(13).
>  > > Define the legacy PCI interrupt bits using the BIT() macro and then use
>  > > these in PCIE_APP_IRN_INT.
>  > >
>  > > Fixes: ed22aaaede44 ("PCI: dwc: intel: PCIe RC controller driver")
>  > > Signed-off-by: Martin Blumenstingl 
>  > > ---
>  > > drivers/pci/controller/dwc/pcie-intel-gw.c | 10 ++
>  > > 1 file changed, 6 insertions(+), 4 deletions(-)
>  > >
>  > > diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c 
> b/drivers/pci/controller/dwc/pcie-intel-gw.c
>  > > index 0cedd1f95f37..ae96bfbb6c83 100644
>  > > --- a/drivers/pci/controller/dwc/pcie-intel-gw.c
>  > > +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
>  > > @@ -39,6 +39,10 @@
>  > > #define PCIE_APP_IRN_PM_TO_ACK BIT(9)
>  > > #define PCIE_APP_IRN_LINK_AUTO_BW_STAT BIT(11)
>  > > #define PCIE_APP_IRN_BW_MGT BIT(12)
>  > > +#define PCIE_APP_IRN_INTA BIT(13)
>  > > +#define PCIE_APP_IRN_INTB BIT(14)
>  > > +#define PCIE_APP_IRN_INTC BIT(15)
>  > > +#define PCIE_APP_IRN_INTD BIT(16)
>  > > #define PCIE_APP_IRN_MSG_LTR BIT(18)
>  > > #define PCIE_APP_IRN_SYS_ERR_RC BIT(29)
>  > > #define PCIE_APP_INTX_OFST 12
>  > > @@ -48,10 +52,8 @@
>  > > PCIE_APP_IRN_RX_VDM_MSG | PCIE_APP_IRN_SYS_ERR_RC | \
>  > > PCIE_APP_IRN_PM_TO_ACK | PCIE_APP_IRN_MSG_LTR | \
>  > > PCIE_APP_IRN_BW_MGT | PCIE_APP_IRN_LINK_AUTO_BW_STAT | \
>  > > - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTA) | \
>  > > - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTB) | \
>  > > - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTC) | \
>  > > - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTD))
>  > > + PCIE_APP_IRN_INTA | PCIE_APP_IRN_INTB | \
>  > > + PCIE_APP_IRN_INTC | PCIE_APP_IRN_INTD)
>  > >
>  > > #define BUS_IATU_OFFSET SZ_256M
>  > > #define RESET_INTERVAL_MS 100
>  >
>  > This looks like a significant bug - which in turn raises the question
>  > on how well this driver has been tested.
> to give them the benefit of doubt: maybe only MSIs were tested
> 
>  > Dilip, can you review and ACK asap please ?
>  From "Re: MaxLinear, please maintain your drivers was Re: [PATCH]
> leds: lgm: fix gpiolib dependency" [0]:
>  > Please send any Lightning Mountain SoC related issues email to Rahul
>  > Tanwar (rtan...@maxlinear.com) and I will ensure that I address the
>  > issues in a timely manner.
> so I added rtan...@maxlinear.com to this email
> 
> 
> Best regards,
> Martin
> 
> 
> [0] https://lkml.org/lkml/2021/3/16/282 
> <https://lkml.org/lkml/2021/3/16/282>


Dilip has left the org. So not sure how exactly he tested it (maybe only 
MSIs). But i have confirmed it to be a bug. Thanks Martin for fixing it.

Acked-by: Rahul Tanwar 

Regards,
Rahul

[PATCH v2 0/1] leds: lgm: Address review concerns

2021-03-25 Thread Rahul Tanwar

Address below review concerns from Pavel:
1. Remove LEDS_BLINK Kconfig symbol.
2. Provide useful Kconfig help text for the driver.

This patch is based on "for-next" branch of kernel from below git tree:
git git://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds.git for-next

v2:
- Fix few code quality related review concerns (Randy Dunlap).
- Further improve Kconfig help text (Pavel).
- Switch back to original copyright (pavel).

v1:
- Initial version.

Rahul Tanwar (1):
  leds: lgm: Improve Kconfig help

 drivers/leds/Kconfig  |  5 ++---
 drivers/leds/Makefile |  2 +-
 drivers/leds/blink/Kconfig| 28 +---
 drivers/leds/blink/Makefile   |  2 +-
 drivers/leds/blink/leds-lgm-sso.c |  4 ++--
 5 files changed, 19 insertions(+), 22 deletions(-)

--
2.17.1



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[PATCH v2 1/1] leds: lgm: Improve Kconfig help

2021-03-25 Thread Rahul Tanwar

Remove unnecessary Kconfig symbol LEDS_BLINK
Improve Kconfig help text to make it more useful.

Signed-off-by: Rahul Tanwar 
---
 drivers/leds/Kconfig  |  5 ++---
 drivers/leds/Makefile |  2 +-
 drivers/leds/blink/Kconfig| 28 +---
 drivers/leds/blink/Makefile   |  2 +-
 drivers/leds/blink/leds-lgm-sso.c |  4 ++--
 5 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index b6742b4231bf..4ca8cd594518 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -928,13 +928,12 @@ config LEDS_ACER_A500
  This option enables support for the Power Button LED of
  Acer Iconia Tab A500.

+source "drivers/leds/blink/Kconfig"
+
 comment "Flash and Torch LED drivers"
 source "drivers/leds/flash/Kconfig"

 comment "LED Triggers"
 source "drivers/leds/trigger/Kconfig"

-comment "LED Blink"
-source "drivers/leds/blink/Kconfig"
-
 endif # NEW_LEDS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 2a698df9da57..7e604d3028c8 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -110,4 +110,4 @@ obj-$(CONFIG_LEDS_CLASS_FLASH)  += flash/
 obj-$(CONFIG_LEDS_TRIGGERS)+= trigger/

 # LED Blink
-obj-$(CONFIG_LEDS_BLINK)+= blink/
+obj-y  += blink/
diff --git a/drivers/leds/blink/Kconfig b/drivers/leds/blink/Kconfig
index 6dedc58c47b3..8a11f9acd1a7 100644
--- a/drivers/leds/blink/Kconfig
+++ b/drivers/leds/blink/Kconfig
@@ -1,21 +1,19 @@
-menuconfig LEDS_BLINK
-   bool "LED Blink support"
-   depends on LEDS_CLASS
-   help
- This option enables blink support for the leds class.
- If unsure, say Y.
-
-if LEDS_BLINK
-
-config LEDS_BLINK_LGM
-   tristate "LED support for Intel LGM SoC series"
+config LEDS_LGM
+   tristate "LED support for LGM SoC series"
depends on GPIOLIB
depends on LEDS_CLASS
depends on MFD_SYSCON
depends on OF
help
- Parallel to serial conversion, which is also called SSO controller,
- can drive external shift register for LED outputs.
- This enables LED support for Serial Shift Output controller(SSO).
+ This option enables support for LEDs connected to GPIO lines on
+ Lightning Mountain (LGM) SoC. Lightning Mountain is a AnyWAN
+ gateway-on-a-chip SoC to be shipped on mid and high end home
+ gateways and routers.
+
+ These LEDs are driven by a Serial Shift Output (SSO) controller.
+ The driver supports hardware blinking and the LEDs can be configured
+ to be triggered by software/CPU or by hardware.

-endif # LEDS_BLINK
+ Say 'Y' here if you are working on LGM SoC based platform. Otherwise,
+ say 'N'. To compile this driver as a module, choose M here: the module
+ will be called leds-lgm-sso.
diff --git a/drivers/leds/blink/Makefile b/drivers/leds/blink/Makefile
index 2fa6c7b7b67e..fa5d04dccf13 100644
--- a/drivers/leds/blink/Makefile
+++ b/drivers/leds/blink/Makefile
@@ -1,2 +1,2 @@
 # SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_LEDS_BLINK_LGM)   += leds-lgm-sso.o
+obj-$(CONFIG_LEDS_LGM) += leds-lgm-sso.o
diff --git a/drivers/leds/blink/leds-lgm-sso.c 
b/drivers/leds/blink/leds-lgm-sso.c
index 7d5c9ca007d6..e78792c90117 100644
--- a/drivers/leds/blink/leds-lgm-sso.c
+++ b/drivers/leds/blink/leds-lgm-sso.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Intel Lightning Mountain SoC LED Serial Shift Output Controller driver
+ * Lightning Mountain SoC LED Serial Shift Output Controller driver
  *
- * Copyright (c) 2020 Intel Corporation.
+ * Copyright (c) 2021 Intel Corporation.
  */

 #include 
--
2.17.1



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Re: [PATCH 1/1] leds: lgm: Improve Kconfig help

2021-03-18 Thread Rahul Tanwar

Hi Pavel,

On 19/3/2021 4:37 am, Pavel Machek wrote:
> Hi!
> 
> 
>  > > > help
>  > > > - Parallel to serial conversion, which is also called SSO
>  > > > controller,
>  > > > - can drive external shift register for LED outputs.
>  > > > - This enables LED support for Serial Shift Output controller(SSO).
>  > > > + This option enables support for LEDs connected to GPIO lines on
>  > > > + Lightning Mountain(LGM) SoC. These LEDs are driven by a Serial
>  > > > + Shift Output(SSO) controller. The driver supports hardware
>  > >
>  > > What is Lightning Mountain? The codename is not widely known. Where
>  > > can we find that hardware? Notebooks? Phones? Only some development
>  > > boards?
>  > >
>  >
>  > Lightning Mountain is generically a network processor with a primary
>  > targeted application as Gateway SoC. It has already been added as a
>  > valid Intel Atom processor variant in
>  > arch/x86/include/asm/intel-family.h as below:
> 
> Yep, but Kconfig users are not going to read header files.
> 
> If the SoC is not shipping in any products, state so.
> 


Got your point. Will update the help text.


>  > > > *
>  > > > - * Copyright (c) 2020 Intel Corporation.
>  > > > + * Copyright (c) 2021 MaxLinear, Inc.
>  > > > */
>  > > >
>  > >
>  > > I don't think you can do that, and I don't think you should be doing
>  > > it in the same patch.
>  >
>  > Well noted. Will revert it back now and update later in a separate
>  > patch. Thanks.
> 
> Don't. You can't update copyright like that.
>

Well noted.

Regards,
Rahul


> Pavel
> -- 
> http://www.livejournal.com/~pavelmachek 
>

Re: [PATCH 1/1] leds: lgm: Improve Kconfig help

2021-03-18 Thread Rahul Tanwar

Hi Pavel,

On 18/3/2021 3:55 pm, Pavel Machek wrote:
> Hi!
> 
>  > Remove unnecessary Kconfig symbol LEDS_BLINK
>  > Improve Kconfig help text to make it more useful.
>  >
>  > Signed-off-by: Rahul Tanwar 
> 
>  > +++ b/drivers/leds/blink/Kconfig
>  > @@ -1,21 +1,19 @@
>  > -menuconfig LEDS_BLINK
>  > - bool "LED Blink support"
>  > - depends on LEDS_CLASS
>  > - help
>  > - This option enables blink support for the leds class.
>  > - If unsure, say Y.
>  > -
>  > -if LEDS_BLINK
>  > -
>  > -config LEDS_BLINK_LGM
>  > - tristate "LED support for Intel LGM SoC series"
>  > +config LEDS_LGM
>  > + tristate "LED support for LGM SoC series"
>  > depends on GPIOLIB
>  > depends on LEDS_CLASS
>  > depends on MFD_SYSCON
>  > depends on OF
>  > help
>  > - Parallel to serial conversion, which is also called SSO
>  > controller,
>  > - can drive external shift register for LED outputs.
>  > - This enables LED support for Serial Shift Output controller(SSO).
>  > + This option enables support for LEDs connected to GPIO lines on
>  > + Lightning Mountain(LGM) SoC. These LEDs are driven by a Serial
>  > + Shift Output(SSO) controller. The driver supports hardware
> 
> What is Lightning Mountain? The codename is not widely known. Where
> can we find that hardware? Notebooks? Phones? Only some development
> boards?
> 

Lightning Mountain is generically a network processor with a primary 
targeted application as Gateway SoC. It has already been added as a 
valid Intel Atom processor variant in 
arch/x86/include/asm/intel-family.h as below:

#define INTEL_FAM6_ATOM_AIRMONT_NP  0x75 /* Lightning Mountain */

Please see [1].


> If user is not likely to need the driver, say so.
> 
>  > + blinking with a configurable LED update/blink frequency in two
>  > + modes, 2/4/8/10 Hz in low speed mode and 50/100/200/250
>  > KHz in
> 
> kHz? But I guess we don't need that here.
>

Well noted. Will update in V2.


>  > *
>  > - * Copyright (c) 2020 Intel Corporation.
>  > + * Copyright (c) 2021 MaxLinear, Inc.
>  > */
>  >
> 
> I don't think you can do that, and I don't think you should be doing
> it in the same patch.


Well noted. Will revert it back now and update later in a separate 
patch. Thanks.


> 

Regards,
Rahul

[1] 
https://github.com/torvalds/linux/blob/master/arch/x86/include/asm/intel-family.h

Re: [PATCH 1/1] leds: lgm: Improve Kconfig help

2021-03-18 Thread Rahul Tanwar

Hi Randy,

On 18/3/2021 11:02 am, Randy Dunlap wrote:
> This email was sent from outside of MaxLinear.
> 
> 
> Hi,
> 
> For the leds/blink/Kconfig file at least, something has
> changed all of the tabs to spaces.
> 
> Keywords in Kconfig files should be indented with one tab,
> while help text should be indented with one tab + 2 spaces.
>


Hmm, facing some IT issues with git send-email so i had to send it by 
other means. I will fix it in V1 by ensuring that i send using git.


> 
> On 3/17/21 3:04 AM, Rahul Tanwar wrote:
>> Remove unnecessary Kconfig symbol LEDS_BLINK
>> Improve Kconfig help text to make it more useful.
>>
>> Signed-off-by: Rahul Tanwar 
>> ---
>>
>> diff --git a/drivers/leds/blink/Kconfig b/drivers/leds/blink/Kconfig
>> index 6dedc58c47b3..2de2973fbc6b 100644
>> --- a/drivers/leds/blink/Kconfig
>> +++ b/drivers/leds/blink/Kconfig
>> @@ -1,21 +1,19 @@
>> -menuconfig LEDS_BLINK
>> -   bool "LED Blink support"
>> -   depends on LEDS_CLASS
>> -   help
>> - This option enables blink support for the leds class.
>> - If unsure, say Y.
>> -
>> -if LEDS_BLINK
>> -
>> -config LEDS_BLINK_LGM
>> -   tristate "LED support for Intel LGM SoC series"
>> +config LEDS_LGM
>> +   tristate "LED support for LGM SoC series"
>>   depends on GPIOLIB
>>   depends on LEDS_CLASS
>>   depends on MFD_SYSCON
>>   depends on OF
>>   help
>> - Parallel to serial conversion, which is also called SSO
>> controller,
>> - can drive external shift register for LED outputs.
>> - This enables LED support for Serial Shift Output controller(SSO).
>> + This option enables support for LEDs connected to GPIO lines on
>> + Lightning Mountain(LGM) SoC. These LEDs are driven by a Serial
> 
>Mountain (LGM)
> 
>> + Shift Output(SSO) controller. The driver supports hardware
> 
>Output (SSO)
> 
>> + blinking with a configurable LED update/blink frequency in two
>> + modes, 2/4/8/10 Hz in low speed mode and 50/100/200/250 KHz in
>> + high speed mode. The LEDs can be configured to be triggered by
>> + SW/CPU or by hardware. Say 'Y' here if you are working on LGM
> 
> Please spell out "software".
> 
>> + SoC based platform.
>> +
>> + To compile this driver as a module, choose M here: the
>> + module will be called leds-lgm-sso.
>>
>> -endif # LEDS_BLINK
> 

Well noted about above improvements suggestions. Shall update in V1. Thanks.

Regards,
Rahul

> thanks.
> --
> ~Randy
> 
>

[PATCH 0/1] leds: lgm: Address review concerns

2021-03-17 Thread Rahul Tanwar

Address below review concerns from Pavel:
1. Remove LEDS_BLINK Kconfig symbol.
2. Provide useful Kconfig help text for the driver.

This patch is based on "for-next" branch of kernel from below git tree:
git git://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds.git 
for-next

Rahul Tanwar (1):
   leds: lgm: Improve Kconfig help

  drivers/leds/Kconfig  |  5 ++---
  drivers/leds/Makefile |  2 +-
  drivers/leds/blink/Kconfig| 28 +---
  drivers/leds/blink/Makefile   |  2 +-
  drivers/leds/blink/leds-lgm-sso.c |  4 ++--
  5 files changed, 19 insertions(+), 22 deletions(-)

--
2.17.1

[PATCH 1/1] leds: lgm: Improve Kconfig help

2021-03-17 Thread Rahul Tanwar

Remove unnecessary Kconfig symbol LEDS_BLINK
Improve Kconfig help text to make it more useful.

Signed-off-by: Rahul Tanwar 
---
  drivers/leds/Kconfig  |  5 ++---
  drivers/leds/Makefile |  2 +-
  drivers/leds/blink/Kconfig| 28 +---
  drivers/leds/blink/Makefile   |  2 +-
  drivers/leds/blink/leds-lgm-sso.c |  4 ++--
  5 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index b6742b4231bf..4ca8cd594518 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -928,13 +928,12 @@ config LEDS_ACER_A500
   This option enables support for the Power Button LED of
   Acer Iconia Tab A500.

+source "drivers/leds/blink/Kconfig"
+
  comment "Flash and Torch LED drivers"
  source "drivers/leds/flash/Kconfig"

  comment "LED Triggers"
  source "drivers/leds/trigger/Kconfig"

-comment "LED Blink"
-source "drivers/leds/blink/Kconfig"
-
  endif # NEW_LEDS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 2a698df9da57..7e604d3028c8 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -110,4 +110,4 @@ obj-$(CONFIG_LEDS_CLASS_FLASH)  += flash/
  obj-$(CONFIG_LEDS_TRIGGERS)+= trigger/

  # LED Blink
-obj-$(CONFIG_LEDS_BLINK)+= blink/
+obj-y  += blink/
diff --git a/drivers/leds/blink/Kconfig b/drivers/leds/blink/Kconfig
index 6dedc58c47b3..2de2973fbc6b 100644
--- a/drivers/leds/blink/Kconfig
+++ b/drivers/leds/blink/Kconfig
@@ -1,21 +1,19 @@
-menuconfig LEDS_BLINK
-   bool "LED Blink support"
-   depends on LEDS_CLASS
-   help
- This option enables blink support for the leds class.
- If unsure, say Y.
-
-if LEDS_BLINK
-
-config LEDS_BLINK_LGM
-   tristate "LED support for Intel LGM SoC series"
+config LEDS_LGM
+   tristate "LED support for LGM SoC series"
 depends on GPIOLIB
 depends on LEDS_CLASS
 depends on MFD_SYSCON
 depends on OF
 help
- Parallel to serial conversion, which is also called SSO 
controller,
- can drive external shift register for LED outputs.
- This enables LED support for Serial Shift Output controller(SSO).
+ This option enables support for LEDs connected to GPIO lines on
+ Lightning Mountain(LGM) SoC. These LEDs are driven by a Serial
+ Shift Output(SSO) controller. The driver supports hardware
+ blinking with a configurable LED update/blink frequency in two
+ modes, 2/4/8/10 Hz in low speed mode and 50/100/200/250 KHz in
+ high speed mode. The LEDs can be configured to be triggered by
+ SW/CPU or by hardware. Say 'Y' here if you are working on LGM
+ SoC based platform.
+
+ To compile this driver as a module, choose M here: the
+ module will be called leds-lgm-sso.

-endif # LEDS_BLINK
diff --git a/drivers/leds/blink/Makefile b/drivers/leds/blink/Makefile
index 2fa6c7b7b67e..fa5d04dccf13 100644
--- a/drivers/leds/blink/Makefile
+++ b/drivers/leds/blink/Makefile
@@ -1,2 +1,2 @@
  # SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_LEDS_BLINK_LGM)   += leds-lgm-sso.o
+obj-$(CONFIG_LEDS_LGM) += leds-lgm-sso.o
diff --git a/drivers/leds/blink/leds-lgm-sso.c 
b/drivers/leds/blink/leds-lgm-sso.c
index 7d5c9ca007d6..e41143a87e20 100644
--- a/drivers/leds/blink/leds-lgm-sso.c
+++ b/drivers/leds/blink/leds-lgm-sso.c
@@ -1,8 +1,8 @@
  // SPDX-License-Identifier: GPL-2.0
  /*
- * Intel Lightning Mountain SoC LED Serial Shift Output Controller driver
+ * Lightning Mountain SoC LED Serial Shift Output Controller driver
   *
- * Copyright (c) 2020 Intel Corporation.
+ * Copyright (c) 2021 MaxLinear, Inc.
   */

  #include 
--
2.17.1

Re: MaxLinear, please maintain your drivers was Re: [PATCH] leds: lgm: fix gpiolib dependency

2021-03-16 Thread Rahul Tanwar

Hi Arnd,

On 11/3/2021 6:01 pm, Arnd Bergmann wrote:
> This email was sent from outside of MaxLinear.
> 
> On Thu, Mar 11, 2021 at 6:48 AM Rahul Tanwar  wrote:
>  > Hi Arnd, Pavel,
>  >
>  > Sorry for the hiccup due to missing email address in the email chain 
> during the ownership transition.
>  >
>  > Henceforth, I will be the maintainer for all kernel drivers/code 
> related to “formerly Intel’s now MaxLinear’s” Lightning Mountain SoC.
>  >
>  > Please send any Lightning Mountain SoC related issues email to Rahul 
> Tanwar (rtan...@maxlinear.com) and I will ensure that I address the 
> issues in a timely manner.
> 
> Thank you for the reply and for stepping up as maintainer.
> 
> I tend to merge updates to the MAINTAINERS file as bugfixes the file 
> contains
> the correct addresses at all times. If you sent an update for this to
> s...@kernel.org,
> I'll get that merged.
> 
> Since I think this is an x86 platform, you can alternatively send the 
> same patch
> to the x86 maintainers.
>


Haven't sent any patch to update MAINTAINERS file yet. Thanks for your 
suggestion. I will take it up soon..


> Are you also planning to maintain or add drivers for some of the older SoC
> generations from Ti/Lantiq/Infineon/Intel that are now owned by MaxLinear?
> It would be good to be explicit about which ones of these you are working
> with. From what I can tell, the arch/mips/lantiq/ platform is only for 
> fairly
> old designs (xrx200 and older), while support for the slightly later mips
> and x86 based chips was submitted a few years ago but never merged.
> 

Thank you for asking. At this point of time, our focus for upstreaming 
and maintaining is on LGM(Lightning Mountain) SoC.

Regards,
Rahul

>  > I will wait for more details on your fix request for LGM LED driver. 
> Thanks.
> 
>  From my side, only an Ack on the original bugfix I sent [1] is needed, but
> Pavel had other concerns about the driver. I expect he will follow up on 
> those
> with you.
> 
> Arnd
> 
> [1] 
> https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org/ 
> <https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org>

Re: [PATCH] leds: lgm: fix gpiolib dependency

2021-03-16 Thread Rahul Tanwar

On 15/3/2021 5:44 pm, Rahul Tanwar wrote:
> From: Arnd Bergmann
> To: Pavel Machek,
>   Amireddy Mallikarjuna reddy
>   
> Cc: Arnd Bergmann, Dan Murphy,
>   linux-l...@vger.kernel.org,linux-kernel@vger.kernel.org
> Subject:[PATCH] leds: lgm: fix gpiolib dependency  
> <https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org/#r>
> Date: Mon,  8 Mar 2021 16:30:46 +0100
> Message-ID:<20210308153052.2353885-1-a...@kernel.org>  (raw  
> <https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org/raw>)
> 
> From: Arnd Bergmann
> 
> Without gpiolib, the driver fails to build:
> 
>  drivers/leds/blink/leds-lgm-sso.c:123:19: error: field has incomplete 
> type 'struct gpio_chip'
>  struct gpio_chip chip;
>   ^
>  include/linux/gpio.h:107:8: note: forward declaration of 'struct 
> gpio_chip'
>  struct gpio_chip;
> ^
>  drivers/leds/blink/leds-lgm-sso.c:263:3: error: implicit declaration of 
> function 'gpiod_set_value' [-Werror,-Wimplicit-function-declaration]
>  gpiod_set_value(led->gpiod, val);
>  ^
>  drivers/leds/blink/leds-lgm-sso.c:263:3: note: did you mean 
> 'gpio_set_value'?
>  include/linux/gpio.h:168:20: note: 'gpio_set_value' declared here
>  static inline void gpio_set_value(unsigned gpio, int value)
> ^
>  drivers/leds/blink/leds-lgm-sso.c:345:3: error: implicit declaration of 
> function 'gpiod_set_value' [-Werror,-Wimplicit-function-declaration]
>  gpiod_set_value(led->gpiod, 1);
>  ^
> 
> Add the dependency in Kconfig.
> 
> Fixes: c3987cd2bca3 ("leds: lgm: Add LED controller driver for LGM SoC")
> Signed-off-by: Arnd Bergmann
> ---
>   drivers/leds/blink/Kconfig  
> <https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org/#Z30drivers:leds:blink:Kconfig>
>   | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff 
> <https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org/#iZ30drivers:leds:blink:Kconfig>
>  
> --git a/drivers/leds/blink/Kconfig b/drivers/leds/blink/Kconfig index 
> 265b53476a80..6dedc58c47b3 100644 --- a/drivers/leds/blink/Kconfig +++ 
> b/drivers/leds/blink/Kconfig @@ -9,6 +9,7 @@ if LEDS_BLINK   
>   config LEDS_BLINK_LGM
>   tristate "LED support for Intel LGM SoC series"
> + depends on GPIOLIB  depends on LEDS_CLASS
>   depends on MFD_SYSCON
>   depends on OF
> -- 
> 2.29.2
> 

Acked-by: Rahul Tanwar

TEST EMAIL - PLEASE IGNORE

2021-03-16 Thread Rahul Tanwar

On 15/3/2021 5:44 pm, Rahul Tanwar wrote:
> From: Arnd Bergmann
> To: Pavel Machek,
>   Amireddy Mallikarjuna reddy
>   
> Cc: Arnd Bergmann, Dan Murphy,
>   linux-l...@vger.kernel.org,linux-kernel@vger.kernel.org
> Subject:[PATCH] leds: lgm: fix gpiolib dependency  
> <https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org/#r>
> Date: Mon,  8 Mar 2021 16:30:46 +0100
> Message-ID:<20210308153052.2353885-1-a...@kernel.org>  (raw  
> <https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org/raw>)
> 
> From: Arnd Bergmann
> 
> Without gpiolib, the driver fails to build:
> 
>  drivers/leds/blink/leds-lgm-sso.c:123:19: error: field has incomplete 
> type 'struct gpio_chip'
>  struct gpio_chip chip;
>   ^
>  include/linux/gpio.h:107:8: note: forward declaration of 'struct 
> gpio_chip'
>  struct gpio_chip;
> ^
>  drivers/leds/blink/leds-lgm-sso.c:263:3: error: implicit declaration of 
> function 'gpiod_set_value' [-Werror,-Wimplicit-function-declaration]
>  gpiod_set_value(led->gpiod, val);
>  ^
>  drivers/leds/blink/leds-lgm-sso.c:263:3: note: did you mean 
> 'gpio_set_value'?
>  include/linux/gpio.h:168:20: note: 'gpio_set_value' declared here
>  static inline void gpio_set_value(unsigned gpio, int value)
> ^
>  drivers/leds/blink/leds-lgm-sso.c:345:3: error: implicit declaration of 
> function 'gpiod_set_value' [-Werror,-Wimplicit-function-declaration]
>  gpiod_set_value(led->gpiod, 1);
>  ^
> 
> Add the dependency in Kconfig.
> 
> Fixes: c3987cd2bca3 ("leds: lgm: Add LED controller driver for LGM SoC")
> Signed-off-by: Arnd Bergmann
> ---
>   drivers/leds/blink/Kconfig  
> <https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org/#Z30drivers:leds:blink:Kconfig>
>   | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff 
> <https://lore.kernel.org/lkml/20210308153052.2353885-1-a...@kernel.org/#iZ30drivers:leds:blink:Kconfig>
>  
> --git a/drivers/leds/blink/Kconfig b/drivers/leds/blink/Kconfig index 
> 265b53476a80..6dedc58c47b3 100644 --- a/drivers/leds/blink/Kconfig +++ 
> b/drivers/leds/blink/Kconfig @@ -9,6 +9,7 @@ if LEDS_BLINK   
>   config LEDS_BLINK_LGM
>   tristate "LED support for Intel LGM SoC series"
> + depends on GPIOLIB  depends on LEDS_CLASS
>   depends on MFD_SYSCON
>   depends on OF
> -- 
> 2.29.2
> 


Acked-by: Rahul Tanwar

TEST - please ignore

2021-03-10 Thread Rahul Tanwar

[PATCH v15 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-11-04 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..11a606536169
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v15 2/2] Add PWM fan controller driver for LGM SoC

2020-11-04 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
Reviewed-by: Andy Shevchenko 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 244 
 3 files changed, 256 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 63be5362fd3a..7218bf3665bc 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on HAS_IOMEM
+   depends on (OF && X86) || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index cbdcd55d69ee..71beaff894c1 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..e9e54dda07aa
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period & configures only 2-wire mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NS(40 * NSEC_PER_MSEC)
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /* The hardware only supports normal polarity and fixed period. */
+   if (state->polarity != PWM_POLARITY_NORMAL || state->period < 
pc->period)
+   return -EINVAL;
+
+   if (!state->enabled)
+   return lgm_pwm_enable(chip, 0);
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+   ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, 
LGM_PWM_FAN_DC_MSK,
+FIELD_PREP(LGM_PWM_FAN_DC_MSK, val));
+   if (ret)
+   return re

[PATCH v15 0/2] pwm: intel: Add PWM driver for a new SoC

2020-11-04 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

v15:
- Rebase to latest linux 5.10-rc2

v14:
- Address below review concerns from Uwe Kleine-K?nig.
 * Add limitations info about fixed 2-wire mode support.
 * Rename clk/reset _disable function names to _release.
 * Remove clk & rst from driver data structure. Instead
   use them as arguments.
 * Add pwm_chip.base = -1.
- Resolve missing MODULE_LICENSE warning.

v13:
- Address below review concerns (Philipp Zabel)
 * Make unnecessary 2 line comment as 1 line comment.
 * Move reset_deassert at the last after clk_enable.
 * Remove unnecessary return ret statement from .remove()
- Move platform_set_drvdata() at the top of probe. 

v12:
- Rebase to linux 5.9-rc4
- Add Reviewed-by tags from Andy Shevchenko & Rob Herring.

v11:
- Address below review concerns (Andy Shevchenko)
  * Fix a issue with dev_err_probe() usage & improve the usage.
  * Fix & improve a ordering issue with clk_enable/disable &
reset_control assert/deassert.

v10:
- Removed unused of_device.h and added platform_device.h
  & mod_devicetable.h

v9:
- Address code quality related review concerns (Andy Shevchenko)
- Use devm_add_action_or_reset() instead of explicit unwind calls.

v8:
- Remove fan related optional properties usage, keep
  them as default. If needed, change pwm-fan driver
  separately in future to add them as generic properties.

v7:
- Address code quality related review concerns.
- Rename fan related property to pwm-*.
- Fix one make dt_binding_check reported error.

v6:
- Readjust .apply op as per review feedback.
- Add back pwm-cells property to resolve make dt_binding_check error.
  pwm-cells is a required property for PWM driver.
- Add back fan related optional properties.

v5:
- Address below review concerns from Uwe Kleine-K?nig.
  * Improve comments about Limitations.
  * Use return value of regmap_update_bits if container function returns
error code.
  * Modify .apply op to have strict checking for fixed period supported
by PWM HW.
  * Use u64 as type when use min_t for duty_cycle.
  * Add reset_control_assert() in failure case in probe where it was missing
earlier.
- Remove fan specific optional properties from pwm dt binding document (Rob 
Herring)

v4:
- Address below review concerns from Uwe Kleine-K?nig.
  * Improve notes and limitations comments.
  * Add common prefixes for all #defines.
  * Modify/Improve logic in .apply & .get_state ops as advised.
  * Skip error messages in probe when error is -EPROBE_DEFER.
  * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
  * Address other code quality related review concerns.
- Fix make dt_binding_check reported error in YAML file.

v3:
- Address below review concerns from Uwe Kleine-K?nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K?nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  44 
 drivers/pwm/Kconfig|  11 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 244 +
 4 files changed, 300 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v5 0/2] Add hwmon driver for Moortec PVT controller

2020-10-05 Thread Rahul Tanwar

Patch 1 adds DT bindings schema in YAML format.
Patch 2 adds driver for MR75203 PVT controller.

v5:
- Add bits.h header.
- Use memset32() instead of using loop.
- Address other code quality related review concerns.
- Add Reviewed-by tags.

v4:
- Fix a spelling mistake in comments.
- Add return value error checking for all regmap_reads/writes.
- Remove unnecessary else statement and a validation check.

v3:
- Resolve make dt_binding_check errors.
- Add vendor prefix and type reference for one property in yaml schema.
- Update new property name in the driver.

v2:
- Address below review concerns from Andy Shevchenko
 * Add more info in comments for clamp_val usage for clk sys cycles.
 * Add mod_devicetable.h & property.h and remove of.h
 * Remove unnecessary additional mutex lock from driver. Rely on regmap's
   internal lock.
 * Use units in timeout macros.
 * Use HZ_PER_MHZ instead of direct values.
 * Use devm_platform_ioremap_resource_byname() instead of separate calls.
 * Use device property read API instead of OF API.
- Address below review concerns from Guenter Roeck
 * Improve commit message - add hardware monitoring driver.
 * Remove unnecessary platform_set_drvdata. Instead add driver data in
   function args at one place where it is used. Fix a issue related to it.
 * Remove unnecessary NULL assignment.
- Address below review concerns from Philipp Zabel
 * Switch to devm_reset_control_get_exclusive().
 * Move reset_deassert at the last after clk_enable in probe.
- Resolve make dt_binding_check error.
- Add MODULE_LICENSE

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings schema for PVT controller
  Add hardware monitoring driver for Moortec MR75203 PVT controller

 .../devicetree/bindings/hwmon/moortec,mr75203.yaml |  71 +++
 drivers/hwmon/Kconfig  |  10 +
 drivers/hwmon/Makefile |   1 +
 drivers/hwmon/mr75203.c| 656 +
 4 files changed, 738 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
 create mode 100644 drivers/hwmon/mr75203.c

-- 
2.11.0

[PATCH v5 1/2] Add DT bindings schema for PVT controller

2020-10-05 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature sensor(TS),
voltage monitor(VM) & process detector(PD) modules.

Add DT bindings schema for PVT controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/hwmon/moortec,mr75203.yaml | 71 ++
 1 file changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml

diff --git a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml 
b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
new file mode 100644
index ..6f3e3c01f717
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/moortec,mr75203.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Moortec Semiconductor MR75203 PVT Controller bindings
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: moortec,mr75203
+
+  reg:
+items:
+  - description: PVT common registers
+  - description: PVT temprature sensor registers
+  - description: PVT process detector registers
+  - description: PVT voltage monitor registers
+
+  reg-names:
+items:
+  - const: common
+  - const: ts
+  - const: pd
+  - const: vm
+
+  intel,vm-map:
+description:
+  PVT controller has 5 VM (voltage monitor) sensors.
+  vm-map defines CPU core to VM instance mapping. A
+  value of 0xff means that VM sensor is unused.
+$ref: /schemas/types.yaml#definitions/uint8-array
+maxItems: 5
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  "#thermal-sensor-cells":
+const: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - intel,vm-map
+  - clocks
+  - resets
+  - "#thermal-sensor-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+pvt: pvt@e068 {
+compatible = "moortec,mr75203";
+reg = <0xe068 0x80>,
+  <0xe0680080 0x180>,
+  <0xe0680200 0x200>,
+  <0xe0680400 0xc00>;
+reg-names = "common", "ts", "pd", "vm";
+intel,vm-map = [03 01 04 ff ff];
+clocks = <>;
+resets = < 0x40 7>;
+#thermal-sensor-cells = <1>;
+};
-- 
2.11.0

[PATCH v5 2/2] Add hardware monitoring driver for Moortec MR75203 PVT controller

2020-10-05 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature
sensor(TS), voltage monitor(VM) & process detector(PD)
modules. Add hardware monitoring driver to support
MR75203 PVT controller.

Signed-off-by: Rahul Tanwar 
Reviewed-by: Guenter Roeck 
Reviewed-by: Andy Shevchenko 
---
 drivers/hwmon/Kconfig   |  10 +
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/mr75203.c | 656 
 3 files changed, 667 insertions(+)
 create mode 100644 drivers/hwmon/mr75203.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 8dc28b26916e..2defb46677b4 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1112,6 +1112,16 @@ config SENSORS_MENF21BMC_HWMON
  This driver can also be built as a module. If so the module
  will be called menf21bmc_hwmon.
 
+config SENSORS_MR75203
+   tristate "Moortec Semiconductor MR75203 PVT Controller"
+   select REGMAP_MMIO
+   help
+ If you say yes here you get support for Moortec MR75203
+ PVT controller.
+
+ This driver can also be built as a module. If so, the module
+ will be called mr75203.
+
 config SENSORS_ADCXX
tristate "National Semiconductor ADCxxxSxxx"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index a8f4b35b136b..bb4bd92a5149 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -142,6 +142,7 @@ obj-$(CONFIG_SENSORS_MCP3021)   += mcp3021.o
 obj-$(CONFIG_SENSORS_TC654)+= tc654.o
 obj-$(CONFIG_SENSORS_MLXREG_FAN) += mlxreg-fan.o
 obj-$(CONFIG_SENSORS_MENF21BMC_HWMON) += menf21bmc_hwmon.o
+obj-$(CONFIG_SENSORS_MR75203)  += mr75203.o
 obj-$(CONFIG_SENSORS_NCT6683)  += nct6683.o
 obj-$(CONFIG_SENSORS_NCT6775)  += nct6775.o
 obj-$(CONFIG_SENSORS_NCT7802)  += nct7802.o
diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c
new file mode 100644
index ..18da5a25e89a
--- /dev/null
+++ b/drivers/hwmon/mr75203.c
@@ -0,0 +1,656 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MaxLinear, Inc.
+ *
+ * This driver is a hardware monitoring driver for PVT controller
+ * (MR75203) which is used to configure & control Moortec embedded
+ * analog IP to enable multiple embedded temperature sensor(TS),
+ * voltage monitor(VM) & process detector(PD) modules.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PVT Common register */
+#define PVT_IP_CONFIG  0x04
+#define TS_NUM_MSK GENMASK(4, 0)
+#define TS_NUM_SFT 0
+#define PD_NUM_MSK GENMASK(12, 8)
+#define PD_NUM_SFT 8
+#define VM_NUM_MSK GENMASK(20, 16)
+#define VM_NUM_SFT 16
+#define CH_NUM_MSK GENMASK(31, 24)
+#define CH_NUM_SFT 24
+
+/* Macro Common Register */
+#define CLK_SYNTH  0x00
+#define CLK_SYNTH_LO_SFT   0
+#define CLK_SYNTH_HI_SFT   8
+#define CLK_SYNTH_HOLD_SFT 16
+#define CLK_SYNTH_EN   BIT(24)
+#define CLK_SYS_CYCLES_MAX 514
+#define CLK_SYS_CYCLES_MIN 2
+#define HZ_PER_MHZ 100L
+
+#define SDIF_DISABLE   0x04
+
+#define SDIF_STAT  0x08
+#define SDIF_BUSY  BIT(0)
+#define SDIF_LOCK  BIT(1)
+
+#define SDIF_W 0x0c
+#define SDIF_PROG  BIT(31)
+#define SDIF_WRN_W BIT(27)
+#define SDIF_WRN_R 0x00
+#define SDIF_ADDR_SFT  24
+
+#define SDIF_HALT  0x10
+#define SDIF_CTRL  0x14
+#define SDIF_SMPL_CTRL 0x20
+
+/* TS & PD Individual Macro Register */
+#define COM_REG_SIZE   0x40
+
+#define SDIF_DONE(n)   (COM_REG_SIZE + 0x14 + 0x40 * (n))
+#define SDIF_SMPL_DONE BIT(0)
+
+#define SDIF_DATA(n)   (COM_REG_SIZE + 0x18 + 0x40 * (n))
+#define SAMPLE_DATA_MSKGENMASK(15, 0)
+
+#define HILO_RESET(n)  (COM_REG_SIZE + 0x2c + 0x40 * (n))
+
+/* VM Individual Macro Register */
+#define VM_COM_REG_SIZE0x200
+#define VM_SDIF_DONE(n)(VM_COM_REG_SIZE + 0x34 + 0x200 * (n))
+#define VM_SDIF_DATA(n)(VM_COM_REG_SIZE + 0x40 + 0x200 * (n))
+
+/* SDA Slave Register */
+#define IP_CTRL0x00
+#define IP_RST_REL BIT(1)
+#define IP_RUN_CONTBIT(3)
+#define IP_AUTOBIT(8)
+#define IP_VM_MODE BIT(10)
+
+#define IP_CFG 0x01
+#define CFG0_MODE_2BIT(0)
+#define CFG0_PARALLEL_OUT  0
+#define CFG0_12_BIT0
+#define CFG1_VOL_MEAS_MODE 0
+#define CFG1_PARALLEL_OUT  0
+#define CFG1_14_BIT0
+
+#define IP_DATA0x03
+
+#define IP_POLL0x04
+#define VM_CH_INIT BIT(20)
+#define VM_CH_REQ  BIT(21)
+
+#define IP_TMR 0x05
+#define POWER_DELAY_CYCLE_256  0x80
+#define POWER_DELAY_CYCLE_64   0x40
+
+#define PVT_POLL_DELAY_US  20
+#define PVT_POLL_TIMEOUT_US2
+#define PVT_H_CONST10
+#define PVT_CAL5_CONST 20

[PATCH v4 1/2] Add DT bindings schema for PVT controller

2020-10-02 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature sensor(TS),
voltage monitor(VM) & process detector(PD) modules.

Add DT bindings schema for PVT controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/hwmon/moortec,mr75203.yaml | 71 ++
 1 file changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml

diff --git a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml 
b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
new file mode 100644
index ..6f3e3c01f717
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/moortec,mr75203.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Moortec Semiconductor MR75203 PVT Controller bindings
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: moortec,mr75203
+
+  reg:
+items:
+  - description: PVT common registers
+  - description: PVT temprature sensor registers
+  - description: PVT process detector registers
+  - description: PVT voltage monitor registers
+
+  reg-names:
+items:
+  - const: common
+  - const: ts
+  - const: pd
+  - const: vm
+
+  intel,vm-map:
+description:
+  PVT controller has 5 VM (voltage monitor) sensors.
+  vm-map defines CPU core to VM instance mapping. A
+  value of 0xff means that VM sensor is unused.
+$ref: /schemas/types.yaml#definitions/uint8-array
+maxItems: 5
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  "#thermal-sensor-cells":
+const: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - intel,vm-map
+  - clocks
+  - resets
+  - "#thermal-sensor-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+pvt: pvt@e068 {
+compatible = "moortec,mr75203";
+reg = <0xe068 0x80>,
+  <0xe0680080 0x180>,
+  <0xe0680200 0x200>,
+  <0xe0680400 0xc00>;
+reg-names = "common", "ts", "pd", "vm";
+intel,vm-map = [03 01 04 ff ff];
+clocks = <>;
+resets = < 0x40 7>;
+#thermal-sensor-cells = <1>;
+};
-- 
2.11.0

[PATCH v4 2/2] Add hardware monitoring driver for Moortec MR75203 PVT controller

2020-10-02 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature
sensor(TS), voltage monitor(VM) & process detector(PD)
modules. Add hardware monitoring driver to support
MR75203 PVT controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/hwmon/Kconfig   |  10 +
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/mr75203.c | 651 
 3 files changed, 662 insertions(+)
 create mode 100644 drivers/hwmon/mr75203.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 8dc28b26916e..2defb46677b4 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1112,6 +1112,16 @@ config SENSORS_MENF21BMC_HWMON
  This driver can also be built as a module. If so the module
  will be called menf21bmc_hwmon.
 
+config SENSORS_MR75203
+   tristate "Moortec Semiconductor MR75203 PVT Controller"
+   select REGMAP_MMIO
+   help
+ If you say yes here you get support for Moortec MR75203
+ PVT controller.
+
+ This driver can also be built as a module. If so, the module
+ will be called mr75203.
+
 config SENSORS_ADCXX
tristate "National Semiconductor ADCxxxSxxx"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index a8f4b35b136b..bb4bd92a5149 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -142,6 +142,7 @@ obj-$(CONFIG_SENSORS_MCP3021)   += mcp3021.o
 obj-$(CONFIG_SENSORS_TC654)+= tc654.o
 obj-$(CONFIG_SENSORS_MLXREG_FAN) += mlxreg-fan.o
 obj-$(CONFIG_SENSORS_MENF21BMC_HWMON) += menf21bmc_hwmon.o
+obj-$(CONFIG_SENSORS_MR75203)  += mr75203.o
 obj-$(CONFIG_SENSORS_NCT6683)  += nct6683.o
 obj-$(CONFIG_SENSORS_NCT6775)  += nct6775.o
 obj-$(CONFIG_SENSORS_NCT7802)  += nct7802.o
diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c
new file mode 100644
index ..dc6f411ae873
--- /dev/null
+++ b/drivers/hwmon/mr75203.c
@@ -0,0 +1,651 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MaxLinear, Inc.
+ *
+ * This driver is a hardware monitoring driver for PVT controller
+ * (MR75203) which is used to configure & control Moortec embedded
+ * analog IP to enable multiple embedded temperature sensor(TS),
+ * voltage monitor(VM) & process detector(PD) modules.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PVT Common register */
+#define PVT_IP_CONFIG  0x04
+#define TS_NUM_MSK GENMASK(4, 0)
+#define TS_NUM_SFT 0
+#define PD_NUM_MSK GENMASK(12, 8)
+#define PD_NUM_SFT 8
+#define VM_NUM_MSK GENMASK(20, 16)
+#define VM_NUM_SFT 16
+#define CH_NUM_MSK GENMASK(31, 24)
+#define CH_NUM_SFT 24
+
+/* Macro Common Register */
+#define CLK_SYNTH  0x00
+#define CLK_SYNTH_LO_SFT   0
+#define CLK_SYNTH_HI_SFT   8
+#define CLK_SYNTH_HOLD_SFT 16
+#define CLK_SYNTH_EN   BIT(24)
+#define CLK_SYS_CYCLES_MAX 514
+#define CLK_SYS_CYCLES_MIN 2
+#define HZ_PER_MHZ 100L
+
+#define SDIF_DISABLE   0x04
+
+#define SDIF_STAT  0x08
+#define SDIF_BUSY  BIT(0)
+#define SDIF_LOCK  BIT(1)
+
+#define SDIF_W 0x0c
+#define SDIF_PROG  BIT(31)
+#define SDIF_WRN_W BIT(27)
+#define SDIF_WRN_R 0x00
+#define SDIF_ADDR_SFT  24
+
+#define SDIF_HALT  0x10
+#define SDIF_CTRL  0x14
+#define SDIF_SMPL_CTRL 0x20
+
+/* TS & PD Individual Macro Register */
+#define COM_REG_SIZE   0x40
+
+#define SDIF_DONE(n)   (COM_REG_SIZE + 0x14 + 0x40 * (n))
+#define SDIF_SMPL_DONE BIT(0)
+
+#define SDIF_DATA(n)   (COM_REG_SIZE + 0x18 + 0x40 * (n))
+#define SAMPLE_DATA_MSKGENMASK(15, 0)
+
+#define HILO_RESET(n)  (COM_REG_SIZE + 0x2c + 0x40 * (n))
+
+/* VM Individual Macro Register */
+#define VM_COM_REG_SIZE0x200
+#define VM_SDIF_DONE(n)(VM_COM_REG_SIZE + 0x34 + 0x200 * (n))
+#define VM_SDIF_DATA(n)(VM_COM_REG_SIZE + 0x40 + 0x200 * (n))
+
+/* SDA Slave Register */
+#define IP_CTRL0x00
+#define IP_RST_REL BIT(1)
+#define IP_RUN_CONTBIT(3)
+#define IP_AUTOBIT(8)
+#define IP_VM_MODE BIT(10)
+
+#define IP_CFG 0x01
+#define CFG0_MODE_2BIT(0)
+#define CFG0_PARALLEL_OUT  0
+#define CFG0_12_BIT0
+#define CFG1_VOL_MEAS_MODE 0
+#define CFG1_PARALLEL_OUT  0
+#define CFG1_14_BIT0
+
+#define IP_DATA0x03
+
+#define IP_POLL0x04
+#define VM_CH_INIT BIT(20)
+#define VM_CH_REQ  BIT(21)
+
+#define IP_TMR 0x05
+#define POWER_DELAY_CYCLE_256  0x80
+#define POWER_DELAY_CYCLE_64   0x40
+
+#define PVT_POLL_DELAY_US  20
+#define PVT_POLL_TIMEOUT_US2
+#define PVT_H_CONST10
+#define PVT_CAL5_CONST 2047
+#define PVT_G_CONST4
+#define PVT_CO

[PATCH v4 0/2] Add hwmon driver for Moortec PVT controller

2020-10-02 Thread Rahul Tanwar

Patch 1 adds DT bindings schema in YAML format.
Patch 2 adds driver for MR75203 PVT controller.

v4:
- Fix a spelling mistake in comments.
- Add return value error checking for all regmap_reads/writes.
- Remove unnecessary else statement and a validation check.

v3:
- Resolve make dt_binding_check errors.
- Add vendor prefix and type reference for one property in yaml schema.
- Update new property name in the driver.

v2:
- Address below review concerns from Andy Shevchenko
 * Add more info in comments for clamp_val usage for clk sys cycles.
 * Add mod_devicetable.h & property.h and remove of.h
 * Remove unnecessary additional mutex lock from driver. Rely on regmap's
   internal lock.
 * Use units in timeout macros.
 * Use HZ_PER_MHZ instead of direct values.
 * Use devm_platform_ioremap_resource_byname() instead of separate calls.
 * Use device property read API instead of OF API.
- Address below review concerns from Guenter Roeck
 * Improve commit message - add hardware monitoring driver.
 * Remove unnecessary platform_set_drvdata. Instead add driver data in
   function args at one place where it is used. Fix a issue related to it.
 * Remove unnecessary NULL assignment.
- Address below review concerns from Philipp Zabel
 * Switch to devm_reset_control_get_exclusive().
 * Move reset_deassert at the last after clk_enable in probe.
- Resolve make dt_binding_check error.
- Add MODULE_LICENSE

v1:
- Initial version.



Rahul Tanwar (2):
  Add DT bindings schema for PVT controller
  Add hardware monitoring driver for Moortec MR75203 PVT controller

 .../devicetree/bindings/hwmon/moortec,mr75203.yaml |  71 +++
 drivers/hwmon/Kconfig  |  10 +
 drivers/hwmon/Makefile |   1 +
 drivers/hwmon/mr75203.c| 651 +
 4 files changed, 733 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
 create mode 100644 drivers/hwmon/mr75203.c

-- 
2.11.0

[PATCH v3 1/2] Add DT bindings schema for PVT controller

2020-09-29 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature sensor(TS),
voltage monitor(VM) & process detector(PD) modules.

Add DT bindings schema for PVT controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/hwmon/moortec,mr75203.yaml | 71 ++
 1 file changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml

diff --git a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml 
b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
new file mode 100644
index ..6f3e3c01f717
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/moortec,mr75203.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Moortec Semiconductor MR75203 PVT Controller bindings
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: moortec,mr75203
+
+  reg:
+items:
+  - description: PVT common registers
+  - description: PVT temprature sensor registers
+  - description: PVT process detector registers
+  - description: PVT voltage monitor registers
+
+  reg-names:
+items:
+  - const: common
+  - const: ts
+  - const: pd
+  - const: vm
+
+  intel,vm-map:
+description:
+  PVT controller has 5 VM (voltage monitor) sensors.
+  vm-map defines CPU core to VM instance mapping. A
+  value of 0xff means that VM sensor is unused.
+$ref: /schemas/types.yaml#definitions/uint8-array
+maxItems: 5
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  "#thermal-sensor-cells":
+const: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - intel,vm-map
+  - clocks
+  - resets
+  - "#thermal-sensor-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+pvt: pvt@e068 {
+compatible = "moortec,mr75203";
+reg = <0xe068 0x80>,
+  <0xe0680080 0x180>,
+  <0xe0680200 0x200>,
+  <0xe0680400 0xc00>;
+reg-names = "common", "ts", "pd", "vm";
+intel,vm-map = [03 01 04 ff ff];
+clocks = <>;
+resets = < 0x40 7>;
+#thermal-sensor-cells = <1>;
+};
-- 
2.11.0

[PATCH v3 0/2] Add hwmon driver for Moortec PVT controller

2020-09-29 Thread Rahul Tanwar

Patch 1 adds DT bindings schema in YAML format.
Patch 2 adds driver for MR75203 PVT controller.

v3:
- Resolve make dt_binding_check errors.
- Add vendor prefix and type reference for one property in yaml schema.
- Update new property name in the driver.

v2:
- Address below review concerns from Andy Shevchenko
 * Add more info in comments for clamp_val usage for clk sys cycles.
 * Add mod_devicetable.h & property.h and remove of.h
 * Remove unnecessary additional mutex lock from driver. Rely on regmap's
   internal lock.
 * Use units in timeout macros.
 * Use HZ_PER_MHZ instead of direct values.
 * Use devm_platform_ioremap_resource_byname() instead of separate calls.
 * Use device property read API instead of OF API.
- Address below review concerns from Guenter Roeck
 * Improve commit message - add hardware monitoring driver.
 * Remove unnecessary platform_set_drvdata. Instead add driver data in
   function args at one place where it is used. Fix a issue related to it.
 * Remove unnecessary NULL assignment.
- Address below review concerns from Philipp Zabel
 * Switch to devm_reset_control_get_exclusive().
 * Move reset_deassert at the last after clk_enable in probe.
- Resolve make dt_binding_check error.
- Add MODULE_LICENSE

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings schema for PVT controller
  Add hardware monitoring driver for Moortec MR75203 PVT controller

 .../devicetree/bindings/hwmon/moortec,mr75203.yaml |  71 +++
 drivers/hwmon/Kconfig  |  10 +
 drivers/hwmon/Makefile |   1 +
 drivers/hwmon/mr75203.c| 605 +
 4 files changed, 687 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
 create mode 100644 drivers/hwmon/mr75203.c

-- 
2.11.0

[PATCH v3 2/2] Add hardware monitoring driver for Moortec MR75203 PVT controller

2020-09-29 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature
sensor(TS), voltage monitor(VM) & process detector(PD)
modules. Add hardware monitoring driver to support
MR75203 PVT controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/hwmon/Kconfig   |  10 +
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/mr75203.c | 605 
 3 files changed, 616 insertions(+)
 create mode 100644 drivers/hwmon/mr75203.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 8dc28b26916e..2defb46677b4 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1112,6 +1112,16 @@ config SENSORS_MENF21BMC_HWMON
  This driver can also be built as a module. If so the module
  will be called menf21bmc_hwmon.
 
+config SENSORS_MR75203
+   tristate "Moortec Semiconductor MR75203 PVT Controller"
+   select REGMAP_MMIO
+   help
+ If you say yes here you get support for Moortec MR75203
+ PVT controller.
+
+ This driver can also be built as a module. If so, the module
+ will be called mr75203.
+
 config SENSORS_ADCXX
tristate "National Semiconductor ADCxxxSxxx"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index a8f4b35b136b..bb4bd92a5149 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -142,6 +142,7 @@ obj-$(CONFIG_SENSORS_MCP3021)   += mcp3021.o
 obj-$(CONFIG_SENSORS_TC654)+= tc654.o
 obj-$(CONFIG_SENSORS_MLXREG_FAN) += mlxreg-fan.o
 obj-$(CONFIG_SENSORS_MENF21BMC_HWMON) += menf21bmc_hwmon.o
+obj-$(CONFIG_SENSORS_MR75203)  += mr75203.o
 obj-$(CONFIG_SENSORS_NCT6683)  += nct6683.o
 obj-$(CONFIG_SENSORS_NCT6775)  += nct6775.o
 obj-$(CONFIG_SENSORS_NCT7802)  += nct7802.o
diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c
new file mode 100644
index ..30a70a3ae82b
--- /dev/null
+++ b/drivers/hwmon/mr75203.c
@@ -0,0 +1,605 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MaxLinear, Inc.
+ *
+ * This driver is a hardware monitoring driver for PVT controller
+ * (MR75203) which is used to configure & control Moortec embedded
+ * analog IP to enable multiple embedded temprature sensor(TS),
+ * voltage monitor(VM) & process detector(PD) modules.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PVT Common register */
+#define PVT_IP_CONFIG  0x04
+#define TS_NUM_MSK GENMASK(4, 0)
+#define TS_NUM_SFT 0
+#define PD_NUM_MSK GENMASK(12, 8)
+#define PD_NUM_SFT 8
+#define VM_NUM_MSK GENMASK(20, 16)
+#define VM_NUM_SFT 16
+#define CH_NUM_MSK GENMASK(31, 24)
+#define CH_NUM_SFT 24
+
+/* Macro Common Register */
+#define CLK_SYNTH  0x00
+#define CLK_SYNTH_LO_SFT   0
+#define CLK_SYNTH_HI_SFT   8
+#define CLK_SYNTH_HOLD_SFT 16
+#define CLK_SYNTH_EN   BIT(24)
+#define CLK_SYS_CYCLES_MAX 514
+#define CLK_SYS_CYCLES_MIN 2
+#define HZ_PER_MHZ 100L
+
+#define SDIF_DISABLE   0x04
+
+#define SDIF_STAT  0x08
+#define SDIF_BUSY  BIT(0)
+#define SDIF_LOCK  BIT(1)
+
+#define SDIF_W 0x0c
+#define SDIF_PROG  BIT(31)
+#define SDIF_WRN_W BIT(27)
+#define SDIF_WRN_R 0x00
+#define SDIF_ADDR_SFT  24
+
+#define SDIF_HALT  0x10
+#define SDIF_CTRL  0x14
+#define SDIF_SMPL_CTRL 0x20
+
+/* TS & PD Individual Macro Register */
+#define COM_REG_SIZE   0x40
+
+#define SDIF_DONE(n)   (COM_REG_SIZE + 0x14 + 0x40 * (n))
+#define SDIF_SMPL_DONE BIT(0)
+
+#define SDIF_DATA(n)   (COM_REG_SIZE + 0x18 + 0x40 * (n))
+#define SAMPLE_DATA_MSKGENMASK(15, 0)
+
+#define HILO_RESET(n)  (COM_REG_SIZE + 0x2c + 0x40 * (n))
+
+/* VM Individual Macro Register */
+#define VM_COM_REG_SIZE0x200
+#define VM_SDIF_DONE(n)(VM_COM_REG_SIZE + 0x34 + 0x200 * (n))
+#define VM_SDIF_DATA(n)(VM_COM_REG_SIZE + 0x40 + 0x200 * (n))
+
+/* SDA Slave Register */
+#define IP_CTRL0x00
+#define IP_RST_REL BIT(1)
+#define IP_RUN_CONTBIT(3)
+#define IP_AUTOBIT(8)
+#define IP_VM_MODE BIT(10)
+
+#define IP_CFG 0x01
+#define CFG0_MODE_2BIT(0)
+#define CFG0_PARALLEL_OUT  0
+#define CFG0_12_BIT0
+#define CFG1_VOL_MEAS_MODE 0
+#define CFG1_PARALLEL_OUT  0
+#define CFG1_14_BIT0
+
+#define IP_DATA0x03
+
+#define IP_POLL0x04
+#define VM_CH_INIT BIT(20)
+#define VM_CH_REQ  BIT(21)
+
+#define IP_TMR 0x05
+#define POWER_DELAY_CYCLE_256  0x80
+#define POWER_DELAY_CYCLE_64   0x40
+
+#define PVT_POLL_DELAY_US  20
+#define PVT_POLL_TIMEOUT_US2
+#define PVT_H_CONST10
+#define PVT_CAL5_CONST 2047
+#define PVT_G_CONST4
+#define PVT_CONV_BITS

[PATCH v2 2/2] Add hardware monitoring driver for Moortec MR75203 PVT controller

2020-09-28 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature
sensor(TS), voltage monitor(VM) & process detector(PD)
modules. Add hardware monitoring driver to support
MR75203 PVT controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/hwmon/Kconfig   |  10 +
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/mr75203.c | 605 
 3 files changed, 616 insertions(+)
 create mode 100644 drivers/hwmon/mr75203.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 8dc28b26916e..2defb46677b4 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1112,6 +1112,16 @@ config SENSORS_MENF21BMC_HWMON
  This driver can also be built as a module. If so the module
  will be called menf21bmc_hwmon.
 
+config SENSORS_MR75203
+   tristate "Moortec Semiconductor MR75203 PVT Controller"
+   select REGMAP_MMIO
+   help
+ If you say yes here you get support for Moortec MR75203
+ PVT controller.
+
+ This driver can also be built as a module. If so, the module
+ will be called mr75203.
+
 config SENSORS_ADCXX
tristate "National Semiconductor ADCxxxSxxx"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index a8f4b35b136b..bb4bd92a5149 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -142,6 +142,7 @@ obj-$(CONFIG_SENSORS_MCP3021)   += mcp3021.o
 obj-$(CONFIG_SENSORS_TC654)+= tc654.o
 obj-$(CONFIG_SENSORS_MLXREG_FAN) += mlxreg-fan.o
 obj-$(CONFIG_SENSORS_MENF21BMC_HWMON) += menf21bmc_hwmon.o
+obj-$(CONFIG_SENSORS_MR75203)  += mr75203.o
 obj-$(CONFIG_SENSORS_NCT6683)  += nct6683.o
 obj-$(CONFIG_SENSORS_NCT6775)  += nct6775.o
 obj-$(CONFIG_SENSORS_NCT7802)  += nct7802.o
diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c
new file mode 100644
index ..a4c0de7b2790
--- /dev/null
+++ b/drivers/hwmon/mr75203.c
@@ -0,0 +1,605 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MaxLinear, Inc.
+ *
+ * This driver is a hardware monitoring driver for PVT controller
+ * (MR75203) which is used to configure & control Moortec embedded
+ * analog IP to enable multiple embedded temprature sensor(TS),
+ * voltage monitor(VM) & process detector(PD) modules.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PVT Common register */
+#define PVT_IP_CONFIG  0x04
+#define TS_NUM_MSK GENMASK(4, 0)
+#define TS_NUM_SFT 0
+#define PD_NUM_MSK GENMASK(12, 8)
+#define PD_NUM_SFT 8
+#define VM_NUM_MSK GENMASK(20, 16)
+#define VM_NUM_SFT 16
+#define CH_NUM_MSK GENMASK(31, 24)
+#define CH_NUM_SFT 24
+
+/* Macro Common Register */
+#define CLK_SYNTH  0x00
+#define CLK_SYNTH_LO_SFT   0
+#define CLK_SYNTH_HI_SFT   8
+#define CLK_SYNTH_HOLD_SFT 16
+#define CLK_SYNTH_EN   BIT(24)
+#define CLK_SYS_CYCLES_MAX 514
+#define CLK_SYS_CYCLES_MIN 2
+#define HZ_PER_MHZ 100L
+
+#define SDIF_DISABLE   0x04
+
+#define SDIF_STAT  0x08
+#define SDIF_BUSY  BIT(0)
+#define SDIF_LOCK  BIT(1)
+
+#define SDIF_W 0x0c
+#define SDIF_PROG  BIT(31)
+#define SDIF_WRN_W BIT(27)
+#define SDIF_WRN_R 0x00
+#define SDIF_ADDR_SFT  24
+
+#define SDIF_HALT  0x10
+#define SDIF_CTRL  0x14
+#define SDIF_SMPL_CTRL 0x20
+
+/* TS & PD Individual Macro Register */
+#define COM_REG_SIZE   0x40
+
+#define SDIF_DONE(n)   (COM_REG_SIZE + 0x14 + 0x40 * (n))
+#define SDIF_SMPL_DONE BIT(0)
+
+#define SDIF_DATA(n)   (COM_REG_SIZE + 0x18 + 0x40 * (n))
+#define SAMPLE_DATA_MSKGENMASK(15, 0)
+
+#define HILO_RESET(n)  (COM_REG_SIZE + 0x2c + 0x40 * (n))
+
+/* VM Individual Macro Register */
+#define VM_COM_REG_SIZE0x200
+#define VM_SDIF_DONE(n)(VM_COM_REG_SIZE + 0x34 + 0x200 * (n))
+#define VM_SDIF_DATA(n)(VM_COM_REG_SIZE + 0x40 + 0x200 * (n))
+
+/* SDA Slave Register */
+#define IP_CTRL0x00
+#define IP_RST_REL BIT(1)
+#define IP_RUN_CONTBIT(3)
+#define IP_AUTOBIT(8)
+#define IP_VM_MODE BIT(10)
+
+#define IP_CFG 0x01
+#define CFG0_MODE_2BIT(0)
+#define CFG0_PARALLEL_OUT  0
+#define CFG0_12_BIT0
+#define CFG1_VOL_MEAS_MODE 0
+#define CFG1_PARALLEL_OUT  0
+#define CFG1_14_BIT0
+
+#define IP_DATA0x03
+
+#define IP_POLL0x04
+#define VM_CH_INIT BIT(20)
+#define VM_CH_REQ  BIT(21)
+
+#define IP_TMR 0x05
+#define POWER_DELAY_CYCLE_256  0x80
+#define POWER_DELAY_CYCLE_64   0x40
+
+#define PVT_POLL_DELAY_US  20
+#define PVT_POLL_TIMEOUT_US2
+#define PVT_H_CONST10
+#define PVT_CAL5_CONST 2047
+#define PVT_G_CONST4
+#define PVT_CONV_BITS

[PATCH v2 1/2] Add DT bindings schema for PVT controller

2020-09-28 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature sensor(TS),
voltage monitor(VM) & process detector(PD) modules.

Add DT bindings schema for PVT controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/hwmon/moortec,mr75203.yaml | 70 ++
 1 file changed, 70 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml

diff --git a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml 
b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
new file mode 100644
index ..85461bfe
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/moortec,mr75203.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Moortec Semiconductor MR75203 PVT Controller bindings
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: moortec,mr75203
+
+  reg:
+items:
+  - description: PVT common registers
+  - description: PVT temprature sensor registers
+  - description: PVT process detector registers
+  - description: PVT voltage monitor registers
+
+  reg-names:
+items:
+  - const: common
+  - const: ts
+  - const: pd
+  - const: vm
+
+  vm-map:
+description:
+  PVT controller has 5 VM (voltage monitor) sensors.
+  vm-map defines CPU core to VM instance mapping. A
+  value of 0xff means that VM sensor is unused.
+maxItems: 5
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  "#thermal-sensor-cells":
+const: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - vm-map
+  - clocks
+  - resets
+  - "#thermal-sensor-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+pvt: pvt@e068 {
+compatible = "moortec,mr75203";
+reg = <0xe068 0x80
+   0xe0680080 0x180
+   0xe0680200 0x200
+   0xe0680400 0xc00>;
+reg-names = "common", "ts", "pd", "vm";
+vm-map = [03 01 04 ff ff];
+clocks = <>;
+resets = < 0x40 7>;
+#thermal-sensor-cells = <1>;
+};
-- 
2.11.0

[PATCH v2 0/2] Add hwmon driver for Moortec PVT controller

2020-09-28 Thread Rahul Tanwar

Patch 1 adds DT bindings schema in YAML format.
Patch 2 adds driver for MR75203 PVT controller.

v2:
- Address below review concerns from Andy Shevchenko
 * Add more info in comments for clamp_val usage for clk sys cycles.
 * Add mod_devicetable.h & property.h and remove of.h
 * Remove unnecessary additional mutex lock from driver. Rely on regmap's
   internal lock.
 * Use units in timeout macros.
 * Use HZ_PER_MHZ instead of direct values.
 * Use devm_platform_ioremap_resource_byname() instead of separate calls.
 * Use device property read API instead of OF API.
- Address below review concerns from Guenter Roeck
 * Improve commit message - add hardware monitoring driver.
 * Remove unnecessary platform_set_drvdata. Instead add driver data in
   function args at one place where it is used. Fix a issue related to it.
 * Remove unnecessary NULL assignment.
- Address below review concerns from Philipp Zabel
 * Switch to devm_reset_control_get_exclusive().
 * Move reset_deassert at the last after clk_enable in probe.
- Resolve make dt_binding_check error.
- Add MODULE_LICENSE

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings schema for PVT controller
  Add hardware monitoring driver for Moortec MR75203 PVT controller

 .../devicetree/bindings/hwmon/moortec,mr75203.yaml |  70 +++
 drivers/hwmon/Kconfig  |  10 +
 drivers/hwmon/Makefile |   1 +
 drivers/hwmon/mr75203.c| 605 +
 4 files changed, 686 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
 create mode 100644 drivers/hwmon/mr75203.c

-- 
2.11.0

[PATCH v14 2/2] Add PWM fan controller driver for LGM SoC

2020-09-28 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
Reviewed-by: Andy Shevchenko 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 244 
 3 files changed, 256 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 7dbcf6973d33..4949c51fe90b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on HAS_IOMEM
+   depends on (OF && X86) || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2c2ba0a03557..e9431b151694 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..e9e54dda07aa
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period & configures only 2-wire mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NS(40 * NSEC_PER_MSEC)
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /* The hardware only supports normal polarity and fixed period. */
+   if (state->polarity != PWM_POLARITY_NORMAL || state->period < 
pc->period)
+   return -EINVAL;
+
+   if (!state->enabled)
+   return lgm_pwm_enable(chip, 0);
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+   ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, 
LGM_PWM_FAN_DC_MSK,
+FIELD_PREP(LGM_PWM_FAN_DC_MSK, val));
+   if (ret)
+   return re

[PATCH v14 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-09-28 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..11a606536169
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v13 2/2] Add PWM fan controller driver for LGM SoC

2020-09-15 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
Reviewed-by: Andy Shevchenko 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 246 
 3 files changed, 258 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 7dbcf6973d33..4949c51fe90b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on HAS_IOMEM
+   depends on (OF && X86) || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2c2ba0a03557..e9431b151694 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..ea3df75a5971
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NS(40 * NSEC_PER_MSEC)
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /* The hardware only supports normal polarity and fixed period. */
+   if (state->polarity != PWM_POLARITY_NORMAL || state->period < 
pc->period)
+   return -EINVAL;
+
+   if (!state->enabled)
+   return lgm_pwm_enable(chip, 0);
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+   ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, 
LGM_PWM_FAN_DC_MSK,
+

[PATCH v13 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-09-15 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..11a606536169
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v12 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-09-09 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..11a606536169
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v12 2/2] Add PWM fan controller driver for LGM SoC

2020-09-09 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
Reviewed-by: Andy Shevchenko 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 253 
 3 files changed, 265 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 7dbcf6973d33..4949c51fe90b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on HAS_IOMEM
+   depends on (OF && X86) || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2c2ba0a03557..e9431b151694 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..8e9f8cd3b7fb
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NS(40 * NSEC_PER_MSEC)
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /*
+* The hardware only supports
+* normal polarity and fixed period.
+*/
+   if (state->polarity != PWM_POLARITY_NORMAL || state->period < 
pc->period)
+   return -EINVAL;
+
+   if (!state->enabled)
+   return lgm_pwm_enable(chip, 0);
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+   ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, 
LGM_PWM_FAN_DC_MSK,
+

[PATCH 2/2] Add driver for Moortec MR75203 PVT controller

2020-09-09 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature
sensor(TS), voltage monitor(VM) & process detector(PD)
modules. Add driver to support MR75203 PVT controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/hwmon/Kconfig   |  10 +
 drivers/hwmon/Makefile  |   1 +
 drivers/hwmon/mr75203.c | 617 
 3 files changed, 628 insertions(+)
 create mode 100644 drivers/hwmon/mr75203.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 8dc28b26916e..2defb46677b4 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1112,6 +1112,16 @@ config SENSORS_MENF21BMC_HWMON
  This driver can also be built as a module. If so the module
  will be called menf21bmc_hwmon.
 
+config SENSORS_MR75203
+   tristate "Moortec Semiconductor MR75203 PVT Controller"
+   select REGMAP_MMIO
+   help
+ If you say yes here you get support for Moortec MR75203
+ PVT controller.
+
+ This driver can also be built as a module. If so, the module
+ will be called mr75203.
+
 config SENSORS_ADCXX
tristate "National Semiconductor ADCxxxSxxx"
depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index a8f4b35b136b..bb4bd92a5149 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -142,6 +142,7 @@ obj-$(CONFIG_SENSORS_MCP3021)   += mcp3021.o
 obj-$(CONFIG_SENSORS_TC654)+= tc654.o
 obj-$(CONFIG_SENSORS_MLXREG_FAN) += mlxreg-fan.o
 obj-$(CONFIG_SENSORS_MENF21BMC_HWMON) += menf21bmc_hwmon.o
+obj-$(CONFIG_SENSORS_MR75203)  += mr75203.o
 obj-$(CONFIG_SENSORS_NCT6683)  += nct6683.o
 obj-$(CONFIG_SENSORS_NCT6775)  += nct6775.o
 obj-$(CONFIG_SENSORS_NCT7802)  += nct7802.o
diff --git a/drivers/hwmon/mr75203.c b/drivers/hwmon/mr75203.c
new file mode 100644
index ..8b616e53f27b
--- /dev/null
+++ b/drivers/hwmon/mr75203.c
@@ -0,0 +1,617 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MaxLinear, Inc.
+ *
+ * This driver is for PVT controller (MR75203) which is used
+ * to configure & control Moortec embedded analog IP to enable
+ * multiple embedded temprature sensor(TS), voltage monitor(VM)
+ * & process detector(PD) modules.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PVT Common register */
+#define PVT_IP_CONFIG  0x04
+#define TS_NUM_MSK GENMASK(4, 0)
+#define TS_NUM_SFT 0
+#define PD_NUM_MSK GENMASK(12, 8)
+#define PD_NUM_SFT 8
+#define VM_NUM_MSK GENMASK(20, 16)
+#define VM_NUM_SFT 16
+#define CH_NUM_MSK GENMASK(31, 24)
+#define CH_NUM_SFT 24
+
+/* Macro Common Register */
+#define CLK_SYNTH  0x00
+#define CLK_SYNTH_LO_SFT   0
+#define CLK_SYNTH_HI_SFT   8
+#define CLK_SYNTH_HOLD_SFT 16
+#define CLK_SYNTH_EN   BIT(24)
+
+#define SDIF_DISABLE   0x04
+
+#define SDIF_STAT  0x08
+#define SDIF_BUSY  BIT(0)
+#define SDIF_LOCK  BIT(1)
+
+#define SDIF_W 0x0c
+#define SDIF_PROG  BIT(31)
+#define SDIF_WRN_W BIT(27)
+#define SDIF_WRN_R 0x00
+#define SDIF_ADDR_SFT  24
+
+#define SDIF_HALT  0x10
+#define SDIF_CTRL  0x14
+#define SDIF_SMPL_CTRL 0x20
+
+/* TS & PD Individual Macro Register */
+#define COM_REG_SIZE   0x40
+
+#define SDIF_DONE(n)   (COM_REG_SIZE + 0x14 + 0x40 * (n))
+#define SDIF_SMPL_DONE BIT(0)
+
+#define SDIF_DATA(n)   (COM_REG_SIZE + 0x18 + 0x40 * (n))
+#define SAMPLE_DATA_MSKGENMASK(15, 0)
+
+#define HILO_RESET(n)  (COM_REG_SIZE + 0x2c + 0x40 * (n))
+
+/* VM Individual Macro Register */
+#define VM_COM_REG_SIZE0x200
+#define VM_SDIF_DONE(n)(VM_COM_REG_SIZE + 0x34 + 0x200 * (n))
+#define VM_SDIF_DATA(n)(VM_COM_REG_SIZE + 0x40 + 0x200 * (n))
+
+/* SDA Slave Register */
+#define IP_CTRL0x00
+#define IP_RST_REL BIT(1)
+#define IP_RUN_CONTBIT(3)
+#define IP_AUTOBIT(8)
+#define IP_VM_MODE BIT(10)
+
+#define IP_CFG 0x01
+#define CFG0_MODE_2BIT(0)
+#define CFG0_PARALLEL_OUT  0
+#define CFG0_12_BIT0
+#define CFG1_VOL_MEAS_MODE 0
+#define CFG1_PARALLEL_OUT  0
+#define CFG1_14_BIT0
+
+#define IP_DATA0x03
+
+#define IP_POLL0x04
+#define VM_CH_INIT BIT(20)
+#define VM_CH_REQ  BIT(21)
+
+#define IP_TMR 0x05
+#define POWER_DELAY_CYCLE_256  0x80
+#define POWER_DELAY_CYCLE_64   0x40
+
+#define PVT_POLL_DELAY_US  20
+#define PVT_POLL_TIMEOUT   2
+#define PVT_H_CONST10
+#define PVT_CAL5_CONST 2047
+#define PVT_G_CONST4
+#define PVT_CONV_BITS  10
+#define PVT_N_CONST90
+#define PVT_R_CONST245805
+
+struct pvt_device {
+   struct regmap   *c_map;
+   struct regmap

[PATCH 1/2] Add DT bindings schema for PVT controller

2020-09-09 Thread Rahul Tanwar

PVT controller (MR75203) is used to configure & control
Moortec embedded analog IP which contains temprature sensor(TS),
voltage monitor(VM) & process detector(PD) modules.

Add DT bindings schema for PVT controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/hwmon/moortec,mr75203.yaml | 70 ++
 1 file changed, 70 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml

diff --git a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml 
b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
new file mode 100644
index ..0d5a90117522
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/moortec,mr75203.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Moortec Semiconductor MR75203 PVT Controller bindings
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: moortec,mr75203
+
+  reg:
+items:
+  - description: PVT common registers
+  - description: PVT temprature sensor registers
+  - description: PVT process detector registers
+  - description: PVT voltage monitor registers
+
+  reg-names:
+items:
+  - const: common
+  - const: ts
+  - const: pd
+  - const: vm
+
+  vm-map:
+description:
+  PVT controller has 5 VM (voltage monitor) sensors.
+  vm-map defines CPU core to VM instance mapping. A
+  value of 0xff means that VM sensor is unused.
+maxItems: 5
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  "#thermal-sensor-cells":
+const: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - vm-map
+  - clocks
+  - resets
+  - "#thermal-sensor-cells":
+
+additionalProperties: false
+
+examples:
+  - |
+pvt: pvt@e068 {
+compatible = "moortec,mr75203";
+reg = <0xe068 0x80
+   0xe0680080 0x180
+   0xe0680200 0x200
+   0xe0680400 0xc00>;
+reg-names = "common", "ts", "pd", "vm";
+vm-map = [03 01 04 ff ff];
+clocks = <>;
+resets = < 0x40 7>;
+#thermal-sensor-cells = <1>;
+};
-- 
2.11.0

[PATCH 0/2] Add driver for Moortec PVT controller

2020-09-09 Thread Rahul Tanwar

Patch 1 adds DT bindings schema in YAML format.
Patch 2 adds driver for MR75203 PVT controller.

Rahul Tanwar (2):
  Add DT bindings schema for PVT controller
  Add driver for Moortec MR75203 PVT controller

 .../devicetree/bindings/hwmon/moortec,mr75203.yaml |  70 +++
 drivers/hwmon/Kconfig  |  10 +
 drivers/hwmon/Makefile |   1 +
 drivers/hwmon/mr75203.c| 617 +
 4 files changed, 698 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml
 create mode 100644 drivers/hwmon/mr75203.c

-- 
2.11.0

[PATCH v11 2/2] Add PWM fan controller driver for LGM SoC

2020-08-24 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 253 
 3 files changed, 265 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 7dbcf6973d33..4949c51fe90b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on HAS_IOMEM
+   depends on (OF && X86) || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2c2ba0a03557..e9431b151694 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..8e9f8cd3b7fb
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NS(40 * NSEC_PER_MSEC)
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /*
+* The hardware only supports
+* normal polarity and fixed period.
+*/
+   if (state->polarity != PWM_POLARITY_NORMAL || state->period < 
pc->period)
+   return -EINVAL;
+
+   if (!state->enabled)
+   return lgm_pwm_enable(chip, 0);
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+   ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, 
LGM_PWM_FAN_DC_MSK,
+

[PATCH v11 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-08-24 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..11a606536169
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v11 0/2] pwm: intel: Add PWM driver for a new SoC

2020-08-24 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

v11:
- Address below review concerns (Andy Shevchenko)
  * Fix a issue with dev_err_probe() usage & improve the usage.
  * Fix & improve a ordering issue with clk_enable/disable &
reset_control assert/deassert.

v10:
- Removed unused of_device.h and added platform_device.h
  & mod_devicetable.h

v9:
- Address code quality related review concerns (Andy Shevchenko)
- Use devm_add_action_or_reset() instead of explicit unwind calls.

v8:
- Remove fan related optional properties usage, keep
  them as default. If needed, change pwm-fan driver
  separately in future to add them as generic properties.

v7:
- Address code quality related review concerns.
- Rename fan related property to pwm-*.
- Fix one make dt_binding_check reported error.

v6:
- Readjust .apply op as per review feedback.
- Add back pwm-cells property to resolve make dt_binding_check error.
  pwm-cells is a required property for PWM driver.
- Add back fan related optional properties.

v5:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve comments about Limitations.
  * Use return value of regmap_update_bits if container function returns
error code.
  * Modify .apply op to have strict checking for fixed period supported
by PWM HW.
  * Use u64 as type when use min_t for duty_cycle.
  * Add reset_control_assert() in failure case in probe where it was missing
earlier.
- Remove fan specific optional properties from pwm dt binding document (Rob 
Herring)

v4:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve notes and limitations comments.
  * Add common prefixes for all #defines.
  * Modify/Improve logic in .apply & .get_state ops as advised.
  * Skip error messages in probe when error is -EPROBE_DEFER.
  * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
  * Address other code quality related review concerns.
- Fix make dt_binding_check reported error in YAML file.

v3:
- Address below review concerns from Uwe Kleine-K�nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K�nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  44 
 drivers/pwm/Kconfig|  11 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 253 +
 4 files changed, 309 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v10 2/2] Add PWM fan controller driver for LGM SoC

2020-08-23 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 242 
 3 files changed, 254 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 7dbcf6973d33..4949c51fe90b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on HAS_IOMEM
+   depends on (OF && X86) || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2c2ba0a03557..e9431b151694 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..bfe784be3809
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NS(40 * NSEC_PER_MSEC)
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /*
+* The hardware only supports
+* normal polarity and fixed period.
+*/
+   if (state->polarity != PWM_POLARITY_NORMAL || state->period < 
pc->period)
+   return -EINVAL;
+
+   if (!state->enabled)
+   return lgm_pwm_enable(chip, 0);
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+   ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, 
LGM_PWM_FAN_DC_MSK,
+

[PATCH v10 0/2] pwm: intel: Add PWM driver for a new SoC

2020-08-23 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

v10:
- Removed unused of_device.h and added platform_device.h
  & mod_devicetable.h

v9:
- Address code quality related review concerns (Andy Shevchenko)
- Use devm_add_action_or_reset() instead of explicit unwind calls.

v8:
- Remove fan related optional properties usage, keep
  them as default. If needed, change pwm-fan driver
  separately in future to add them as generic properties.

v7:
- Address code quality related review concerns.
- Rename fan related property to pwm-*.
- Fix one make dt_binding_check reported error.

v6:
- Readjust .apply op as per review feedback.
- Add back pwm-cells property to resolve make dt_binding_check error.
  pwm-cells is a required property for PWM driver.
- Add back fan related optional properties.

v5:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve comments about Limitations.
  * Use return value of regmap_update_bits if container function returns
error code.
  * Modify .apply op to have strict checking for fixed period supported
by PWM HW.
  * Use u64 as type when use min_t for duty_cycle.
  * Add reset_control_assert() in failure case in probe where it was missing
earlier.
- Remove fan specific optional properties from pwm dt binding document (Rob 
Herring)

v4:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve notes and limitations comments.
  * Add common prefixes for all #defines.
  * Modify/Improve logic in .apply & .get_state ops as advised.
  * Skip error messages in probe when error is -EPROBE_DEFER.
  * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
  * Address other code quality related review concerns.
- Fix make dt_binding_check reported error in YAML file.

v3:
- Address below review concerns from Uwe Kleine-K�nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K�nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  44 
 drivers/pwm/Kconfig|  11 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 242 +
 4 files changed, 298 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v10 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-08-23 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..11a606536169
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v9 0/2] pwm: intel: Add PWM driver for a new SoC

2020-08-21 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

v9:
- Address code quality related review concerns (Andy Shevchenko)
- Use devm_add_action_or_reset() instead of explicit unwind calls.

v8:
- Remove fan related optional properties usage, keep
  them as default. If needed, change pwm-fan driver
  separately in future to add them as generic properties.

v7:
- Address code quality related review concerns.
- Rename fan related property to pwm-*.
- Fix one make dt_binding_check reported error.

v6:
- Readjust .apply op as per review feedback.
- Add back pwm-cells property to resolve make dt_binding_check error.
  pwm-cells is a required property for PWM driver.
- Add back fan related optional properties.

v5:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve comments about Limitations.
  * Use return value of regmap_update_bits if container function returns
error code.
  * Modify .apply op to have strict checking for fixed period supported
by PWM HW.
  * Use u64 as type when use min_t for duty_cycle.
  * Add reset_control_assert() in failure case in probe where it was missing
earlier.
- Remove fan specific optional properties from pwm dt binding document (Rob 
Herring)

v4:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve notes and limitations comments.
  * Add common prefixes for all #defines.
  * Modify/Improve logic in .apply & .get_state ops as advised.
  * Skip error messages in probe when error is -EPROBE_DEFER.
  * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
  * Address other code quality related review concerns.
- Fix make dt_binding_check reported error in YAML file.

v3:
- Address below review concerns from Uwe Kleine-K�nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K�nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  44 
 drivers/pwm/Kconfig|  11 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 241 +
 4 files changed, 297 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v9 2/2] Add PWM fan controller driver for LGM SoC

2020-08-21 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 241 
 3 files changed, 253 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 7dbcf6973d33..4949c51fe90b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on HAS_IOMEM
+   depends on (OF && X86) || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2c2ba0a03557..e9431b151694 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..fe9464d8d941
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NS(40 * NSEC_PER_MSEC)
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /*
+* The hardware only supports
+* normal polarity and fixed period.
+*/
+   if (state->polarity != PWM_POLARITY_NORMAL || state->period < 
pc->period)
+   return -EINVAL;
+
+   if (!state->enabled)
+   return lgm_pwm_enable(chip, 0);
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+   ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, 
LGM_PWM_FAN_DC_MSK,
+

[PATCH v9 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-08-21 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..11a606536169
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v8 0/2] pwm: intel: Add PWM driver for a new SoC

2020-08-19 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

v8:
- Remove fan related optional properties usage, keep
  them as default. If needed, change pwm-fan driver
  separately in future to add them as generic properties.

v7:
- Address code quality related review concerns.
- Rename fan related property to pwm-*.
- Fix one make dt_binding_check reported error.

v6:
- Readjust .apply op as per review feedback.
- Add back pwm-cells property to resolve make dt_binding_check error.
  pwm-cells is a required property for PWM driver.
- Add back fan related optional properties.

v5:
- Address below review concerns from Uwe Kleine-K?nig.
  * Improve comments about Limitations.
  * Use return value of regmap_update_bits if container function returns
error code.
  * Modify .apply op to have strict checking for fixed period supported
by PWM HW.
  * Use u64 as type when use min_t for duty_cycle.
  * Add reset_control_assert() in failure case in probe where it was missing
earlier.
- Remove fan specific optional properties from pwm dt binding document (Rob 
Herring)

v4:
- Address below review concerns from Uwe Kleine-K?nig.
  * Improve notes and limitations comments.
  * Add common prefixes for all #defines.
  * Modify/Improve logic in .apply & .get_state ops as advised.
  * Skip error messages in probe when error is -EPROBE_DEFER.
  * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
  * Address other code quality related review concerns.
- Fix make dt_binding_check reported error in YAML file.

v3:
- Address below review concerns from Uwe Kleine-K?nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K?nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  44 
 drivers/pwm/Kconfig|  11 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 244 +
 4 files changed, 300 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v8 2/2] Add PWM fan controller driver for LGM SoC

2020-08-19 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 244 
 3 files changed, 256 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 7dbcf6973d33..f7a832268c79 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on OF && HAS_IOMEM
+   depends on X86 || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2c2ba0a03557..e9431b151694 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..3d0f79b69532
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NSECS 4000
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /*
+* The hardware only supports
+* normal polarity and fixed period.
+*/
+   if (state->polarity != PWM_POLARITY_NORMAL ||
+   state->period < pc->period)
+   return -EINVAL;
+
+   if (!state->enabled) {
+   ret = lgm_pwm_enable(chip, 0);
+   return ret;
+   }
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+   ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, 
LGM_PWM_FAN_DC_MSK,
+

[PATCH v8 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-08-19 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..11a606536169
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v7 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-08-17 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 54 ++
 1 file changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..289b82213e23
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  pwm-fanmode:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description: Specifies PWM fan mode. Default when unspecified is 2.
+
+  pwm-maxrpm:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description:
+  Specifies maximum RPM of PWM fan attached to the system.
+  Default when unspecified is 4000.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v7 2/2] Add PWM fan controller driver for LGM SoC

2020-08-17 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 267 
 3 files changed, 279 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 7dbcf6973d33..f7a832268c79 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on OF && HAS_IOMEM
+   depends on X86 || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2c2ba0a03557..e9431b151694 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..7f26a30c70f1
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_4WIRE 0x1
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NSECS 4000
+#define LGM_PWM_PERIOD_4WIRE_NSECS 4
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /*
+* The hardware only supports
+* normal polarity and fixed period.
+*/
+   if (state->polarity != PWM_POLARITY_NORMAL ||
+   state->period < pc->period)
+   return -EINVAL;
+
+   if (!state->enabled) {
+   ret = lgm_pwm_enable(chip, 0);
+   return ret;
+   }
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+

[PATCH v7 0/2] pwm: intel: Add PWM driver for a new SoC

2020-08-17 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

v7:
- Address code quality related review concerns.
- Rename fan related property to pwm-*.
- Fix one make dt_binding_check reported error.

v6:
- Readjust .apply op as per review feedback.
- Add back pwm-cells property to resolve make dt_binding_check error.
  pwm-cells is a required property for PWM driver.
- Add back fan related optional properties.

v5:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve comments about Limitations.
  * Use return value of regmap_update_bits if container function returns
error code.
  * Modify .apply op to have strict checking for fixed period supported
by PWM HW.
  * Use u64 as type when use min_t for duty_cycle.
  * Add reset_control_assert() in failure case in probe where it was missing
earlier.
- Remove fan specific optional properties from pwm dt binding document (Rob 
Herring)

v4:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve notes and limitations comments.
  * Add common prefixes for all #defines.
  * Modify/Improve logic in .apply & .get_state ops as advised.
  * Skip error messages in probe when error is -EPROBE_DEFER.
  * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
  * Address other code quality related review concerns.
- Fix make dt_binding_check reported error in YAML file.

v3:
- Address below review concerns from Uwe Kleine-K�nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K�nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  54 +
 drivers/pwm/Kconfig|  11 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 267 +
 4 files changed, 333 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v6 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-07-28 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 54 ++
 1 file changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..9879972470dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  intel,fan-wire:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description: Specifies fan mode. Default when unspecified is 2.
+
+  intel,max-rpm:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description:
+  Specifies maximum RPM of fan attached to the system.
+  Default when unspecified is 4000.
+
++required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v6 0/2] pwm: intel: Add PWM driver for a new SoC

2020-07-28 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

v6:
- Readjust .apply op as per review feedback.
- Add back pwm-cells property to resolve make dt_binding_check error.
  pwm-cells is a required property for PWM driver.
- Add back fan related optional properties.

v5:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve comments about Limitations.
  * Use return value of regmap_update_bits if container function returns
error code.
  * Modify .apply op to have strict checking for fixed period supported
by PWM HW.
  * Use u64 as type when use min_t for duty_cycle.
  * Add reset_control_assert() in failure case in probe where it was missing
earlier.
- Remove fan specific optional properties from pwm dt binding document (Rob 
Herring)

v4:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve notes and limitations comments.
  * Add common prefixes for all #defines.
  * Modify/Improve logic in .apply & .get_state ops as advised.
  * Skip error messages in probe when error is -EPROBE_DEFER.
  * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
  * Address other code quality related review concerns.
- Fix make dt_binding_check reported error in YAML file.

v3:
- Address below review concerns from Uwe Kleine-K�nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K�nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.



Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  54 +
 drivers/pwm/Kconfig|  11 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 268 +
 4 files changed, 334 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v6 2/2] Add PWM fan controller driver for LGM SoC

2020-07-28 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 268 
 3 files changed, 280 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cb8d739067d2..3486edab09c4 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on OF && HAS_IOMEM
+   depends on X86 || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index a59c710e98c7..db154a6b4f51 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..61a722647f28
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_4WIRE 0x1
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NSECS 4000
+#define LGM_PWM_PERIOD_4WIRE_NSECS 4
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   /*
+* HW only supports only NORMAL polarity
+* HW supports fixed period
+*/
+   if (state->polarity != PWM_POLARITY_NORMAL ||
+   state->period < pc->period)
+   return -EINVAL;
+
+   if (!state->enabled) {
+   ret = lgm_pwm_enable(chip, 0);
+   return ret;
+   }
+
+   duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+   val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+

[PATCH v5 2/2] Add PWM fan controller driver for LGM SoC

2020-07-23 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 269 
 3 files changed, 281 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cb8d739067d2..3486edab09c4 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on OF && HAS_IOMEM
+   depends on X86 || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index a59c710e98c7..db154a6b4f51 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..7c6c21512d53
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_4WIRE 0x1
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NSECS 4000
+#define LGM_PWM_PERIOD_4WIRE_NSECS 4
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : 
LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   int ret;
+
+   if (!state->enabled) {
+   ret = lgm_pwm_enable(chip, 0);
+   return ret;
+   }
+
+   /*
+* HW only supports NORMAL polarity
+* HW supports fixed period which can not be changed/configured by user
+*/
+   if (state->polarity != PWM_POLARITY_NORMAL ||
+   state->period != pc->period)
+   return -EINVAL;
+
+   duty_cycle = min_t(u64, state->duty_cycle, state->period);
+   /* reg_value = duty_ns * LGM_PW

[PATCH v5 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-07-23 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 40 ++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..0211a0dc79ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v5 0/2] pwm: intel: Add PWM driver for a new SoC

2020-07-23 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

Patch series is baselined on linux 5.8-rc5.

v5:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve comments about Limitations.
  * Use return value of regmap_update_bits if container function returns
error code.
  * Modify .apply op to have strict checking for fixed period supported
by PWM HW.
  * Use u64 as type when use min_t for duty_cycle.
  * Add reset_control_assert() in failure case in probe where it was missing
earlier.
- Remove fan specific optional properties from pwm dt binding document (Rob 
Herring)

v4:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve notes and limitations comments.
  * Add common prefixes for all #defines.
  * Modify/Improve logic in .apply & .get_state ops as advised.
  * Skip error messages in probe when error is -EPROBE_DEFER.
  * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
  * Address other code quality related review concerns.
- Fix make dt_binding_check reported error in YAML file.

v3:
- Address below review concerns from Uwe Kleine-K�nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K�nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  40 +++
 drivers/pwm/Kconfig|  11 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 269 +
 4 files changed, 321 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v2 2/3] clk: intel: Improve locking in the driver

2020-07-16 Thread Rahul Tanwar

Remove/reduce unnecessary spin locking of the code.

Signed-off-by: Rahul Tanwar 
---
 drivers/clk/x86/clk-cgu.c | 17 +
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
index 88ebeb53b109..c379fedfb9f2 100644
--- a/drivers/clk/x86/clk-cgu.c
+++ b/drivers/clk/x86/clk-cgu.c
@@ -420,18 +420,14 @@ lgm_clk_ddiv_recalc_rate(struct clk_hw *hw, unsigned long 
parent_rate)
 {
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
unsigned int div0, div1, exdiv;
-   unsigned long flags;
u64 prate;
 
-   spin_lock_irqsave(>lock, flags);
div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
   ddiv->shift0, ddiv->width0) + 1;
div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
   ddiv->shift1, ddiv->width1) + 1;
exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg,
ddiv->shift2, ddiv->width2);
-   spin_unlock_irqrestore(>lock, flags);
-
prate = (u64)parent_rate;
do_div(prate, div0);
do_div(prate, div1);
@@ -548,24 +544,21 @@ lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long 
rate,
div = div * 2;
div = DIV_ROUND_CLOSEST_ULL((u64)div, 5);
}
+   spin_unlock_irqrestore(>lock, flags);
 
-   if (div <= 0) {
-   spin_unlock_irqrestore(>lock, flags);
+   if (div <= 0)
return *prate;
-   }
 
-   if (lgm_clk_get_ddiv_val(div, , ) != 0) {
-   if (lgm_clk_get_ddiv_val(div + 1, , ) != 0) {
-   spin_unlock_irqrestore(>lock, flags);
+   if (lgm_clk_get_ddiv_val(div, , ) != 0)
+   if (lgm_clk_get_ddiv_val(div + 1, , ) != 0)
return -EINVAL;
-   }
-   }
 
rate64 = *prate;
do_div(rate64, ddiv1);
do_div(rate64, ddiv2);
 
/* if predivide bit is enabled, modify rounded rate by factor of 2.5 */
+   spin_lock_irqsave(>lock, flags);
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
rate64 = rate64 * 2;
rate64 = DIV_ROUND_CLOSEST_ULL(rate64, 5);
-- 
2.11.0

[PATCH v2 3/3] clk: intel: Avoid unnecessary memset by improving code

2020-07-16 Thread Rahul Tanwar

memset can be avoided in a loop if the variables used are declared
inside the loop. Move such variables declaration inside the loop
to avoid memset.

Signed-off-by: Rahul Tanwar 
---
 drivers/clk/x86/clk-cgu.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
index c379fedfb9f2..9a1be7035fd0 100644
--- a/drivers/clk/x86/clk-cgu.c
+++ b/drivers/clk/x86/clk-cgu.c
@@ -581,19 +581,18 @@ int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
  unsigned int nr_clk)
 {
struct device *dev = ctx->dev;
-   struct clk_init_data init = {};
-   struct lgm_clk_ddiv *ddiv;
struct clk_hw *hw;
unsigned int idx;
int ret;
 
for (idx = 0; idx < nr_clk; idx++, list++) {
-   ddiv = NULL;
+   struct clk_init_data init = {};
+   struct lgm_clk_ddiv *ddiv = NULL;
+
ddiv = devm_kzalloc(dev, sizeof(*ddiv), GFP_KERNEL);
if (!ddiv)
return -ENOMEM;
 
-   memset(, 0, sizeof(init));
init.name = list->name;
init.ops = _clk_ddiv_ops;
init.flags = list->flags;
-- 
2.11.0

[PATCH v2 1/3] clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()

2020-07-16 Thread Rahul Tanwar

To ensure that clks are unregistered in case of any failure, use
devm_clk_hw_register() instead of clk_hw_register().

Signed-off-by: Rahul Tanwar 
---
 drivers/clk/x86/clk-cgu-pll.c | 2 +-
 drivers/clk/x86/clk-cgu.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/x86/clk-cgu-pll.c b/drivers/clk/x86/clk-cgu-pll.c
index c03cc6b85b9f..3179557b5f78 100644
--- a/drivers/clk/x86/clk-cgu-pll.c
+++ b/drivers/clk/x86/clk-cgu-pll.c
@@ -128,7 +128,7 @@ lgm_clk_register_pll(struct lgm_clk_provider *ctx,
pll->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret)
return ERR_PTR(ret);
 
diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
index 56af0e04ec1e..88ebeb53b109 100644
--- a/drivers/clk/x86/clk-cgu.c
+++ b/drivers/clk/x86/clk-cgu.c
@@ -119,7 +119,7 @@ lgm_clk_register_mux(struct lgm_clk_provider *ctx,
mux->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret)
return ERR_PTR(ret);
 
@@ -247,7 +247,7 @@ lgm_clk_register_divider(struct lgm_clk_provider *ctx,
div->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret)
return ERR_PTR(ret);
 
@@ -361,7 +361,7 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx,
gate->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret)
return ERR_PTR(ret);
 
@@ -624,7 +624,7 @@ int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
ddiv->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret) {
dev_err(dev, "register clk: %s failed!\n", list->name);
return ret;
-- 
2.11.0

[PATCH v1] clk: intel: Address pending review concerns

2020-07-14 Thread Rahul Tanwar

Use devm_clk_hw_register() instead of clk_hw_register().
Remove unnecessary locking. Avoid memset by improving code.

Signed-off-by: Rahul Tanwar 
---
 drivers/clk/x86/clk-cgu-pll.c |  2 +-
 drivers/clk/x86/clk-cgu.c | 32 
 2 files changed, 13 insertions(+), 21 deletions(-)

diff --git a/drivers/clk/x86/clk-cgu-pll.c b/drivers/clk/x86/clk-cgu-pll.c
index c03cc6b85b9f..3179557b5f78 100644
--- a/drivers/clk/x86/clk-cgu-pll.c
+++ b/drivers/clk/x86/clk-cgu-pll.c
@@ -128,7 +128,7 @@ lgm_clk_register_pll(struct lgm_clk_provider *ctx,
pll->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret)
return ERR_PTR(ret);
 
diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
index 56af0e04ec1e..9a1be7035fd0 100644
--- a/drivers/clk/x86/clk-cgu.c
+++ b/drivers/clk/x86/clk-cgu.c
@@ -119,7 +119,7 @@ lgm_clk_register_mux(struct lgm_clk_provider *ctx,
mux->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret)
return ERR_PTR(ret);
 
@@ -247,7 +247,7 @@ lgm_clk_register_divider(struct lgm_clk_provider *ctx,
div->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret)
return ERR_PTR(ret);
 
@@ -361,7 +361,7 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx,
gate->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret)
return ERR_PTR(ret);
 
@@ -420,18 +420,14 @@ lgm_clk_ddiv_recalc_rate(struct clk_hw *hw, unsigned long 
parent_rate)
 {
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
unsigned int div0, div1, exdiv;
-   unsigned long flags;
u64 prate;
 
-   spin_lock_irqsave(>lock, flags);
div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
   ddiv->shift0, ddiv->width0) + 1;
div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
   ddiv->shift1, ddiv->width1) + 1;
exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg,
ddiv->shift2, ddiv->width2);
-   spin_unlock_irqrestore(>lock, flags);
-
prate = (u64)parent_rate;
do_div(prate, div0);
do_div(prate, div1);
@@ -548,24 +544,21 @@ lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long 
rate,
div = div * 2;
div = DIV_ROUND_CLOSEST_ULL((u64)div, 5);
}
+   spin_unlock_irqrestore(>lock, flags);
 
-   if (div <= 0) {
-   spin_unlock_irqrestore(>lock, flags);
+   if (div <= 0)
return *prate;
-   }
 
-   if (lgm_clk_get_ddiv_val(div, , ) != 0) {
-   if (lgm_clk_get_ddiv_val(div + 1, , ) != 0) {
-   spin_unlock_irqrestore(>lock, flags);
+   if (lgm_clk_get_ddiv_val(div, , ) != 0)
+   if (lgm_clk_get_ddiv_val(div + 1, , ) != 0)
return -EINVAL;
-   }
-   }
 
rate64 = *prate;
do_div(rate64, ddiv1);
do_div(rate64, ddiv2);
 
/* if predivide bit is enabled, modify rounded rate by factor of 2.5 */
+   spin_lock_irqsave(>lock, flags);
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
rate64 = rate64 * 2;
rate64 = DIV_ROUND_CLOSEST_ULL(rate64, 5);
@@ -588,19 +581,18 @@ int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
  unsigned int nr_clk)
 {
struct device *dev = ctx->dev;
-   struct clk_init_data init = {};
-   struct lgm_clk_ddiv *ddiv;
struct clk_hw *hw;
unsigned int idx;
int ret;
 
for (idx = 0; idx < nr_clk; idx++, list++) {
-   ddiv = NULL;
+   struct clk_init_data init = {};
+   struct lgm_clk_ddiv *ddiv = NULL;
+
ddiv = devm_kzalloc(dev, sizeof(*ddiv), GFP_KERNEL);
if (!ddiv)
return -ENOMEM;
 
-   memset(, 0, sizeof(init));
init.name = list->name;
init.ops = _clk_ddiv_ops;
init.flags = list->flags;
@@ -624,7 +616,7 @@ int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
ddiv->hw.init = 
 
hw = >hw;
-   ret = clk_hw_register(dev, hw);
+   ret = devm_clk_hw_register(dev, hw);
if (ret) {
dev_err(dev, "register clk: %s failed!\n", list->name);
return ret;
-- 
2.11.0

[PATCH v4 2/2] Add PWM fan controller driver for LGM SoC

2020-06-30 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |  11 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 266 
 3 files changed, 278 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cb8d739067d2..3486edab09c4 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on OF && HAS_IOMEM
+   depends on X86 || COMPILE_TEST
+   select REGMAP_MMIO
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index a59c710e98c7..db154a6b4f51 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..fddfedd56fc3
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Notes & Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LGM_PWM_FAN_CON0   0x0
+#define LGM_PWM_FAN_EN_EN  BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_4WIRE 0x1
+#define LGM_PWM_FAN_MODE_MSK   BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1   0x4
+#define LGM_PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM(BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS8
+
+#define LGM_PWM_PERIOD_2WIRE_NSECS 4000
+#define LGM_PWM_PERIOD_4WIRE_NSECS 4
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+  enable ? LGM_PWM_FAN_EN_EN : LGM_PWM_FAN_EN_DIS);
+
+   return 0;
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   unsigned int period;
+
+   if (!state->enabled) {
+   lgm_pwm_enable(chip, 0);
+   return 0;
+   }
+
+   period = min_t(u64, state->period, pc->period);
+
+   if (state->polarity != PWM_POLARITY_NORMAL ||
+   period < pc->period)
+   return -EINVAL;
+
+   duty_cycle = min_t(u32, state->duty_cycle, period);
+   /* reg_value = duty_ns * LGM_PWM_MAX_DUTY_CYCLE(0xff) / period_ns */
+   val = duty_cycle * LGM_PWM_MAX_DUTY

[PATCH v4 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-06-30 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 50 ++
 1 file changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..120bf3d85a24
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  intel,fan-wire:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description: Specifies fan mode. Default when unspecified is 2.
+
+  intel,max-rpm:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description:
+  Specifies maximum RPM of fan attached to the system.
+  Default when unspecified is 4000.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v4 0/2] pwm: intel: Add PWM driver for a new SoC

2020-06-30 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

Patch series is baselined on linux 5.8-rc2.

v3:
- Address below review concerns from Uwe Kleine-K�nig.
  * Improve notes and limitations comments.
  * Add common prefixes for all #defines.
  * Modify/Improve logic in .apply & .get_state ops as advised.
  * Skip error messages in probe when error is -EPROBE_DEFER.
  * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
  * Address other code quality related review concerns.
- Fix make dt_binding_check reported error in YAML file.

v3:
- Address below review concerns from Uwe Kleine-K�nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K�nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  50 
 drivers/pwm/Kconfig|  11 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 266 +
 4 files changed, 328 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v3 2/2] Add PWM fan controller driver for LGM SoC

2020-06-29 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |   9 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 265 
 3 files changed, 275 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cb8d739067d2..a3303e22d5fa 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,15 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on X86 || COMPILE_TEST
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index a59c710e98c7..db154a6b4f51 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..661fa7d9145d
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Notes & Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - Supports 100% duty cycle.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PWM_FAN_CON0   0x0
+#define PWM_FAN_EN_EN  BIT(0)
+#define PWM_FAN_EN_DIS 0x0
+#define PWM_FAN_EN_MSK BIT(0)
+#define PWM_FAN_MODE_2WIRE 0x0
+#define PWM_FAN_MODE_4WIRE 0x1
+#define PWM_FAN_MODE_MSK   BIT(1)
+#define PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define PWM_FAN_CON1   0x4
+#define PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define MAX_RPM(BIT(16) - 1)
+#define DFAULT_RPM 4000
+#define MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define DC_BITS8
+
+#define PERIOD_2WIRE_NSECS 4000
+#define PERIOD_4WIRE_NSECS 4
+
+#define LGM_PWM_DIV_ROUND_DOWN(n, d) (((n) + ((d) / 2) - 1) / (d))
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   if (enable)
+   regmap_update_bits(regmap, PWM_FAN_CON0,
+  PWM_FAN_EN_MSK, PWM_FAN_EN_EN);
+   else
+   regmap_update_bits(regmap, PWM_FAN_CON0,
+  PWM_FAN_EN_MSK, PWM_FAN_EN_DIS);
+
+   return 0;
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+const struct pwm_state *state)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   u32 duty_cycle, val;
+   unsigned int period;
+
+   period = min_t(unsigned int, state->period, pc->period);
+
+   if (state->polarity != PWM_POLARITY_NORMAL ||
+   period < pc->period)
+   return -EINVAL;
+
+   duty_cycle = min_t(u32, state->duty_cycle, period);
+
+   /* reg_value = duty_ns * MAX_REG_VAL(0xff) / period_ns */
+   val = LGM_PWM_DIV_ROUND_DOWN(duty_cycle << DC_BITS, period);
+   val = min_t(u32, val, MAX_DUTY_CYCLE);
+

[PATCH v3 0/2] pwm: intel: Add PWM driver for a new SoC

2020-06-29 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

Patch series is baselined on linux 5.8-rc2.

v3:
- Address below review concerns from Uwe Kleine-K�nig.
  * Remove fan rpm calibration task from the driver.
  * Modify apply op as per the review feedback.
  * Add roundup & round down where necessary.
  * Address other misc code quality related review concerns.
  * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
  * Improve dt binding document.

v2:
- Address below review concerns from Uwe Kleine-K�nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.


Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  51 
 drivers/pwm/Kconfig|   9 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 265 +
 4 files changed, 326 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v3 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-06-29 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 51 ++
 1 file changed, 51 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..bc3fbc46ec5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  intel,fan-wire:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description: Specifies fan mode. Default when unspecified is 2.
+
+  intel,max-rpm:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description:
+  Specifies maximum RPM of fan attached to the system.
+  Default when unspecified is 4000.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v2 2/2] Add PWM fan controller driver for LGM SoC

2020-06-18 Thread Rahul Tanwar

Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |   9 +
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 400 
 3 files changed, 410 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cb8d739067d2..a3303e22d5fa 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,15 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on X86 || COMPILE_TEST
+   help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index a59c710e98c7..db154a6b4f51 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_IQS620A)  += pwm-iqs620a.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..3c7077acb161
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Notes & Limitations:
+ * - The hardware supports fixed period which is dependent on 2/3 or 4
+ *   wire fan mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ *   keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ *   and new setting for the first period. From second period, the output is
+ *   based on new setting.
+ * - Supports 100% duty cycle.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ *   this PWM controller.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PWM_FAN_CON0   0x0
+#define PWM_FAN_EN_EN  BIT(0)
+#define PWM_FAN_EN_DIS 0x0
+#define PWM_FAN_EN_MSK BIT(0)
+#define PWM_FAN_MODE_2WIRE 0x0
+#define PWM_FAN_MODE_4WIRE 0x1
+#define PWM_FAN_MODE_MSK   BIT(1)
+#define PWM_FAN_PWM_DIS_DIS0x0
+#define PWM_FAN_PWM_DIS_MSKBIT(2)
+#define PWM_TACH_EN_EN 0x1
+#define PWM_TACH_EN_MSKBIT(4)
+#define PWM_TACH_PLUS_20x0
+#define PWM_TACH_PLUS_40x1
+#define PWM_TACH_PLUS_MSK  BIT(5)
+#define PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define PWM_FAN_CON1   0x4
+#define PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define PWM_FAN_STAT   0x10
+#define PWM_FAN_TACH_MASK  GENMASK(15, 0)
+
+#define MAX_RPM(BIT(16) - 1)
+#define DFAULT_RPM 4000
+#define MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define FRAC_BITS  10
+#define DC_BITS8
+#define TWO_TENTH  204
+
+#define PERIOD_2WIRE_NSECS 4000
+#define PERIOD_4WIRE_NSECS 4
+
+#define TWO_SECONDS2000
+#define IGNORE_FIRST_ERR   1
+#define THIRTY_SECS_WINDOW 15
+#define ERR_CNT_THRESHOLD  6
+
+struct lgm_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap *regmap;
+   struct clk *clk;
+   struct reset_control *rst;
+   u32 tach_en;
+   u32 max_rpm;
+   u32 set_rpm;
+   u32 set_dc;
+   u32 period;
+   struct delayed_work work;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_update_dc(struct lgm_pwm_chip *pc, u32 val)
+{
+   return regmap_update_bits(pc->regmap, PWM_FAN_CON0, PWM_FAN_DC_MSK,
+ FIELD_PREP(PWM_FAN_DC_MSK, val));
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+   struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   if (enable) {
+   regmap_update_bits(regmap, PWM_FAN_CON0,
+  PWM_FAN_EN_MSK, PWM_FAN_EN_EN);
+

[PATCH v2 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC

2020-06-18 Thread Rahul Tanwar

Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 57 ++
 1 file changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml 
b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index ..e71cc25e4e6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+  intel,fan-wire:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description: Specifies fan mode
+
+  intel,tach-plus:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description: Specifies fan tach pulse periods
+
+  intel,max-rpm:
+$ref: '/schemas/types.yaml#/definitions/uint32'
+description: Specifies maximum RPM of fan attached to the system
+
+required:
+  - compatible
+  - reg
+  - "#pwm-cells"
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v2 0/2] pwm: intel: Add PWM driver for a new SoC

2020-06-18 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM fan controller driver for LGM SoC.

Patch series is baselined on linux 5.8-rc1.

v2:
- Address below review concerns from Uwe Kleine-K?nig.
  * Add notes and limitations about PWM HW.
  * Rename all functions and structure to lgm_pwm_* 
  * Readjust space aligninment in structure fields to single space.
  * Switch to using apply instead of config/enable/disable.
  * Address other code quality related concerns.
  * Rebase to 5.8-rc1.
- Address review concerns in dt binding YAML from Rob Herring.

v1:
- Initial version.

Rahul Tanwar (2):
  Add DT bindings YAML schema for PWM fan controller of LGM SoC
  Add PWM fan controller driver for LGM SoC

 .../devicetree/bindings/pwm/intel,lgm-pwm.yaml |  57 +++
 drivers/pwm/Kconfig|   9 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 400 +
 4 files changed, 467 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v1 0/2] pwm: intel: Add PWM driver for new SoC

2020-05-22 Thread Rahul Tanwar

Patch 1 adds dt binding document in YAML format.
Patch 2 add PWM driver for LGM SoC.


Rahul Tanwar (2):
  Add YAML schema for a new PWM driver
  Add PWM driver for LGM

 .../devicetree/bindings/pwm/pwm-intel-lgm.yaml |  43 +++
 drivers/pwm/Kconfig|   9 +
 drivers/pwm/Makefile   |   1 +
 drivers/pwm/pwm-intel-lgm.c| 356 +
 4 files changed, 409 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm-intel-lgm.yaml
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

-- 
2.11.0

[PATCH v1 1/2] Add YAML schema for a new PWM driver

2020-05-22 Thread Rahul Tanwar

Add DT bindings YAML schema for PWM controller driver of
Lightning Mountain(LGM) SoC.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/pwm/pwm-intel-lgm.yaml | 43 ++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm-intel-lgm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/pwm-intel-lgm.yaml 
b/Documentation/devicetree/bindings/pwm/pwm-intel-lgm.yaml
new file mode 100644
index ..adb33265aa5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-intel-lgm.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/pwm-intel-lgm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM controller
+
+maintainers:
+  - Rahul Tanwar 
+
+properties:
+  compatible:
+const: intel,lgm-pwm
+
+  reg:
+maxItems: 1
+
+  "#pwm-cells":
+const: 2
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#pwm-cells"
+  - clocks
+  - resets
+
+examples:
+  - |
+pwm: pwm@e0d0 {
+compatible = "intel,lgm-pwm";
+reg = <0xe0d0 0x30>;
+#pwm-cells = <2>;
+clocks = < 126>;
+resets = < 0x30 21>;
+};
-- 
2.11.0

[PATCH v1 2/2] Add PWM driver for LGM

2020-05-22 Thread Rahul Tanwar

Add PWM controller driver for Intel's Lightning Mountain(LGM) SoC.

Signed-off-by: Rahul Tanwar 
---
 drivers/pwm/Kconfig |   9 ++
 drivers/pwm/Makefile|   1 +
 drivers/pwm/pwm-intel-lgm.c | 356 
 3 files changed, 366 insertions(+)
 create mode 100644 drivers/pwm/pwm-intel-lgm.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index eebbc917ac97..a582214f50b2 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,15 @@ config PWM_IMX_TPM
  To compile this driver as a module, choose M here: the module
  will be called pwm-imx-tpm.
 
+config PWM_INTEL_LGM
+   tristate "Intel LGM PWM support"
+   depends on X86 || COMPILE_TEST
+   help
+ Generic PWM framework driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
 config PWM_JZ4740
tristate "Ingenic JZ47xx PWM support"
depends on MACH_INGENIC
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 9a475073dafc..c16a972a101d 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
 obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
 obj-$(CONFIG_PWM_IMX27)+= pwm-imx27.o
 obj-$(CONFIG_PWM_IMX_TPM)  += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM)+= pwm-intel-lgm.o
 obj-$(CONFIG_PWM_JZ4740)   += pwm-jz4740.o
 obj-$(CONFIG_PWM_LP3943)   += pwm-lp3943.o
 obj-$(CONFIG_PWM_LPC18XX_SCT)  += pwm-lpc18xx-sct.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index ..e307fd2457df
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PWM_FAN_CON0   0x0
+#define PWM_FAN_EN_EN  BIT(0)
+#define PWM_FAN_EN_DIS 0x0
+#define PWM_FAN_EN_MSK BIT(0)
+#define PWM_FAN_MODE_2WIRE 0x0
+#define PWM_FAN_MODE_4WIRE 0x1
+#define PWM_FAN_MODE_MSK   BIT(1)
+#define PWM_FAN_PWM_DIS_DIS0x0
+#define PWM_FAN_PWM_DIS_MSKBIT(2)
+#define PWM_TACH_EN_EN 0x1
+#define PWM_TACH_EN_MSKBIT(4)
+#define PWM_TACH_PLUS_20x0
+#define PWM_TACH_PLUS_40x1
+#define PWM_TACH_PLUS_MSK  BIT(5)
+#define PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define PWM_FAN_CON1   0x4
+#define PWM_FAN_MAX_RPM_MSKGENMASK(15, 0)
+
+#define PWM_FAN_STAT   0x10
+#define PWM_FAN_TACH_MASK  GENMASK(15, 0)
+
+#define MAX_RPM(BIT(16) - 1)
+#define DFAULT_RPM 4000
+#define MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define FRAC_BITS  10
+#define TWO_TENTH  204
+
+#define TWO_SECONDS2000
+#define IGNORE_FIRST_ERR   1
+#define THIRTY_SECS_WINDOW 15
+#define ERR_CNT_THRESHOLD  6
+
+struct intel_pwm_chip {
+   struct pwm_chip chip;
+   struct regmap   *regmap;
+   struct clk  *clk;
+   struct reset_control*rst;
+   u32 tach_en;
+   u32 max_rpm;
+   u32 set_rpm;
+   u32 set_dc;
+   struct delayed_work work;
+};
+
+static inline struct intel_pwm_chip *to_intel_pwm_chip(struct pwm_chip *chip)
+{
+   return container_of(chip, struct intel_pwm_chip, chip);
+}
+
+static int pwm_update_dc(struct intel_pwm_chip *pc, u32 val)
+{
+   return regmap_update_bits(pc->regmap, PWM_FAN_CON0, PWM_FAN_DC_MSK,
+ FIELD_PREP(PWM_FAN_DC_MSK, val));
+}
+
+static int intel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+   int duty_ns, int period_ns)
+{
+   struct intel_pwm_chip *pc = to_intel_pwm_chip(chip);
+   u32 val;
+
+   val = DIV_ROUND_CLOSEST(duty_ns * MAX_DUTY_CYCLE, period_ns);
+   val = min_t(u32, val, MAX_DUTY_CYCLE);
+
+   if (pc->tach_en) {
+   pc->set_dc = val;
+   pc->set_rpm = val * pc->max_rpm / MAX_DUTY_CYCLE;
+   }
+
+   return pwm_update_dc(pc, val);
+}
+
+static int intel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+   struct intel_pwm_chip *pc = to_intel_pwm_chip(chip);
+   struct regmap *regmap = pc->regmap;
+
+   regmap_update_bits(regmap, PWM_FAN_CON0,
+  PWM_FAN_EN_MSK, PWM_FAN_EN_EN);
+
+   if (pc->tach_en)
+   schedule_delayed_work(>work, msecs_to_jiffies(1));
+
+   return 0;
+}
+
+static void intel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+   struct intel_pwm_chip *pc = to_intel_pwm_chip(chip);
+   struct regmap *re

[PATCH v3 0/2] serial: lantiq: Make driver modular & console configurable

2020-05-10 Thread Rahul Tanwar

Patch 1 is to make lantiq UART driver's use as console selectable/configurable.
Patch 2 adds changes so the driver can be compiled as module.

v3:
- Fix a section mismatch warning. Reported-by: kbuild test robot 
.

v2:
- Split into two patches. One for console configuration and two for
  modular driver. (Greg KH) 

v1:
- Initial version.


Rahul Tanwar (2):
  serial: lantiq: Make UART's use as console selectable
  serial: lantiq: Make driver modular

 drivers/tty/serial/Kconfig  | 13 +++--
 drivers/tty/serial/lantiq.c | 40 +++-
 2 files changed, 46 insertions(+), 7 deletions(-)

-- 
2.11.0

[PATCH v3 1/2] serial: lantiq: Make UART's use as console selectable

2020-05-10 Thread Rahul Tanwar

Lantiq UART driver can be used for system console. Add changes to
make this driver's use as console selectable/configurable.

Signed-off-by: Rahul Tanwar 
---
 drivers/tty/serial/Kconfig  |  9 -
 drivers/tty/serial/lantiq.c | 11 ++-
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 4b0a7b98f8c7..bb4009a1135f 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1037,10 +1037,17 @@ config SERIAL_LANTIQ
bool "Lantiq serial driver"
depends on (LANTIQ || X86) || COMPILE_TEST
select SERIAL_CORE
+   help
+ Support for UART on Lantiq and Intel SoCs.
+
+config SERIAL_LANTIQ_CONSOLE
+   bool "Console on Lantiq UART"
+   depends on SERIAL_LANTIQ=y
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
help
- Support for console and UART on Lantiq SoCs.
+ Select this option if you would like to use a Lantiq UART as the
+ system console.
 
 config SERIAL_QE
tristate "Freescale QUICC Engine serial port support"
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index c5e46ff972e4..d3b62a1be6ad 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -597,6 +597,7 @@ static const struct uart_ops lqasc_pops = {
.verify_port =  lqasc_verify_port,
 };
 
+#ifdef CONFIG_SERIAL_LANTIQ_CONSOLE
 static void
 lqasc_console_putchar(struct uart_port *port, int ch)
 {
@@ -705,6 +706,14 @@ lqasc_serial_early_console_setup(struct earlycon_device 
*device,
 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
 
+#define LANTIQ_SERIAL_CONSOLE  (_console)
+
+#else
+
+#define LANTIQ_SERIAL_CONSOLE  NULL
+
+#endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */
+
 static struct uart_driver lqasc_reg = {
.owner =THIS_MODULE,
.driver_name =  DRVNAME,
@@ -712,7 +721,7 @@ static struct uart_driver lqasc_reg = {
.major =0,
.minor =0,
.nr =   MAXPORTS,
-   .cons = _console,
+   .cons = LANTIQ_SERIAL_CONSOLE,
 };
 
 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
-- 
2.11.0

[PATCH v3 2/2] serial: lantiq: Make driver modular

2020-05-10 Thread Rahul Tanwar

Add changes so Lantiq serial driver can be compiled as a module.

Signed-off-by: Rahul Tanwar 
---
 drivers/tty/serial/Kconfig  |  4 +++-
 drivers/tty/serial/lantiq.c | 29 +
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index bb4009a1135f..c0681da66653 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1034,11 +1034,13 @@ config SERIAL_SIFIVE_CONSOLE
  boot time.)
 
 config SERIAL_LANTIQ
-   bool "Lantiq serial driver"
+   tristate "Lantiq serial driver"
depends on (LANTIQ || X86) || COMPILE_TEST
select SERIAL_CORE
help
  Support for UART on Lantiq and Intel SoCs.
+ To compile this driver as a module, select M here. The
+ module will be called lantiq.
 
 config SERIAL_LANTIQ_CONSOLE
bool "Console on Lantiq UART"
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index d3b62a1be6ad..62813e421f12 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -823,8 +824,7 @@ static void free_irq_intel(struct uart_port *port)
free_irq(ltq_port->common_irq, port);
 }
 
-static int __init
-lqasc_probe(struct platform_device *pdev)
+static int lqasc_probe(struct platform_device *pdev)
 {
struct device_node *node = pdev->dev.of_node;
struct ltq_uart_port *ltq_port;
@@ -908,6 +908,13 @@ lqasc_probe(struct platform_device *pdev)
return ret;
 }
 
+static int lqasc_remove(struct platform_device *pdev)
+{
+   struct uart_port *port = platform_get_drvdata(pdev);
+
+   return uart_remove_one_port(_reg, port);
+}
+
 static const struct ltq_soc_data soc_data_lantiq = {
.fetch_irq = fetch_irq_lantiq,
.request_irq = request_irq_lantiq,
@@ -925,8 +932,11 @@ static const struct of_device_id ltq_asc_match[] = {
{ .compatible = "intel,lgm-asc", .data = _data_intel },
{},
 };
+MODULE_DEVICE_TABLE(of, ltq_asc_match);
 
 static struct platform_driver lqasc_driver = {
+   .probe  = lqasc_probe,
+   .remove = lqasc_remove,
.driver = {
.name   = DRVNAME,
.of_match_table = ltq_asc_match,
@@ -942,10 +952,21 @@ init_lqasc(void)
if (ret != 0)
return ret;
 
-   ret = platform_driver_probe(_driver, lqasc_probe);
+   ret = platform_driver_register(_driver);
if (ret != 0)
uart_unregister_driver(_reg);
 
return ret;
 }
-device_initcall(init_lqasc);
+
+static void __exit exit_lqasc(void)
+{
+   platform_driver_unregister(_driver);
+   uart_unregister_driver(_reg);
+}
+
+module_init(init_lqasc);
+module_exit(exit_lqasc);
+
+MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs");
+MODULE_LICENSE("GPL v2");
-- 
2.11.0

[PATCH v2 1/2] serial: lantiq: Make UART's use as console selectable

2020-05-09 Thread Rahul Tanwar

Lantiq UART driver can be used for system console. Add changes to
make this driver's use as console selectable/configurable.

Signed-off-by: Rahul Tanwar 
---
 drivers/tty/serial/Kconfig  |  9 -
 drivers/tty/serial/lantiq.c | 11 ++-
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 4b0a7b98f8c7..bb4009a1135f 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1037,10 +1037,17 @@ config SERIAL_LANTIQ
bool "Lantiq serial driver"
depends on (LANTIQ || X86) || COMPILE_TEST
select SERIAL_CORE
+   help
+ Support for UART on Lantiq and Intel SoCs.
+
+config SERIAL_LANTIQ_CONSOLE
+   bool "Console on Lantiq UART"
+   depends on SERIAL_LANTIQ=y
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
help
- Support for console and UART on Lantiq SoCs.
+ Select this option if you would like to use a Lantiq UART as the
+ system console.
 
 config SERIAL_QE
tristate "Freescale QUICC Engine serial port support"
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index c5e46ff972e4..d3b62a1be6ad 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -597,6 +597,7 @@ static const struct uart_ops lqasc_pops = {
.verify_port =  lqasc_verify_port,
 };
 
+#ifdef CONFIG_SERIAL_LANTIQ_CONSOLE
 static void
 lqasc_console_putchar(struct uart_port *port, int ch)
 {
@@ -705,6 +706,14 @@ lqasc_serial_early_console_setup(struct earlycon_device 
*device,
 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
 
+#define LANTIQ_SERIAL_CONSOLE  (_console)
+
+#else
+
+#define LANTIQ_SERIAL_CONSOLE  NULL
+
+#endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */
+
 static struct uart_driver lqasc_reg = {
.owner =THIS_MODULE,
.driver_name =  DRVNAME,
@@ -712,7 +721,7 @@ static struct uart_driver lqasc_reg = {
.major =0,
.minor =0,
.nr =   MAXPORTS,
-   .cons = _console,
+   .cons = LANTIQ_SERIAL_CONSOLE,
 };
 
 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
-- 
2.11.0

[PATCH v2 2/2] serial: lantiq: Make driver modular

2020-05-09 Thread Rahul Tanwar

Add changes so Lantiq serial driver can be compiled as a module.

Signed-off-by: Rahul Tanwar 
---
 drivers/tty/serial/Kconfig  |  4 +++-
 drivers/tty/serial/lantiq.c | 26 --
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index bb4009a1135f..c0681da66653 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1034,11 +1034,13 @@ config SERIAL_SIFIVE_CONSOLE
  boot time.)
 
 config SERIAL_LANTIQ
-   bool "Lantiq serial driver"
+   tristate "Lantiq serial driver"
depends on (LANTIQ || X86) || COMPILE_TEST
select SERIAL_CORE
help
  Support for UART on Lantiq and Intel SoCs.
+ To compile this driver as a module, select M here. The
+ module will be called lantiq.
 
 config SERIAL_LANTIQ_CONSOLE
bool "Console on Lantiq UART"
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index d3b62a1be6ad..42fa52a224f7 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -908,6 +909,13 @@ lqasc_probe(struct platform_device *pdev)
return ret;
 }
 
+static int lqasc_remove(struct platform_device *pdev)
+{
+   struct uart_port *port = platform_get_drvdata(pdev);
+
+   return uart_remove_one_port(_reg, port);
+}
+
 static const struct ltq_soc_data soc_data_lantiq = {
.fetch_irq = fetch_irq_lantiq,
.request_irq = request_irq_lantiq,
@@ -925,8 +933,11 @@ static const struct of_device_id ltq_asc_match[] = {
{ .compatible = "intel,lgm-asc", .data = _data_intel },
{},
 };
+MODULE_DEVICE_TABLE(of, ltq_asc_match);
 
 static struct platform_driver lqasc_driver = {
+   .probe  = lqasc_probe,
+   .remove = lqasc_remove,
.driver = {
.name   = DRVNAME,
.of_match_table = ltq_asc_match,
@@ -942,10 +953,21 @@ init_lqasc(void)
if (ret != 0)
return ret;
 
-   ret = platform_driver_probe(_driver, lqasc_probe);
+   ret = platform_driver_register(_driver);
if (ret != 0)
uart_unregister_driver(_reg);
 
return ret;
 }
-device_initcall(init_lqasc);
+
+static void __exit exit_lqasc(void)
+{
+   platform_driver_unregister(_driver);
+   uart_unregister_driver(_reg);
+}
+
+module_init(init_lqasc);
+module_exit(exit_lqasc);
+
+MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs");
+MODULE_LICENSE("GPL v2");
-- 
2.11.0

[PATCH] serial: lantiq: Make driver modular and console configurable

2020-05-08 Thread Rahul Tanwar

Add changes so Lantiq serial driver can be compiled as a module.
Also, make this driver's use as console selectable/configurable.

Signed-off-by: Rahul Tanwar 
---
 drivers/tty/serial/Kconfig  | 13 +++--
 drivers/tty/serial/lantiq.c | 43 ---
 2 files changed, 51 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 4b0a7b98f8c7..996782247174 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1034,13 +1034,22 @@ config SERIAL_SIFIVE_CONSOLE
  boot time.)
 
 config SERIAL_LANTIQ
-   bool "Lantiq serial driver"
+   tristate "Lantiq serial driver"
depends on (LANTIQ || X86) || COMPILE_TEST
select SERIAL_CORE
+   help
+ Support for UART on Lantiq and Intel SoCs.
+ To compile this driver as a module, choose M here, the
+ module will be called lantiq.
+
+config SERIAL_LANTIQ_CONSOLE
+   bool "Console on Lantiq UART"
+   depends on SERIAL_LANTIQ=y
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
help
- Support for console and UART on Lantiq SoCs.
+ Select this option if you would like to use a Lantiq UART as the
+ system console.
 
 config SERIAL_QE
tristate "Freescale QUICC Engine serial port support"
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index c5e46ff972e4..93ed59bccd11 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -597,6 +598,13 @@ static const struct uart_ops lqasc_pops = {
.verify_port =  lqasc_verify_port,
 };
 
+
+/*
+ * Linux console interface
+ */
+
+#ifdef CONFIG_SERIAL_LANTIQ_CONSOLE
+
 static void
 lqasc_console_putchar(struct uart_port *port, int ch)
 {
@@ -705,6 +713,14 @@ lqasc_serial_early_console_setup(struct earlycon_device 
*device,
 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
 
+#define LANTIQ_SERIAL_CONSOLE  (_console)
+
+#else
+
+#define LANTIQ_SERIAL_CONSOLE  NULL
+
+#endif
+
 static struct uart_driver lqasc_reg = {
.owner =THIS_MODULE,
.driver_name =  DRVNAME,
@@ -712,7 +728,7 @@ static struct uart_driver lqasc_reg = {
.major =0,
.minor =0,
.nr =   MAXPORTS,
-   .cons = _console,
+   .cons = LANTIQ_SERIAL_CONSOLE,
 };
 
 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
@@ -899,6 +915,13 @@ lqasc_probe(struct platform_device *pdev)
return ret;
 }
 
+static int lqasc_remove(struct platform_device *pdev)
+{
+   struct uart_port *port = platform_get_drvdata(pdev);
+
+   return uart_remove_one_port(_reg, port);
+}
+
 static const struct ltq_soc_data soc_data_lantiq = {
.fetch_irq = fetch_irq_lantiq,
.request_irq = request_irq_lantiq,
@@ -916,8 +939,11 @@ static const struct of_device_id ltq_asc_match[] = {
{ .compatible = "intel,lgm-asc", .data = _data_intel },
{},
 };
+MODULE_DEVICE_TABLE(of, ltq_asc_match);
 
 static struct platform_driver lqasc_driver = {
+   .probe  = lqasc_probe,
+   .remove = lqasc_remove,
.driver = {
.name   = DRVNAME,
.of_match_table = ltq_asc_match,
@@ -933,10 +959,21 @@ init_lqasc(void)
if (ret != 0)
return ret;
 
-   ret = platform_driver_probe(_driver, lqasc_probe);
+   ret = platform_driver_register(_driver);
if (ret != 0)
uart_unregister_driver(_reg);
 
return ret;
 }
-device_initcall(init_lqasc);
+
+static void __exit exit_lqasc(void)
+{
+   platform_driver_unregister(_driver);
+   uart_unregister_driver(_reg);
+}
+
+module_init(init_lqasc);
+module_exit(exit_lqasc);
+
+MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs");
+MODULE_LICENSE("GPL v2");
-- 
2.11.0

[PATCH] serial: lantiq: Add x86 in Kconfig dependencies for Lantiq serial driver

2020-05-04 Thread Rahul Tanwar

Lantiq serial driver/IP is reused for a x86 based SoC as well.
Update the Kconfig accordingly.

Signed-off-by: Rahul Tanwar 
---
 drivers/tty/serial/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 0aea76cd67ff..4b0a7b98f8c7 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1035,7 +1035,7 @@ config SERIAL_SIFIVE_CONSOLE
 
 config SERIAL_LANTIQ
bool "Lantiq serial driver"
-   depends on LANTIQ
+   depends on (LANTIQ || X86) || COMPILE_TEST
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
-- 
2.11.0

[PATCH v3 1/1] x86/init: Noop get/set wallclock when platform doesn't support RTC

2019-10-10 Thread Rahul Tanwar

Use wallclock_init() op to detect platforms which does not support RTC and
noop get/set wallclock ops for such platforms.

Suggested-by: Andy Shevchenko 
Signed-off-by: Rahul Tanwar 
---
 arch/x86/kernel/x86_init.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 18a799c8fa28..4f572fd942eb 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -31,6 +31,30 @@ static int __init iommu_init_noop(void) { return 0; }
 static void iommu_shutdown_noop(void) { }
 bool __init bool_x86_init_noop(void) { return false; }
 void x86_op_int_noop(int cpu) { }
+static int set_rtc_noop(const struct timespec64 *now) { return -EINVAL; }
+static void get_rtc_noop(struct timespec64 *now) { }
+
+static const struct of_device_id of_cmos_match[] = {
+   { .compatible = "motorola,mc146818" },
+   {}
+};
+
+static void x86_wallclock_init(void)
+{
+   struct device_node *node;
+
+   node = of_find_matching_node(NULL, of_cmos_match);
+   if (node && !of_device_is_available(node)) {
+   /*
+* Some products do not support RTC as persistent clock source. 
This can be
+* optionally indicated by having status property as disabled 
in the
+* corresponding DT node. Override get/set wallclock routines 
to noops for
+* such products.
+*/
+   x86_platform.get_wallclock = get_rtc_noop;
+   x86_platform.set_wallclock = set_rtc_noop;
+   }
+}
 
 /*
  * The platform setup functions are preset with the default functions
@@ -73,7 +97,7 @@ struct x86_init_ops x86_init __initdata = {
.timers = {
.setup_percpu_clockev   = setup_boot_APIC_clock,
.timer_init = hpet_time_init,
-   .wallclock_init = x86_init_noop,
+   .wallclock_init = x86_wallclock_init,
},
 
.iommu = {
-- 
2.11.0

[PATCH v3 0/1] x86/init: Add option to skip using RTC

2019-10-10 Thread Rahul Tanwar

Hi,

We have a new Atom Airmont core based product which does not support
RTC as persistent clock source.

Presently, platform ops get/set wallclock always use MC146818 RTC/CMOS
device to read & set time. This causes boot failure on our SOC with no
RTC. More specifically, it hangs in RTC driver's mach_get_cmos_time() 
when it polls RTC_FRQ_SELECT register and loops until Update-In-Progress
(UIP) flag gets cleared i.e. below code snippet.

while ((CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
cpu_relax();

After few rounds of review cycles/feedback, we concluded that we should
control it from Motorola MC146818 compatible RTC devicetree node.
Please see [1].

Make RTC read/write optional by detecting platforms which does not
support RTC/CMOS device through the corresponding DT node status
property. If status says disabled, then noop the get/set wallclock
ops.

For non DT enabled platforms or for DT enabled platforms which does
not define optional status property, proceed same as before.

Patch is baselined upon Linux 5.4-rc2 at below Git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core

[1] Documentation/devicetree/bindings/rtc/rtc-cmos.txt

v3:
* Rebase to latest 5.4-rc2 kernel.
* Fix a build warning reported by kbuild test robot.

v2:
* As per review feedback, do not hack RTC read/write functions directly. 
  Instead, override get/set wallclock ops during setup_arch init sequence.

v1:
* Detect platforms with no RTC in RTC read/write functions and skip RTC
  read/write if not applicable.


Rahul Tanwar (1):
  x86/init: Noop get/set wallclock when platform doesn't support RTC

 arch/x86/kernel/x86_init.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

-- 
2.11.0

[PATCH v1 2/2] dt-bindings: pinctrl: intel: Add for new SoC

2019-09-12 Thread Rahul Tanwar

Add dt bindings document & include file for pinmux & GPIO controller driver of
Intel Lightning Mountain SoC.

Signed-off-by: Rahul Tanwar 
---
 .../bindings/pinctrl/intel,lgm-pinctrl.yaml| 131 +
 include/dt-bindings/pinctrl/intel,equilibrium.h|  23 
 2 files changed, 154 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml
 create mode 100644 include/dt-bindings/pinctrl/intel,equilibrium.h

diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml 
b/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml
new file mode 100644
index ..1aee42f0057e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
+
+maintainers:
+  - Rahul Tanwar 
+
+description: |
+  Pinmux & GPIO controller controls pin multiplexing & configuration including
+  GPIO function selection & GPIO attributes configuration.
+
+  Please refer to [1] for details of the common pinctrl bindings used by the
+  client devices.
+
+  [1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+properties:
+  compatible:
+const: intel,lgm-pinctrl
+
+  reg:
+maxItems: 1
+
+# Client device subnode's properties
+patternProperties:
+  "^.*@[0-9a-fA-F]+$":
+type: object
+description:
+  Pinctrl node's client devices use subnodes for desired pin configuration.
+  Client device subnodes use below defined properties.
+
+properties:
+  intel,function:
+$ref: /schemas/types.yaml#/definitions/string
+description:
+  A string containing the name of the function to mux to the group.
+
+  intel,groups:
+$ref: /schemas/types.yaml#/definitions/string-array
+description:
+  An array of strings identifying the list of groups.
+
+  intel,pins:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+description:
+  List of pins to select with this function.
+
+  intel,mux:
+description: The applicable mux group.
+allOf:
+  - $ref: "/schemas/types.yaml#/definitions/uint32"
+  - enum:
+  # Refer include/dt-bindings/pinctrl/intel,equilibrium.h
+  - PINMUX_0 # 0 PINMUX_GPIO
+  - PINMUX_1 # 1
+  - PINMUX_2 # 2
+  - PINMUX_3 # 3
+  - PINMUX_4 # 4
+
+  intel,pullup:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Specifies pull-up configuration.
+
+  intel,pulldown:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Specifies pull-down configuration.
+
+  intel,drive-current:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Enables driver-current.
+
+  intel,slew-rate:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Enables slew-rate.
+
+  intel,open-drain:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Specifies open-drain configuration.
+
+  intel,output:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Specifies if the pin is to be configured as output.
+
+
+required:
+  - intel,function
+  - intel,groups
+
+required:
+  - compatible
+  - reg
+
+examples:
+  # Pinmux controller node
+  - |
+pinctrl: pinctrl@e288 {
+  compatible = "intel,lgm-pinctrl";
+  reg = <0xe288 0x10>;
+};
+
+  # Client device node
+  - |
+asc0: serial@e0a0 {
+  compatible = "intel,lgm-asc";
+  reg = <0xe0a0 0x1000>;
+  interrupt-parent = <>;
+  interrupts = <128 1>;
+  interrupt-names = "asc_irq";
+  clocks = < 31>, < 98>;
+  clock-names = "freq", "asc";
+  pinctrl-names = "default";
+  pinctrl-0 = <>;
+};
+
+   # Client device subnode
+  - |
+uart0:uart0 {
+  intel,pins = <64>, /* UART_RX0 */
+   <65>; /* UART_TX0 */
+  intel,function = "CONSOLE_UART0";
+  intel,mux = <1>,
+  <1>;
+  intel,groups = "CONSOLE_UART0";
+};
+
+
+...
diff --git a/include/dt-bindings/pinctrl/intel,equilibrium.h 
b/include/dt-bindings/pinctrl/intel,equilibrium.h
new file mode 100644
index ..c37bfbea8ff1
--- /dev/null
+++ b/include/dt-bindings/pinctrl/intel,equilibrium.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __DT_BINDINGS_PINCTRL_INTEL_EQUILIBR

[PATCH v1 1/2] pinctrl: Add pinmux & GPIO controller driver for new SoC

2019-09-12 Thread Rahul Tanwar

Intel Lightning Mountain SoC has a pinmux controller & GPIO controller IP
which controls pin multiplexing & configuration including GPIO functions
selection & GPIO attributes configuration. Add GPIO & pin control framework
based driver for this IP.

Signed-off-by: Rahul Tanwar 
---
 drivers/pinctrl/Kconfig   |   13 +
 drivers/pinctrl/Makefile  |1 +
 drivers/pinctrl/pinctrl-equilibrium.c | 1377 +
 drivers/pinctrl/pinctrl-equilibrium.h |  194 +
 4 files changed, 1585 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-equilibrium.c
 create mode 100644 drivers/pinctrl/pinctrl-equilibrium.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b372419d61f2..99f20099b8eb 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -420,4 +420,17 @@ config PINCTRL_TB10X
depends on OF && ARC_PLAT_TB10X
select GPIOLIB
 
+config PINCTRL_EQUILIBRIUM
+   tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain 
SoC"
+   select PINMUX
+   select PINCONF
+   select GPIOLIB
+   select GPIOLIB_IRQCHIP
+   help
+ Equilibrium pinctrl driver is a pinctrl & GPIO driver for Intel 
Lightning
+ Mountain network processor SoC that supports both the linux GPIO and 
pin
+ control frameworks. It provides interfaces to setup pinmux, assign 
desired
+ pin functions, configure GPIO attributes for LGM SoC pins. Pinmux and
+ pinconf settings are retrieved from device tree.
+
 endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index ac537fdbc998..879f312bfb75 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ)+= pinctrl-zynq.o
 obj-$(CONFIG_PINCTRL_INGENIC)  += pinctrl-ingenic.o
 obj-$(CONFIG_PINCTRL_RK805)+= pinctrl-rk805.o
 obj-$(CONFIG_PINCTRL_OCELOT)   += pinctrl-ocelot.o
+obj-$(CONFIG_PINCTRL_EQUILIBRIUM)   += pinctrl-equilibrium.o
 
 obj-y  += actions/
 obj-$(CONFIG_ARCH_ASPEED)  += aspeed/
diff --git a/drivers/pinctrl/pinctrl-equilibrium.c 
b/drivers/pinctrl/pinctrl-equilibrium.c
new file mode 100644
index ..abe522cdffbe
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-equilibrium.c
@@ -0,0 +1,1377 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2019 Intel Corporation */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include "pinctrl-equilibrium.h"
+
+#define PIN_NAME_FMT   "io-%d"
+#define PIN_NAME_LEN   10
+#define PAD_REG_OFF0x100
+
+static const struct pin_config pin_cfg_type[] = {
+   {"intel,pullup",PINCONF_TYPE_PULL_UP},
+   {"intel,pulldown",  PINCONF_TYPE_PULL_DOWN},
+   {"intel,drive-current", PINCONF_TYPE_DRIVE_CURRENT},
+   {"intel,slew-rate", PINCONF_TYPE_SLEW_RATE},
+   {"intel,open-drain",PINCONF_TYPE_OPEN_DRAIN},
+   {"intel,output",PINCONF_TYPE_OUTPUT},
+};
+
+static inline void eqbr_set_val(void __iomem *addr, u32 offset,
+   u32 mask, u32 set, raw_spinlock_t *lock)
+{
+   u32 val;
+   unsigned long flags;
+
+   raw_spin_lock_irqsave(lock, flags);
+   val = readl(addr) & ~(mask << offset);
+   writel(val | ((set & mask) << offset), addr);
+   raw_spin_unlock_irqrestore(lock, flags);
+}
+
+static int eqbr_irq_map(struct irq_domain *d,
+   unsigned int virq, irq_hw_number_t hw)
+{
+   struct intel_gpio_desc *desc = d->host_data;
+
+   irq_set_chip_data(virq, desc);
+   irq_set_chip_and_handler(virq, desc->ic, handle_level_irq);
+   return 0;
+}
+
+static const struct irq_domain_ops gc_irqdomain_ops = {
+   .map= eqbr_irq_map,
+   .xlate  = irq_domain_xlate_twocell,
+};
+
+/* get direction 0 is out, 1 is in */
+static int intel_eqbr_gpio_get_dir(struct gpio_chip *gc, unsigned int offset)
+{
+   struct intel_gpio_desc *desc = gpiochip_get_data(gc);
+
+   return !(readl(desc->membase + GPIO_DIR) & BIT(offset));
+}
+
+static int intel_eqbr_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
+{
+   struct intel_gpio_desc *desc = gpiochip_get_data(gc);
+
+   writel(BIT(offset), desc->membase + GPIO_DIRCLR);
+   return 0;
+}
+
+static int intel_eqbr_gpio_dir_output(struct gpio_chip *gc, unsigned int 
offset,
+ int value)
+{
+   struct intel_gpio_desc *desc = gpiochip_get_data(gc);
+
+   if (value)
+   writel(BIT(offset), desc->membase + GPIO_OUTSET);
+   else
+   writel(BIT(offset), desc->membase + GPIO_OUTCLR);
+
+   writel(BIT(offset), desc->

[PATCH v1 0/2] pinctrl: Add new pinctrl/GPIO driver

2019-09-12 Thread Rahul Tanwar

Hi,

This series is to add pinctrl & GPIO controller driver for a new SoC.
Patch 1 adds pinmux & GPIO controller driver.
Patch 2 adds the dt bindings document & include file.

Patches are against Linux 5.3-rc5 at below Git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git


Rahul Tanwar (2):
  pinctrl: Add pinmux & GPIO controller driver for new SoC
  dt-bindings: pinctrl: intel: Add for new SoC

 .../bindings/pinctrl/intel,lgm-pinctrl.yaml|  131 ++
 drivers/pinctrl/Kconfig|   13 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/pinctrl-equilibrium.c  | 1377 
 drivers/pinctrl/pinctrl-equilibrium.h  |  194 +++
 include/dt-bindings/pinctrl/intel,equilibrium.h|   23 +
 6 files changed, 1739 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml
 create mode 100644 drivers/pinctrl/pinctrl-equilibrium.c
 create mode 100644 drivers/pinctrl/pinctrl-equilibrium.h
 create mode 100644 include/dt-bindings/pinctrl/intel,equilibrium.h

-- 
2.11.0

[tip: x86/cpu] x86/cpu: Add new Airmont variant to Intel family

2019-09-05 Thread tip-bot2 for Rahul Tanwar

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID: 855fa1f362cab2dc7574acb853b0963dd01d6b8d
Gitweb:
https://git.kernel.org/tip/855fa1f362cab2dc7574acb853b0963dd01d6b8d
Author:Rahul Tanwar 
AuthorDate:Thu, 05 Sep 2019 12:30:19 -07:00
Committer: Ingo Molnar 
CommitterDate: Fri, 06 Sep 2019 07:30:39 +02:00

x86/cpu: Add new Airmont variant to Intel family

Add new Airmont variant CPU model to Intel family.

Signed-off-by: Rahul Tanwar 
Signed-off-by: Tony Luck 
Cc: Gayatri Kammela 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: https://lkml.kernel.org/r/20190905193020.14707-4-tony.l...@intel.com
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/intel-family.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/intel-family.h 
b/arch/x86/include/asm/intel-family.h
index 55568af..f046225 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -98,6 +98,7 @@
 
 #define INTEL_FAM6_ATOM_AIRMONT0x4C /* Cherry Trail, Braswell 
*/
 #define INTEL_FAM6_ATOM_AIRMONT_MID0x5A /* Moorefield */
+#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
 
 #define INTEL_FAM6_ATOM_GOLDMONT   0x5C /* Apollo Lake */
 #define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */

[tip: x86/cpu] x86/cpu: Update init data for new Airmont CPU model

2019-09-05 Thread tip-bot2 for Rahul Tanwar

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID: 0cc5359d8fd45bc410906e009117e78e2b5b2322
Gitweb:
https://git.kernel.org/tip/0cc5359d8fd45bc410906e009117e78e2b5b2322
Author:Rahul Tanwar 
AuthorDate:Thu, 05 Sep 2019 12:30:20 -07:00
Committer: Ingo Molnar 
CommitterDate: Fri, 06 Sep 2019 07:30:40 +02:00

x86/cpu: Update init data for new Airmont CPU model

Update properties for newly added Airmont CPU variant.

Signed-off-by: Rahul Tanwar 
Signed-off-by: Tony Luck 
Cc: Gayatri Kammela 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: https://lkml.kernel.org/r/20190905193020.14707-5-tony.l...@intel.com
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/common.c | 1 +
 arch/x86/kernel/cpu/intel.c  | 1 +
 arch/x86/kernel/tsc_msr.c| 5 +
 3 files changed, 7 insertions(+)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index b6a9e27..030e527 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1059,6 +1059,7 @@ static const __initconst struct x86_cpu_id 
cpu_vuln_whitelist[] = {
VULNWL_INTEL(CORE_YONAH,NO_SSB),
 
VULNWL_INTEL(ATOM_AIRMONT_MID,  NO_L1TF | MSBDS_ONLY | 
NO_SWAPGS),
+   VULNWL_INTEL(ATOM_AIRMONT_NP,   NO_L1TF | NO_SWAPGS),
 
VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS),
VULNWL_INTEL(ATOM_GOLDMONT_D,   NO_MDS | NO_L1TF | NO_SWAPGS),
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index e2082cc..c2fdc00 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -268,6 +268,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
case INTEL_FAM6_ATOM_SALTWELL_MID:
case INTEL_FAM6_ATOM_SALTWELL_TABLET:
case INTEL_FAM6_ATOM_SILVERMONT_MID:
+   case INTEL_FAM6_ATOM_AIRMONT_NP:
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
break;
default:
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 067858f..e0cbe4f 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -58,6 +58,10 @@ static const struct freq_desc freq_desc_ann = {
1, { 83300, 10, 133300, 10, 0, 0, 0, 0 }
 };
 
+static const struct freq_desc freq_desc_lgm = {
+   1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }
+};
+
 static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
INTEL_CPU_FAM6(ATOM_SALTWELL_MID,   freq_desc_pnw),
INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET,freq_desc_clv),
@@ -65,6 +69,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
INTEL_CPU_FAM6(ATOM_AIRMONT,freq_desc_cht),
INTEL_CPU_FAM6(ATOM_AIRMONT_MID,freq_desc_ann),
+   INTEL_CPU_FAM6(ATOM_AIRMONT_NP, freq_desc_lgm),
{}
 };

[PATCH v3 1/1] x86/init: Noop get/set wallclock when platform doesn't support RTC

2019-09-03 Thread Rahul Tanwar

Use wallclock_init() op to detect platforms which does not support RTC and
noop get/set wallclock ops for such platforms.

Reported-by: kbuild test robot 
Fixes: 1461badd03e7 ("x86/init: Noop get/set wallclock when platform doesn't 
support RTC")
Suggested-by: Andy Shevchenko 
Signed-off-by: Rahul Tanwar 
---
 arch/x86/kernel/x86_init.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 1bef687faf22..50aa8257fd20 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -31,6 +31,30 @@ static int __init iommu_init_noop(void) { return 0; }
 static void iommu_shutdown_noop(void) { }
 bool __init bool_x86_init_noop(void) { return false; }
 void x86_op_int_noop(int cpu) { }
+static int set_rtc_noop(const struct timespec64 *now) { return -EINVAL; }
+static void get_rtc_noop(struct timespec64 *now) { }
+
+static const struct of_device_id of_cmos_match[] = {
+   { .compatible = "motorola,mc146818" },
+   {}
+};
+
+static void x86_wallclock_init(void)
+{
+   struct device_node *node;
+
+   node = of_find_matching_node(NULL, of_cmos_match);
+   if (node && !of_device_is_available(node)) {
+   /*
+* Some products do not support RTC as persistent clock source. 
This can be
+* optionally indicated by having status property as disabled 
in the
+* corresponding DT node. Override get/set wallclock routines 
to noops for
+* such products.
+*/
+   x86_platform.get_wallclock = get_rtc_noop;
+   x86_platform.set_wallclock = set_rtc_noop;
+   }
+}
 
 /*
  * The platform setup functions are preset with the default functions
@@ -73,7 +97,7 @@ struct x86_init_ops x86_init __initdata = {
.timers = {
.setup_percpu_clockev   = setup_boot_APIC_clock,
.timer_init = hpet_time_init,
-   .wallclock_init = x86_init_noop,
+   .wallclock_init = x86_wallclock_init,
},
 
.iommu = {
-- 
2.11.0

[PATCH v3 0/1] Add option to skip using RTC

2019-09-03 Thread Rahul Tanwar

Hi,

There is a new product which does not support RTC as persistent clock source.

Platform ops get/set wallclock are used to get/set timespec through kernel 
timekeeping read/update_persistent_clock64() routines. Presently, get/set
wallclock ops always use MC146818A RTC/CMOS device to read & set time.
This causes boot failure on our new SOC with no RTC.

Make RTC read/write optional by detecting platforms which does not support
RTC/CMOS device through the corresponding DT node status property. If status
says disabled, then noop the get/set wallclock ops.

For non DT enabled machines or for DT enabled machines which does not define
optional status property, proceed same as before.

These patches are baselined upon Linux 5.3-rc6 at below Git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core

v3:
* Fix a build warning reported by kbuild test robot.

v2:
* As per review feedback, do not hack RTC read/write functions directly. 
  Instead, override get/set wallclock ops during setup_arch init sequence.

v1:
* Detect platforms with no RTC in RTC read/write functions and skip RTC
  read/write if not applicable.


Rahul Tanwar (1):
  x86/init: Noop get/set wallclock when platform doesn't support RTC

 arch/x86/kernel/x86_init.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

-- 
2.11.0

[PATCH v1 1/2] clk: intel: Add CGU clock driver for a new SoC

2019-08-28 Thread Rahul Tanwar

From: rtanwar 

Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
Intel network processor SoC. It provides programming interfaces to control
& configure all CPU & peripheral clocks. Add common clock framework based
clock controller driver for CGU.

Signed-off-by: Rahul Tanwar 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/intel/Kconfig   |  13 +
 drivers/clk/intel/Makefile  |   4 +
 drivers/clk/intel/clk-cgu-pll.c | 160 
 drivers/clk/intel/clk-cgu-pll.h |  24 ++
 drivers/clk/intel/clk-cgu.c | 544 
 drivers/clk/intel/clk-cgu.h | 278 
 drivers/clk/intel/clk-lgm.c | 352 ++
 9 files changed, 1377 insertions(+)
 create mode 100644 drivers/clk/intel/Kconfig
 create mode 100644 drivers/clk/intel/Makefile
 create mode 100644 drivers/clk/intel/clk-cgu-pll.c
 create mode 100644 drivers/clk/intel/clk-cgu-pll.h
 create mode 100644 drivers/clk/intel/clk-cgu.c
 create mode 100644 drivers/clk/intel/clk-cgu.h
 create mode 100644 drivers/clk/intel/clk-lgm.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 801fa1cd0321..3b2e0106b305 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -336,5 +336,6 @@ source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/ti/Kconfig"
 source "drivers/clk/uniphier/Kconfig"
 source "drivers/clk/zynqmp/Kconfig"
+source "drivers/clk/intel/Kconfig"
 
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0cad76021297..f7e2ef6931b7 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -117,3 +117,4 @@ endif
 obj-$(CONFIG_ARCH_ZX)  += zte/
 obj-$(CONFIG_ARCH_ZYNQ)+= zynq/
 obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
+obj-$(CONFIG_INTEL_LGM_CGU_CLK)+= intel/
diff --git a/drivers/clk/intel/Kconfig b/drivers/clk/intel/Kconfig
new file mode 100644
index ..6608ae88a9a7
--- /dev/null
+++ b/drivers/clk/intel/Kconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0
+config INTEL_LGM_CGU_CLK
+   depends on COMMON_CLK
+   select MFD_SYSCON
+   select OF_EARLY_FLATTREE
+   bool "Intel Clock Genration Unit support"
+   help
+ Support for clock generation unit driver for Intel Lightning
+ Mountain(LGM) series SoCs. It is based on Common Clock Framework.
+ CGU driver provides all means to access the clock generation unit
+ hardware module of LGM in order to generate a series of clocks for
+ the whole system and individual peripherals. Choose Y here if you
+ are building for Lightning Mountain(LGM) platform.
diff --git a/drivers/clk/intel/Makefile b/drivers/clk/intel/Makefile
new file mode 100644
index ..82741528d2fb
--- /dev/null
+++ b/drivers/clk/intel/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+# Makefile for intel specific clk
+
+obj-$(CONFIG_INTEL_LGM_CGU_CLK) += clk-cgu.o clk-cgu-pll.o clk-lgm.o
diff --git a/drivers/clk/intel/clk-cgu-pll.c b/drivers/clk/intel/clk-cgu-pll.c
new file mode 100644
index ..e1e9036470df
--- /dev/null
+++ b/drivers/clk/intel/clk-cgu-pll.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  Copyright (C) 2018 Intel Corporation.
+ *  Zhu YiXin 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk-cgu-pll.h"
+#include "clk-cgu.h"
+
+#define to_intel_clk_pll(_hw)  container_of(_hw, struct intel_clk_pll, hw)
+
+/*
+ * Calculate formula:
+ * rate = (prate * mult + (prate * frac) / frac_div) / div
+ */
+static unsigned long
+intel_pll_calc_rate(unsigned long prate, unsigned int mult,
+   unsigned int div, unsigned int frac, unsigned int frac_div)
+{
+   u64 crate, frate, rate64;
+
+   rate64 = prate;
+   crate = rate64 * mult;
+
+   if (frac) {
+   frate = rate64 * frac;
+   do_div(frate, frac_div);
+   crate += frate;
+   }
+   do_div(crate, div);
+
+   return (unsigned long)crate;
+}
+
+static int intel_pll_wait_for_lock(struct intel_clk_pll *pll)
+{
+   unsigned int v;
+
+   return regmap_read_poll_timeout(pll->map, pll->reg, v, v & 1, 1, 100);
+}
+
+static void
+lgm_pll_get_params(struct intel_clk_pll *pll, unsigned int *mult,
+  unsigned int *div, unsigned int *frac)
+{
+   *mult = intel_get_clk_val(pll->map, pll->reg + 0x8, 0, 12);
+   *div = intel_get_clk_val(pll->map, pll->reg + 0x8, 18, 6);
+   *frac = intel_get_clk_val(pll->map, pll->reg, 2, 24);
+}
+
+static unsigned long lgm_pll_recalc_rate(struct clk_hw *hw, unsigned long 
prate)
+{
+   struct intel_clk_pll *pll = to_intel_clk_pll(hw);
+   unsigned int div, mult, frac;
+
+

[PATCH v1 2/2] dt-bindings: clk: intel: Add bindings document & header file for CGU

2019-08-28 Thread Rahul Tanwar

Clock generation unit(CGU) is a clock controller IP of Intel's Lightning
Mountain(LGM) SoC. Add DT bindings include file and document for CGU clock
controller driver of LGM.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/clock/intel,cgu-lgm.yaml   |  61 +
 include/dt-bindings/clock/intel,lgm-clk.h  | 150 +
 2 files changed, 211 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
 create mode 100644 include/dt-bindings/clock/intel,lgm-clk.h

diff --git a/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml 
b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
new file mode 100644
index ..8bc5c6f9f792
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/intel,cgu-lgm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding
+
+maintainers:
+  - Rahul Tanwar 
+
+description: |
+  Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
+  all means to access the CGU hardware module in order to generate a series
+  of clocks for the whole system and individual peripherals.
+
+  This binding uses the common clock bindings
+  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+properties:
+  compatible:
+const: intel,cgu-lgm
+
+  reg:
+maxItems: 1
+
+  '#clock-cells':
+const: 1
+
+  clock-output-names:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+examples:
+  # CGU node
+  - |
+cgu: cgu@e020 {
+compatible = "intel,cgu-lgm", "syscon";
+reg = <0xe020 0x33c>;
+#clock-cells = <1>;
+};
+
+  # Example of clock consumer (UART driver)
+  - |
+asc0: serial@e0a0 {
+compatible = "intel,lgm-asc";
+reg = <0xe0a0 0x1000>;
+interrupt-parent = <>;
+interrupts = <128 1>;
+interrupt-names = "asc_irq";
+clocks = < LGM_CLK_NOC4>, < LGM_GCLK_ASC0>;
+clock-names = "freq", "asc";
+pinctrl-names = "default";
+pinctrl-0 = <>;
+};
+
+...
diff --git a/include/dt-bindings/clock/intel,lgm-clk.h 
b/include/dt-bindings/clock/intel,lgm-clk.h
new file mode 100644
index ..09e5dc59ff5b
--- /dev/null
+++ b/include/dt-bindings/clock/intel,lgm-clk.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Intel Corporation.
+ * Lei Chuanhua 
+ * Zhu Yixin 
+ */
+
+#ifndef __INTEL_LGM_CLK_H
+#define __INTEL_LGM_CLK_H
+
+/* PLL clocks */
+#define LGM_CLK_PLLPP  2
+#define LGM_CLK_PLL2   3
+#define LGM_CLK_PLL0CZ 4
+#define LGM_CLK_PLL0B  5
+#define LGM_CLK_PLL1   6
+#define LGM_CLK_LJPLL3 7
+#define LGM_CLK_LJPLL4 8
+#define LGM_CLK_PLL0CM09
+#define LGM_CLK_PLL0CM110
+
+/* clocks from PLLs */
+
+/* ROPLL clocks */
+#define LGM_CLK_PP_HW  15
+#define LGM_CLK_PP_UC  16
+#define LGM_CLK_PP_FXD 17
+#define LGM_CLK_PP_TBM 18
+
+/* PLL2 clocks */
+#define LGM_CLK_DDR20
+
+/* PLL0CZ */
+#define LGM_CLK_CM 25
+#define LGM_CLK_IC 26
+#define LGM_CLK_SDIO3  27
+
+/* PLL0B */
+#define LGM_CLK_NGI30
+#define LGM_CLK_NOC4   31
+#define LGM_CLK_SW 32
+#define LGM_CLK_QSPI   33
+#define LGM_CLK_CQEM   LGM_CLK_SW
+#define LGM_CLK_EMMC5  LGM_CLK_NOC4
+
+/* PLL1 */
+#define LGM_CLK_CT 35
+#define LGM_CLK_DSP36
+#define LGM_CLK_4X 37
+#define LGM_CLK_DCL38
+
+/* LJPLL3 */
+#define LGM_CLK_CML40
+#define LGM_CLK_CBPHY  41
+#define LGM_CLK_POOL   42
+#define LGM_CLK_PTP43
+
+/* LJPLL4 */
+#define LGM_CLK_PCIE   45
+#define LGM_CLK_SATA   LGM_CLK_PCIE
+
+/* Miscellaneous clocks */
+#define LGM_CLK_EMMC4  46
+#define LGM_CLK_SDIO2  47
+#define LGM_CLK_EMMC   48
+#define LGM_CLK_SDIO   49
+
+
+/* Gate clocks */
+/* Gate CLK0 */
+#define LGM_GCLK_C55   60
+#define LGM_GCLK_VCODEC61
+#define LGM_GCLK_QSPI  62
+#define LGM_GCLK_TEP   63
+#define LGM_GCLK_EIP19764
+#define LGM_GCLK_VAULT 65
+#define LGM_GCLK_TOE   66
+#define LGM_GCLK_SDXC  67
+#define LGM_GCLK_EMMC  68
+#define LGM_GCLK_EIP15469
+#define LGM_GCLK_SPI_DBG   70
+#define LGM_GCLK_DMA3  71
+#define LGM_GCLK_TOPNOC72
+
+/* Gate CLK1 */
+#define LGM_GCLK_DMA0  80
+#define LGM_GCLK_LEDC0 81
+#define LGM_GCLK_LEDC1 82
+#define LGM_GCLK_I2S0  83
+#define LGM_GCLK_I2S

[PATCH v1 0/2] clk: intel: Add a new driver for a new clock controller IP

2019-08-28 Thread Rahul Tanwar

Hi,

A forthcoming Intel network processor SoC uses a new Clock Generation Unit(CGU)
IP for clock controller. This series adds the clock driver for CGU.

Patch 1 adds common clock framework based clock driver for CGU.
Patch 2 adds bindings document & include file for CGU.

These patches are baselined upon Linux 5.3-rc1 at below Git link:
git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git


Rahul Tanwar (1):
  dt-bindings: clk: intel: Add bindings document & header file for CGU

rtanwar (1):
  clk: intel: Add CGU clock driver for a new SoC

 .../devicetree/bindings/clock/intel,cgu-lgm.yaml   |  61 +++
 drivers/clk/Kconfig|   1 +
 drivers/clk/Makefile   |   1 +
 drivers/clk/intel/Kconfig  |  13 +
 drivers/clk/intel/Makefile |   4 +
 drivers/clk/intel/clk-cgu-pll.c| 160 ++
 drivers/clk/intel/clk-cgu-pll.h|  24 +
 drivers/clk/intel/clk-cgu.c| 544 +
 drivers/clk/intel/clk-cgu.h| 278 +++
 drivers/clk/intel/clk-lgm.c| 352 +
 include/dt-bindings/clock/intel,lgm-clk.h  | 150 ++
 11 files changed, 1588 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
 create mode 100644 drivers/clk/intel/Kconfig
 create mode 100644 drivers/clk/intel/Makefile
 create mode 100644 drivers/clk/intel/clk-cgu-pll.c
 create mode 100644 drivers/clk/intel/clk-cgu-pll.h
 create mode 100644 drivers/clk/intel/clk-cgu.c
 create mode 100644 drivers/clk/intel/clk-cgu.h
 create mode 100644 drivers/clk/intel/clk-lgm.c
 create mode 100644 include/dt-bindings/clock/intel,lgm-clk.h

-- 
2.11.0

[PATCH v2 0/1] Add option to skip using RTC

2019-08-27 Thread Rahul Tanwar

Hi,

There is a new product which does not support RTC as persistent clock source.

Platform ops get/set wallclock are used to get/set timespec through kernel 
timekeeping read/update_persistent_clock64() routines. Presently, get/set
wallclock ops always use MC146818A RTC/CMOS device to read & set time.
This causes boot failure on our new SOC with no RTC.

Make RTC read/write optional by detecting platforms which does not support
RTC/CMOS device through the corresponding DT node status property. If status
says disabled, then noop the get/set wallclock ops.

For non DT enabled machines or for DT enabled machines which does not define
optional status property, proceed same as before.

These patches are baselined upon Linux 5.3-rc6 at below Git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core

v2:
* As per review feedback, do not hack RTC read/write functions directly. 
  Instead, override get/set wallclock ops during setup_arch init sequence.

v1:
* Detect platforms with no RTC in RTC read/write functions and skip RTC
  read/write if not applicable.

Rahul Tanwar (1):
  x86/init: Noop get/set wallclock when platform doesn't support RTC

 arch/x86/kernel/x86_init.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

-- 
2.11.0

[PATCH v2 1/1] x86/init: Noop get/set wallclock when platform doesn't support RTC

2019-08-27 Thread Rahul Tanwar

Use wallclock_init() op to detect platforms which does not support RTC and
noop get/set wallclock ops for such platforms.

Suggested-by: Andy Shevchenko 
Signed-off-by: Rahul Tanwar 
---
 arch/x86/kernel/x86_init.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 1bef687faf22..88c120710d5d 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -31,6 +31,30 @@ static int __init iommu_init_noop(void) { return 0; }
 static void iommu_shutdown_noop(void) { }
 bool __init bool_x86_init_noop(void) { return false; }
 void x86_op_int_noop(int cpu) { }
+static int set_rtc_noop(const struct timespec64 *now) { return -EINVAL; }
+static void get_rtc_noop(struct timespec64 *now) { }
+
+static const struct of_device_id of_cmos_match[] = {
+   { .compatible = "motorola,mc146818" },
+   {}
+};
+
+void x86_wallclock_init(void)
+{
+   struct device_node *node;
+
+   node = of_find_matching_node(NULL, of_cmos_match);
+   if (node && !of_device_is_available(node)) {
+   /*
+* Some products do not support RTC as persistent clock source. 
This can be
+* optionally indicated by having status property as disabled 
in the
+* corresponding DT node. Override get/set wallclock routines 
to noops for
+* such products.
+*/
+   x86_platform.get_wallclock = get_rtc_noop;
+   x86_platform.set_wallclock = set_rtc_noop;
+   }
+}
 
 /*
  * The platform setup functions are preset with the default functions
@@ -73,7 +97,7 @@ struct x86_init_ops x86_init __initdata = {
.timers = {
.setup_percpu_clockev   = setup_boot_APIC_clock,
.timer_init = hpet_time_init,
-   .wallclock_init = x86_init_noop,
+   .wallclock_init = x86_wallclock_init,
},
 
.iommu = {
-- 
2.11.0

[PATCH v1 2/2] dt-bindings: rtc: Add optional status property

2019-08-22 Thread Rahul Tanwar

Some products may not support MC146818 RTC CMOS device. Introduce a optional
'status' standard property for RTC-CMOS to indicate if the MC146818 RTC device
is available (status="okay") or not (status="disabled")

Signed-off-by: Rahul Tanwar 
---
 Documentation/devicetree/bindings/rtc/rtc-cmos.txt | 4 
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/rtc/rtc-cmos.txt 
b/Documentation/devicetree/bindings/rtc/rtc-cmos.txt
index b94b35f3600b..fea4fe0ed4b9 100644
--- a/Documentation/devicetree/bindings/rtc/rtc-cmos.txt
+++ b/Documentation/devicetree/bindings/rtc/rtc-cmos.txt
@@ -11,6 +11,9 @@ Optional properties:
 called "Register B".
   - freq-reg : Contains the initial value of the frequency register also
 called "Regsiter A".
+  - status: indicates the operational status of the device.
+Value must be either "disabled" or "okay".
+
 
 "Register A" and "B" are usually initialized by the firmware (BIOS for
 instance). If this is not done, it can be performed by the driver.
@@ -24,4 +27,5 @@ ISA Example:
 ctrl-reg = <2>;
 freq-reg = <0x26>;
 reg = <1 0x70 2>;
+status = "okay";
 };
-- 
2.11.0

[PATCH v1 0/2] x86/rtc: Add option to skip using RTC

2019-08-22 Thread Rahul Tanwar

Platform init ops get_wallclock()/set_wallclock() are by default setup such
that they use MC146818A RTC/CMOS device to set & read time. However, some
products might not support RTC. One such example is Intel Atom based Lightning
Mountain network processor SOC. 

Patch 1: Use status standard property of motorola,mc146818 compatible DT node
to determine if RTC is supported. Skip read/write from RTC device only when
this node is present and status is disabled.

For non DT machines, do not change anything, proceed same as before.

For DT machines, if this node is not present, proceed same as before.

For DT machines, if this node is present but newly introduced status property
is not defined in DTS, proceed same as before.

For DT machines, if this node is present and status property indicates
"disabled", then skip read/write from RTC/CMOS device. If status property
indicates "okay", proceed same as before.

Patch 2: Update dt bindings document to add status property.

These patches are baselined upon Linux 5.3-rc5 at below Git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core


Rahul Tanwar (2):
  x86/rtc: Add option to skip using RTC
  dt-bindings: rtc: Add optional status property

 Documentation/devicetree/bindings/rtc/rtc-cmos.txt |  4 
 arch/x86/kernel/rtc.c  | 17 +
 2 files changed, 21 insertions(+)

-- 
2.11.0

[PATCH v1 1/2] x86/rtc: Add option to skip using RTC

2019-08-22 Thread Rahul Tanwar

Use a newly introduced optional "status" property of "motorola,mc146818"
compatible DT node to determine if RTC is supported. Skip read/write from
RTC device only when this node is present and status is "disabled". In all
other cases, proceed as before.

Suggested-by: Alan Cox 
Signed-off-by: Rahul Tanwar 
---
 arch/x86/kernel/rtc.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c
index 586f718b8e95..f9f760a8e76a 100644
--- a/arch/x86/kernel/rtc.c
+++ b/arch/x86/kernel/rtc.c
@@ -32,6 +32,11 @@ EXPORT_SYMBOL(cmos_lock);
 DEFINE_SPINLOCK(rtc_lock);
 EXPORT_SYMBOL(rtc_lock);
 
+static const struct of_device_id of_cmos_match[] = {
+{ .compatible = "motorola,mc146818" },
+{}
+};
+
 /*
  * In order to set the CMOS clock precisely, set_rtc_mmss has to be
  * called 500 ms after the second nowtime has started, because when
@@ -42,9 +47,14 @@ EXPORT_SYMBOL(rtc_lock);
 int mach_set_rtc_mmss(const struct timespec64 *now)
 {
unsigned long long nowtime = now->tv_sec;
+   struct device_node *node;
struct rtc_time tm;
int retval = 0;
 
+   node = of_find_matching_node(NULL, of_cmos_match);
+   if (node && !of_device_is_available(node))
+   return -EINVAL;
+
rtc_time64_to_tm(nowtime, );
if (!rtc_valid_tm()) {
retval = mc146818_set_time();
@@ -63,8 +73,15 @@ int mach_set_rtc_mmss(const struct timespec64 *now)
 void mach_get_cmos_time(struct timespec64 *now)
 {
unsigned int status, year, mon, day, hour, min, sec, century = 0;
+   struct device_node *node;
unsigned long flags;
 
+   node = of_find_matching_node(NULL, of_cmos_match);
+   if (node && !of_device_is_available(node)) {
+   now->tv_sec = now->tv_nsec = 0;
+   return;
+   }
+
/*
 * If pm_trace abused the RTC as storage, set the timespec to 0,
 * which tells the caller that this RTC value is unusable.
-- 
2.11.0

[PATCH] x86/apic: Update virtual irq base for DT/OF based system as well

2019-08-21 Thread Rahul Tanwar

'ioapic_dynirq_base' contains the virtual IRQ base number. Presently, it is
updated to the end of hardware IRQ numbers but this is done only when IOAPIC
configuration type is IOAPIC_DOMAIN_LEGACY or IOAPIC_DOMAIN_STRICT. There is
a third type IOAPIC_DOMAIN_DYNAMIC which applies when IOAPIC configuration
comes from devicetree.
Please see dtb_add_ioapic() in arch/x86/kernel/devicetree.c

In case of IOAPIC_DOMAIN_DYNAMIC (DT/OF based system), 'ioapic_dynirq_base'
remains to zero initialized value. This means that for OF based systems,
virtual IRQ base will get set to zero. Zero value for a virtual IRQ is a
invalid value.
Please see https://yarchive.net/comp/linux/zero.html for more details.

Update 'ioapic_dynirq_base' for IOAPIC_DOMAIN_DYNAMIC case as well just like
it is presently updated for IOAPIC_DOMAIN_LEGACY & IOAPIC_DOMAIN_STRICT i.e.
set the virtual IRQ base to the end of hardware IRQ numbers when IOAPIC
configuration comes from devicetree.

Signed-off-by: Rahul Tanwar 
---
 arch/x86/kernel/apic/io_apic.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index c7bb6c69f21c..fe50cd91122b 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -2336,7 +2336,8 @@ static int mp_irqdomain_create(int ioapic)
ip->irqdomain->parent = parent;
 
if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
-   cfg->type == IOAPIC_DOMAIN_STRICT)
+   cfg->type == IOAPIC_DOMAIN_STRICT ||
+   cfg->type == IOAPIC_DOMAIN_DYNAMIC)
ioapic_dynirq_base = max(ioapic_dynirq_base,
 gsi_cfg->gsi_end + 1);
 
-- 
2.11.0

[PATCH v3 1/2] dt-bindings: serial: lantiq: Convert to YAML schema

2019-08-21 Thread Rahul Tanwar

Convert the existing DT binding document for Lantiq SoC ASC serial controller
from txt format to YAML format.

Signed-off-by: Rahul Tanwar 
---
 .../devicetree/bindings/serial/lantiq,asc.yaml | 55 ++
 .../devicetree/bindings/serial/lantiq_asc.txt  | 31 
 2 files changed, 55 insertions(+), 31 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/serial/lantiq,asc.yaml
 delete mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.txt

diff --git a/Documentation/devicetree/bindings/serial/lantiq,asc.yaml 
b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml
new file mode 100644
index ..72ea2a3d75c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/lantiq,asc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq SoC ASC serial controller
+
+maintainers:
+  - Rahul Tanwar 
+
+allOf:
+  - $ref: /schemas/serial.yaml#
+
+properties:
+  compatible:
+enum:
+  - lantiq,asc
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 3
+
+  clocks:
+items:
+  - description: phandle to the frequency clock
+  - description: phandle to the gate clock
+
+  clock-names:
+items:
+  - const: freq
+  - const: asc
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+
+examples:
+  - |
+asc0: serial@1660 {
+compatible = "lantiq,asc";
+reg = <0x1660 0x10>;
+interrupt-parent = <>;
+interrupts = ,
+ ,
+ ;
+clocks = < CLK_SSX4>, < GCLK_UART>;
+clock-names = "freq", "asc";
+};
+
+...
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt 
b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
deleted file mode 100644
index 40e81a5818f6..
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Lantiq SoC ASC serial controller
-
-Required properties:
-- compatible : Should be "lantiq,asc"
-- reg : Address and length of the register set for the device
-- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
-  depends on the interrupt-parent interrupt controller.
-
-Optional properties:
-- clocks: Should contain frequency clock and gate clock
-- clock-names: Should be "freq" and "asc"
-
-Example:
-
-asc0: serial@1660 {
-   compatible = "lantiq,asc";
-   reg = <0x1660 0x10>;
-   interrupt-parent = <>;
-   interrupts = ,
-   ,
-   ;
-   clocks = < CLK_SSX4>, < GCLK_UART>;
-   clock-names = "freq", "asc";
-};
-
-asc1: serial@e100c00 {
-   compatible = "lantiq,asc";
-   reg = <0xE100C00 0x400>;
-   interrupt-parent = <>;
-   interrupts = <112 113 114>;
-};
-- 
2.11.0

[PATCH v3 0/2] dt-bindings: serial: lantiq: Convert to YAML & add support for new SoC

2019-08-21 Thread Rahul Tanwar

There is a new product which reuses Lantiq serial controller IP. Patch 1 in this
series converts existing lantiq dt bindings to YAML schema and Patch 2 updates
it to support newer product.

These patches are baselined upon Linux 5.3-rc4 at below Git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git

v3:
* Use compatible name for filename.
* Use if/then schema to describe a property which is different for each
  compatibles.
* Address other review concerns about YAML format.

v2:
* Update license to GPL-2.0-only.
* Fix trailing whitespace error.


Rahul Tanwar (2):
  dt-bindings: serial: lantiq: Convert to YAML schema
  dt-bindings: lantiq: Update for new SoC

 .../devicetree/bindings/serial/lantiq,asc.yaml | 90 ++
 .../devicetree/bindings/serial/lantiq_asc.txt  | 31 
 2 files changed, 90 insertions(+), 31 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/serial/lantiq,asc.yaml
 delete mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.txt

-- 
2.11.0

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