[PATCH v4 2/2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig | 10 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-dp.c | 541 +++ 5 files changed, 554 insertions(+) create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-dp.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 5c8d452..cc47f85 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -43,6 +43,7 @@ config PHY_XGENE source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" +source "drivers/phy/cadence/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/lantiq/Kconfig" source "drivers/phy/marvell/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 84e3bd9..ba48acd 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/ obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += broadcom/\ + cadence/ \ hisilicon/ \ marvell/ \ motorola/\ diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig new file mode 100644 index 000..57fff7d --- /dev/null +++ b/drivers/phy/cadence/Kconfig @@ -0,0 +1,10 @@ +# +# Phy driver for Cadence MHDP DisplayPort controller +# +config PHY_CADENCE_DP + tristate "Cadence MHDP DisplayPort PHY driver" + depends on OF + depends on HAS_IOMEM + select GENERIC_PHY + help + Support for Cadence MHDP DisplayPort PHY. diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile new file mode 100644 index 000..e5b0a11 --- /dev/null +++ b/drivers/phy/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o diff --git a/drivers/phy/cadence/phy-cadence-dp.c b/drivers/phy/cadence/phy-cadence-dp.c new file mode 100644 index 000..bc10cb2 --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-dp.c @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence MHDP DisplayPort SD0801 PHY driver. + * + * Copyright 2018 Cadence Design Systems, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEFAULT_NUM_LANES 2 +#define MAX_NUM_LANES 4 +#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ + +#define POLL_TIMEOUT_US2000 +#define LANE_MASK 0x7 + +/* + * register offsets from DPTX PHY register block base (i.e MHDP + * register base + 0x30a00) + */ +#define PHY_AUX_CONFIG 0x00 +#define PHY_AUX_CTRL 0x04 +#define PHY_RESET 0x20 +#define PHY_PMA_XCVR_PLLCLK_EN 0x24 +#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 +#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c +#define PHY_POWER_STATE_LN_0 0x +#define PHY_POWER_STATE_LN_1 0x0008 +#define PHY_POWER_STATE_LN_2 0x0010 +#define PHY_POWER_STATE_LN_3 0x0018 +#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 +#define PHY_PMA_CMN_READY 0x34 +#define PHY_PMA_XCVR_TX_VMARGIN0x38 +#define PHY_PMA_XCVR_TX_DEEMPH 0x3c + +/* + * register offsets from SD0801 PHY register block base (i.e MHDP + * register base + 0x50) + */ +#define CMN_SSM_BANDGAP_TMR0x00084 +#define CMN_SSM_BIAS_TMR 0x00088 +#define CMN_PLLSM0_PLLPRE_TMR 0x000a8 +#define CMN_PLLSM0_PLLLOCK_TMR 0x000b0 +#define CMN_PLLSM1_PLLPRE_TMR 0x000c8 +#define CMN_PLLSM1_PLLLOCK_TMR 0x000d0 +#define CMN_BGCAL_INIT_TMR 0x00190 +#define CMN_BGCAL_ITER_TMR 0x00194 +#define CMN_IBCAL_INIT_TMR 0x001d0 +#define CMN_PLL0_VCOCAL_INIT_TMR 0x00210 +#define CMN_PLL0_VCOCAL_ITER_TMR 0x00214 +#define CMN_PLL0_VCOCAL_REFTIM_START 0x00218 +#define CMN_PLL0_VCOCAL_PLLCNT_START 0x00220 +#define CMN_PLL0_INTDIV_M0 0x00240 +#define CMN_PLL0_FRACDIVL_M0 0x00244 +#define CMN_PLL0_FRACDIVH_M0 0x00248 +#define CMN_PLL0_HIGH_THR_M0 0x0024c +#define CMN_PLL0_DSM_DIAG_M0 0x00250 +#define CMN_PLL0_LOCK_PLLCNT_START 0x00278 +#define CMN_PLL1_VCOCAL_INIT_TMR 0x00310 +#define CMN_P
[PATCH v4 2/2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig | 10 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-dp.c | 541 +++ 5 files changed, 554 insertions(+) create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-dp.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 5c8d452..cc47f85 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -43,6 +43,7 @@ config PHY_XGENE source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" +source "drivers/phy/cadence/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/lantiq/Kconfig" source "drivers/phy/marvell/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 84e3bd9..ba48acd 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/ obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += broadcom/\ + cadence/ \ hisilicon/ \ marvell/ \ motorola/\ diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig new file mode 100644 index 000..57fff7d --- /dev/null +++ b/drivers/phy/cadence/Kconfig @@ -0,0 +1,10 @@ +# +# Phy driver for Cadence MHDP DisplayPort controller +# +config PHY_CADENCE_DP + tristate "Cadence MHDP DisplayPort PHY driver" + depends on OF + depends on HAS_IOMEM + select GENERIC_PHY + help + Support for Cadence MHDP DisplayPort PHY. diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile new file mode 100644 index 000..e5b0a11 --- /dev/null +++ b/drivers/phy/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o diff --git a/drivers/phy/cadence/phy-cadence-dp.c b/drivers/phy/cadence/phy-cadence-dp.c new file mode 100644 index 000..bc10cb2 --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-dp.c @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence MHDP DisplayPort SD0801 PHY driver. + * + * Copyright 2018 Cadence Design Systems, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEFAULT_NUM_LANES 2 +#define MAX_NUM_LANES 4 +#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ + +#define POLL_TIMEOUT_US2000 +#define LANE_MASK 0x7 + +/* + * register offsets from DPTX PHY register block base (i.e MHDP + * register base + 0x30a00) + */ +#define PHY_AUX_CONFIG 0x00 +#define PHY_AUX_CTRL 0x04 +#define PHY_RESET 0x20 +#define PHY_PMA_XCVR_PLLCLK_EN 0x24 +#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 +#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c +#define PHY_POWER_STATE_LN_0 0x +#define PHY_POWER_STATE_LN_1 0x0008 +#define PHY_POWER_STATE_LN_2 0x0010 +#define PHY_POWER_STATE_LN_3 0x0018 +#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 +#define PHY_PMA_CMN_READY 0x34 +#define PHY_PMA_XCVR_TX_VMARGIN0x38 +#define PHY_PMA_XCVR_TX_DEEMPH 0x3c + +/* + * register offsets from SD0801 PHY register block base (i.e MHDP + * register base + 0x50) + */ +#define CMN_SSM_BANDGAP_TMR0x00084 +#define CMN_SSM_BIAS_TMR 0x00088 +#define CMN_PLLSM0_PLLPRE_TMR 0x000a8 +#define CMN_PLLSM0_PLLLOCK_TMR 0x000b0 +#define CMN_PLLSM1_PLLPRE_TMR 0x000c8 +#define CMN_PLLSM1_PLLLOCK_TMR 0x000d0 +#define CMN_BGCAL_INIT_TMR 0x00190 +#define CMN_BGCAL_ITER_TMR 0x00194 +#define CMN_IBCAL_INIT_TMR 0x001d0 +#define CMN_PLL0_VCOCAL_INIT_TMR 0x00210 +#define CMN_PLL0_VCOCAL_ITER_TMR 0x00214 +#define CMN_PLL0_VCOCAL_REFTIM_START 0x00218 +#define CMN_PLL0_VCOCAL_PLLCNT_START 0x00220 +#define CMN_PLL0_INTDIV_M0 0x00240 +#define CMN_PLL0_FRACDIVL_M0 0x00244 +#define CMN_PLL0_FRACDIVH_M0 0x00248 +#define CMN_PLL0_HIGH_THR_M0 0x0024c +#define CMN_PLL0_DSM_DIAG_M0 0x00250 +#define CMN_PLL0_LOCK_PLLCNT_START 0x00278 +#define CMN_PLL1_VCOCAL_INIT_TMR 0x00310 +#define CMN_P
[PATCH v4 0/2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
These patches add preliminary support for the Cadence "Torrent" SD0801 PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. v4: * Comment formatting * Describe "num_lanes" and "max_bit_rate" properties as optional in dt-bindings documentation v3: * Split devicetree bindings documentation into separate commit * Merged phy-cadence-dp.h into phy-cadence-dp.c * Moved probe function to end of file * Minor refactoring of cdns_dp_phy_pma_lane_cfg() * Fixed SPDX comment format v2: * Fixed Linux/um build Scott Telford (2): dt-bindings: phy: Document Cadence MHDP DisplayPort PHY bindings phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY .../devicetree/bindings/phy/phy-cadence-dp.txt | 30 ++ drivers/phy/Kconfig| 1 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig| 10 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-dp.c | 541 + 6 files changed, 584 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-dp.c -- 2.2.2
[PATCH v4 0/2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
These patches add preliminary support for the Cadence "Torrent" SD0801 PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. v4: * Comment formatting * Describe "num_lanes" and "max_bit_rate" properties as optional in dt-bindings documentation v3: * Split devicetree bindings documentation into separate commit * Merged phy-cadence-dp.h into phy-cadence-dp.c * Moved probe function to end of file * Minor refactoring of cdns_dp_phy_pma_lane_cfg() * Fixed SPDX comment format v2: * Fixed Linux/um build Scott Telford (2): dt-bindings: phy: Document Cadence MHDP DisplayPort PHY bindings phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY .../devicetree/bindings/phy/phy-cadence-dp.txt | 30 ++ drivers/phy/Kconfig| 1 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig| 10 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-dp.c | 541 + 6 files changed, 584 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-dp.c -- 2.2.2
[PATCH v4 1/2] dt-bindings: phy: Document Cadence MHDP DisplayPort PHY bindings
Signed-off-by: Scott Telford
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
new file mode 100644
index 000..7f49fd54e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
@@ -0,0 +1,30 @@
+Cadence MHDP DisplayPort SD0801 PHY binding
+===
+
+This binding describes the Cadence SD0801 PHY hardware included with
+the Cadence MHDP DisplayPort controller.
+
+---
+Required properties (controller (parent) node):
+- compatible : Should be "cdns,dp-phy"
+- reg : Defines the following sets of registers in the parent
+ mhdp device:
+ - Offset of the DPTX PHY configuration registers
+ - Offset of the SD0801 PHY configuration registers
+- #phy-cells : from the generic PHY bindings, must be 0.
+
+Optional properties:
+- num_lanes: Number of DisplayPort lanes to use (1, 2 or 4)
+- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
+ 2430, 2700, 3240, 4320, 5400 or 8100)
+---
+
+Example:
+ dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,dp-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x0040>,
+ <0xf0 0xfb50 0x0 0x0010>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ };
--
2.2.2
[PATCH v4 1/2] dt-bindings: phy: Document Cadence MHDP DisplayPort PHY bindings
Signed-off-by: Scott Telford
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
new file mode 100644
index 000..7f49fd54e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
@@ -0,0 +1,30 @@
+Cadence MHDP DisplayPort SD0801 PHY binding
+===
+
+This binding describes the Cadence SD0801 PHY hardware included with
+the Cadence MHDP DisplayPort controller.
+
+---
+Required properties (controller (parent) node):
+- compatible : Should be "cdns,dp-phy"
+- reg : Defines the following sets of registers in the parent
+ mhdp device:
+ - Offset of the DPTX PHY configuration registers
+ - Offset of the SD0801 PHY configuration registers
+- #phy-cells : from the generic PHY bindings, must be 0.
+
+Optional properties:
+- num_lanes: Number of DisplayPort lanes to use (1, 2 or 4)
+- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
+ 2430, 2700, 3240, 4320, 5400 or 8100)
+---
+
+Example:
+ dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,dp-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x0040>,
+ <0xf0 0xfb50 0x0 0x0010>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ };
--
2.2.2
[PATCH v3 2/2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig | 10 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-dp.c | 538 +++ 5 files changed, 551 insertions(+) create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-dp.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 5c8d452..cc47f85 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -43,6 +43,7 @@ config PHY_XGENE source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" +source "drivers/phy/cadence/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/lantiq/Kconfig" source "drivers/phy/marvell/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 84e3bd9..ba48acd 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/ obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += broadcom/\ + cadence/ \ hisilicon/ \ marvell/ \ motorola/\ diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig new file mode 100644 index 000..57fff7d --- /dev/null +++ b/drivers/phy/cadence/Kconfig @@ -0,0 +1,10 @@ +# +# Phy driver for Cadence MHDP DisplayPort controller +# +config PHY_CADENCE_DP + tristate "Cadence MHDP DisplayPort PHY driver" + depends on OF + depends on HAS_IOMEM + select GENERIC_PHY + help + Support for Cadence MHDP DisplayPort PHY. diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile new file mode 100644 index 000..e5b0a11 --- /dev/null +++ b/drivers/phy/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o diff --git a/drivers/phy/cadence/phy-cadence-dp.c b/drivers/phy/cadence/phy-cadence-dp.c new file mode 100644 index 000..10f2e21 --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-dp.c @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence MHDP DisplayPort SD0801 PHY driver. + * + * Copyright 2018 Cadence Design Systems, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEFAULT_NUM_LANES 2 +#define MAX_NUM_LANES 4 +#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ + +#define POLL_TIMEOUT_US2000 +#define LANE_MASK 0x7 + +/* register offsets from DPTX PHY register block base (i.e MHDP + * register base + 0x30a00) + */ +#define PHY_AUX_CONFIG 0x00 +#define PHY_AUX_CTRL 0x04 +#define PHY_RESET 0x20 +#define PHY_PMA_XCVR_PLLCLK_EN 0x24 +#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 +#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c +#define PHY_POWER_STATE_LN_0 0x +#define PHY_POWER_STATE_LN_1 0x0008 +#define PHY_POWER_STATE_LN_2 0x0010 +#define PHY_POWER_STATE_LN_3 0x0018 +#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 +#define PHY_PMA_CMN_READY 0x34 +#define PHY_PMA_XCVR_TX_VMARGIN0x38 +#define PHY_PMA_XCVR_TX_DEEMPH 0x3c + +/* register offsets from SD0801 PHY register block base (i.e MHDP + * register base + 0x50) + */ +#define CMN_SSM_BANDGAP_TMR0x00084 +#define CMN_SSM_BIAS_TMR 0x00088 +#define CMN_PLLSM0_PLLPRE_TMR 0x000a8 +#define CMN_PLLSM0_PLLLOCK_TMR 0x000b0 +#define CMN_PLLSM1_PLLPRE_TMR 0x000c8 +#define CMN_PLLSM1_PLLLOCK_TMR 0x000d0 +#define CMN_BGCAL_INIT_TMR 0x00190 +#define CMN_BGCAL_ITER_TMR 0x00194 +#define CMN_IBCAL_INIT_TMR 0x001d0 +#define CMN_PLL0_VCOCAL_INIT_TMR 0x00210 +#define CMN_PLL0_VCOCAL_ITER_TMR 0x00214 +#define CMN_PLL0_VCOCAL_REFTIM_START 0x00218 +#define CMN_PLL0_VCOCAL_PLLCNT_START 0x00220 +#define CMN_PLL0_INTDIV_M0 0x00240 +#define CMN_PLL0_FRACDIVL_M0 0x00244 +#define CMN_PLL0_FRACDIVH_M0 0x00248 +#define CMN_PLL0_HIGH_THR_M0 0x0024c +#define CMN_PLL0_DSM_DIAG_M0 0x00250 +#define CMN_PLL0_LOCK_PLLCNT_START 0x00278 +#define CMN_PLL1_VCOCAL_INIT_TMR 0x00310 +#define CMN_PLL1_VCOCAL_ITER_TMR
[PATCH v3 2/2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig | 10 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-dp.c | 538 +++ 5 files changed, 551 insertions(+) create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-dp.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 5c8d452..cc47f85 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -43,6 +43,7 @@ config PHY_XGENE source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" +source "drivers/phy/cadence/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/lantiq/Kconfig" source "drivers/phy/marvell/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 84e3bd9..ba48acd 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/ obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += broadcom/\ + cadence/ \ hisilicon/ \ marvell/ \ motorola/\ diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig new file mode 100644 index 000..57fff7d --- /dev/null +++ b/drivers/phy/cadence/Kconfig @@ -0,0 +1,10 @@ +# +# Phy driver for Cadence MHDP DisplayPort controller +# +config PHY_CADENCE_DP + tristate "Cadence MHDP DisplayPort PHY driver" + depends on OF + depends on HAS_IOMEM + select GENERIC_PHY + help + Support for Cadence MHDP DisplayPort PHY. diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile new file mode 100644 index 000..e5b0a11 --- /dev/null +++ b/drivers/phy/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o diff --git a/drivers/phy/cadence/phy-cadence-dp.c b/drivers/phy/cadence/phy-cadence-dp.c new file mode 100644 index 000..10f2e21 --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-dp.c @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence MHDP DisplayPort SD0801 PHY driver. + * + * Copyright 2018 Cadence Design Systems, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEFAULT_NUM_LANES 2 +#define MAX_NUM_LANES 4 +#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ + +#define POLL_TIMEOUT_US2000 +#define LANE_MASK 0x7 + +/* register offsets from DPTX PHY register block base (i.e MHDP + * register base + 0x30a00) + */ +#define PHY_AUX_CONFIG 0x00 +#define PHY_AUX_CTRL 0x04 +#define PHY_RESET 0x20 +#define PHY_PMA_XCVR_PLLCLK_EN 0x24 +#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 +#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c +#define PHY_POWER_STATE_LN_0 0x +#define PHY_POWER_STATE_LN_1 0x0008 +#define PHY_POWER_STATE_LN_2 0x0010 +#define PHY_POWER_STATE_LN_3 0x0018 +#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 +#define PHY_PMA_CMN_READY 0x34 +#define PHY_PMA_XCVR_TX_VMARGIN0x38 +#define PHY_PMA_XCVR_TX_DEEMPH 0x3c + +/* register offsets from SD0801 PHY register block base (i.e MHDP + * register base + 0x50) + */ +#define CMN_SSM_BANDGAP_TMR0x00084 +#define CMN_SSM_BIAS_TMR 0x00088 +#define CMN_PLLSM0_PLLPRE_TMR 0x000a8 +#define CMN_PLLSM0_PLLLOCK_TMR 0x000b0 +#define CMN_PLLSM1_PLLPRE_TMR 0x000c8 +#define CMN_PLLSM1_PLLLOCK_TMR 0x000d0 +#define CMN_BGCAL_INIT_TMR 0x00190 +#define CMN_BGCAL_ITER_TMR 0x00194 +#define CMN_IBCAL_INIT_TMR 0x001d0 +#define CMN_PLL0_VCOCAL_INIT_TMR 0x00210 +#define CMN_PLL0_VCOCAL_ITER_TMR 0x00214 +#define CMN_PLL0_VCOCAL_REFTIM_START 0x00218 +#define CMN_PLL0_VCOCAL_PLLCNT_START 0x00220 +#define CMN_PLL0_INTDIV_M0 0x00240 +#define CMN_PLL0_FRACDIVL_M0 0x00244 +#define CMN_PLL0_FRACDIVH_M0 0x00248 +#define CMN_PLL0_HIGH_THR_M0 0x0024c +#define CMN_PLL0_DSM_DIAG_M0 0x00250 +#define CMN_PLL0_LOCK_PLLCNT_START 0x00278 +#define CMN_PLL1_VCOCAL_INIT_TMR 0x00310 +#define CMN_PLL1_VCOCAL_ITER_TMR
[PATCH v3 1/2] dt-bindings: phy: Document Cadence MHDP DisplayPort PHY bindings
Signed-off-by: Scott Telford
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 28 ++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
new file mode 100644
index 000..8de0526
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
@@ -0,0 +1,28 @@
+Cadence MHDP DisplayPort SD0801 PHY binding
+===
+
+This binding describes the Cadence SD0801 PHY hardware included with
+the Cadence MHDP DisplayPort controller.
+
+---
+Required properties (controller (parent) node):
+- compatible : Should be "cdns,dp-phy"
+- reg : Defines the following sets of registers in the parent
+ mhdp device:
+ - Offset of the DPTX PHY configuration registers
+ - Offset of the SD0801 PHY configuration registers
+- num_lanes: Number of DisplayPort lanes to use (1, 2 or 4)
+- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
+ 2430, 2700, 3240, 4320, 5400 or 8100)
+- #phy-cells : from the generic PHY bindings, must be 0.
+---
+
+Example:
+ dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,dp-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x0040>,
+ <0xf0 0xfb50 0x0 0x0010>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ };
--
2.2.2
[PATCH v3 1/2] dt-bindings: phy: Document Cadence MHDP DisplayPort PHY bindings
Signed-off-by: Scott Telford
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 28 ++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
new file mode 100644
index 000..8de0526
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
@@ -0,0 +1,28 @@
+Cadence MHDP DisplayPort SD0801 PHY binding
+===
+
+This binding describes the Cadence SD0801 PHY hardware included with
+the Cadence MHDP DisplayPort controller.
+
+---
+Required properties (controller (parent) node):
+- compatible : Should be "cdns,dp-phy"
+- reg : Defines the following sets of registers in the parent
+ mhdp device:
+ - Offset of the DPTX PHY configuration registers
+ - Offset of the SD0801 PHY configuration registers
+- num_lanes: Number of DisplayPort lanes to use (1, 2 or 4)
+- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
+ 2430, 2700, 3240, 4320, 5400 or 8100)
+- #phy-cells : from the generic PHY bindings, must be 0.
+---
+
+Example:
+ dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,dp-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x0040>,
+ <0xf0 0xfb50 0x0 0x0010>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ };
--
2.2.2
[PATCH v3 0/2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
These patches add preliminary support for the Cadence "Torrent" SD0801 PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. v3: * Split devicetree bindings documentation into separate commit * Merged phy-cadence-dp.h into phy-cadence-dp.c * Moved probe function to end of file * Minor refactoring of cdns_dp_phy_pma_lane_cfg() * Fixed SPDX comment format v2: * Fixed Linux/um build Scott Telford (2): dt-bindings: phy: Document Cadence MHDP DisplayPort PHY bindings phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY .../devicetree/bindings/phy/phy-cadence-dp.txt | 28 ++ drivers/phy/Kconfig| 1 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig| 10 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-dp.c | 538 + 6 files changed, 579 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-dp.c -- 2.2.2
[PATCH v3 0/2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
These patches add preliminary support for the Cadence "Torrent" SD0801 PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. v3: * Split devicetree bindings documentation into separate commit * Merged phy-cadence-dp.h into phy-cadence-dp.c * Moved probe function to end of file * Minor refactoring of cdns_dp_phy_pma_lane_cfg() * Fixed SPDX comment format v2: * Fixed Linux/um build Scott Telford (2): dt-bindings: phy: Document Cadence MHDP DisplayPort PHY bindings phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY .../devicetree/bindings/phy/phy-cadence-dp.txt | 28 ++ drivers/phy/Kconfig| 1 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig| 10 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-dp.c | 538 + 6 files changed, 579 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-dp.c -- 2.2.2
RE: [PATCH v2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Hi Kishon,
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: 24 July 2018 04:57
> To: Scott Telford ; linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; Damian Kos
> Subject: Re: [PATCH v2] phy: Add driver for Cadence MHDP DisplayPort
> SD0801 PHY
>
[..]
> > +static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy
> *cdns_phy)
> > +{
> > + /* refclock registers - assumes 25 MHz refclock */
> > + writel(0x0019, cdns_phy->sd_base + CMN_SSM_BIAS_TMR);
> > + writel(0x0032, cdns_phy->sd_base + CMN_PLLSM0_PLLPRE_TMR);
> > + writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM0_PLLLOCK_TMR);
> > + writel(0x0032, cdns_phy->sd_base + CMN_PLLSM1_PLLPRE_TMR);
> > + writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM1_PLLLOCK_TMR);
> > + writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_INIT_TMR);
> > + writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_ITER_TMR);
> > + writel(0x0019, cdns_phy->sd_base + CMN_IBCAL_INIT_TMR);
> > + writel(0x001E, cdns_phy->sd_base + CMN_TXPUCAL_INIT_TMR);
> > + writel(0x0006, cdns_phy->sd_base + CMN_TXPUCAL_ITER_TMR);
> > + writel(0x001E, cdns_phy->sd_base + CMN_TXPDCAL_INIT_TMR);
> > + writel(0x0006, cdns_phy->sd_base + CMN_TXPDCAL_ITER_TMR);
> > + writel(0x02EE, cdns_phy->sd_base + CMN_RXCAL_INIT_TMR);
> > + writel(0x0006, cdns_phy->sd_base + CMN_RXCAL_ITER_TMR);
> > + writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_INIT_TMR);
> > + writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_ITER_TMR);
> > + writel(0x000E, cdns_phy->sd_base + CMN_SD_CAL_REFTIM_START);
> > + writel(0x012B, cdns_phy->sd_base + CMN_SD_CAL_PLLCNT_START);
> > + /* PLL registers */
> > + writel(0x0409, cdns_phy->sd_base +
> CMN_PDIAG_PLL0_CP_PADJ_M0);
> > + writel(0x1001, cdns_phy->sd_base +
> CMN_PDIAG_PLL0_CP_IADJ_M0);
> > + writel(0x0F08, cdns_phy->sd_base +
> CMN_PDIAG_PLL0_FILT_PADJ_M0);
> > + writel(0x0004, cdns_phy->sd_base + CMN_PLL0_DSM_DIAG_M0);
> > + writel(0x00FA, cdns_phy->sd_base +
> CMN_PLL0_VCOCAL_INIT_TMR);
> > + writel(0x0004, cdns_phy->sd_base +
> CMN_PLL0_VCOCAL_ITER_TMR);
> > + writel(0x00FA, cdns_phy->sd_base +
> CMN_PLL1_VCOCAL_INIT_TMR);
> > + writel(0x0004, cdns_phy->sd_base +
> CMN_PLL1_VCOCAL_ITER_TMR);
> > + writel(0x0318, cdns_phy->sd_base +
> CMN_PLL0_VCOCAL_REFTIM_START);
>
> Are these values that are written just calibration data or are they bitfields
> for a specific setting. If they are not calibration data, then macros should
> be
> added.
These are calibration values.
I will post a new revision addressing your other comments shortly.
Regards,
Scott.
RE: [PATCH v2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Hi Kishon,
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: 24 July 2018 04:57
> To: Scott Telford ; linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; Damian Kos
> Subject: Re: [PATCH v2] phy: Add driver for Cadence MHDP DisplayPort
> SD0801 PHY
>
[..]
> > +static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy
> *cdns_phy)
> > +{
> > + /* refclock registers - assumes 25 MHz refclock */
> > + writel(0x0019, cdns_phy->sd_base + CMN_SSM_BIAS_TMR);
> > + writel(0x0032, cdns_phy->sd_base + CMN_PLLSM0_PLLPRE_TMR);
> > + writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM0_PLLLOCK_TMR);
> > + writel(0x0032, cdns_phy->sd_base + CMN_PLLSM1_PLLPRE_TMR);
> > + writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM1_PLLLOCK_TMR);
> > + writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_INIT_TMR);
> > + writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_ITER_TMR);
> > + writel(0x0019, cdns_phy->sd_base + CMN_IBCAL_INIT_TMR);
> > + writel(0x001E, cdns_phy->sd_base + CMN_TXPUCAL_INIT_TMR);
> > + writel(0x0006, cdns_phy->sd_base + CMN_TXPUCAL_ITER_TMR);
> > + writel(0x001E, cdns_phy->sd_base + CMN_TXPDCAL_INIT_TMR);
> > + writel(0x0006, cdns_phy->sd_base + CMN_TXPDCAL_ITER_TMR);
> > + writel(0x02EE, cdns_phy->sd_base + CMN_RXCAL_INIT_TMR);
> > + writel(0x0006, cdns_phy->sd_base + CMN_RXCAL_ITER_TMR);
> > + writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_INIT_TMR);
> > + writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_ITER_TMR);
> > + writel(0x000E, cdns_phy->sd_base + CMN_SD_CAL_REFTIM_START);
> > + writel(0x012B, cdns_phy->sd_base + CMN_SD_CAL_PLLCNT_START);
> > + /* PLL registers */
> > + writel(0x0409, cdns_phy->sd_base +
> CMN_PDIAG_PLL0_CP_PADJ_M0);
> > + writel(0x1001, cdns_phy->sd_base +
> CMN_PDIAG_PLL0_CP_IADJ_M0);
> > + writel(0x0F08, cdns_phy->sd_base +
> CMN_PDIAG_PLL0_FILT_PADJ_M0);
> > + writel(0x0004, cdns_phy->sd_base + CMN_PLL0_DSM_DIAG_M0);
> > + writel(0x00FA, cdns_phy->sd_base +
> CMN_PLL0_VCOCAL_INIT_TMR);
> > + writel(0x0004, cdns_phy->sd_base +
> CMN_PLL0_VCOCAL_ITER_TMR);
> > + writel(0x00FA, cdns_phy->sd_base +
> CMN_PLL1_VCOCAL_INIT_TMR);
> > + writel(0x0004, cdns_phy->sd_base +
> CMN_PLL1_VCOCAL_ITER_TMR);
> > + writel(0x0318, cdns_phy->sd_base +
> CMN_PLL0_VCOCAL_REFTIM_START);
>
> Are these values that are written just calibration data or are they bitfields
> for a specific setting. If they are not calibration data, then macros should
> be
> added.
These are calibration values.
I will post a new revision addressing your other comments shortly.
Regards,
Scott.
[PATCH v2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP
DisplayPort Tx controller.
Integration with the MHDP driver will be the subject of another commit.
Signed-off-by: Scott Telford
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 28 ++
drivers/phy/Kconfig| 1 +
drivers/phy/Makefile | 1 +
drivers/phy/cadence/Kconfig| 10 +
drivers/phy/cadence/Makefile | 1 +
drivers/phy/cadence/phy-cadence-dp.c | 436 +
drivers/phy/cadence/phy-cadence-dp.h | 117 ++
7 files changed, 594 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
create mode 100644 drivers/phy/cadence/Kconfig
create mode 100644 drivers/phy/cadence/Makefile
create mode 100644 drivers/phy/cadence/phy-cadence-dp.c
create mode 100644 drivers/phy/cadence/phy-cadence-dp.h
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
new file mode 100644
index 000..8de0526
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
@@ -0,0 +1,28 @@
+Cadence MHDP DisplayPort SD0801 PHY binding
+===
+
+This binding describes the Cadence SD0801 PHY hardware included with
+the Cadence MHDP DisplayPort controller.
+
+---
+Required properties (controller (parent) node):
+- compatible : Should be "cdns,dp-phy"
+- reg : Defines the following sets of registers in the parent
+ mhdp device:
+ - Offset of the DPTX PHY configuration registers
+ - Offset of the SD0801 PHY configuration registers
+- num_lanes: Number of DisplayPort lanes to use (1, 2 or 4)
+- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
+ 2430, 2700, 3240, 4320, 5400 or 8100)
+- #phy-cells : from the generic PHY bindings, must be 0.
+---
+
+Example:
+ dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,dp-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x0040>,
+ <0xf0 0xfb50 0x0 0x0010>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
source "drivers/phy/hisilicon/Kconfig"
source "drivers/phy/lantiq/Kconfig"
source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += broadcom/\
+ cadence/ \
hisilicon/ \
marvell/ \
motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..57fff7d
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,10 @@
+#
+# Phy driver for Cadence MHDP DisplayPort controller
+#
+config PHY_CADENCE_DP
+ tristate "Cadence MHDP DisplayPort PHY driver"
+ depends on OF
+ depends on HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Support for Cadence MHDP DisplayPort PHY.
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..e5b0a11
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o
diff --git a/drivers/phy/cadence/phy-cadence-dp.c
b/drivers/phy/cadence/phy-cadence-dp.c
new file mode 100644
index 000..c1cf89b
--- /dev/null
+++ b/drivers/phy/cadence/phy-cadence-dp.c
@@ -0,0 +1,436 @@
+/*
+ * Cadence MHDP DisplayPort SD0801 PHY driver.
+ *
+ * Copyright 2018 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "phy-cadence-dp.h"
+
+
+static const struct phy_ops cdns_dp_phy_o
[PATCH v2] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP
DisplayPort Tx controller.
Integration with the MHDP driver will be the subject of another commit.
Signed-off-by: Scott Telford
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 28 ++
drivers/phy/Kconfig| 1 +
drivers/phy/Makefile | 1 +
drivers/phy/cadence/Kconfig| 10 +
drivers/phy/cadence/Makefile | 1 +
drivers/phy/cadence/phy-cadence-dp.c | 436 +
drivers/phy/cadence/phy-cadence-dp.h | 117 ++
7 files changed, 594 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
create mode 100644 drivers/phy/cadence/Kconfig
create mode 100644 drivers/phy/cadence/Makefile
create mode 100644 drivers/phy/cadence/phy-cadence-dp.c
create mode 100644 drivers/phy/cadence/phy-cadence-dp.h
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
new file mode 100644
index 000..8de0526
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
@@ -0,0 +1,28 @@
+Cadence MHDP DisplayPort SD0801 PHY binding
+===
+
+This binding describes the Cadence SD0801 PHY hardware included with
+the Cadence MHDP DisplayPort controller.
+
+---
+Required properties (controller (parent) node):
+- compatible : Should be "cdns,dp-phy"
+- reg : Defines the following sets of registers in the parent
+ mhdp device:
+ - Offset of the DPTX PHY configuration registers
+ - Offset of the SD0801 PHY configuration registers
+- num_lanes: Number of DisplayPort lanes to use (1, 2 or 4)
+- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
+ 2430, 2700, 3240, 4320, 5400 or 8100)
+- #phy-cells : from the generic PHY bindings, must be 0.
+---
+
+Example:
+ dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,dp-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x0040>,
+ <0xf0 0xfb50 0x0 0x0010>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
source "drivers/phy/hisilicon/Kconfig"
source "drivers/phy/lantiq/Kconfig"
source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += broadcom/\
+ cadence/ \
hisilicon/ \
marvell/ \
motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..57fff7d
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,10 @@
+#
+# Phy driver for Cadence MHDP DisplayPort controller
+#
+config PHY_CADENCE_DP
+ tristate "Cadence MHDP DisplayPort PHY driver"
+ depends on OF
+ depends on HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Support for Cadence MHDP DisplayPort PHY.
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..e5b0a11
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o
diff --git a/drivers/phy/cadence/phy-cadence-dp.c
b/drivers/phy/cadence/phy-cadence-dp.c
new file mode 100644
index 000..c1cf89b
--- /dev/null
+++ b/drivers/phy/cadence/phy-cadence-dp.c
@@ -0,0 +1,436 @@
+/*
+ * Cadence MHDP DisplayPort SD0801 PHY driver.
+ *
+ * Copyright 2018 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "phy-cadence-dp.h"
+
+
+static const struct phy_ops cdns_dp_phy_o
[PATCH] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP
DisplayPort Tx controller.
Integration with the MHDP driver will be the subject of another commit.
Signed-off-by: Scott Telford
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 28 ++
drivers/phy/Kconfig| 1 +
drivers/phy/Makefile | 1 +
drivers/phy/cadence/Kconfig| 9 +
drivers/phy/cadence/Makefile | 1 +
drivers/phy/cadence/phy-cadence-dp.c | 436 +
drivers/phy/cadence/phy-cadence-dp.h | 117 ++
7 files changed, 593 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
create mode 100644 drivers/phy/cadence/Kconfig
create mode 100644 drivers/phy/cadence/Makefile
create mode 100644 drivers/phy/cadence/phy-cadence-dp.c
create mode 100644 drivers/phy/cadence/phy-cadence-dp.h
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
new file mode 100644
index 000..8de0526
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
@@ -0,0 +1,28 @@
+Cadence MHDP DisplayPort SD0801 PHY binding
+===
+
+This binding describes the Cadence SD0801 PHY hardware included with
+the Cadence MHDP DisplayPort controller.
+
+---
+Required properties (controller (parent) node):
+- compatible : Should be "cdns,dp-phy"
+- reg : Defines the following sets of registers in the parent
+ mhdp device:
+ - Offset of the DPTX PHY configuration registers
+ - Offset of the SD0801 PHY configuration registers
+- num_lanes: Number of DisplayPort lanes to use (1, 2 or 4)
+- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
+ 2430, 2700, 3240, 4320, 5400 or 8100)
+- #phy-cells : from the generic PHY bindings, must be 0.
+---
+
+Example:
+ dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,dp-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x0040>,
+ <0xf0 0xfb50 0x0 0x0010>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
source "drivers/phy/hisilicon/Kconfig"
source "drivers/phy/lantiq/Kconfig"
source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += broadcom/\
+ cadence/ \
hisilicon/ \
marvell/ \
motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..0cb12c2
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy driver for Cadence MHDP DisplayPort controller
+#
+config PHY_CADENCE_DP
+ tristate "Cadence MHDP DisplayPort PHY driver"
+ depends on OF
+ select GENERIC_PHY
+ help
+ Support for Cadence MHDP DisplayPort PHY.
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..e5b0a11
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o
diff --git a/drivers/phy/cadence/phy-cadence-dp.c
b/drivers/phy/cadence/phy-cadence-dp.c
new file mode 100644
index 000..c1cf89b
--- /dev/null
+++ b/drivers/phy/cadence/phy-cadence-dp.c
@@ -0,0 +1,436 @@
+/*
+ * Cadence MHDP DisplayPort SD0801 PHY driver.
+ *
+ * Copyright 2018 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "phy-cadence-dp.h"
+
+
+static const struct phy_ops cdns_dp_phy_ops = {
+ .init = cdns_dp_phy_init,
+
[PATCH] phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY
Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP
DisplayPort Tx controller.
Integration with the MHDP driver will be the subject of another commit.
Signed-off-by: Scott Telford
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 28 ++
drivers/phy/Kconfig| 1 +
drivers/phy/Makefile | 1 +
drivers/phy/cadence/Kconfig| 9 +
drivers/phy/cadence/Makefile | 1 +
drivers/phy/cadence/phy-cadence-dp.c | 436 +
drivers/phy/cadence/phy-cadence-dp.h | 117 ++
7 files changed, 593 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
create mode 100644 drivers/phy/cadence/Kconfig
create mode 100644 drivers/phy/cadence/Makefile
create mode 100644 drivers/phy/cadence/phy-cadence-dp.c
create mode 100644 drivers/phy/cadence/phy-cadence-dp.h
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
new file mode 100644
index 000..8de0526
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
@@ -0,0 +1,28 @@
+Cadence MHDP DisplayPort SD0801 PHY binding
+===
+
+This binding describes the Cadence SD0801 PHY hardware included with
+the Cadence MHDP DisplayPort controller.
+
+---
+Required properties (controller (parent) node):
+- compatible : Should be "cdns,dp-phy"
+- reg : Defines the following sets of registers in the parent
+ mhdp device:
+ - Offset of the DPTX PHY configuration registers
+ - Offset of the SD0801 PHY configuration registers
+- num_lanes: Number of DisplayPort lanes to use (1, 2 or 4)
+- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
+ 2430, 2700, 3240, 4320, 5400 or 8100)
+- #phy-cells : from the generic PHY bindings, must be 0.
+---
+
+Example:
+ dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,dp-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x0040>,
+ <0xf0 0xfb50 0x0 0x0010>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
source "drivers/phy/hisilicon/Kconfig"
source "drivers/phy/lantiq/Kconfig"
source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += broadcom/\
+ cadence/ \
hisilicon/ \
marvell/ \
motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..0cb12c2
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy driver for Cadence MHDP DisplayPort controller
+#
+config PHY_CADENCE_DP
+ tristate "Cadence MHDP DisplayPort PHY driver"
+ depends on OF
+ select GENERIC_PHY
+ help
+ Support for Cadence MHDP DisplayPort PHY.
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..e5b0a11
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o
diff --git a/drivers/phy/cadence/phy-cadence-dp.c
b/drivers/phy/cadence/phy-cadence-dp.c
new file mode 100644
index 000..c1cf89b
--- /dev/null
+++ b/drivers/phy/cadence/phy-cadence-dp.c
@@ -0,0 +1,436 @@
+/*
+ * Cadence MHDP DisplayPort SD0801 PHY driver.
+ *
+ * Copyright 2018 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "phy-cadence-dp.h"
+
+
+static const struct phy_ops cdns_dp_phy_ops = {
+ .init = cdns_dp_phy_init,
+
