[Resend/PATCH] arm: dts: dra7: Add qspi device.
These add device tree entry for qspi controller driver on dra7-evm.
Signed-off-by: Sourav Poddar
---
Depends on sricharan's irq crossbar.
arch/arm/boot/dts/dra7-evm.dts | 80
arch/arm/boot/dts/dra7.dtsi| 14 +++
2 files changed, 94 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..62f4256 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins = <
+ 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
+ 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
+ 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs2.qspi1_cs0 */
+ 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
+ >;
+ };
};
{
@@ -273,3 +288,68 @@
{
cpu0-supply = <_reg>;
};
+
+ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ spi-max-frequency = <4800>;
+ m25p80@0 {
+ compatible = "s25fl256s1";
+ spi-max-frequency = <4800>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+* The ROM checks the first four physical blocks
+* for a valid file to boot and the flash here is
+* 64KiB block size.
+*/
+ partition@0 {
+ label = "QSPI.SPL";
+ reg = <0x 0x1>;
+ };
+ partition@1 {
+ label = "QSPI.SPL.backup1";
+ reg = <0x0001 0x0001>;
+ };
+ partition@2 {
+ label = "QSPI.SPL.backup2";
+ reg = <0x0002 0x0001>;
+ };
+ partition@3 {
+ label = "QSPI.SPL.backup3";
+ reg = <0x0003 0x0001>;
+ };
+ partition@4 {
+ label = "QSPI.u-boot";
+ reg = <0x0004 0x0010>;
+ };
+ partition@5 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x0014 0x0001>;
+ };
+ partition@6 {
+ label = "QSPI.u-boot-env";
+ reg = <0x0015 0x0001>;
+ };
+ partition@7 {
+ label = "QSPI.u-boot-env.backup1";
+ reg = <0x0016 0x001>;
+ };
+ partition@8 {
+ label = "QSPI.kernel";
+ reg = <0x0017 0x080>;
+ };
+ partition@9 {
+ label = "QSPI.file-system";
+ reg = <0x0097 0x0169>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d93311a..a4557b4 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -798,6 +798,20 @@
dma-names = "tx0", "rx0";
status = "disabled";
};
+
+ qspi: qspi@4b30 {
+ compatible = "ti,dra7xxx-qspi";
+ reg = <0x4b30 0x100>;
+ reg-names = "qspi_base";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "qspi";
+ clocks = <_gfclk_div>;
+ clock-names = "fck";
+ num-cs = <4>;
+
[Resend/PATCH] arm: dts: dra7: Add qspi device.
These add device tree entry for qspi controller driver on dra7-evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Depends on sricharan's irq crossbar.
arch/arm/boot/dts/dra7-evm.dts | 80
arch/arm/boot/dts/dra7.dtsi| 14 +++
2 files changed, 94 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..62f4256 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins =
+ 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
+ 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
+ 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs2.qspi1_cs0 */
+ 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
+ ;
+ };
};
i2c1 {
@@ -273,3 +288,68 @@
cpu0 {
cpu0-supply = smps123_reg;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_pins;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = s25fl256s1;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ /* MTD partition table.
+* The ROM checks the first four physical blocks
+* for a valid file to boot and the flash here is
+* 64KiB block size.
+*/
+ partition@0 {
+ label = QSPI.SPL;
+ reg = 0x 0x1;
+ };
+ partition@1 {
+ label = QSPI.SPL.backup1;
+ reg = 0x0001 0x0001;
+ };
+ partition@2 {
+ label = QSPI.SPL.backup2;
+ reg = 0x0002 0x0001;
+ };
+ partition@3 {
+ label = QSPI.SPL.backup3;
+ reg = 0x0003 0x0001;
+ };
+ partition@4 {
+ label = QSPI.u-boot;
+ reg = 0x0004 0x0010;
+ };
+ partition@5 {
+ label = QSPI.u-boot-spl-os;
+ reg = 0x0014 0x0001;
+ };
+ partition@6 {
+ label = QSPI.u-boot-env;
+ reg = 0x0015 0x0001;
+ };
+ partition@7 {
+ label = QSPI.u-boot-env.backup1;
+ reg = 0x0016 0x001;
+ };
+ partition@8 {
+ label = QSPI.kernel;
+ reg = 0x0017 0x080;
+ };
+ partition@9 {
+ label = QSPI.file-system;
+ reg = 0x0097 0x0169;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d93311a..a4557b4 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -798,6 +798,20 @@
dma-names = tx0, rx0;
status = disabled;
};
+
+ qspi: qspi@4b30 {
+ compatible = ti,dra7xxx-qspi;
+ reg = 0x4b30 0x100;
+ reg-names = qspi_base;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = qspi;
+ clocks = qspi_gfclk_div;
+ clock-names = fck;
+ num-cs = 4;
+ interrupts = 0 343 0x4;
+ status = disabled;
+ };
};
crossbar_mpu: crossbar@4a02 {
--
1.7.9.5
--
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[Resend/PATCH] arm: dts: am43x-epos: Add qspi device.
This patch adds qspi nodes for am43xx SOC devices.
Signed-off-by: Sourav Poddar
---
Note,
checpatch gives 1 warning on flash compatible string
"mx66l51235l". This flash is supported in m25p80 driver and
the driver is used for other flash devices also. Hence, each
flash compatible is not described in[1], but a genric example
is shown using spansion flash device.
[1]:
Documentation/devicetree/bindings/mtd/m25p80.txt
arch/arm/boot/dts/am4372.dtsi| 11 ++
arch/arm/boot/dts/am43x-epos-evm.dts | 63 ++
2 files changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 36d523a..49633ff 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -735,6 +735,17 @@
#size-cells = <1>;
status = "disabled";
};
+
+ qspi: qspi@4790 {
+ compatible = "ti,am4372-qspi";
+ reg = <0x4790 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "qspi";
+ interrupts = <0 138 0x4>;
+ num-cs = <4>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 167dbc8..25cd07c 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -138,6 +138,17 @@
0x160 (PIN_INPUT | MUX_MODE7) /*
spi0_cs1.gpio0_6 */
>;
};
+
+ qspi1_default: qspi1_default {
+ pinctrl-single,pins = <
+ 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+ 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -367,3 +378,55 @@
pinctrl-0 = <_pins>;
status = "okay";
};
+
+ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_default>;
+
+ spi-max-frequency = <4800>;
+ m25p80@0 {
+ compatible = "mx66l51235l";
+ spi-max-frequency = <4800>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+* The ROM checks the first 512KiB
+* for a valid file to boot(XIP).
+*/
+ partition@0 {
+ label = "QSPI.U_BOOT";
+ reg = <0x 0x8>;
+ };
+ partition@1 {
+ label = "QSPI.U_BOOT.backup";
+ reg = <0x0008 0x0008>;
+ };
+ partition@2 {
+ label = "QSPI.U-BOOT-SPL_OS";
+ reg = <0x0010 0x0001>;
+ };
+ partition@3 {
+ label = "QSPI.U_BOOT_ENV";
+ reg = <0x0011 0x0001>;
+ };
+ partition@4 {
+ label = "QSPI.U-BOOT-ENV.backup";
+ reg = <0x0012 0x0001>;
+ };
+ partition@5 {
+ label = "QSPI.KERNEL";
+ reg = <0x0013 0x080>;
+ };
+ partition@6 {
+ label = "QSPI.FILESYSTEM";
+ reg = <0x0093 0x36D>;
+ };
+ };
+};
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Please read the FAQ at http://www.tux.org/lkml/
[Resend/PATCH] arm: dts: am43x-epos: Add qspi device.
This patch adds qspi nodes for am43xx SOC devices.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Note,
checpatch gives 1 warning on flash compatible string
mx66l51235l. This flash is supported in m25p80 driver and
the driver is used for other flash devices also. Hence, each
flash compatible is not described in[1], but a genric example
is shown using spansion flash device.
[1]:
Documentation/devicetree/bindings/mtd/m25p80.txt
arch/arm/boot/dts/am4372.dtsi| 11 ++
arch/arm/boot/dts/am43x-epos-evm.dts | 63 ++
2 files changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 36d523a..49633ff 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -735,6 +735,17 @@
#size-cells = 1;
status = disabled;
};
+
+ qspi: qspi@4790 {
+ compatible = ti,am4372-qspi;
+ reg = 0x4790 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = qspi;
+ interrupts = 0 138 0x4;
+ num-cs = 4;
+ status = disabled;
+ };
};
};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 167dbc8..25cd07c 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -138,6 +138,17 @@
0x160 (PIN_INPUT | MUX_MODE7) /*
spi0_cs1.gpio0_6 */
;
};
+
+ qspi1_default: qspi1_default {
+ pinctrl-single,pins =
+ 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+ 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -367,3 +378,55 @@
pinctrl-0 = spi1_pins;
status = okay;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_default;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = mx66l51235l;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ /* MTD partition table.
+* The ROM checks the first 512KiB
+* for a valid file to boot(XIP).
+*/
+ partition@0 {
+ label = QSPI.U_BOOT;
+ reg = 0x 0x8;
+ };
+ partition@1 {
+ label = QSPI.U_BOOT.backup;
+ reg = 0x0008 0x0008;
+ };
+ partition@2 {
+ label = QSPI.U-BOOT-SPL_OS;
+ reg = 0x0010 0x0001;
+ };
+ partition@3 {
+ label = QSPI.U_BOOT_ENV;
+ reg = 0x0011 0x0001;
+ };
+ partition@4 {
+ label = QSPI.U-BOOT-ENV.backup;
+ reg = 0x0012 0x0001;
+ };
+ partition@5 {
+ label = QSPI.KERNEL;
+ reg = 0x0013 0x080;
+ };
+ partition@6 {
+ label = QSPI.FILESYSTEM;
+ reg = 0x0093 0x36D;
+ };
+ };
+};
--
1.7.9.5
--
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the body of a message to majord...@vger.kernel.org
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Re: [PATCH 02/10] mtd: st_spi_fsm: Supply all register address and bit logic defines
On Monday 18 November 2013 11:02 PM, Lee Jones wrote:
On Mon, 18 Nov 2013, Mark Brown wrote:
On Mon, Nov 18, 2013 at 04:02:26PM +, Lee Jones wrote:
On Mon, 18 Nov 2013, Mark Brown wrote:
Like I say I'm suggesting that the bit of the code that understands the
flash chip is separate to the bit of code that knows the mechanics of
sending commands and data to the chip.
The issue is that almost the entire driver is controller side. The
only bits that are the same (and not in all cases) are the OPCODEs,
but they are one liners (21 lines out of 1153). Most of the
controllers which use this stuff could reuse quite a bit of the m25p80
driver as they just write the message containing the OPCODE as the
m25p80 driver sets it up, but that's simply not the case with our
controller. We would have to pull the OPCODE out and based on which
one it is, we'd have to build our own message.
OK, so then perhaps the abstraction here is simply to export the table
with the opcodes from the m25p80 driver so that when someone comes along
and adds a new chip they can just add it there and other drivers will
get the update too.
We could do that, although I'd have to insist on extending the current
framework to add a configuration call-back, as it's the neatest way to
configure chip specific attributes.
This looks like the problem which some other controllers(from ti,
freescale) are facing.
I will just summarise the problem with the ti qspi flash controller
which I am
working on. There is a set of registers which need to be filled with flash
specific commands. One way to deal it with to provide a device tree bindings
for all the requirements(which is really cumbersome.).
Similarly, for freescale there is a LUT registers which has such flash
requirements.
So, surely we need a way out from m25p80 driver to handle such cases.
drivers/mtd/devices/m25p80.c
int pass_flash_info () {
u8 info[6];
info[0] = DUMMY WR;
info[1] = RD_OPCODE;
info[2] - DUMMY BITS;
..
...
spi_write(flash, info, 6)
}
Then, somehow parse this information to set up the required info.
This is just a rough idea, and can be implemented in a better way.
I can get a patch out tomorrow if the MTD guys agree. Where are they
by the way? I haven't seen hide nor hair of them since sending out the
patch set.
Put it this way, if we tried to use the m25p80 our controller driver
would most likely be twice as large and twice as complex as it is
currently, which is exactly the inverse of what we're trying to
achieve here.
If we're having to add new flashes to multiple drivers I'd not say we're
winning.
I agree.
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 02/10] mtd: st_spi_fsm: Supply all register address and bit logic defines
On Monday 18 November 2013 11:02 PM, Lee Jones wrote:
On Mon, 18 Nov 2013, Mark Brown wrote:
On Mon, Nov 18, 2013 at 04:02:26PM +, Lee Jones wrote:
On Mon, 18 Nov 2013, Mark Brown wrote:
Like I say I'm suggesting that the bit of the code that understands the
flash chip is separate to the bit of code that knows the mechanics of
sending commands and data to the chip.
The issue is that almost the entire driver is controller side. The
only bits that are the same (and not in all cases) are the OPCODEs,
but they are one liners (21 lines out of 1153). Most of the
controllers which use this stuff could reuse quite a bit of the m25p80
driver as they just write the message containing the OPCODE as the
m25p80 driver sets it up, but that's simply not the case with our
controller. We would have to pull the OPCODE out and based on which
one it is, we'd have to build our own message.
OK, so then perhaps the abstraction here is simply to export the table
with the opcodes from the m25p80 driver so that when someone comes along
and adds a new chip they can just add it there and other drivers will
get the update too.
We could do that, although I'd have to insist on extending the current
framework to add a configuration call-back, as it's the neatest way to
configure chip specific attributes.
This looks like the problem which some other controllers(from ti,
freescale) are facing.
I will just summarise the problem with the ti qspi flash controller
which I am
working on. There is a set of registers which need to be filled with flash
specific commands. One way to deal it with to provide a device tree bindings
for all the requirements(which is really cumbersome.).
Similarly, for freescale there is a LUT registers which has such flash
requirements.
So, surely we need a way out from m25p80 driver to handle such cases.
drivers/mtd/devices/m25p80.c
int pass_flash_info () {
u8 info[6];
info[0] = DUMMY WR;
info[1] = RD_OPCODE;
info[2] - DUMMY BITS;
..
...
spi_write(flash, info, 6)
}
Then, somehow parse this information to set up the required info.
This is just a rough idea, and can be implemented in a better way.
I can get a patch out tomorrow if the MTD guys agree. Where are they
by the way? I haven't seen hide nor hair of them since sending out the
patch set.
Put it this way, if we tried to use the m25p80 our controller driver
would most likely be twice as large and twice as complex as it is
currently, which is exactly the inverse of what we're trying to
achieve here.
If we're having to add new flashes to multiple drivers I'd not say we're
winning.
I agree.
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: linux-next: build failure after merge of the spi tree
Hi,
On Tuesday 27 August 2013 11:45 AM, Stephen Rothwell wrote:
Hi Mark,
After merging the spi tree, today's linux-next build (x86_64 allmodconfig)
failed like this:
In file included from drivers/spi/spi-ti-qspi.c:19:0:
include/linux/module.h:87:32: error: '__mod_of_device_table' aliased to
undefined symbol 'dra7xxx_qspi_match'
extern const struct gtype##_id __mod_##gtype##_table \
^
include/linux/module.h:145:3: note: in expansion of macro 'MODULE_GENERIC_TABLE'
MODULE_GENERIC_TABLE(type##_device,name)
^
drivers/spi/spi-ti-qspi.c:458:1: note: in expansion of macro
'MODULE_DEVICE_TABLE'
MODULE_DEVICE_TABLE(of, dra7xxx_qspi_match);
^
Caused by commit 505a14954e2d ("spi/qspi: Add qspi flash controller").
Clearly not build tested as a module. :-(
Yes, module build test was missed. I will send a patch for this
to Mark.
I have used the spi tree from next-20130822 for today.
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Re: linux-next: build failure after merge of the spi tree
Hi, On Tuesday 27 August 2013 11:45 AM, Stephen Rothwell wrote: Hi Mark, After merging the spi tree, today's linux-next build (x86_64 allmodconfig) failed like this: In file included from drivers/spi/spi-ti-qspi.c:19:0: include/linux/module.h:87:32: error: '__mod_of_device_table' aliased to undefined symbol 'dra7xxx_qspi_match' extern const struct gtype##_id __mod_##gtype##_table \ ^ include/linux/module.h:145:3: note: in expansion of macro 'MODULE_GENERIC_TABLE' MODULE_GENERIC_TABLE(type##_device,name) ^ drivers/spi/spi-ti-qspi.c:458:1: note: in expansion of macro 'MODULE_DEVICE_TABLE' MODULE_DEVICE_TABLE(of, dra7xxx_qspi_match); ^ Caused by commit 505a14954e2d (spi/qspi: Add qspi flash controller). Clearly not build tested as a module. :-( Yes, module build test was missed. I will send a patch for this to Mark. I have used the spi tree from next-20130822 for today. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC/PATCH 2/2] driver: spi: Add quad spi read support
Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following patch[1], which is just the
basic idea of adding dual/quad support in spi framework.
$subject patch will undergo changes once the ongoing discussion in the
community is freezed.
This patch is posted to demonstrate how patch 1 of the series will support
quad read.
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar
---
drivers/spi/spi-ti-qspi.c | 22 --
1 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 73a1675..fac1722 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -265,18 +265,30 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
int wlen, count, ret;
+ unsigned cmd = qspi->cmd;
count = t->len;
wlen = t->bits_per_word;
+ switch (t->bitwidth) {
+ case SPI_BITWIDTH_QUAD:
+ cmd |= QSPI_RD_QUAD;
+ break;
+ case SPI_BITWIDTH_DUAL:
+ cmd |= QSPI_RD_DUAL;
+ break;
+ case SPI_BITWIDTH_SINGLE:
+ default:
+ cmd |= QSPI_RD_SNGL;
+ }
+
if (wlen == 8) {
u8*rxbuf;
rxbuf = t->rx_buf;
do {
dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n",
qspi->cmd | QSPI_RD_SNGL, qspi->dc);
- ti_qspi_write(qspi, qspi->cmd | QSPI_RD_SNGL,
- QSPI_SPI_CMD_REG);
+ ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
ret =
wait_for_completion_timeout(>transfer_complete,
QSPI_COMPLETION_TIMEOUT);
if (ret == 0) {
@@ -294,8 +306,7 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
do {
dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n",
qspi->cmd | QSPI_RD_SNGL, qspi->dc);
- ti_qspi_write(qspi, qspi->cmd | QSPI_RD_SNGL,
- QSPI_SPI_CMD_REG);
+ ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
ret =
wait_for_completion_timeout(>transfer_complete,
QSPI_COMPLETION_TIMEOUT);
if (ret == 0) {
@@ -313,8 +324,7 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
do {
dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n",
qspi->cmd | QSPI_RD_SNGL, qspi->dc);
- ti_qspi_write(qspi, qspi->cmd | QSPI_RD_SNGL,
- QSPI_SPI_CMD_REG);
+ ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
ret =
wait_for_completion_timeout(>transfer_complete,
QSPI_COMPLETION_TIMEOUT);
if (ret == 0) {
--
1.7.1
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[PATCHv8 1/2] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Test details:
-
Tested this on dra7 board.
Test1: Ran mtd_stesstest for 4 iterations.
- All iterations went through without failure.
Test2: Use mtd utilities:
- flash_erase to erase the flash device
- nanddump to read data back.
- nandwrite to write to the data flash.
diff between the write and read data shows zero.
Signed-off-by: Sourav Poddar
---
I have kept few more than 80 characters warning for better
code readilbilty.
v7->v8:
- Get rid of write/read data for better handling of
different word length
- Lock the transfer list
- miscellaneous cleanup.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 +
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/spi-ti-qspi.c | 591 +
4 files changed, 622 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/spi-ti-qspi.c
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b/Documentation/devicetree/bindings/spi/ti_qspi.txt
new file mode 100644
index 000..398ef59
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -0,0 +1,22 @@
+TI QSPI controller.
+
+Required properties:
+- compatible : should be "ti,dra7xxx-qspi".
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+qspi: qspi@4b30 {
+ compatible = "ti,dra7xxx-qspi";
+ reg = <0x4b30 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <2500>;
+ ti,hwmods = "qspi";
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..1c4e758 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,14 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config SPI_TI_QSPI
+ tristate "DRA7xxx QSPI controller support"
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+ This device supports single, dual and quad read support, while
+ it only supports single write mode.
+
config SPI_OMAP_100K
tristate "OMAP SPI 100K"
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..a174030 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..1d5767d
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
@@ -0,0 +1,591 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Sourav Poddar
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GPLv2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct ti_qspi_regs {
+ u32 clkctrl;
+};
+
+struct ti_qspi {
+ struct completion transfer_complete;
+
+ /* IRQ synchronization */
+ spinlock_t lock;
+
+ /* list synchronization */
+ struct mutexlist_lock;
+
+
[PATCHv8 0/2] Add ti qspi controller
This patch series add support for ti qspi controller. Adapted this series on top of Mark brown series[1]: [1]: https://patchwork.kernel.org/patch/2834694/ Sourav Poddar (2): drivers: spi: Add qspi flash controller driver: spi: Add quad spi read support Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 + drivers/spi/Kconfig |8 + drivers/spi/Makefile |1 + drivers/spi/spi-ti-qspi.c | 600 + 4 files changed, 631 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt create mode 100644 drivers/spi/spi-ti-qspi.c -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCHv8 0/2] Add ti qspi controller
This patch series add support for ti qspi controller. Adapted this series on top of Mark brown series[1]: [1]: https://patchwork.kernel.org/patch/2834694/ Sourav Poddar (2): drivers: spi: Add qspi flash controller driver: spi: Add quad spi read support Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 + drivers/spi/Kconfig |8 + drivers/spi/Makefile |1 + drivers/spi/spi-ti-qspi.c | 600 + 4 files changed, 631 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt create mode 100644 drivers/spi/spi-ti-qspi.c -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCHv8 1/2] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Test details:
-
Tested this on dra7 board.
Test1: Ran mtd_stesstest for 4 iterations.
- All iterations went through without failure.
Test2: Use mtd utilities:
- flash_erase to erase the flash device
- nanddump to read data back.
- nandwrite to write to the data flash.
diff between the write and read data shows zero.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
I have kept few more than 80 characters warning for better
code readilbilty.
v7-v8:
- Get rid of write/read data for better handling of
different word length
- Lock the transfer list
- miscellaneous cleanup.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 +
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/spi-ti-qspi.c | 591 +
4 files changed, 622 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/spi-ti-qspi.c
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b/Documentation/devicetree/bindings/spi/ti_qspi.txt
new file mode 100644
index 000..398ef59
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -0,0 +1,22 @@
+TI QSPI controller.
+
+Required properties:
+- compatible : should be ti,dra7xxx-qspi.
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+qspi: qspi@4b30 {
+ compatible = ti,dra7xxx-qspi;
+ reg = 0x4b30 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+ spi-max-frequency = 2500;
+ ti,hwmods = qspi;
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..1c4e758 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,14 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config SPI_TI_QSPI
+ tristate DRA7xxx QSPI controller support
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+ This device supports single, dual and quad read support, while
+ it only supports single write mode.
+
config SPI_OMAP_100K
tristate OMAP SPI 100K
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..a174030 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..1d5767d
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
@@ -0,0 +1,591 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Sourav Poddar sourav.pod...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GPLv2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/device.h
+#include linux/delay.h
+#include linux/dma-mapping.h
+#include linux/dmaengine.h
+#include linux/omap-dma.h
+#include linux/platform_device.h
+#include linux/err.h
+#include linux/clk.h
+#include linux/io.h
+#include linux/slab.h
+#include linux/pm_runtime.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/consumer.h
+
+#include linux/spi/spi.h
+
+struct ti_qspi_regs {
+ u32 clkctrl
[RFC/PATCH 2/2] driver: spi: Add quad spi read support
Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following patch[1], which is just the
basic idea of adding dual/quad support in spi framework.
$subject patch will undergo changes once the ongoing discussion in the
community is freezed.
This patch is posted to demonstrate how patch 1 of the series will support
quad read.
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 22 --
1 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 73a1675..fac1722 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -265,18 +265,30 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
{
int wlen, count, ret;
+ unsigned cmd = qspi-cmd;
count = t-len;
wlen = t-bits_per_word;
+ switch (t-bitwidth) {
+ case SPI_BITWIDTH_QUAD:
+ cmd |= QSPI_RD_QUAD;
+ break;
+ case SPI_BITWIDTH_DUAL:
+ cmd |= QSPI_RD_DUAL;
+ break;
+ case SPI_BITWIDTH_SINGLE:
+ default:
+ cmd |= QSPI_RD_SNGL;
+ }
+
if (wlen == 8) {
u8*rxbuf;
rxbuf = t-rx_buf;
do {
dev_dbg(qspi-dev, rx cmd %08x dc %08x\n,
qspi-cmd | QSPI_RD_SNGL, qspi-dc);
- ti_qspi_write(qspi, qspi-cmd | QSPI_RD_SNGL,
- QSPI_SPI_CMD_REG);
+ ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
ret =
wait_for_completion_timeout(qspi-transfer_complete,
QSPI_COMPLETION_TIMEOUT);
if (ret == 0) {
@@ -294,8 +306,7 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
do {
dev_dbg(qspi-dev, rx cmd %08x dc %08x\n,
qspi-cmd | QSPI_RD_SNGL, qspi-dc);
- ti_qspi_write(qspi, qspi-cmd | QSPI_RD_SNGL,
- QSPI_SPI_CMD_REG);
+ ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
ret =
wait_for_completion_timeout(qspi-transfer_complete,
QSPI_COMPLETION_TIMEOUT);
if (ret == 0) {
@@ -313,8 +324,7 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
do {
dev_dbg(qspi-dev, rx cmd %08x dc %08x\n,
qspi-cmd | QSPI_RD_SNGL, qspi-dc);
- ti_qspi_write(qspi, qspi-cmd | QSPI_RD_SNGL,
- QSPI_SPI_CMD_REG);
+ ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
ret =
wait_for_completion_timeout(qspi-transfer_complete,
QSPI_COMPLETION_TIMEOUT);
if (ret == 0) {
--
1.7.1
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
Hi Mark,
On Thursday 18 July 2013 04:12 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
Have you seen the ongoing thread about SPI buses with extra data lines?
How does this driver fit in with that?
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION) += spi-orion.o
obj-$(CONFIG_SPI_PL022) += spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
Please use SPI_ like the other drivers.
+static int ti_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ int ret;
+
+ ret = pm_runtime_get_sync(qspi->dev);
+ if (ret< 0) {
+ dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
+ return ret;
+ }
+
+ return 0;
+}
This is a very common pattern, it should probably be factored out into
the core, probably not even as ops but rather as an actual feature.
I see, every other driver doing it this way right now.
Is it ok, if I take your above idea as an seperate excercise after this
patch.?
+ list_for_each_entry(t,>transfers, transfer_list) {
+ qspi->cmd |= QSPI_WLEN(t->bits_per_word);
+ qspi->cmd |= QSPI_WC_CMD_INT_EN;
+
+ ret = qspi_transfer_msg(qspi, t);
+ if (ret) {
+ dev_dbg(qspi->dev, "transfer message failed\n");
+ return -EINVAL;
+ }
+
+ m->actual_length += t->len;
+
+ if (list_is_last(>transfer_list,>transfers))
+ goto out;
+ }
The use of list_is_last() here is *realy* strange - what's going on
there?
+static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
+{
+ struct ti_qspi *qspi = dev_id;
+ u16 mask, stat;
+
+ irqreturn_t ret = IRQ_HANDLED;
+
+ spin_lock(>lock);
+
+ stat = ti_qspi_readl(qspi, QSPI_SPI_STATUS_REG);
+ mask = ti_qspi_readl(qspi, QSPI_INTR_ENABLE_SET_REG);
+
+ if (stat&& mask)
+ ret = IRQ_WAKE_THREAD;
+
+ spin_unlock(>lock);
+
+ return ret;
According to the above code we might interrupt for masked events...
that's a bit worrying isn't it?
+ ret = devm_request_threaded_irq(>dev, irq, ti_qspi_isr,
+ ti_qspi_threaded_isr, IRQF_NO_SUSPEND | IRQF_ONESHOT,
+ dev_name(>dev), qspi);
+ if (ret< 0) {
+ dev_err(>dev, "Failed to register ISR for IRQ %d\n",
+ irq);
+ goto free_master;
+ }
Standard question about devm_request_threaded_irq() - how can we be
certain it's safe to use during removal?
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
Hi Felipe,
On Thursday 18 July 2013 04:54 PM, Felipe Balbi wrote:
On Thu, Jul 18, 2013 at 04:48:41PM +0530, Sourav Poddar wrote:
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t->len;
+ txbuf = t->tx_buf;
+ wlen = t->bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
+ qspi->cmd | QSPI_WR_SNGL, qspi->dc, *txbuf);
+ ti_qspi_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
you always increment by each byte. Here, if you used writel(), you wrote
4 bytes and should increment txbuf by 4.
hmm..got this point. Yes, my mistake, here I agree if wlen is not 8 bits
txbuf++ is not valid.
Same goes for read_data(),
below. Another thing. Even though your wlen might be 8 bits, if you
write 4 bytes to write, you can save a few CPU cycles by using writel().
Do you mean 4 words of 8 bits?
yeah. Say you have wlen = 8 but the transfer length is 8 bytes (64
bits). If you use writeb(), you will do 8 writes, if you use writel()
you'll do 2 writes.
Just some more findings on this, after wlen bits are transferred we need
an WC interrupt.
So, if I try to pack 4 words of 8bits and use readl/writel, there will
be an interrupt after every
wlen bits transferred and things will get screwd up.
So, for 8 bits word we need to use readb, for 16 bits word readw.
+static int ti_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m->spi;
+ struct spi_transfer *t;
+ int status = 0, ret;
+ int frame_length;
+
+ /* setup device control reg */
+ qspi->dc = 0;
+
+ if (spi->mode& SPI_CPHA)
+ qspi->dc |= QSPI_CKPHA(spi->chip_select);
+ if (spi->mode& SPI_CPOL)
+ qspi->dc |= QSPI_CKPOL(spi->chip_select);
+ if (spi->mode& SPI_CS_HIGH)
+ qspi->dc |= QSPI_CSPOL(spi->chip_select);
+
+ frame_length = DIV_ROUND_UP(m->frame_length * spi->bits_per_word,
+ spi->bits_per_word);
this calculation doesn't look correct.
(m->frame_length * spi->bits_per_word) /
spi->bits_per_word = m->frame_length
What are you trying to achieve here ? frame_length should be counted in
words right ? And we get that value in bytes. So what's the best
calculation to convert bytes into words ? If you have 8 bits_per_word
you don't need any calculation, but if you have 32 bits_per_word, you
_do_ need something.
Yes, just derive this formulae with 8 bits per word in mind.
Will change.
It should be (m->frame_length * 8) / spi->bits_per_word
right on. To make sure this will execute a little faster (you never know
what several different versions of GCC will do), instead of multiplying
by 8, left shift by 3.
How will you achieve the number you want ? (hint: 1 byte == 8 bits)
And btw, all of these mistakes pretty much tell me that this driver
hasn't been tested. How have you tested this driver ?
After bootup, I checked for deive detting enumerated as /proc/mtd.
After which I am using mtdutils(erase, dump and write utilied to
check for the communication with the flash device.)
alright, make that clear in your commit log.
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
Hi Felipe,
On Thursday 18 July 2013 04:54 PM, Felipe Balbi wrote:
On Thu, Jul 18, 2013 at 04:48:41PM +0530, Sourav Poddar wrote:
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf = t-tx_buf;
+ wlen = t-bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi-dev, tx cmd %08x dc %08x data %02x\n,
+ qspi-cmd | QSPI_WR_SNGL, qspi-dc, *txbuf);
+ ti_qspi_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
you always increment by each byte. Here, if you used writel(), you wrote
4 bytes and should increment txbuf by 4.
hmm..got this point. Yes, my mistake, here I agree if wlen is not 8 bits
txbuf++ is not valid.
Same goes for read_data(),
below. Another thing. Even though your wlen might be 8 bits, if you
write 4 bytes to write, you can save a few CPU cycles by using writel().
Do you mean 4 words of 8 bits?
yeah. Say you have wlen = 8 but the transfer length is 8 bytes (64
bits). If you use writeb(), you will do 8 writes, if you use writel()
you'll do 2 writes.
Just some more findings on this, after wlen bits are transferred we need
an WC interrupt.
So, if I try to pack 4 words of 8bits and use readl/writel, there will
be an interrupt after every
wlen bits transferred and things will get screwd up.
So, for 8 bits word we need to use readb, for 16 bits word readw.
+static int ti_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m-spi;
+ struct spi_transfer *t;
+ int status = 0, ret;
+ int frame_length;
+
+ /* setup device control reg */
+ qspi-dc = 0;
+
+ if (spi-mode SPI_CPHA)
+ qspi-dc |= QSPI_CKPHA(spi-chip_select);
+ if (spi-mode SPI_CPOL)
+ qspi-dc |= QSPI_CKPOL(spi-chip_select);
+ if (spi-mode SPI_CS_HIGH)
+ qspi-dc |= QSPI_CSPOL(spi-chip_select);
+
+ frame_length = DIV_ROUND_UP(m-frame_length * spi-bits_per_word,
+ spi-bits_per_word);
this calculation doesn't look correct.
(m-frame_length * spi-bits_per_word) /
spi-bits_per_word = m-frame_length
What are you trying to achieve here ? frame_length should be counted in
words right ? And we get that value in bytes. So what's the best
calculation to convert bytes into words ? If you have 8 bits_per_word
you don't need any calculation, but if you have 32 bits_per_word, you
_do_ need something.
Yes, just derive this formulae with 8 bits per word in mind.
Will change.
It should be (m-frame_length * 8) / spi-bits_per_word
right on. To make sure this will execute a little faster (you never know
what several different versions of GCC will do), instead of multiplying
by 8, left shift by 3.
How will you achieve the number you want ? (hint: 1 byte == 8 bits)
And btw, all of these mistakes pretty much tell me that this driver
hasn't been tested. How have you tested this driver ?
After bootup, I checked for deive detting enumerated as /proc/mtd.
After which I am using mtdutils(erase, dump and write utilied to
check for the communication with the flash device.)
alright, make that clear in your commit log.
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
Hi Mark,
On Thursday 18 July 2013 04:12 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
Have you seen the ongoing thread about SPI buses with extra data lines?
How does this driver fit in with that?
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION) += spi-orion.o
obj-$(CONFIG_SPI_PL022) += spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
Please use SPI_ like the other drivers.
+static int ti_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ int ret;
+
+ ret = pm_runtime_get_sync(qspi-dev);
+ if (ret 0) {
+ dev_err(qspi-dev, pm_runtime_get_sync() failed\n);
+ return ret;
+ }
+
+ return 0;
+}
This is a very common pattern, it should probably be factored out into
the core, probably not even as ops but rather as an actual feature.
I see, every other driver doing it this way right now.
Is it ok, if I take your above idea as an seperate excercise after this
patch.?
+ list_for_each_entry(t,m-transfers, transfer_list) {
+ qspi-cmd |= QSPI_WLEN(t-bits_per_word);
+ qspi-cmd |= QSPI_WC_CMD_INT_EN;
+
+ ret = qspi_transfer_msg(qspi, t);
+ if (ret) {
+ dev_dbg(qspi-dev, transfer message failed\n);
+ return -EINVAL;
+ }
+
+ m-actual_length += t-len;
+
+ if (list_is_last(t-transfer_list,m-transfers))
+ goto out;
+ }
The use of list_is_last() here is *realy* strange - what's going on
there?
+static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
+{
+ struct ti_qspi *qspi = dev_id;
+ u16 mask, stat;
+
+ irqreturn_t ret = IRQ_HANDLED;
+
+ spin_lock(qspi-lock);
+
+ stat = ti_qspi_readl(qspi, QSPI_SPI_STATUS_REG);
+ mask = ti_qspi_readl(qspi, QSPI_INTR_ENABLE_SET_REG);
+
+ if (stat mask)
+ ret = IRQ_WAKE_THREAD;
+
+ spin_unlock(qspi-lock);
+
+ return ret;
According to the above code we might interrupt for masked events...
that's a bit worrying isn't it?
+ ret = devm_request_threaded_irq(pdev-dev, irq, ti_qspi_isr,
+ ti_qspi_threaded_isr, IRQF_NO_SUSPEND | IRQF_ONESHOT,
+ dev_name(pdev-dev), qspi);
+ if (ret 0) {
+ dev_err(pdev-dev, Failed to register ISR for IRQ %d\n,
+ irq);
+ goto free_master;
+ }
Standard question about devm_request_threaded_irq() - how can we be
certain it's safe to use during removal?
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
On Friday 19 July 2013 12:38 AM, Trent Piepho wrote:
On Thu, Jul 18, 2013 at 3:01 AM, Sourav Poddar wrote:
+Required properties:
+- compatible : should be "ti,dra7xxx-qspi".
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
What is ti,hwmods? It's not clear from the description. It also
doesn't appear to be used in the driver. At least, I did not find any
occurrence of "hwmods" in the driver code.
+static inline unsigned long ti_qspi_readl_data(struct ti_qspi *qspi,
+ unsigned long reg, int wlen)
"readl" means read LONG. That's what the L is for. But this does
different widths.
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi->base + reg);
+ break;
wlen == 8, but readw == 16 bit read?
Yes, I need to change this. should be readb.
The break after the return isn't necessary.
+ case 16:
+ return readb(qspi->base + reg);
+ break;
wlen == 16, but readb == 8 bit read?
same here.
+ case 32:
+ return readl(qspi->base + reg);
wlen == 32, readl == 32, this one makes sense, but
+static inline void ti_qspi_writel_data(struct ti_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+ case 32:
+ writeb(val, qspi->base + reg);
+ break;
A 32 bit write uses an 8 bit write command, while read is 32 bits??
This doesn't make a lot of sense. If it's actually correct, there
should be come kind of comment about it.
Yes, I will change this in the next version.
+
+static int ti_qspi_setup(struct spi_device *spi)
+{
+
+ clk_ctrl_reg = ti_qspi_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ clk_ctrl_reg&= ~QSPI_CLK_EN;
+
+ /* disable SCLK */
+ ti_qspi_writel(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
Did you read this from Documentation/spi/spi-summary?
** BUG ALERT: for some reason the first version of
** many spi_master drivers seems to get this wrong.
** When you code setup(), ASSUME that the controller
** is actively processing transfers for another device.
But I see in this documentation, that setup is usually used for setting up
device clock rate, modes etc.
So, what do you recommend here, should we move clk settings to prepare
hardware ?
+static int ti_qspi_probe(struct platform_device *pdev)
+{
+
+ master->mode_bits = SPI_CPOL | SPI_CPHA;
Does your device support full duplex? It doesn't look like it does.
You should set the SPI_MASER_HALF_DUPLEX flag in master->flags.
hmm. Ok, will add.
+
+ if (!of_property_read_u32(np, "ti,spi-num-cs",_cs))
+ master->num_chipselect = num_cs;
You didn't document this property. How is this different than the
"num-cs" property already documented in spi-bus bindings?
Actually, it is no different. This also means the total number of
chipselects.
I used it from omap mcspi. I will make this property in accordance with the
generic binding.
Will also send a seperate patch for omap mcspi.
+ qspi->base = devm_ioremap_resource(>dev, r);
+ if (IS_ERR(qspi->base)) {
+ ret = -ENOMEM;
Shouldn't that be ret = PTR_ERR(qspi->base)
hmm.will change.
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
Hi Mark, On Thursday 18 July 2013 08:12 PM, Mark Brown wrote: On Thu, Jul 18, 2013 at 04:31:58PM +0300, Felipe Balbi wrote: On Thu, Jul 18, 2013 at 02:18:22PM +0100, Mark Brown wrote: So why do we report that we handled the interrupt then? Shouldn't we at least warn if we're getting spurious IRQs? not spurious. OMAP has two sets of IRQ status registers. One is call IRQSTATUS$n (n = 0, 1, ...) and IRQSTATUS_RAW$n. IRQSTATUS$n will only enable the bits which fired IRQs and aren't masked while IRQSTATUS_RAW$n will also enable the bits which are masked. I could never come up with a use case where we would need to handle IRQs which we decided to mask, but perhaps there might be some cases, I don't know. Based on that, I believe Sourav is reading IRQSTATUS_RAW$n, then he need to clear the masked bits. That's not the issue - the issue is that if none of the unmasked interrupts are being asserted we shouldn't be in the interrupt handler in the first place but the driver silently accepts that and reports that it handled the interrupt. I believe this is what you hinted at doing.. there is a QSPI_INTR_STATUS_ENABLED_CLEAR register, which indicated the interrupt status. if nothing is set in the above register, I should return IRQ_NONE. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
On Thursday 18 July 2013 04:54 PM, Felipe Balbi wrote:
On Thu, Jul 18, 2013 at 04:48:41PM +0530, Sourav Poddar wrote:
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t->len;
+ txbuf = t->tx_buf;
+ wlen = t->bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
+ qspi->cmd | QSPI_WR_SNGL, qspi->dc, *txbuf);
+ ti_qspi_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
you always increment by each byte. Here, if you used writel(), you wrote
4 bytes and should increment txbuf by 4.
hmm..got this point. Yes, my mistake, here I agree if wlen is not 8 bits
txbuf++ is not valid.
Same goes for read_data(),
below. Another thing. Even though your wlen might be 8 bits, if you
write 4 bytes to write, you can save a few CPU cycles by using writel().
Do you mean 4 words of 8 bits?
yeah. Say you have wlen = 8 but the transfer length is 8 bytes (64
bits). If you use writeb(), you will do 8 writes, if you use writel()
you'll do 2 writes.
hmm.. I will check this out.
If our wlen is 8, after every 8 bits there will be
an interrupt. Will check that out, how that interrupt
should be tackled if we desired to read 4 bytes in a single writel/readl.
+static int ti_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m->spi;
+ struct spi_transfer *t;
+ int status = 0, ret;
+ int frame_length;
+
+ /* setup device control reg */
+ qspi->dc = 0;
+
+ if (spi->mode& SPI_CPHA)
+ qspi->dc |= QSPI_CKPHA(spi->chip_select);
+ if (spi->mode& SPI_CPOL)
+ qspi->dc |= QSPI_CKPOL(spi->chip_select);
+ if (spi->mode& SPI_CS_HIGH)
+ qspi->dc |= QSPI_CSPOL(spi->chip_select);
+
+ frame_length = DIV_ROUND_UP(m->frame_length * spi->bits_per_word,
+ spi->bits_per_word);
this calculation doesn't look correct.
(m->frame_length * spi->bits_per_word) /
spi->bits_per_word = m->frame_length
What are you trying to achieve here ? frame_length should be counted in
words right ? And we get that value in bytes. So what's the best
calculation to convert bytes into words ? If you have 8 bits_per_word
you don't need any calculation, but if you have 32 bits_per_word, you
_do_ need something.
Yes, just derive this formulae with 8 bits per word in mind.
Will change.
It should be (m->frame_length * 8) / spi->bits_per_word
right on. To make sure this will execute a little faster (you never know
what several different versions of GCC will do), instead of multiplying
by 8, left shift by 3.
Ok. Will do.
How will you achieve the number you want ? (hint: 1 byte == 8 bits)
And btw, all of these mistakes pretty much tell me that this driver
hasn't been tested. How have you tested this driver ?
After bootup, I checked for deive detting enumerated as /proc/mtd.
After which I am using mtdutils(erase, dump and write utilied to
check for the communication with the flash device.)
alright, make that clear in your commit log.
Ok.
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Re: [RFC/PATCHv2 3/3] driver: spi: Add quad spi read support
On Thursday 18 July 2013 04:14 PM, Mark Brown wrote: On Thu, Jul 18, 2013 at 03:31:27PM +0530, Sourav Poddar wrote: Since, qspi controller uses quad read. Configuring the command register, if the transfer of data needs dual or quad lines. This patch has been done on top of the following patch[1], which is just the basic idea of adding dual/quad support in spi framework. $subject patch will undergo changes as the parent patch goes[1] [1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047 Just as with commit IDs you should include a plain text description of anything you link to so that people reading your e-mail can tell what you're talking about without going on line. Ok, will keep that in mind for future. Just to give you a brief description here, Requirement is to have a dual/quad support in spi frameowrk, so that drivers can use multiple lines for data transfers. What patch[1] tries to does, is [1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047 is to add to each transfer the bitwidth it supports, so that that bitwidth information can be parsed in controller driver and can be used for respective read/writes. A typical usecase on my side is, I have a spansion flash connected to qspi. Flash device supports quad read with a certain read opcode(QUAD_READ). So, Whenever the opcode send is QUAD_READ, we will append that information as a bitwidth to the spi transfer. This information will be parsed by the controller driver and will be used to configure the cmd reg to do the particular type of reads. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
On Thursday 18 July 2013 04:12 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
Have you seen the ongoing thread about SPI buses with extra data lines?
How does this driver fit in with that?
I have tried using it in my patch3 of this series..
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION) += spi-orion.o
obj-$(CONFIG_SPI_PL022) += spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
Please use SPI_ like the other drivers.
Ok.
+static int ti_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ int ret;
+
+ ret = pm_runtime_get_sync(qspi->dev);
+ if (ret< 0) {
+ dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
+ return ret;
+ }
+
+ return 0;
+}
This is a very common pattern, it should probably be factored out into
the core, probably not even as ops but rather as an actual feature.
May be yes.
+ list_for_each_entry(t,>transfers, transfer_list) {
+ qspi->cmd |= QSPI_WLEN(t->bits_per_word);
+ qspi->cmd |= QSPI_WC_CMD_INT_EN;
+
+ ret = qspi_transfer_msg(qspi, t);
+ if (ret) {
+ dev_dbg(qspi->dev, "transfer message failed\n");
+ return -EINVAL;
+ }
+
+ m->actual_length += t->len;
+
+ if (list_is_last(>transfer_list,>transfers))
+ goto out;
+ }
The use of list_is_last() here is *realy* strange - what's going on
there?
We are checking if there is any transfer left, if no we are signalling the
flash device about the end of transfer.
+static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
+{
+ struct ti_qspi *qspi = dev_id;
+ u16 mask, stat;
+
+ irqreturn_t ret = IRQ_HANDLED;
+
+ spin_lock(>lock);
+
+ stat = ti_qspi_readl(qspi, QSPI_SPI_STATUS_REG);
+ mask = ti_qspi_readl(qspi, QSPI_INTR_ENABLE_SET_REG);
+
+ if (stat&& mask)
+ ret = IRQ_WAKE_THREAD;
+
+ spin_unlock(>lock);
+
+ return ret;
According to the above code we might interrupt for masked events...
that's a bit worrying isn't it?
Yes, there is WC interrupt enable bit which enables the interrupt. This
interrupt
gets disabled by writing to the CLEAR reg in the threaded irq.
+ ret = devm_request_threaded_irq(>dev, irq, ti_qspi_isr,
+ ti_qspi_threaded_isr, IRQF_NO_SUSPEND | IRQF_ONESHOT,
+ dev_name(>dev), qspi);
+ if (ret< 0) {
+ dev_err(>dev, "Failed to register ISR for IRQ %d\n",
+ irq);
+ goto free_master;
+ }
Standard question about devm_request_threaded_irq() - how can we be
certain it's safe to use during removal?
I am not sure about the exact flow. If we see the api description, it
says about irq getting
freed automatically.
Practically, I will check that on removing the driver, cat
/proc/interrupts should not show
the required interrupt getting registered.
Though, I see an api also existing "devm_free_irq", which explicitly un
allocate your irq requested
through devm_* variants.
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
Hi Felipe,
On Thursday 18 July 2013 03:54 PM, Felipe Balbi wrote:
Hi,
it might be just me, but ...
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
+static inline unsigned long ti_qspi_readl_data(struct ti_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi->base + reg);
+ break;
+ case 16:
+ return readb(qspi->base + reg);
+ break;
+ case 32:
+ return readl(qspi->base + reg);
+ break;
+ default:
+ return -EINVAL;
+ }
+}
+
+static inline void ti_qspi_writel_data(struct ti_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ writew(val, qspi->base + reg);
+ break;
+ case 16:
+ writeb(val, qspi->base + reg);
+ break;
+ case 32:
+ writeb(val, qspi->base + reg);
+ break;
+ default:
+ dev_dbg(qspi->dev, "word lenght out of range");
+ break;
+ }
+}
because of these two functions you have the hability to read/write
*more* than one byte, and yet ...
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t->len;
+ txbuf = t->tx_buf;
+ wlen = t->bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
+ qspi->cmd | QSPI_WR_SNGL, qspi->dc, *txbuf);
+ ti_qspi_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
you always increment by each byte. Here, if you used writel(), you wrote
4 bytes and should increment txbuf by 4.
hmm..got this point. Yes, my mistake, here I agree if wlen is not 8 bits
txbuf++ is not valid.
Same goes for read_data(),
below. Another thing. Even though your wlen might be 8 bits, if you
write 4 bytes to write, you can save a few CPU cycles by using writel().
Do you mean 4 words of 8 bits?
You only use writew() if you have exactly 2 bytes to write and writeb()
if you have exactly 1 byte to write. 3 bytes we'll be left as an
exercise.
hmm..yes.
+static int ti_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m->spi;
+ struct spi_transfer *t;
+ int status = 0, ret;
+ int frame_length;
+
+ /* setup device control reg */
+ qspi->dc = 0;
+
+ if (spi->mode& SPI_CPHA)
+ qspi->dc |= QSPI_CKPHA(spi->chip_select);
+ if (spi->mode& SPI_CPOL)
+ qspi->dc |= QSPI_CKPOL(spi->chip_select);
+ if (spi->mode& SPI_CS_HIGH)
+ qspi->dc |= QSPI_CSPOL(spi->chip_select);
+
+ frame_length = DIV_ROUND_UP(m->frame_length * spi->bits_per_word,
+ spi->bits_per_word);
this calculation doesn't look correct.
(m->frame_length * spi->bits_per_word) /
spi->bits_per_word = m->frame_length
What are you trying to achieve here ? frame_length should be counted in
words right ? And we get that value in bytes. So what's the best
calculation to convert bytes into words ? If you have 8 bits_per_word
you don't need any calculation, but if you have 32 bits_per_word, you
_do_ need something.
Yes, just derive this formulae with 8 bits per word in mind.
Will change.
It should be (m->frame_length * 8) / spi->bits_per_word
How will you achieve the number you want ? (hint: 1 byte == 8 bits)
And btw, all of these mistakes pretty much tell me that this driver
hasn't been tested. How have you tested this driver ?
After bootup, I checked for deive detting enumerated as /proc/mtd.
After which I am using mtdutils(erase, dump and write utilied to
check for the communication with the flash device.)
Is your spansion
memory accessed with 8 bits_per_word only ?
Yes, most of the places is like that and data is sapmled in 8 bits.
For some opcodes, we need to send 3 bytes addresses after instruction
to the flash chip.
Is there anyway to use
32 bits_per_word with that device ? That would uncover quite a few
mistakes in $subject.
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[RFC/PATCHv2 1/3] driver: spi: Modify core to compute the message length
Make spi core calculate the message length while
populating the other transfer parameters.
Usecase, driver can use it to populate framelength filed in their
controller.
Signed-off-by: Sourav Poddar
---
drivers/spi/spi.c |1 +
include/linux/spi/spi.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 32b7bb1..6a05b3c 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1375,6 +1375,7 @@ static int __spi_async(struct spi_device *spi, struct
spi_message *message)
* it is not set for this transfer.
*/
list_for_each_entry(xfer, >transfers, transfer_list) {
+ message->frame_length += xfer->len;
if (!xfer->bits_per_word)
xfer->bits_per_word = spi->bits_per_word;
if (!xfer->speed_hz)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6ff26c8..d83841e 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -575,6 +575,7 @@ struct spi_message {
/* completion is reported through a callback */
void(*complete)(void *context);
void*context;
+ unsignedframe_length;
unsignedactual_length;
int status;
--
1.7.1
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[RFC/PATCHv2 3/3] driver: spi: Add quad spi read support
Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following patch[1], which is just the
basic idea of adding dual/quad support in spi framework.
$subject patch will undergo changes as the parent patch goes[1]
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar
---
v1->v2
Added support for dual also.
drivers/spi/spi-ti-qspi.c | 17 +++--
1 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 3cae731..3a5c56d 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -86,6 +86,7 @@ struct ti_qspi {
#define QSPI_3_PIN (1 << 18)
#define QSPI_RD_SNGL (1 << 16)
#define QSPI_WR_SNGL (2 << 16)
+#defineQSPI_RD_DUAL(3 << 16)
#define QSPI_RD_QUAD (7 << 16)
#define QSPI_INVAL (4 << 16)
#define QSPI_WC_CMD_INT_EN (1 << 14)
@@ -280,6 +281,7 @@ static void qspi_read_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
{
u8 *rxbuf;
int wlen, count;
+ unsigned cmd = qspi->cmd;
count = t->len;
rxbuf = t->rx_buf;
@@ -289,8 +291,19 @@ static void qspi_read_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n",
qspi->cmd | QSPI_RD_SNGL, qspi->dc);
ti_qspi_writel(qspi, qspi->dc, QSPI_SPI_DC_REG);
- ti_qspi_writel(qspi, qspi->cmd | QSPI_RD_SNGL,
- QSPI_SPI_CMD_REG);
+ switch (t->bitwidth) {
+ case SPI_BITWIDTH_QUAD:
+ cmd |= QSPI_RD_QUAD;
+ break;
+ case SPI_BITWIDTH_DUAL:
+ cmd |= QSPI_RD_DUAL;
+ break;
+ case SPI_BITWIDTH_SINGLE:
+ default:
+ cmd |= QSPI_RD_SNGL;
+ }
+
+ ti_qspi_writel(qspi, cmd, QSPI_SPI_CMD_REG);
ti_qspi_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
wait_for_completion(>transfer_complete);
*rxbuf++ = ti_qspi_readl_data(qspi, QSPI_SPI_DATA_REG, wlen);
--
1.7.1
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[PATCHv4 2/3] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar
---
v3->v4
- Did miscellaneous cleanup
- Added power management support.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 +
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/spi-ti-qspi.c | 537 +
4 files changed, 568 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/spi-ti-qspi.c
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b/Documentation/devicetree/bindings/spi/ti_qspi.txt
new file mode 100644
index 000..398ef59
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -0,0 +1,22 @@
+TI QSPI controller.
+
+Required properties:
+- compatible : should be "ti,dra7xxx-qspi".
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+qspi: qspi@4b30 {
+ compatible = "ti,dra7xxx-qspi";
+ reg = <0x4b30 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <2500>;
+ ti,hwmods = "qspi";
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..e594fdb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,14 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate "DRA7xxx QSPI controller support"
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+ This device supports single, dual and quad read support, while
+ it only supports single write mode.
+
config SPI_OMAP_100K
tristate "OMAP SPI 100K"
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..b3b4857 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..3cae731
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
@@ -0,0 +1,537 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Sourav Poddar
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GPLv2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct ti_qspi_regs {
+ u32 clkctrl;
+};
+
+struct ti_qspi {
+ spinlock_t lock; /* IRQ synchronization */
+ struct spi_master *master;
+ void __iomem*base;
+ struct device *dev;
+ struct completion transfer_complete;
+ struct clk *fclk;
+ struct ti_qspi_regs ctx_reg;
+ int device_type;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define QSPI_SYSCONFIG (0x10)
+#define QSPI_INTR_STATUS_RAW_SET (0x20)
+#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
+#define QSPI_INTR_ENABLE_SET_REG (0x28)
+#define QSPI_INTR_ENABLE_CLEAR_REG (
[PATCH 0/3] spi changes and ti quad spi controller.
Add support for calculating message length in spi framework. Add support for quad spi controller. Patch 2 of this series had been posted before. Sending along with the series along with ather propsed change. Sourav Poddar (3): driver: spi: Modify core to compute the message length drivers: spi: Add qspi flash controller driver: spi: Add quad spi read support Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 + drivers/spi/Kconfig |8 + drivers/spi/Makefile |1 + drivers/spi/spi-ti-qspi.c | 550 + drivers/spi/spi.c |1 + include/linux/spi/spi.h |1 + 6 files changed, 583 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt create mode 100644 drivers/spi/spi-ti-qspi.c -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/3] spi changes and ti quad spi controller.
Add support for calculating message length in spi framework. Add support for quad spi controller. Patch 2 of this series had been posted before. Sending along with the series along with ather propsed change. Sourav Poddar (3): driver: spi: Modify core to compute the message length drivers: spi: Add qspi flash controller driver: spi: Add quad spi read support Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 + drivers/spi/Kconfig |8 + drivers/spi/Makefile |1 + drivers/spi/spi-ti-qspi.c | 550 + drivers/spi/spi.c |1 + include/linux/spi/spi.h |1 + 6 files changed, 583 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt create mode 100644 drivers/spi/spi-ti-qspi.c -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC/PATCHv2 3/3] driver: spi: Add quad spi read support
Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following patch[1], which is just the
basic idea of adding dual/quad support in spi framework.
$subject patch will undergo changes as the parent patch goes[1]
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2
Added support for dual also.
drivers/spi/spi-ti-qspi.c | 17 +++--
1 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 3cae731..3a5c56d 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -86,6 +86,7 @@ struct ti_qspi {
#define QSPI_3_PIN (1 18)
#define QSPI_RD_SNGL (1 16)
#define QSPI_WR_SNGL (2 16)
+#defineQSPI_RD_DUAL(3 16)
#define QSPI_RD_QUAD (7 16)
#define QSPI_INVAL (4 16)
#define QSPI_WC_CMD_INT_EN (1 14)
@@ -280,6 +281,7 @@ static void qspi_read_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
{
u8 *rxbuf;
int wlen, count;
+ unsigned cmd = qspi-cmd;
count = t-len;
rxbuf = t-rx_buf;
@@ -289,8 +291,19 @@ static void qspi_read_msg(struct ti_qspi *qspi, struct
spi_transfer *t)
dev_dbg(qspi-dev, rx cmd %08x dc %08x\n,
qspi-cmd | QSPI_RD_SNGL, qspi-dc);
ti_qspi_writel(qspi, qspi-dc, QSPI_SPI_DC_REG);
- ti_qspi_writel(qspi, qspi-cmd | QSPI_RD_SNGL,
- QSPI_SPI_CMD_REG);
+ switch (t-bitwidth) {
+ case SPI_BITWIDTH_QUAD:
+ cmd |= QSPI_RD_QUAD;
+ break;
+ case SPI_BITWIDTH_DUAL:
+ cmd |= QSPI_RD_DUAL;
+ break;
+ case SPI_BITWIDTH_SINGLE:
+ default:
+ cmd |= QSPI_RD_SNGL;
+ }
+
+ ti_qspi_writel(qspi, cmd, QSPI_SPI_CMD_REG);
ti_qspi_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
wait_for_completion(qspi-transfer_complete);
*rxbuf++ = ti_qspi_readl_data(qspi, QSPI_SPI_DATA_REG, wlen);
--
1.7.1
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[PATCHv4 2/3] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v3-v4
- Did miscellaneous cleanup
- Added power management support.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 +
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/spi-ti-qspi.c | 537 +
4 files changed, 568 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/spi-ti-qspi.c
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b/Documentation/devicetree/bindings/spi/ti_qspi.txt
new file mode 100644
index 000..398ef59
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -0,0 +1,22 @@
+TI QSPI controller.
+
+Required properties:
+- compatible : should be ti,dra7xxx-qspi.
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+qspi: qspi@4b30 {
+ compatible = ti,dra7xxx-qspi;
+ reg = 0x4b30 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+ spi-max-frequency = 2500;
+ ti,hwmods = qspi;
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..e594fdb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,14 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate DRA7xxx QSPI controller support
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+ This device supports single, dual and quad read support, while
+ it only supports single write mode.
+
config SPI_OMAP_100K
tristate OMAP SPI 100K
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..b3b4857 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..3cae731
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
@@ -0,0 +1,537 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Sourav Poddar sourav.pod...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GPLv2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/device.h
+#include linux/delay.h
+#include linux/dma-mapping.h
+#include linux/dmaengine.h
+#include linux/omap-dma.h
+#include linux/platform_device.h
+#include linux/err.h
+#include linux/clk.h
+#include linux/io.h
+#include linux/slab.h
+#include linux/pm_runtime.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/consumer.h
+
+#include linux/spi/spi.h
+
+struct ti_qspi_regs {
+ u32 clkctrl;
+};
+
+struct ti_qspi {
+ spinlock_t lock; /* IRQ synchronization */
+ struct spi_master *master;
+ void __iomem*base;
+ struct device *dev;
+ struct completion transfer_complete;
+ struct clk *fclk;
+ struct ti_qspi_regs ctx_reg;
+ int device_type;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define
[RFC/PATCHv2 1/3] driver: spi: Modify core to compute the message length
Make spi core calculate the message length while
populating the other transfer parameters.
Usecase, driver can use it to populate framelength filed in their
controller.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi.c |1 +
include/linux/spi/spi.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 32b7bb1..6a05b3c 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1375,6 +1375,7 @@ static int __spi_async(struct spi_device *spi, struct
spi_message *message)
* it is not set for this transfer.
*/
list_for_each_entry(xfer, message-transfers, transfer_list) {
+ message-frame_length += xfer-len;
if (!xfer-bits_per_word)
xfer-bits_per_word = spi-bits_per_word;
if (!xfer-speed_hz)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6ff26c8..d83841e 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -575,6 +575,7 @@ struct spi_message {
/* completion is reported through a callback */
void(*complete)(void *context);
void*context;
+ unsignedframe_length;
unsignedactual_length;
int status;
--
1.7.1
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
Hi Felipe,
On Thursday 18 July 2013 03:54 PM, Felipe Balbi wrote:
Hi,
it might be just me, but ...
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
+static inline unsigned long ti_qspi_readl_data(struct ti_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi-base + reg);
+ break;
+ case 16:
+ return readb(qspi-base + reg);
+ break;
+ case 32:
+ return readl(qspi-base + reg);
+ break;
+ default:
+ return -EINVAL;
+ }
+}
+
+static inline void ti_qspi_writel_data(struct ti_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ writew(val, qspi-base + reg);
+ break;
+ case 16:
+ writeb(val, qspi-base + reg);
+ break;
+ case 32:
+ writeb(val, qspi-base + reg);
+ break;
+ default:
+ dev_dbg(qspi-dev, word lenght out of range);
+ break;
+ }
+}
because of these two functions you have the hability to read/write
*more* than one byte, and yet ...
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf = t-tx_buf;
+ wlen = t-bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi-dev, tx cmd %08x dc %08x data %02x\n,
+ qspi-cmd | QSPI_WR_SNGL, qspi-dc, *txbuf);
+ ti_qspi_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
you always increment by each byte. Here, if you used writel(), you wrote
4 bytes and should increment txbuf by 4.
hmm..got this point. Yes, my mistake, here I agree if wlen is not 8 bits
txbuf++ is not valid.
Same goes for read_data(),
below. Another thing. Even though your wlen might be 8 bits, if you
write 4 bytes to write, you can save a few CPU cycles by using writel().
Do you mean 4 words of 8 bits?
You only use writew() if you have exactly 2 bytes to write and writeb()
if you have exactly 1 byte to write. 3 bytes we'll be left as an
exercise.
hmm..yes.
+static int ti_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m-spi;
+ struct spi_transfer *t;
+ int status = 0, ret;
+ int frame_length;
+
+ /* setup device control reg */
+ qspi-dc = 0;
+
+ if (spi-mode SPI_CPHA)
+ qspi-dc |= QSPI_CKPHA(spi-chip_select);
+ if (spi-mode SPI_CPOL)
+ qspi-dc |= QSPI_CKPOL(spi-chip_select);
+ if (spi-mode SPI_CS_HIGH)
+ qspi-dc |= QSPI_CSPOL(spi-chip_select);
+
+ frame_length = DIV_ROUND_UP(m-frame_length * spi-bits_per_word,
+ spi-bits_per_word);
this calculation doesn't look correct.
(m-frame_length * spi-bits_per_word) /
spi-bits_per_word = m-frame_length
What are you trying to achieve here ? frame_length should be counted in
words right ? And we get that value in bytes. So what's the best
calculation to convert bytes into words ? If you have 8 bits_per_word
you don't need any calculation, but if you have 32 bits_per_word, you
_do_ need something.
Yes, just derive this formulae with 8 bits per word in mind.
Will change.
It should be (m-frame_length * 8) / spi-bits_per_word
How will you achieve the number you want ? (hint: 1 byte == 8 bits)
And btw, all of these mistakes pretty much tell me that this driver
hasn't been tested. How have you tested this driver ?
After bootup, I checked for deive detting enumerated as /proc/mtd.
After which I am using mtdutils(erase, dump and write utilied to
check for the communication with the flash device.)
Is your spansion
memory accessed with 8 bits_per_word only ?
Yes, most of the places is like that and data is sapmled in 8 bits.
For some opcodes, we need to send 3 bytes addresses after instruction
to the flash chip.
Is there anyway to use
32 bits_per_word with that device ? That would uncover quite a few
mistakes in $subject.
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
On Thursday 18 July 2013 04:12 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
Have you seen the ongoing thread about SPI buses with extra data lines?
How does this driver fit in with that?
I have tried using it in my patch3 of this series..
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION) += spi-orion.o
obj-$(CONFIG_SPI_PL022) += spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
Please use SPI_ like the other drivers.
Ok.
+static int ti_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ int ret;
+
+ ret = pm_runtime_get_sync(qspi-dev);
+ if (ret 0) {
+ dev_err(qspi-dev, pm_runtime_get_sync() failed\n);
+ return ret;
+ }
+
+ return 0;
+}
This is a very common pattern, it should probably be factored out into
the core, probably not even as ops but rather as an actual feature.
May be yes.
+ list_for_each_entry(t,m-transfers, transfer_list) {
+ qspi-cmd |= QSPI_WLEN(t-bits_per_word);
+ qspi-cmd |= QSPI_WC_CMD_INT_EN;
+
+ ret = qspi_transfer_msg(qspi, t);
+ if (ret) {
+ dev_dbg(qspi-dev, transfer message failed\n);
+ return -EINVAL;
+ }
+
+ m-actual_length += t-len;
+
+ if (list_is_last(t-transfer_list,m-transfers))
+ goto out;
+ }
The use of list_is_last() here is *realy* strange - what's going on
there?
We are checking if there is any transfer left, if no we are signalling the
flash device about the end of transfer.
+static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
+{
+ struct ti_qspi *qspi = dev_id;
+ u16 mask, stat;
+
+ irqreturn_t ret = IRQ_HANDLED;
+
+ spin_lock(qspi-lock);
+
+ stat = ti_qspi_readl(qspi, QSPI_SPI_STATUS_REG);
+ mask = ti_qspi_readl(qspi, QSPI_INTR_ENABLE_SET_REG);
+
+ if (stat mask)
+ ret = IRQ_WAKE_THREAD;
+
+ spin_unlock(qspi-lock);
+
+ return ret;
According to the above code we might interrupt for masked events...
that's a bit worrying isn't it?
Yes, there is WC interrupt enable bit which enables the interrupt. This
interrupt
gets disabled by writing to the CLEAR reg in the threaded irq.
+ ret = devm_request_threaded_irq(pdev-dev, irq, ti_qspi_isr,
+ ti_qspi_threaded_isr, IRQF_NO_SUSPEND | IRQF_ONESHOT,
+ dev_name(pdev-dev), qspi);
+ if (ret 0) {
+ dev_err(pdev-dev, Failed to register ISR for IRQ %d\n,
+ irq);
+ goto free_master;
+ }
Standard question about devm_request_threaded_irq() - how can we be
certain it's safe to use during removal?
I am not sure about the exact flow. If we see the api description, it
says about irq getting
freed automatically.
Practically, I will check that on removing the driver, cat
/proc/interrupts should not show
the required interrupt getting registered.
Though, I see an api also existing devm_free_irq, which explicitly un
allocate your irq requested
through devm_* variants.
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Re: [RFC/PATCHv2 3/3] driver: spi: Add quad spi read support
On Thursday 18 July 2013 04:14 PM, Mark Brown wrote: On Thu, Jul 18, 2013 at 03:31:27PM +0530, Sourav Poddar wrote: Since, qspi controller uses quad read. Configuring the command register, if the transfer of data needs dual or quad lines. This patch has been done on top of the following patch[1], which is just the basic idea of adding dual/quad support in spi framework. $subject patch will undergo changes as the parent patch goes[1] [1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047 Just as with commit IDs you should include a plain text description of anything you link to so that people reading your e-mail can tell what you're talking about without going on line. Ok, will keep that in mind for future. Just to give you a brief description here, Requirement is to have a dual/quad support in spi frameowrk, so that drivers can use multiple lines for data transfers. What patch[1] tries to does, is [1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047 is to add to each transfer the bitwidth it supports, so that that bitwidth information can be parsed in controller driver and can be used for respective read/writes. A typical usecase on my side is, I have a spansion flash connected to qspi. Flash device supports quad read with a certain read opcode(QUAD_READ). So, Whenever the opcode send is QUAD_READ, we will append that information as a bitwidth to the spi transfer. This information will be parsed by the controller driver and will be used to configure the cmd reg to do the particular type of reads. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
On Thursday 18 July 2013 04:54 PM, Felipe Balbi wrote:
On Thu, Jul 18, 2013 at 04:48:41PM +0530, Sourav Poddar wrote:
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf = t-tx_buf;
+ wlen = t-bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi-dev, tx cmd %08x dc %08x data %02x\n,
+ qspi-cmd | QSPI_WR_SNGL, qspi-dc, *txbuf);
+ ti_qspi_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
you always increment by each byte. Here, if you used writel(), you wrote
4 bytes and should increment txbuf by 4.
hmm..got this point. Yes, my mistake, here I agree if wlen is not 8 bits
txbuf++ is not valid.
Same goes for read_data(),
below. Another thing. Even though your wlen might be 8 bits, if you
write 4 bytes to write, you can save a few CPU cycles by using writel().
Do you mean 4 words of 8 bits?
yeah. Say you have wlen = 8 but the transfer length is 8 bytes (64
bits). If you use writeb(), you will do 8 writes, if you use writel()
you'll do 2 writes.
hmm.. I will check this out.
If our wlen is 8, after every 8 bits there will be
an interrupt. Will check that out, how that interrupt
should be tackled if we desired to read 4 bytes in a single writel/readl.
+static int ti_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m-spi;
+ struct spi_transfer *t;
+ int status = 0, ret;
+ int frame_length;
+
+ /* setup device control reg */
+ qspi-dc = 0;
+
+ if (spi-mode SPI_CPHA)
+ qspi-dc |= QSPI_CKPHA(spi-chip_select);
+ if (spi-mode SPI_CPOL)
+ qspi-dc |= QSPI_CKPOL(spi-chip_select);
+ if (spi-mode SPI_CS_HIGH)
+ qspi-dc |= QSPI_CSPOL(spi-chip_select);
+
+ frame_length = DIV_ROUND_UP(m-frame_length * spi-bits_per_word,
+ spi-bits_per_word);
this calculation doesn't look correct.
(m-frame_length * spi-bits_per_word) /
spi-bits_per_word = m-frame_length
What are you trying to achieve here ? frame_length should be counted in
words right ? And we get that value in bytes. So what's the best
calculation to convert bytes into words ? If you have 8 bits_per_word
you don't need any calculation, but if you have 32 bits_per_word, you
_do_ need something.
Yes, just derive this formulae with 8 bits per word in mind.
Will change.
It should be (m-frame_length * 8) / spi-bits_per_word
right on. To make sure this will execute a little faster (you never know
what several different versions of GCC will do), instead of multiplying
by 8, left shift by 3.
Ok. Will do.
How will you achieve the number you want ? (hint: 1 byte == 8 bits)
And btw, all of these mistakes pretty much tell me that this driver
hasn't been tested. How have you tested this driver ?
After bootup, I checked for deive detting enumerated as /proc/mtd.
After which I am using mtdutils(erase, dump and write utilied to
check for the communication with the flash device.)
alright, make that clear in your commit log.
Ok.
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Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
Hi Mark, On Thursday 18 July 2013 08:12 PM, Mark Brown wrote: On Thu, Jul 18, 2013 at 04:31:58PM +0300, Felipe Balbi wrote: On Thu, Jul 18, 2013 at 02:18:22PM +0100, Mark Brown wrote: So why do we report that we handled the interrupt then? Shouldn't we at least warn if we're getting spurious IRQs? not spurious. OMAP has two sets of IRQ status registers. One is call IRQSTATUS$n (n = 0, 1, ...) and IRQSTATUS_RAW$n. IRQSTATUS$n will only enable the bits which fired IRQs and aren't masked while IRQSTATUS_RAW$n will also enable the bits which are masked. I could never come up with a use case where we would need to handle IRQs which we decided to mask, but perhaps there might be some cases, I don't know. Based on that, I believe Sourav is reading IRQSTATUS_RAW$n, then he need to clear the masked bits. That's not the issue - the issue is that if none of the unmasked interrupts are being asserted we shouldn't be in the interrupt handler in the first place but the driver silently accepts that and reports that it handled the interrupt. I believe this is what you hinted at doing.. there is a QSPI_INTR_STATUS_ENABLED_CLEAR register, which indicated the interrupt status. if nothing is set in the above register, I should return IRQ_NONE. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller
On Friday 19 July 2013 12:38 AM, Trent Piepho wrote:
On Thu, Jul 18, 2013 at 3:01 AM, Sourav Poddarsourav.pod...@ti.com wrote:
+Required properties:
+- compatible : should be ti,dra7xxx-qspi.
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
What is ti,hwmods? It's not clear from the description. It also
doesn't appear to be used in the driver. At least, I did not find any
occurrence of hwmods in the driver code.
+static inline unsigned long ti_qspi_readl_data(struct ti_qspi *qspi,
+ unsigned long reg, int wlen)
readl means read LONG. That's what the L is for. But this does
different widths.
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi-base + reg);
+ break;
wlen == 8, but readw == 16 bit read?
Yes, I need to change this. should be readb.
The break after the return isn't necessary.
+ case 16:
+ return readb(qspi-base + reg);
+ break;
wlen == 16, but readb == 8 bit read?
same here.
+ case 32:
+ return readl(qspi-base + reg);
wlen == 32, readl == 32, this one makes sense, but
+static inline void ti_qspi_writel_data(struct ti_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+ case 32:
+ writeb(val, qspi-base + reg);
+ break;
A 32 bit write uses an 8 bit write command, while read is 32 bits??
This doesn't make a lot of sense. If it's actually correct, there
should be come kind of comment about it.
Yes, I will change this in the next version.
+
+static int ti_qspi_setup(struct spi_device *spi)
+{
+
+ clk_ctrl_reg = ti_qspi_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ clk_ctrl_reg= ~QSPI_CLK_EN;
+
+ /* disable SCLK */
+ ti_qspi_writel(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
Did you read this from Documentation/spi/spi-summary?
** BUG ALERT: for some reason the first version of
** many spi_master drivers seems to get this wrong.
** When you code setup(), ASSUME that the controller
** is actively processing transfers for another device.
But I see in this documentation, that setup is usually used for setting up
device clock rate, modes etc.
So, what do you recommend here, should we move clk settings to prepare
hardware ?
+static int ti_qspi_probe(struct platform_device *pdev)
+{
+
+ master-mode_bits = SPI_CPOL | SPI_CPHA;
Does your device support full duplex? It doesn't look like it does.
You should set the SPI_MASER_HALF_DUPLEX flag in master-flags.
hmm. Ok, will add.
+
+ if (!of_property_read_u32(np, ti,spi-num-cs,num_cs))
+ master-num_chipselect = num_cs;
You didn't document this property. How is this different than the
num-cs property already documented in spi-bus bindings?
Actually, it is no different. This also means the total number of
chipselects.
I used it from omap mcspi. I will make this property in accordance with the
generic binding.
Will also send a seperate patch for omap mcspi.
+ qspi-base = devm_ioremap_resource(pdev-dev, r);
+ if (IS_ERR(qspi-base)) {
+ ret = -ENOMEM;
Shouldn't that be ret = PTR_ERR(qspi-base)
hmm.will change.
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Re: [PATCHv3 2/3] drivers: spi: Add qspi flash controller
On Monday 08 July 2013 08:02 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 08, 2013 at 07:12:59PM +0530, Sourav Poddar wrote:
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi->base + reg);
+}
+
+static inline void dra7xxx_writel(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg)
+{
+ writel(val, qspi->base + reg);
+}
+
+static inline unsigned long dra7xxx_readl_data(struct dra7xxx_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi->base + reg);
+ break;
+ case 16:
+ return readb(qspi->base + reg);
+ break;
+ case 32:
+ return readl(qspi->base + reg);
+ break;
+ default:
+ return -1;
return -EINVAL ? or some other error code ?
+ }
+}
+
+static inline void dra7xxx_writel_data(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ writew(val, qspi->base + reg);
+ break;
+ case 16:
+ writeb(val, qspi->base + reg);
+ break;
+ case 32:
+ writeb(val, qspi->base + reg);
+ break;
+ default:
+ dev_dbg(qspi->dev, "word lenght out of range");
+ break;
+ }
+}
+
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(spi->master);
+ int clk_div = 0;
+ u32 clk_ctrl_reg, clk_rate;
+
+ clk_rate = clk_get_rate(qspi->fclk);
+
+ if (!qspi->spi_max_frequency) {
+ dev_err(qspi->dev, "spi max frequency not defined\n");
+ return -1;
same here
+ } else
this needs to have curly braces too, per CodingStyle
+ clk_div = (clk_rate / qspi->spi_max_frequency) - 1;
+
+ dev_dbg(qspi->dev, "%s: hz: %d, clock divider %d\n", __func__,
+ qspi->spi_max_frequency, clk_div);
+
+ pm_runtime_get_sync(qspi->dev);
+
+ clk_ctrl_reg = dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ clk_ctrl_reg&= ~QSPI_CLK_EN;
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div< 0) {
+ dev_dbg(qspi->dev, "%s: clock divider< 0, using /1 divider\n",
+ __func__);
+ clk_div = 1;
+ }
+
+ if (clk_div> QSPI_CLK_DIV_MAX) {
+ dev_dbg(qspi->dev, "%s: clock divider>%d , using /%d divider\n",
+ __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
+ clk_div = QSPI_CLK_DIV_MAX;
+ }
+
+ /* enable SCLK */
+ dra7xxx_writel(qspi, QSPI_CLK_EN | clk_div, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ pm_runtime_mark_last_busy(qspi->dev);
+ pm_runtime_put_autosuspend(qspi->dev);
+
+ return 0;
+}
+
+static int dra7xxx_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(qspi->dev);
not going to check return value ?
+ return 0;
+}
+
+static int dra7xxx_qspi_unprepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_mark_last_busy(qspi->dev);
+ pm_runtime_put_autosuspend(qspi->dev);
what about on these two ?
Just realised this, pm_runtime_mark_last_busy does not need a check, it
returns nothing.
+ return 0;
+}
+
+static int qspi_write_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t->len;
+ txbuf = t->tx_buf;
+ wlen = t->bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
+ qspi->cmd | QSPI_WR_SNGL, qspi->dc, *txbuf);
+ dra7xxx_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
you should enable the interrupt as the last step. Also, why aren't you
using frame interrupt ?
+ dra7xxx_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
+ dra7xxx_writel(qspi, qspi->dc, QSPI_SPI_DC_REG);
+ dra7xxx_writel(qspi, qspi->cmd | QSPI_WR_SNGL,
+ QSPI_SPI_CMD_REG);
+ wait_for_completion(>word_complete);
+ }
+
+ return 0;
+}
+
+static int qspi_read_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ u8 *rxbuf;
+ int wlen, count;
+
+ count = t->len;
+ rxbuf = t->rx_buf;
+ wlen = t->bits_per_word;
Re: [PATCHv3 2/3] drivers: spi: Add qspi flash controller
On Monday 08 July 2013 08:02 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 08, 2013 at 07:12:59PM +0530, Sourav Poddar wrote:
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi-base + reg);
+}
+
+static inline void dra7xxx_writel(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg)
+{
+ writel(val, qspi-base + reg);
+}
+
+static inline unsigned long dra7xxx_readl_data(struct dra7xxx_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi-base + reg);
+ break;
+ case 16:
+ return readb(qspi-base + reg);
+ break;
+ case 32:
+ return readl(qspi-base + reg);
+ break;
+ default:
+ return -1;
return -EINVAL ? or some other error code ?
+ }
+}
+
+static inline void dra7xxx_writel_data(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ writew(val, qspi-base + reg);
+ break;
+ case 16:
+ writeb(val, qspi-base + reg);
+ break;
+ case 32:
+ writeb(val, qspi-base + reg);
+ break;
+ default:
+ dev_dbg(qspi-dev, word lenght out of range);
+ break;
+ }
+}
+
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(spi-master);
+ int clk_div = 0;
+ u32 clk_ctrl_reg, clk_rate;
+
+ clk_rate = clk_get_rate(qspi-fclk);
+
+ if (!qspi-spi_max_frequency) {
+ dev_err(qspi-dev, spi max frequency not defined\n);
+ return -1;
same here
+ } else
this needs to have curly braces too, per CodingStyle
+ clk_div = (clk_rate / qspi-spi_max_frequency) - 1;
+
+ dev_dbg(qspi-dev, %s: hz: %d, clock divider %d\n, __func__,
+ qspi-spi_max_frequency, clk_div);
+
+ pm_runtime_get_sync(qspi-dev);
+
+ clk_ctrl_reg = dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ clk_ctrl_reg= ~QSPI_CLK_EN;
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div 0) {
+ dev_dbg(qspi-dev, %s: clock divider 0, using /1 divider\n,
+ __func__);
+ clk_div = 1;
+ }
+
+ if (clk_div QSPI_CLK_DIV_MAX) {
+ dev_dbg(qspi-dev, %s: clock divider%d , using /%d divider\n,
+ __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
+ clk_div = QSPI_CLK_DIV_MAX;
+ }
+
+ /* enable SCLK */
+ dra7xxx_writel(qspi, QSPI_CLK_EN | clk_div, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ pm_runtime_mark_last_busy(qspi-dev);
+ pm_runtime_put_autosuspend(qspi-dev);
+
+ return 0;
+}
+
+static int dra7xxx_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(qspi-dev);
not going to check return value ?
+ return 0;
+}
+
+static int dra7xxx_qspi_unprepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_mark_last_busy(qspi-dev);
+ pm_runtime_put_autosuspend(qspi-dev);
what about on these two ?
Just realised this, pm_runtime_mark_last_busy does not need a check, it
returns nothing.
+ return 0;
+}
+
+static int qspi_write_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf = t-tx_buf;
+ wlen = t-bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi-dev, tx cmd %08x dc %08x data %02x\n,
+ qspi-cmd | QSPI_WR_SNGL, qspi-dc, *txbuf);
+ dra7xxx_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
you should enable the interrupt as the last step. Also, why aren't you
using frame interrupt ?
+ dra7xxx_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
+ dra7xxx_writel(qspi, qspi-dc, QSPI_SPI_DC_REG);
+ dra7xxx_writel(qspi, qspi-cmd | QSPI_WR_SNGL,
+ QSPI_SPI_CMD_REG);
+ wait_for_completion(qspi-word_complete);
+ }
+
+ return 0;
+}
+
+static int qspi_read_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ u8 *rxbuf;
+ int wlen, count;
+
+ count = t-len;
+ rxbuf = t-rx_buf;
+ wlen = t-bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi-dev, rx cmd %08x dc %08x\n,
+ qspi-cmd | QSPI_RD_SNGL, qspi-dc);
+ dra7xxx_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
ditto
Re: [PATCHv3 2/3] drivers: spi: Add qspi flash controller
On Monday 08 July 2013 08:02 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 08, 2013 at 07:12:59PM +0530, Sourav Poddar wrote:
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi->base + reg);
+}
+
+static inline void dra7xxx_writel(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg)
+{
+ writel(val, qspi->base + reg);
+}
+
+static inline unsigned long dra7xxx_readl_data(struct dra7xxx_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi->base + reg);
+ break;
+ case 16:
+ return readb(qspi->base + reg);
+ break;
+ case 32:
+ return readl(qspi->base + reg);
+ break;
+ default:
+ return -1;
return -EINVAL ? or some other error code ?
Ok.will change.
+ }
+}
+
+static inline void dra7xxx_writel_data(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ writew(val, qspi->base + reg);
+ break;
+ case 16:
+ writeb(val, qspi->base + reg);
+ break;
+ case 32:
+ writeb(val, qspi->base + reg);
+ break;
+ default:
+ dev_dbg(qspi->dev, "word lenght out of range");
+ break;
+ }
+}
+
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(spi->master);
+ int clk_div = 0;
+ u32 clk_ctrl_reg, clk_rate;
+
+ clk_rate = clk_get_rate(qspi->fclk);
+
+ if (!qspi->spi_max_frequency) {
+ dev_err(qspi->dev, "spi max frequency not defined\n");
+ return -1;
same here
Ok.
+ } else
this needs to have curly braces too, per CodingStyle
hmm..will change.
+ clk_div = (clk_rate / qspi->spi_max_frequency) - 1;
+
+ dev_dbg(qspi->dev, "%s: hz: %d, clock divider %d\n", __func__,
+ qspi->spi_max_frequency, clk_div);
+
+ pm_runtime_get_sync(qspi->dev);
+
+ clk_ctrl_reg = dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ clk_ctrl_reg&= ~QSPI_CLK_EN;
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div< 0) {
+ dev_dbg(qspi->dev, "%s: clock divider< 0, using /1 divider\n",
+ __func__);
+ clk_div = 1;
+ }
+
+ if (clk_div> QSPI_CLK_DIV_MAX) {
+ dev_dbg(qspi->dev, "%s: clock divider>%d , using /%d divider\n",
+ __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
+ clk_div = QSPI_CLK_DIV_MAX;
+ }
+
+ /* enable SCLK */
+ dra7xxx_writel(qspi, QSPI_CLK_EN | clk_div, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ pm_runtime_mark_last_busy(qspi->dev);
+ pm_runtime_put_autosuspend(qspi->dev);
+
+ return 0;
+}
+
+static int dra7xxx_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(qspi->dev);
not going to check return value ?
Will add.
+ return 0;
+}
+
+static int dra7xxx_qspi_unprepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_mark_last_busy(qspi->dev);
+ pm_runtime_put_autosuspend(qspi->dev);
what about on these two ?
Yes, will add error checking.
+ return 0;
+}
+
+static int qspi_write_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t->len;
+ txbuf = t->tx_buf;
+ wlen = t->bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
+ qspi->cmd | QSPI_WR_SNGL, qspi->dc, *txbuf);
+ dra7xxx_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
you should enable the interrupt as the last step. Also, why aren't you
using frame interrupt ?
+ dra7xxx_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
+ dra7xxx_writel(qspi, qspi->dc, QSPI_SPI_DC_REG);
+ dra7xxx_writel(qspi, qspi->cmd | QSPI_WR_SNGL,
+ QSPI_SPI_CMD_REG);
+ wait_for_completion(>word_complete);
+ }
+
+ return 0;
+}
+
+static int qspi_read_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ u8 *rxbuf;
+ int wlen, count;
+
+ count = t->len;
+ rxbuf = t->rx_buf;
+ wlen = t->bits_per_word;
Re: [PATCHv3 2/3] drivers: spi: Add qspi flash controller
On Tuesday 09 July 2013 02:03 AM, Nishanth Menon wrote:
On 19:12-20130708, Sourav Poddar wrote:
[..]
generic comment, given our historical mistakes of making drivers
specific to a SoC family, it never is.
Now, ti-qspi in file name is a step in the right direction, but, rest
of the code(function names etc) is just married to DRA7 family of
processor, when it should not be.
Make sense. Will change apis accordingly.
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..430de9c
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
[...]
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi->base + reg);
+}
+
+static inline void dra7xxx_writel(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg)
+{
+ writel(val, qspi->base + reg);
+}
+
+static inline unsigned long dra7xxx_readl_data(struct dra7xxx_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi->base + reg);
+ break;
+ case 16:
+ return readb(qspi->base + reg);
+ break;
+ case 32:
+ return readl(qspi->base + reg);
+ break;
+ default:
+ return -1;
+ }
+}
+
+static inline void dra7xxx_writel_data(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ writew(val, qspi->base + reg);
+ break;
+ case 16:
+ writeb(val, qspi->base + reg);
+ break;
+ case 32:
+ writeb(val, qspi->base + reg);
+ break;
+ default:
+ dev_dbg(qspi->dev, "word lenght out of range");
+ break;
+ }
+}
Looks like a case to use regmap?
Dumb q: why cant we use regmap_spi? worst case, you should be able to
use mmio if regmap_spi cant be used. The commit message was not clear
about this.
MMIO can be used as this controller supports memory mapped port, but that
will be addition/enhancement on top of this.
This driver is adding qspi controller read/write support in SPI mode.
+
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(spi->master);
+ int clk_div = 0;
+ u32 clk_ctrl_reg, clk_rate;
+
+ clk_rate = clk_get_rate(qspi->fclk);
+
+ if (!qspi->spi_max_frequency) {
+ dev_err(qspi->dev, "spi max frequency not defined\n");
+ return -1;
+ } else
+ clk_div = (clk_rate / qspi->spi_max_frequency) - 1;
did you run checkpatch --strict here?
Didn,t do the strict, yes will add braces.
Also, would you prefer to use DIV_ROUND_UP?
Ok.
+
+ dev_dbg(qspi->dev, "%s: hz: %d, clock divider %d\n", __func__,
+ qspi->spi_max_frequency, clk_div);
+
+ pm_runtime_get_sync(qspi->dev);
error check?
Will add.
+
+ clk_ctrl_reg = dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ clk_ctrl_reg&= ~QSPI_CLK_EN;
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div< 0) {
+ dev_dbg(qspi->dev, "%s: clock divider< 0, using /1 divider\n",
+ __func__);
+ clk_div = 1;
should you not fail here?
May be yes.
+ }
+
+ if (clk_div> QSPI_CLK_DIV_MAX) {
+ dev_dbg(qspi->dev, "%s: clock divider>%d , using /%d divider\n",
+ __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
+ clk_div = QSPI_CLK_DIV_MAX;
should you not fail here?
Yup.
+ }
+
+ /* enable SCLK */
+ dra7xxx_writel(qspi, QSPI_CLK_EN | clk_div, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ pm_runtime_mark_last_busy(qspi->dev);
+ pm_runtime_put_autosuspend(qspi->dev);
error check?
Will add.
+
+ return 0;
+}
+
+static int dra7xxx_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(qspi->dev);
error check?
Will add.
+
+ return 0;
+}
+
+static int dra7xxx_qspi_unprepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_mark_last_busy(qspi->dev);
+ pm_runtime_put_autosuspend(qspi->dev);
error check?
Will add.
+
+ return 0;
+}
+
+static int qspi_write_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t->len;
+ txbuf = t->tx_buf;
+ wlen = t->bits_per_word;
+
+ while (
Re: [PATCHv3 2/3] drivers: spi: Add qspi flash controller
On Tuesday 09 July 2013 02:03 AM, Nishanth Menon wrote:
On 19:12-20130708, Sourav Poddar wrote:
[..]
generic comment, given our historical mistakes of making drivers
specific to a SoC family, it never is.
Now, ti-qspi in file name is a step in the right direction, but, rest
of the code(function names etc) is just married to DRA7 family of
processor, when it should not be.
Make sense. Will change apis accordingly.
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..430de9c
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
[...]
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi-base + reg);
+}
+
+static inline void dra7xxx_writel(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg)
+{
+ writel(val, qspi-base + reg);
+}
+
+static inline unsigned long dra7xxx_readl_data(struct dra7xxx_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi-base + reg);
+ break;
+ case 16:
+ return readb(qspi-base + reg);
+ break;
+ case 32:
+ return readl(qspi-base + reg);
+ break;
+ default:
+ return -1;
+ }
+}
+
+static inline void dra7xxx_writel_data(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ writew(val, qspi-base + reg);
+ break;
+ case 16:
+ writeb(val, qspi-base + reg);
+ break;
+ case 32:
+ writeb(val, qspi-base + reg);
+ break;
+ default:
+ dev_dbg(qspi-dev, word lenght out of range);
+ break;
+ }
+}
Looks like a case to use regmap?
Dumb q: why cant we use regmap_spi? worst case, you should be able to
use mmio if regmap_spi cant be used. The commit message was not clear
about this.
MMIO can be used as this controller supports memory mapped port, but that
will be addition/enhancement on top of this.
This driver is adding qspi controller read/write support in SPI mode.
+
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(spi-master);
+ int clk_div = 0;
+ u32 clk_ctrl_reg, clk_rate;
+
+ clk_rate = clk_get_rate(qspi-fclk);
+
+ if (!qspi-spi_max_frequency) {
+ dev_err(qspi-dev, spi max frequency not defined\n);
+ return -1;
+ } else
+ clk_div = (clk_rate / qspi-spi_max_frequency) - 1;
did you run checkpatch --strict here?
Didn,t do the strict, yes will add braces.
Also, would you prefer to use DIV_ROUND_UP?
Ok.
+
+ dev_dbg(qspi-dev, %s: hz: %d, clock divider %d\n, __func__,
+ qspi-spi_max_frequency, clk_div);
+
+ pm_runtime_get_sync(qspi-dev);
error check?
Will add.
+
+ clk_ctrl_reg = dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ clk_ctrl_reg= ~QSPI_CLK_EN;
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div 0) {
+ dev_dbg(qspi-dev, %s: clock divider 0, using /1 divider\n,
+ __func__);
+ clk_div = 1;
should you not fail here?
May be yes.
+ }
+
+ if (clk_div QSPI_CLK_DIV_MAX) {
+ dev_dbg(qspi-dev, %s: clock divider%d , using /%d divider\n,
+ __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
+ clk_div = QSPI_CLK_DIV_MAX;
should you not fail here?
Yup.
+ }
+
+ /* enable SCLK */
+ dra7xxx_writel(qspi, QSPI_CLK_EN | clk_div, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ pm_runtime_mark_last_busy(qspi-dev);
+ pm_runtime_put_autosuspend(qspi-dev);
error check?
Will add.
+
+ return 0;
+}
+
+static int dra7xxx_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(qspi-dev);
error check?
Will add.
+
+ return 0;
+}
+
+static int dra7xxx_qspi_unprepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_mark_last_busy(qspi-dev);
+ pm_runtime_put_autosuspend(qspi-dev);
error check?
Will add.
+
+ return 0;
+}
+
+static int qspi_write_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf = t-tx_buf;
+ wlen = t-bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi-dev, tx cmd %08x dc %08x data %02x\n,
+ qspi-cmd | QSPI_WR_SNGL, qspi-dc, *txbuf);
+ dra7xxx_writel(qspi, QSPI_WC_INT_EN
Re: [PATCHv3 2/3] drivers: spi: Add qspi flash controller
On Monday 08 July 2013 08:02 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 08, 2013 at 07:12:59PM +0530, Sourav Poddar wrote:
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi-base + reg);
+}
+
+static inline void dra7xxx_writel(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg)
+{
+ writel(val, qspi-base + reg);
+}
+
+static inline unsigned long dra7xxx_readl_data(struct dra7xxx_qspi *qspi,
+ unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ return readw(qspi-base + reg);
+ break;
+ case 16:
+ return readb(qspi-base + reg);
+ break;
+ case 32:
+ return readl(qspi-base + reg);
+ break;
+ default:
+ return -1;
return -EINVAL ? or some other error code ?
Ok.will change.
+ }
+}
+
+static inline void dra7xxx_writel_data(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg, int wlen)
+{
+ switch (wlen) {
+ case 8:
+ writew(val, qspi-base + reg);
+ break;
+ case 16:
+ writeb(val, qspi-base + reg);
+ break;
+ case 32:
+ writeb(val, qspi-base + reg);
+ break;
+ default:
+ dev_dbg(qspi-dev, word lenght out of range);
+ break;
+ }
+}
+
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(spi-master);
+ int clk_div = 0;
+ u32 clk_ctrl_reg, clk_rate;
+
+ clk_rate = clk_get_rate(qspi-fclk);
+
+ if (!qspi-spi_max_frequency) {
+ dev_err(qspi-dev, spi max frequency not defined\n);
+ return -1;
same here
Ok.
+ } else
this needs to have curly braces too, per CodingStyle
hmm..will change.
+ clk_div = (clk_rate / qspi-spi_max_frequency) - 1;
+
+ dev_dbg(qspi-dev, %s: hz: %d, clock divider %d\n, __func__,
+ qspi-spi_max_frequency, clk_div);
+
+ pm_runtime_get_sync(qspi-dev);
+
+ clk_ctrl_reg = dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ clk_ctrl_reg= ~QSPI_CLK_EN;
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div 0) {
+ dev_dbg(qspi-dev, %s: clock divider 0, using /1 divider\n,
+ __func__);
+ clk_div = 1;
+ }
+
+ if (clk_div QSPI_CLK_DIV_MAX) {
+ dev_dbg(qspi-dev, %s: clock divider%d , using /%d divider\n,
+ __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
+ clk_div = QSPI_CLK_DIV_MAX;
+ }
+
+ /* enable SCLK */
+ dra7xxx_writel(qspi, QSPI_CLK_EN | clk_div, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ pm_runtime_mark_last_busy(qspi-dev);
+ pm_runtime_put_autosuspend(qspi-dev);
+
+ return 0;
+}
+
+static int dra7xxx_qspi_prepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(qspi-dev);
not going to check return value ?
Will add.
+ return 0;
+}
+
+static int dra7xxx_qspi_unprepare_xfer(struct spi_master *master)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_mark_last_busy(qspi-dev);
+ pm_runtime_put_autosuspend(qspi-dev);
what about on these two ?
Yes, will add error checking.
+ return 0;
+}
+
+static int qspi_write_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf = t-tx_buf;
+ wlen = t-bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi-dev, tx cmd %08x dc %08x data %02x\n,
+ qspi-cmd | QSPI_WR_SNGL, qspi-dc, *txbuf);
+ dra7xxx_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
you should enable the interrupt as the last step. Also, why aren't you
using frame interrupt ?
+ dra7xxx_writel_data(qspi, *txbuf++, QSPI_SPI_DATA_REG, wlen);
+ dra7xxx_writel(qspi, qspi-dc, QSPI_SPI_DC_REG);
+ dra7xxx_writel(qspi, qspi-cmd | QSPI_WR_SNGL,
+ QSPI_SPI_CMD_REG);
+ wait_for_completion(qspi-word_complete);
+ }
+
+ return 0;
+}
+
+static int qspi_read_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t)
+{
+ u8 *rxbuf;
+ int wlen, count;
+
+ count = t-len;
+ rxbuf = t-rx_buf;
+ wlen = t-bits_per_word;
+
+ while (count--) {
+ dev_dbg(qspi-dev, rx cmd %08x dc %08x\n,
+ qspi-cmd | QSPI_RD_SNGL, qspi-dc);
+ dra7xxx_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
ditto
hmm. will move
[RFC/PATCH 3/3] driver: spi: Add quad spi read support
Since, qspi controller uses quad read. Configuring the command register, if the transfer of data needs quad lines. This patch has been done on top of the following patch[1], which is still under review/comments. This patch will also go changes, as the parent patch[1] does. [1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047 Signed-off-by: Sourav Poddar --- drivers/spi/spi-ti-qspi.c |8 ++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 430de9c..307cbed 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -258,8 +258,12 @@ static int qspi_read_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t) qspi->cmd | QSPI_RD_SNGL, qspi->dc); dra7xxx_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG); dra7xxx_writel(qspi, qspi->dc, QSPI_SPI_DC_REG); - dra7xxx_writel(qspi, qspi->cmd | QSPI_RD_SNGL, - QSPI_SPI_CMD_REG); + if (t->bitwidth == SPI_BITWIDTH_QUAD) + dra7xxx_writel(qspi, qspi->cmd | QSPI_RD_QUAD, + QSPI_SPI_CMD_REG); + else + dra7xxx_writel(qspi, qspi->cmd | QSPI_RD_SNGL, + QSPI_SPI_CMD_REG); wait_for_completion(>word_complete); *rxbuf++ = dra7xxx_readl_data(qspi, QSPI_SPI_DATA_REG, wlen); dev_dbg(qspi->dev, "rx done, read %02x\n", *(rxbuf-1)); -- 1.7.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCHv3 2/3] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar
---
v2->v3
1. Add threaded irq support
2. made the driver more generic in terms of chip select, bits_per_word etc.
3. Made it more modular by sepoerating tx/rx function.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 +
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/spi-ti-qspi.c | 485 +
4 files changed, 516 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/spi-ti-qspi.c
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b/Documentation/devicetree/bindings/spi/ti_qspi.txt
new file mode 100644
index 000..398ef59
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -0,0 +1,22 @@
+TI QSPI controller.
+
+Required properties:
+- compatible : should be "ti,dra7xxx-qspi".
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+qspi: qspi@4b30 {
+ compatible = "ti,dra7xxx-qspi";
+ reg = <0x4b30 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <2500>;
+ ti,hwmods = "qspi";
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..e594fdb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,14 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate "DRA7xxx QSPI controller support"
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+ This device supports single, dual and quad read support, while
+ it only supports single write mode.
+
config SPI_OMAP_100K
tristate "OMAP SPI 100K"
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..b3b4857 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..430de9c
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
@@ -0,0 +1,485 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Sourav Poddar
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GPLv2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct dra7xxx_qspi {
+ spinlock_t lock; /* IRQ synchronization */
+ struct spi_master *master;
+ void __iomem*base;
+ struct device *dev;
+ struct completion word_complete;
+ struct clk *fclk;
+ int device_type;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define QSPI_SYSCONFIG (0x10)
+#define QSPI_INTR_STATUS_RAW_SET (0x20)
+#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
+#define QSPI_INTR_ENABLE_SET_REG (0x28)
+#define QSPI_INTR_ENABLE_CLEAR_REG (
[RFC/PATCH 1/3] driver: spi: Modify core to compute the message length
Make spi core calculate the message length while
populating the other transfer parameters. This will
be useful in cases where controller driver need to configure its
framelength field without iterating through the linklist again in the
driver controller.
Signed-off-by: Sourav Poddar
---
drivers/spi/spi.c |1 +
include/linux/spi/spi.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 32b7bb1..6a05b3c 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1375,6 +1375,7 @@ static int __spi_async(struct spi_device *spi, struct
spi_message *message)
* it is not set for this transfer.
*/
list_for_each_entry(xfer, >transfers, transfer_list) {
+ message->frame_length += xfer->len;
if (!xfer->bits_per_word)
xfer->bits_per_word = spi->bits_per_word;
if (!xfer->speed_hz)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6ff26c8..d83841e 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -575,6 +575,7 @@ struct spi_message {
/* completion is reported through a callback */
void(*complete)(void *context);
void*context;
+ unsignedframe_length;
unsignedactual_length;
int status;
--
1.7.1
--
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[PATCH 0/3] spi changes and ti quad spi controller.
Add support for calculating message length in spi framework. Add support for quad spi controller. Patch 2 of this series had been posted before. Sending along with the series along with ather propsed change. Sourav Poddar (3): driver: spi: Modify core to compute the message length drivers: spi: Add qspi flash controller driver: spi: Add quad spi read support Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 + drivers/spi/Kconfig |8 + drivers/spi/Makefile |1 + drivers/spi/spi-ti-qspi.c | 489 + drivers/spi/spi.c |1 + include/linux/spi/spi.h |1 + 6 files changed, 522 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt create mode 100644 drivers/spi/spi-ti-qspi.c -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/3] spi changes and ti quad spi controller.
Add support for calculating message length in spi framework. Add support for quad spi controller. Patch 2 of this series had been posted before. Sending along with the series along with ather propsed change. Sourav Poddar (3): driver: spi: Modify core to compute the message length drivers: spi: Add qspi flash controller driver: spi: Add quad spi read support Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 + drivers/spi/Kconfig |8 + drivers/spi/Makefile |1 + drivers/spi/spi-ti-qspi.c | 489 + drivers/spi/spi.c |1 + include/linux/spi/spi.h |1 + 6 files changed, 522 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt create mode 100644 drivers/spi/spi-ti-qspi.c -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC/PATCH 1/3] driver: spi: Modify core to compute the message length
Make spi core calculate the message length while
populating the other transfer parameters. This will
be useful in cases where controller driver need to configure its
framelength field without iterating through the linklist again in the
driver controller.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi.c |1 +
include/linux/spi/spi.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 32b7bb1..6a05b3c 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1375,6 +1375,7 @@ static int __spi_async(struct spi_device *spi, struct
spi_message *message)
* it is not set for this transfer.
*/
list_for_each_entry(xfer, message-transfers, transfer_list) {
+ message-frame_length += xfer-len;
if (!xfer-bits_per_word)
xfer-bits_per_word = spi-bits_per_word;
if (!xfer-speed_hz)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6ff26c8..d83841e 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -575,6 +575,7 @@ struct spi_message {
/* completion is reported through a callback */
void(*complete)(void *context);
void*context;
+ unsignedframe_length;
unsignedactual_length;
int status;
--
1.7.1
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCHv3 2/3] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v2-v3
1. Add threaded irq support
2. made the driver more generic in terms of chip select, bits_per_word etc.
3. Made it more modular by sepoerating tx/rx function.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 +
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/spi-ti-qspi.c | 485 +
4 files changed, 516 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/spi-ti-qspi.c
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b/Documentation/devicetree/bindings/spi/ti_qspi.txt
new file mode 100644
index 000..398ef59
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -0,0 +1,22 @@
+TI QSPI controller.
+
+Required properties:
+- compatible : should be ti,dra7xxx-qspi.
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+qspi: qspi@4b30 {
+ compatible = ti,dra7xxx-qspi;
+ reg = 0x4b30 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+ spi-max-frequency = 2500;
+ ti,hwmods = qspi;
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..e594fdb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,14 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate DRA7xxx QSPI controller support
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+ This device supports single, dual and quad read support, while
+ it only supports single write mode.
+
config SPI_OMAP_100K
tristate OMAP SPI 100K
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..b3b4857 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += spi-ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..430de9c
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
@@ -0,0 +1,485 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Sourav Poddar sourav.pod...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GPLv2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/device.h
+#include linux/delay.h
+#include linux/dma-mapping.h
+#include linux/dmaengine.h
+#include linux/omap-dma.h
+#include linux/platform_device.h
+#include linux/err.h
+#include linux/clk.h
+#include linux/io.h
+#include linux/slab.h
+#include linux/pm_runtime.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/consumer.h
+
+#include linux/spi/spi.h
+
+struct dra7xxx_qspi {
+ spinlock_t lock; /* IRQ synchronization */
+ struct spi_master *master;
+ void __iomem*base;
+ struct device *dev;
+ struct completion word_complete;
+ struct clk *fclk;
+ int device_type;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0
[RFC/PATCH 3/3] driver: spi: Add quad spi read support
Since, qspi controller uses quad read. Configuring the command register, if the transfer of data needs quad lines. This patch has been done on top of the following patch[1], which is still under review/comments. This patch will also go changes, as the parent patch[1] does. [1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047 Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- drivers/spi/spi-ti-qspi.c |8 ++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 430de9c..307cbed 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -258,8 +258,12 @@ static int qspi_read_msg(struct dra7xxx_qspi *qspi, struct spi_transfer *t) qspi-cmd | QSPI_RD_SNGL, qspi-dc); dra7xxx_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG); dra7xxx_writel(qspi, qspi-dc, QSPI_SPI_DC_REG); - dra7xxx_writel(qspi, qspi-cmd | QSPI_RD_SNGL, - QSPI_SPI_CMD_REG); + if (t-bitwidth == SPI_BITWIDTH_QUAD) + dra7xxx_writel(qspi, qspi-cmd | QSPI_RD_QUAD, + QSPI_SPI_CMD_REG); + else + dra7xxx_writel(qspi, qspi-cmd | QSPI_RD_SNGL, + QSPI_SPI_CMD_REG); wait_for_completion(qspi-word_complete); *rxbuf++ = dra7xxx_readl_data(qspi, QSPI_SPI_DATA_REG, wlen); dev_dbg(qspi-dev, rx done, read %02x\n, *(rxbuf-1)); -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCHv2] drivers: mtd: spinand: Add generic spinand frameowrk.
Hi,
On Wednesday 03 July 2013 10:47 PM, Florian Fainelli wrote:
Hello,
2013/7/3 Sourav Poddar:
From: Mona Anonuevo
This patch adds support for a generic spinand framework(spinand_mtd.c).
This frameowrk can be used for other spi based flash devices. The idea
is to have a common model under drivers/mtd, as also present for other non spi
devices(there is a generic framework and device part simply attaches itself to
it.)
Resending my comments since your previous submissino
Signed-off-by: Mona Anonuevo
Signed-off-by: Tuan Nguyen
Signed-off-by: Sourav Poddar
[snip]
+if MTD_SPINAND
+
+config MTD_SPINAND_ONDIEECC
+ bool "Use SPINAND internal ECC"
+ help
+Internel ECC
+
+config MTD_SPINAND_SWECC
+ bool "Use software ECC"
+ depends on MTD_NAND
+ help
+software ECC
Can this somehow be made a runtime thing?
Ahh..I think we might opt for a device tree entry and based on that
check for ECC.
[snip]
+ if (count< oob_num&& ops->oobbuf&& chip->oobbuf) {
+ int size;
+ int offset, len, temp;
+
+ /* repack spare to oob */
+ memset(chip->oobbuf, 0, info->ecclayout->oobavail);
+
+ temp = 0;
+ offset = info->ecclayout->oobfree[0].offset;
+ len = info->ecclayout->oobfree[0].length;
+ memcpy(chip->oobbuf + temp,
+ chip->buf + info->page_main_size + offset, len);
Sounds like a for look might be useful here
I dont think so, there is a while loop above under which it happens.
We are increasing count at the bottom of the while loop. So, I think
this should work fine.
+
+ temp += len;
+ offset = info->ecclayout->oobfree[1].offset;
+ len = info->ecclayout->oobfree[1].length;
+ memcpy(chip->oobbuf + temp,
+ chip->buf + info->page_main_size + offset, len);
+
+ temp += len;
+ offset = info->ecclayout->oobfree[2].offset;
+ len = info->ecclayout->oobfree[2].length;
+ memcpy(chip->oobbuf + temp,
+ chip->buf + info->page_main_size + offset, len);
+
+ temp += len;
+ offset = info->ecclayout->oobfree[3].offset;
+ len = info->ecclayout->oobfree[3].length;
+ memcpy(chip->oobbuf + temp,
+ chip->buf + info->page_main_size + offset, len);
+
[snip]
+ /* repack oob to spare */
+ temp = 0;
+ offset = info->ecclayout->oobfree[0].offset;
+ len = info->ecclayout->oobfree[0].length;
+ memcpy(chip->buf + info->page_main_size + offset,
+ chip->oobbuf + temp, len);
And here too.
Same as above.
+
+ temp += len;
+ offset = info->ecclayout->oobfree[1].offset;
+ len = info->ecclayout->oobfree[1].length;
+ memcpy(chip->buf + info->page_main_size + offset,
+ chip->oobbuf + temp, len);
+
+ temp += len;
+ offset = info->ecclayout->oobfree[2].offset;
+ len = info->ecclayout->oobfree[2].length;
+ memcpy(chip->buf + info->page_main_size + offset,
+ chip->oobbuf + temp, len);
+
+ temp += len;
+ offset = info->ecclayout->oobfree[3].offset;
+ len = info->ecclayout->oobfree[3].length;
+ memcpy(chip->buf + info->page_main_size + offset,
+ chip->oobbuf + temp, len);
+ }
[snip]
+++ b/include/linux/mtd/spinand.h
@@ -0,0 +1,155 @@
+/*
+ * linux/include/linux/mtd/spinand.h
+ * Copyright (c) 2009-2010 Micron Technology, Inc.
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+/bin/bash: 4: command not found
+ *
+ * based on nand.h
+ */
+#ifndef __LINUX_MTD_SPI_NAND_
[PATCHv2] drivers: mtd: spinand: Add generic spinand frameowrk.
From: Mona Anonuevo
This patch adds support for a generic spinand framework(spinand_mtd.c).
This frameowrk can be used for other spi based flash devices. The idea
is to have a common model under drivers/mtd, as also present for other non spi
devices(there is a generic framework and device part simply attaches itself to
it.)
Signed-off-by: Mona Anonuevo
Signed-off-by: Tuan Nguyen
Signed-off-by: Sourav Poddar
This patch was sent as a part of a series[1];
but this can go in as a standalone patch.
[1]: https://lkml.org/lkml/2013/6/26/83
v1->v2:
seperated the specific micron driver,
flash devices can attach itself seperately to this
generic framework.
drivers/mtd/Kconfig |2 +
drivers/mtd/Makefile |2 +
drivers/mtd/spinand/Kconfig | 24 ++
drivers/mtd/spinand/Makefile |8 +
drivers/mtd/spinand/spinand_mtd.c | 690 +
include/linux/mtd/spinand.h | 155 +
6 files changed, 881 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/spinand/Kconfig
create mode 100644 drivers/mtd/spinand/Makefile
create mode 100644 drivers/mtd/spinand/spinand_mtd.c
create mode 100644 include/linux/mtd/spinand.h
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 5fab4e6..c9e6c60 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -318,6 +318,8 @@ source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/onenand/Kconfig"
+source "drivers/mtd/spinand/Kconfig"
+
source "drivers/mtd/lpddr/Kconfig"
source "drivers/mtd/ubi/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 4cfb31e..cce68db 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -32,4 +32,6 @@ inftl-objs:= inftlcore.o inftlmount.o
obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
+obj-y += spinand/
+
obj-$(CONFIG_MTD_UBI) += ubi/
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
new file mode 100644
index 000..38c739f
--- /dev/null
+++ b/drivers/mtd/spinand/Kconfig
@@ -0,0 +1,24 @@
+#
+# linux/drivers/mtd/spinand/Kconfig
+#
+
+menuconfig MTD_SPINAND
+ tristate "SPINAND Device Support"
+ depends on MTD
+ help
+This enables support for accessing Micron SPI NAND flash
+devices.
+
+if MTD_SPINAND
+
+config MTD_SPINAND_ONDIEECC
+ bool "Use SPINAND internal ECC"
+ help
+Internel ECC
+
+config MTD_SPINAND_SWECC
+ bool "Use software ECC"
+ depends on MTD_NAND
+ help
+software ECC
+endif
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
new file mode 100644
index 000..be18de7
--- /dev/null
+++ b/drivers/mtd/spinand/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the SPI NAND MTD
+#
+
+# Core functionality.
+obj-$(CONFIG_MTD_SPINAND) += spinand.o
+
+spinand-objs := spinand_mtd.o
diff --git a/drivers/mtd/spinand/spinand_mtd.c
b/drivers/mtd/spinand/spinand_mtd.c
new file mode 100644
index 000..8bfff86
--- /dev/null
+++ b/drivers/mtd/spinand/spinand_mtd.c
@@ -0,0 +1,690 @@
+/*
+spinand_mtd.c
+
+Copyright (c) 2009-2010 Micron Technology, Inc.
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * spinand_get_device - [GENERIC] Get chip for selected access
+ * @param mtd MTD device structure
+ * @param new_statethe state which is requested
+ *
+ * Get the device and lock it for exclusive access
+ */
+#define mu_spi_nand_driver_version "Beagle-MTD_01.00_Linux2.6.33_20100507"
+
+static int spinand_get_device(struct mtd_info *mtd, int new_state)
+{
+ struct spinand_chip *this = mtd->priv;
+ DECLARE_WAITQUEUE(wait, current);
+
+ /*
+* Grab the lock and see if the device is available
+*/
+ while (1) {
+ spin_lock(>chip_lock);
+ if (this->state == FL_READY) {
+ this->state = new_state;
+ spin_unlock(>chip_lock);
+ break;
+ }
+ if (new_state == FL_PM_SUSPENDED) {
+ spin_unlock(>chip_lock);
+ return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
+ }
+ set_current_state(TASK_UNINTERR
[PATCHv2] drivers: mtd: spinand: Add generic spinand frameowrk.
From: Mona Anonuevo manonu...@micron.com
This patch adds support for a generic spinand framework(spinand_mtd.c).
This frameowrk can be used for other spi based flash devices. The idea
is to have a common model under drivers/mtd, as also present for other non spi
devices(there is a generic framework and device part simply attaches itself to
it.)
Signed-off-by: Mona Anonuevo manonu...@micron.com
Signed-off-by: Tuan Nguyen tqngu...@micron.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
This patch was sent as a part of a series[1];
but this can go in as a standalone patch.
[1]: https://lkml.org/lkml/2013/6/26/83
v1-v2:
seperated the specific micron driver,
flash devices can attach itself seperately to this
generic framework.
drivers/mtd/Kconfig |2 +
drivers/mtd/Makefile |2 +
drivers/mtd/spinand/Kconfig | 24 ++
drivers/mtd/spinand/Makefile |8 +
drivers/mtd/spinand/spinand_mtd.c | 690 +
include/linux/mtd/spinand.h | 155 +
6 files changed, 881 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/spinand/Kconfig
create mode 100644 drivers/mtd/spinand/Makefile
create mode 100644 drivers/mtd/spinand/spinand_mtd.c
create mode 100644 include/linux/mtd/spinand.h
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 5fab4e6..c9e6c60 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -318,6 +318,8 @@ source drivers/mtd/nand/Kconfig
source drivers/mtd/onenand/Kconfig
+source drivers/mtd/spinand/Kconfig
+
source drivers/mtd/lpddr/Kconfig
source drivers/mtd/ubi/Kconfig
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 4cfb31e..cce68db 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -32,4 +32,6 @@ inftl-objs:= inftlcore.o inftlmount.o
obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
+obj-y += spinand/
+
obj-$(CONFIG_MTD_UBI) += ubi/
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
new file mode 100644
index 000..38c739f
--- /dev/null
+++ b/drivers/mtd/spinand/Kconfig
@@ -0,0 +1,24 @@
+#
+# linux/drivers/mtd/spinand/Kconfig
+#
+
+menuconfig MTD_SPINAND
+ tristate SPINAND Device Support
+ depends on MTD
+ help
+This enables support for accessing Micron SPI NAND flash
+devices.
+
+if MTD_SPINAND
+
+config MTD_SPINAND_ONDIEECC
+ bool Use SPINAND internal ECC
+ help
+Internel ECC
+
+config MTD_SPINAND_SWECC
+ bool Use software ECC
+ depends on MTD_NAND
+ help
+software ECC
+endif
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
new file mode 100644
index 000..be18de7
--- /dev/null
+++ b/drivers/mtd/spinand/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the SPI NAND MTD
+#
+
+# Core functionality.
+obj-$(CONFIG_MTD_SPINAND) += spinand.o
+
+spinand-objs := spinand_mtd.o
diff --git a/drivers/mtd/spinand/spinand_mtd.c
b/drivers/mtd/spinand/spinand_mtd.c
new file mode 100644
index 000..8bfff86
--- /dev/null
+++ b/drivers/mtd/spinand/spinand_mtd.c
@@ -0,0 +1,690 @@
+/*
+spinand_mtd.c
+
+Copyright (c) 2009-2010 Micron Technology, Inc.
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+*/
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/init.h
+#include linux/sched.h
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/jiffies.h
+#include linux/mtd/mtd.h
+#include linux/mtd/partitions.h
+#include linux/mtd/spinand.h
+#include linux/mtd/nand_ecc.h
+
+/**
+ * spinand_get_device - [GENERIC] Get chip for selected access
+ * @param mtd MTD device structure
+ * @param new_statethe state which is requested
+ *
+ * Get the device and lock it for exclusive access
+ */
+#define mu_spi_nand_driver_version Beagle-MTD_01.00_Linux2.6.33_20100507
+
+static int spinand_get_device(struct mtd_info *mtd, int new_state)
+{
+ struct spinand_chip *this = mtd-priv;
+ DECLARE_WAITQUEUE(wait, current);
+
+ /*
+* Grab the lock and see if the device is available
+*/
+ while (1) {
+ spin_lock(this-chip_lock);
+ if (this-state == FL_READY) {
+ this-state = new_state;
+ spin_unlock(this-chip_lock);
+ break;
+ }
+ if (new_state == FL_PM_SUSPENDED) {
+ spin_unlock(this-chip_lock);
+ return
Re: [PATCHv2] drivers: mtd: spinand: Add generic spinand frameowrk.
Hi,
On Wednesday 03 July 2013 10:47 PM, Florian Fainelli wrote:
Hello,
2013/7/3 Sourav Poddarsourav.pod...@ti.com:
From: Mona Anonuevomanonu...@micron.com
This patch adds support for a generic spinand framework(spinand_mtd.c).
This frameowrk can be used for other spi based flash devices. The idea
is to have a common model under drivers/mtd, as also present for other non spi
devices(there is a generic framework and device part simply attaches itself to
it.)
Resending my comments since your previous submissino
Signed-off-by: Mona Anonuevomanonu...@micron.com
Signed-off-by: Tuan Nguyentqngu...@micron.com
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
[snip]
+if MTD_SPINAND
+
+config MTD_SPINAND_ONDIEECC
+ bool Use SPINAND internal ECC
+ help
+Internel ECC
+
+config MTD_SPINAND_SWECC
+ bool Use software ECC
+ depends on MTD_NAND
+ help
+software ECC
Can this somehow be made a runtime thing?
Ahh..I think we might opt for a device tree entry and based on that
check for ECC.
[snip]
+ if (count oob_num ops-oobbuf chip-oobbuf) {
+ int size;
+ int offset, len, temp;
+
+ /* repack spare to oob */
+ memset(chip-oobbuf, 0, info-ecclayout-oobavail);
+
+ temp = 0;
+ offset = info-ecclayout-oobfree[0].offset;
+ len = info-ecclayout-oobfree[0].length;
+ memcpy(chip-oobbuf + temp,
+ chip-buf + info-page_main_size + offset, len);
Sounds like a for look might be useful here
I dont think so, there is a while loop above under which it happens.
We are increasing count at the bottom of the while loop. So, I think
this should work fine.
+
+ temp += len;
+ offset = info-ecclayout-oobfree[1].offset;
+ len = info-ecclayout-oobfree[1].length;
+ memcpy(chip-oobbuf + temp,
+ chip-buf + info-page_main_size + offset, len);
+
+ temp += len;
+ offset = info-ecclayout-oobfree[2].offset;
+ len = info-ecclayout-oobfree[2].length;
+ memcpy(chip-oobbuf + temp,
+ chip-buf + info-page_main_size + offset, len);
+
+ temp += len;
+ offset = info-ecclayout-oobfree[3].offset;
+ len = info-ecclayout-oobfree[3].length;
+ memcpy(chip-oobbuf + temp,
+ chip-buf + info-page_main_size + offset, len);
+
[snip]
+ /* repack oob to spare */
+ temp = 0;
+ offset = info-ecclayout-oobfree[0].offset;
+ len = info-ecclayout-oobfree[0].length;
+ memcpy(chip-buf + info-page_main_size + offset,
+ chip-oobbuf + temp, len);
And here too.
Same as above.
+
+ temp += len;
+ offset = info-ecclayout-oobfree[1].offset;
+ len = info-ecclayout-oobfree[1].length;
+ memcpy(chip-buf + info-page_main_size + offset,
+ chip-oobbuf + temp, len);
+
+ temp += len;
+ offset = info-ecclayout-oobfree[2].offset;
+ len = info-ecclayout-oobfree[2].length;
+ memcpy(chip-buf + info-page_main_size + offset,
+ chip-oobbuf + temp, len);
+
+ temp += len;
+ offset = info-ecclayout-oobfree[3].offset;
+ len = info-ecclayout-oobfree[3].length;
+ memcpy(chip-buf + info-page_main_size + offset,
+ chip-oobbuf + temp, len);
+ }
[snip]
+++ b/include/linux/mtd/spinand.h
@@ -0,0 +1,155 @@
+/*
+ * linux/include/linux/mtd/spinand.h
+ * Copyright (c) 2009-2010 Micron Technology, Inc.
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+/bin/bash: 4: command not found
+ *
+ * based on nand.h
+ */
+#ifndef __LINUX_MTD_SPI_NAND_H
+#define __LINUX_MTD_SPI_NAND_H
+
+#includelinux/wait.h
+#includelinux/spinlock.h
+#includelinux/mtd/mtd.h
+
+/* cmd */
+#define CMD_READ 0x13
+#define CMD_READ_RDM
Re: [PATCHv2] drivers: spi: Add qspi flash controller
Hi Sekhar,
On Tuesday 02 July 2013 04:27 PM, Sekhar Nori wrote:
On 7/2/2013 2:26 PM, Sourav Poddar wrote:
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar
---
This patch was sent as a part of a series[1];
but this can go in as a standalone patch.
[1]: https://lkml.org/lkml/2013/6/26/83
v1->v2:
1. Placed pm specific calls in prepare/unprepare apis.
2. Put a mask to support upto 32 bits word length.
3. Used "devm_ioremap_resource" variants.
4. Add dt binding doumentation.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 ++
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/ti-qspi.c | 357 +
4 files changed, 388 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/ti-qspi.c
Please cc devicetree-discuss list when adding new bindings.
Ok.
+static int dra7xxx_qspi_probe(struct platform_device *pdev)
+{
+ struct dra7xxx_qspi *qspi;
+ struct spi_master *master;
+ struct resource *r;
+ struct device_node *np = pdev->dev.of_node;
+ u32 max_freq;
+ int ret;
+
+ master = spi_alloc_master(>dev, sizeof(*qspi));
+ if (!master)
+ return -ENOMEM;
+
+ master->mode_bits = SPI_CPOL | SPI_CPHA;
+
+ master->num_chipselect = 1;
+ master->bus_num = -1;
+ master->setup = dra7xxx_qspi_setup;
+ master->prepare_transfer_hardware = dra7xxx_qspi_prepare_xfer;
+ master->transfer_one_message = dra7xxx_qspi_start_transfer_one;
+ master->unprepare_transfer_hardware = dra7xxx_qspi_unprepare_xfer;
+ master->dev.of_node = pdev->dev.of_node;
+ master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
+
+ dev_set_drvdata(>dev, master);
+
+ qspi = spi_master_get_devdata(master);
+ qspi->master = master;
+ qspi->dev =>dev;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (r == NULL) {
+ ret = -ENODEV;
+ goto free_master;
+ }
+
+ qspi->base = devm_ioremap_resource(>dev, r);
+ if (!qspi->base) {
+ dev_dbg(>dev, "can't ioremap MCSPI\n");
+ ret = -ENOMEM;
+ goto free_master;
+ }
This should be
if (IS_ERR(qspi->base)) {
dev_dbg(>dev, "can't ioremap QSPI\n");
ret = PTR_ERR(qspi->base);
goto free_master;
}
Ok. will change it in next version.
Thanks,
Sekhar
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Re: [PATCHv2] drivers: spi: Add qspi flash controller
On Tuesday 02 July 2013 04:01 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:53:49PM +0530, Sourav Poddar wrote:
On Tuesday 02 July 2013 03:46 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:30:42PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi =
+ spi_master_get_devdata(spi->master);
+
+ int clk_div;
+
+ if (!qspi->spi_max_frequency)
+ clk_div = 0;
won't this generate division by zero ?
Yes, Probably only an error should be thrown here. ?
since min clk_div should be kept at 1.
right, if spi_max_frequency isn't passed, this is a broken DT binding.
Bail out.
+ pm_runtime_get_sync(qspi->dev);
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG)
+ &~QSPI_CLK_EN, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div<0) {
btw, add a space between clk_div and<
+ dra7xxx_writel(qspi, *txbuf++, QSPI_SPI_DATA_REG);
+ dra7xxx_writel(qspi, qspi->dc, QSPI_SPI_DC_REG);
+ dra7xxx_writel(qspi, qspi->cmd | QSPI_WR_SNGL,
+ QSPI_SPI_CMD_REG);
+ status = dra7xxx_readl(qspi, QSPI_SPI_STATUS_REG);
+ timeout = QSPI_TIMEOUT;
+ while ((status&QSPI_WC_BUSY) != QSPI_XFER_DONE) {
do you really need to poll ? No IRQ available ?
There is an interrupt available, I will try using that.
look at how i2c-omap.c synchronizes interrupt with the transfer_msg
code. It just uses a wait_for_completion().
Ok.
+static int dra7xxx_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m->spi;
+ struct spi_transfer *t;
+ int status = 0;
+ int flags = 0;
+
+ /* setup command reg */
+ qspi->cmd = 0;
+ qspi->cmd |= QSPI_WLEN(8);
+ qspi->cmd |= QSPI_EN_CS(0);
+ qspi->cmd |= 0xfff;
Since, we dont know the number of frame lenght that need to be
transferred and it comes from the spi framework, we keep the frame
lenght to maximum.
Then depending on the count value above in while loop, we terminate
our trasnfer.
what ? seriously didn't get what you meant.
I mean, the lower 12 bits of cmd register is meant to be filled with
frame lenght.
But the frame lenght is parsed when you iterate the list. So, what is
which list ?
message list, from which we iterate through each transfers.
done here is that
the framelenght is kept to its maximum value.
why ? That seems wrong. If you can get the actual frame length at some
point, that's what you should use.
Ok.Then probably it makes sense to have frame count interrupt also to
signal the end of frame.
Then, to signal the the end of the frame, we use
static int qspi_transfer_msg(struct dra7xxx_qspi *qspi, unsigned count,
const u8 *txbuf, u8 *rxbuf, bool flags)
{
uint status;
int timeout;
while (count--) {
if (txbuf) {
pr_debug("tx cmd %08x dc %08x data %02x\n",
qspi->cmd | QSPI_WR_SNGL, qspi->dc,
*txbuf);
dra7xxx_writel(qspi, *txbuf++, QSPI_SPI_DATA_REG);
dra7xxx_writel(qspi, qspi->dc, QSPI_SPI_DC_REG);
dra7xxx_writel(qspi, qspi->cmd | QSPI_WR_SNGL,
QSPI_SPI_CMD_REG);
status = dra7xxx_readl(qspi, QSPI_SPI_STATUS_REG);
timeout = QSPI_TIMEOUT;
while ((status& QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout< 0) {
pr_debug("QSPI tx timed out\n");
return
.
status, *(rxbuf-1));
}
}
if (flags& XFER_END)
dra7xxx_writel(qspi, qspi->cmd | QSPI_INVAL,
QSPI_SPI_CMD_REG);
}
INVAL will terminate the current frame.
nevermind that this value is "RESERVED" on the documentation. You should
not rely on reserved features, they can go away at any point in time.
That's probably there only for some IP debugging kinda thing.
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Re: [PATCHv2] drivers: spi: Add qspi flash controller
Hi Mark, On Tuesday 02 July 2013 03:47 PM, Mark Brown wrote: On Tue, Jul 02, 2013 at 12:44:04PM +0300, Felipe Balbi wrote: On Tue, Jul 02, 2013 at 10:32:47AM +0100, Mark Brown wrote: Does this hardware really support anything other than 8 bits per word? There is no code in the driver which pays any attention to the word size... the HW has a 128-bit shift register ;-) but driver doesn't look complete. That's not the issue - remember that SPI specifies big endian byte ordering for words on the bus so things will need to be reordered by the hardware for anything except 8 bits. Yes, I defaulted my driver to assume 8 bits. I will introduce case by case reads based on t->len Something like.. case 8: readb(); case 16: readw(); case 32: readl(); ~Sourav -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCHv2] drivers: spi: Add qspi flash controller
On Tuesday 02 July 2013 03:46 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:30:42PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi =
+ spi_master_get_devdata(spi->master);
+
+ int clk_div;
+
+ if (!qspi->spi_max_frequency)
+ clk_div = 0;
won't this generate division by zero ?
Yes, Probably only an error should be thrown here. ?
since min clk_div should be kept at 1.
right, if spi_max_frequency isn't passed, this is a broken DT binding.
Bail out.
+ pm_runtime_get_sync(qspi->dev);
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG)
+ & ~QSPI_CLK_EN, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div< 0) {
btw, add a space between clk_div and<
+ dra7xxx_writel(qspi, *txbuf++, QSPI_SPI_DATA_REG);
+ dra7xxx_writel(qspi, qspi->dc, QSPI_SPI_DC_REG);
+ dra7xxx_writel(qspi, qspi->cmd | QSPI_WR_SNGL,
+ QSPI_SPI_CMD_REG);
+ status = dra7xxx_readl(qspi, QSPI_SPI_STATUS_REG);
+ timeout = QSPI_TIMEOUT;
+ while ((status& QSPI_WC_BUSY) != QSPI_XFER_DONE) {
do you really need to poll ? No IRQ available ?
There is an interrupt available, I will try using that.
look at how i2c-omap.c synchronizes interrupt with the transfer_msg
code. It just uses a wait_for_completion().
Ok.
+static int dra7xxx_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m->spi;
+ struct spi_transfer *t;
+ int status = 0;
+ int flags = 0;
+
+ /* setup command reg */
+ qspi->cmd = 0;
+ qspi->cmd |= QSPI_WLEN(8);
+ qspi->cmd |= QSPI_EN_CS(0);
+ qspi->cmd |= 0xfff;
Since, we dont know the number of frame lenght that need to be
transferred and it comes from the spi framework, we keep the frame
lenght to maximum.
Then depending on the count value above in while loop, we terminate
our trasnfer.
what ? seriously didn't get what you meant.
I mean, the lower 12 bits of cmd register is meant to be filled with
frame lenght.
But the frame lenght is parsed when you iterate the list. So, what is
done here is that
the framelenght is kept to its maximum value.
Then, to signal the the end of the frame, we use
static int qspi_transfer_msg(struct dra7xxx_qspi *qspi, unsigned count,
const u8 *txbuf, u8 *rxbuf, bool flags)
{
uint status;
int timeout;
while (count--) {
if (txbuf) {
pr_debug("tx cmd %08x dc %08x data %02x\n",
qspi->cmd | QSPI_WR_SNGL, qspi->dc,
*txbuf);
dra7xxx_writel(qspi, *txbuf++, QSPI_SPI_DATA_REG);
dra7xxx_writel(qspi, qspi->dc, QSPI_SPI_DC_REG);
dra7xxx_writel(qspi, qspi->cmd | QSPI_WR_SNGL,
QSPI_SPI_CMD_REG);
status = dra7xxx_readl(qspi, QSPI_SPI_STATUS_REG);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout < 0) {
pr_debug("QSPI tx timed out\n");
return
.
status, *(rxbuf-1));
}
}
if (flags & XFER_END)
dra7xxx_writel(qspi, qspi->cmd | QSPI_INVAL,
QSPI_SPI_CMD_REG);
}
INVAL will terminate the current frame.
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Re: [PATCHv2] drivers: spi: Add qspi flash controller
Hi Felipe,
On Tuesday 02 July 2013 02:54 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 02:26:39PM +0530, Sourav Poddar wrote:
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += ti-qspi.o
all other drivers are prepended with spi-
Hmm, will change the name in next version.
diff --git a/drivers/spi/ti-qspi.c b/drivers/spi/ti-qspi.c
new file mode 100644
index 000..e646a93
--- /dev/null
+++ b/drivers/spi/ti-qspi.c
@@ -0,0 +1,357 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct dra7xxx_qspi {
+ struct spi_master *master;
+ void __iomem*base;
+ int device_type;
+ struct device *dev;
nit: move this pointer up and the int down.
Ok.
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define QSPI_SYSCONFIG (0x10)
+#define QSPI_INTR_STATUS_RAW_SET (0x20)
+#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
+#define QSPI_INTR_ENABLE_SET_REG (0x28)
+#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
+#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
+#define QSPI_SPI_DC_REG(0x44)
+#define QSPI_SPI_CMD_REG (0x48)
+#define QSPI_SPI_STATUS_REG(0x4c)
+#define QSPI_SPI_DATA_REG (0x50)
+#define QSPI_SPI_SETUP0_REG(0x54)
+#define QSPI_SPI_SWITCH_REG(0x64)
+#define QSPI_SPI_SETUP1_REG(0x58)
+#define QSPI_SPI_SETUP2_REG(0x5c)
+#define QSPI_SPI_SETUP3_REG(0x60)
+#define QSPI_SPI_DATA_REG_1(0x68)
+#define QSPI_SPI_DATA_REG_2(0x6c)
+#define QSPI_SPI_DATA_REG_3(0x70)
+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1<< 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n<< 28)
+#define QSPI_WLEN(n) ((n-1)<< 19)
+#define QSPI_3_PIN (1<< 18)
+#define QSPI_RD_SNGL (1<< 16)
+#define QSPI_WR_SNGL (2<< 16)
+#define QSPI_RD_QUAD (7<< 16)
+#define QSPI_INVAL (4<< 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m<< (3 + n*8))
+#define QSPI_CKPHA(n) (1<< (2 + n*8))
+#define QSPI_CSPOL(n) (1<< (1 + n*8))
+#define QSPI_CKPOL(n) (1<< (n*8))
+
+/* Status */
+#define QSPI_WC(1<< 1)
+#define QSPI_BUSY (1<< 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define XFER_END 0x01
+
+#define SPI_AUTOSUSPEND_TIMEOUT 2000
+
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi->base + reg);
+}
+
+static inline void dra7xxx_writel(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg)
+{
+ writel(val, qspi->base + reg);
+}
+
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi =
+ spi_master_get_devdata(spi->master);
+
+ int clk_div;
+
+ if (!qspi->spi_max_frequency)
+ clk_div = 0;
won't this generate division by zero ?
Yes, Probably only an error should be thrown here. ?
since min clk_div should be kept at 1.
+ else
+ clk_div = (QSPI_FCLK / qspi->spi_max_frequency) - 1;
this QSPI_FCLK looks like it should be a clk_get_rate().
Ok.
+ pr_debug("%s: hz: %d, c
[PATCHv2] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar
---
This patch was sent as a part of a series[1];
but this can go in as a standalone patch.
[1]: https://lkml.org/lkml/2013/6/26/83
v1->v2:
1. Placed pm specific calls in prepare/unprepare apis.
2. Put a mask to support upto 32 bits word length.
3. Used "devm_ioremap_resource" variants.
4. Add dt binding doumentation.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 ++
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/ti-qspi.c | 357 +
4 files changed, 388 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/ti-qspi.c
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b/Documentation/devicetree/bindings/spi/ti_qspi.txt
new file mode 100644
index 000..65075c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -0,0 +1,22 @@
+TI QSPI controller.
+
+Required properties:
+- compatible : should be "ti,dra7xxx-qspi".
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+qspi: qspi@4b30 {
+ compatible = "ti,dra7xxx-qspi";
+ reg = <0x4b30 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+spi-max-frequency = <2500>;
+ ti,hwmods = "qspi";
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..9937d66 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,14 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate "DRA7xxx QSPI controller support"
+ depends on ARCH_OMAP2PLUS
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+ This device supports single, dual and quad read support, while
+ it only supports single write mode.
+
config SPI_OMAP_100K
tristate "OMAP SPI 100K"
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/ti-qspi.c b/drivers/spi/ti-qspi.c
new file mode 100644
index 000..e646a93
--- /dev/null
+++ b/drivers/spi/ti-qspi.c
@@ -0,0 +1,357 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct dra7xxx_qspi {
+ struct spi_master *master;
+ void __iomem*base;
+ int device_type;
+ struct device *dev;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define QSPI_SYSCONFIG (0x10)
+#define QSPI_INTR_STATUS_RAW_SET (0x20)
+#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
+#def
[PATCHv2] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
This patch was sent as a part of a series[1];
but this can go in as a standalone patch.
[1]: https://lkml.org/lkml/2013/6/26/83
v1-v2:
1. Placed pm specific calls in prepare/unprepare apis.
2. Put a mask to support upto 32 bits word length.
3. Used devm_ioremap_resource variants.
4. Add dt binding doumentation.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 ++
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/ti-qspi.c | 357 +
4 files changed, 388 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/ti-qspi.c
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b/Documentation/devicetree/bindings/spi/ti_qspi.txt
new file mode 100644
index 000..65075c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -0,0 +1,22 @@
+TI QSPI controller.
+
+Required properties:
+- compatible : should be ti,dra7xxx-qspi.
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+qspi: qspi@4b30 {
+ compatible = ti,dra7xxx-qspi;
+ reg = 0x4b30 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+spi-max-frequency = 2500;
+ ti,hwmods = qspi;
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..9937d66 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,14 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate DRA7xxx QSPI controller support
+ depends on ARCH_OMAP2PLUS
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+ This device supports single, dual and quad read support, while
+ it only supports single write mode.
+
config SPI_OMAP_100K
tristate OMAP SPI 100K
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/ti-qspi.c b/drivers/spi/ti-qspi.c
new file mode 100644
index 000..e646a93
--- /dev/null
+++ b/drivers/spi/ti-qspi.c
@@ -0,0 +1,357 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/device.h
+#include linux/delay.h
+#include linux/dma-mapping.h
+#include linux/dmaengine.h
+#include linux/omap-dma.h
+#include linux/platform_device.h
+#include linux/err.h
+#include linux/clk.h
+#include linux/io.h
+#include linux/slab.h
+#include linux/pm_runtime.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/consumer.h
+
+#include linux/spi/spi.h
+
+struct dra7xxx_qspi {
+ struct spi_master *master;
+ void __iomem*base;
+ int device_type;
+ struct device *dev;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc
Re: [PATCHv2] drivers: spi: Add qspi flash controller
Hi Felipe,
On Tuesday 02 July 2013 02:54 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 02:26:39PM +0530, Sourav Poddar wrote:
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += ti-qspi.o
all other drivers are prepended with spi-
Hmm, will change the name in next version.
diff --git a/drivers/spi/ti-qspi.c b/drivers/spi/ti-qspi.c
new file mode 100644
index 000..e646a93
--- /dev/null
+++ b/drivers/spi/ti-qspi.c
@@ -0,0 +1,357 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#includelinux/kernel.h
+#includelinux/init.h
+#includelinux/interrupt.h
+#includelinux/module.h
+#includelinux/device.h
+#includelinux/delay.h
+#includelinux/dma-mapping.h
+#includelinux/dmaengine.h
+#includelinux/omap-dma.h
+#includelinux/platform_device.h
+#includelinux/err.h
+#includelinux/clk.h
+#includelinux/io.h
+#includelinux/slab.h
+#includelinux/pm_runtime.h
+#includelinux/of.h
+#includelinux/of_device.h
+#includelinux/pinctrl/consumer.h
+
+#includelinux/spi/spi.h
+
+struct dra7xxx_qspi {
+ struct spi_master *master;
+ void __iomem*base;
+ int device_type;
+ struct device *dev;
nit: move this pointer up and the int down.
Ok.
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define QSPI_SYSCONFIG (0x10)
+#define QSPI_INTR_STATUS_RAW_SET (0x20)
+#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
+#define QSPI_INTR_ENABLE_SET_REG (0x28)
+#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
+#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
+#define QSPI_SPI_DC_REG(0x44)
+#define QSPI_SPI_CMD_REG (0x48)
+#define QSPI_SPI_STATUS_REG(0x4c)
+#define QSPI_SPI_DATA_REG (0x50)
+#define QSPI_SPI_SETUP0_REG(0x54)
+#define QSPI_SPI_SWITCH_REG(0x64)
+#define QSPI_SPI_SETUP1_REG(0x58)
+#define QSPI_SPI_SETUP2_REG(0x5c)
+#define QSPI_SPI_SETUP3_REG(0x60)
+#define QSPI_SPI_DATA_REG_1(0x68)
+#define QSPI_SPI_DATA_REG_2(0x6c)
+#define QSPI_SPI_DATA_REG_3(0x70)
+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_RD_QUAD (7 16)
+#define QSPI_INVAL (4 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+
+/* Status */
+#define QSPI_WC(1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define XFER_END 0x01
+
+#define SPI_AUTOSUSPEND_TIMEOUT 2000
+
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi-base + reg);
+}
+
+static inline void dra7xxx_writel(struct dra7xxx_qspi *qspi,
+ unsigned long val, unsigned long reg)
+{
+ writel(val, qspi-base + reg);
+}
+
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi =
+ spi_master_get_devdata(spi-master);
+
+ int clk_div;
+
+ if (!qspi-spi_max_frequency)
+ clk_div = 0;
won't this generate division by zero ?
Yes, Probably only an error should be thrown here. ?
since min clk_div should be kept at 1.
+ else
+ clk_div = (QSPI_FCLK
Re: [PATCHv2] drivers: spi: Add qspi flash controller
On Tuesday 02 July 2013 03:46 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:30:42PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi =
+ spi_master_get_devdata(spi-master);
+
+ int clk_div;
+
+ if (!qspi-spi_max_frequency)
+ clk_div = 0;
won't this generate division by zero ?
Yes, Probably only an error should be thrown here. ?
since min clk_div should be kept at 1.
right, if spi_max_frequency isn't passed, this is a broken DT binding.
Bail out.
+ pm_runtime_get_sync(qspi-dev);
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG)
+ ~QSPI_CLK_EN, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div 0) {
btw, add a space between clk_div and
+ dra7xxx_writel(qspi, *txbuf++, QSPI_SPI_DATA_REG);
+ dra7xxx_writel(qspi, qspi-dc, QSPI_SPI_DC_REG);
+ dra7xxx_writel(qspi, qspi-cmd | QSPI_WR_SNGL,
+ QSPI_SPI_CMD_REG);
+ status = dra7xxx_readl(qspi, QSPI_SPI_STATUS_REG);
+ timeout = QSPI_TIMEOUT;
+ while ((status QSPI_WC_BUSY) != QSPI_XFER_DONE) {
do you really need to poll ? No IRQ available ?
There is an interrupt available, I will try using that.
look at how i2c-omap.c synchronizes interrupt with the transfer_msg
code. It just uses a wait_for_completion().
Ok.
+static int dra7xxx_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m-spi;
+ struct spi_transfer *t;
+ int status = 0;
+ int flags = 0;
+
+ /* setup command reg */
+ qspi-cmd = 0;
+ qspi-cmd |= QSPI_WLEN(8);
+ qspi-cmd |= QSPI_EN_CS(0);
+ qspi-cmd |= 0xfff;
Since, we dont know the number of frame lenght that need to be
transferred and it comes from the spi framework, we keep the frame
lenght to maximum.
Then depending on the count value above in while loop, we terminate
our trasnfer.
what ? seriously didn't get what you meant.
I mean, the lower 12 bits of cmd register is meant to be filled with
frame lenght.
But the frame lenght is parsed when you iterate the list. So, what is
done here is that
the framelenght is kept to its maximum value.
Then, to signal the the end of the frame, we use
static int qspi_transfer_msg(struct dra7xxx_qspi *qspi, unsigned count,
const u8 *txbuf, u8 *rxbuf, bool flags)
{
uint status;
int timeout;
while (count--) {
if (txbuf) {
pr_debug(tx cmd %08x dc %08x data %02x\n,
qspi-cmd | QSPI_WR_SNGL, qspi-dc,
*txbuf);
dra7xxx_writel(qspi, *txbuf++, QSPI_SPI_DATA_REG);
dra7xxx_writel(qspi, qspi-dc, QSPI_SPI_DC_REG);
dra7xxx_writel(qspi, qspi-cmd | QSPI_WR_SNGL,
QSPI_SPI_CMD_REG);
status = dra7xxx_readl(qspi, QSPI_SPI_STATUS_REG);
timeout = QSPI_TIMEOUT;
while ((status QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout 0) {
pr_debug(QSPI tx timed out\n);
return
.
status, *(rxbuf-1));
}
}
if (flags XFER_END)
dra7xxx_writel(qspi, qspi-cmd | QSPI_INVAL,
QSPI_SPI_CMD_REG);
}
INVAL will terminate the current frame.
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Re: [PATCHv2] drivers: spi: Add qspi flash controller
Hi Mark, On Tuesday 02 July 2013 03:47 PM, Mark Brown wrote: On Tue, Jul 02, 2013 at 12:44:04PM +0300, Felipe Balbi wrote: On Tue, Jul 02, 2013 at 10:32:47AM +0100, Mark Brown wrote: Does this hardware really support anything other than 8 bits per word? There is no code in the driver which pays any attention to the word size... the HW has a 128-bit shift register ;-) but driver doesn't look complete. That's not the issue - remember that SPI specifies big endian byte ordering for words on the bus so things will need to be reordered by the hardware for anything except 8 bits. Yes, I defaulted my driver to assume 8 bits. I will introduce case by case reads based on t-len Something like.. case 8: readb(); case 16: readw(); case 32: readl(); ~Sourav -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCHv2] drivers: spi: Add qspi flash controller
On Tuesday 02 July 2013 04:01 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:53:49PM +0530, Sourav Poddar wrote:
On Tuesday 02 July 2013 03:46 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 02, 2013 at 03:30:42PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_setup(struct spi_device *spi)
+{
+ struct dra7xxx_qspi *qspi =
+ spi_master_get_devdata(spi-master);
+
+ int clk_div;
+
+ if (!qspi-spi_max_frequency)
+ clk_div = 0;
won't this generate division by zero ?
Yes, Probably only an error should be thrown here. ?
since min clk_div should be kept at 1.
right, if spi_max_frequency isn't passed, this is a broken DT binding.
Bail out.
+ pm_runtime_get_sync(qspi-dev);
+
+ /* disable SCLK */
+ dra7xxx_writel(qspi, dra7xxx_readl(qspi, QSPI_SPI_CLOCK_CNTRL_REG)
+ ~QSPI_CLK_EN, QSPI_SPI_CLOCK_CNTRL_REG);
+
+ if (clk_div0) {
btw, add a space between clk_div and
+ dra7xxx_writel(qspi, *txbuf++, QSPI_SPI_DATA_REG);
+ dra7xxx_writel(qspi, qspi-dc, QSPI_SPI_DC_REG);
+ dra7xxx_writel(qspi, qspi-cmd | QSPI_WR_SNGL,
+ QSPI_SPI_CMD_REG);
+ status = dra7xxx_readl(qspi, QSPI_SPI_STATUS_REG);
+ timeout = QSPI_TIMEOUT;
+ while ((statusQSPI_WC_BUSY) != QSPI_XFER_DONE) {
do you really need to poll ? No IRQ available ?
There is an interrupt available, I will try using that.
look at how i2c-omap.c synchronizes interrupt with the transfer_msg
code. It just uses a wait_for_completion().
Ok.
+static int dra7xxx_qspi_start_transfer_one(struct spi_master *master,
+ struct spi_message *m)
+{
+ struct dra7xxx_qspi *qspi = spi_master_get_devdata(master);
+ struct spi_device *spi = m-spi;
+ struct spi_transfer *t;
+ int status = 0;
+ int flags = 0;
+
+ /* setup command reg */
+ qspi-cmd = 0;
+ qspi-cmd |= QSPI_WLEN(8);
+ qspi-cmd |= QSPI_EN_CS(0);
+ qspi-cmd |= 0xfff;
Since, we dont know the number of frame lenght that need to be
transferred and it comes from the spi framework, we keep the frame
lenght to maximum.
Then depending on the count value above in while loop, we terminate
our trasnfer.
what ? seriously didn't get what you meant.
I mean, the lower 12 bits of cmd register is meant to be filled with
frame lenght.
But the frame lenght is parsed when you iterate the list. So, what is
which list ?
message list, from which we iterate through each transfers.
done here is that
the framelenght is kept to its maximum value.
why ? That seems wrong. If you can get the actual frame length at some
point, that's what you should use.
Ok.Then probably it makes sense to have frame count interrupt also to
signal the end of frame.
Then, to signal the the end of the frame, we use
static int qspi_transfer_msg(struct dra7xxx_qspi *qspi, unsigned count,
const u8 *txbuf, u8 *rxbuf, bool flags)
{
uint status;
int timeout;
while (count--) {
if (txbuf) {
pr_debug(tx cmd %08x dc %08x data %02x\n,
qspi-cmd | QSPI_WR_SNGL, qspi-dc,
*txbuf);
dra7xxx_writel(qspi, *txbuf++, QSPI_SPI_DATA_REG);
dra7xxx_writel(qspi, qspi-dc, QSPI_SPI_DC_REG);
dra7xxx_writel(qspi, qspi-cmd | QSPI_WR_SNGL,
QSPI_SPI_CMD_REG);
status = dra7xxx_readl(qspi, QSPI_SPI_STATUS_REG);
timeout = QSPI_TIMEOUT;
while ((status QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout 0) {
pr_debug(QSPI tx timed out\n);
return
.
status, *(rxbuf-1));
}
}
if (flags XFER_END)
dra7xxx_writel(qspi, qspi-cmd | QSPI_INVAL,
QSPI_SPI_CMD_REG);
}
INVAL will terminate the current frame.
nevermind that this value is RESERVED on the documentation. You should
not rely on reserved features, they can go away at any point in time.
That's probably there only for some IP debugging kinda thing.
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Re: [PATCHv2] drivers: spi: Add qspi flash controller
Hi Sekhar,
On Tuesday 02 July 2013 04:27 PM, Sekhar Nori wrote:
On 7/2/2013 2:26 PM, Sourav Poddar wrote:
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
This patch was sent as a part of a series[1];
but this can go in as a standalone patch.
[1]: https://lkml.org/lkml/2013/6/26/83
v1-v2:
1. Placed pm specific calls in prepare/unprepare apis.
2. Put a mask to support upto 32 bits word length.
3. Used devm_ioremap_resource variants.
4. Add dt binding doumentation.
Documentation/devicetree/bindings/spi/ti_qspi.txt | 22 ++
drivers/spi/Kconfig |8 +
drivers/spi/Makefile |1 +
drivers/spi/ti-qspi.c | 357 +
4 files changed, 388 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/ti_qspi.txt
create mode 100644 drivers/spi/ti-qspi.c
Please cc devicetree-discuss list when adding new bindings.
Ok.
+static int dra7xxx_qspi_probe(struct platform_device *pdev)
+{
+ struct dra7xxx_qspi *qspi;
+ struct spi_master *master;
+ struct resource *r;
+ struct device_node *np = pdev-dev.of_node;
+ u32 max_freq;
+ int ret;
+
+ master = spi_alloc_master(pdev-dev, sizeof(*qspi));
+ if (!master)
+ return -ENOMEM;
+
+ master-mode_bits = SPI_CPOL | SPI_CPHA;
+
+ master-num_chipselect = 1;
+ master-bus_num = -1;
+ master-setup = dra7xxx_qspi_setup;
+ master-prepare_transfer_hardware = dra7xxx_qspi_prepare_xfer;
+ master-transfer_one_message = dra7xxx_qspi_start_transfer_one;
+ master-unprepare_transfer_hardware = dra7xxx_qspi_unprepare_xfer;
+ master-dev.of_node = pdev-dev.of_node;
+ master-bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
+
+ dev_set_drvdata(pdev-dev, master);
+
+ qspi = spi_master_get_devdata(master);
+ qspi-master = master;
+ qspi-dev =pdev-dev;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (r == NULL) {
+ ret = -ENODEV;
+ goto free_master;
+ }
+
+ qspi-base = devm_ioremap_resource(pdev-dev, r);
+ if (!qspi-base) {
+ dev_dbg(pdev-dev, can't ioremap MCSPI\n);
+ ret = -ENOMEM;
+ goto free_master;
+ }
This should be
if (IS_ERR(qspi-base)) {
dev_dbg(pdev-dev, can't ioremap QSPI\n);
ret = PTR_ERR(qspi-base);
goto free_master;
}
Ok. will change it in next version.
Thanks,
Sekhar
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Re: [PATCH 2/3] drivers: spi: Add qspi flash controller
Hi Mark,
Thanks for the review.
Comments in lined.
On Monday 01 July 2013 04:26 PM, Mark Brown wrote:
On Wed, Jun 26, 2013 at 01:11:11PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_prepare_xfer(struct spi_master *master)
+{
+ return 0;
+}
+
+static int dra7xxx_qspi_unprepare_xfer(struct spi_master *master)
+{
+ return 0;
+}
Remove empty functions, though...
+ if (flags& XFER_END)
+ dra7xxx_writel(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
+
+ pm_runtime_mark_last_busy(qspi->dev);
+ pm_runtime_put_autosuspend(qspi->dev);
...there's no point in doing this per-message, it should be in the
prepare and unprepare functions.
Ok, will do runtime PM part in prepare/unprepare in my next version.
+ master = spi_alloc_master(>dev, sizeof(*qspi));
+ if (!master)
+ return -ENOMEM;
+
+ master->mode_bits = SPI_CPOL | SPI_CPHA;
+
+ master->num_chipselect = 1;
+ master->bus_num = -1;
+ master->setup = dra7xxx_qspi_setup;
+ master->prepare_transfer_hardware = dra7xxx_qspi_prepare_xfer;
+ master->transfer_one_message = dra7xxx_qspi_start_transfer_one;
+ master->unprepare_transfer_hardware = dra7xxx_qspi_unprepare_xfer;
+ master->dev.of_node = pdev->dev.of_node;
There should be some bits per word restrictions in here I think - it
looks like only 8 bits per word is supported.
Yes, currently its only 8 bits per word support.
Yes, bits_per_word_mask can be filled to support upto 32 bits word
transition. Will add in v2.
+ qspi->base = devm_request_and_ioremap(>dev, r);
+ if (!qspi->base) {
+ dev_dbg(>dev, "can't ioremap MCSPI\n");
+ ret = -ENOMEM;
+ goto free_master;
+ }
Use devm_ioremap_resource().
Ok. Will replace.
+ if (!of_property_read_u32(np, "spi-max-frequency",_freq))
+ qspi->spi_max_frequency = max_freq;
You have OF bindings, there should be a binding document and an OF ID
table.
Yes, will add binding documentation in my next version.
Though, I have a "of_device_id" [1] populated in my patch.
May be, I need to re-arrange it above probe function. ?
[1]:
+
+static const struct of_device_id dra7xxx_qspi_match[] = {
+{.compatible = "ti,dra7xxx-qspi" },
+{},
+};
+MODULE_DEVICE_TABLE(of, dra7xxx_qspi_match);
+
Thanks,
Sourav
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Re: [PATCH 2/3] drivers: spi: Add qspi flash controller
Hi Mark,
Thanks for the review.
Comments in lined.
On Monday 01 July 2013 04:26 PM, Mark Brown wrote:
On Wed, Jun 26, 2013 at 01:11:11PM +0530, Sourav Poddar wrote:
+static int dra7xxx_qspi_prepare_xfer(struct spi_master *master)
+{
+ return 0;
+}
+
+static int dra7xxx_qspi_unprepare_xfer(struct spi_master *master)
+{
+ return 0;
+}
Remove empty functions, though...
+ if (flags XFER_END)
+ dra7xxx_writel(qspi, qspi-cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
+
+ pm_runtime_mark_last_busy(qspi-dev);
+ pm_runtime_put_autosuspend(qspi-dev);
...there's no point in doing this per-message, it should be in the
prepare and unprepare functions.
Ok, will do runtime PM part in prepare/unprepare in my next version.
+ master = spi_alloc_master(pdev-dev, sizeof(*qspi));
+ if (!master)
+ return -ENOMEM;
+
+ master-mode_bits = SPI_CPOL | SPI_CPHA;
+
+ master-num_chipselect = 1;
+ master-bus_num = -1;
+ master-setup = dra7xxx_qspi_setup;
+ master-prepare_transfer_hardware = dra7xxx_qspi_prepare_xfer;
+ master-transfer_one_message = dra7xxx_qspi_start_transfer_one;
+ master-unprepare_transfer_hardware = dra7xxx_qspi_unprepare_xfer;
+ master-dev.of_node = pdev-dev.of_node;
There should be some bits per word restrictions in here I think - it
looks like only 8 bits per word is supported.
Yes, currently its only 8 bits per word support.
Yes, bits_per_word_mask can be filled to support upto 32 bits word
transition. Will add in v2.
+ qspi-base = devm_request_and_ioremap(pdev-dev, r);
+ if (!qspi-base) {
+ dev_dbg(pdev-dev, can't ioremap MCSPI\n);
+ ret = -ENOMEM;
+ goto free_master;
+ }
Use devm_ioremap_resource().
Ok. Will replace.
+ if (!of_property_read_u32(np, spi-max-frequency,max_freq))
+ qspi-spi_max_frequency = max_freq;
You have OF bindings, there should be a binding document and an OF ID
table.
Yes, will add binding documentation in my next version.
Though, I have a of_device_id [1] populated in my patch.
May be, I need to re-arrange it above probe function. ?
[1]:
+
+static const struct of_device_id dra7xxx_qspi_match[] = {
+{.compatible = ti,dra7xxx-qspi },
+{},
+};
+MODULE_DEVICE_TABLE(of, dra7xxx_qspi_match);
+
Thanks,
Sourav
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Re: [PATCH 2/3] drivers: spi: Add qspi flash controller
+ Artem
On Wednesday 26 June 2013 01:11 PM, Sourav Poddar wrote:
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar
---
drivers/spi/Kconfig |6 +
drivers/spi/Makefile |1 +
drivers/spi/ti-qspi.c | 352 +
3 files changed, 359 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti-qspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..29a363b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,12 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate "DRA7xxx QSPI controller support"
+ depends on ARCH_OMAP2PLUS
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+
config SPI_OMAP_100K
tristate "OMAP SPI 100K"
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += ti-qspi.o
obj-$(CONFIG_SPI_ORION) += spi-orion.o
obj-$(CONFIG_SPI_PL022) += spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/ti-qspi.c b/drivers/spi/ti-qspi.c
new file mode 100644
index 000..b33646a
--- /dev/null
+++ b/drivers/spi/ti-qspi.c
@@ -0,0 +1,352 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct dra7xxx_qspi {
+ struct spi_master *master;
+ void __iomem*base;
+ int device_type;
+ struct device *dev;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define QSPI_SYSCONFIG (0x10)
+#define QSPI_INTR_STATUS_RAW_SET (0x20)
+#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
+#define QSPI_INTR_ENABLE_SET_REG (0x28)
+#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
+#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
+#define QSPI_SPI_DC_REG(0x44)
+#define QSPI_SPI_CMD_REG (0x48)
+#define QSPI_SPI_STATUS_REG(0x4c)
+#define QSPI_SPI_DATA_REG (0x50)
+#define QSPI_SPI_SETUP0_REG(0x54)
+#define QSPI_SPI_SWITCH_REG(0x64)
+#define QSPI_SPI_SETUP1_REG(0x58)
+#define QSPI_SPI_SETUP2_REG(0x5c)
+#define QSPI_SPI_SETUP3_REG(0x60)
+#define QSPI_SPI_DATA_REG_1(0x68)
+#define QSPI_SPI_DATA_REG_2(0x6c)
+#define QSPI_SPI_DATA_REG_3(0x70)
+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1<< 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n<< 28)
+#define QSPI_WLEN(n) ((n-1)<< 19)
+#define QSPI_3_PIN (1<< 18)
+#define QSPI_RD_SNGL (1<< 16)
+#define QSPI_WR_SNGL (2<< 16)
+#define QSPI_RD_QUAD (7<< 16)
+#define QSPI_INVAL (4<< 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m<< (3 + n*8))
+#define QSPI_CKPHA(n) (1<< (2 + n*8))
+#define QSPI_CSPOL(n) (1<< (1
Re: [PATCH 3/3] drivers: mtd: spinand: Add qspi spansion flash controller
+ Artem
On Wednesday 26 June 2013 01:11 PM, Sourav Poddar wrote:
The patch adds support for spansion s25fl256s spi flash controller.
Currently, the patch supports only SPI based transaction.
As, the qspi to which flash is attached supports memory mapped interface,
support will be added in future for memory mapped transactions also.
This driver gets attached to the generic spinand mtd framework proposed in the
first patch of the series.
Signed-off-by: Sourav Poddar
---
drivers/mtd/spinand/Kconfig |7 +
drivers/mtd/spinand/Makefile|2 +-
drivers/mtd/spinand/ti-qspi-flash.c | 373 +++
3 files changed, 381 insertions(+), 1 deletions(-)
create mode 100644 drivers/mtd/spinand/ti-qspi-flash.c
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
index 38c739f..1342de3 100644
--- a/drivers/mtd/spinand/Kconfig
+++ b/drivers/mtd/spinand/Kconfig
@@ -16,6 +16,13 @@ config MTD_SPINAND_ONDIEECC
help
Internel ECC
+config MTD_S25FL256S
+ tristate "Support spansion memory mapped SPI Flash chips"
+ depends on SPI_MASTER
+ help
+ This enables access to spansion QSPI flash chips, which used
+ memory mapped interface used for program and data storage.
+
config MTD_SPINAND_SWECC
bool "Use software ECC"
depends on MTD_NAND
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
index 355e726..8ad0dd5 100644
--- a/drivers/mtd/spinand/Makefile
+++ b/drivers/mtd/spinand/Makefile
@@ -5,6 +5,6 @@
# Core functionality.
obj-$(CONFIG_MTD_SPINAND) += spinand.o
-spinand-objs := spinand_mtd.o spinand_lld.o
+spinand-objs := spinand_mtd.o spinand_lld.o ti-qspi-flash.o
diff --git a/drivers/mtd/spinand/ti-qspi-flash.c
b/drivers/mtd/spinand/ti-qspi-flash.c
new file mode 100644
index 000..dfa6235
--- /dev/null
+++ b/drivers/mtd/spinand/ti-qspi-flash.c
@@ -0,0 +1,373 @@
+/*
+ * MTD SPI driver for spansion s25fl256s (and similar) serial flash chips
+ *
+ * Author: Sourav Poddar, sourav.pod...@ti.com
+ *
+ * Copyright (c) 2013, Texas Instruments.
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+
+#defineCMD_OPCODE_RDSR 0x05/* Read status register */
+#define CMD_OPCODE_FAST_READ 0x0b/* Fast Read */
+#defineMAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip
erase */
+
+#defineSR_WIP 1 /* Write in progress */
+#defineSR_WEL 2 /* Write enable latch */
+
+static u16 addr_width;
+bool fast_read;
+
+static struct nand_ecclayout spinand_oob_0 = {
+ .eccbytes = 0,
+ .eccpos = {},
+ .oobavail = 0,
+ .oobfree = {
+ {.offset = 0,
+ .length = 0}, }
+};
+
+/*
+ * Read the status register, returning its value in the location
+ * Return the status register value.
+ * Returns negative if error occurred.
+*/
+static int read_sr(struct spi_device *spi_nand)
+{
+ ssize_t retval;
+ u8 val;
+ u8 code = CMD_OPCODE_RDSR;
+
+ retval = spi_write_then_read(spi_nand,, 1,, 1);
+
+ if (retval< 0) {
+ dev_info(_nand->dev, "error %d reading SR\n",
+ (int) retval);
+ return retval;
+ }
+
+ return val;
+}
+
+/*
+ * Set write enable latch with Write Enable command.
+ * Returns negative if error occurred.
+*/
+static inline int write_enable(struct spi_device *spi_nand)
+{
+ u8 code = CMD_WR_ENABLE;
+
+ return spi_write_then_read(spi_nand,, 1, NULL, 0);
+}
+
+/*
+ * Send write disble instruction to the chip.
+*/
+static inline int write_disable(struct spi_device *spi_nand)
+{
+ u8 code = CMD_WR_DISABLE;
+
+ return spi_write_then_read(spi_nand,, 1, NULL, 0);
+}
+
+/*
+ * Service routine to read status register until ready, or timeout occurs.
+ * Returns non-zero if error.
+*/
+static int wait_till_ready(struct spi_device *spi_nand)
+{
+ unsigned long deadline;
+ int sr;
+
+ deadline = jiffies + MAX_READY_WAIT_JIFFIES;
+
+ do {
+ sr = read_sr(spi_nand);
+ if (sr< 0)
+ return -1;
+ else if (!(sr& SR_WIP))
+ break;
+
+ cond_resched();
+ } while (!time_after_eq(jiffies, deadline));
+
+ if ((sr& SR_WIP) == 0)
+ return 0;
+
+ return -1;
+}
+
+static inline int spinand_read_id(struct spi_device *spi_nand, u8 *id)
+{
+ u8 code = CMD_READ_ID;
+
+ return spi_write_then_read(spi_nand,, 1, id
Re: [PATCH 0/3] spi/mtd generic framework,ti qspi controller and spansion driver
+ Artem On Wednesday 26 June 2013 01:11 PM, Sourav Poddar wrote: This patch series add support for the generic spi based flash framework(spinand_mtd), which can be used used by any spi based flash device to attach itself to mtd framework. The first patch of this series includes both the generic framework and the the micron device(spinand_lld) making use of the framework. I picked the first patch as a standalone patch. Can split the generic and the lld part based on community suggestions. The second patch is the ti qspi controller driver. The third patch is the spansion s25fl256s driver, making use of the the generic spinand_mtd frameowrk. Test info: Tested the generic framework(spinand_mtd.c) along with patch(2&3) on my dra7xx board for write/erase/read using nand utils. Compile tested(spinand_lld.c). Mona Anonuevo (1): drivers: mtd: spinand: Add generic spinand frameowrk and micron driver. Sourav Poddar (2): drivers: spi: Add qspi flash controller drivers: mtd: spinand: Add qspi spansion flash controller drivers/mtd/Kconfig |2 + drivers/mtd/Makefile|2 + drivers/mtd/spinand/Kconfig | 31 ++ drivers/mtd/spinand/Makefile| 10 + drivers/mtd/spinand/spinand_lld.c | 776 +++ drivers/mtd/spinand/spinand_mtd.c | 690 +++ drivers/mtd/spinand/ti-qspi-flash.c | 373 + drivers/spi/Kconfig |6 + drivers/spi/Makefile|1 + drivers/spi/ti-qspi.c | 352 include/linux/mtd/spinand.h | 155 +++ 11 files changed, 2398 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spinand/Kconfig create mode 100644 drivers/mtd/spinand/Makefile create mode 100644 drivers/mtd/spinand/spinand_lld.c create mode 100644 drivers/mtd/spinand/spinand_mtd.c create mode 100644 drivers/mtd/spinand/ti-qspi-flash.c create mode 100644 drivers/spi/ti-qspi.c create mode 100644 include/linux/mtd/spinand.h -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/3] drivers: mtd: spinand: Add generic spinand frameowrk and micron driver.
+ Artem
On Wednesday 26 June 2013 01:11 PM, Sourav Poddar wrote:
From: Mona Anonuevo
This patch adds support for a generic spinand framework(spinand_mtd.c).
This frameowrk can be used for other spi based flash devices also. The idea
is to have a common model under drivers/mtd, as also present for other no spi
devices(there is a generic framework and device part simply attaches itself to
it.)
The generic frework will be used later by me for a SPI based spansion S25FL256
device.
The patch also contains a micron driver attaching itself to generic framework.
Signed-off-by: Mona Anonuevo
Signed-off-by: Tuan Nguyen
Signed-off-by: Sourav Poddar
[I picked this as a standalone patch, can split it into generic and device part
based on community feedback.]
drivers/mtd/Kconfig |2 +
drivers/mtd/Makefile |2 +
drivers/mtd/spinand/Kconfig | 24 ++
drivers/mtd/spinand/Makefile | 10 +
drivers/mtd/spinand/spinand_lld.c | 776 +
drivers/mtd/spinand/spinand_mtd.c | 690 +
include/linux/mtd/spinand.h | 155
7 files changed, 1659 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/spinand/Kconfig
create mode 100644 drivers/mtd/spinand/Makefile
create mode 100644 drivers/mtd/spinand/spinand_lld.c
create mode 100644 drivers/mtd/spinand/spinand_mtd.c
create mode 100644 include/linux/mtd/spinand.h
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 5fab4e6..c9e6c60 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -318,6 +318,8 @@ source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/onenand/Kconfig"
+source "drivers/mtd/spinand/Kconfig"
+
source "drivers/mtd/lpddr/Kconfig"
source "drivers/mtd/ubi/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 4cfb31e..cce68db 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -32,4 +32,6 @@ inftl-objs:= inftlcore.o inftlmount.o
obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
+obj-y += spinand/
+
obj-$(CONFIG_MTD_UBI) += ubi/
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
new file mode 100644
index 000..38c739f
--- /dev/null
+++ b/drivers/mtd/spinand/Kconfig
@@ -0,0 +1,24 @@
+#
+# linux/drivers/mtd/spinand/Kconfig
+#
+
+menuconfig MTD_SPINAND
+ tristate "SPINAND Device Support"
+ depends on MTD
+ help
+This enables support for accessing Micron SPI NAND flash
+devices.
+
+if MTD_SPINAND
+
+config MTD_SPINAND_ONDIEECC
+ bool "Use SPINAND internal ECC"
+ help
+Internel ECC
+
+config MTD_SPINAND_SWECC
+ bool "Use software ECC"
+ depends on MTD_NAND
+ help
+software ECC
+endif
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
new file mode 100644
index 000..355e726
--- /dev/null
+++ b/drivers/mtd/spinand/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the SPI NAND MTD
+#
+
+# Core functionality.
+obj-$(CONFIG_MTD_SPINAND) += spinand.o
+
+spinand-objs := spinand_mtd.o spinand_lld.o
+
+
diff --git a/drivers/mtd/spinand/spinand_lld.c
b/drivers/mtd/spinand/spinand_lld.c
new file mode 100644
index 000..9f53737
--- /dev/null
+++ b/drivers/mtd/spinand/spinand_lld.c
@@ -0,0 +1,776 @@
+/*
+spinand_lld.c
+
+Copyright (c) 2009-2010 Micron Technology, Inc.
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+
+#define mu_spi_nand_driver_version "Beagle-MTD_01.00_Linux2.6.33_20100507"
+#define SPI_NAND_MICRON_DRIVER_KEY 0x1233567
+
+//
+
+/**
+ OOB area specification layout: Total 32 available free bytes.
+*/
+static struct nand_ecclayout spinand_oob_64 = {
+ .eccbytes = 24,
+ .eccpos = {
+ 1, 2, 3, 4, 5, 6,
+ 17, 18, 19, 20, 21, 22,
+ 33, 34, 35, 36, 37, 38,
+ 49, 50, 51, 52, 53, 54, },
+ .oobavail = 32,
+ .oobfree = {
+ {.offset = 8,
+.length = 8},
+ {.offset = 24,
+.length = 8},
+ {.offset = 40,
+.length = 8},
+ {.offset = 56,
+.length = 8}, }
+
Re: [PATCH 0/3] spi/mtd generic framework,ti qspi controller and spansion driver
+ Artem On Wednesday 26 June 2013 01:11 PM, Sourav Poddar wrote: This patch series add support for the generic spi based flash framework(spinand_mtd), which can be used used by any spi based flash device to attach itself to mtd framework. The first patch of this series includes both the generic framework and the the micron device(spinand_lld) making use of the framework. I picked the first patch as a standalone patch. Can split the generic and the lld part based on community suggestions. The second patch is the ti qspi controller driver. The third patch is the spansion s25fl256s driver, making use of the the generic spinand_mtd frameowrk. Test info: Tested the generic framework(spinand_mtd.c) along with patch(23) on my dra7xx board for write/erase/read using nand utils. Compile tested(spinand_lld.c). Mona Anonuevo (1): drivers: mtd: spinand: Add generic spinand frameowrk and micron driver. Sourav Poddar (2): drivers: spi: Add qspi flash controller drivers: mtd: spinand: Add qspi spansion flash controller drivers/mtd/Kconfig |2 + drivers/mtd/Makefile|2 + drivers/mtd/spinand/Kconfig | 31 ++ drivers/mtd/spinand/Makefile| 10 + drivers/mtd/spinand/spinand_lld.c | 776 +++ drivers/mtd/spinand/spinand_mtd.c | 690 +++ drivers/mtd/spinand/ti-qspi-flash.c | 373 + drivers/spi/Kconfig |6 + drivers/spi/Makefile|1 + drivers/spi/ti-qspi.c | 352 include/linux/mtd/spinand.h | 155 +++ 11 files changed, 2398 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spinand/Kconfig create mode 100644 drivers/mtd/spinand/Makefile create mode 100644 drivers/mtd/spinand/spinand_lld.c create mode 100644 drivers/mtd/spinand/spinand_mtd.c create mode 100644 drivers/mtd/spinand/ti-qspi-flash.c create mode 100644 drivers/spi/ti-qspi.c create mode 100644 include/linux/mtd/spinand.h -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/3] drivers: mtd: spinand: Add generic spinand frameowrk and micron driver.
+ Artem
On Wednesday 26 June 2013 01:11 PM, Sourav Poddar wrote:
From: Mona Anonuevomanonu...@micron.com
This patch adds support for a generic spinand framework(spinand_mtd.c).
This frameowrk can be used for other spi based flash devices also. The idea
is to have a common model under drivers/mtd, as also present for other no spi
devices(there is a generic framework and device part simply attaches itself to
it.)
The generic frework will be used later by me for a SPI based spansion S25FL256
device.
The patch also contains a micron driver attaching itself to generic framework.
Signed-off-by: Mona Anonuevomanonu...@micron.com
Signed-off-by: Tuan Nguyentqngu...@micron.com
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
[I picked this as a standalone patch, can split it into generic and device part
based on community feedback.]
drivers/mtd/Kconfig |2 +
drivers/mtd/Makefile |2 +
drivers/mtd/spinand/Kconfig | 24 ++
drivers/mtd/spinand/Makefile | 10 +
drivers/mtd/spinand/spinand_lld.c | 776 +
drivers/mtd/spinand/spinand_mtd.c | 690 +
include/linux/mtd/spinand.h | 155
7 files changed, 1659 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/spinand/Kconfig
create mode 100644 drivers/mtd/spinand/Makefile
create mode 100644 drivers/mtd/spinand/spinand_lld.c
create mode 100644 drivers/mtd/spinand/spinand_mtd.c
create mode 100644 include/linux/mtd/spinand.h
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 5fab4e6..c9e6c60 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -318,6 +318,8 @@ source drivers/mtd/nand/Kconfig
source drivers/mtd/onenand/Kconfig
+source drivers/mtd/spinand/Kconfig
+
source drivers/mtd/lpddr/Kconfig
source drivers/mtd/ubi/Kconfig
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 4cfb31e..cce68db 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -32,4 +32,6 @@ inftl-objs:= inftlcore.o inftlmount.o
obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
+obj-y += spinand/
+
obj-$(CONFIG_MTD_UBI) += ubi/
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
new file mode 100644
index 000..38c739f
--- /dev/null
+++ b/drivers/mtd/spinand/Kconfig
@@ -0,0 +1,24 @@
+#
+# linux/drivers/mtd/spinand/Kconfig
+#
+
+menuconfig MTD_SPINAND
+ tristate SPINAND Device Support
+ depends on MTD
+ help
+This enables support for accessing Micron SPI NAND flash
+devices.
+
+if MTD_SPINAND
+
+config MTD_SPINAND_ONDIEECC
+ bool Use SPINAND internal ECC
+ help
+Internel ECC
+
+config MTD_SPINAND_SWECC
+ bool Use software ECC
+ depends on MTD_NAND
+ help
+software ECC
+endif
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
new file mode 100644
index 000..355e726
--- /dev/null
+++ b/drivers/mtd/spinand/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the SPI NAND MTD
+#
+
+# Core functionality.
+obj-$(CONFIG_MTD_SPINAND) += spinand.o
+
+spinand-objs := spinand_mtd.o spinand_lld.o
+
+
diff --git a/drivers/mtd/spinand/spinand_lld.c
b/drivers/mtd/spinand/spinand_lld.c
new file mode 100644
index 000..9f53737
--- /dev/null
+++ b/drivers/mtd/spinand/spinand_lld.c
@@ -0,0 +1,776 @@
+/*
+spinand_lld.c
+
+Copyright (c) 2009-2010 Micron Technology, Inc.
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+*/
+
+#includelinux/init.h
+#includelinux/module.h
+#includelinux/device.h
+#includelinux/interrupt.h
+#includelinux/mutex.h
+#includelinux/math64.h
+
+#includelinux/mtd/mtd.h
+#includelinux/mtd/partitions.h
+#includelinux/mtd/spinand.h
+
+#includelinux/spi/spi.h
+#includelinux/spi/flash.h
+
+#define mu_spi_nand_driver_version Beagle-MTD_01.00_Linux2.6.33_20100507
+#define SPI_NAND_MICRON_DRIVER_KEY 0x1233567
+
+//
+
+/**
+ OOB area specification layout: Total 32 available free bytes.
+*/
+static struct nand_ecclayout spinand_oob_64 = {
+ .eccbytes = 24,
+ .eccpos = {
+ 1, 2, 3, 4, 5, 6,
+ 17, 18, 19, 20, 21, 22,
+ 33, 34, 35, 36, 37, 38,
+ 49, 50, 51, 52, 53, 54, },
+ .oobavail = 32,
+ .oobfree = {
+ {.offset = 8,
+.length = 8},
+ {.offset = 24
Re: [PATCH 3/3] drivers: mtd: spinand: Add qspi spansion flash controller
+ Artem
On Wednesday 26 June 2013 01:11 PM, Sourav Poddar wrote:
The patch adds support for spansion s25fl256s spi flash controller.
Currently, the patch supports only SPI based transaction.
As, the qspi to which flash is attached supports memory mapped interface,
support will be added in future for memory mapped transactions also.
This driver gets attached to the generic spinand mtd framework proposed in the
first patch of the series.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spinand/Kconfig |7 +
drivers/mtd/spinand/Makefile|2 +-
drivers/mtd/spinand/ti-qspi-flash.c | 373 +++
3 files changed, 381 insertions(+), 1 deletions(-)
create mode 100644 drivers/mtd/spinand/ti-qspi-flash.c
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
index 38c739f..1342de3 100644
--- a/drivers/mtd/spinand/Kconfig
+++ b/drivers/mtd/spinand/Kconfig
@@ -16,6 +16,13 @@ config MTD_SPINAND_ONDIEECC
help
Internel ECC
+config MTD_S25FL256S
+ tristate Support spansion memory mapped SPI Flash chips
+ depends on SPI_MASTER
+ help
+ This enables access to spansion QSPI flash chips, which used
+ memory mapped interface used for program and data storage.
+
config MTD_SPINAND_SWECC
bool Use software ECC
depends on MTD_NAND
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
index 355e726..8ad0dd5 100644
--- a/drivers/mtd/spinand/Makefile
+++ b/drivers/mtd/spinand/Makefile
@@ -5,6 +5,6 @@
# Core functionality.
obj-$(CONFIG_MTD_SPINAND) += spinand.o
-spinand-objs := spinand_mtd.o spinand_lld.o
+spinand-objs := spinand_mtd.o spinand_lld.o ti-qspi-flash.o
diff --git a/drivers/mtd/spinand/ti-qspi-flash.c
b/drivers/mtd/spinand/ti-qspi-flash.c
new file mode 100644
index 000..dfa6235
--- /dev/null
+++ b/drivers/mtd/spinand/ti-qspi-flash.c
@@ -0,0 +1,373 @@
+/*
+ * MTD SPI driver for spansion s25fl256s (and similar) serial flash chips
+ *
+ * Author: Sourav Poddar, sourav.pod...@ti.com
+ *
+ * Copyright (c) 2013, Texas Instruments.
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#includelinux/init.h
+#includelinux/err.h
+#includelinux/errno.h
+#includelinux/module.h
+#includelinux/device.h
+#includelinux/interrupt.h
+#includelinux/mutex.h
+#includelinux/math64.h
+#includelinux/slab.h
+#includelinux/sched.h
+#includelinux/mod_devicetable.h
+
+#includelinux/mtd/mtd.h
+#includelinux/mtd/partitions.h
+#includelinux/of_platform.h
+
+#includelinux/spi/spi.h
+#includelinux/mtd/spinand.h
+
+#defineCMD_OPCODE_RDSR 0x05/* Read status register */
+#define CMD_OPCODE_FAST_READ 0x0b/* Fast Read */
+#defineMAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip
erase */
+
+#defineSR_WIP 1 /* Write in progress */
+#defineSR_WEL 2 /* Write enable latch */
+
+static u16 addr_width;
+bool fast_read;
+
+static struct nand_ecclayout spinand_oob_0 = {
+ .eccbytes = 0,
+ .eccpos = {},
+ .oobavail = 0,
+ .oobfree = {
+ {.offset = 0,
+ .length = 0}, }
+};
+
+/*
+ * Read the status register, returning its value in the location
+ * Return the status register value.
+ * Returns negative if error occurred.
+*/
+static int read_sr(struct spi_device *spi_nand)
+{
+ ssize_t retval;
+ u8 val;
+ u8 code = CMD_OPCODE_RDSR;
+
+ retval = spi_write_then_read(spi_nand,code, 1,val, 1);
+
+ if (retval 0) {
+ dev_info(spi_nand-dev, error %d reading SR\n,
+ (int) retval);
+ return retval;
+ }
+
+ return val;
+}
+
+/*
+ * Set write enable latch with Write Enable command.
+ * Returns negative if error occurred.
+*/
+static inline int write_enable(struct spi_device *spi_nand)
+{
+ u8 code = CMD_WR_ENABLE;
+
+ return spi_write_then_read(spi_nand,code, 1, NULL, 0);
+}
+
+/*
+ * Send write disble instruction to the chip.
+*/
+static inline int write_disable(struct spi_device *spi_nand)
+{
+ u8 code = CMD_WR_DISABLE;
+
+ return spi_write_then_read(spi_nand,code, 1, NULL, 0);
+}
+
+/*
+ * Service routine to read status register until ready, or timeout occurs.
+ * Returns non-zero if error.
+*/
+static int wait_till_ready(struct spi_device *spi_nand)
+{
+ unsigned long deadline;
+ int sr;
+
+ deadline = jiffies + MAX_READY_WAIT_JIFFIES;
+
+ do {
+ sr = read_sr(spi_nand);
+ if (sr 0)
+ return -1;
+ else if (!(sr SR_WIP))
+ break;
+
+ cond_resched();
+ } while (!time_after_eq(jiffies, deadline));
+
+ if ((sr
Re: [PATCH 2/3] drivers: spi: Add qspi flash controller
+ Artem
On Wednesday 26 June 2013 01:11 PM, Sourav Poddar wrote:
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/spi/Kconfig |6 +
drivers/spi/Makefile |1 +
drivers/spi/ti-qspi.c | 352 +
3 files changed, 359 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti-qspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..29a363b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,12 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate DRA7xxx QSPI controller support
+ depends on ARCH_OMAP2PLUS
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+
config SPI_OMAP_100K
tristate OMAP SPI 100K
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX)+= spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += ti-qspi.o
obj-$(CONFIG_SPI_ORION) += spi-orion.o
obj-$(CONFIG_SPI_PL022) += spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/ti-qspi.c b/drivers/spi/ti-qspi.c
new file mode 100644
index 000..b33646a
--- /dev/null
+++ b/drivers/spi/ti-qspi.c
@@ -0,0 +1,352 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#includelinux/kernel.h
+#includelinux/init.h
+#includelinux/interrupt.h
+#includelinux/module.h
+#includelinux/device.h
+#includelinux/delay.h
+#includelinux/dma-mapping.h
+#includelinux/dmaengine.h
+#includelinux/omap-dma.h
+#includelinux/platform_device.h
+#includelinux/err.h
+#includelinux/clk.h
+#includelinux/io.h
+#includelinux/slab.h
+#includelinux/pm_runtime.h
+#includelinux/of.h
+#includelinux/of_device.h
+#includelinux/pinctrl/consumer.h
+
+#includelinux/spi/spi.h
+
+struct dra7xxx_qspi {
+ struct spi_master *master;
+ void __iomem*base;
+ int device_type;
+ struct device *dev;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define QSPI_SYSCONFIG (0x10)
+#define QSPI_INTR_STATUS_RAW_SET (0x20)
+#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
+#define QSPI_INTR_ENABLE_SET_REG (0x28)
+#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
+#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
+#define QSPI_SPI_DC_REG(0x44)
+#define QSPI_SPI_CMD_REG (0x48)
+#define QSPI_SPI_STATUS_REG(0x4c)
+#define QSPI_SPI_DATA_REG (0x50)
+#define QSPI_SPI_SETUP0_REG(0x54)
+#define QSPI_SPI_SWITCH_REG(0x64)
+#define QSPI_SPI_SETUP1_REG(0x58)
+#define QSPI_SPI_SETUP2_REG(0x5c)
+#define QSPI_SPI_SETUP3_REG(0x60)
+#define QSPI_SPI_DATA_REG_1(0x68)
+#define QSPI_SPI_DATA_REG_2(0x6c)
+#define QSPI_SPI_DATA_REG_3(0x70)
+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_RD_QUAD (7 16)
+#define QSPI_INVAL
Re: [PATCH 1/3] drivers: mtd: spinand: Add generic spinand frameowrk and micron driver.
Hi Kamlakant, On Wednesday 26 June 2013 08:52 PM, Kamlakant Patel wrote: On Wed, Jun 26, 2013 at 01:11:10PM +0530, Sourav Poddar wrote: From: Mona Anonuevo This patch adds support for a generic spinand framework(spinand_mtd.c). This frameowrk can be used for other spi based flash devices also. The idea is to have a common model under drivers/mtd, as also present for other no spi devices(there is a generic framework and device part simply attaches itself to it.) The generic frework will be used later by me for a SPI based spansion S25FL256 device. The patch also contains a micron driver attaching itself to generic framework. Signed-off-by: Mona Anonuevo Signed-off-by: Tuan Nguyen Signed-off-by: Sourav Poddar [I picked this as a standalone patch, can split it into generic and device part based on community feedback.] drivers/mtd/Kconfig |2 + drivers/mtd/Makefile |2 + drivers/mtd/spinand/Kconfig | 24 ++ drivers/mtd/spinand/Makefile | 10 + drivers/mtd/spinand/spinand_lld.c | 776 + drivers/mtd/spinand/spinand_mtd.c | 690 + include/linux/mtd/spinand.h | 155 7 files changed, 1659 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spinand/Kconfig create mode 100644 drivers/mtd/spinand/Makefile create mode 100644 drivers/mtd/spinand/spinand_lld.c create mode 100644 drivers/mtd/spinand/spinand_mtd.c create mode 100644 include/linux/mtd/spinand.h I am working on Micron SPINAND(Micron MT29F1G01ZACH). I tried this patch, but it's not working. It is throwing following error message while mounting: [ 260.232000] jffs2: cannot read OOB for EB at , requested 8 bytes, read 0 bytes, error -22 mount: mounting /dev/mtdblock5 on /mnt/ failed: Input/output error I am working on it to fix into the driver, will send an updated patch with the fix. Thanks for replying on this. Since, this patch is already posted, I think it will be better if you post the delta fix on top of this patch. Thanks, Kamlakant Patel -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/3] drivers: mtd: spinand: Add qspi spansion flash controller
The patch adds support for spansion s25fl256s spi flash controller.
Currently, the patch supports only SPI based transaction.
As, the qspi to which flash is attached supports memory mapped interface,
support will be added in future for memory mapped transactions also.
This driver gets attached to the generic spinand mtd framework proposed in the
first patch of the series.
Signed-off-by: Sourav Poddar
---
drivers/mtd/spinand/Kconfig |7 +
drivers/mtd/spinand/Makefile|2 +-
drivers/mtd/spinand/ti-qspi-flash.c | 373 +++
3 files changed, 381 insertions(+), 1 deletions(-)
create mode 100644 drivers/mtd/spinand/ti-qspi-flash.c
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
index 38c739f..1342de3 100644
--- a/drivers/mtd/spinand/Kconfig
+++ b/drivers/mtd/spinand/Kconfig
@@ -16,6 +16,13 @@ config MTD_SPINAND_ONDIEECC
help
Internel ECC
+config MTD_S25FL256S
+ tristate "Support spansion memory mapped SPI Flash chips"
+ depends on SPI_MASTER
+ help
+ This enables access to spansion QSPI flash chips, which used
+ memory mapped interface used for program and data storage.
+
config MTD_SPINAND_SWECC
bool "Use software ECC"
depends on MTD_NAND
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
index 355e726..8ad0dd5 100644
--- a/drivers/mtd/spinand/Makefile
+++ b/drivers/mtd/spinand/Makefile
@@ -5,6 +5,6 @@
# Core functionality.
obj-$(CONFIG_MTD_SPINAND) += spinand.o
-spinand-objs := spinand_mtd.o spinand_lld.o
+spinand-objs := spinand_mtd.o spinand_lld.o ti-qspi-flash.o
diff --git a/drivers/mtd/spinand/ti-qspi-flash.c
b/drivers/mtd/spinand/ti-qspi-flash.c
new file mode 100644
index 000..dfa6235
--- /dev/null
+++ b/drivers/mtd/spinand/ti-qspi-flash.c
@@ -0,0 +1,373 @@
+/*
+ * MTD SPI driver for spansion s25fl256s (and similar) serial flash chips
+ *
+ * Author: Sourav Poddar, sourav.pod...@ti.com
+ *
+ * Copyright (c) 2013, Texas Instruments.
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+
+#defineCMD_OPCODE_RDSR 0x05/* Read status register */
+#define CMD_OPCODE_FAST_READ 0x0b/* Fast Read */
+#defineMAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip
erase */
+
+#defineSR_WIP 1 /* Write in progress */
+#defineSR_WEL 2 /* Write enable latch */
+
+static u16 addr_width;
+bool fast_read;
+
+static struct nand_ecclayout spinand_oob_0 = {
+ .eccbytes = 0,
+ .eccpos = {},
+ .oobavail = 0,
+ .oobfree = {
+ {.offset = 0,
+ .length = 0}, }
+};
+
+/*
+ * Read the status register, returning its value in the location
+ * Return the status register value.
+ * Returns negative if error occurred.
+*/
+static int read_sr(struct spi_device *spi_nand)
+{
+ ssize_t retval;
+ u8 val;
+ u8 code = CMD_OPCODE_RDSR;
+
+ retval = spi_write_then_read(spi_nand, , 1, , 1);
+
+ if (retval < 0) {
+ dev_info(_nand->dev, "error %d reading SR\n",
+ (int) retval);
+ return retval;
+ }
+
+ return val;
+}
+
+/*
+ * Set write enable latch with Write Enable command.
+ * Returns negative if error occurred.
+*/
+static inline int write_enable(struct spi_device *spi_nand)
+{
+ u8 code = CMD_WR_ENABLE;
+
+ return spi_write_then_read(spi_nand, , 1, NULL, 0);
+}
+
+/*
+ * Send write disble instruction to the chip.
+*/
+static inline int write_disable(struct spi_device *spi_nand)
+{
+ u8 code = CMD_WR_DISABLE;
+
+ return spi_write_then_read(spi_nand, , 1, NULL, 0);
+}
+
+/*
+ * Service routine to read status register until ready, or timeout occurs.
+ * Returns non-zero if error.
+*/
+static int wait_till_ready(struct spi_device *spi_nand)
+{
+ unsigned long deadline;
+ int sr;
+
+ deadline = jiffies + MAX_READY_WAIT_JIFFIES;
+
+ do {
+ sr = read_sr(spi_nand);
+ if (sr < 0)
+ return -1;
+ else if (!(sr & SR_WIP))
+ break;
+
+ cond_resched();
+ } while (!time_after_eq(jiffies, deadline));
+
+ if ((sr & SR_WIP) == 0)
+ return 0;
+
+ return -1;
+}
+
+static inline int spinand_read_id(struct spi_device *spi_nand, u8 *id)
+{
+ u8 code = CMD_READ_ID;
+
+ return spi_write_then_read(spi_nand, , 1, id, sizeof(id));
+}
+
+static
[PATCH 1/3] drivers: mtd: spinand: Add generic spinand frameowrk and micron driver.
From: Mona Anonuevo
This patch adds support for a generic spinand framework(spinand_mtd.c).
This frameowrk can be used for other spi based flash devices also. The idea
is to have a common model under drivers/mtd, as also present for other no spi
devices(there is a generic framework and device part simply attaches itself to
it.)
The generic frework will be used later by me for a SPI based spansion S25FL256
device.
The patch also contains a micron driver attaching itself to generic framework.
Signed-off-by: Mona Anonuevo
Signed-off-by: Tuan Nguyen
Signed-off-by: Sourav Poddar
[I picked this as a standalone patch, can split it into generic and device part
based on community feedback.]
drivers/mtd/Kconfig |2 +
drivers/mtd/Makefile |2 +
drivers/mtd/spinand/Kconfig | 24 ++
drivers/mtd/spinand/Makefile | 10 +
drivers/mtd/spinand/spinand_lld.c | 776 +
drivers/mtd/spinand/spinand_mtd.c | 690 +
include/linux/mtd/spinand.h | 155
7 files changed, 1659 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/spinand/Kconfig
create mode 100644 drivers/mtd/spinand/Makefile
create mode 100644 drivers/mtd/spinand/spinand_lld.c
create mode 100644 drivers/mtd/spinand/spinand_mtd.c
create mode 100644 include/linux/mtd/spinand.h
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 5fab4e6..c9e6c60 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -318,6 +318,8 @@ source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/onenand/Kconfig"
+source "drivers/mtd/spinand/Kconfig"
+
source "drivers/mtd/lpddr/Kconfig"
source "drivers/mtd/ubi/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 4cfb31e..cce68db 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -32,4 +32,6 @@ inftl-objs:= inftlcore.o inftlmount.o
obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
+obj-y += spinand/
+
obj-$(CONFIG_MTD_UBI) += ubi/
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
new file mode 100644
index 000..38c739f
--- /dev/null
+++ b/drivers/mtd/spinand/Kconfig
@@ -0,0 +1,24 @@
+#
+# linux/drivers/mtd/spinand/Kconfig
+#
+
+menuconfig MTD_SPINAND
+ tristate "SPINAND Device Support"
+ depends on MTD
+ help
+This enables support for accessing Micron SPI NAND flash
+devices.
+
+if MTD_SPINAND
+
+config MTD_SPINAND_ONDIEECC
+ bool "Use SPINAND internal ECC"
+ help
+Internel ECC
+
+config MTD_SPINAND_SWECC
+ bool "Use software ECC"
+ depends on MTD_NAND
+ help
+software ECC
+endif
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
new file mode 100644
index 000..355e726
--- /dev/null
+++ b/drivers/mtd/spinand/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the SPI NAND MTD
+#
+
+# Core functionality.
+obj-$(CONFIG_MTD_SPINAND) += spinand.o
+
+spinand-objs := spinand_mtd.o spinand_lld.o
+
+
diff --git a/drivers/mtd/spinand/spinand_lld.c
b/drivers/mtd/spinand/spinand_lld.c
new file mode 100644
index 000..9f53737
--- /dev/null
+++ b/drivers/mtd/spinand/spinand_lld.c
@@ -0,0 +1,776 @@
+/*
+spinand_lld.c
+
+Copyright (c) 2009-2010 Micron Technology, Inc.
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+
+#define mu_spi_nand_driver_version "Beagle-MTD_01.00_Linux2.6.33_20100507"
+#define SPI_NAND_MICRON_DRIVER_KEY 0x1233567
+
+//
+
+/**
+ OOB area specification layout: Total 32 available free bytes.
+*/
+static struct nand_ecclayout spinand_oob_64 = {
+ .eccbytes = 24,
+ .eccpos = {
+ 1, 2, 3, 4, 5, 6,
+ 17, 18, 19, 20, 21, 22,
+ 33, 34, 35, 36, 37, 38,
+ 49, 50, 51, 52, 53, 54, },
+ .oobavail = 32,
+ .oobfree = {
+ {.offset = 8,
+.length = 8},
+ {.offset = 24,
+.length = 8},
+ {.offset = 40,
+.length = 8},
+ {.offset = 56,
+.length = 8}, }
+};
+/**
+ * spinand_cmd - to process a command to send to the SP
[PATCH 0/3] spi/mtd generic framework,ti qspi controller and spansion driver
This patch series add support for the generic spi based flash framework(spinand_mtd), which can be used used by any spi based flash device to attach itself to mtd framework. The first patch of this series includes both the generic framework and the the micron device(spinand_lld) making use of the framework. I picked the first patch as a standalone patch. Can split the generic and the lld part based on community suggestions. The second patch is the ti qspi controller driver. The third patch is the spansion s25fl256s driver, making use of the the generic spinand_mtd frameowrk. Test info: Tested the generic framework(spinand_mtd.c) along with patch(2&3) on my dra7xx board for write/erase/read using nand utils. Compile tested(spinand_lld.c). Mona Anonuevo (1): drivers: mtd: spinand: Add generic spinand frameowrk and micron driver. Sourav Poddar (2): drivers: spi: Add qspi flash controller drivers: mtd: spinand: Add qspi spansion flash controller drivers/mtd/Kconfig |2 + drivers/mtd/Makefile|2 + drivers/mtd/spinand/Kconfig | 31 ++ drivers/mtd/spinand/Makefile| 10 + drivers/mtd/spinand/spinand_lld.c | 776 +++ drivers/mtd/spinand/spinand_mtd.c | 690 +++ drivers/mtd/spinand/ti-qspi-flash.c | 373 + drivers/spi/Kconfig |6 + drivers/spi/Makefile|1 + drivers/spi/ti-qspi.c | 352 include/linux/mtd/spinand.h | 155 +++ 11 files changed, 2398 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spinand/Kconfig create mode 100644 drivers/mtd/spinand/Makefile create mode 100644 drivers/mtd/spinand/spinand_lld.c create mode 100644 drivers/mtd/spinand/spinand_mtd.c create mode 100644 drivers/mtd/spinand/ti-qspi-flash.c create mode 100644 drivers/spi/ti-qspi.c create mode 100644 include/linux/mtd/spinand.h -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/3] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar
---
drivers/spi/Kconfig |6 +
drivers/spi/Makefile |1 +
drivers/spi/ti-qspi.c | 352 +
3 files changed, 359 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti-qspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..29a363b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,12 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate "DRA7xxx QSPI controller support"
+ depends on ARCH_OMAP2PLUS
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+
config SPI_OMAP_100K
tristate "OMAP SPI 100K"
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/ti-qspi.c b/drivers/spi/ti-qspi.c
new file mode 100644
index 000..b33646a
--- /dev/null
+++ b/drivers/spi/ti-qspi.c
@@ -0,0 +1,352 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct dra7xxx_qspi {
+ struct spi_master *master;
+ void __iomem*base;
+ int device_type;
+ struct device *dev;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define QSPI_SYSCONFIG (0x10)
+#define QSPI_INTR_STATUS_RAW_SET (0x20)
+#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
+#define QSPI_INTR_ENABLE_SET_REG (0x28)
+#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
+#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
+#define QSPI_SPI_DC_REG(0x44)
+#define QSPI_SPI_CMD_REG (0x48)
+#define QSPI_SPI_STATUS_REG(0x4c)
+#define QSPI_SPI_DATA_REG (0x50)
+#define QSPI_SPI_SETUP0_REG(0x54)
+#define QSPI_SPI_SWITCH_REG(0x64)
+#define QSPI_SPI_SETUP1_REG(0x58)
+#define QSPI_SPI_SETUP2_REG(0x5c)
+#define QSPI_SPI_SETUP3_REG(0x60)
+#define QSPI_SPI_DATA_REG_1(0x68)
+#define QSPI_SPI_DATA_REG_2(0x6c)
+#define QSPI_SPI_DATA_REG_3(0x70)
+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 << 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n << 28)
+#define QSPI_WLEN(n) ((n-1) << 19)
+#define QSPI_3_PIN (1 << 18)
+#define QSPI_RD_SNGL (1 << 16)
+#define QSPI_WR_SNGL (2 << 16)
+#define QSPI_RD_QUAD (7 << 16)
+#define QSPI_INVAL (4 << 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m << (3 + n*8))
+#define QSPI_CKPHA(n) (1 << (2 + n*8))
+#define QSPI_CSPOL(n) (1 << (1 + n*8))
+#define QSPI_CKPOL(n)
[PATCH 2/3] drivers: spi: Add qspi flash controller
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/Kconfig |6 +
drivers/spi/Makefile |1 +
drivers/spi/ti-qspi.c | 352 +
3 files changed, 359 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti-qspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 92a9345..29a363b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,12 @@ config SPI_OMAP24XX
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI) modules.
+config QSPI_DRA7xxx
+ tristate DRA7xxx QSPI controller support
+ depends on ARCH_OMAP2PLUS
+ help
+ QSPI master controller for DRA7xxx used for flash devices.
+
config SPI_OMAP_100K
tristate OMAP SPI 100K
depends on ARCH_OMAP850 || ARCH_OMAP730
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09..ea14eff 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
obj-$(CONFIG_SPI_OMAP_100K)+= spi-omap-100k.o
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
+obj-$(CONFIG_QSPI_DRA7xxx) += ti-qspi.o
obj-$(CONFIG_SPI_ORION)+= spi-orion.o
obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
diff --git a/drivers/spi/ti-qspi.c b/drivers/spi/ti-qspi.c
new file mode 100644
index 000..b33646a
--- /dev/null
+++ b/drivers/spi/ti-qspi.c
@@ -0,0 +1,352 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/device.h
+#include linux/delay.h
+#include linux/dma-mapping.h
+#include linux/dmaengine.h
+#include linux/omap-dma.h
+#include linux/platform_device.h
+#include linux/err.h
+#include linux/clk.h
+#include linux/io.h
+#include linux/slab.h
+#include linux/pm_runtime.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/consumer.h
+
+#include linux/spi/spi.h
+
+struct dra7xxx_qspi {
+ struct spi_master *master;
+ void __iomem*base;
+ int device_type;
+ struct device *dev;
+ u32 spi_max_frequency;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_PID (0x0)
+#define QSPI_SYSCONFIG (0x10)
+#define QSPI_INTR_STATUS_RAW_SET (0x20)
+#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
+#define QSPI_INTR_ENABLE_SET_REG (0x28)
+#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
+#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
+#define QSPI_SPI_DC_REG(0x44)
+#define QSPI_SPI_CMD_REG (0x48)
+#define QSPI_SPI_STATUS_REG(0x4c)
+#define QSPI_SPI_DATA_REG (0x50)
+#define QSPI_SPI_SETUP0_REG(0x54)
+#define QSPI_SPI_SWITCH_REG(0x64)
+#define QSPI_SPI_SETUP1_REG(0x58)
+#define QSPI_SPI_SETUP2_REG(0x5c)
+#define QSPI_SPI_SETUP3_REG(0x60)
+#define QSPI_SPI_DATA_REG_1(0x68)
+#define QSPI_SPI_DATA_REG_2(0x6c)
+#define QSPI_SPI_DATA_REG_3(0x70)
+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_RD_QUAD (7 16)
+#define QSPI_INVAL (4 16)
+
+/* Device Control */
+#define
[PATCH 0/3] spi/mtd generic framework,ti qspi controller and spansion driver
This patch series add support for the generic spi based flash framework(spinand_mtd), which can be used used by any spi based flash device to attach itself to mtd framework. The first patch of this series includes both the generic framework and the the micron device(spinand_lld) making use of the framework. I picked the first patch as a standalone patch. Can split the generic and the lld part based on community suggestions. The second patch is the ti qspi controller driver. The third patch is the spansion s25fl256s driver, making use of the the generic spinand_mtd frameowrk. Test info: Tested the generic framework(spinand_mtd.c) along with patch(23) on my dra7xx board for write/erase/read using nand utils. Compile tested(spinand_lld.c). Mona Anonuevo (1): drivers: mtd: spinand: Add generic spinand frameowrk and micron driver. Sourav Poddar (2): drivers: spi: Add qspi flash controller drivers: mtd: spinand: Add qspi spansion flash controller drivers/mtd/Kconfig |2 + drivers/mtd/Makefile|2 + drivers/mtd/spinand/Kconfig | 31 ++ drivers/mtd/spinand/Makefile| 10 + drivers/mtd/spinand/spinand_lld.c | 776 +++ drivers/mtd/spinand/spinand_mtd.c | 690 +++ drivers/mtd/spinand/ti-qspi-flash.c | 373 + drivers/spi/Kconfig |6 + drivers/spi/Makefile|1 + drivers/spi/ti-qspi.c | 352 include/linux/mtd/spinand.h | 155 +++ 11 files changed, 2398 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spinand/Kconfig create mode 100644 drivers/mtd/spinand/Makefile create mode 100644 drivers/mtd/spinand/spinand_lld.c create mode 100644 drivers/mtd/spinand/spinand_mtd.c create mode 100644 drivers/mtd/spinand/ti-qspi-flash.c create mode 100644 drivers/spi/ti-qspi.c create mode 100644 include/linux/mtd/spinand.h -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/3] drivers: mtd: spinand: Add generic spinand frameowrk and micron driver.
From: Mona Anonuevo manonu...@micron.com
This patch adds support for a generic spinand framework(spinand_mtd.c).
This frameowrk can be used for other spi based flash devices also. The idea
is to have a common model under drivers/mtd, as also present for other no spi
devices(there is a generic framework and device part simply attaches itself to
it.)
The generic frework will be used later by me for a SPI based spansion S25FL256
device.
The patch also contains a micron driver attaching itself to generic framework.
Signed-off-by: Mona Anonuevo manonu...@micron.com
Signed-off-by: Tuan Nguyen tqngu...@micron.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[I picked this as a standalone patch, can split it into generic and device part
based on community feedback.]
drivers/mtd/Kconfig |2 +
drivers/mtd/Makefile |2 +
drivers/mtd/spinand/Kconfig | 24 ++
drivers/mtd/spinand/Makefile | 10 +
drivers/mtd/spinand/spinand_lld.c | 776 +
drivers/mtd/spinand/spinand_mtd.c | 690 +
include/linux/mtd/spinand.h | 155
7 files changed, 1659 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/spinand/Kconfig
create mode 100644 drivers/mtd/spinand/Makefile
create mode 100644 drivers/mtd/spinand/spinand_lld.c
create mode 100644 drivers/mtd/spinand/spinand_mtd.c
create mode 100644 include/linux/mtd/spinand.h
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 5fab4e6..c9e6c60 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -318,6 +318,8 @@ source drivers/mtd/nand/Kconfig
source drivers/mtd/onenand/Kconfig
+source drivers/mtd/spinand/Kconfig
+
source drivers/mtd/lpddr/Kconfig
source drivers/mtd/ubi/Kconfig
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 4cfb31e..cce68db 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -32,4 +32,6 @@ inftl-objs:= inftlcore.o inftlmount.o
obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
+obj-y += spinand/
+
obj-$(CONFIG_MTD_UBI) += ubi/
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
new file mode 100644
index 000..38c739f
--- /dev/null
+++ b/drivers/mtd/spinand/Kconfig
@@ -0,0 +1,24 @@
+#
+# linux/drivers/mtd/spinand/Kconfig
+#
+
+menuconfig MTD_SPINAND
+ tristate SPINAND Device Support
+ depends on MTD
+ help
+This enables support for accessing Micron SPI NAND flash
+devices.
+
+if MTD_SPINAND
+
+config MTD_SPINAND_ONDIEECC
+ bool Use SPINAND internal ECC
+ help
+Internel ECC
+
+config MTD_SPINAND_SWECC
+ bool Use software ECC
+ depends on MTD_NAND
+ help
+software ECC
+endif
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
new file mode 100644
index 000..355e726
--- /dev/null
+++ b/drivers/mtd/spinand/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the SPI NAND MTD
+#
+
+# Core functionality.
+obj-$(CONFIG_MTD_SPINAND) += spinand.o
+
+spinand-objs := spinand_mtd.o spinand_lld.o
+
+
diff --git a/drivers/mtd/spinand/spinand_lld.c
b/drivers/mtd/spinand/spinand_lld.c
new file mode 100644
index 000..9f53737
--- /dev/null
+++ b/drivers/mtd/spinand/spinand_lld.c
@@ -0,0 +1,776 @@
+/*
+spinand_lld.c
+
+Copyright (c) 2009-2010 Micron Technology, Inc.
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+*/
+
+#include linux/init.h
+#include linux/module.h
+#include linux/device.h
+#include linux/interrupt.h
+#include linux/mutex.h
+#include linux/math64.h
+
+#include linux/mtd/mtd.h
+#include linux/mtd/partitions.h
+#include linux/mtd/spinand.h
+
+#include linux/spi/spi.h
+#include linux/spi/flash.h
+
+#define mu_spi_nand_driver_version Beagle-MTD_01.00_Linux2.6.33_20100507
+#define SPI_NAND_MICRON_DRIVER_KEY 0x1233567
+
+//
+
+/**
+ OOB area specification layout: Total 32 available free bytes.
+*/
+static struct nand_ecclayout spinand_oob_64 = {
+ .eccbytes = 24,
+ .eccpos = {
+ 1, 2, 3, 4, 5, 6,
+ 17, 18, 19, 20, 21, 22,
+ 33, 34, 35, 36, 37, 38,
+ 49, 50, 51, 52, 53, 54, },
+ .oobavail = 32,
+ .oobfree = {
+ {.offset = 8,
+.length = 8},
+ {.offset = 24,
+.length = 8},
+ {.offset = 40
[PATCH 3/3] drivers: mtd: spinand: Add qspi spansion flash controller
The patch adds support for spansion s25fl256s spi flash controller.
Currently, the patch supports only SPI based transaction.
As, the qspi to which flash is attached supports memory mapped interface,
support will be added in future for memory mapped transactions also.
This driver gets attached to the generic spinand mtd framework proposed in the
first patch of the series.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/spinand/Kconfig |7 +
drivers/mtd/spinand/Makefile|2 +-
drivers/mtd/spinand/ti-qspi-flash.c | 373 +++
3 files changed, 381 insertions(+), 1 deletions(-)
create mode 100644 drivers/mtd/spinand/ti-qspi-flash.c
diff --git a/drivers/mtd/spinand/Kconfig b/drivers/mtd/spinand/Kconfig
index 38c739f..1342de3 100644
--- a/drivers/mtd/spinand/Kconfig
+++ b/drivers/mtd/spinand/Kconfig
@@ -16,6 +16,13 @@ config MTD_SPINAND_ONDIEECC
help
Internel ECC
+config MTD_S25FL256S
+ tristate Support spansion memory mapped SPI Flash chips
+ depends on SPI_MASTER
+ help
+ This enables access to spansion QSPI flash chips, which used
+ memory mapped interface used for program and data storage.
+
config MTD_SPINAND_SWECC
bool Use software ECC
depends on MTD_NAND
diff --git a/drivers/mtd/spinand/Makefile b/drivers/mtd/spinand/Makefile
index 355e726..8ad0dd5 100644
--- a/drivers/mtd/spinand/Makefile
+++ b/drivers/mtd/spinand/Makefile
@@ -5,6 +5,6 @@
# Core functionality.
obj-$(CONFIG_MTD_SPINAND) += spinand.o
-spinand-objs := spinand_mtd.o spinand_lld.o
+spinand-objs := spinand_mtd.o spinand_lld.o ti-qspi-flash.o
diff --git a/drivers/mtd/spinand/ti-qspi-flash.c
b/drivers/mtd/spinand/ti-qspi-flash.c
new file mode 100644
index 000..dfa6235
--- /dev/null
+++ b/drivers/mtd/spinand/ti-qspi-flash.c
@@ -0,0 +1,373 @@
+/*
+ * MTD SPI driver for spansion s25fl256s (and similar) serial flash chips
+ *
+ * Author: Sourav Poddar, sourav.pod...@ti.com
+ *
+ * Copyright (c) 2013, Texas Instruments.
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include linux/init.h
+#include linux/err.h
+#include linux/errno.h
+#include linux/module.h
+#include linux/device.h
+#include linux/interrupt.h
+#include linux/mutex.h
+#include linux/math64.h
+#include linux/slab.h
+#include linux/sched.h
+#include linux/mod_devicetable.h
+
+#include linux/mtd/mtd.h
+#include linux/mtd/partitions.h
+#include linux/of_platform.h
+
+#include linux/spi/spi.h
+#include linux/mtd/spinand.h
+
+#defineCMD_OPCODE_RDSR 0x05/* Read status register */
+#define CMD_OPCODE_FAST_READ 0x0b/* Fast Read */
+#defineMAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip
erase */
+
+#defineSR_WIP 1 /* Write in progress */
+#defineSR_WEL 2 /* Write enable latch */
+
+static u16 addr_width;
+bool fast_read;
+
+static struct nand_ecclayout spinand_oob_0 = {
+ .eccbytes = 0,
+ .eccpos = {},
+ .oobavail = 0,
+ .oobfree = {
+ {.offset = 0,
+ .length = 0}, }
+};
+
+/*
+ * Read the status register, returning its value in the location
+ * Return the status register value.
+ * Returns negative if error occurred.
+*/
+static int read_sr(struct spi_device *spi_nand)
+{
+ ssize_t retval;
+ u8 val;
+ u8 code = CMD_OPCODE_RDSR;
+
+ retval = spi_write_then_read(spi_nand, code, 1, val, 1);
+
+ if (retval 0) {
+ dev_info(spi_nand-dev, error %d reading SR\n,
+ (int) retval);
+ return retval;
+ }
+
+ return val;
+}
+
+/*
+ * Set write enable latch with Write Enable command.
+ * Returns negative if error occurred.
+*/
+static inline int write_enable(struct spi_device *spi_nand)
+{
+ u8 code = CMD_WR_ENABLE;
+
+ return spi_write_then_read(spi_nand, code, 1, NULL, 0);
+}
+
+/*
+ * Send write disble instruction to the chip.
+*/
+static inline int write_disable(struct spi_device *spi_nand)
+{
+ u8 code = CMD_WR_DISABLE;
+
+ return spi_write_then_read(spi_nand, code, 1, NULL, 0);
+}
+
+/*
+ * Service routine to read status register until ready, or timeout occurs.
+ * Returns non-zero if error.
+*/
+static int wait_till_ready(struct spi_device *spi_nand)
+{
+ unsigned long deadline;
+ int sr;
+
+ deadline = jiffies + MAX_READY_WAIT_JIFFIES;
+
+ do {
+ sr = read_sr(spi_nand);
+ if (sr 0)
+ return -1;
+ else if (!(sr SR_WIP))
+ break;
+
+ cond_resched();
+ } while (!time_after_eq(jiffies, deadline));
+
+ if ((sr SR_WIP) == 0)
+ return 0
Re: [PATCH 1/3] drivers: mtd: spinand: Add generic spinand frameowrk and micron driver.
Hi Kamlakant, On Wednesday 26 June 2013 08:52 PM, Kamlakant Patel wrote: On Wed, Jun 26, 2013 at 01:11:10PM +0530, Sourav Poddar wrote: From: Mona Anonuevomanonu...@micron.com This patch adds support for a generic spinand framework(spinand_mtd.c). This frameowrk can be used for other spi based flash devices also. The idea is to have a common model under drivers/mtd, as also present for other no spi devices(there is a generic framework and device part simply attaches itself to it.) The generic frework will be used later by me for a SPI based spansion S25FL256 device. The patch also contains a micron driver attaching itself to generic framework. Signed-off-by: Mona Anonuevomanonu...@micron.com Signed-off-by: Tuan Nguyentqngu...@micron.com Signed-off-by: Sourav Poddarsourav.pod...@ti.com [I picked this as a standalone patch, can split it into generic and device part based on community feedback.] drivers/mtd/Kconfig |2 + drivers/mtd/Makefile |2 + drivers/mtd/spinand/Kconfig | 24 ++ drivers/mtd/spinand/Makefile | 10 + drivers/mtd/spinand/spinand_lld.c | 776 + drivers/mtd/spinand/spinand_mtd.c | 690 + include/linux/mtd/spinand.h | 155 7 files changed, 1659 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spinand/Kconfig create mode 100644 drivers/mtd/spinand/Makefile create mode 100644 drivers/mtd/spinand/spinand_lld.c create mode 100644 drivers/mtd/spinand/spinand_mtd.c create mode 100644 include/linux/mtd/spinand.h I am working on Micron SPINAND(Micron MT29F1G01ZACH). I tried this patch, but it's not working. It is throwing following error message while mounting: [ 260.232000] jffs2: cannot read OOB for EB at , requested 8 bytes, read 0 bytes, error -22 mount: mounting /dev/mtdblock5 on /mnt/ failed: Input/output error I am working on it to fix into the driver, will send an updated patch with the fix. Thanks for replying on this. Since, this patch is already posted, I think it will be better if you post the delta fix on top of this patch. Thanks, Kamlakant Patel -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v12 00/11] DMA Engine support for AM33XX
On Monday 24 June 2013 05:09 PM, Sekhar Nori wrote: Sourav, On 6/24/2013 3:49 PM, Tony Lindgren wrote: Hi, For merging this series, I suggest the following sets: * Joel A Fernandes [130620 14:13]: spi: omap2-mcspi: add generic DMA request support to the DT binding spi: omap2-mcspi: convert to dma_request_slave_channel_compat() The spi changes should get merged via the driver list. Can you please send just the DT binding patch above to Mark's correct address with the relevant lists copied. Thanks, Sekhar Sure. Will send that. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v12 00/11] DMA Engine support for AM33XX
On Monday 24 June 2013 05:09 PM, Sekhar Nori wrote: Sourav, On 6/24/2013 3:49 PM, Tony Lindgren wrote: Hi, For merging this series, I suggest the following sets: * Joel A Fernandesjoelag...@ti.com [130620 14:13]: spi: omap2-mcspi: add generic DMA request support to the DT binding spi: omap2-mcspi: convert to dma_request_slave_channel_compat() The spi changes should get merged via the driver list. Can you please send just the DT binding patch above to Mark's correct address with the relevant lists copied. Thanks, Sekhar Sure. Will send that. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v12 09/11] spi: omap2-mcspi: convert to dma_request_slave_channel_compat()
Hi Mark, On Friday 21 June 2013 04:58 PM, Mark Brown wrote: On Fri, Jun 21, 2013 at 04:07:51PM +0530, Sekhar Nori wrote: We can resend the patch if you don't have it from the mailing list. I'll probably have it assuming it's been sent to some mailing list I read (the CC list here looks absurldy large...) but if you don't send me the patch and/or ignore bounces then it's going to take longer. I have send you this patch seperately. Thanks , Sourav -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v12 08/11] spi: omap2-mcspi: add generic DMA request support to the DT binding
Hi Benoit,
On Friday 21 June 2013 02:36 AM, Joel A Fernandes wrote:
From: Matt Porter
The binding definition is based on the generic DMA request binding
Signed-off-by: Matt Porter
Signed-off-by: Joel A Fernandes
---
Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt
b/Documentation/devicetree/bindings/spi/omap-spi.txt
index 938809c..4c85c4c 100644
--- a/Documentation/devicetree/bindings/spi/omap-spi.txt
+++ b/Documentation/devicetree/bindings/spi/omap-spi.txt
@@ -10,7 +10,18 @@ Required properties:
input. The default is D0 as input and
D1 as output.
-Example:
+Optional properties:
+- dmas: List of DMA specifiers with the controller specific format
+ as described in the generic DMA client binding. A tx and rx
+ specifier is required for each chip select.
+- dma-names: List of DMA request names. These strings correspond
+ 1:1 with the DMA specifiers listed in dmas. The string naming
+ is to be "rxN" and "txN" for RX and TX requests,
+ respectively, where N equals the chip select number.
+
+Examples:
+
+[hwmod populated DMA resources]
mcspi1: mcspi@1 {
#address-cells =<1>;
@@ -20,3 +31,17 @@ mcspi1: mcspi@1 {
ti,spi-num-cs =<4>;
};
+[generic DMA request binding]
+
+mcspi1: mcspi@1 {
+#address-cells =<1>;
+#size-cells =<0>;
+compatible = "ti,omap4-mcspi";
+ti,hwmods = "mcspi1";
+ti,spi-num-cs =<2>;
+dmas =< 42
+43
+44
+45>;
+dma-names = "tx0", "rx0", "tx1", "rx1";
+};
If the patch looks good to you, these can go independently in your
tree.
Reviewed-by: Sourav Poddar
~Sourav
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v12 09/11] spi: omap2-mcspi: convert to dma_request_slave_channel_compat()
Hi Mark,
On Friday 21 June 2013 02:36 AM, Joel A Fernandes wrote:
From: Matt Porter
Convert dmaengine channel requests to use
dma_request_slave_channel_compat(). This supports the DT case of
platforms requiring channel selection from either the OMAP DMA or
the EDMA engine. AM33xx only boots from DT and is the only user
implementing EDMA so in the !DT case we can default to the OMAP DMA
filter.
Signed-off-by: Matt Porter
Acked-by: Mark Brown
Signed-off-by: Joel A Fernandes
---
drivers/spi/spi-omap2-mcspi.c | 64 -
1 file changed, 44 insertions(+), 20 deletions(-)
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 86d2158..ca4ab78 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -102,6 +102,9 @@ struct omap2_mcspi_dma {
struct completion dma_tx_completion;
struct completion dma_rx_completion;
+
+ char dma_rx_ch_name[14];
+ char dma_tx_ch_name[14];
};
/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
@@ -830,12 +833,20 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
sig = mcspi_dma->dma_rx_sync_dev;
- mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn,);
+
+ mcspi_dma->dma_rx =
+ dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+ ,>dev,
+mcspi_dma->dma_rx_ch_name);
if (!mcspi_dma->dma_rx)
goto no_dma;
sig = mcspi_dma->dma_tx_sync_dev;
- mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn,);
+ mcspi_dma->dma_tx =
+ dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+ ,>dev,
+mcspi_dma->dma_tx_ch_name);
+
if (!mcspi_dma->dma_tx) {
dma_release_channel(mcspi_dma->dma_rx);
mcspi_dma->dma_rx = NULL;
@@ -1256,29 +1267,42 @@ static int omap2_mcspi_probe(struct platform_device
*pdev)
goto free_master;
for (i = 0; i< master->num_chipselect; i++) {
- char dma_ch_name[14];
+ char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
+ char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
struct resource *dma_res;
- sprintf(dma_ch_name, "rx%d", i);
- dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
- dma_ch_name);
- if (!dma_res) {
- dev_dbg(>dev, "cannot get DMA RX channel\n");
- status = -ENODEV;
- break;
- }
+ sprintf(dma_rx_ch_name, "rx%d", i);
+ if (!pdev->dev.of_node) {
+ dma_res =
+ platform_get_resource_byname(pdev,
+IORESOURCE_DMA,
+dma_rx_ch_name);
+ if (!dma_res) {
+ dev_dbg(>dev,
+ "cannot get DMA RX channel\n");
+ status = -ENODEV;
+ break;
+ }
- mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
- sprintf(dma_ch_name, "tx%d", i);
- dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
- dma_ch_name);
- if (!dma_res) {
- dev_dbg(>dev, "cannot get DMA TX channel\n");
- status = -ENODEV;
- break;
+ mcspi->dma_channels[i].dma_rx_sync_dev =
+ dma_res->start;
}
+ sprintf(dma_tx_ch_name, "tx%d", i);
+ if (!pdev->dev.of_node) {
+ dma_res =
+ platform_get_resource_byname(pdev,
+IORESOURCE_DMA,
+dma_tx_ch_name);
+ if (!dma_res) {
+ dev_dbg(>dev,
+ "cannot get DMA TX channel\n");
+ status = -ENODEV;
+ break;
+ }
- mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
+ mcspi->dma_channels
Re: [PATCH v12 09/11] spi: omap2-mcspi: convert to dma_request_slave_channel_compat()
; + } } if (status 0) Acked-by: Sourav Poddar sourav.pod...@ti.com Tested-by: Sourav Poddar sourav.pod...@ti.com This patch can go independently and does not depend on the rest of the series. Can these patch be pulled? -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v12 08/11] spi: omap2-mcspi: add generic DMA request support to the DT binding
Hi Benoit,
On Friday 21 June 2013 02:36 AM, Joel A Fernandes wrote:
From: Matt Portermpor...@ti.com
The binding definition is based on the generic DMA request binding
Signed-off-by: Matt Portermpor...@ti.com
Signed-off-by: Joel A Fernandesjoelag...@ti.com
---
Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt
b/Documentation/devicetree/bindings/spi/omap-spi.txt
index 938809c..4c85c4c 100644
--- a/Documentation/devicetree/bindings/spi/omap-spi.txt
+++ b/Documentation/devicetree/bindings/spi/omap-spi.txt
@@ -10,7 +10,18 @@ Required properties:
input. The default is D0 as input and
D1 as output.
-Example:
+Optional properties:
+- dmas: List of DMA specifiers with the controller specific format
+ as described in the generic DMA client binding. A tx and rx
+ specifier is required for each chip select.
+- dma-names: List of DMA request names. These strings correspond
+ 1:1 with the DMA specifiers listed in dmas. The string naming
+ is to be rxN and txN for RX and TX requests,
+ respectively, where N equals the chip select number.
+
+Examples:
+
+[hwmod populated DMA resources]
mcspi1: mcspi@1 {
#address-cells =1;
@@ -20,3 +31,17 @@ mcspi1: mcspi@1 {
ti,spi-num-cs =4;
};
+[generic DMA request binding]
+
+mcspi1: mcspi@1 {
+#address-cells =1;
+#size-cells =0;
+compatible = ti,omap4-mcspi;
+ti,hwmods = mcspi1;
+ti,spi-num-cs =2;
+dmas =edma 42
+ edma 43
+ edma 44
+ edma 45;
+dma-names = tx0, rx0, tx1, rx1;
+};
If the patch looks good to you, these can go independently in your
tree.
Reviewed-by: Sourav Poddar sourav.pod...@ti.com
~Sourav
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To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v12 09/11] spi: omap2-mcspi: convert to dma_request_slave_channel_compat()
Hi Mark, On Friday 21 June 2013 04:58 PM, Mark Brown wrote: On Fri, Jun 21, 2013 at 04:07:51PM +0530, Sekhar Nori wrote: We can resend the patch if you don't have it from the mailing list. I'll probably have it assuming it's been sent to some mailing list I read (the CC list here looks absurldy large...) but if you don't send me the patch and/or ignore bounces then it's going to take longer. I have send you this patch seperately. Thanks , Sourav -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] serial: omap: repair building without PM_SLEEP
Hi Arnd, On Saturday 01 June 2013 02:48 PM, Arnd Bergmann wrote: A recent bug fix in 3.10, ddd85e225c "serial: omap: prevent runtime PM for "no_console_suspend"", introduced a regression from an obvious typo: drivers/tty/serial/omap-serial.c:1677:14: error: 'serial_omap_complete' undeclared here (not in a function) This changes the incorrectly added macro to the one that we need instead. Signed-off-by: Arnd Bergmann --- Please apply for 3.10-rc diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c index 393a8eb..1aaeca8 100644 --- a/drivers/tty/serial/omap-serial.c +++ b/drivers/tty/serial/omap-serial.c @@ -1326,7 +1326,7 @@ static int serial_omap_resume(struct device *dev) } #else #define serial_omap_prepare NULL -#define serial_omap_prepare NULL +#define serial_omap_complete NULL #endif /* CONFIG_PM_SLEEP */ static void omap_serial_fill_features_erratas(struct uart_omap_port *up) Yes, this bug was noticed last week and a patch for it has already been posted to the serial mailing list[1]. [1]: http://www.spinics.net/lists/linux-serial/msg09741.html -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] serial: omap: repair building without PM_SLEEP
Hi Arnd, On Saturday 01 June 2013 02:48 PM, Arnd Bergmann wrote: A recent bug fix in 3.10, ddd85e225c serial: omap: prevent runtime PM for no_console_suspend, introduced a regression from an obvious typo: drivers/tty/serial/omap-serial.c:1677:14: error: 'serial_omap_complete' undeclared here (not in a function) This changes the incorrectly added macro to the one that we need instead. Signed-off-by: Arnd Bergmanna...@arndb.de --- Please apply for 3.10-rc diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c index 393a8eb..1aaeca8 100644 --- a/drivers/tty/serial/omap-serial.c +++ b/drivers/tty/serial/omap-serial.c @@ -1326,7 +1326,7 @@ static int serial_omap_resume(struct device *dev) } #else #define serial_omap_prepare NULL -#define serial_omap_prepare NULL +#define serial_omap_complete NULL #endif /* CONFIG_PM_SLEEP */ static void omap_serial_fill_features_erratas(struct uart_omap_port *up) Yes, this bug was noticed last week and a patch for it has already been posted to the serial mailing list[1]. [1]: http://www.spinics.net/lists/linux-serial/msg09741.html -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[Resend/PATCHv5 3/3] arm: omap2+: omap_device: remove no_idle_on_suspend
Remove "no_idle_on_suspend" check, since respective
driver should be able to prevent idling of an
omap device whenever required.
Driver's can get same behavior by just returning -EBUSY
from their ->runtime_suspend only during suspend.
Cc: Santosh Shilimkar
Cc: Felipe Balbi
Cc: Rajendra nayak
Cc: Grygorii Strashko
Signed-off-by: Sourav Poddar
Reviewed-by: Felipe Balbi
---
arch/arm/mach-omap2/omap_device.c |9 ++---
arch/arm/mach-omap2/omap_device.h | 10 --
2 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_device.c
b/arch/arm/mach-omap2/omap_device.c
index e6d2307..68be532 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -170,9 +170,6 @@ static int omap_device_build_from_dt(struct platform_device
*pdev)
r->name = dev_name(>dev);
}
- if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
- omap_device_disable_idle_on_suspend(pdev);
-
pdev->dev.pm_domain = _device_pm_domain;
odbfd_exit1:
@@ -621,8 +618,7 @@ static int _od_suspend_noirq(struct device *dev)
if (!ret && !pm_runtime_status_suspended(dev)) {
if (pm_generic_runtime_suspend(dev) == 0) {
- if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
- omap_device_idle(pdev);
+ omap_device_idle(pdev);
od->flags |= OMAP_DEVICE_SUSPENDED;
}
}
@@ -638,8 +634,7 @@ static int _od_resume_noirq(struct device *dev)
if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
!pm_runtime_status_suspended(dev)) {
od->flags &= ~OMAP_DEVICE_SUSPENDED;
- if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
- omap_device_enable(pdev);
+ omap_device_enable(pdev);
pm_generic_runtime_resume(dev);
}
diff --git a/arch/arm/mach-omap2/omap_device.h
b/arch/arm/mach-omap2/omap_device.h
index 044c31d..17ca1ae 100644
--- a/arch/arm/mach-omap2/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -38,7 +38,6 @@ extern struct dev_pm_domain omap_device_pm_domain;
/* omap_device.flags values */
#define OMAP_DEVICE_SUSPENDED BIT(0)
-#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1)
/**
* struct omap_device - omap_device wrapper for platform_devices
@@ -101,13 +100,4 @@ static inline struct omap_device *to_omap_device(struct
platform_device *pdev)
{
return pdev ? pdev->archdata.od : NULL;
}
-
-static inline
-void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
-{
- struct omap_device *od = to_omap_device(pdev);
-
- od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
-}
-
#endif
--
1.7.1
--
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[Resend/PATCHv5 1/3] arm: omap2+: serial: remove no_console_suspend support
"no_console_suspend" is no longer handled in platform file,
Since the omap serial driver is now adapted to prevent
console UART idleing during suspend.
Cc: Santosh Shilimkar
Cc: Felipe Balbi
Cc: Rajendra nayak
Signed-off-by: Sourav Poddar
Reviewed-by: Felipe Balbi
---
arch/arm/mach-omap2/serial.c |7 ---
1 files changed, 0 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 8396b5b..25fb6e9 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -63,7 +63,6 @@ struct omap_uart_state {
static LIST_HEAD(uart_list);
static u8 num_uarts;
static u8 console_uart_id = -1;
-static u8 no_console_suspend;
static u8 uart_debug;
#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */
@@ -236,9 +235,6 @@ static int __init omap_serial_early_init(void)
uart_name, uart->num);
}
- if (cmdline_find_option("no_console_suspend"))
- no_console_suspend = true;
-
/*
* omap-uart can be used for earlyprintk logs
* So if omap-uart is used as console then prevent
@@ -323,9 +319,6 @@ void __init omap_serial_init_port(struct omap_board_data
*bdata,
return;
}
- if ((console_uart_id == bdata->id) && no_console_suspend)
- omap_device_disable_idle_on_suspend(pdev);
-
oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
if (console_uart_id == bdata->id) {
--
1.7.1
--
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