Re: [PATCH] Documentation: memory-barriers: Fix typo in the first example
Hi,
Kindly review the patch.
Thanks
Srikanth
On Tue, Nov 18, 2014 at 10:09 AM, Srikanth Thokala
wrote:
> In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
> match the sequence of events described below it. To match the
> sequence of events, the values of 'A' and 'B' should be loaded
> into 'x' and 'y' respectively.
>
> Signed-off-by: Srikanth Thokala
> ---
> Documentation/memory-barriers.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/memory-barriers.txt
> b/Documentation/memory-barriers.txt
> index 22a969c..2770bce 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -115,8 +115,8 @@ For example, consider the following sequence of events:
> CPU 1 CPU 2
> === ===
> { A == 1; B == 2 }
> - A = 3; x = B;
> - B = 4; y = A;
> + A = 3; x = A;
> + B = 4; y = B;
>
> The set of accesses as seen by the memory system in the middle can be
> arranged
> in 24 different combinations:
> --
> 1.9.1
>
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Re: [PATCH] Documentation: memory-barriers: Fix typo in the first example
Hi,
Kindly review the patch.
Thanks
Srikanth
On Tue, Nov 18, 2014 at 10:09 AM, Srikanth Thokala
sriku.li...@gmail.com wrote:
In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
match the sequence of events described below it. To match the
sequence of events, the values of 'A' and 'B' should be loaded
into 'x' and 'y' respectively.
Signed-off-by: Srikanth Thokala sriku.li...@gmail.com
---
Documentation/memory-barriers.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/memory-barriers.txt
b/Documentation/memory-barriers.txt
index 22a969c..2770bce 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -115,8 +115,8 @@ For example, consider the following sequence of events:
CPU 1 CPU 2
=== ===
{ A == 1; B == 2 }
- A = 3; x = B;
- B = 4; y = A;
+ A = 3; x = A;
+ B = 4; y = B;
The set of accesses as seen by the memory system in the middle can be
arranged
in 24 different combinations:
--
1.9.1
--
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[PATCH] Documentation: memory-barriers: Fix typo in the first example
In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
match the sequence of events described below it. To match the
sequence of events, the values of 'A' and 'B' should be loaded
into 'x' and 'y' respectively.
Signed-off-by: Srikanth Thokala
---
Documentation/memory-barriers.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/memory-barriers.txt
b/Documentation/memory-barriers.txt
index 22a969c..2770bce 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -115,8 +115,8 @@ For example, consider the following sequence of events:
CPU 1 CPU 2
=== ===
{ A == 1; B == 2 }
- A = 3; x = B;
- B = 4; y = A;
+ A = 3; x = A;
+ B = 4; y = B;
The set of accesses as seen by the memory system in the middle can be arranged
in 24 different combinations:
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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[PATCH] Documentation: memory-barriers: Fix typo in the first example
In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
match the sequence of events described below it. To match the
sequence of events, the values of 'A' and 'B' should be loaded
into 'x' and 'y' respectively.
Signed-off-by: Srikanth Thokala sriku.li...@gmail.com
---
Documentation/memory-barriers.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/memory-barriers.txt
b/Documentation/memory-barriers.txt
index 22a969c..2770bce 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -115,8 +115,8 @@ For example, consider the following sequence of events:
CPU 1 CPU 2
=== ===
{ A == 1; B == 2 }
- A = 3; x = B;
- B = 4; y = A;
+ A = 3; x = A;
+ B = 4; y = B;
The set of accesses as seen by the memory system in the middle can be arranged
in 24 different combinations:
--
1.9.1
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
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Re: [PATCH V2 2/2] PCI: generic: Add msi_parent DT binding
Hi,
On Wed, Nov 12, 2014 at 12:26 PM, Srikanth Thokala
wrote:
> Hi,
>
> On Wed, Nov 12, 2014 at 12:47 AM, wrote:
>> From: Suravee Suthikulpanit
>>
>> This patch introduces a new DT binding, msi-parent, which can
>> be used to specify MSI-parent phandle for a particular PCI
>> generic host controller.
>>
>> Also, it implements and registers set_msi_parent callback.
>>
>> Cc: Bjorn Helgass
>> Cc: Liviu Dudau
>> Cc: Will Deacon
>> Cc: Lorenzo Pieralisi
>> Signed-off-by: Suravee Suthikulpanit
>> ---
>> Documentation/devicetree/bindings/pci/host-generic-pci.txt | 3 +++
>> drivers/pci/host/pci-host-generic.c| 13
>> +
>> 2 files changed, 16 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
>> b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
>> index cf3e205..6996af7 100644
>> --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
>> +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
>> @@ -36,6 +36,8 @@ Properties of the host controller node:
>> - reg: The Configuration Space base address and size, as
>> accessed
>> from the parent bus.
>>
>> +- msi-parent : Specify the phandle of the corresponded MSI controller
>> + for this PCI host controller.
>>
>> Properties of the /chosen node:
>>
>> @@ -77,6 +79,7 @@ pci {
>> device_type = "pci";
>> #address-cells = <3>;
>> #size-cells = <2>;
>> +msi-parent = <>;
>> bus-range = <0x0 0x1>;
>>
>> // CPU_PHYSICAL(2) SIZE(2)
>> diff --git a/drivers/pci/host/pci-host-generic.c
>> b/drivers/pci/host/pci-host-generic.c
>> index 1895907..c4fbcda 100644
>> --- a/drivers/pci/host/pci-host-generic.c
>> +++ b/drivers/pci/host/pci-host-generic.c
>> @@ -42,6 +42,7 @@ struct gen_pci {
>> struct pci_host_bridge host;
>> struct gen_pci_cfg_windows cfg;
>> struct list_headresources;
>> + struct msi_chip *mchip;
>> };
>>
>> static void __iomem *gen_pci_map_cfg_bus_cam(struct pci_bus *bus,
>> @@ -122,9 +123,19 @@ static int gen_pci_config_write(struct pci_bus *bus,
>> unsigned int devfn,
>> return PCIBIOS_SUCCESSFUL;
>> }
>>
>> +static int gen_pci_set_msi_parent(struct pci_bus *bus)
>> +{
>> + struct gen_pci *pci = bus_to_gen_pci(bus);
>> +
>> + bus->msi = pci->mchip;
>> +
>> + return PCIBIOS_SUCCESSFUL;
>> +}
>> +
>> static struct pci_ops gen_pci_ops = {
>> .read = gen_pci_config_read,
>> .write = gen_pci_config_write,
>> + .set_msi_parent = gen_pci_set_msi_parent,
>
> We assign the msi chip through add_bus() call, do we still need this?
>
There are series of patches from Yijing Wang around this. You may have
to go through them.
Srikanth
> Srikanth
>
>> };
>>
>> static const struct of_device_id gen_pci_of_match[] = {
>> @@ -303,6 +314,8 @@ static int gen_pci_probe(struct platform_device *pdev)
>> return err;
>> }
>>
>> + pci->mchip = of_pci_find_msi_chip_by_node(of_parse_phandle(np,
>> + "msi-parent", 0));
>> pci_common_init_dev(dev, );
>> return 0;
>> }
>> --
>> 1.9.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
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Re: [PATCH V2 2/2] PCI: generic: Add msi_parent DT binding
Hi,
On Wed, Nov 12, 2014 at 12:47 AM, wrote:
> From: Suravee Suthikulpanit
>
> This patch introduces a new DT binding, msi-parent, which can
> be used to specify MSI-parent phandle for a particular PCI
> generic host controller.
>
> Also, it implements and registers set_msi_parent callback.
>
> Cc: Bjorn Helgass
> Cc: Liviu Dudau
> Cc: Will Deacon
> Cc: Lorenzo Pieralisi
> Signed-off-by: Suravee Suthikulpanit
> ---
> Documentation/devicetree/bindings/pci/host-generic-pci.txt | 3 +++
> drivers/pci/host/pci-host-generic.c| 13 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
> b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
> index cf3e205..6996af7 100644
> --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
> @@ -36,6 +36,8 @@ Properties of the host controller node:
> - reg: The Configuration Space base address and size, as accessed
> from the parent bus.
>
> +- msi-parent : Specify the phandle of the corresponded MSI controller
> + for this PCI host controller.
>
> Properties of the /chosen node:
>
> @@ -77,6 +79,7 @@ pci {
> device_type = "pci";
> #address-cells = <3>;
> #size-cells = <2>;
> +msi-parent = <>;
> bus-range = <0x0 0x1>;
>
> // CPU_PHYSICAL(2) SIZE(2)
> diff --git a/drivers/pci/host/pci-host-generic.c
> b/drivers/pci/host/pci-host-generic.c
> index 1895907..c4fbcda 100644
> --- a/drivers/pci/host/pci-host-generic.c
> +++ b/drivers/pci/host/pci-host-generic.c
> @@ -42,6 +42,7 @@ struct gen_pci {
> struct pci_host_bridge host;
> struct gen_pci_cfg_windows cfg;
> struct list_headresources;
> + struct msi_chip *mchip;
> };
>
> static void __iomem *gen_pci_map_cfg_bus_cam(struct pci_bus *bus,
> @@ -122,9 +123,19 @@ static int gen_pci_config_write(struct pci_bus *bus,
> unsigned int devfn,
> return PCIBIOS_SUCCESSFUL;
> }
>
> +static int gen_pci_set_msi_parent(struct pci_bus *bus)
> +{
> + struct gen_pci *pci = bus_to_gen_pci(bus);
> +
> + bus->msi = pci->mchip;
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> static struct pci_ops gen_pci_ops = {
> .read = gen_pci_config_read,
> .write = gen_pci_config_write,
> + .set_msi_parent = gen_pci_set_msi_parent,
We assign the msi chip through add_bus() call, do we still need this?
Srikanth
> };
>
> static const struct of_device_id gen_pci_of_match[] = {
> @@ -303,6 +314,8 @@ static int gen_pci_probe(struct platform_device *pdev)
> return err;
> }
>
> + pci->mchip = of_pci_find_msi_chip_by_node(of_parse_phandle(np,
> + "msi-parent", 0));
> pci_common_init_dev(dev, );
> return 0;
> }
> --
> 1.9.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majord...@vger.kernel.org
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Re: [PATCH V2 2/2] PCI: generic: Add msi_parent DT binding
Hi,
On Wed, Nov 12, 2014 at 12:47 AM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch introduces a new DT binding, msi-parent, which can
be used to specify MSI-parent phandle for a particular PCI
generic host controller.
Also, it implements and registers set_msi_parent callback.
Cc: Bjorn Helgass bhelg...@google.com
Cc: Liviu Dudau liviu.du...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
Documentation/devicetree/bindings/pci/host-generic-pci.txt | 3 +++
drivers/pci/host/pci-host-generic.c| 13 +
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
index cf3e205..6996af7 100644
--- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
+++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
@@ -36,6 +36,8 @@ Properties of the host controller node:
- reg: The Configuration Space base address and size, as accessed
from the parent bus.
+- msi-parent : Specify the phandle of the corresponded MSI controller
+ for this PCI host controller.
Properties of the /chosen node:
@@ -77,6 +79,7 @@ pci {
device_type = pci;
#address-cells = 3;
#size-cells = 2;
+msi-parent = msictrl0;
bus-range = 0x0 0x1;
// CPU_PHYSICAL(2) SIZE(2)
diff --git a/drivers/pci/host/pci-host-generic.c
b/drivers/pci/host/pci-host-generic.c
index 1895907..c4fbcda 100644
--- a/drivers/pci/host/pci-host-generic.c
+++ b/drivers/pci/host/pci-host-generic.c
@@ -42,6 +42,7 @@ struct gen_pci {
struct pci_host_bridge host;
struct gen_pci_cfg_windows cfg;
struct list_headresources;
+ struct msi_chip *mchip;
};
static void __iomem *gen_pci_map_cfg_bus_cam(struct pci_bus *bus,
@@ -122,9 +123,19 @@ static int gen_pci_config_write(struct pci_bus *bus,
unsigned int devfn,
return PCIBIOS_SUCCESSFUL;
}
+static int gen_pci_set_msi_parent(struct pci_bus *bus)
+{
+ struct gen_pci *pci = bus_to_gen_pci(bus);
+
+ bus-msi = pci-mchip;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
static struct pci_ops gen_pci_ops = {
.read = gen_pci_config_read,
.write = gen_pci_config_write,
+ .set_msi_parent = gen_pci_set_msi_parent,
We assign the msi chip through add_bus() call, do we still need this?
Srikanth
};
static const struct of_device_id gen_pci_of_match[] = {
@@ -303,6 +314,8 @@ static int gen_pci_probe(struct platform_device *pdev)
return err;
}
+ pci-mchip = of_pci_find_msi_chip_by_node(of_parse_phandle(np,
+ msi-parent, 0));
pci_common_init_dev(dev, hw);
return 0;
}
--
1.9.3
--
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Re: [PATCH V2 2/2] PCI: generic: Add msi_parent DT binding
Hi,
On Wed, Nov 12, 2014 at 12:26 PM, Srikanth Thokala
sriku.li...@gmail.com wrote:
Hi,
On Wed, Nov 12, 2014 at 12:47 AM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch introduces a new DT binding, msi-parent, which can
be used to specify MSI-parent phandle for a particular PCI
generic host controller.
Also, it implements and registers set_msi_parent callback.
Cc: Bjorn Helgass bhelg...@google.com
Cc: Liviu Dudau liviu.du...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
Documentation/devicetree/bindings/pci/host-generic-pci.txt | 3 +++
drivers/pci/host/pci-host-generic.c| 13
+
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
index cf3e205..6996af7 100644
--- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
+++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
@@ -36,6 +36,8 @@ Properties of the host controller node:
- reg: The Configuration Space base address and size, as
accessed
from the parent bus.
+- msi-parent : Specify the phandle of the corresponded MSI controller
+ for this PCI host controller.
Properties of the /chosen node:
@@ -77,6 +79,7 @@ pci {
device_type = pci;
#address-cells = 3;
#size-cells = 2;
+msi-parent = msictrl0;
bus-range = 0x0 0x1;
// CPU_PHYSICAL(2) SIZE(2)
diff --git a/drivers/pci/host/pci-host-generic.c
b/drivers/pci/host/pci-host-generic.c
index 1895907..c4fbcda 100644
--- a/drivers/pci/host/pci-host-generic.c
+++ b/drivers/pci/host/pci-host-generic.c
@@ -42,6 +42,7 @@ struct gen_pci {
struct pci_host_bridge host;
struct gen_pci_cfg_windows cfg;
struct list_headresources;
+ struct msi_chip *mchip;
};
static void __iomem *gen_pci_map_cfg_bus_cam(struct pci_bus *bus,
@@ -122,9 +123,19 @@ static int gen_pci_config_write(struct pci_bus *bus,
unsigned int devfn,
return PCIBIOS_SUCCESSFUL;
}
+static int gen_pci_set_msi_parent(struct pci_bus *bus)
+{
+ struct gen_pci *pci = bus_to_gen_pci(bus);
+
+ bus-msi = pci-mchip;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
static struct pci_ops gen_pci_ops = {
.read = gen_pci_config_read,
.write = gen_pci_config_write,
+ .set_msi_parent = gen_pci_set_msi_parent,
We assign the msi chip through add_bus() call, do we still need this?
There are series of patches from Yijing Wang around this. You may have
to go through them.
Srikanth
Srikanth
};
static const struct of_device_id gen_pci_of_match[] = {
@@ -303,6 +314,8 @@ static int gen_pci_probe(struct platform_device *pdev)
return err;
}
+ pci-mchip = of_pci_find_msi_chip_by_node(of_parse_phandle(np,
+ msi-parent, 0));
pci_common_init_dev(dev, hw);
return 0;
}
--
1.9.3
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Re: [PATCH v2] PCI: remove an unnecessary if condition before a return statement
Hi Quentin, On Fri, Nov 7, 2014 at 1:36 PM, Quentin Lambert wrote: > Simplify a trivial if-return sequence. Possibly combine with a > preceding function call. > Generated by: scripts/coccinelle/misc/simple_return.cocci > > Signed-off-by: Quentin Lambert > --- > > Changes in v2: > - remove a checkpatch warning due to the a space between after the >function name. > > drivers/pci/hotplug/ibmphp_res.c | 5 + > drivers/pci/pci.c| 6 +- > 2 files changed, 2 insertions(+), 9 deletions(-) > > diff --git a/drivers/pci/hotplug/ibmphp_res.c > b/drivers/pci/hotplug/ibmphp_res.c > index 219ba80..2da59ef 100644 > --- a/drivers/pci/hotplug/ibmphp_res.c > +++ b/drivers/pci/hotplug/ibmphp_res.c > @@ -376,10 +376,7 @@ int __init ibmphp_rsrc_init (void) > if (rc) > return rc; > } > - rc = once_over (); /* This is to align ranges (so no -1) */ > - if (rc) > - return rc; > - return 0; > + return once_over(); I think we need to retain the comment? - Srikanth > } > > > / > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 625a4ac..9a5871f 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -1012,11 +1012,7 @@ int pci_save_state(struct pci_dev *dev) > if (i != 0) > return i; > > - i = pci_save_vc_state(dev); > - if (i != 0) > - return i; > - > - return 0; > + return pci_save_vc_state(dev); > } > EXPORT_SYMBOL(pci_save_state); > > -- > 1.9.1 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2] PCI: remove an unnecessary if condition before a return statement
Hi Quentin, On Fri, Nov 7, 2014 at 1:36 PM, Quentin Lambert lambert.quen...@gmail.com wrote: Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci Signed-off-by: Quentin Lambert lambert.quen...@gmail.com --- Changes in v2: - remove a checkpatch warning due to the a space between after the function name. drivers/pci/hotplug/ibmphp_res.c | 5 + drivers/pci/pci.c| 6 +- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/pci/hotplug/ibmphp_res.c b/drivers/pci/hotplug/ibmphp_res.c index 219ba80..2da59ef 100644 --- a/drivers/pci/hotplug/ibmphp_res.c +++ b/drivers/pci/hotplug/ibmphp_res.c @@ -376,10 +376,7 @@ int __init ibmphp_rsrc_init (void) if (rc) return rc; } - rc = once_over (); /* This is to align ranges (so no -1) */ - if (rc) - return rc; - return 0; + return once_over(); I think we need to retain the comment? - Srikanth } / diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 625a4ac..9a5871f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1012,11 +1012,7 @@ int pci_save_state(struct pci_dev *dev) if (i != 0) return i; - i = pci_save_vc_state(dev); - if (i != 0) - return i; - - return 0; + return pci_save_vc_state(dev); } EXPORT_SYMBOL(pci_save_state); -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-pci in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi Mark,
Thanks for reviewing patch.
I should have made a note that the binding patch is applied. I will
make a note of this and add to next versions.
Thanks
Srikanth
On Wed, Oct 15, 2014 at 6:15 PM, Mark Rutland wrote:
> Hi,
>
> On Wed, Oct 15, 2014 at 01:00:36PM +0100, Srikanth Thokala wrote:
>> This is the driver for the AXI Direct Memory Access (AXI DMA)
>> core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct memory access between memory and AXI4-Stream
>> type target peripherals.
>>
>> This module works on Zynq (ARM Based SoC) and Microblaze platforms.
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v4:
>> - Add direction field to VDMA descriptor structure and removed from
>> channel structure to avoid duplication.
>> - Check for DMA idle condition before changing the configuration.
>> - Residue is being calculated in complete_descriptor() and is reported
>> to slave driver.
>>
>> Changes in v3:
>> - Rebased on 3.16-rc7
>>
>> Changes in v2:
>> - Simplified the logic to set SOP and APP words in prep_slave_sg().
>> - Corrected function description comments to match the return type.
>> - Fixed some minor comments as suggested by Andy, Thanks.
>> ---
>> drivers/dma/Kconfig | 13 +
>> drivers/dma/xilinx/Makefile |1 +
>> drivers/dma/xilinx/xilinx_dma.c | 1242
>> +++
>> include/linux/amba/xilinx_dma.h | 17 +
>> 4 files changed, 1273 insertions(+)
>> create mode 100644 drivers/dma/xilinx/xilinx_dma.c
>
> [...]
>
>> +static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
>> +struct device_node *node)
>> +{
>> + struct xilinx_dma_chan *chan;
>> + int err;
>> + bool has_dre;
>> + u32 value, width = 0;
>> +
>> + /* Allocate a channel */
>> + chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
>> + if (!chan)
>> + return -ENOMEM;
>> +
>> + chan->dev = xdev->dev;
>> + chan->xdev = xdev;
>> + chan->has_sg = xdev->has_sg;
>> +
>> + spin_lock_init(>lock);
>> + INIT_LIST_HEAD(>pending_list);
>> + INIT_LIST_HEAD(>done_list);
>> + INIT_LIST_HEAD(>free_seg_list);
>> +
>> + /* Get the DT properties */
>> + has_dre = of_property_read_bool(node, "xlnx,include-dre");
>> +
>> + err = of_property_read_u32(node, "xlnx,datawidth", );
>> + if (err) {
>> + dev_err(xdev->dev, "unable to read datawidth property");
>> + return err;
>> + }
>> +
>> + width = value >> 3; /* Convert bits to bytes */
>> +
>> + /* If data width is greater than 8 bytes, DRE is not in hw */
>> + if (width > 8)
>> + has_dre = false;
>> +
>> + if (!has_dre)
>> + xdev->common.copy_align = fls(width - 1);
>> +
>> + if (of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel")) {
>> + chan->id = 0;
>> + chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
>> + } else if (of_device_is_compatible(node,
>> + "xlnx,axi-dma-s2mm-channel")) {
>> + chan->id = 1;
>> + chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
>> + } else {
>> + dev_err(xdev->dev, "Invalid channel compatible node\n");
>> + return -EINVAL;
>> + }
>> +
>> + /* Find the IRQ line, if it exists in the device tree */
>> + chan->irq = irq_of_parse_and_map(node, 0);
>> + err = request_irq(chan->irq, xilinx_dma_irq_handler,
>> + IRQF_SHARED,
>> + "xilinx-dma-controller", chan);
>> + if (err) {
>> + dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
>> + return err;
>> + }
>> +
>> + /* Initialize the tasklet */
>> + tasklet_init(>tasklet, xilinx_dma_do_tasklet,
>> +(unsigned long)chan);
>> +
>> + /*
>> +* Initialize the DMA channel and add it to the DMA engine channels
>> +* list.
>> +*/
>> + chan->common.device = >common;
>> +
>> +
[PATCH v4] dma: Add Xilinx AXI Direct Memory Access Engine driver support
This is the driver for the AXI Direct Memory Access (AXI DMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type target peripherals. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala --- Changes in v4: - Add direction field to VDMA descriptor structure and removed from channel structure to avoid duplication. - Check for DMA idle condition before changing the configuration. - Residue is being calculated in complete_descriptor() and is reported to slave driver. Changes in v3: - Rebased on 3.16-rc7 Changes in v2: - Simplified the logic to set SOP and APP words in prep_slave_sg(). - Corrected function description comments to match the return type. - Fixed some minor comments as suggested by Andy, Thanks. --- drivers/dma/Kconfig | 13 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_dma.c | 1242 +++ include/linux/amba/xilinx_dma.h | 17 + 4 files changed, 1273 insertions(+) create mode 100644 drivers/dma/xilinx/xilinx_dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1eca7b9..b8e831e 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -375,6 +375,19 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_DMA + tristate "Xilinx AXI DMA Engine" + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI DMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream type target peripherals. + It has two stream interfaces/channels, Memory Mapped to + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the + data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..6224a49 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c new file mode 100644 index 000..f32c8f5 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -0,0 +1,1242 @@ +/* + * DMA driver for Xilinx DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access between memory and AXI4-Stream-type target peripherals. It can be + * configured to have one channel or two channels and if configured as two + * channels, one is to transmit data from memory to a device and another is + * to receive from a device. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../dmaengine.h" + +/* Register Offsets */ +#define XILINX_DMA_REG_CONTROL 0x00 +#define XILINX_DMA_REG_STATUS 0x04 +#define XILINX_DMA_REG_CURDESC 0x08 +#define XILINX_DMA_REG_TAILDESC0x10 +#define XILINX_DMA_REG_SRCADDR 0x18 +#define XILINX_DMA_REG_DSTADDR 0x20 +#define XILINX_DMA_REG_BTT 0x28 + +/* Channel/Descriptor Offsets */ +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 + +/* General register bits definitions */ +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_DMA_CR_RESET_MASK BIT(2) + +#define XILINX_DMA_CR_DELAY_SHIFT 24 +#define XILINX_DMA_CR_COALESCE_SHIFT 16 + +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) + +#define XILINX_DMA_SR_HALTED_MASK BIT(0) +#define XILINX_DMA_SR_IDLE_MASKBIT(1) + +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) + +/* BD definitions */ +#define XILINX_DMA_BD_STS_ALL_MASK GENMASK(31, 28) +#define XILINX_DMA_BD_SOP BIT(27) +#define XILINX_DMA_BD_EOP BIT(26) + +/* Hw specific definitions */ +#define XILINX_DMA_MAX_CHANS_PER_DEVICE0x2 +#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) + +/* Delay loop counter to prevent hardware failure */ +#define XILINX_DMA_LOOP_COUNT 100 + +/* Maximum number of Descriptors */ +#define XILINX_DMA_NU
[PATCH v4] dma: Add Xilinx AXI Direct Memory Access Engine driver support
This is the driver for the AXI Direct Memory Access (AXI DMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type target peripherals. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala stho...@xilinx.com --- Changes in v4: - Add direction field to VDMA descriptor structure and removed from channel structure to avoid duplication. - Check for DMA idle condition before changing the configuration. - Residue is being calculated in complete_descriptor() and is reported to slave driver. Changes in v3: - Rebased on 3.16-rc7 Changes in v2: - Simplified the logic to set SOP and APP words in prep_slave_sg(). - Corrected function description comments to match the return type. - Fixed some minor comments as suggested by Andy, Thanks. --- drivers/dma/Kconfig | 13 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_dma.c | 1242 +++ include/linux/amba/xilinx_dma.h | 17 + 4 files changed, 1273 insertions(+) create mode 100644 drivers/dma/xilinx/xilinx_dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1eca7b9..b8e831e 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -375,6 +375,19 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_DMA + tristate Xilinx AXI DMA Engine + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI DMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream type target peripherals. + It has two stream interfaces/channels, Memory Mapped to + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the + data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..6224a49 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c new file mode 100644 index 000..f32c8f5 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -0,0 +1,1242 @@ +/* + * DMA driver for Xilinx DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access between memory and AXI4-Stream-type target peripherals. It can be + * configured to have one channel or two channels and if configured as two + * channels, one is to transmit data from memory to a device and another is + * to receive from a device. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include linux/amba/xilinx_dma.h +#include linux/bitops.h +#include linux/init.h +#include linux/interrupt.h +#include linux/io.h +#include linux/module.h +#include linux/of_address.h +#include linux/of_dma.h +#include linux/of_irq.h +#include linux/of_platform.h +#include linux/slab.h + +#include ../dmaengine.h + +/* Register Offsets */ +#define XILINX_DMA_REG_CONTROL 0x00 +#define XILINX_DMA_REG_STATUS 0x04 +#define XILINX_DMA_REG_CURDESC 0x08 +#define XILINX_DMA_REG_TAILDESC0x10 +#define XILINX_DMA_REG_SRCADDR 0x18 +#define XILINX_DMA_REG_DSTADDR 0x20 +#define XILINX_DMA_REG_BTT 0x28 + +/* Channel/Descriptor Offsets */ +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 + +/* General register bits definitions */ +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_DMA_CR_RESET_MASK BIT(2) + +#define XILINX_DMA_CR_DELAY_SHIFT 24 +#define XILINX_DMA_CR_COALESCE_SHIFT 16 + +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) + +#define XILINX_DMA_SR_HALTED_MASK BIT(0) +#define XILINX_DMA_SR_IDLE_MASKBIT(1) + +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) + +/* BD definitions */ +#define XILINX_DMA_BD_STS_ALL_MASK GENMASK(31, 28) +#define XILINX_DMA_BD_SOP BIT(27) +#define XILINX_DMA_BD_EOP BIT(26) + +/* Hw specific definitions */ +#define XILINX_DMA_MAX_CHANS_PER_DEVICE0x2 +#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) + +/* Delay loop
Re: [PATCH v4] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi Mark,
Thanks for reviewing patch.
I should have made a note that the binding patch is applied. I will
make a note of this and add to next versions.
Thanks
Srikanth
On Wed, Oct 15, 2014 at 6:15 PM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
On Wed, Oct 15, 2014 at 01:00:36PM +0100, Srikanth Thokala wrote:
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v4:
- Add direction field to VDMA descriptor structure and removed from
channel structure to avoid duplication.
- Check for DMA idle condition before changing the configuration.
- Residue is being calculated in complete_descriptor() and is reported
to slave driver.
Changes in v3:
- Rebased on 3.16-rc7
Changes in v2:
- Simplified the logic to set SOP and APP words in prep_slave_sg().
- Corrected function description comments to match the return type.
- Fixed some minor comments as suggested by Andy, Thanks.
---
drivers/dma/Kconfig | 13 +
drivers/dma/xilinx/Makefile |1 +
drivers/dma/xilinx/xilinx_dma.c | 1242
+++
include/linux/amba/xilinx_dma.h | 17 +
4 files changed, 1273 insertions(+)
create mode 100644 drivers/dma/xilinx/xilinx_dma.c
[...]
+static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
+struct device_node *node)
+{
+ struct xilinx_dma_chan *chan;
+ int err;
+ bool has_dre;
+ u32 value, width = 0;
+
+ /* Allocate a channel */
+ chan = devm_kzalloc(xdev-dev, sizeof(*chan), GFP_KERNEL);
+ if (!chan)
+ return -ENOMEM;
+
+ chan-dev = xdev-dev;
+ chan-xdev = xdev;
+ chan-has_sg = xdev-has_sg;
+
+ spin_lock_init(chan-lock);
+ INIT_LIST_HEAD(chan-pending_list);
+ INIT_LIST_HEAD(chan-done_list);
+ INIT_LIST_HEAD(chan-free_seg_list);
+
+ /* Get the DT properties */
+ has_dre = of_property_read_bool(node, xlnx,include-dre);
+
+ err = of_property_read_u32(node, xlnx,datawidth, value);
+ if (err) {
+ dev_err(xdev-dev, unable to read datawidth property);
+ return err;
+ }
+
+ width = value 3; /* Convert bits to bytes */
+
+ /* If data width is greater than 8 bytes, DRE is not in hw */
+ if (width 8)
+ has_dre = false;
+
+ if (!has_dre)
+ xdev-common.copy_align = fls(width - 1);
+
+ if (of_device_is_compatible(node, xlnx,axi-dma-mm2s-channel)) {
+ chan-id = 0;
+ chan-ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
+ } else if (of_device_is_compatible(node,
+ xlnx,axi-dma-s2mm-channel)) {
+ chan-id = 1;
+ chan-ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
+ } else {
+ dev_err(xdev-dev, Invalid channel compatible node\n);
+ return -EINVAL;
+ }
+
+ /* Find the IRQ line, if it exists in the device tree */
+ chan-irq = irq_of_parse_and_map(node, 0);
+ err = request_irq(chan-irq, xilinx_dma_irq_handler,
+ IRQF_SHARED,
+ xilinx-dma-controller, chan);
+ if (err) {
+ dev_err(xdev-dev, unable to request IRQ %d\n, chan-irq);
+ return err;
+ }
+
+ /* Initialize the tasklet */
+ tasklet_init(chan-tasklet, xilinx_dma_do_tasklet,
+(unsigned long)chan);
+
+ /*
+* Initialize the DMA channel and add it to the DMA engine channels
+* list.
+*/
+ chan-common.device = xdev-common;
+
+ list_add_tail(chan-common.device_node, xdev-common.channels);
+ xdev-chan[chan-id] = chan;
+
+ /* Reset the channel */
+ err = xilinx_dma_reset(chan);
+ if (err) {
+ dev_err(xdev-dev, Reset channel failed\n);
+ return err;
+ }
+
+ return 0;
+}
+
+/**
+ * of_dma_xilinx_xlate - Translation function
+ * @dma_spec: Pointer to DMA specifier as found in the device tree
+ * @ofdma: Pointer to DMA controller data
+ *
+ * Return: DMA channel pointer on success and NULL on error
+ */
+static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args
*dma_spec,
+ struct of_dma *ofdma)
+{
+ struct xilinx_dma_device *xdev = ofdma-of_dma_data;
+ int chan_id = dma_spec-args[0];
+
+ if (chan_id = XILINX_DMA_MAX_CHANS_PER_DEVICE)
+ return NULL;
+
+ return dma_get_slave_channel(xdev-chan[chan_id]-common
Re: [PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi Vinod,
On Tue, Sep 9, 2014 at 9:27 PM, Vinod Koul wrote:
> On Tue, Sep 09, 2014 at 12:52:16AM +0530, Srikanth Thokala wrote:
>> Hi Vinod,
>>
>> On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul wrote:
>> > On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth Thokala wrote:
>> >> Hi Vinod,
>> >>
>> >> Apologies for the delay.
>> >>
>> >> On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul wrote:
>> >> > On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
>> >> >> +struct xilinx_dma_chan {
>> >> >> + struct xilinx_dma_device *xdev;
>> >> >> + u32 ctrl_offset;
>> >> >> + spinlock_t lock;
>> >> >> + struct list_head pending_list;
>> >> >> + struct xilinx_dma_tx_descriptor *active_desc;
>> >> >> + struct xilinx_dma_tx_descriptor *allocated_desc;
>> >> >> + struct list_head done_list;
>> >> >> + struct list_head free_seg_list;
>> >> >> + struct dma_chan common;
>> >> >> + struct xilinx_dma_tx_segment *seg_v;
>> >> >> + dma_addr_t seg_p;
>> >> >> + struct device *dev;
>> >> >> + int irq;
>> >> >> + int id;
>> >> >> + enum dma_transfer_direction direction;
>> >> > This looks suspect. Why should channel have direction, for a descriptor
>> >> > it
>> >> > makes sense though.
>> >>
>> >> The channel only supports transfers in one direction. Either from memory
>> >> to
>> >> peripheral or from peripheral to memory, that's fixed and can't be changed
>> >> at runtime. So, the driver needs to know which direction the channel
>> >> supports
>> >> and hence it can reject transfers with the wrong direction.
>> > But you already have this information in descriptor so why duplicate?
>>
>> Our descriptor doesn't have the information of channel direction, we have
>> this
>> information only in the chan structure (struct xilinx_dma_chan) which
>> is populated
>> while parsing the DT. So, we use this information to ensure if we are
>> servicing
>> proper channel (in prep_slave_sg call).
> One of the argument of prep_slave_sg call is direction. You need to use that
> and store in in your descriptor for using it afterwards
>
>> FYI: We also need the direction of the channel so that we can select SRC/DST
>> register address in the issue_pending() call.
> And you have the descriptor there as well so can use it
Ok, got it. Thanks. I will send v4 with the changes mentioned.
- Srikanth
>
> --
> ~Vinod
>
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Re: [PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi Vinod,
On Tue, Sep 9, 2014 at 9:27 PM, Vinod Koul vinod.k...@intel.com wrote:
On Tue, Sep 09, 2014 at 12:52:16AM +0530, Srikanth Thokala wrote:
Hi Vinod,
On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul vinod.k...@intel.com wrote:
On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth Thokala wrote:
Hi Vinod,
Apologies for the delay.
On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
+struct xilinx_dma_chan {
+ struct xilinx_dma_device *xdev;
+ u32 ctrl_offset;
+ spinlock_t lock;
+ struct list_head pending_list;
+ struct xilinx_dma_tx_descriptor *active_desc;
+ struct xilinx_dma_tx_descriptor *allocated_desc;
+ struct list_head done_list;
+ struct list_head free_seg_list;
+ struct dma_chan common;
+ struct xilinx_dma_tx_segment *seg_v;
+ dma_addr_t seg_p;
+ struct device *dev;
+ int irq;
+ int id;
+ enum dma_transfer_direction direction;
This looks suspect. Why should channel have direction, for a descriptor
it
makes sense though.
The channel only supports transfers in one direction. Either from memory
to
peripheral or from peripheral to memory, that's fixed and can't be changed
at runtime. So, the driver needs to know which direction the channel
supports
and hence it can reject transfers with the wrong direction.
But you already have this information in descriptor so why duplicate?
Our descriptor doesn't have the information of channel direction, we have
this
information only in the chan structure (struct xilinx_dma_chan) which
is populated
while parsing the DT. So, we use this information to ensure if we are
servicing
proper channel (in prep_slave_sg call).
One of the argument of prep_slave_sg call is direction. You need to use that
and store in in your descriptor for using it afterwards
FYI: We also need the direction of the channel so that we can select SRC/DST
register address in the issue_pending() call.
And you have the descriptor there as well so can use it
Ok, got it. Thanks. I will send v4 with the changes mentioned.
- Srikanth
--
~Vinod
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Re: [PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi Vinod,
On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul wrote:
> On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth Thokala wrote:
>> Hi Vinod,
>>
>> Apologies for the delay.
>>
>> On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul wrote:
>> > On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
>> >> +struct xilinx_dma_chan {
>> >> + struct xilinx_dma_device *xdev;
>> >> + u32 ctrl_offset;
>> >> + spinlock_t lock;
>> >> + struct list_head pending_list;
>> >> + struct xilinx_dma_tx_descriptor *active_desc;
>> >> + struct xilinx_dma_tx_descriptor *allocated_desc;
>> >> + struct list_head done_list;
>> >> + struct list_head free_seg_list;
>> >> + struct dma_chan common;
>> >> + struct xilinx_dma_tx_segment *seg_v;
>> >> + dma_addr_t seg_p;
>> >> + struct device *dev;
>> >> + int irq;
>> >> + int id;
>> >> + enum dma_transfer_direction direction;
>> > This looks suspect. Why should channel have direction, for a descriptor it
>> > makes sense though.
>>
>> The channel only supports transfers in one direction. Either from memory to
>> peripheral or from peripheral to memory, that's fixed and can't be changed
>> at runtime. So, the driver needs to know which direction the channel
>> supports
>> and hence it can reject transfers with the wrong direction.
> But you already have this information in descriptor so why duplicate?
Our descriptor doesn't have the information of channel direction, we have this
information only in the chan structure (struct xilinx_dma_chan) which
is populated
while parsing the DT. So, we use this information to ensure if we are servicing
proper channel (in prep_slave_sg call).
FYI: We also need the direction of the channel so that we can select SRC/DST
register address in the issue_pending() call.
Could you please elaborate, if I am missing something?
>
>> >> +/**
>> >> + * xilinx_dma_channel_set_config - Configure DMA channel
>> >> + * @dchan: DMA channel
>> >> + * @cfg: DMA device configuration pointer
>> >> + *
>> >> + * Return: '0' on success and failure value on error
>> >> + */
>> >> +int xilinx_dma_channel_set_config(struct dma_chan *dchan,
>> >> + struct xilinx_dma_config *cfg)
>> >> +{
>> >> + struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
>> >> + u32 reg = dma_ctrl_read(chan, XILINX_DMA_REG_CONTROL);
>> >> +
>> >> + if (cfg->reset)
>> >> + return xilinx_dma_reset(chan);
>> >> +
>> >> + if (cfg->coalesc <= XILINX_DMA_CR_COALESCE_MAX)
>> >> + reg |= cfg->coalesc << XILINX_DMA_CR_COALESCE_SHIFT;
>> >> +
>> >> + if (cfg->delay <= XILINX_DMA_CR_DELAY_MAX)
>> >> + reg |= cfg->delay << XILINX_DMA_CR_DELAY_SHIFT;
>> >> +
>> >> + dma_ctrl_write(chan, XILINX_DMA_REG_CONTROL, reg);
>> > You aren't checking if a transaction is already running on this channel.
>> > Also don't you need other slave parameters, I see you have removed the
>> > dma_slave_config entirely
>>
>> All the parameters that are required for this DMA engine are provided by
>> SG list, so I don't see the need of dma_slave_config. There are some
>> specific IP parameters that are not part of dma_slave_config and these
>> are being set by 'dma_channel_set_config' which is exported to slave
>> drivers.
> And that means you dont have any common parameters between dma_slave_config
> right?
Yes, true.
Thanks,
Srikanth
>
> --
> ~Vinod
>
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Re: [PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi Vinod,
On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul vinod.k...@intel.com wrote:
On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth Thokala wrote:
Hi Vinod,
Apologies for the delay.
On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
+struct xilinx_dma_chan {
+ struct xilinx_dma_device *xdev;
+ u32 ctrl_offset;
+ spinlock_t lock;
+ struct list_head pending_list;
+ struct xilinx_dma_tx_descriptor *active_desc;
+ struct xilinx_dma_tx_descriptor *allocated_desc;
+ struct list_head done_list;
+ struct list_head free_seg_list;
+ struct dma_chan common;
+ struct xilinx_dma_tx_segment *seg_v;
+ dma_addr_t seg_p;
+ struct device *dev;
+ int irq;
+ int id;
+ enum dma_transfer_direction direction;
This looks suspect. Why should channel have direction, for a descriptor it
makes sense though.
The channel only supports transfers in one direction. Either from memory to
peripheral or from peripheral to memory, that's fixed and can't be changed
at runtime. So, the driver needs to know which direction the channel
supports
and hence it can reject transfers with the wrong direction.
But you already have this information in descriptor so why duplicate?
Our descriptor doesn't have the information of channel direction, we have this
information only in the chan structure (struct xilinx_dma_chan) which
is populated
while parsing the DT. So, we use this information to ensure if we are servicing
proper channel (in prep_slave_sg call).
FYI: We also need the direction of the channel so that we can select SRC/DST
register address in the issue_pending() call.
Could you please elaborate, if I am missing something?
+/**
+ * xilinx_dma_channel_set_config - Configure DMA channel
+ * @dchan: DMA channel
+ * @cfg: DMA device configuration pointer
+ *
+ * Return: '0' on success and failure value on error
+ */
+int xilinx_dma_channel_set_config(struct dma_chan *dchan,
+ struct xilinx_dma_config *cfg)
+{
+ struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
+ u32 reg = dma_ctrl_read(chan, XILINX_DMA_REG_CONTROL);
+
+ if (cfg-reset)
+ return xilinx_dma_reset(chan);
+
+ if (cfg-coalesc = XILINX_DMA_CR_COALESCE_MAX)
+ reg |= cfg-coalesc XILINX_DMA_CR_COALESCE_SHIFT;
+
+ if (cfg-delay = XILINX_DMA_CR_DELAY_MAX)
+ reg |= cfg-delay XILINX_DMA_CR_DELAY_SHIFT;
+
+ dma_ctrl_write(chan, XILINX_DMA_REG_CONTROL, reg);
You aren't checking if a transaction is already running on this channel.
Also don't you need other slave parameters, I see you have removed the
dma_slave_config entirely
All the parameters that are required for this DMA engine are provided by
SG list, so I don't see the need of dma_slave_config. There are some
specific IP parameters that are not part of dma_slave_config and these
are being set by 'dma_channel_set_config' which is exported to slave
drivers.
And that means you dont have any common parameters between dma_slave_config
right?
Yes, true.
Thanks,
Srikanth
--
~Vinod
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Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, Sep 3, 2014 at 11:35 PM, Bjorn Helgaas wrote: > On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote: >> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP >> >> Signed-off-by: Srikanth Thokala >> Acked-by: Arnd Bergmann > > Applied to pci/host-xilinx for v3.18, thanks! Thanks Bjorn! Srikanth > >> --- >> Changes in v7: >> - Removed errors reported from build-bot. The errors are >> mainly due to same CONFIG_PCI_XILINX flag being used for >> Zynq and Microblaze platforms. So, renamed the driver >> config flag name to CONFIG_PCIE_XILINX. >> - Also, renamed the driver file to pcie-xilinx.c to be in >> sync with CONFIG option. >> - Fixed the annotation of xilinx_pcie_scan_bus() function >> to remove build-bot warnings. >> >> Changes in v6: >> - Added Ack from Arnd. Thanks Arnd. >> - Rebased on 3.16-rc7. >> >> Changes in v5: >> - Removed unnecessary checking of port structure. >> - Changed the return type of verify_config from int to bool. >> - Renamed following functions, >> xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up() >> xilinx_pcie_verify_config() -> xilinx_pcie_valid_device() >> xilinx_pcie_get_config_base() -> xilinx_pcie_config_base() >> - Removed link_up bool flag from port structure, as it is not >> being used. >> - Removed unused constants. >> - Rebased on 3.16-rc6. >> - Fixed some minor comments. >> - Thanks Bjorn for the review. >> >> Changes in v4: >> - Regarding the comments to separate ECAM functionality, >> I have sent a separate patch and it is decided to implement >> it later. The patch is here, >> https://lkml.org/lkml/2014/5/18/54 >> - Fixed issue with adding configuration bus resource. >> - Moved the logic for setting up bus resources to probe() from >> pcie_setup(). >> - Instead of mapping all the MSI interrupts in the probe, changed >> to map only when a MSI is requested. >> - Earlier, the implementation of legacy and MSI interrupts init- >> is mutually exclusive, now changed to have the legacy interrupts >> init always and MSI interrupt init based on CONFIG_PCI_MSI flag. >> - Regarding the MSI generic implementation comment, I will plan to >> do on top of this driver patch. >> - Rebased on 3.16-rc2. >> - Fixed other minor comments. >> - Thanks Arnd and Bjorn for the review. >> >> Changes in v3: >> - Rebased on v3.15.0-rc1 >> - Added support for interrupt-map DT functionality. >> - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). >> - Modified resource mapping logic as per the series >> "PCI: ARM: add support for generic PCI host controller" >> - Modified devicetree binding documentation to update with interrupt- >> map properties. >> - Use devm calls wherever applicable. >> - Fixed minor comments from Jason >> - Thanks Jason for the review and suggestions. >> >> Changes in v2: >> - Rebased on v3.14.0-rc8 >> - Removed IP specific DT properties like include-rc, axibar-num etc., >> as suggested by Jason and Bjorn, Thanks >> --- >> .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ >> drivers/pci/host/Kconfig |7 + >> drivers/pci/host/Makefile |1 + >> drivers/pci/host/pcie-xilinx.c | 978 >> >> 4 files changed, 1048 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> create mode 100644 drivers/pci/host/pcie-xilinx.c >> >> diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> new file mode 100644 >> index 000..3e2c88d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> @@ -0,0 +1,62 @@ >> +* Xilinx AXI PCIe Root Port Bridge DT description >> + >> +Required properties: >> +- #address-cells: Address representation for root ports, set to <3> >> +- #size-cells: Size representation for root ports, set to <2> >> +- #interrupt-cells: specifies the number of cells needed to encode an >> + interrupt source. The value must be 1. >> +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" >> +- reg: Should contain AXI PCIe registers location and length >> +- device_type: must be "pci" >> +- interrupts: Should contain AXI PCIe interrupt >> +- interrupt-map-mask, >> + interrupt-map: standard
Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, Sep 3, 2014 at 11:35 PM, Bjorn Helgaas bhelg...@google.com wrote: On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote: This is the driver for Xilinx AXI PCIe Host Bridge Soft IP Signed-off-by: Srikanth Thokala stho...@xilinx.com Acked-by: Arnd Bergmann a...@arndb.de Applied to pci/host-xilinx for v3.18, thanks! Thanks Bjorn! Srikanth --- Changes in v7: - Removed errors reported from build-bot. The errors are mainly due to same CONFIG_PCI_XILINX flag being used for Zynq and Microblaze platforms. So, renamed the driver config flag name to CONFIG_PCIE_XILINX. - Also, renamed the driver file to pcie-xilinx.c to be in sync with CONFIG option. - Fixed the annotation of xilinx_pcie_scan_bus() function to remove build-bot warnings. Changes in v6: - Added Ack from Arnd. Thanks Arnd. - Rebased on 3.16-rc7. Changes in v5: - Removed unnecessary checking of port structure. - Changed the return type of verify_config from int to bool. - Renamed following functions, xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up() xilinx_pcie_verify_config() - xilinx_pcie_valid_device() xilinx_pcie_get_config_base() - xilinx_pcie_config_base() - Removed link_up bool flag from port structure, as it is not being used. - Removed unused constants. - Rebased on 3.16-rc6. - Fixed some minor comments. - Thanks Bjorn for the review. Changes in v4: - Regarding the comments to separate ECAM functionality, I have sent a separate patch and it is decided to implement it later. The patch is here, https://lkml.org/lkml/2014/5/18/54 - Fixed issue with adding configuration bus resource. - Moved the logic for setting up bus resources to probe() from pcie_setup(). - Instead of mapping all the MSI interrupts in the probe, changed to map only when a MSI is requested. - Earlier, the implementation of legacy and MSI interrupts init- is mutually exclusive, now changed to have the legacy interrupts init always and MSI interrupt init based on CONFIG_PCI_MSI flag. - Regarding the MSI generic implementation comment, I will plan to do on top of this driver patch. - Rebased on 3.16-rc2. - Fixed other minor comments. - Thanks Arnd and Bjorn for the review. Changes in v3: - Rebased on v3.15.0-rc1 - Added support for interrupt-map DT functionality. - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). - Modified resource mapping logic as per the series PCI: ARM: add support for generic PCI host controller - Modified devicetree binding documentation to update with interrupt- map properties. - Use devm calls wherever applicable. - Fixed minor comments from Jason - Thanks Jason for the review and suggestions. Changes in v2: - Rebased on v3.14.0-rc8 - Removed IP specific DT properties like include-rc, axibar-num etc., as suggested by Jason and Bjorn, Thanks --- .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ drivers/pci/host/Kconfig |7 + drivers/pci/host/Makefile |1 + drivers/pci/host/pcie-xilinx.c | 978 4 files changed, 1048 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 drivers/pci/host/pcie-xilinx.c diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt new file mode 100644 index 000..3e2c88d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -0,0 +1,62 @@ +* Xilinx AXI PCIe Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to 3 +- #size-cells: Size representation for root ports, set to 2 +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain xlnx,axi-pcie-host-1.00.a +- reg: Should contain AXI PCIe registers location and length +- device_type: must be pci +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation + +Optional properties: +- bus-range: PCI bus numbers covered + +Interrupt controller child node +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + +NOTE: +The core provides a single interrupt for both INTx/MSI
Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, I fixed the mentioned issues with build-bot in v7. Could you please take this patch? Thanks Srikanth On Wed, Aug 20, 2014 at 9:56 PM, Srikanth Thokala wrote: > This is the driver for Xilinx AXI PCIe Host Bridge Soft IP > > Signed-off-by: Srikanth Thokala > Acked-by: Arnd Bergmann > --- > Changes in v7: > - Removed errors reported from build-bot. The errors are > mainly due to same CONFIG_PCI_XILINX flag being used for > Zynq and Microblaze platforms. So, renamed the driver > config flag name to CONFIG_PCIE_XILINX. > - Also, renamed the driver file to pcie-xilinx.c to be in > sync with CONFIG option. > - Fixed the annotation of xilinx_pcie_scan_bus() function > to remove build-bot warnings. > > Changes in v6: > - Added Ack from Arnd. Thanks Arnd. > - Rebased on 3.16-rc7. > > Changes in v5: > - Removed unnecessary checking of port structure. > - Changed the return type of verify_config from int to bool. > - Renamed following functions, > xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up() > xilinx_pcie_verify_config() -> xilinx_pcie_valid_device() > xilinx_pcie_get_config_base() -> xilinx_pcie_config_base() > - Removed link_up bool flag from port structure, as it is not > being used. > - Removed unused constants. > - Rebased on 3.16-rc6. > - Fixed some minor comments. > - Thanks Bjorn for the review. > > Changes in v4: > - Regarding the comments to separate ECAM functionality, > I have sent a separate patch and it is decided to implement > it later. The patch is here, > https://lkml.org/lkml/2014/5/18/54 > - Fixed issue with adding configuration bus resource. > - Moved the logic for setting up bus resources to probe() from > pcie_setup(). > - Instead of mapping all the MSI interrupts in the probe, changed > to map only when a MSI is requested. > - Earlier, the implementation of legacy and MSI interrupts init- > is mutually exclusive, now changed to have the legacy interrupts > init always and MSI interrupt init based on CONFIG_PCI_MSI flag. > - Regarding the MSI generic implementation comment, I will plan to > do on top of this driver patch. > - Rebased on 3.16-rc2. > - Fixed other minor comments. > - Thanks Arnd and Bjorn for the review. > > Changes in v3: > - Rebased on v3.15.0-rc1 > - Added support for interrupt-map DT functionality. > - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). > - Modified resource mapping logic as per the series > "PCI: ARM: add support for generic PCI host controller" > - Modified devicetree binding documentation to update with interrupt- > map properties. > - Use devm calls wherever applicable. > - Fixed minor comments from Jason > - Thanks Jason for the review and suggestions. > > Changes in v2: > - Rebased on v3.14.0-rc8 > - Removed IP specific DT properties like include-rc, axibar-num etc., > as suggested by Jason and Bjorn, Thanks > --- > .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ > drivers/pci/host/Kconfig |7 + > drivers/pci/host/Makefile |1 + > drivers/pci/host/pcie-xilinx.c | 978 > > 4 files changed, 1048 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt > create mode 100644 drivers/pci/host/pcie-xilinx.c > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > new file mode 100644 > index 000..3e2c88d > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > @@ -0,0 +1,62 @@ > +* Xilinx AXI PCIe Root Port Bridge DT description > + > +Required properties: > +- #address-cells: Address representation for root ports, set to <3> > +- #size-cells: Size representation for root ports, set to <2> > +- #interrupt-cells: specifies the number of cells needed to encode an > + interrupt source. The value must be 1. > +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" > +- reg: Should contain AXI PCIe registers location and length > +- device_type: must be "pci" > +- interrupts: Should contain AXI PCIe interrupt > +- interrupt-map-mask, > + interrupt-map: standard PCI properties to define the mapping of the > + PCI interface to interrupt numbers. > +- ranges: ranges for the PCI memory regions (I/O space region is not > + supported by hardware) > + Please refer to the standard PCI bus binding document for a more > + detailed explanation > + > +Optional properties: > +- bus-range: PCI bus numbers covered > + > +Interrupt controller
Re: [PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi Vinod,
Apologies for the delay.
On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul wrote:
> On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
>> +struct xilinx_dma_chan {
>> + struct xilinx_dma_device *xdev;
>> + u32 ctrl_offset;
>> + spinlock_t lock;
>> + struct list_head pending_list;
>> + struct xilinx_dma_tx_descriptor *active_desc;
>> + struct xilinx_dma_tx_descriptor *allocated_desc;
>> + struct list_head done_list;
>> + struct list_head free_seg_list;
>> + struct dma_chan common;
>> + struct xilinx_dma_tx_segment *seg_v;
>> + dma_addr_t seg_p;
>> + struct device *dev;
>> + int irq;
>> + int id;
>> + enum dma_transfer_direction direction;
> This looks suspect. Why should channel have direction, for a descriptor it
> makes sense though.
The channel only supports transfers in one direction. Either from memory to
peripheral or from peripheral to memory, that's fixed and can't be changed
at runtime. So, the driver needs to know which direction the channel supports
and hence it can reject transfers with the wrong direction.
>
>> +static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
>> + dma_cookie_t cookie,
>> + struct dma_tx_state *txstate)
>> +{
>> + struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
>> + enum dma_status ret;
>> + unsigned long flags;
>> +
>> + ret = dma_cookie_status(dchan, cookie, txstate);
>> + if (ret != DMA_COMPLETE) {
>> + spin_lock_irqsave(>lock, flags);
>> + dma_set_residue(txstate, chan->residue);
>> + spin_unlock_irqrestore(>lock, flags);
>> + }
> No residue reporting?
I will fix this, thanks.
>
>> +static int xilinx_dma_device_control(struct dma_chan *dchan,
>> + enum dma_ctrl_cmd cmd, unsigned long arg)
>> +{
>> + struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
>> + unsigned long flags;
>> +
>> + if (cmd != DMA_TERMINATE_ALL)
>> + return -ENXIO;
>> +
>> + /* Halt the DMA engine */
>> + xilinx_dma_halt(chan);
>> +
>> + spin_lock_irqsave(>lock, flags);
>> +
>> + /* Remove and free all of the descriptors in the lists */
>> + xilinx_dma_free_desc_list(chan, >pending_list);
>> + xilinx_dma_free_desc_list(chan, >done_list);
>
>> +
>> + spin_unlock_irqrestore(>lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * xilinx_dma_channel_set_config - Configure DMA channel
>> + * @dchan: DMA channel
>> + * @cfg: DMA device configuration pointer
>> + *
>> + * Return: '0' on success and failure value on error
>> + */
>> +int xilinx_dma_channel_set_config(struct dma_chan *dchan,
>> + struct xilinx_dma_config *cfg)
>> +{
>> + struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
>> + u32 reg = dma_ctrl_read(chan, XILINX_DMA_REG_CONTROL);
>> +
>> + if (cfg->reset)
>> + return xilinx_dma_reset(chan);
>> +
>> + if (cfg->coalesc <= XILINX_DMA_CR_COALESCE_MAX)
>> + reg |= cfg->coalesc << XILINX_DMA_CR_COALESCE_SHIFT;
>> +
>> + if (cfg->delay <= XILINX_DMA_CR_DELAY_MAX)
>> + reg |= cfg->delay << XILINX_DMA_CR_DELAY_SHIFT;
>> +
>> + dma_ctrl_write(chan, XILINX_DMA_REG_CONTROL, reg);
> You aren't checking if a transaction is already running on this channel.
> Also don't you need other slave parameters, I see you have removed the
> dma_slave_config entirely
All the parameters that are required for this DMA engine are provided by
SG list, so I don't see the need of dma_slave_config. There are some
specific IP parameters that are not part of dma_slave_config and these
are being set by 'dma_channel_set_config' which is exported to slave
drivers.
Thanks for the reveiw,
Srikanth
>
> --
> ~Vinod
> --
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Re: [PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi Vinod,
Apologies for the delay.
On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
+struct xilinx_dma_chan {
+ struct xilinx_dma_device *xdev;
+ u32 ctrl_offset;
+ spinlock_t lock;
+ struct list_head pending_list;
+ struct xilinx_dma_tx_descriptor *active_desc;
+ struct xilinx_dma_tx_descriptor *allocated_desc;
+ struct list_head done_list;
+ struct list_head free_seg_list;
+ struct dma_chan common;
+ struct xilinx_dma_tx_segment *seg_v;
+ dma_addr_t seg_p;
+ struct device *dev;
+ int irq;
+ int id;
+ enum dma_transfer_direction direction;
This looks suspect. Why should channel have direction, for a descriptor it
makes sense though.
The channel only supports transfers in one direction. Either from memory to
peripheral or from peripheral to memory, that's fixed and can't be changed
at runtime. So, the driver needs to know which direction the channel supports
and hence it can reject transfers with the wrong direction.
+static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
+ enum dma_status ret;
+ unsigned long flags;
+
+ ret = dma_cookie_status(dchan, cookie, txstate);
+ if (ret != DMA_COMPLETE) {
+ spin_lock_irqsave(chan-lock, flags);
+ dma_set_residue(txstate, chan-residue);
+ spin_unlock_irqrestore(chan-lock, flags);
+ }
No residue reporting?
I will fix this, thanks.
+static int xilinx_dma_device_control(struct dma_chan *dchan,
+ enum dma_ctrl_cmd cmd, unsigned long arg)
+{
+ struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
+ unsigned long flags;
+
+ if (cmd != DMA_TERMINATE_ALL)
+ return -ENXIO;
+
+ /* Halt the DMA engine */
+ xilinx_dma_halt(chan);
+
+ spin_lock_irqsave(chan-lock, flags);
+
+ /* Remove and free all of the descriptors in the lists */
+ xilinx_dma_free_desc_list(chan, chan-pending_list);
+ xilinx_dma_free_desc_list(chan, chan-done_list);
+
+ spin_unlock_irqrestore(chan-lock, flags);
+
+ return 0;
+}
+
+/**
+ * xilinx_dma_channel_set_config - Configure DMA channel
+ * @dchan: DMA channel
+ * @cfg: DMA device configuration pointer
+ *
+ * Return: '0' on success and failure value on error
+ */
+int xilinx_dma_channel_set_config(struct dma_chan *dchan,
+ struct xilinx_dma_config *cfg)
+{
+ struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
+ u32 reg = dma_ctrl_read(chan, XILINX_DMA_REG_CONTROL);
+
+ if (cfg-reset)
+ return xilinx_dma_reset(chan);
+
+ if (cfg-coalesc = XILINX_DMA_CR_COALESCE_MAX)
+ reg |= cfg-coalesc XILINX_DMA_CR_COALESCE_SHIFT;
+
+ if (cfg-delay = XILINX_DMA_CR_DELAY_MAX)
+ reg |= cfg-delay XILINX_DMA_CR_DELAY_SHIFT;
+
+ dma_ctrl_write(chan, XILINX_DMA_REG_CONTROL, reg);
You aren't checking if a transaction is already running on this channel.
Also don't you need other slave parameters, I see you have removed the
dma_slave_config entirely
All the parameters that are required for this DMA engine are provided by
SG list, so I don't see the need of dma_slave_config. There are some
specific IP parameters that are not part of dma_slave_config and these
are being set by 'dma_channel_set_config' which is exported to slave
drivers.
Thanks for the reveiw,
Srikanth
--
~Vinod
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Re: [PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, I fixed the mentioned issues with build-bot in v7. Could you please take this patch? Thanks Srikanth On Wed, Aug 20, 2014 at 9:56 PM, Srikanth Thokala stho...@xilinx.com wrote: This is the driver for Xilinx AXI PCIe Host Bridge Soft IP Signed-off-by: Srikanth Thokala stho...@xilinx.com Acked-by: Arnd Bergmann a...@arndb.de --- Changes in v7: - Removed errors reported from build-bot. The errors are mainly due to same CONFIG_PCI_XILINX flag being used for Zynq and Microblaze platforms. So, renamed the driver config flag name to CONFIG_PCIE_XILINX. - Also, renamed the driver file to pcie-xilinx.c to be in sync with CONFIG option. - Fixed the annotation of xilinx_pcie_scan_bus() function to remove build-bot warnings. Changes in v6: - Added Ack from Arnd. Thanks Arnd. - Rebased on 3.16-rc7. Changes in v5: - Removed unnecessary checking of port structure. - Changed the return type of verify_config from int to bool. - Renamed following functions, xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up() xilinx_pcie_verify_config() - xilinx_pcie_valid_device() xilinx_pcie_get_config_base() - xilinx_pcie_config_base() - Removed link_up bool flag from port structure, as it is not being used. - Removed unused constants. - Rebased on 3.16-rc6. - Fixed some minor comments. - Thanks Bjorn for the review. Changes in v4: - Regarding the comments to separate ECAM functionality, I have sent a separate patch and it is decided to implement it later. The patch is here, https://lkml.org/lkml/2014/5/18/54 - Fixed issue with adding configuration bus resource. - Moved the logic for setting up bus resources to probe() from pcie_setup(). - Instead of mapping all the MSI interrupts in the probe, changed to map only when a MSI is requested. - Earlier, the implementation of legacy and MSI interrupts init- is mutually exclusive, now changed to have the legacy interrupts init always and MSI interrupt init based on CONFIG_PCI_MSI flag. - Regarding the MSI generic implementation comment, I will plan to do on top of this driver patch. - Rebased on 3.16-rc2. - Fixed other minor comments. - Thanks Arnd and Bjorn for the review. Changes in v3: - Rebased on v3.15.0-rc1 - Added support for interrupt-map DT functionality. - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). - Modified resource mapping logic as per the series PCI: ARM: add support for generic PCI host controller - Modified devicetree binding documentation to update with interrupt- map properties. - Use devm calls wherever applicable. - Fixed minor comments from Jason - Thanks Jason for the review and suggestions. Changes in v2: - Rebased on v3.14.0-rc8 - Removed IP specific DT properties like include-rc, axibar-num etc., as suggested by Jason and Bjorn, Thanks --- .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ drivers/pci/host/Kconfig |7 + drivers/pci/host/Makefile |1 + drivers/pci/host/pcie-xilinx.c | 978 4 files changed, 1048 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 drivers/pci/host/pcie-xilinx.c diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt new file mode 100644 index 000..3e2c88d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -0,0 +1,62 @@ +* Xilinx AXI PCIe Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to 3 +- #size-cells: Size representation for root ports, set to 2 +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain xlnx,axi-pcie-host-1.00.a +- reg: Should contain AXI PCIe registers location and length +- device_type: must be pci +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation + +Optional properties: +- bus-range: PCI bus numbers covered + +Interrupt controller child node +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + +NOTE: +The core provides a single interrupt for both INTx/MSI messages. So
[PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP Signed-off-by: Srikanth Thokala Acked-by: Arnd Bergmann --- Changes in v7: - Removed errors reported from build-bot. The errors are mainly due to same CONFIG_PCI_XILINX flag being used for Zynq and Microblaze platforms. So, renamed the driver config flag name to CONFIG_PCIE_XILINX. - Also, renamed the driver file to pcie-xilinx.c to be in sync with CONFIG option. - Fixed the annotation of xilinx_pcie_scan_bus() function to remove build-bot warnings. Changes in v6: - Added Ack from Arnd. Thanks Arnd. - Rebased on 3.16-rc7. Changes in v5: - Removed unnecessary checking of port structure. - Changed the return type of verify_config from int to bool. - Renamed following functions, xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up() xilinx_pcie_verify_config() -> xilinx_pcie_valid_device() xilinx_pcie_get_config_base() -> xilinx_pcie_config_base() - Removed link_up bool flag from port structure, as it is not being used. - Removed unused constants. - Rebased on 3.16-rc6. - Fixed some minor comments. - Thanks Bjorn for the review. Changes in v4: - Regarding the comments to separate ECAM functionality, I have sent a separate patch and it is decided to implement it later. The patch is here, https://lkml.org/lkml/2014/5/18/54 - Fixed issue with adding configuration bus resource. - Moved the logic for setting up bus resources to probe() from pcie_setup(). - Instead of mapping all the MSI interrupts in the probe, changed to map only when a MSI is requested. - Earlier, the implementation of legacy and MSI interrupts init- is mutually exclusive, now changed to have the legacy interrupts init always and MSI interrupt init based on CONFIG_PCI_MSI flag. - Regarding the MSI generic implementation comment, I will plan to do on top of this driver patch. - Rebased on 3.16-rc2. - Fixed other minor comments. - Thanks Arnd and Bjorn for the review. Changes in v3: - Rebased on v3.15.0-rc1 - Added support for interrupt-map DT functionality. - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). - Modified resource mapping logic as per the series "PCI: ARM: add support for generic PCI host controller" - Modified devicetree binding documentation to update with interrupt- map properties. - Use devm calls wherever applicable. - Fixed minor comments from Jason - Thanks Jason for the review and suggestions. Changes in v2: - Rebased on v3.14.0-rc8 - Removed IP specific DT properties like include-rc, axibar-num etc., as suggested by Jason and Bjorn, Thanks --- .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ drivers/pci/host/Kconfig |7 + drivers/pci/host/Makefile |1 + drivers/pci/host/pcie-xilinx.c | 978 4 files changed, 1048 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 drivers/pci/host/pcie-xilinx.c diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt new file mode 100644 index 000..3e2c88d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -0,0 +1,62 @@ +* Xilinx AXI PCIe Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to <3> +- #size-cells: Size representation for root ports, set to <2> +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" +- reg: Should contain AXI PCIe registers location and length +- device_type: must be "pci" +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation + +Optional properties: +- bus-range: PCI bus numbers covered + +Interrupt controller child node +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + +NOTE: +The core provides a single interrupt for both INTx/MSI messages. So, +created a interrupt controller node to support 'interrupt-map' DT +functionality. The driver will create an IRQ domain for this map, decode +the four INTx interrupts in ISR and route them to this domain. + + +Example: + + + pci_express: axi-
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, On Tue, Aug 19, 2014 at 12:19 AM, Bjorn Helgaas wrote: > On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote: >> Hi Michal, >> >> On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote: >> > Hi Bjorn, >> > >> > On 07/30/2014 01:24 PM, Srikanth Thokala wrote: >> >> Hi Arnd, >> >> >> >> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote: >> >>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: >> >>>> Hi Arnd and Rob, >> >>>> >> >>>> I discussed with Bjorn and we believe this patch is in good shape to >> >>>> apply. And Bjorn requires ACKs to apply this patch. So, could you >> >>>> guys please review this patch and provided your ACKs to this patch. >> >>> >> >>> Looks great for the most part. I've looked through the whole driver >> >>> again, and I have two small issues remaining: >> >>> >> >>> a) Please clarify in the changeset description why there is no support >> >>>for PCI I/O space. >> >> >> >> Sure, I will add to my changeset. >> >> >> >>> >> >>> b) I think you should use the 'msi-parent' property, and the >> >>>of_pci_find_msi_chip_by_node() to find the msi_chip for the >> >>>PCI controller. This will make it possible to forward MSIs >> >>>to the main interrupt controller in the system, which is more >> >>>efficient. See the pcie-mvebu driver for an example of this. >> >> >> >> Ok, I need to look into this and I will plan to implement on top of this >> >> patch. >> >> >> >>> >> >>> Other than these: >> >>> >> >>> Acked-by: Arnd Bergmann >> >> >> >> Thanks Arnd for the Ack. >> > >> > What's the status on this one? >> >> It looks like Bjorn is on vacation. I have sent v6 patch by adding >> Ack from Arnd, which >> I feel is in good shape to be applied. > > I actually started applying this last night (see [1]), but got some > errors from the build-bot (attached). I haven't looked into them, > but my guess is that you're missing a Kconfig dependency or something > equally minor. These are due to the same config flag name (CONFIG_PCI_XILINX) being used for Microblaze and Zynq platforms. I will fix it and send you next version of patch. Thanks, Srikanth > > Bjorn > > [1] > http://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-xilinx=a58f3d0c3b1c4a71a2418c3306fba86c26a49781 > > > -- Forwarded message -- > From: kbuild test robot > To: Bjorn Helgaas > Cc: > Date: Mon, 18 Aug 2014 12:40:06 +0800 > Subject: [pci:pci/host-xilinx] a58f3d0c3b1c4a71a2418c3306fba86c26a49781 BUILD > DONE > git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-xilinx > a58f3d0c3b1c4a71a2418c3306fba86c26a49781 PCI: xilinx: Add Xilinx PCIe Host > Bridge IP driver > > drivers/pci/host/pci-xilinx.c:470:21: error: 'IRQF_VALID' undeclared (first > use in this function) > drivers/pci/host/pci-xilinx.c:742:14: error: dereferencing pointer to > incomplete type > drivers/pci/host/pci-xilinx.c:939:2: error: implicit declaration of function > 'pci_common_init_dev' [-Werror=implicit-function-declaration] > drivers/pci/host/pci-xilinx.c:417:2: error: implicit declaration of function > 'set_irq_flags' [-Werror=implicit-function-declaration] > drivers/pci/host/pci-xilinx.c:938:2: error: invalid use of undefined type > 'struct hw_pci' > drivers/pci/host/pci-xilinx.c:888:16: error: storage size of 'hw' isn't known > drivers/pci/host/pci-xilinx.c:935:3: error: unknown field 'add_bus' specified > in initializer > drivers/pci/host/pci-xilinx.c:934:3: error: unknown field 'map_irq' specified > in initializer > drivers/pci/host/pci-xilinx.c:931:3: error: unknown field 'nr_controllers' > specified in initializer > drivers/pci/host/pci-xilinx.c:937:3: error: unknown field 'ops' specified in > initializer > drivers/pci/host/pci-xilinx.c:932:3: error: unknown field 'private_data' > specified in initializer > drivers/pci/host/pci-xilinx.c:936:3: error: unknown field 'scan' specified in > initializer > drivers/pci/host/pci-xilinx.c:933:3: error: unknown field 'setup' specified > in initializer > drivers/pci/host/pci-xilinx.c:937:3: warning: (near initialization for > '(anonymous)') > drivers/pci/host/pci-xilinx.c:937:3: warning: excess elements in struct > initializer > drivers/pci/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, On Tue, Aug 19, 2014 at 12:19 AM, Bjorn Helgaas bhelg...@google.com wrote: On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote: Hi Michal, On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek mon...@monstr.eu wrote: Hi Bjorn, On 07/30/2014 01:24 PM, Srikanth Thokala wrote: Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. Sure, I will add to my changeset. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. Other than these: Acked-by: Arnd Bergmann a...@arndb.de Thanks Arnd for the Ack. What's the status on this one? It looks like Bjorn is on vacation. I have sent v6 patch by adding Ack from Arnd, which I feel is in good shape to be applied. I actually started applying this last night (see [1]), but got some errors from the build-bot (attached). I haven't looked into them, but my guess is that you're missing a Kconfig dependency or something equally minor. These are due to the same config flag name (CONFIG_PCI_XILINX) being used for Microblaze and Zynq platforms. I will fix it and send you next version of patch. Thanks, Srikanth Bjorn [1] http://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-xilinxid=a58f3d0c3b1c4a71a2418c3306fba86c26a49781 -- Forwarded message -- From: kbuild test robot fengguang...@intel.com To: Bjorn Helgaas bhelg...@google.com Cc: Date: Mon, 18 Aug 2014 12:40:06 +0800 Subject: [pci:pci/host-xilinx] a58f3d0c3b1c4a71a2418c3306fba86c26a49781 BUILD DONE git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-xilinx a58f3d0c3b1c4a71a2418c3306fba86c26a49781 PCI: xilinx: Add Xilinx PCIe Host Bridge IP driver drivers/pci/host/pci-xilinx.c:470:21: error: 'IRQF_VALID' undeclared (first use in this function) drivers/pci/host/pci-xilinx.c:742:14: error: dereferencing pointer to incomplete type drivers/pci/host/pci-xilinx.c:939:2: error: implicit declaration of function 'pci_common_init_dev' [-Werror=implicit-function-declaration] drivers/pci/host/pci-xilinx.c:417:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration] drivers/pci/host/pci-xilinx.c:938:2: error: invalid use of undefined type 'struct hw_pci' drivers/pci/host/pci-xilinx.c:888:16: error: storage size of 'hw' isn't known drivers/pci/host/pci-xilinx.c:935:3: error: unknown field 'add_bus' specified in initializer drivers/pci/host/pci-xilinx.c:934:3: error: unknown field 'map_irq' specified in initializer drivers/pci/host/pci-xilinx.c:931:3: error: unknown field 'nr_controllers' specified in initializer drivers/pci/host/pci-xilinx.c:937:3: error: unknown field 'ops' specified in initializer drivers/pci/host/pci-xilinx.c:932:3: error: unknown field 'private_data' specified in initializer drivers/pci/host/pci-xilinx.c:936:3: error: unknown field 'scan' specified in initializer drivers/pci/host/pci-xilinx.c:933:3: error: unknown field 'setup' specified in initializer drivers/pci/host/pci-xilinx.c:937:3: warning: (near initialization for '(anonymous)') drivers/pci/host/pci-xilinx.c:937:3: warning: excess elements in struct initializer drivers/pci/host/pci-xilinx.c:124:59: warning: its scope is only this definition or declaration, which is probably not what you want drivers/pci/host/pci-xilinx.c:737:34: warning: passing argument 1 of 'sys_to_pcie' from incompatible pointer type drivers/pci/host/pci-xilinx.c:735:17: warning: 'struct pci_sys_data' declared inside parameter list elapsed time: 25m configs tested: 112 pariscc3000_defconfig parisc b180_defconfig parisc defconfig alpha defconfig pariscallnoconfig i386 allnoconfig i386defconfig i386 allmodconfig i386 alldefconfig shtitan_defconfig sh
[PATCH v7] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Changes in v7:
- Removed errors reported from build-bot. The errors are
mainly due to same CONFIG_PCI_XILINX flag being used for
Zynq and Microblaze platforms. So, renamed the driver
config flag name to CONFIG_PCIE_XILINX.
- Also, renamed the driver file to pcie-xilinx.c to be in
sync with CONFIG option.
- Fixed the annotation of xilinx_pcie_scan_bus() function
to remove build-bot warnings.
Changes in v6:
- Added Ack from Arnd. Thanks Arnd.
- Rebased on 3.16-rc7.
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() - xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() - xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pcie-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pcie-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells
Re: [PATCH v2 1/2] dma: Add Xilinx Central DMA DT Binding Documentation
Hi Varka Bhadram, On Tue, Aug 5, 2014 at 5:29 PM, Varka Bhadram wrote: > On 08/05/2014 05:09 PM, Srikanth Thokala wrote: >> >> Device-tree binding documentation of Xilinx Central DMA Engine >> >> Signed-off-by: Srikanth Thokala >> --- >> Changes in v2: >> - Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description >>to match the implementation. >> >> --- >> .../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54 >> >> 1 file changed, 54 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt >> >> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt >> b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt >> new file mode 100644 >> index 000..b04f76b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt >> @@ -0,0 +1,54 @@ >> +Xilinx AXI CDMA engine, it does transfers between memory-mapped source >> +address and a memory-mapped destination address. >> + >> +Required properties: >> +- compatible: Should be "xlnx,axi-cdma-1.00.a" >> +- #dma-cells: Should be <1>, see "dmas" property below >> +- reg: Should contain cdma registers location and length. >> +- dma-channel child node: Should have only one channel >> + >> + > > > proper alignment for all the properties... > Required properties: > - compatible: Should be "xlnx,axi-cdma-1.00.a" > > - #dma-cells: Should be <1>, see "dmas" property below > - reg : Should contain cdma registers location and length. > . I would like to change, but is it documented anywhere? Because, I didn't receive any such comments on other drivers, so I am just wondering. Thanks Srikanth > > > > -- > Regards, > Varka Bhadram. > > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Michal, On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote: > Hi Bjorn, > > On 07/30/2014 01:24 PM, Srikanth Thokala wrote: >> Hi Arnd, >> >> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote: >>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: >>>> Hi Arnd and Rob, >>>> >>>> I discussed with Bjorn and we believe this patch is in good shape to >>>> apply. And Bjorn requires ACKs to apply this patch. So, could you >>>> guys please review this patch and provided your ACKs to this patch. >>> >>> Looks great for the most part. I've looked through the whole driver >>> again, and I have two small issues remaining: >>> >>> a) Please clarify in the changeset description why there is no support >>>for PCI I/O space. >> >> Sure, I will add to my changeset. >> >>> >>> b) I think you should use the 'msi-parent' property, and the >>>of_pci_find_msi_chip_by_node() to find the msi_chip for the >>>PCI controller. This will make it possible to forward MSIs >>>to the main interrupt controller in the system, which is more >>>efficient. See the pcie-mvebu driver for an example of this. >> >> Ok, I need to look into this and I will plan to implement on top of this >> patch. >> >>> >>> Other than these: >>> >>> Acked-by: Arnd Bergmann >> >> Thanks Arnd for the Ack. > > What's the status on this one? It looks like Bjorn is on vacation. I have sent v6 patch by adding Ack from Arnd, which I feel is in good shape to be applied. > > Srikanth: > Isn't pcie-xilinx.c better name if this is just pcie host bridge? Yes, it looks better. But, many other drivers which are basically drivers for PCIe host controllers has the prefix 'pci-' in the file name. So, I feel it should be fine and would be happy to change if I have to. Thanks Srikanth > > Thanks, > Michal > > -- > Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 > w: www.monstr.eu p: +42-0-721842854 > Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ > Maintainer of Linux kernel - Xilinx Zynq ARM architecture > Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform > > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Michal, On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek mon...@monstr.eu wrote: Hi Bjorn, On 07/30/2014 01:24 PM, Srikanth Thokala wrote: Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. Sure, I will add to my changeset. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. Other than these: Acked-by: Arnd Bergmann a...@arndb.de Thanks Arnd for the Ack. What's the status on this one? It looks like Bjorn is on vacation. I have sent v6 patch by adding Ack from Arnd, which I feel is in good shape to be applied. Srikanth: Isn't pcie-xilinx.c better name if this is just pcie host bridge? Yes, it looks better. But, many other drivers which are basically drivers for PCIe host controllers has the prefix 'pci-' in the file name. So, I feel it should be fine and would be happy to change if I have to. Thanks Srikanth Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 1/2] dma: Add Xilinx Central DMA DT Binding Documentation
Hi Varka Bhadram, On Tue, Aug 5, 2014 at 5:29 PM, Varka Bhadram varkabhad...@gmail.com wrote: On 08/05/2014 05:09 PM, Srikanth Thokala wrote: Device-tree binding documentation of Xilinx Central DMA Engine Signed-off-by: Srikanth Thokala stho...@xilinx.com --- Changes in v2: - Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description to match the implementation. --- .../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt new file mode 100644 index 000..b04f76b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt @@ -0,0 +1,54 @@ +Xilinx AXI CDMA engine, it does transfers between memory-mapped source +address and a memory-mapped destination address. + +Required properties: +- compatible: Should be xlnx,axi-cdma-1.00.a +- #dma-cells: Should be 1, see dmas property below +- reg: Should contain cdma registers location and length. +- dma-channel child node: Should have only one channel + + proper alignment for all the properties... Required properties: - compatible: Should be xlnx,axi-cdma-1.00.a - #dma-cells: Should be 1, see dmas property below - reg : Should contain cdma registers location and length. . I would like to change, but is it documented anywhere? Because, I didn't receive any such comments on other drivers, so I am just wondering. Thanks Srikanth -- Regards, Varka Bhadram. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support
This is the driver for the AXI Central Direct Memory Access (AXI
CDMA) core, which is a soft Xilinx IP core that provides high-bandwidth
Direct Memory Access (DMA) between a memory-mapped source address and a
memory-mapped destination address.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
---
Changes in v2:
- Rebased on 3.16-rc7.
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |1 +
drivers/dma/xilinx/xilinx_cdma.c | 998 ++
include/linux/amba/xilinx_dma.h | 15 +-
4 files changed, 1025 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma/xilinx/xilinx_cdma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8f6afbf..453bdab 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -393,6 +393,18 @@ config XILINX_VDMA
channels, Memory Mapped to Stream (MM2S) and Stream to
Memory Mapped (S2MM) for the data transfers.
+config XILINX_CDMA
+ tristate "Xilinx AXI CDMA Engine"
+ depends on (ARCH_ZYNQ || MICROBLAZE)
+ select DMA_ENGINE
+ help
+ Enable support for Xilinx AXI CDMA Soft IP.
+
+ The AXI CDMA is a soft IP which provides high-bandwidth
+ Direct Memory Access (DMA) between a memory-mapped source
+ address and a memory-mapped destination address using the
+ AXI4 protocol.
+
config DMA_ENGINE
bool
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 3c4e9f2..e1dee77 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o
+obj-$(CONFIG_XILINX_CDMA) += xilinx_cdma.o
diff --git a/drivers/dma/xilinx/xilinx_cdma.c b/drivers/dma/xilinx/xilinx_cdma.c
new file mode 100644
index 000..2ae7c77
--- /dev/null
+++ b/drivers/dma/xilinx/xilinx_cdma.c
@@ -0,0 +1,998 @@
+/*
+ * DMA driver for Xilinx Central DMA Engine
+ *
+ * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+ *
+ * Based on the Freescale DMA driver.
+ *
+ * Description:
+ * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
+ * Access (DMA) between a memory-mapped source address and a memory-mapped
+ * destination address.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../dmaengine.h"
+
+/* Register Offsets */
+#define XILINX_CDMA_CONTROL_OFFSET 0x00
+#define XILINX_CDMA_STATUS_OFFSET 0x04
+#define XILINX_CDMA_CDESC_OFFSET 0x08
+#define XILINX_CDMA_TDESC_OFFSET 0x10
+#define XILINX_CDMA_SRCADDR_OFFSET 0x18
+#define XILINX_CDMA_DSTADDR_OFFSET 0x20
+#define XILINX_CDMA_BTT_OFFSET 0x28
+
+/* General register bits definitions */
+#define XILINX_CDMA_CR_RESET BIT(2)
+#define XILINX_CDMA_CR_SGMODE BIT(3)
+
+#define XILINX_CDMA_SR_IDLEBIT(1)
+
+#define XILINX_CDMA_XR_IRQ_IOC_MASKBIT(12)
+#define XILINX_CDMA_XR_IRQ_DELAY_MASK BIT(13)
+#define XILINX_CDMA_XR_IRQ_ERROR_MASK BIT(14)
+#define XILINX_CDMA_XR_IRQ_ALL_MASKGENMASK(14, 12)
+
+#define XILINX_CDMA_XR_DELAY_MASK GENMASK(31, 24)
+#define XILINX_CDMA_XR_COALESCE_MASK GENMASK(23, 16)
+
+#define XILINX_CDMA_DELAY_MAX GENMASK(7, 0)
+#define XILINX_CDMA_DELAY_SHIFT24
+
+#define XILINX_CDMA_COALESCE_MAX GENMASK(7, 0)
+#define XILINX_CDMA_COALESCE_SHIFT 16
+
+/* Delay loop counter to prevent hardware failure */
+#define XILINX_CDMA_RESET_LOOP 100
+
+/* Maximum transfer length */
+#define XILINX_CDMA_MAX_TRANS_LEN GENMASK(22, 0)
+
+/**
+ * struct xilinx_cdma_desc_hw - Hardware Descriptor
+ * @next_desc: Next Descriptor Pointer @0x00
+ * @pad1: Reserved @0x04
+ * @src_addr: Source address @0x08
+ * @pad2: Reserved @0x0C
+ * @dest_addr: Destination address @0x10
+ * @pad3: Reserved @0x14
+ * @control: Control field @0x18
+ * @status: Status field @0x1C
+ */
+struct xilinx_cdma_desc_hw {
+ u32 next_desc;
+ u32 pad1;
+ u32 src_addr;
+ u32 pad2;
+ u32 dest_addr;
+ u32 pad3;
+ u32 control;
+ u32 status;
+} __aligned(64);
+
+/**
+ * struct xilinx_cdma_tx_segment - Descriptor segment
+ * @hw: Hardware descriptor
+ * @node: Node in the descriptor segments list
+ * @phys: Physical address of segment
+ */
+struct xilinx_cdma_tx_segment {
+ struct xilinx_cdma_desc_hw hw;
+ struct list_head node;
+ dma_addr_t phys;
+} __aligned(64);
+
+/**
+ * struct xilinx_cdma_tx_descriptor - Per Transaction structure
+ * @async_tx: Async transaction descriptor
+ * @segmen
[PATCH v2 1/2] dma: Add Xilinx Central DMA DT Binding Documentation
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v2:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
new file mode 100644
index 000..b04f76b
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
@@ -0,0 +1,54 @@
+Xilinx AXI CDMA engine, it does transfers between memory-mapped source
+address and a memory-mapped destination address.
+
+Required properties:
+- compatible: Should be "xlnx,axi-cdma-1.00.a"
+- #dma-cells: Should be <1>, see "dmas" property below
+- reg: Should contain cdma registers location and length.
+- dma-channel child node: Should have only one channel
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+ the hardware.
+
+Required child node properties:
+- compatible: It should be "xlnx,axi-cdma-channel".
+- interrupts: Should contain per channel CDMA interrupts.
+- xlnx,datawidth: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+ Realignment Engine.
+
+Example:
+
+
+axi_cdma_0: axicdma@7e20 {
+ compatible = "xlnx,axi-cdma-1.00.a";
+ #dma_cells = <1>;
+ reg = < 0x7e20 0x1 >;
+ dma-channel@7e20 {
+ compatible = "xlnx,axi-cdma-channel";
+ interrupts = < 0 55 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of <[Central DMA device phandle] [Channel ID]> pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per "dmas" entry
+
+Example:
+
+
+cdmatest_0: cdmatest@0 {
+ compatible ="xlnx,axi-cdma-test-1.00.a";
+ dmas = <_cdma_0 0>;
+ dma-names = "cdma0";
+} ;
--
1.7.9.5
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[PATCH v6] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
Acked-by: Arnd Bergmann
---
NOTE: The AXI PCIe IP doesn't support I/O space, so this
driver has no support for I/O space.
Changes in v6:
- Added Ack from Arnd. Thanks Arnd.
- Rebased on 3.16-rc7.
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() -> xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() -> xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
"PCI: ARM: add support for generic PCI host controller"
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be "pci"
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ reg = < 0x5000 0x1000 >;
+ device_type = "pc
[PATCH v6] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
NOTE: The AXI PCIe IP doesn't support I/O space, so this
driver has no support for I/O space.
Changes in v6:
- Added Ack from Arnd. Thanks Arnd.
- Rebased on 3.16-rc7.
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() - xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() - xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = 3;
+ #size-cells = 2;
+ #interrupt-cells = 1;
+ compatible = xlnx,axi-pcie-host-1.00.a;
+ reg = 0x5000 0x1000 ;
+ device_type = pci;
+ interrupts = 0 52 4 ;
+ interrupt-map-mask = 0 0 0 7
[PATCH v2 1/2] dma: Add Xilinx Central DMA DT Binding Documentation
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v2:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
new file mode 100644
index 000..b04f76b
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
@@ -0,0 +1,54 @@
+Xilinx AXI CDMA engine, it does transfers between memory-mapped source
+address and a memory-mapped destination address.
+
+Required properties:
+- compatible: Should be xlnx,axi-cdma-1.00.a
+- #dma-cells: Should be 1, see dmas property below
+- reg: Should contain cdma registers location and length.
+- dma-channel child node: Should have only one channel
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+ the hardware.
+
+Required child node properties:
+- compatible: It should be xlnx,axi-cdma-channel.
+- interrupts: Should contain per channel CDMA interrupts.
+- xlnx,datawidth: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+ Realignment Engine.
+
+Example:
+
+
+axi_cdma_0: axicdma@7e20 {
+ compatible = xlnx,axi-cdma-1.00.a;
+ #dma_cells = 1;
+ reg = 0x7e20 0x1 ;
+ dma-channel@7e20 {
+ compatible = xlnx,axi-cdma-channel;
+ interrupts = 0 55 4 ;
+ xlnx,datawidth = 0x40;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of [Central DMA device phandle] [Channel ID] pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per dmas entry
+
+Example:
+
+
+cdmatest_0: cdmatest@0 {
+ compatible =xlnx,axi-cdma-test-1.00.a;
+ dmas = axi_cdma_0 0;
+ dma-names = cdma0;
+} ;
--
1.7.9.5
--
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[PATCH v2 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support
This is the driver for the AXI Central Direct Memory Access (AXI
CDMA) core, which is a soft Xilinx IP core that provides high-bandwidth
Direct Memory Access (DMA) between a memory-mapped source address and a
memory-mapped destination address.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v2:
- Rebased on 3.16-rc7.
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |1 +
drivers/dma/xilinx/xilinx_cdma.c | 998 ++
include/linux/amba/xilinx_dma.h | 15 +-
4 files changed, 1025 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma/xilinx/xilinx_cdma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8f6afbf..453bdab 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -393,6 +393,18 @@ config XILINX_VDMA
channels, Memory Mapped to Stream (MM2S) and Stream to
Memory Mapped (S2MM) for the data transfers.
+config XILINX_CDMA
+ tristate Xilinx AXI CDMA Engine
+ depends on (ARCH_ZYNQ || MICROBLAZE)
+ select DMA_ENGINE
+ help
+ Enable support for Xilinx AXI CDMA Soft IP.
+
+ The AXI CDMA is a soft IP which provides high-bandwidth
+ Direct Memory Access (DMA) between a memory-mapped source
+ address and a memory-mapped destination address using the
+ AXI4 protocol.
+
config DMA_ENGINE
bool
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 3c4e9f2..e1dee77 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o
+obj-$(CONFIG_XILINX_CDMA) += xilinx_cdma.o
diff --git a/drivers/dma/xilinx/xilinx_cdma.c b/drivers/dma/xilinx/xilinx_cdma.c
new file mode 100644
index 000..2ae7c77
--- /dev/null
+++ b/drivers/dma/xilinx/xilinx_cdma.c
@@ -0,0 +1,998 @@
+/*
+ * DMA driver for Xilinx Central DMA Engine
+ *
+ * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+ *
+ * Based on the Freescale DMA driver.
+ *
+ * Description:
+ * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
+ * Access (DMA) between a memory-mapped source address and a memory-mapped
+ * destination address.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/amba/xilinx_dma.h
+#include linux/bitops.h
+#include linux/dmapool.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of_address.h
+#include linux/of_dma.h
+#include linux/of_irq.h
+#include linux/of_platform.h
+#include linux/slab.h
+
+#include ../dmaengine.h
+
+/* Register Offsets */
+#define XILINX_CDMA_CONTROL_OFFSET 0x00
+#define XILINX_CDMA_STATUS_OFFSET 0x04
+#define XILINX_CDMA_CDESC_OFFSET 0x08
+#define XILINX_CDMA_TDESC_OFFSET 0x10
+#define XILINX_CDMA_SRCADDR_OFFSET 0x18
+#define XILINX_CDMA_DSTADDR_OFFSET 0x20
+#define XILINX_CDMA_BTT_OFFSET 0x28
+
+/* General register bits definitions */
+#define XILINX_CDMA_CR_RESET BIT(2)
+#define XILINX_CDMA_CR_SGMODE BIT(3)
+
+#define XILINX_CDMA_SR_IDLEBIT(1)
+
+#define XILINX_CDMA_XR_IRQ_IOC_MASKBIT(12)
+#define XILINX_CDMA_XR_IRQ_DELAY_MASK BIT(13)
+#define XILINX_CDMA_XR_IRQ_ERROR_MASK BIT(14)
+#define XILINX_CDMA_XR_IRQ_ALL_MASKGENMASK(14, 12)
+
+#define XILINX_CDMA_XR_DELAY_MASK GENMASK(31, 24)
+#define XILINX_CDMA_XR_COALESCE_MASK GENMASK(23, 16)
+
+#define XILINX_CDMA_DELAY_MAX GENMASK(7, 0)
+#define XILINX_CDMA_DELAY_SHIFT24
+
+#define XILINX_CDMA_COALESCE_MAX GENMASK(7, 0)
+#define XILINX_CDMA_COALESCE_SHIFT 16
+
+/* Delay loop counter to prevent hardware failure */
+#define XILINX_CDMA_RESET_LOOP 100
+
+/* Maximum transfer length */
+#define XILINX_CDMA_MAX_TRANS_LEN GENMASK(22, 0)
+
+/**
+ * struct xilinx_cdma_desc_hw - Hardware Descriptor
+ * @next_desc: Next Descriptor Pointer @0x00
+ * @pad1: Reserved @0x04
+ * @src_addr: Source address @0x08
+ * @pad2: Reserved @0x0C
+ * @dest_addr: Destination address @0x10
+ * @pad3: Reserved @0x14
+ * @control: Control field @0x18
+ * @status: Status field @0x1C
+ */
+struct xilinx_cdma_desc_hw {
+ u32 next_desc;
+ u32 pad1;
+ u32 src_addr;
+ u32 pad2;
+ u32 dest_addr;
+ u32 pad3;
+ u32 control;
+ u32 status;
+} __aligned(64);
+
+/**
+ * struct xilinx_cdma_tx_segment - Descriptor segment
+ * @hw: Hardware descriptor
+ * @node: Node in the descriptor segments list
+ * @phys: Physical address of segment
+ */
+struct xilinx_cdma_tx_segment {
+ struct xilinx_cdma_desc_hw hw;
+ struct list_head node
Re: [PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi, Kindly review this patch and please provide your inputs. Thanks Srikanth On Mon, Jul 28, 2014 at 5:47 PM, Srikanth Thokala wrote: > This is the driver for the AXI Direct Memory Access (AXI DMA) > core, which is a soft Xilinx IP core that provides high- > bandwidth direct memory access between memory and AXI4-Stream > type target peripherals. > > This module works on Zynq (ARM Based SoC) and Microblaze platforms. > > Signed-off-by: Srikanth Thokala > --- > Changes in v3: > - Rebased on 3.16-rc7 > > Changes in v2: > - Simplified the logic to set SOP and APP words in prep_slave_sg(). > - Corrected function description comments to match the return type. > - Fixed some minor comments as suggested by Andy, Thanks. > --- > drivers/dma/Kconfig | 13 + > drivers/dma/xilinx/Makefile |1 + > drivers/dma/xilinx/xilinx_dma.c | 1225 > +++ > include/linux/amba/xilinx_dma.h | 17 + > 4 files changed, 1256 insertions(+) > create mode 100644 drivers/dma/xilinx/xilinx_dma.c > > diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig > index 1eca7b9..b8e831e 100644 > --- a/drivers/dma/Kconfig > +++ b/drivers/dma/Kconfig > @@ -375,6 +375,19 @@ config XILINX_VDMA > channels, Memory Mapped to Stream (MM2S) and Stream to > Memory Mapped (S2MM) for the data transfers. > > +config XILINX_DMA > + tristate "Xilinx AXI DMA Engine" > + depends on (ARCH_ZYNQ || MICROBLAZE) > + select DMA_ENGINE > + help > + Enable support for Xilinx AXI DMA Soft IP. > + > + This engine provides high-bandwidth direct memory access > + between memory and AXI4-Stream type target peripherals. > + It has two stream interfaces/channels, Memory Mapped to > + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the > + data transfers. > + > config DMA_ENGINE > bool > > diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile > index 3c4e9f2..6224a49 100644 > --- a/drivers/dma/xilinx/Makefile > +++ b/drivers/dma/xilinx/Makefile > @@ -1 +1,2 @@ > obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o > +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > new file mode 100644 > index 000..0500773 > --- /dev/null > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -0,0 +1,1225 @@ > +/* > + * DMA driver for Xilinx DMA Engine > + * > + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. > + * > + * Based on the Freescale DMA driver. > + * > + * Description: > + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory > + * Access between memory and AXI4-Stream-type target peripherals. It can be > + * configured to have one channel or two channels and if configured as two > + * channels, one is to transmit data from memory to a device and another is > + * to receive from a device. > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "../dmaengine.h" > + > +/* Register Offsets */ > +#define XILINX_DMA_REG_CONTROL 0x00 > +#define XILINX_DMA_REG_STATUS 0x04 > +#define XILINX_DMA_REG_CURDESC 0x08 > +#define XILINX_DMA_REG_TAILDESC0x10 > +#define XILINX_DMA_REG_SRCADDR 0x18 > +#define XILINX_DMA_REG_DSTADDR 0x20 > +#define XILINX_DMA_REG_BTT 0x28 > + > +/* Channel/Descriptor Offsets */ > +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 > +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 > + > +/* General register bits definitions */ > +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) > +#define XILINX_DMA_CR_RESET_MASK BIT(2) > + > +#define XILINX_DMA_CR_DELAY_SHIFT 24 > +#define XILINX_DMA_CR_COALESCE_SHIFT 16 > + > +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) > +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) > + > +#define XILINX_DMA_SR_HALTED_MASK BIT(0) > +#define XILINX_DMA_SR_IDLE_MASKBIT(1) > + > +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) > +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) > +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) > +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) > +
Re: [PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi, Kindly review this patch and please provide your inputs. Thanks Srikanth On Mon, Jul 28, 2014 at 5:47 PM, Srikanth Thokala stho...@xilinx.com wrote: This is the driver for the AXI Direct Memory Access (AXI DMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type target peripherals. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala stho...@xilinx.com --- Changes in v3: - Rebased on 3.16-rc7 Changes in v2: - Simplified the logic to set SOP and APP words in prep_slave_sg(). - Corrected function description comments to match the return type. - Fixed some minor comments as suggested by Andy, Thanks. --- drivers/dma/Kconfig | 13 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_dma.c | 1225 +++ include/linux/amba/xilinx_dma.h | 17 + 4 files changed, 1256 insertions(+) create mode 100644 drivers/dma/xilinx/xilinx_dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1eca7b9..b8e831e 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -375,6 +375,19 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_DMA + tristate Xilinx AXI DMA Engine + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI DMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream type target peripherals. + It has two stream interfaces/channels, Memory Mapped to + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the + data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..6224a49 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c new file mode 100644 index 000..0500773 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -0,0 +1,1225 @@ +/* + * DMA driver for Xilinx DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access between memory and AXI4-Stream-type target peripherals. It can be + * configured to have one channel or two channels and if configured as two + * channels, one is to transmit data from memory to a device and another is + * to receive from a device. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include linux/amba/xilinx_dma.h +#include linux/bitops.h +#include linux/init.h +#include linux/interrupt.h +#include linux/io.h +#include linux/module.h +#include linux/of_address.h +#include linux/of_dma.h +#include linux/of_irq.h +#include linux/of_platform.h +#include linux/slab.h + +#include ../dmaengine.h + +/* Register Offsets */ +#define XILINX_DMA_REG_CONTROL 0x00 +#define XILINX_DMA_REG_STATUS 0x04 +#define XILINX_DMA_REG_CURDESC 0x08 +#define XILINX_DMA_REG_TAILDESC0x10 +#define XILINX_DMA_REG_SRCADDR 0x18 +#define XILINX_DMA_REG_DSTADDR 0x20 +#define XILINX_DMA_REG_BTT 0x28 + +/* Channel/Descriptor Offsets */ +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 + +/* General register bits definitions */ +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_DMA_CR_RESET_MASK BIT(2) + +#define XILINX_DMA_CR_DELAY_SHIFT 24 +#define XILINX_DMA_CR_COALESCE_SHIFT 16 + +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) + +#define XILINX_DMA_SR_HALTED_MASK BIT(0) +#define XILINX_DMA_SR_IDLE_MASKBIT(1) + +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) + +/* BD definitions */ +#define XILINX_DMA_BD_STS_ALL_MASK GENMASK(31, 28) +#define XILINX_DMA_BD_SOP BIT(27) +#define XILINX_DMA_BD_EOP BIT(26) + +/* Hw specific definitions */ +#define XILINX_DMA_MAX_CHANS_PER_DEVICE0x2 +#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) + +/* Delay
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote: > On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: >> Hi Arnd and Rob, >> >> I discussed with Bjorn and we believe this patch is in good shape to >> apply. And Bjorn requires ACKs to apply this patch. So, could you >> guys please review this patch and provided your ACKs to this patch. > > Looks great for the most part. I've looked through the whole driver > again, and I have two small issues remaining: > > a) Please clarify in the changeset description why there is no support >for PCI I/O space. Sure, I will add to my changeset. > > b) I think you should use the 'msi-parent' property, and the >of_pci_find_msi_chip_by_node() to find the msi_chip for the >PCI controller. This will make it possible to forward MSIs >to the main interrupt controller in the system, which is more >efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. > > Other than these: > > Acked-by: Arnd Bergmann Thanks Arnd for the Ack. Srikanth > > Arnd > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Arnd, On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote: Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Looks great for the most part. I've looked through the whole driver again, and I have two small issues remaining: a) Please clarify in the changeset description why there is no support for PCI I/O space. Sure, I will add to my changeset. b) I think you should use the 'msi-parent' property, and the of_pci_find_msi_chip_by_node() to find the msi_chip for the PCI controller. This will make it possible to forward MSIs to the main interrupt controller in the system, which is more efficient. See the pcie-mvebu driver for an example of this. Ok, I need to look into this and I will plan to implement on top of this patch. Other than these: Acked-by: Arnd Bergmann a...@arndb.de Thanks Arnd for the Ack. Srikanth Arnd -- To unsubscribe from this list: send the line unsubscribe linux-pci in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 1/2] dma: Add Xilinx AXI DMA DT Binding Documentation
On Mon, Jul 28, 2014 at 5:58 PM, Arnd Bergmann wrote: > On Monday 28 July 2014 17:47:48 Srikanth Thokala wrote: >> Device-tree binding documentation of Xilinx DMA Engine >> >> Signed-off-by: Srikanth Thokala > > Looks ok to me, > > Acked-by: Arnd Bergmann Thanks Arnd. Srikanth > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Arnd and Rob, I discussed with Bjorn and we believe this patch is in good shape to apply. And Bjorn requires ACKs to apply this patch. So, could you guys please review this patch and provided your ACKs to this patch. Thanks Srikanth On Wed, Jul 23, 2014 at 9:33 PM, Srikanth Thokala wrote: > This is the driver for Xilinx AXI PCIe Host Bridge Soft IP > > Signed-off-by: Srikanth Thokala > --- > Changes in v5: > - Removed unnecessary checking of port structure. > - Changed the return type of verify_config from int to bool. > - Renamed following functions, > xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up() > xilinx_pcie_verify_config() -> xilinx_pcie_valid_device() > xilinx_pcie_get_config_base() -> xilinx_pcie_config_base() > - Removed link_up bool flag from port structure, as it is not > being used. > - Removed unused constants. > - Rebased on 3.16-rc6. > - Fixed some minor comments. > - Thanks Bjorn for the review. > > Changes in v4: > - Regarding the comments to separate ECAM functionality, > I have sent a separate patch and it is decided to implement > it later. The patch is here, > https://lkml.org/lkml/2014/5/18/54 > - Fixed issue with adding configuration bus resource. > - Moved the logic for setting up bus resources to probe() from > pcie_setup(). > - Instead of mapping all the MSI interrupts in the probe, changed > to map only when a MSI is requested. > - Earlier, the implementation of legacy and MSI interrupts init- > is mutually exclusive, now changed to have the legacy interrupts > init always and MSI interrupt init based on CONFIG_PCI_MSI flag. > - Regarding the MSI generic implementation comment, I will plan to > do on top of this driver patch. > - Rebased on 3.16-rc2. > - Fixed other minor comments. > - Thanks Arnd and Bjorn for the review. > > Changes in v3: > - Rebased on v3.15.0-rc1 > - Added support for interrupt-map DT functionality. > - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). > - Modified resource mapping logic as per the series > "PCI: ARM: add support for generic PCI host controller" > - Modified devicetree binding documentation to update with interrupt- > map properties. > - Use devm calls wherever applicable. > - Fixed minor comments from Jason > - Thanks Jason for the review and suggestions. > > Changes in v2: > - Rebased on v3.14.0-rc8 > - Removed IP specific DT properties like include-rc, axibar-num etc., > as suggested by Jason and Bjorn, Thanks > --- > .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ > drivers/pci/host/Kconfig |7 + > drivers/pci/host/Makefile |1 + > drivers/pci/host/pci-xilinx.c | 978 > > 4 files changed, 1048 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt > create mode 100644 drivers/pci/host/pci-xilinx.c > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > new file mode 100644 > index 000..3e2c88d > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt > @@ -0,0 +1,62 @@ > +* Xilinx AXI PCIe Root Port Bridge DT description > + > +Required properties: > +- #address-cells: Address representation for root ports, set to <3> > +- #size-cells: Size representation for root ports, set to <2> > +- #interrupt-cells: specifies the number of cells needed to encode an > + interrupt source. The value must be 1. > +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" > +- reg: Should contain AXI PCIe registers location and length > +- device_type: must be "pci" > +- interrupts: Should contain AXI PCIe interrupt > +- interrupt-map-mask, > + interrupt-map: standard PCI properties to define the mapping of the > + PCI interface to interrupt numbers. > +- ranges: ranges for the PCI memory regions (I/O space region is not > + supported by hardware) > + Please refer to the standard PCI bus binding document for a more > + detailed explanation > + > +Optional properties: > +- bus-range: PCI bus numbers covered > + > +Interrupt controller child node > > +Required properties: > +- interrupt-controller: identifies the node as an interrupt controller > +- #address-cells: specifies the number of cells needed to encode an > + address. The value must be 0. > +- #interrupt-cells: specifies the number of cells needed to encode an > + interrupt source. The value must be 1. > + > +NOTE: > +The core provides a single interrupt
[PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
This is the driver for the AXI Direct Memory Access (AXI DMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type target peripherals. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala --- Changes in v3: - Rebased on 3.16-rc7 Changes in v2: - Simplified the logic to set SOP and APP words in prep_slave_sg(). - Corrected function description comments to match the return type. - Fixed some minor comments as suggested by Andy, Thanks. --- drivers/dma/Kconfig | 13 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_dma.c | 1225 +++ include/linux/amba/xilinx_dma.h | 17 + 4 files changed, 1256 insertions(+) create mode 100644 drivers/dma/xilinx/xilinx_dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1eca7b9..b8e831e 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -375,6 +375,19 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_DMA + tristate "Xilinx AXI DMA Engine" + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI DMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream type target peripherals. + It has two stream interfaces/channels, Memory Mapped to + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the + data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..6224a49 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c new file mode 100644 index 000..0500773 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -0,0 +1,1225 @@ +/* + * DMA driver for Xilinx DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access between memory and AXI4-Stream-type target peripherals. It can be + * configured to have one channel or two channels and if configured as two + * channels, one is to transmit data from memory to a device and another is + * to receive from a device. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../dmaengine.h" + +/* Register Offsets */ +#define XILINX_DMA_REG_CONTROL 0x00 +#define XILINX_DMA_REG_STATUS 0x04 +#define XILINX_DMA_REG_CURDESC 0x08 +#define XILINX_DMA_REG_TAILDESC0x10 +#define XILINX_DMA_REG_SRCADDR 0x18 +#define XILINX_DMA_REG_DSTADDR 0x20 +#define XILINX_DMA_REG_BTT 0x28 + +/* Channel/Descriptor Offsets */ +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 + +/* General register bits definitions */ +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_DMA_CR_RESET_MASK BIT(2) + +#define XILINX_DMA_CR_DELAY_SHIFT 24 +#define XILINX_DMA_CR_COALESCE_SHIFT 16 + +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) + +#define XILINX_DMA_SR_HALTED_MASK BIT(0) +#define XILINX_DMA_SR_IDLE_MASKBIT(1) + +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) + +/* BD definitions */ +#define XILINX_DMA_BD_STS_ALL_MASK GENMASK(31, 28) +#define XILINX_DMA_BD_SOP BIT(27) +#define XILINX_DMA_BD_EOP BIT(26) + +/* Hw specific definitions */ +#define XILINX_DMA_MAX_CHANS_PER_DEVICE0x2 +#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) + +/* Delay loop counter to prevent hardware failure */ +#define XILINX_DMA_LOOP_COUNT 100 + +/* Maximum number of Descriptors */ +#define XILINX_DMA_NUM_DESCS 64 + +/** + * struct xilinx_dma_desc_hw - Hardware Descriptor + * @next_desc: Next Descriptor Pointer @0x00 + * @pad1: Reserved @0x04 + * @buf_addr: Buffer address @0x08 + * @pad2: Reserved @0x0C + * @pad3: Reserved @0x10 + * @pad4: Reserved @0x14 + * @control: Control fie
[PATCH v3 1/2] dma: Add Xilinx AXI DMA DT Binding Documentation
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v3:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
new file mode 100644
index 000..18e8bcc
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -0,0 +1,65 @@
+Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
+target devices. It can be configured to have one channel or two channels.
+If configured as two channels, one is to transmit to the device and another
+is to receive from the device.
+
+Required properties:
+- compatible: Should be "xlnx,axi-dma-1.00.a"
+- #dma-cells: Should be <1>, see "dmas" property below
+- reg: Should contain DMA registers location and length.
+- dma-channel child node: Should have atleast one channel and can have upto
+ two channels per device. This node specifies the properties of each
+ DMA channel (see child node properties below).
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+ the hardware.
+
+Required child node properties:
+- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
+ "xlnx,axi-dma-s2mm-channel".
+- interrupts: Should contain per channel DMA interrupts.
+- xlnx,datawidth: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+ Realignment Engine.
+
+Example:
+
+
+axi_dma_0: axidma@4040 {
+ compatible = "xlnx,axi-dma-1.00.a";
+ #dma_cells = <1>;
+ reg = < 0x4040 0x1 >;
+ dma-channel@4040 {
+ compatible = "xlnx,axi-dma-mm2s-channel";
+ interrupts = < 0 59 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+ dma-channel@40400030 {
+ compatible = "xlnx,axi-dma-s2mm-channel";
+ interrupts = < 0 58 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per "dmas" entry
+
+Example:
+
+
+dmatest_0: dmatest@0 {
+ compatible ="xlnx,axi-dma-test-1.00.a";
+ dmas = <_dma_0 0
+ _dma_0 1>;
+ dma-names = "dma0", "dma1";
+} ;
--
1.7.9.5
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[PATCH v3 1/2] dma: Add Xilinx AXI DMA DT Binding Documentation
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v3:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
new file mode 100644
index 000..18e8bcc
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -0,0 +1,65 @@
+Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
+target devices. It can be configured to have one channel or two channels.
+If configured as two channels, one is to transmit to the device and another
+is to receive from the device.
+
+Required properties:
+- compatible: Should be xlnx,axi-dma-1.00.a
+- #dma-cells: Should be 1, see dmas property below
+- reg: Should contain DMA registers location and length.
+- dma-channel child node: Should have atleast one channel and can have upto
+ two channels per device. This node specifies the properties of each
+ DMA channel (see child node properties below).
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+ the hardware.
+
+Required child node properties:
+- compatible: It should be either xlnx,axi-dma-mm2s-channel or
+ xlnx,axi-dma-s2mm-channel.
+- interrupts: Should contain per channel DMA interrupts.
+- xlnx,datawidth: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+ Realignment Engine.
+
+Example:
+
+
+axi_dma_0: axidma@4040 {
+ compatible = xlnx,axi-dma-1.00.a;
+ #dma_cells = 1;
+ reg = 0x4040 0x1 ;
+ dma-channel@4040 {
+ compatible = xlnx,axi-dma-mm2s-channel;
+ interrupts = 0 59 4 ;
+ xlnx,datawidth = 0x40;
+ } ;
+ dma-channel@40400030 {
+ compatible = xlnx,axi-dma-s2mm-channel;
+ interrupts = 0 58 4 ;
+ xlnx,datawidth = 0x40;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of [DMA device phandle] [Channel ID] pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per dmas entry
+
+Example:
+
+
+dmatest_0: dmatest@0 {
+ compatible =xlnx,axi-dma-test-1.00.a;
+ dmas = axi_dma_0 0
+ axi_dma_0 1;
+ dma-names = dma0, dma1;
+} ;
--
1.7.9.5
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[PATCH v3 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
This is the driver for the AXI Direct Memory Access (AXI DMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type target peripherals. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala stho...@xilinx.com --- Changes in v3: - Rebased on 3.16-rc7 Changes in v2: - Simplified the logic to set SOP and APP words in prep_slave_sg(). - Corrected function description comments to match the return type. - Fixed some minor comments as suggested by Andy, Thanks. --- drivers/dma/Kconfig | 13 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_dma.c | 1225 +++ include/linux/amba/xilinx_dma.h | 17 + 4 files changed, 1256 insertions(+) create mode 100644 drivers/dma/xilinx/xilinx_dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1eca7b9..b8e831e 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -375,6 +375,19 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_DMA + tristate Xilinx AXI DMA Engine + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI DMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream type target peripherals. + It has two stream interfaces/channels, Memory Mapped to + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the + data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..6224a49 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c new file mode 100644 index 000..0500773 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -0,0 +1,1225 @@ +/* + * DMA driver for Xilinx DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access between memory and AXI4-Stream-type target peripherals. It can be + * configured to have one channel or two channels and if configured as two + * channels, one is to transmit data from memory to a device and another is + * to receive from a device. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include linux/amba/xilinx_dma.h +#include linux/bitops.h +#include linux/init.h +#include linux/interrupt.h +#include linux/io.h +#include linux/module.h +#include linux/of_address.h +#include linux/of_dma.h +#include linux/of_irq.h +#include linux/of_platform.h +#include linux/slab.h + +#include ../dmaengine.h + +/* Register Offsets */ +#define XILINX_DMA_REG_CONTROL 0x00 +#define XILINX_DMA_REG_STATUS 0x04 +#define XILINX_DMA_REG_CURDESC 0x08 +#define XILINX_DMA_REG_TAILDESC0x10 +#define XILINX_DMA_REG_SRCADDR 0x18 +#define XILINX_DMA_REG_DSTADDR 0x20 +#define XILINX_DMA_REG_BTT 0x28 + +/* Channel/Descriptor Offsets */ +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 + +/* General register bits definitions */ +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_DMA_CR_RESET_MASK BIT(2) + +#define XILINX_DMA_CR_DELAY_SHIFT 24 +#define XILINX_DMA_CR_COALESCE_SHIFT 16 + +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) + +#define XILINX_DMA_SR_HALTED_MASK BIT(0) +#define XILINX_DMA_SR_IDLE_MASKBIT(1) + +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) + +/* BD definitions */ +#define XILINX_DMA_BD_STS_ALL_MASK GENMASK(31, 28) +#define XILINX_DMA_BD_SOP BIT(27) +#define XILINX_DMA_BD_EOP BIT(26) + +/* Hw specific definitions */ +#define XILINX_DMA_MAX_CHANS_PER_DEVICE0x2 +#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) + +/* Delay loop counter to prevent hardware failure */ +#define XILINX_DMA_LOOP_COUNT 100 + +/* Maximum number of Descriptors */ +#define XILINX_DMA_NUM_DESCS 64 + +/** + * struct xilinx_dma_desc_hw - Hardware Descriptor + * @next_desc: Next Descriptor Pointer @0x00
Re: [PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Arnd and Rob,
I discussed with Bjorn and we believe this patch is in good shape to
apply. And Bjorn requires ACKs to apply this patch. So, could you
guys please review this patch and provided your ACKs to this patch.
Thanks
Srikanth
On Wed, Jul 23, 2014 at 9:33 PM, Srikanth Thokala stho...@xilinx.com wrote:
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() - xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() - xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = 3;
+ #size-cells = 2;
+ #interrupt-cells = 1
Re: [PATCH v3 1/2] dma: Add Xilinx AXI DMA DT Binding Documentation
On Mon, Jul 28, 2014 at 5:58 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 28 July 2014 17:47:48 Srikanth Thokala wrote: Device-tree binding documentation of Xilinx DMA Engine Signed-off-by: Srikanth Thokala stho...@xilinx.com Looks ok to me, Acked-by: Arnd Bergmann a...@arndb.de Thanks Arnd. Srikanth -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA specification
Hi Andreas,
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Friday, July 25, 2014 3:10 PM
> To: Andreas Färber; mon...@monstr.eu; Srikanth Thokala
> Cc: Vinod Koul; Michal Simek; Andreas Olofsson; Matteo Vit; Sean Rickerd;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell;
> Kumar Gala
> Subject: Re: [PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA
> specification
>
> Hi Andreas,
>
> On 07/25/2014 10:46 AM, Andreas Färber wrote:
> > Hi Michal,
> >
> > Am 25.07.2014 09:49, schrieb Michal Simek:
> >> On 07/25/2014 01:00 AM, Andreas Färber wrote:
> >>> The specification requires xlnx,data-width, but example and driver
> >>> use xlnx,datawidth. Change the specification to match the implementation.
> >>>
> >>> Signed-off-by: Andreas Färber
> >>> ---
> >>> v2: New
> >>>
> >>> Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 2 +-
> >>> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> >>> b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> >>> index 1405ed0..e4c4d47 100644
> >>> --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> >>> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> >>> @@ -25,7 +25,7 @@ Required child node properties:
> >>> - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
> >>> "xlnx,axi-vdma-s2mm-channel".
> >>> - interrupts: Should contain per channel VDMA interrupts.
> >>> -- xlnx,data-width: Should contain the stream data width, take
> >>> values
> >>> +- xlnx,datawidth: Should contain the stream data width, take values
> >>> {32,64...1024}.
> >
> > BTW I just notice that this values specification is ambiguous as to
> > whether 96 is a valid value or only powers of 2 like 128. Maybe you
> > want to clarify that in a follow-up patch?
>
> really appreciate your help for improving this.
> Srikanth T: Can you please look at it?
It should be only power of 2. I could send a patch, but it is design-specific
and
the design will not allow to take the intermediate values and so the device-tree
script. So, I feel it should be fine to keep this way.
Thanks for this patch.
Srikanth
>
> Thanks,
> Michal
>
>
This email and any attachments are intended for the sole use of the named
recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
recipient, do not read, copy, or forward this email message or any attachments.
Delete this email message and any attachments immediately.
RE: [PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA specification
Hi Andreas,
-Original Message-
From: Michal Simek [mailto:michal.si...@xilinx.com]
Sent: Friday, July 25, 2014 3:10 PM
To: Andreas Färber; mon...@monstr.eu; Srikanth Thokala
Cc: Vinod Koul; Michal Simek; Andreas Olofsson; Matteo Vit; Sean Rickerd;
devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
ker...@vger.kernel.org; Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell;
Kumar Gala
Subject: Re: [PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA
specification
Hi Andreas,
On 07/25/2014 10:46 AM, Andreas Färber wrote:
Hi Michal,
Am 25.07.2014 09:49, schrieb Michal Simek:
On 07/25/2014 01:00 AM, Andreas Färber wrote:
The specification requires xlnx,data-width, but example and driver
use xlnx,datawidth. Change the specification to match the implementation.
Signed-off-by: Andreas Färber afaer...@suse.de
---
v2: New
Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
index 1405ed0..e4c4d47 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
@@ -25,7 +25,7 @@ Required child node properties:
- compatible: It should be either xlnx,axi-vdma-mm2s-channel or
xlnx,axi-vdma-s2mm-channel.
- interrupts: Should contain per channel VDMA interrupts.
-- xlnx,data-width: Should contain the stream data width, take
values
+- xlnx,datawidth: Should contain the stream data width, take values
{32,64...1024}.
BTW I just notice that this values specification is ambiguous as to
whether 96 is a valid value or only powers of 2 like 128. Maybe you
want to clarify that in a follow-up patch?
really appreciate your help for improving this.
Srikanth T: Can you please look at it?
It should be only power of 2. I could send a patch, but it is design-specific
and
the design will not allow to take the intermediate values and so the device-tree
script. So, I feel it should be fine to keep this way.
Thanks for this patch.
Srikanth
Thanks,
Michal
This email and any attachments are intended for the sole use of the named
recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
recipient, do not read, copy, or forward this email message or any attachments.
Delete this email message and any attachments immediately.
[PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() -> xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() -> xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
"PCI: ARM: add support for generic PCI host controller"
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be "pci"
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ reg = < 0x5000 0x1000 >;
+ device_type = "pci";
+ interrupts = < 0 52 4 >;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 _intc 1>,
+ <0
[PATCH v5] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up() - xilinx_pcie_link_is_up()
xilinx_pcie_verify_config() - xilinx_pcie_valid_device()
xilinx_pcie_get_config_base() - xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 978
4 files changed, 1048 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = 3;
+ #size-cells = 2;
+ #interrupt-cells = 1;
+ compatible = xlnx,axi-pcie-host-1.00.a;
+ reg = 0x5000 0x1000 ;
+ device_type = pci;
+ interrupts = 0 52 4 ;
+ interrupt-map-mask = 0 0 0 7;
+ interrupt-map = 0 0 0 1 pcie_intc 1,
+ 0 0 0 2 pcie_intc 2,
+ 0 0 0 3 pcie_intc 3,
+ 0 0 0 4 pcie_intc 4
Re: [PATCH v4] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, On Wed, Jul 16, 2014 at 11:08 PM, Bjorn Helgaas wrote: > On Thu, Jul 03, 2014 at 09:57:34AM +0530, Srikanth Thokala wrote: >> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP >> >> Signed-off-by: Srikanth Thokala >> --- >> Changes in v4: >> - Regarding the comments to separate ECAM functionality, >> I have sent a separate patch and it is decided to implement >> it later. The patch is here, >> https://lkml.org/lkml/2014/5/18/54 >> - Fixed issue with adding configuration bus resource. >> - Moved the logic for setting up bus resources to probe() from >> pcie_setup(). >> - Instead of mapping all the MSI interrupts in the probe, changed >> to map only when a MSI is requested. >> - Earlier, the implementation of legacy and MSI interrupts init- >> is mutually exclusive, now changed to have the legacy interrupts >> init always and MSI interrupt init based on CONFIG_PCI_MSI flag. >> - Regarding the MSI generic implementation comment, I will plan to >> do on top of this driver patch. >> - Rebased on 3.16-rc2. >> - Fixed other minor comments. >> - Thanks Arnd and Bjorn for the review. >> >> Changes in v3: >> - Rebased on v3.15.0-rc1 >> - Added support for interrupt-map DT functionality. >> - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). >> - Modified resource mapping logic as per the series >> "PCI: ARM: add support for generic PCI host controller" >> - Modified devicetree binding documentation to update with interrupt- >> map properties. >> - Use devm calls wherever applicable. >> - Fixed minor comments from Jason >> - Thanks Jason for the review and suggestions. >> >> Changes in v2: >> - Rebased on v3.14.0-rc8 >> - Removed IP specific DT properties like include-rc, axibar-num etc., >> as suggested by Jason and Bjorn, Thanks >> --- >> .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ >> drivers/pci/host/Kconfig |7 + >> drivers/pci/host/Makefile |1 + >> drivers/pci/host/pci-xilinx.c | 1027 >> >> 4 files changed, 1097 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> create mode 100644 drivers/pci/host/pci-xilinx.c > > I see I forgot to ask for a MAINTAINERS entry for this driver. Can > you add one? There was a discussion on this earlier and Michal mentioned it is not required as it is handled by our Xilinx record. Here is the reply from Michal to the MAINTAINERS update comment, < Reply from Michal > > Please also include a MAINTAINERS update for drivers/pci/host/pci-xilinx.c. This should be handle by our record that's why MAINTAINERS update is not necessary. (N: xilinx below) ARM/ZYNQ ARCHITECTURE M: Michal Simek L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) W: http://wiki.xilinx.com T: git git://git.xilinx.com/linux-xlnx.git S: Supported F: arch/arm/mach-zynq/ F: drivers/cpuidle/cpuidle-zynq.c N: zynq N: xilinx F: drivers/clocksource/cadence_ttc_timer.c F: drivers/mmc/host/sdhci-of-arasan.c Thanks, Michal < Reply from Michal > > > I'd also like an ack from Arnd or another devicetree person for the > binding. Sure, I will request them. > > I have a few minor comments below. Sure. > >> diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> new file mode 100644 >> index 000..3e2c88d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt >> @@ -0,0 +1,62 @@ >> +* Xilinx AXI PCIe Root Port Bridge DT description >> + >> +Required properties: >> +- #address-cells: Address representation for root ports, set to <3> >> +- #size-cells: Size representation for root ports, set to <2> >> +- #interrupt-cells: specifies the number of cells needed to encode an >> + interrupt source. The value must be 1. >> +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" >> +- reg: Should contain AXI PCIe registers location and length >> +- device_type: must be "pci" >> +- interrupts: Should contain AXI PCIe interrupt >> +- interrupt-map-mask, >> + interrupt-map: standard PCI properties to define the mapping of the >> + PCI interface to interrupt numbers. >> +- ranges: ranges for the PCI memory regions (I/O space region is not >> + supported by hardware) >> + Please refer to the standar
Re: [PATCH v4] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi Bjorn, On Wed, Jul 16, 2014 at 11:08 PM, Bjorn Helgaas bhelg...@google.com wrote: On Thu, Jul 03, 2014 at 09:57:34AM +0530, Srikanth Thokala wrote: This is the driver for Xilinx AXI PCIe Host Bridge Soft IP Signed-off-by: Srikanth Thokala stho...@xilinx.com --- Changes in v4: - Regarding the comments to separate ECAM functionality, I have sent a separate patch and it is decided to implement it later. The patch is here, https://lkml.org/lkml/2014/5/18/54 - Fixed issue with adding configuration bus resource. - Moved the logic for setting up bus resources to probe() from pcie_setup(). - Instead of mapping all the MSI interrupts in the probe, changed to map only when a MSI is requested. - Earlier, the implementation of legacy and MSI interrupts init- is mutually exclusive, now changed to have the legacy interrupts init always and MSI interrupt init based on CONFIG_PCI_MSI flag. - Regarding the MSI generic implementation comment, I will plan to do on top of this driver patch. - Rebased on 3.16-rc2. - Fixed other minor comments. - Thanks Arnd and Bjorn for the review. Changes in v3: - Rebased on v3.15.0-rc1 - Added support for interrupt-map DT functionality. - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci(). - Modified resource mapping logic as per the series PCI: ARM: add support for generic PCI host controller - Modified devicetree binding documentation to update with interrupt- map properties. - Use devm calls wherever applicable. - Fixed minor comments from Jason - Thanks Jason for the review and suggestions. Changes in v2: - Rebased on v3.14.0-rc8 - Removed IP specific DT properties like include-rc, axibar-num etc., as suggested by Jason and Bjorn, Thanks --- .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++ drivers/pci/host/Kconfig |7 + drivers/pci/host/Makefile |1 + drivers/pci/host/pci-xilinx.c | 1027 4 files changed, 1097 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 drivers/pci/host/pci-xilinx.c I see I forgot to ask for a MAINTAINERS entry for this driver. Can you add one? There was a discussion on this earlier and Michal mentioned it is not required as it is handled by our Xilinx record. Here is the reply from Michal to the MAINTAINERS update comment, Reply from Michal Please also include a MAINTAINERS update for drivers/pci/host/pci-xilinx.c. This should be handle by our record that's why MAINTAINERS update is not necessary. (N: xilinx below) ARM/ZYNQ ARCHITECTURE M: Michal Simek michal.si...@xilinx.com L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) W: http://wiki.xilinx.com T: git git://git.xilinx.com/linux-xlnx.git S: Supported F: arch/arm/mach-zynq/ F: drivers/cpuidle/cpuidle-zynq.c N: zynq N: xilinx F: drivers/clocksource/cadence_ttc_timer.c F: drivers/mmc/host/sdhci-of-arasan.c Thanks, Michal Reply from Michal I'd also like an ack from Arnd or another devicetree person for the binding. Sure, I will request them. I have a few minor comments below. Sure. diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt new file mode 100644 index 000..3e2c88d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -0,0 +1,62 @@ +* Xilinx AXI PCIe Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to 3 +- #size-cells: Size representation for root ports, set to 2 +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain xlnx,axi-pcie-host-1.00.a +- reg: Should contain AXI PCIe registers location and length +- device_type: must be pci +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation + +Optional properties: +- bus-range: PCI bus numbers covered + +Interrupt controller child node +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + +NOTE: +The core provides a single interrupt for both INTx/MSI messages. So, +created a interrupt
[PATCH v4] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
"PCI: ARM: add support for generic PCI host controller"
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 1027
4 files changed, 1097 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be "pci"
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ reg = < 0x5000 0x1000 >;
+ device_type = "pci";
+ interrupts = < 0 52 4 >;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 _intc 1>,
+ <0 0 0 2 _intc 2>,
+ <0 0 0 3 _intc 3>,
+ <0 0 0 4 _intc 4>;
+ ranges = < 0x0200 0 0x6000 0x6000 0 0x1000 >;
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ }
+ };
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 21df477..afedcde
[PATCH v4] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
is mutually exclusive, now changed to have the legacy interrupts
init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 1027
4 files changed, 1097 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..3e2c88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = 3;
+ #size-cells = 2;
+ #interrupt-cells = 1;
+ compatible = xlnx,axi-pcie-host-1.00.a;
+ reg = 0x5000 0x1000 ;
+ device_type = pci;
+ interrupts = 0 52 4 ;
+ interrupt-map-mask = 0 0 0 7;
+ interrupt-map = 0 0 0 1 pcie_intc 1,
+ 0 0 0 2 pcie_intc 2,
+ 0 0 0 3 pcie_intc 3,
+ 0 0 0 4 pcie_intc 4;
+ ranges = 0x0200 0 0x6000 0x6000 0 0x1000 ;
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 1;
+ }
+ };
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 21df477..afedcde 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -46,4 +46,11 @@ config PCI_HOST_GENERIC
Say Y here if you want
RE: [PATCH] PCI: Generic Configuration Access Mechanism support
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Wednesday, May 21, 2014 1:23 PM
> To: Srikanth Thokala
> Cc: Bjorn Helgaas; will.dea...@arm.com; Michal Simek; linux-
> ker...@vger.kernel.org; linux-...@vger.kernel.org
> Subject: Re: [PATCH] PCI: Generic Configuration Access Mechanism support
>
> On Tuesday 20 May 2014 20:01:01 Srikanth Thokala wrote:
> > On Mon, May 19, 2014 at 10:33 PM, Arnd Bergmann
> wrote:
> > > On Sunday 18 May 2014 19:38:45 Srikanth Thokala wrote:
> > >> +
> > >> + if (cfg->ops->is_valid_cfg_access) {
> > >> + if (!cfg->ops->is_valid_cfg_access(bus, devfn)) {
> > >> + *val = PCI_CFG_INVALID_DEVFN;
> > >> + return PCIBIOS_DEVICE_NOT_FOUND;
> > >> + }
> > >> + }
> > >
> > > Can you explain why this callback is needed? If the space for the
> > > bus is mapped, any access should just work.
> >
> > As I was explaining to Will, there are some controllers which doesn't
> > return FF's when a device is not found on the bus (as per the PCI
> > specification) and accessing such a device address from the kernel
> > results in an external abort.
> > So, I added this additional logic in my driver to bypass this and
> > return FF's. Our IP and even other controllers like Tegra, Renesas
> > have similar implementation.
> > We cant think of a better solution and please let you us know if you
> > have any inputs.
>
> Does your hardware need this? My first response would otherwise be to
> treat that as noncompliant and not handle this case in the generic
> implementation.
Yes, my hardware needs this additional logic.
Srikanth
>
> Arnd
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RE: [PATCH] PCI: Generic Configuration Access Mechanism support
-Original Message-
From: Arnd Bergmann [mailto:a...@arndb.de]
Sent: Wednesday, May 21, 2014 1:23 PM
To: Srikanth Thokala
Cc: Bjorn Helgaas; will.dea...@arm.com; Michal Simek; linux-
ker...@vger.kernel.org; linux-...@vger.kernel.org
Subject: Re: [PATCH] PCI: Generic Configuration Access Mechanism support
On Tuesday 20 May 2014 20:01:01 Srikanth Thokala wrote:
On Mon, May 19, 2014 at 10:33 PM, Arnd Bergmann a...@arndb.de
wrote:
On Sunday 18 May 2014 19:38:45 Srikanth Thokala wrote:
+
+ if (cfg-ops-is_valid_cfg_access) {
+ if (!cfg-ops-is_valid_cfg_access(bus, devfn)) {
+ *val = PCI_CFG_INVALID_DEVFN;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ }
Can you explain why this callback is needed? If the space for the
bus is mapped, any access should just work.
As I was explaining to Will, there are some controllers which doesn't
return FF's when a device is not found on the bus (as per the PCI
specification) and accessing such a device address from the kernel
results in an external abort.
So, I added this additional logic in my driver to bypass this and
return FF's. Our IP and even other controllers like Tegra, Renesas
have similar implementation.
We cant think of a better solution and please let you us know if you
have any inputs.
Does your hardware need this? My first response would otherwise be to
treat that as noncompliant and not handle this case in the generic
implementation.
Yes, my hardware needs this additional logic.
Srikanth
Arnd
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Re: [PATCH] PCI: Generic Configuration Access Mechanism support
Hi Arnd,
On Mon, May 19, 2014 at 10:33 PM, Arnd Bergmann wrote:
> On Sunday 18 May 2014 19:38:45 Srikanth Thokala wrote:
>> +
>> + if (cfg->ops->is_valid_cfg_access) {
>> + if (!cfg->ops->is_valid_cfg_access(bus, devfn)) {
>> + *val = PCI_CFG_INVALID_DEVFN;
>> + return PCIBIOS_DEVICE_NOT_FOUND;
>> + }
>> + }
>
> Can you explain why this callback is needed? If the space for the
> bus is mapped, any access should just work.
As I was explaining to Will, there are some controllers which doesn't
return FF's
when a device is not found on the bus (as per the PCI specification) and
accessing such a device address from the kernel results in an external abort.
So, I added this additional logic in my driver to bypass this and
return FF's. Our IP
and even other controllers like Tegra, Renesas have similar implementation.
We cant think of a better solution and please let you us know if you
have any inputs.
Thanks
Srikanth
>
>> +
>> +/* Generic PCI CAM/ECAM Configuration Bus Operations */
>> +
>> +struct pci_cfg_bus_ops pci_cfg_cam_bus_ops = {
>> + .bus_shift = PCI_CFG_CAM_BUS_NUM,
>> + .map_bus= pci_cfg_map_bus_cam,
>> +};
>> +EXPORT_SYMBOL_GPL(pci_cfg_cam_bus_ops);
>> +
>> +struct pci_cfg_bus_ops pci_cfg_ecam_bus_ops = {
>> + .bus_shift = PCI_CFG_ECAM_BUS_NUM,
>> + .map_bus= pci_cfg_map_bus_ecam,
>> +};
>> +EXPORT_SYMBOL_GPL(pci_cfg_ecam_bus_ops);
>> +
>> +struct pci_ops pci_cfg_ops = {
>> + .read = pci_cfg_read,
>> + .write = pci_cfg_write,
>> +};
>> +EXPORT_SYMBOL_GPL(pci_cfg_ops);
>
>
> If we can find a way to remove the is_valid_cfg_access() check, we're
> probably better off removing the cfg_bus_ops as well, and exporting
> two sets of pci_ops. There will be a little more duplication here, but
> also less complexity in this module, and more importantly in the drivers
> using it.
>
> Arnd
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Re: [PATCH] PCI: Generic Configuration Access Mechanism support
Hi Arnd,
On Mon, May 19, 2014 at 10:33 PM, Arnd Bergmann a...@arndb.de wrote:
On Sunday 18 May 2014 19:38:45 Srikanth Thokala wrote:
+
+ if (cfg-ops-is_valid_cfg_access) {
+ if (!cfg-ops-is_valid_cfg_access(bus, devfn)) {
+ *val = PCI_CFG_INVALID_DEVFN;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ }
Can you explain why this callback is needed? If the space for the
bus is mapped, any access should just work.
As I was explaining to Will, there are some controllers which doesn't
return FF's
when a device is not found on the bus (as per the PCI specification) and
accessing such a device address from the kernel results in an external abort.
So, I added this additional logic in my driver to bypass this and
return FF's. Our IP
and even other controllers like Tegra, Renesas have similar implementation.
We cant think of a better solution and please let you us know if you
have any inputs.
Thanks
Srikanth
+
+/* Generic PCI CAM/ECAM Configuration Bus Operations */
+
+struct pci_cfg_bus_ops pci_cfg_cam_bus_ops = {
+ .bus_shift = PCI_CFG_CAM_BUS_NUM,
+ .map_bus= pci_cfg_map_bus_cam,
+};
+EXPORT_SYMBOL_GPL(pci_cfg_cam_bus_ops);
+
+struct pci_cfg_bus_ops pci_cfg_ecam_bus_ops = {
+ .bus_shift = PCI_CFG_ECAM_BUS_NUM,
+ .map_bus= pci_cfg_map_bus_ecam,
+};
+EXPORT_SYMBOL_GPL(pci_cfg_ecam_bus_ops);
+
+struct pci_ops pci_cfg_ops = {
+ .read = pci_cfg_read,
+ .write = pci_cfg_write,
+};
+EXPORT_SYMBOL_GPL(pci_cfg_ops);
If we can find a way to remove the is_valid_cfg_access() check, we're
probably better off removing the cfg_bus_ops as well, and exporting
two sets of pci_ops. There will be a little more duplication here, but
also less complexity in this module, and more importantly in the drivers
using it.
Arnd
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[PATCH] PCI: Generic Configuration Access Mechanism support
This patch adds support for a generic CAM and ECAM configuration
space accesses.
Signed-off-by: Srikanth Thokala
---
This patch is created with reference from Will's patch series:
1/3 - "ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM"
2/3 - "PCI: ARM: add support for generic PCI host controller"
3/3 - "MAINTAINERS: add entry for generic PCI host controller driver"
---
drivers/pci/Makefile |2 +-
drivers/pci/pci-cfg.c | 162 +
include/linux/pci.h | 34 +++
3 files changed, 197 insertions(+), 1 deletion(-)
create mode 100644 drivers/pci/pci-cfg.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index e04fe2d..37cfc33 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -4,7 +4,7 @@
obj-y += access.o bus.o probe.o host-bridge.o remove.o pci.o \
pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \
- irq.o vpd.o setup-bus.o vc.o
+ irq.o vpd.o setup-bus.o vc.o pci-cfg.o
obj-$(CONFIG_PROC_FS) += proc.o
obj-$(CONFIG_SYSFS) += slot.o
diff --git a/drivers/pci/pci-cfg.c b/drivers/pci/pci-cfg.c
new file mode 100644
index 000..2b15fe4
--- /dev/null
+++ b/drivers/pci/pci-cfg.c
@@ -0,0 +1,162 @@
+/*
+ * PCI generic configuration access mechanism
+ *
+ * Copyright (C) 2014 ARM Limited
+ * Copyright (c) 2014 Xilinx, Inc.
+ *
+ * Author: Will Deacon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+
+/* CAM definitions */
+#define PCI_CFG_CAM_BUS_NUM16
+#define PCI_CFG_CAM_DEV_NUM8
+
+/* ECAM definitions */
+#define PCI_CFG_ECAM_BUS_NUM 20
+#define PCI_CFG_ECAM_DEV_NUM 12
+
+/* Invalid device/function value */
+#define PCI_CFG_INVALID_DEVFN 0x
+
+/**
+ * pci_cfg_map_bus_cam - Get the CAM based configuration space address
+ * @bus: PCI Bus pointer
+ * @devfn: Device/Function
+ * @where: Offset from base
+ *
+ * Return: Configuration Space address
+ */
+static void __iomem *pci_cfg_map_bus_cam(struct pci_bus *bus,
+unsigned int devfn,
+int where)
+{
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pci_cfg_windows *cfg = sys->private_data;
+ resource_size_t idx = bus->number - cfg->bus_range.start;
+
+ return cfg->win[idx] + ((devfn << PCI_CFG_CAM_DEV_NUM) | where);
+}
+
+/**
+ * pci_cfg_map_bus_ecam - Get the ECAM based configuration space address
+ * @bus: PCI bus pointer
+ * @devfn: Device/Function
+ * @where: Offset from base
+ *
+ * Return: Configuration space address
+ */
+static void __iomem *pci_cfg_map_bus_ecam(struct pci_bus *bus,
+ unsigned int devfn,
+ int where)
+{
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pci_cfg_windows *cfg = sys->private_data;
+ resource_size_t idx = bus->number - cfg->bus_range.start;
+
+ return cfg->win[idx] + ((devfn << PCI_CFG_ECAM_DEV_NUM) | where);
+}
+
+/**
+ * pci_cfg_read - Read configuration space
+ * @bus: PCI bus pointer
+ * @devfn: Device/function
+ * @where: Offset from base
+ * @size: Byte/word/dword
+ * @val: Value to be read
+ *
+ * Return: PCIBIOS_SUCCESSFUL on success
+ *PCIBIOS_DEVICE_NOT_FOUND on failure
+ */
+static int pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, unsigned int *val)
+{
+ void __iomem *addr;
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pci_cfg_windows *cfg = sys->private_data;
+
+ if (cfg->ops->is_valid_cfg_access) {
+ if (!cfg->ops->is_valid_cfg_access(bus, devfn)) {
+ *val = PCI_CFG_INVALID_DEVFN;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ }
+
+ addr = cfg->ops->map_bus(bus, devfn, where);
+
+ switch (size) {
+ case 1:
+ *val = readb(addr);
+ break;
+ case 2:
+ *val = readw(addr);
+ break;
+ default:
+ *val = readl(addr);
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/**
+ * pci_cfg_write - Write configuration space
+ * @bus: PCI bus pointer
+ * @devfn: Device/function
+ * @where: Offset from base
+ * @size: Byte/word/dword
+ * @val: Value to write
+ *
+ * Return: PCIBIOS_SUCCESSFUL on success
+ *PCIBIOS_DEVICE_NOT_FOUND on failure
+ */
+static int pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
+int where, int size, unsigned int val)
+{
+ void __iomem *addr;
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pci_cfg_windows *
[PATCH] PCI: Generic Configuration Access Mechanism support
This patch adds support for a generic CAM and ECAM configuration
space accesses.
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
This patch is created with reference from Will's patch series:
1/3 - ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM
2/3 - PCI: ARM: add support for generic PCI host controller
3/3 - MAINTAINERS: add entry for generic PCI host controller driver
---
drivers/pci/Makefile |2 +-
drivers/pci/pci-cfg.c | 162 +
include/linux/pci.h | 34 +++
3 files changed, 197 insertions(+), 1 deletion(-)
create mode 100644 drivers/pci/pci-cfg.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index e04fe2d..37cfc33 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -4,7 +4,7 @@
obj-y += access.o bus.o probe.o host-bridge.o remove.o pci.o \
pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \
- irq.o vpd.o setup-bus.o vc.o
+ irq.o vpd.o setup-bus.o vc.o pci-cfg.o
obj-$(CONFIG_PROC_FS) += proc.o
obj-$(CONFIG_SYSFS) += slot.o
diff --git a/drivers/pci/pci-cfg.c b/drivers/pci/pci-cfg.c
new file mode 100644
index 000..2b15fe4
--- /dev/null
+++ b/drivers/pci/pci-cfg.c
@@ -0,0 +1,162 @@
+/*
+ * PCI generic configuration access mechanism
+ *
+ * Copyright (C) 2014 ARM Limited
+ * Copyright (c) 2014 Xilinx, Inc.
+ *
+ * Author: Will Deacon will.dea...@arm.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/of_pci.h
+
+/* CAM definitions */
+#define PCI_CFG_CAM_BUS_NUM16
+#define PCI_CFG_CAM_DEV_NUM8
+
+/* ECAM definitions */
+#define PCI_CFG_ECAM_BUS_NUM 20
+#define PCI_CFG_ECAM_DEV_NUM 12
+
+/* Invalid device/function value */
+#define PCI_CFG_INVALID_DEVFN 0x
+
+/**
+ * pci_cfg_map_bus_cam - Get the CAM based configuration space address
+ * @bus: PCI Bus pointer
+ * @devfn: Device/Function
+ * @where: Offset from base
+ *
+ * Return: Configuration Space address
+ */
+static void __iomem *pci_cfg_map_bus_cam(struct pci_bus *bus,
+unsigned int devfn,
+int where)
+{
+ struct pci_sys_data *sys = bus-sysdata;
+ struct pci_cfg_windows *cfg = sys-private_data;
+ resource_size_t idx = bus-number - cfg-bus_range.start;
+
+ return cfg-win[idx] + ((devfn PCI_CFG_CAM_DEV_NUM) | where);
+}
+
+/**
+ * pci_cfg_map_bus_ecam - Get the ECAM based configuration space address
+ * @bus: PCI bus pointer
+ * @devfn: Device/Function
+ * @where: Offset from base
+ *
+ * Return: Configuration space address
+ */
+static void __iomem *pci_cfg_map_bus_ecam(struct pci_bus *bus,
+ unsigned int devfn,
+ int where)
+{
+ struct pci_sys_data *sys = bus-sysdata;
+ struct pci_cfg_windows *cfg = sys-private_data;
+ resource_size_t idx = bus-number - cfg-bus_range.start;
+
+ return cfg-win[idx] + ((devfn PCI_CFG_ECAM_DEV_NUM) | where);
+}
+
+/**
+ * pci_cfg_read - Read configuration space
+ * @bus: PCI bus pointer
+ * @devfn: Device/function
+ * @where: Offset from base
+ * @size: Byte/word/dword
+ * @val: Value to be read
+ *
+ * Return: PCIBIOS_SUCCESSFUL on success
+ *PCIBIOS_DEVICE_NOT_FOUND on failure
+ */
+static int pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, unsigned int *val)
+{
+ void __iomem *addr;
+ struct pci_sys_data *sys = bus-sysdata;
+ struct pci_cfg_windows *cfg = sys-private_data;
+
+ if (cfg-ops-is_valid_cfg_access) {
+ if (!cfg-ops-is_valid_cfg_access(bus, devfn)) {
+ *val = PCI_CFG_INVALID_DEVFN;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ }
+
+ addr = cfg-ops-map_bus(bus, devfn, where);
+
+ switch (size) {
+ case 1:
+ *val = readb(addr);
+ break;
+ case 2:
+ *val = readw(addr);
+ break;
+ default:
+ *val = readl(addr);
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/**
+ * pci_cfg_write - Write configuration space
+ * @bus: PCI bus pointer
+ * @devfn: Device/function
+ * @where: Offset from base
+ * @size: Byte/word/dword
+ * @val: Value to write
+ *
+ * Return: PCIBIOS_SUCCESSFUL on success
+ *PCIBIOS_DEVICE_NOT_FOUND on failure
+ */
+static int pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
+int where, int size, unsigned int val)
+{
+ void __iomem *addr;
+ struct pci_sys_data *sys = bus-sysdata;
+ struct pci_cfg_windows *cfg = sys-private_data;
+
+ if (cfg-ops-is_valid_cfg_access
Re: [PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, May 7, 2014 at 8:05 PM, Arnd Bergmann wrote:
> On Wednesday 07 May 2014 17:21:13 Srikanth Thokala wrote:
>> On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann wrote:
>> > On Tuesday 15 April 2014, Srikanth Thokala wrote:
>> >> +/**
>> >> + * xilinx_pcie_get_config_base - Get configuration base
>> >> + * @bus: Bus structure of current bus
>> >> + * @devfn: Device/function
>> >> + * @where: Offset from base
>> >> + *
>> >> + * Return: Base address of the configuration space needed to be
>> >> + * accessed.
>> >> + */
>> >> +static void __iomem *xilinx_pcie_get_config_base(struct pci_bus *bus,
>> >> + unsigned int devfn,
>> >> + int where)
>> >> +{
>> >> + struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
>> >> + int relbus;
>> >> +
>> >> + relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
>> >> + (devfn << ECAM_DEV_NUM_SHIFT);
>> >> +
>> >> + return port->reg_base + relbus + where;
>> >> +}
>> >
>> > Does this mean you have an ECAM-compliant config space? Nice!
>> >
>> > Would it be possible to split the config space access out into
>> > a separate file? It would be nice to share that with the generic
>> > ECAM driver that Will Deacon has sent.
>>
>> Yes, it should be possible. Is it ok, if I work on top of this driver?
>
> Do you mean as a follow-on patch? My feeling is that since we are trying
> to merge both for 3.16, it would be good to get it done right away if
> it doesn't cause too much extra work.
Sure, I will work with Will and let you know.
>
>> >> +/**
>> >> + * xilinx_pcie_enable_msi - Enable MSI support
>> >> + * @port: PCIe port information
>> >> + */
>> >> +static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
>> >> +{
>> >> + port->msg_addr = __get_free_pages(GFP_KERNEL, 0);
>> >> +
>> >> + pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
>> >> + pcie_write(port, virt_to_phys((void *)port->msg_addr),
>> >> +XILINX_PCIE_REG_MSIBASE2);
>> >> +}
>> >
>> > As a general comment about the MSI implementation, I wonder if this is
>> > actually
>> > generic enough to be shared with other host controllers. It could be moved
>> > into a separate file like the config space access in that case.
>>
>> I feel the MSI implementation is not generic by looking into the other
>> host controllers,
>> it is more specific to the hardware. Correct me, if am wrong.
>
> The other host controllers are certainly incompatible, but this one looks
> like it could be used on other controllers easily.
>
> Splitting it out would also make it easier to use another MSI implementation
> like the one in the GIC.
I need to look into this and I will come back to you.
>
>
>> >> + /* Register the device */
>> >> + pci_common_init_dev(dev, );
>> >> +
>> >> + platform_set_drvdata(pdev, port);
>> >
>> > Don't you have to do the platform_set_drvdata() before
>> > pci_common_init_dev()?
>>
>> It should be fine, as I don't see any dependencies.
>
> Ah, it's only used in the remove function. It looks correct then, but I think
> it would be better to set it first anyway, in case another function starts
> using
> the drvdata later and that function may get called by the PCI initialization.
Ok.
Srikanth
>
> Arnd
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Re: [PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, May 7, 2014 at 8:05 PM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 07 May 2014 17:21:13 Srikanth Thokala wrote:
On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 15 April 2014, Srikanth Thokala wrote:
+/**
+ * xilinx_pcie_get_config_base - Get configuration base
+ * @bus: Bus structure of current bus
+ * @devfn: Device/function
+ * @where: Offset from base
+ *
+ * Return: Base address of the configuration space needed to be
+ * accessed.
+ */
+static void __iomem *xilinx_pcie_get_config_base(struct pci_bus *bus,
+ unsigned int devfn,
+ int where)
+{
+ struct xilinx_pcie_port *port = sys_to_pcie(bus-sysdata);
+ int relbus;
+
+ relbus = (bus-number ECAM_BUS_NUM_SHIFT) |
+ (devfn ECAM_DEV_NUM_SHIFT);
+
+ return port-reg_base + relbus + where;
+}
Does this mean you have an ECAM-compliant config space? Nice!
Would it be possible to split the config space access out into
a separate file? It would be nice to share that with the generic
ECAM driver that Will Deacon has sent.
Yes, it should be possible. Is it ok, if I work on top of this driver?
Do you mean as a follow-on patch? My feeling is that since we are trying
to merge both for 3.16, it would be good to get it done right away if
it doesn't cause too much extra work.
Sure, I will work with Will and let you know.
+/**
+ * xilinx_pcie_enable_msi - Enable MSI support
+ * @port: PCIe port information
+ */
+static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
+{
+ port-msg_addr = __get_free_pages(GFP_KERNEL, 0);
+
+ pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
+ pcie_write(port, virt_to_phys((void *)port-msg_addr),
+XILINX_PCIE_REG_MSIBASE2);
+}
As a general comment about the MSI implementation, I wonder if this is
actually
generic enough to be shared with other host controllers. It could be moved
into a separate file like the config space access in that case.
I feel the MSI implementation is not generic by looking into the other
host controllers,
it is more specific to the hardware. Correct me, if am wrong.
The other host controllers are certainly incompatible, but this one looks
like it could be used on other controllers easily.
Splitting it out would also make it easier to use another MSI implementation
like the one in the GIC.
I need to look into this and I will come back to you.
+ /* Register the device */
+ pci_common_init_dev(dev, hw);
+
+ platform_set_drvdata(pdev, port);
Don't you have to do the platform_set_drvdata() before
pci_common_init_dev()?
It should be fine, as I don't see any dependencies.
Ah, it's only used in the remove function. It looks correct then, but I think
it would be better to set it first anyway, in case another function starts
using
the drvdata later and that function may get called by the PCI initialization.
Ok.
Srikanth
Arnd
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Re: [PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann wrote:
> On Tuesday 15 April 2014, Srikanth Thokala wrote:
>> +Required properties:
>> +- #address-cells: Address representation for root ports, set to <3>
>> +- #size-cells: Size representation for root ports, set to <2>
>> +- #interrupt-cells: specifies the number of cells needed to encode an
>> + interrupt source. The value must be 1.
>> +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
>> +- reg: Should contain AXI PCIe registers location and length
>> +- device_type: must be "pci"
>> +- interrupts: Should contain AXI PCIe interrupt
>> +- interrupt-map-mask,
>> + interrupt-map: standard PCI properties to define the mapping of the
>> + PCI interface to interrupt numbers.
>> +- ranges: ranges for the PCI memory regions (I/O space region is noti
>
> typo: noti -> not
Ok, will fix.
>
>> + supported by hardware)
>> + Please refer to the standard PCI bus binding document for a more
>> + detailed explanation
>> +
>> +Optional properties:
>> +- bus-range: PCI bus numbers covered
>> +
>> +Interrupt controller child node
>>
>> +Required properties:
>> +- interrupt-controller: identifies the node as an interrupt controller
>> +- #address-cells: specifies the number of cells needed to encode an
>> + address. The value must be 0.
>> +- #interrupt-cells: specifies the number of cells needed to encode an
>> + interrupt source. The value must be 1.
>> +
>> +NOTE:
>> +The core provides a single interrupt for both INTx/MSI messages. So,
>> +created a interrupt controller node to support 'interrupt-map' DT
>> +functionality. The driver will create an IRQ domain for this map, decode
>> +the four INTx interrupts in ISR and route them to this domain.
>
> How does this work if the pci core is combined with a GIC version that
> also has MSI support. Presumably you'd want to use that for performance
> reason rather than the integrated MSI chip.
>
> Shouldn't there be a way to pick between the two?
I will check and come back to you on this.
>
>> +/**
>> + * xilinx_pcie_get_config_base - Get configuration base
>> + * @bus: Bus structure of current bus
>> + * @devfn: Device/function
>> + * @where: Offset from base
>> + *
>> + * Return: Base address of the configuration space needed to be
>> + * accessed.
>> + */
>> +static void __iomem *xilinx_pcie_get_config_base(struct pci_bus *bus,
>> + unsigned int devfn,
>> + int where)
>> +{
>> + struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
>> + int relbus;
>> +
>> + relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
>> + (devfn << ECAM_DEV_NUM_SHIFT);
>> +
>> + return port->reg_base + relbus + where;
>> +}
>
> Does this mean you have an ECAM-compliant config space? Nice!
>
> Would it be possible to split the config space access out into
> a separate file? It would be nice to share that with the generic
> ECAM driver that Will Deacon has sent.
Yes, it should be possible. Is it ok, if I work on top of this driver?
>
>> +
>> + msg.address_hi = 0;
>> + msg.address_lo = virt_to_phys((void *)port->msg_addr);
>> + msg.data = irq;
>> +
>> + write_msi_msg(irq, );
>
> It seems strange to pass the msg_addr as an integer referring to
> a virtual address. I'd suggest using phys_addr_t for the type
> and converting it at the point the page gets allocated, and then
> always assigning both the high and low part here. You'll need
> that anyway for 64-bit operation.
Ok, I will fix it. Thanks.
>
>> +/**
>> + * xilinx_pcie_enable_msi - Enable MSI support
>> + * @port: PCIe port information
>> + */
>> +static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
>> +{
>> + port->msg_addr = __get_free_pages(GFP_KERNEL, 0);
>> +
>> + pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
>> + pcie_write(port, virt_to_phys((void *)port->msg_addr),
>> +XILINX_PCIE_REG_MSIBASE2);
>> +}
>
> here too.
>
> As a general comment about the MSI implementation, I wonder if this is
> actually
> generic enough to be shared with other host controllers. It could be moved
> into a separate file like the config space access in that case.
I feel the MSI implementation is not generic by looking into the other
hos
Re: [PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 15 April 2014, Srikanth Thokala wrote:
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is noti
typo: noti - not
Ok, will fix.
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
How does this work if the pci core is combined with a GIC version that
also has MSI support. Presumably you'd want to use that for performance
reason rather than the integrated MSI chip.
Shouldn't there be a way to pick between the two?
I will check and come back to you on this.
+/**
+ * xilinx_pcie_get_config_base - Get configuration base
+ * @bus: Bus structure of current bus
+ * @devfn: Device/function
+ * @where: Offset from base
+ *
+ * Return: Base address of the configuration space needed to be
+ * accessed.
+ */
+static void __iomem *xilinx_pcie_get_config_base(struct pci_bus *bus,
+ unsigned int devfn,
+ int where)
+{
+ struct xilinx_pcie_port *port = sys_to_pcie(bus-sysdata);
+ int relbus;
+
+ relbus = (bus-number ECAM_BUS_NUM_SHIFT) |
+ (devfn ECAM_DEV_NUM_SHIFT);
+
+ return port-reg_base + relbus + where;
+}
Does this mean you have an ECAM-compliant config space? Nice!
Would it be possible to split the config space access out into
a separate file? It would be nice to share that with the generic
ECAM driver that Will Deacon has sent.
Yes, it should be possible. Is it ok, if I work on top of this driver?
+
+ msg.address_hi = 0;
+ msg.address_lo = virt_to_phys((void *)port-msg_addr);
+ msg.data = irq;
+
+ write_msi_msg(irq, msg);
It seems strange to pass the msg_addr as an integer referring to
a virtual address. I'd suggest using phys_addr_t for the type
and converting it at the point the page gets allocated, and then
always assigning both the high and low part here. You'll need
that anyway for 64-bit operation.
Ok, I will fix it. Thanks.
+/**
+ * xilinx_pcie_enable_msi - Enable MSI support
+ * @port: PCIe port information
+ */
+static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
+{
+ port-msg_addr = __get_free_pages(GFP_KERNEL, 0);
+
+ pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
+ pcie_write(port, virt_to_phys((void *)port-msg_addr),
+XILINX_PCIE_REG_MSIBASE2);
+}
here too.
As a general comment about the MSI implementation, I wonder if this is
actually
generic enough to be shared with other host controllers. It could be moved
into a separate file like the config space access in that case.
I feel the MSI implementation is not generic by looking into the other
host controllers,
it is more specific to the hardware. Correct me, if am wrong.
+/**
+ * xilinx_pcie_init_irq_domain - Initialize IRQ domain
+ * @port: PCIe port information
+ *
+ * Return: '0' on success and error value on failure
+ */
+static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
+{
+ struct device *dev = port-dev;
+ struct device_node *node = dev-of_node;
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ /* Setup MSI */
+ int i;
+
+ port-irq_domain = irq_domain_add_linear(node,
+ XILINX_NUM_MSI_IRQS,
+ msi_domain_ops,
+
xilinx_pcie_msi_chip
Re: [PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
On Thu, May 1, 2014 at 3:11 AM, Bjorn Helgaas wrote:
> On Tue, Apr 15, 2014 at 05:08:31PM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v3:
>> - Rebased on v3.15.0-rc1
>> - Added support for interrupt-map DT functionality.
>> - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
>> - Modified resource mapping logic as per the series
>> "PCI: ARM: add support for generic PCI host controller"
>> - Modified devicetree binding documentation to update with interrupt-
>> map properties.
>> - Use devm calls wherever applicable.
>> - Fixed minor comments from Jason
>> - Thanks Jason for the review and suggestions.
>>
>> Changes in v2:
>> - Rebased on v3.14.0-rc8
>> - Removed IP specific DT properties like include-rc, axibar-num etc.,
>> as suggested by Jason and Bjorn, Thanks
>> ---
>> .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
>> drivers/pci/host/Kconfig |7 +
>> drivers/pci/host/Makefile |1 +
>> drivers/pci/host/pci-xilinx.c | 999
>>
>> 4 files changed, 1069 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
>> create mode 100644 drivers/pci/host/pci-xilinx.c
>>
>> diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
>> b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
>> new file mode 100644
>> index 000..2fb28e0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
>> @@ -0,0 +1,62 @@
>> +* Xilinx AXI PCIe Root Port Bridge DT description
>> +
>> +Required properties:
>> +- #address-cells: Address representation for root ports, set to <3>
>> +- #size-cells: Size representation for root ports, set to <2>
>> +- #interrupt-cells: specifies the number of cells needed to encode an
>> + interrupt source. The value must be 1.
>> +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
>> +- reg: Should contain AXI PCIe registers location and length
>> +- device_type: must be "pci"
>> +- interrupts: Should contain AXI PCIe interrupt
>> +- interrupt-map-mask,
>> + interrupt-map: standard PCI properties to define the mapping of the
>> + PCI interface to interrupt numbers.
>> +- ranges: ranges for the PCI memory regions (I/O space region is noti
>> + supported by hardware)
>> + Please refer to the standard PCI bus binding document for a more
>> + detailed explanation
>> +
>> +Optional properties:
>> +- bus-range: PCI bus numbers covered
>> +
>> +Interrupt controller child node
>>
>> +Required properties:
>> +- interrupt-controller: identifies the node as an interrupt controller
>> +- #address-cells: specifies the number of cells needed to encode an
>> + address. The value must be 0.
>> +- #interrupt-cells: specifies the number of cells needed to encode an
>> + interrupt source. The value must be 1.
>> +
>> +NOTE:
>> +The core provides a single interrupt for both INTx/MSI messages. So,
>> +created a interrupt controller node to support 'interrupt-map' DT
>> +functionality. The driver will create an IRQ domain for this map, decode
>> +the four INTx interrupts in ISR and route them to this domain.
>> +
>> +
>> +Example:
>> +
>> +
>> + pci_express: axi-pcie@5000 {
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + #interrupt-cells = <1>;
>> + compatible = "xlnx,axi-pcie-host-1.00.a";
>> + reg = < 0x5000 0x1000 >;
>> + device_type = "pci";
>> + interrupts = < 0 52 4 >;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 _intc 1>,
>> + <0 0 0 2 _intc 2>,
>> + <0 0 0 3 _intc 3>,
>> + <0 0 0 4 _intc 4>;
>> + ranges = < 0x0200 0 0x6000 0x6000 0 0x1000 >;
>> +
>> + pcie_intc: interrupt-controller {
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
&g
Re: [PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
On Thu, May 1, 2014 at 3:11 AM, Bjorn Helgaas bhelg...@google.com wrote:
On Tue, Apr 15, 2014 at 05:08:31PM +0530, Srikanth Thokala wrote:
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 999
4 files changed, 1069 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..2fb28e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is noti
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = 3;
+ #size-cells = 2;
+ #interrupt-cells = 1;
+ compatible = xlnx,axi-pcie-host-1.00.a;
+ reg = 0x5000 0x1000 ;
+ device_type = pci;
+ interrupts = 0 52 4 ;
+ interrupt-map-mask = 0 0 0 7;
+ interrupt-map = 0 0 0 1 pcie_intc 1,
+ 0 0 0 2 pcie_intc 2,
+ 0 0 0 3 pcie_intc 3,
+ 0 0 0 4 pcie_intc 4;
+ ranges = 0x0200 0 0x6000 0x6000 0 0x1000 ;
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 1;
+ }
+ };
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a6f67ec..71afdcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,11 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
+config PCI_XILINX
+ bool Xilinx AXI PCIe host bridge support
+ depends on ARCH_ZYNQ
+ help
+ Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
+ Host Bridge driver.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..4e9c843 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj
[PATCH v8 2/2] dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
This is the driver for the AXI Video Direct Memory Access (AXI VDMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. The core provides efficient two dimensional DMA operations with independent asynchronous read and write channel operation. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala Acked-by: Jassi Brar Reviewed-by: Levente Kurusa --- NOTE: - Created a separate directory 'dma/xilinx' as Xilinx has two more DMA IPs and we are also planning to upstream these drivers soon. - This driver enables us to start pushing our media driver. Changes in v8: - Removed unnecessary cookie initialization as it is done by dma_cookie_assign() as suggested by Vinod, Thanks. Changes in v7: - Corrected the function description name of interleaved_dma API, as suggested by Jaswinder, Thanks. - Modified is_idle and is_running APIs to return 'bool'. Changes in v6: - Used is_slave_direction() API, as suggested by Andy, Thanks. - Moved the dev_info to end of probe() to indicate the probe is successful as suggested by Andy, Thanks. Changes in v5: - Modified to accept only 1 frame per interleaved_dma() call, as suggested by Jaswinder, Thanks. Changes in v4: - Created a separate function for the IP specific configuration instead of embedding the driver specific configuration into generic structure 'dma_slave_config', as suggested by Lars, Thanks. - Reverted the changes that were done in the earlier patch series, 1/3: 'Support multiple interleaved frames with non-contiguous memory' and accordingly made changes to support SG and non-SG Mode, as suggested by Jaswinder, Thanks. Changes in v3: - Implemented interleaved DMA API as suggested by Vinod and Lars, Thanks. - Use dma_slave_config generic API as suggested by Vinod and Lars, Thanks. - Simplified cookie implementation as sugguested by Vinod, Thanks. - Simplified *_xlate function by using dma_get_slave_channel() as suggested by Lars, Thanks. - Proper indentation of constants and maintained same multi-line of comments as suggested by Andy Shevchenko, Thanks. - Modified to use request_irq() instead of devm_request_irq as suggested by Lars, Thanks. - Fixed minor comments suggested by Andy and Levente, Thanks. Changes in v2: - Removed DMA Test client module from the patchset as suggested by Andy Shevchenko - Returning with error, if registration of DMA to node fails - Fixed typo errors - Used BIT() macro at applicable places - Added missing header file to the patchset - Changed copyright year to include 2014 --- drivers/dma/Kconfig | 14 + drivers/dma/Makefile |1 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_vdma.c | 1379 ++ include/linux/amba/xilinx_dma.h | 47 ++ 5 files changed, 1442 insertions(+) create mode 100644 drivers/dma/xilinx/Makefile create mode 100644 drivers/dma/xilinx/xilinx_vdma.c create mode 100644 include/linux/amba/xilinx_dma.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index ba06d1d..8257ffd 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -361,6 +361,20 @@ config FSL_EDMA multiplexing capability for DMA request sources(slot). This module can be found on Freescale Vybrid and LS-1 SoCs. +config XILINX_VDMA + tristate "Xilinx AXI VDMA Engine" + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI VDMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream video type target + peripherals including peripherals which support AXI4- + Stream Video Protocol. It has two stream interfaces/ + channels, Memory Mapped to Stream (MM2S) and Stream to + Memory Mapped (S2MM) for the data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 5150c82..c779e1e 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -46,3 +46,4 @@ obj-$(CONFIG_K3_DMA) += k3dma.o obj-$(CONFIG_MOXART_DMA) += moxart-dma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o +obj-y += xilinx/ diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile new file mode 100644 index 000..3c4e9f2 --- /dev/null +++ b/drivers/dma/xilinx/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o diff --git a/drivers/dma/xilinx/xilinx_vdma.c b/drivers/dma/xilinx/xilinx_vdma.c new file mode 100644 index 000..42a13e8 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_vdma.c @@ -0,0 +1,1379 @@ +/* + * DMA driver for Xilinx Video DMA Engine + * + * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI Video Dir
[PATCH v8 1/2] dma: Add Xilinx Video DMA DT Binding Documentation
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
Acked-by: Rob Herring
---
Changes in v8:
Fixed typos as suggested by Rob, Thanks.
Changes in v7:
None
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2:
- Removed device-id DT property, as suggested by Arnd Bergmann
- Properly documented DT bindings as suggested by Arnd Bergmann
---
.../devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 75
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
new file mode 100644
index 000..264100c
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
@@ -0,0 +1,75 @@
+Xilinx AXI VDMA engine, it does transfers between memory and video devices.
+It can be configured to have one channel or two channels. If configured
+as two channels, one is to transmit to the video device and another is
+to receive from the video device.
+
+Required properties:
+- compatible: Should be "xlnx,axi-vdma-1.00.a"
+- #dma-cells: Should be <1>, see "dmas" property below
+- reg: Should contain VDMA registers location and length.
+- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
+- dma-channel child node: Should have at least one channel and can have up to
+ two channels per device. This node specifies the properties of each
+ DMA channel (see child node properties below).
+
+Optional properties:
+- xlnx,include-sg: Tells configured for Scatter-mode in
+ the hardware.
+- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
+ It takes following values:
+ {1}, flush both channels
+ {2}, flush mm2s channel
+ {3}, flush s2mm channel
+
+Required child node properties:
+- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
+ "xlnx,axi-vdma-s2mm-channel".
+- interrupts: Should contain per channel VDMA interrupts.
+- xlnx,data-width: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Optional child node properties:
+- xlnx,include-dre: Tells hardware is configured for Data
+ Realignment Engine.
+- xlnx,genlock-mode: Tells Genlock synchronization is
+ enabled/disabled in hardware.
+
+Example:
+
+
+axi_vdma_0: axivdma@4003 {
+ compatible = "xlnx,axi-vdma-1.00.a";
+ #dma_cells = <1>;
+ reg = < 0x4003 0x1 >;
+ xlnx,num-fstores = <0x8>;
+ xlnx,flush-fsync = <0x1>;
+ dma-channel@4003 {
+ compatible = "xlnx,axi-vdma-mm2s-channel";
+ interrupts = < 0 54 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+ dma-channel@40030030 {
+ compatible = "xlnx,axi-vdma-s2mm-channel";
+ interrupts = < 0 53 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per "dmas" entry
+
+Example:
+
+
+vdmatest_0: vdmatest@0 {
+ compatible ="xlnx,axi-vdma-test-1.00.a";
+ dmas = <_vdma_0 0
+ _vdma_0 1>;
+ dma-names = "vdma0", "vdma1";
+} ;
--
1.7.9.5
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Re: [PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi,
Kindly review the driver and please let me know if you have any comments.
Thanks
Srikanth
On Tue, Apr 15, 2014 at 5:08 PM, Srikanth Thokala wrote:
> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
> Signed-off-by: Srikanth Thokala
> ---
> Changes in v3:
> - Rebased on v3.15.0-rc1
> - Added support for interrupt-map DT functionality.
> - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
> - Modified resource mapping logic as per the series
> "PCI: ARM: add support for generic PCI host controller"
> - Modified devicetree binding documentation to update with interrupt-
> map properties.
> - Use devm calls wherever applicable.
> - Fixed minor comments from Jason
> - Thanks Jason for the review and suggestions.
>
> Changes in v2:
> - Rebased on v3.14.0-rc8
> - Removed IP specific DT properties like include-rc, axibar-num etc.,
> as suggested by Jason and Bjorn, Thanks
> ---
> .../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
> drivers/pci/host/Kconfig |7 +
> drivers/pci/host/Makefile |1 +
> drivers/pci/host/pci-xilinx.c | 999
>
> 4 files changed, 1069 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> create mode 100644 drivers/pci/host/pci-xilinx.c
>
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> new file mode 100644
> index 000..2fb28e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> @@ -0,0 +1,62 @@
> +* Xilinx AXI PCIe Root Port Bridge DT description
> +
> +Required properties:
> +- #address-cells: Address representation for root ports, set to <3>
> +- #size-cells: Size representation for root ports, set to <2>
> +- #interrupt-cells: specifies the number of cells needed to encode an
> + interrupt source. The value must be 1.
> +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
> +- reg: Should contain AXI PCIe registers location and length
> +- device_type: must be "pci"
> +- interrupts: Should contain AXI PCIe interrupt
> +- interrupt-map-mask,
> + interrupt-map: standard PCI properties to define the mapping of the
> + PCI interface to interrupt numbers.
> +- ranges: ranges for the PCI memory regions (I/O space region is noti
> + supported by hardware)
> + Please refer to the standard PCI bus binding document for a more
> + detailed explanation
> +
> +Optional properties:
> +- bus-range: PCI bus numbers covered
> +
> +Interrupt controller child node
>
> +Required properties:
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #address-cells: specifies the number of cells needed to encode an
> + address. The value must be 0.
> +- #interrupt-cells: specifies the number of cells needed to encode an
> + interrupt source. The value must be 1.
> +
> +NOTE:
> +The core provides a single interrupt for both INTx/MSI messages. So,
> +created a interrupt controller node to support 'interrupt-map' DT
> +functionality. The driver will create an IRQ domain for this map, decode
> +the four INTx interrupts in ISR and route them to this domain.
> +
> +
> +Example:
> +
> +
> + pci_express: axi-pcie@5000 {
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + compatible = "xlnx,axi-pcie-host-1.00.a";
> + reg = < 0x5000 0x1000 >;
> + device_type = "pci";
> + interrupts = < 0 52 4 >;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 _intc 1>,
> + <0 0 0 2 _intc 2>,
> + <0 0 0 3 _intc 3>,
> + <0 0 0 4 _intc 4>;
> + ranges = < 0x0200 0 0x6000 0x6000 0 0x1000 >;
> +
> + pcie_intc: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + }
> + };
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index a6f67ec..71afdcd 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -33,4 +33,11 @@ config PCI_RCAR_GEN2
> There are 3 internal PCI controllers a
Re: [PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
Hi,
Kindly review the driver and please let me know if you have any comments.
Thanks
Srikanth
On Tue, Apr 15, 2014 at 5:08 PM, Srikanth Thokala stho...@xilinx.com wrote:
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 999
4 files changed, 1069 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..2fb28e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is noti
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = 3;
+ #size-cells = 2;
+ #interrupt-cells = 1;
+ compatible = xlnx,axi-pcie-host-1.00.a;
+ reg = 0x5000 0x1000 ;
+ device_type = pci;
+ interrupts = 0 52 4 ;
+ interrupt-map-mask = 0 0 0 7;
+ interrupt-map = 0 0 0 1 pcie_intc 1,
+ 0 0 0 2 pcie_intc 2,
+ 0 0 0 3 pcie_intc 3,
+ 0 0 0 4 pcie_intc 4;
+ ranges = 0x0200 0 0x6000 0x6000 0 0x1000 ;
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 1;
+ }
+ };
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a6f67ec..71afdcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,11 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
+config PCI_XILINX
+ bool Xilinx AXI PCIe host bridge support
+ depends on ARCH_ZYNQ
+ help
+ Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
+ Host Bridge driver.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..4e9c843 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj
[PATCH v8 1/2] dma: Add Xilinx Video DMA DT Binding Documentation
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Acked-by: Rob Herring r...@kernel.org
---
Changes in v8:
Fixed typos as suggested by Rob, Thanks.
Changes in v7:
None
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2:
- Removed device-id DT property, as suggested by Arnd Bergmann
- Properly documented DT bindings as suggested by Arnd Bergmann
---
.../devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 75
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
new file mode 100644
index 000..264100c
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
@@ -0,0 +1,75 @@
+Xilinx AXI VDMA engine, it does transfers between memory and video devices.
+It can be configured to have one channel or two channels. If configured
+as two channels, one is to transmit to the video device and another is
+to receive from the video device.
+
+Required properties:
+- compatible: Should be xlnx,axi-vdma-1.00.a
+- #dma-cells: Should be 1, see dmas property below
+- reg: Should contain VDMA registers location and length.
+- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
+- dma-channel child node: Should have at least one channel and can have up to
+ two channels per device. This node specifies the properties of each
+ DMA channel (see child node properties below).
+
+Optional properties:
+- xlnx,include-sg: Tells configured for Scatter-mode in
+ the hardware.
+- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
+ It takes following values:
+ {1}, flush both channels
+ {2}, flush mm2s channel
+ {3}, flush s2mm channel
+
+Required child node properties:
+- compatible: It should be either xlnx,axi-vdma-mm2s-channel or
+ xlnx,axi-vdma-s2mm-channel.
+- interrupts: Should contain per channel VDMA interrupts.
+- xlnx,data-width: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Optional child node properties:
+- xlnx,include-dre: Tells hardware is configured for Data
+ Realignment Engine.
+- xlnx,genlock-mode: Tells Genlock synchronization is
+ enabled/disabled in hardware.
+
+Example:
+
+
+axi_vdma_0: axivdma@4003 {
+ compatible = xlnx,axi-vdma-1.00.a;
+ #dma_cells = 1;
+ reg = 0x4003 0x1 ;
+ xlnx,num-fstores = 0x8;
+ xlnx,flush-fsync = 0x1;
+ dma-channel@4003 {
+ compatible = xlnx,axi-vdma-mm2s-channel;
+ interrupts = 0 54 4 ;
+ xlnx,datawidth = 0x40;
+ } ;
+ dma-channel@40030030 {
+ compatible = xlnx,axi-vdma-s2mm-channel;
+ interrupts = 0 53 4 ;
+ xlnx,datawidth = 0x40;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of [Video DMA device phandle] [Channel ID] pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per dmas entry
+
+Example:
+
+
+vdmatest_0: vdmatest@0 {
+ compatible =xlnx,axi-vdma-test-1.00.a;
+ dmas = axi_vdma_0 0
+ axi_vdma_0 1;
+ dma-names = vdma0, vdma1;
+} ;
--
1.7.9.5
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 2/2] dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
This is the driver for the AXI Video Direct Memory Access (AXI VDMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. The core provides efficient two dimensional DMA operations with independent asynchronous read and write channel operation. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala stho...@xilinx.com Acked-by: Jassi Brar jassisinghb...@gmail.com Reviewed-by: Levente Kurusa le...@linux.com --- NOTE: - Created a separate directory 'dma/xilinx' as Xilinx has two more DMA IPs and we are also planning to upstream these drivers soon. - This driver enables us to start pushing our media driver. Changes in v8: - Removed unnecessary cookie initialization as it is done by dma_cookie_assign() as suggested by Vinod, Thanks. Changes in v7: - Corrected the function description name of interleaved_dma API, as suggested by Jaswinder, Thanks. - Modified is_idle and is_running APIs to return 'bool'. Changes in v6: - Used is_slave_direction() API, as suggested by Andy, Thanks. - Moved the dev_info to end of probe() to indicate the probe is successful as suggested by Andy, Thanks. Changes in v5: - Modified to accept only 1 frame per interleaved_dma() call, as suggested by Jaswinder, Thanks. Changes in v4: - Created a separate function for the IP specific configuration instead of embedding the driver specific configuration into generic structure 'dma_slave_config', as suggested by Lars, Thanks. - Reverted the changes that were done in the earlier patch series, 1/3: 'Support multiple interleaved frames with non-contiguous memory' and accordingly made changes to support SG and non-SG Mode, as suggested by Jaswinder, Thanks. Changes in v3: - Implemented interleaved DMA API as suggested by Vinod and Lars, Thanks. - Use dma_slave_config generic API as suggested by Vinod and Lars, Thanks. - Simplified cookie implementation as sugguested by Vinod, Thanks. - Simplified *_xlate function by using dma_get_slave_channel() as suggested by Lars, Thanks. - Proper indentation of constants and maintained same multi-line of comments as suggested by Andy Shevchenko, Thanks. - Modified to use request_irq() instead of devm_request_irq as suggested by Lars, Thanks. - Fixed minor comments suggested by Andy and Levente, Thanks. Changes in v2: - Removed DMA Test client module from the patchset as suggested by Andy Shevchenko - Returning with error, if registration of DMA to node fails - Fixed typo errors - Used BIT() macro at applicable places - Added missing header file to the patchset - Changed copyright year to include 2014 --- drivers/dma/Kconfig | 14 + drivers/dma/Makefile |1 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_vdma.c | 1379 ++ include/linux/amba/xilinx_dma.h | 47 ++ 5 files changed, 1442 insertions(+) create mode 100644 drivers/dma/xilinx/Makefile create mode 100644 drivers/dma/xilinx/xilinx_vdma.c create mode 100644 include/linux/amba/xilinx_dma.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index ba06d1d..8257ffd 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -361,6 +361,20 @@ config FSL_EDMA multiplexing capability for DMA request sources(slot). This module can be found on Freescale Vybrid and LS-1 SoCs. +config XILINX_VDMA + tristate Xilinx AXI VDMA Engine + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI VDMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream video type target + peripherals including peripherals which support AXI4- + Stream Video Protocol. It has two stream interfaces/ + channels, Memory Mapped to Stream (MM2S) and Stream to + Memory Mapped (S2MM) for the data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 5150c82..c779e1e 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -46,3 +46,4 @@ obj-$(CONFIG_K3_DMA) += k3dma.o obj-$(CONFIG_MOXART_DMA) += moxart-dma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o +obj-y += xilinx/ diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile new file mode 100644 index 000..3c4e9f2 --- /dev/null +++ b/drivers/dma/xilinx/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o diff --git a/drivers/dma/xilinx/xilinx_vdma.c b/drivers/dma/xilinx/xilinx_vdma.c new file mode 100644 index 000..42a13e8 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_vdma.c @@ -0,0 +1,1379 @@ +/* + * DMA driver for Xilinx Video DMA Engine + * + * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver
Re: [PATCH v2 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
On Wed, Apr 16, 2014 at 5:01 PM, Vinod Koul wrote: > On Tue, Apr 01, 2014 at 05:57:04PM +0530, Srikanth Thokala wrote: >> This is the driver for the AXI Direct Memory Access (AXI DMA) >> core, which is a soft Xilinx IP core that provides high- >> bandwidth direct memory access between memory and AXI4-Stream >> type target peripherals. >> >> This module works on Zynq (ARM Based SoC) and Microblaze platforms. >> >> Signed-off-by: Srikanth Thokala >> --- >> Note: >> - This driver patch is created on top of earlier series, >> 1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation" >> 2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver >> support" >> - Rebased on v3.14.0-rc8 >> >> Changes in v2: >> - Simplified the logic to set SOP and APP words in prep_slave_sg(). >> - Corrected function description comments to match the return type. >> - Fixed some minor comments as suggested by Andy, Thanks. >> --- >> drivers/dma/Kconfig | 13 + >> drivers/dma/xilinx/Makefile |1 + >> drivers/dma/xilinx/xilinx_dma.c | 1225 >> +++ >> include/linux/amba/xilinx_dma.h | 17 + >> 4 files changed, 1256 insertions(+) >> create mode 100644 drivers/dma/xilinx/xilinx_dma.c >> >> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig >> index 44b312e..8cfcc74 100644 >> --- a/drivers/dma/Kconfig >> +++ b/drivers/dma/Kconfig >> @@ -365,6 +365,19 @@ config XILINX_VDMA >> channels, Memory Mapped to Stream (MM2S) and Stream to >> Memory Mapped (S2MM) for the data transfers. >> >> +config XILINX_DMA >> + tristate "Xilinx AXI DMA Engine" >> + depends on (ARCH_ZYNQ || MICROBLAZE) >> + select DMA_ENGINE >> + help >> + Enable support for Xilinx AXI DMA Soft IP. >> + >> + This engine provides high-bandwidth direct memory access >> + between memory and AXI4-Stream type target peripherals. >> + It has two stream interfaces/channels, Memory Mapped to >> + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the >> + data transfers. >> + >> config DMA_ENGINE >> bool >> >> diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile >> index 3c4e9f2..6224a49 100644 >> --- a/drivers/dma/xilinx/Makefile >> +++ b/drivers/dma/xilinx/Makefile >> @@ -1 +1,2 @@ >> obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o >> +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o >> diff --git a/drivers/dma/xilinx/xilinx_dma.c >> b/drivers/dma/xilinx/xilinx_dma.c >> new file mode 100644 >> index 000..0500773 >> --- /dev/null >> +++ b/drivers/dma/xilinx/xilinx_dma.c >> @@ -0,0 +1,1225 @@ >> +/* >> + * DMA driver for Xilinx DMA Engine >> + * >> + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. >> + * >> + * Based on the Freescale DMA driver. >> + * >> + * Description: >> + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory >> + * Access between memory and AXI4-Stream-type target peripherals. It can be >> + * configured to have one channel or two channels and if configured as two >> + * channels, one is to transmit data from memory to a device and another is >> + * to receive from a device. >> + * >> + * This program is free software: you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation, either version 2 of the License, or >> + * (at your option) any later version. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "../dmaengine.h" >> + >> +/* Register Offsets */ >> +#define XILINX_DMA_REG_CONTROL 0x00 >> +#define XILINX_DMA_REG_STATUS0x04 >> +#define XILINX_DMA_REG_CURDESC 0x08 >> +#define XILINX_DMA_REG_TAILDESC 0x10 >> +#define XILINX_DMA_REG_SRCADDR 0x18 >> +#define XILINX_DMA_REG_DSTADDR 0x20 >> +#define XILINX_DMA_REG_BTT 0x28 >> + >> +/* Channel/Descriptor Offsets */ >> +#define XILINX_DMA_MM2S_CTRL_OFFSET 0x00 >> +#define XILINX_DMA_S2MM_CTRL_OFFSET 0x30 >> + >> +/* General register bits definitions */ >> +#de
Re: [PATCH v2 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
On Wed, Apr 16, 2014 at 5:01 PM, Vinod Koul vinod.k...@intel.com wrote: On Tue, Apr 01, 2014 at 05:57:04PM +0530, Srikanth Thokala wrote: This is the driver for the AXI Direct Memory Access (AXI DMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type target peripherals. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala stho...@xilinx.com --- Note: - This driver patch is created on top of earlier series, 1/2 - dma: Add Xilinx Video DMA DT Binding Documentation 2/2 - dma: Add Xilinx AXI Video Direct Memory Access Engine driver support - Rebased on v3.14.0-rc8 Changes in v2: - Simplified the logic to set SOP and APP words in prep_slave_sg(). - Corrected function description comments to match the return type. - Fixed some minor comments as suggested by Andy, Thanks. --- drivers/dma/Kconfig | 13 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_dma.c | 1225 +++ include/linux/amba/xilinx_dma.h | 17 + 4 files changed, 1256 insertions(+) create mode 100644 drivers/dma/xilinx/xilinx_dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 44b312e..8cfcc74 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -365,6 +365,19 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_DMA + tristate Xilinx AXI DMA Engine + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI DMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream type target peripherals. + It has two stream interfaces/channels, Memory Mapped to + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the + data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..6224a49 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c new file mode 100644 index 000..0500773 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -0,0 +1,1225 @@ +/* + * DMA driver for Xilinx DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access between memory and AXI4-Stream-type target peripherals. It can be + * configured to have one channel or two channels and if configured as two + * channels, one is to transmit data from memory to a device and another is + * to receive from a device. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include linux/amba/xilinx_dma.h +#include linux/bitops.h +#include linux/init.h +#include linux/interrupt.h +#include linux/io.h +#include linux/module.h +#include linux/of_address.h +#include linux/of_dma.h +#include linux/of_irq.h +#include linux/of_platform.h +#include linux/slab.h + +#include ../dmaengine.h + +/* Register Offsets */ +#define XILINX_DMA_REG_CONTROL 0x00 +#define XILINX_DMA_REG_STATUS0x04 +#define XILINX_DMA_REG_CURDESC 0x08 +#define XILINX_DMA_REG_TAILDESC 0x10 +#define XILINX_DMA_REG_SRCADDR 0x18 +#define XILINX_DMA_REG_DSTADDR 0x20 +#define XILINX_DMA_REG_BTT 0x28 + +/* Channel/Descriptor Offsets */ +#define XILINX_DMA_MM2S_CTRL_OFFSET 0x00 +#define XILINX_DMA_S2MM_CTRL_OFFSET 0x30 + +/* General register bits definitions */ +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_DMA_CR_RESET_MASK BIT(2) + +#define XILINX_DMA_CR_DELAY_SHIFT24 +#define XILINX_DMA_CR_COALESCE_SHIFT 16 + +#define XILINX_DMA_CR_DELAY_MAX GENMASK(7, 0) +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) + +#define XILINX_DMA_SR_HALTED_MASKBIT(0) +#define XILINX_DMA_SR_IDLE_MASK BIT(1) + +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) + +/* BD definitions */ +#define XILINX_DMA_BD_STS_ALL_MASK GENMASK(31, 28) +#define XILINX_DMA_BD_SOPBIT(27) +#define XILINX_DMA_BD_EOPBIT(26) + +/* Hw
Re: [PATCH v7 2/2] dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
On Wed, Apr 16, 2014 at 3:56 PM, Vinod Koul wrote:
> On Wed, Apr 16, 2014 at 03:41:34PM +0530, Srikanth Thokala wrote:
>> On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul wrote:
>> > On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
>> >> This is the driver for the AXI Video Direct Memory Access (AXI
>> >> VDMA) core, which is a soft Xilinx IP core that provides high-
>> >> bandwidth direct memory access between memory and AXI4-Stream
>> >> type video target peripherals. The core provides efficient two
>> >> dimensional DMA operations with independent asynchronous read
>> >> and write channel operation.
>> >>
>> >> This module works on Zynq (ARM Based SoC) and Microblaze platforms.
>> >
>> > Okay the series is fine and was going to apply it BUT
>> > 1) need ack on DT patch..
>> > 2) issues below on managing the descriptor and resetting the cookie :(
>>
>> Ok.
>>
>> >
>> >> +
>> >> +/**
>> >> + * xilinx_vdma_tx_descriptor - Allocate transaction descriptor
>> >> + * @chan: Driver specific VDMA channel
>> >> + *
>> >> + * Return: The allocated descriptor on success and NULL on failure.
>> >> + */
>> >> +static struct xilinx_vdma_tx_descriptor *
>> >> +xilinx_vdma_alloc_tx_descriptor(struct xilinx_vdma_chan *chan)
>> >> +{
>> >> + struct xilinx_vdma_tx_descriptor *desc;
>> >> + unsigned long flags;
>> >> +
>> >> + if (chan->allocated_desc)
>> >> + return chan->allocated_desc;
>> > ??
>> >
>> >> +
>> >> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> >> + if (!desc)
>> >> + return NULL;
>> >> +
>> >> + spin_lock_irqsave(>lock, flags);
>> >> + chan->allocated_desc = desc;
>> > ah why do you need this?
>> >
>> > So this essentailly prevents you from preparing two trasactions at same
>> > time as
>> > you would overwrite??
>>
>> This will allow to queue up multiple segments on to a single
>> transaction descriptor.
>> User will submit this single desc and in the issue_pending() we decode
>> multiple
>> segments and submit to SG HW engine. We free up the allocated_desc when it
>> is
>> submitted to the HW. This is added after my discussion with Jaswinder, to
>> best
>> utilize HW SG engine.
>
> I think best utilization of HW SG engine would happen if we collate the
> pending
> list when you start dma
Is that ok if I revisit this code as an enhancement at a later time?
Srikanth
>
> --
> ~Vinod
> --
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Re: [PATCH v7 2/2] dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul wrote:
> On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Video Direct Memory Access (AXI
>> VDMA) core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct memory access between memory and AXI4-Stream
>> type video target peripherals. The core provides efficient two
>> dimensional DMA operations with independent asynchronous read
>> and write channel operation.
>>
>> This module works on Zynq (ARM Based SoC) and Microblaze platforms.
>
> Okay the series is fine and was going to apply it BUT
> 1) need ack on DT patch..
> 2) issues below on managing the descriptor and resetting the cookie :(
Ok.
>
>> +
>> +/**
>> + * xilinx_vdma_tx_descriptor - Allocate transaction descriptor
>> + * @chan: Driver specific VDMA channel
>> + *
>> + * Return: The allocated descriptor on success and NULL on failure.
>> + */
>> +static struct xilinx_vdma_tx_descriptor *
>> +xilinx_vdma_alloc_tx_descriptor(struct xilinx_vdma_chan *chan)
>> +{
>> + struct xilinx_vdma_tx_descriptor *desc;
>> + unsigned long flags;
>> +
>> + if (chan->allocated_desc)
>> + return chan->allocated_desc;
> ??
>
>> +
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return NULL;
>> +
>> + spin_lock_irqsave(>lock, flags);
>> + chan->allocated_desc = desc;
> ah why do you need this?
>
> So this essentailly prevents you from preparing two trasactions at same time
> as
> you would overwrite??
This will allow to queue up multiple segments on to a single
transaction descriptor.
User will submit this single desc and in the issue_pending() we decode multiple
segments and submit to SG HW engine. We free up the allocated_desc when it is
submitted to the HW. This is added after my discussion with Jaswinder, to best
utilize HW SG engine.
>
> You should maintain a list for pending and submitted.
Yes, we maintain two lists pending_list and done_list.
>
>> + spin_unlock_irqrestore(>lock, flags);
>> +
>> + INIT_LIST_HEAD(>segments);
>> +
>> + return desc;
>> +}
>> +
>
>> +/**
>> + * xilinx_vdma_tx_submit - Submit DMA transaction
>> + * @tx: Async transaction descriptor
>> + *
>> + * Return: cookie value on success and failure value on error
>> + */
>> +static dma_cookie_t xilinx_vdma_tx_submit(struct dma_async_tx_descriptor
>> *tx)
>> +{
>> + struct xilinx_vdma_tx_descriptor *desc = to_vdma_tx_descriptor(tx);
>> + struct xilinx_vdma_chan *chan = to_xilinx_chan(tx->chan);
>> + dma_cookie_t cookie;
>> + unsigned long flags;
>> + int err;
>> +
>> + if (chan->err) {
>> + /*
>> + * If reset fails, need to hard reset the system.
>> + * Channel is no longer functional
>> + */
>> + err = xilinx_vdma_chan_reset(chan);
>> + if (err < 0)
>> + return err;
>> + }
>> +
>> + spin_lock_irqsave(>lock, flags);
>> +
>> + cookie = dma_cookie_assign(tx);
>> +
>> + /* Append the transaction to the pending transactions queue. */
>> + list_add_tail(>node, >pending_list);
>> +
>> + /* Free the allocated desc */
>> + chan->allocated_desc = NULL;
>> +
>> + spin_unlock_irqrestore(>lock, flags);
>> +
>> + return cookie;
>> +}
>> +
>> +/**
>> + * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
>> + * DMA_SLAVE transaction
>> + * @dchan: DMA channel
>> + * @xt: Interleaved template pointer
>> + * @flags: transfer ack flags
>> + *
>> + * Return: Async transaction descriptor on success and NULL on failure
>> + */
>> +static struct dma_async_tx_descriptor *
>> +xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
>> + struct dma_interleaved_template *xt,
>> + unsigned long flags)
>> +{
>> + struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
>> + struct xilinx_vdma_tx_descriptor *desc;
>> + struct xilinx_vdma_tx_segment *segment, *prev = NULL;
>> + struct xilinx_vdma_desc_hw *hw;
>> +
>> + if (!is_slave_direction(xt->dir))
>> + return NULL;
>> +
>> + if (!xt->numf || !xt->sgl[0].size)
>> + return NULL;
>> +
>>
Re: [PATCH v7 2/2] dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul vinod.k...@intel.com wrote:
On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
This is the driver for the AXI Video Direct Memory Access (AXI
VDMA) core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type video target peripherals. The core provides efficient two
dimensional DMA operations with independent asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Okay the series is fine and was going to apply it BUT
1) need ack on DT patch..
2) issues below on managing the descriptor and resetting the cookie :(
Ok.
+
+/**
+ * xilinx_vdma_tx_descriptor - Allocate transaction descriptor
+ * @chan: Driver specific VDMA channel
+ *
+ * Return: The allocated descriptor on success and NULL on failure.
+ */
+static struct xilinx_vdma_tx_descriptor *
+xilinx_vdma_alloc_tx_descriptor(struct xilinx_vdma_chan *chan)
+{
+ struct xilinx_vdma_tx_descriptor *desc;
+ unsigned long flags;
+
+ if (chan-allocated_desc)
+ return chan-allocated_desc;
??
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return NULL;
+
+ spin_lock_irqsave(chan-lock, flags);
+ chan-allocated_desc = desc;
ah why do you need this?
So this essentailly prevents you from preparing two trasactions at same time
as
you would overwrite??
This will allow to queue up multiple segments on to a single
transaction descriptor.
User will submit this single desc and in the issue_pending() we decode multiple
segments and submit to SG HW engine. We free up the allocated_desc when it is
submitted to the HW. This is added after my discussion with Jaswinder, to best
utilize HW SG engine.
You should maintain a list for pending and submitted.
Yes, we maintain two lists pending_list and done_list.
+ spin_unlock_irqrestore(chan-lock, flags);
+
+ INIT_LIST_HEAD(desc-segments);
+
+ return desc;
+}
+
+/**
+ * xilinx_vdma_tx_submit - Submit DMA transaction
+ * @tx: Async transaction descriptor
+ *
+ * Return: cookie value on success and failure value on error
+ */
+static dma_cookie_t xilinx_vdma_tx_submit(struct dma_async_tx_descriptor
*tx)
+{
+ struct xilinx_vdma_tx_descriptor *desc = to_vdma_tx_descriptor(tx);
+ struct xilinx_vdma_chan *chan = to_xilinx_chan(tx-chan);
+ dma_cookie_t cookie;
+ unsigned long flags;
+ int err;
+
+ if (chan-err) {
+ /*
+ * If reset fails, need to hard reset the system.
+ * Channel is no longer functional
+ */
+ err = xilinx_vdma_chan_reset(chan);
+ if (err 0)
+ return err;
+ }
+
+ spin_lock_irqsave(chan-lock, flags);
+
+ cookie = dma_cookie_assign(tx);
+
+ /* Append the transaction to the pending transactions queue. */
+ list_add_tail(desc-node, chan-pending_list);
+
+ /* Free the allocated desc */
+ chan-allocated_desc = NULL;
+
+ spin_unlock_irqrestore(chan-lock, flags);
+
+ return cookie;
+}
+
+/**
+ * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
+ * DMA_SLAVE transaction
+ * @dchan: DMA channel
+ * @xt: Interleaved template pointer
+ * @flags: transfer ack flags
+ *
+ * Return: Async transaction descriptor on success and NULL on failure
+ */
+static struct dma_async_tx_descriptor *
+xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
+ struct dma_interleaved_template *xt,
+ unsigned long flags)
+{
+ struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
+ struct xilinx_vdma_tx_descriptor *desc;
+ struct xilinx_vdma_tx_segment *segment, *prev = NULL;
+ struct xilinx_vdma_desc_hw *hw;
+
+ if (!is_slave_direction(xt-dir))
+ return NULL;
+
+ if (!xt-numf || !xt-sgl[0].size)
+ return NULL;
+
+ /* Allocate a transaction descriptor. */
+ desc = xilinx_vdma_alloc_tx_descriptor(chan);
+ if (!desc)
+ return NULL;
+
+ dma_async_tx_descriptor_init(desc-async_tx, chan-common);
+ desc-async_tx.tx_submit = xilinx_vdma_tx_submit;
+ desc-async_tx.cookie = 0;
why this is initialized in submit.. when you call dma_cookie_assign()
This is while preparing the descs, but I see your point. I will fix
it in my next version.
Srikanth
--
~Vinod
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Re: [PATCH v7 2/2] dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
On Wed, Apr 16, 2014 at 3:56 PM, Vinod Koul vinod.k...@intel.com wrote:
On Wed, Apr 16, 2014 at 03:41:34PM +0530, Srikanth Thokala wrote:
On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul vinod.k...@intel.com wrote:
On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
This is the driver for the AXI Video Direct Memory Access (AXI
VDMA) core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type video target peripherals. The core provides efficient two
dimensional DMA operations with independent asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Okay the series is fine and was going to apply it BUT
1) need ack on DT patch..
2) issues below on managing the descriptor and resetting the cookie :(
Ok.
+
+/**
+ * xilinx_vdma_tx_descriptor - Allocate transaction descriptor
+ * @chan: Driver specific VDMA channel
+ *
+ * Return: The allocated descriptor on success and NULL on failure.
+ */
+static struct xilinx_vdma_tx_descriptor *
+xilinx_vdma_alloc_tx_descriptor(struct xilinx_vdma_chan *chan)
+{
+ struct xilinx_vdma_tx_descriptor *desc;
+ unsigned long flags;
+
+ if (chan-allocated_desc)
+ return chan-allocated_desc;
??
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return NULL;
+
+ spin_lock_irqsave(chan-lock, flags);
+ chan-allocated_desc = desc;
ah why do you need this?
So this essentailly prevents you from preparing two trasactions at same
time as
you would overwrite??
This will allow to queue up multiple segments on to a single
transaction descriptor.
User will submit this single desc and in the issue_pending() we decode
multiple
segments and submit to SG HW engine. We free up the allocated_desc when it
is
submitted to the HW. This is added after my discussion with Jaswinder, to
best
utilize HW SG engine.
I think best utilization of HW SG engine would happen if we collate the
pending
list when you start dma
Is that ok if I revisit this code as an enhancement at a later time?
Srikanth
--
~Vinod
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
--
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[PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
"PCI: ARM: add support for generic PCI host controller"
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 999
4 files changed, 1069 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..2fb28e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be "pci"
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is noti
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ reg = < 0x5000 0x1000 >;
+ device_type = "pci";
+ interrupts = < 0 52 4 >;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 _intc 1>,
+ <0 0 0 2 _intc 2>,
+ <0 0 0 3 _intc 3>,
+ <0 0 0 4 _intc 4>;
+ ranges = < 0x0200 0 0x6000 0x6000 0 0x1000 >;
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ }
+ };
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a6f67ec..71afdcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,11 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
+config PCI_XILINX
+ bool "Xilinx AXI PCIe host bridge support"
+ depends on ARCH_ZYNQ
+ help
+ Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
+ Host Bridge driver.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..4e9c843 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+
[PATCH v3] pcie: Add Xilinx PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
PCI: ARM: add support for generic PCI host controller
- Modified devicetree binding documentation to update with interrupt-
map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.
Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 62 ++
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile |1 +
drivers/pci/host/pci-xilinx.c | 999
4 files changed, 1069 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
create mode 100644 drivers/pci/host/pci-xilinx.c
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000..2fb28e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain xlnx,axi-pcie-host-1.00.a
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be pci
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is noti
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+Optional properties:
+- bus-range: PCI bus numbers covered
+
+Interrupt controller child node
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+ address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality. The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+
+
+Example:
+
+
+ pci_express: axi-pcie@5000 {
+ #address-cells = 3;
+ #size-cells = 2;
+ #interrupt-cells = 1;
+ compatible = xlnx,axi-pcie-host-1.00.a;
+ reg = 0x5000 0x1000 ;
+ device_type = pci;
+ interrupts = 0 52 4 ;
+ interrupt-map-mask = 0 0 0 7;
+ interrupt-map = 0 0 0 1 pcie_intc 1,
+ 0 0 0 2 pcie_intc 2,
+ 0 0 0 3 pcie_intc 3,
+ 0 0 0 4 pcie_intc 4;
+ ranges = 0x0200 0 0x6000 0x6000 0 0x1000 ;
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 1;
+ }
+ };
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a6f67ec..71afdcd 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,11 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
+config PCI_XILINX
+ bool Xilinx AXI PCIe host bridge support
+ depends on ARCH_ZYNQ
+ help
+ Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
+ Host Bridge driver.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..4e9c843 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+obj-$(CONFIG_PCI_XILINX) += pci-xilinx.o
diff --git a/drivers/pci/host/pci-xilinx.c b/drivers/pci/host/pci-xilinx.c
new file mode 100644
index 000..d9afe66
Re: [PATCH 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support
Hi Jonathan,
On Tue, Apr 8, 2014 at 8:14 PM, Jonathan Corbet wrote:
> On Mon, 7 Apr 2014 20:22:54 +0530
> Srikanth Thokala wrote:
>
>> Kindly review this driver and please let me know if you have any comments.
>
> Here's some comments from a quick look at the patch; they do not qualify as
> a proper review by any means.
>
>> +/**
>> + * struct xilinx_cdma_chan - Driver specific cdma channel structure
>> + * @xdev: Driver specific device structure
>> + * @lock: Descriptor operation lock
>> + * @done_list: Complete descriptors
>> + * @pending_list: Descriptors waiting
>> + * @active_desc: Active descriptor
>> + * @allocated_desc: Allocated descriptor
>> + * @common: DMA common channel
>> + * @desc_pool: Descriptors pool
>> + * @dev: The dma device
>> + * @irq: Channel IRQ
>> + * @has_sg: Support scatter transfers
>> + * @err: Channel has errors
>> + * @tasklet: Cleanup work after irq
>> + */
>> +struct xilinx_cdma_chan {
>> + struct xilinx_cdma_device *xdev;
>> + spinlock_t lock;
>> + struct list_head done_list;
>> + struct list_head pending_list;
>> + struct xilinx_cdma_tx_descriptor *active_desc;
>> + struct xilinx_cdma_tx_descriptor *allocated_desc;
>> + struct dma_chan common;
>> + struct dma_pool *desc_pool;
>> + struct device *dev;
>> + int irq;
>> + bool has_sg;
>> + int err;
>> + struct tasklet_struct tasklet;
>> +};
>
> Have you thought about using a threaded IRQ handler instead of a tasklet?
> The tasklet interface has its pitfalls and some reviewers frown on the
> addition of more users.
Ok, I see. I will add it to my list and send this change as a patch on top of
this driver. Thanks.
>
> [...]
>
>> +/**
>> + * xilinx_cdma_tx_descriptor - Allocate transaction descriptor
>> + * @chan: Driver specific cdma channel
>> + *
>> + * Return: The allocated descriptor on success and NULL on failure.
>> + */
>> +static struct xilinx_cdma_tx_descriptor *
>> +xilinx_cdma_alloc_tx_descriptor(struct xilinx_cdma_chan *chan)
>> +{
>> + struct xilinx_cdma_tx_descriptor *desc;
>> + unsigned long flags;
>> +
>> + if (chan->allocated_desc)
>> + return chan->allocated_desc;
>
> This looks racy. What happens if two threads hit here at once, or, in
> general, some other thread does something with chan->allocated_desc?
>
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return NULL;
>> +
>> + spin_lock_irqsave(>lock, flags);
>> + chan->allocated_desc = desc;
>> + spin_unlock_irqrestore(>lock, flags);
>> +
>> + INIT_LIST_HEAD(>segments);
>
> Using the lock to protect a single assignment doesn't really buy you much;
> it's what is going on outside of the locked region that is going to bite
> you.
>
> Also, as soon as you do that assignment, desc is visible to the rest of the
> world. Somebody else could try to use it before you get around to that
> INIT_LIST_HEAD() call, with unpleasant results. You really need a lock
> around the whole test/allocate/initialize operation.
Ok.
>
>> + return desc;
>> +}
>> +
>> +/**
>> + * xilinx_cdma_free_tx_descriptor - Free transaction descriptor
>> + * @chan: Driver specific cdma channel
>> + * @desc: cdma transaction descriptor
>> + */
>> +static void
>> +xilinx_cdma_free_tx_descriptor(struct xilinx_cdma_chan *chan,
>> + struct xilinx_cdma_tx_descriptor *desc)
>> +{
>> + struct xilinx_cdma_tx_segment *segment, *next;
>> +
>> + if (!desc)
>> + return;
>> +
>> + list_for_each_entry_safe(segment, next, >segments, node) {
>> + list_del(>node);
>> + xilinx_cdma_free_tx_segment(chan, segment);
>> + }
>> +
>> + kfree(desc);
>> +}
>
> What are the locking requirements for this function? It looks from a
> casual reading like some callers hold the spinlock while others do not. It
> would be good to sort out (and document!) the requirement here.
Ok sure, I will document them.
>
>> +/**
>> + * xilinx_cdma_free_chan_resources - Free channel resources
>> + * @dchan: DMA channel
>> + */
>> +static void xilinx_cdma_free_chan_resources(struct dma_chan *dchan)
>> +{
>> + struct xilinx_cdma_chan *chan = to_xilinx_chan(dchan);
>> + unsigned long flags;
Re: [PATCH 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support
Hi Jonathan,
On Tue, Apr 8, 2014 at 8:14 PM, Jonathan Corbet cor...@lwn.net wrote:
On Mon, 7 Apr 2014 20:22:54 +0530
Srikanth Thokala stho...@xilinx.com wrote:
Kindly review this driver and please let me know if you have any comments.
Here's some comments from a quick look at the patch; they do not qualify as
a proper review by any means.
+/**
+ * struct xilinx_cdma_chan - Driver specific cdma channel structure
+ * @xdev: Driver specific device structure
+ * @lock: Descriptor operation lock
+ * @done_list: Complete descriptors
+ * @pending_list: Descriptors waiting
+ * @active_desc: Active descriptor
+ * @allocated_desc: Allocated descriptor
+ * @common: DMA common channel
+ * @desc_pool: Descriptors pool
+ * @dev: The dma device
+ * @irq: Channel IRQ
+ * @has_sg: Support scatter transfers
+ * @err: Channel has errors
+ * @tasklet: Cleanup work after irq
+ */
+struct xilinx_cdma_chan {
+ struct xilinx_cdma_device *xdev;
+ spinlock_t lock;
+ struct list_head done_list;
+ struct list_head pending_list;
+ struct xilinx_cdma_tx_descriptor *active_desc;
+ struct xilinx_cdma_tx_descriptor *allocated_desc;
+ struct dma_chan common;
+ struct dma_pool *desc_pool;
+ struct device *dev;
+ int irq;
+ bool has_sg;
+ int err;
+ struct tasklet_struct tasklet;
+};
Have you thought about using a threaded IRQ handler instead of a tasklet?
The tasklet interface has its pitfalls and some reviewers frown on the
addition of more users.
Ok, I see. I will add it to my list and send this change as a patch on top of
this driver. Thanks.
[...]
+/**
+ * xilinx_cdma_tx_descriptor - Allocate transaction descriptor
+ * @chan: Driver specific cdma channel
+ *
+ * Return: The allocated descriptor on success and NULL on failure.
+ */
+static struct xilinx_cdma_tx_descriptor *
+xilinx_cdma_alloc_tx_descriptor(struct xilinx_cdma_chan *chan)
+{
+ struct xilinx_cdma_tx_descriptor *desc;
+ unsigned long flags;
+
+ if (chan-allocated_desc)
+ return chan-allocated_desc;
This looks racy. What happens if two threads hit here at once, or, in
general, some other thread does something with chan-allocated_desc?
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return NULL;
+
+ spin_lock_irqsave(chan-lock, flags);
+ chan-allocated_desc = desc;
+ spin_unlock_irqrestore(chan-lock, flags);
+
+ INIT_LIST_HEAD(desc-segments);
Using the lock to protect a single assignment doesn't really buy you much;
it's what is going on outside of the locked region that is going to bite
you.
Also, as soon as you do that assignment, desc is visible to the rest of the
world. Somebody else could try to use it before you get around to that
INIT_LIST_HEAD() call, with unpleasant results. You really need a lock
around the whole test/allocate/initialize operation.
Ok.
+ return desc;
+}
+
+/**
+ * xilinx_cdma_free_tx_descriptor - Free transaction descriptor
+ * @chan: Driver specific cdma channel
+ * @desc: cdma transaction descriptor
+ */
+static void
+xilinx_cdma_free_tx_descriptor(struct xilinx_cdma_chan *chan,
+ struct xilinx_cdma_tx_descriptor *desc)
+{
+ struct xilinx_cdma_tx_segment *segment, *next;
+
+ if (!desc)
+ return;
+
+ list_for_each_entry_safe(segment, next, desc-segments, node) {
+ list_del(segment-node);
+ xilinx_cdma_free_tx_segment(chan, segment);
+ }
+
+ kfree(desc);
+}
What are the locking requirements for this function? It looks from a
casual reading like some callers hold the spinlock while others do not. It
would be good to sort out (and document!) the requirement here.
Ok sure, I will document them.
+/**
+ * xilinx_cdma_free_chan_resources - Free channel resources
+ * @dchan: DMA channel
+ */
+static void xilinx_cdma_free_chan_resources(struct dma_chan *dchan)
+{
+ struct xilinx_cdma_chan *chan = to_xilinx_chan(dchan);
+ unsigned long flags;
+
+ spin_lock_irqsave(chan-lock, flags);
+ xilinx_cdma_free_desc_list(chan, chan-done_list);
+ xilinx_cdma_free_desc_list(chan, chan-pending_list);
+ spin_unlock_irqrestore(chan-lock, flags);
+
+ dma_pool_destroy(chan-desc_pool);
+ chan-desc_pool = NULL;
Why is this part done outside the lock?
I feel it is not required because we ensure no memory is used from pool
(by freeing up all the descriptors) before calling the pool_destroy() function.
+ */
+static void xilinx_cdma_chan_desc_cleanup(struct xilinx_cdma_chan *chan)
+{
+ struct xilinx_cdma_tx_descriptor *desc, *next;
+ unsigned long flags;
+
+ spin_lock_irqsave(chan-lock, flags);
+
+ list_for_each_entry_safe(desc, next, chan-done_list, node
Re: [PATCH 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support
Hi, Kindly review this driver and please let me know if you have any comments. Thanks Srikanth On Mon, Mar 31, 2014 at 7:24 PM, Srikanth Thokala wrote: > This is the driver for the AXI Central Direct Memory Access (AXI > CDMA) core, which is a soft Xilinx IP core that provides high-bandwidth > Direct Memory Access (DMA) between a memory-mapped source address and a > memory-mapped destination address. > > This module works on Zynq (ARM Based SoC) and Microblaze platforms. > > Signed-off-by: Srikanth Thokala > --- > NOTE: > - This driver patch is created on top of earlier series, > 1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation" > 2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support" > - Rebased on v3.14.0-rc8 > --- > drivers/dma/Kconfig | 12 + > drivers/dma/xilinx/Makefile |1 + > drivers/dma/xilinx/xilinx_cdma.c | 998 > ++ > include/linux/amba/xilinx_dma.h | 15 +- > 4 files changed, 1025 insertions(+), 1 deletion(-) > create mode 100644 drivers/dma/xilinx/xilinx_cdma.c > > diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig > index 44b312e..e2c5cf2 100644 > --- a/drivers/dma/Kconfig > +++ b/drivers/dma/Kconfig > @@ -365,6 +365,18 @@ config XILINX_VDMA > channels, Memory Mapped to Stream (MM2S) and Stream to > Memory Mapped (S2MM) for the data transfers. > > +config XILINX_CDMA > + tristate "Xilinx AXI CDMA Engine" > + depends on (ARCH_ZYNQ || MICROBLAZE) > + select DMA_ENGINE > + help > + Enable support for Xilinx AXI CDMA Soft IP. > + > + The AXI CDMA is a soft IP which provides high-bandwidth > + Direct Memory Access (DMA) between a memory-mapped source > + address and a memory-mapped destination address using the > + AXI4 protocol. > + > config DMA_ENGINE > bool > > diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile > index 3c4e9f2..e1dee77 100644 > --- a/drivers/dma/xilinx/Makefile > +++ b/drivers/dma/xilinx/Makefile > @@ -1 +1,2 @@ > obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o > +obj-$(CONFIG_XILINX_CDMA) += xilinx_cdma.o > diff --git a/drivers/dma/xilinx/xilinx_cdma.c > b/drivers/dma/xilinx/xilinx_cdma.c > new file mode 100644 > index 000..2ae7c77 > --- /dev/null > +++ b/drivers/dma/xilinx/xilinx_cdma.c > @@ -0,0 +1,998 @@ > +/* > + * DMA driver for Xilinx Central DMA Engine > + * > + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. > + * > + * Based on the Freescale DMA driver. > + * > + * Description: > + * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory > + * Access (DMA) between a memory-mapped source address and a memory-mapped > + * destination address. > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "../dmaengine.h" > + > +/* Register Offsets */ > +#define XILINX_CDMA_CONTROL_OFFSET 0x00 > +#define XILINX_CDMA_STATUS_OFFSET 0x04 > +#define XILINX_CDMA_CDESC_OFFSET 0x08 > +#define XILINX_CDMA_TDESC_OFFSET 0x10 > +#define XILINX_CDMA_SRCADDR_OFFSET 0x18 > +#define XILINX_CDMA_DSTADDR_OFFSET 0x20 > +#define XILINX_CDMA_BTT_OFFSET 0x28 > + > +/* General register bits definitions */ > +#define XILINX_CDMA_CR_RESET BIT(2) > +#define XILINX_CDMA_CR_SGMODE BIT(3) > + > +#define XILINX_CDMA_SR_IDLEBIT(1) > + > +#define XILINX_CDMA_XR_IRQ_IOC_MASKBIT(12) > +#define XILINX_CDMA_XR_IRQ_DELAY_MASK BIT(13) > +#define XILINX_CDMA_XR_IRQ_ERROR_MASK BIT(14) > +#define XILINX_CDMA_XR_IRQ_ALL_MASKGENMASK(14, 12) > + > +#define XILINX_CDMA_XR_DELAY_MASK GENMASK(31, 24) > +#define XILINX_CDMA_XR_COALESCE_MASK GENMASK(23, 16) > + > +#define XILINX_CDMA_DELAY_MAX GENMASK(7, 0) > +#define XILINX_CDMA_DELAY_SHIFT24 > + > +#define XILINX_CDMA_COALESCE_MAX GENMASK(7, 0) > +#define XILINX_CDMA_COALESCE_SHIFT 16 > + > +/* Delay loop counter to prevent hardware failure */ > +#define XILINX_CDMA_RESET_LOOP 100 > + > +/* Maximum transfer length */ > +#define XILINX_CDMA_MAX_TRANS_LEN GENMASK(22, 0) > + >
Re: [PATCH v2 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi, Kindly review this driver patch and please let me know if you have any comments. Srikanth On Tue, Apr 1, 2014 at 5:57 PM, Srikanth Thokala wrote: > This is the driver for the AXI Direct Memory Access (AXI DMA) > core, which is a soft Xilinx IP core that provides high- > bandwidth direct memory access between memory and AXI4-Stream > type target peripherals. > > This module works on Zynq (ARM Based SoC) and Microblaze platforms. > > Signed-off-by: Srikanth Thokala > --- > Note: > - This driver patch is created on top of earlier series, > 1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation" > 2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support" > - Rebased on v3.14.0-rc8 > > Changes in v2: > - Simplified the logic to set SOP and APP words in prep_slave_sg(). > - Corrected function description comments to match the return type. > - Fixed some minor comments as suggested by Andy, Thanks. > --- > drivers/dma/Kconfig | 13 + > drivers/dma/xilinx/Makefile |1 + > drivers/dma/xilinx/xilinx_dma.c | 1225 > +++ > include/linux/amba/xilinx_dma.h | 17 + > 4 files changed, 1256 insertions(+) > create mode 100644 drivers/dma/xilinx/xilinx_dma.c > > diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig > index 44b312e..8cfcc74 100644 > --- a/drivers/dma/Kconfig > +++ b/drivers/dma/Kconfig > @@ -365,6 +365,19 @@ config XILINX_VDMA > channels, Memory Mapped to Stream (MM2S) and Stream to > Memory Mapped (S2MM) for the data transfers. > > +config XILINX_DMA > + tristate "Xilinx AXI DMA Engine" > + depends on (ARCH_ZYNQ || MICROBLAZE) > + select DMA_ENGINE > + help > + Enable support for Xilinx AXI DMA Soft IP. > + > + This engine provides high-bandwidth direct memory access > + between memory and AXI4-Stream type target peripherals. > + It has two stream interfaces/channels, Memory Mapped to > + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the > + data transfers. > + > config DMA_ENGINE > bool > > diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile > index 3c4e9f2..6224a49 100644 > --- a/drivers/dma/xilinx/Makefile > +++ b/drivers/dma/xilinx/Makefile > @@ -1 +1,2 @@ > obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o > +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > new file mode 100644 > index 000..0500773 > --- /dev/null > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -0,0 +1,1225 @@ > +/* > + * DMA driver for Xilinx DMA Engine > + * > + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. > + * > + * Based on the Freescale DMA driver. > + * > + * Description: > + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory > + * Access between memory and AXI4-Stream-type target peripherals. It can be > + * configured to have one channel or two channels and if configured as two > + * channels, one is to transmit data from memory to a device and another is > + * to receive from a device. > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "../dmaengine.h" > + > +/* Register Offsets */ > +#define XILINX_DMA_REG_CONTROL 0x00 > +#define XILINX_DMA_REG_STATUS 0x04 > +#define XILINX_DMA_REG_CURDESC 0x08 > +#define XILINX_DMA_REG_TAILDESC0x10 > +#define XILINX_DMA_REG_SRCADDR 0x18 > +#define XILINX_DMA_REG_DSTADDR 0x20 > +#define XILINX_DMA_REG_BTT 0x28 > + > +/* Channel/Descriptor Offsets */ > +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 > +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 > + > +/* General register bits definitions */ > +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) > +#define XILINX_DMA_CR_RESET_MASK BIT(2) > + > +#define XILINX_DMA_CR_DELAY_SHIFT 24 > +#define XILINX_DMA_CR_COALESCE_SHIFT 16 > + > +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) > +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) > + > +#define XILINX_DMA_SR_HALTED_MASK BIT(0) > +#define XILINX_DMA_SR_IDLE_MASKBIT(1
Re: [PATCH v2 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi, Kindly review this driver patch and please let me know if you have any comments. Srikanth On Tue, Apr 1, 2014 at 5:57 PM, Srikanth Thokala stho...@xilinx.com wrote: This is the driver for the AXI Direct Memory Access (AXI DMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type target peripherals. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala stho...@xilinx.com --- Note: - This driver patch is created on top of earlier series, 1/2 - dma: Add Xilinx Video DMA DT Binding Documentation 2/2 - dma: Add Xilinx AXI Video Direct Memory Access Engine driver support - Rebased on v3.14.0-rc8 Changes in v2: - Simplified the logic to set SOP and APP words in prep_slave_sg(). - Corrected function description comments to match the return type. - Fixed some minor comments as suggested by Andy, Thanks. --- drivers/dma/Kconfig | 13 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_dma.c | 1225 +++ include/linux/amba/xilinx_dma.h | 17 + 4 files changed, 1256 insertions(+) create mode 100644 drivers/dma/xilinx/xilinx_dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 44b312e..8cfcc74 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -365,6 +365,19 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_DMA + tristate Xilinx AXI DMA Engine + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI DMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream type target peripherals. + It has two stream interfaces/channels, Memory Mapped to + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the + data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..6224a49 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c new file mode 100644 index 000..0500773 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -0,0 +1,1225 @@ +/* + * DMA driver for Xilinx DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access between memory and AXI4-Stream-type target peripherals. It can be + * configured to have one channel or two channels and if configured as two + * channels, one is to transmit data from memory to a device and another is + * to receive from a device. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include linux/amba/xilinx_dma.h +#include linux/bitops.h +#include linux/init.h +#include linux/interrupt.h +#include linux/io.h +#include linux/module.h +#include linux/of_address.h +#include linux/of_dma.h +#include linux/of_irq.h +#include linux/of_platform.h +#include linux/slab.h + +#include ../dmaengine.h + +/* Register Offsets */ +#define XILINX_DMA_REG_CONTROL 0x00 +#define XILINX_DMA_REG_STATUS 0x04 +#define XILINX_DMA_REG_CURDESC 0x08 +#define XILINX_DMA_REG_TAILDESC0x10 +#define XILINX_DMA_REG_SRCADDR 0x18 +#define XILINX_DMA_REG_DSTADDR 0x20 +#define XILINX_DMA_REG_BTT 0x28 + +/* Channel/Descriptor Offsets */ +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 + +/* General register bits definitions */ +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_DMA_CR_RESET_MASK BIT(2) + +#define XILINX_DMA_CR_DELAY_SHIFT 24 +#define XILINX_DMA_CR_COALESCE_SHIFT 16 + +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) + +#define XILINX_DMA_SR_HALTED_MASK BIT(0) +#define XILINX_DMA_SR_IDLE_MASKBIT(1) + +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) + +/* BD definitions */ +#define XILINX_DMA_BD_STS_ALL_MASK GENMASK(31, 28) +#define XILINX_DMA_BD_SOP BIT(27
Re: [PATCH 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support
Hi, Kindly review this driver and please let me know if you have any comments. Thanks Srikanth On Mon, Mar 31, 2014 at 7:24 PM, Srikanth Thokala stho...@xilinx.com wrote: This is the driver for the AXI Central Direct Memory Access (AXI CDMA) core, which is a soft Xilinx IP core that provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala stho...@xilinx.com --- NOTE: - This driver patch is created on top of earlier series, 1/2 - dma: Add Xilinx Video DMA DT Binding Documentation 2/2 - dma: Add Xilinx AXI Video Direct Memory Access Engine driver support - Rebased on v3.14.0-rc8 --- drivers/dma/Kconfig | 12 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_cdma.c | 998 ++ include/linux/amba/xilinx_dma.h | 15 +- 4 files changed, 1025 insertions(+), 1 deletion(-) create mode 100644 drivers/dma/xilinx/xilinx_cdma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 44b312e..e2c5cf2 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -365,6 +365,18 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_CDMA + tristate Xilinx AXI CDMA Engine + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI CDMA Soft IP. + + The AXI CDMA is a soft IP which provides high-bandwidth + Direct Memory Access (DMA) between a memory-mapped source + address and a memory-mapped destination address using the + AXI4 protocol. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..e1dee77 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_CDMA) += xilinx_cdma.o diff --git a/drivers/dma/xilinx/xilinx_cdma.c b/drivers/dma/xilinx/xilinx_cdma.c new file mode 100644 index 000..2ae7c77 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_cdma.c @@ -0,0 +1,998 @@ +/* + * DMA driver for Xilinx Central DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access (DMA) between a memory-mapped source address and a memory-mapped + * destination address. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include linux/amba/xilinx_dma.h +#include linux/bitops.h +#include linux/dmapool.h +#include linux/init.h +#include linux/interrupt.h +#include linux/io.h +#include linux/module.h +#include linux/of_address.h +#include linux/of_dma.h +#include linux/of_irq.h +#include linux/of_platform.h +#include linux/slab.h + +#include ../dmaengine.h + +/* Register Offsets */ +#define XILINX_CDMA_CONTROL_OFFSET 0x00 +#define XILINX_CDMA_STATUS_OFFSET 0x04 +#define XILINX_CDMA_CDESC_OFFSET 0x08 +#define XILINX_CDMA_TDESC_OFFSET 0x10 +#define XILINX_CDMA_SRCADDR_OFFSET 0x18 +#define XILINX_CDMA_DSTADDR_OFFSET 0x20 +#define XILINX_CDMA_BTT_OFFSET 0x28 + +/* General register bits definitions */ +#define XILINX_CDMA_CR_RESET BIT(2) +#define XILINX_CDMA_CR_SGMODE BIT(3) + +#define XILINX_CDMA_SR_IDLEBIT(1) + +#define XILINX_CDMA_XR_IRQ_IOC_MASKBIT(12) +#define XILINX_CDMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_CDMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_CDMA_XR_IRQ_ALL_MASKGENMASK(14, 12) + +#define XILINX_CDMA_XR_DELAY_MASK GENMASK(31, 24) +#define XILINX_CDMA_XR_COALESCE_MASK GENMASK(23, 16) + +#define XILINX_CDMA_DELAY_MAX GENMASK(7, 0) +#define XILINX_CDMA_DELAY_SHIFT24 + +#define XILINX_CDMA_COALESCE_MAX GENMASK(7, 0) +#define XILINX_CDMA_COALESCE_SHIFT 16 + +/* Delay loop counter to prevent hardware failure */ +#define XILINX_CDMA_RESET_LOOP 100 + +/* Maximum transfer length */ +#define XILINX_CDMA_MAX_TRANS_LEN GENMASK(22, 0) + +/** + * struct xilinx_cdma_desc_hw - Hardware Descriptor + * @next_desc: Next Descriptor Pointer @0x00 + * @pad1: Reserved @0x04 + * @src_addr: Source address @0x08 + * @pad2: Reserved @0x0C + * @dest_addr: Destination address @0x10 + * @pad3: Reserved @0x14 + * @control: Control field @0x18 + * @status: Status field @0x1C
[PATCH v2 1/2] dma: Add Xilinx AXI DMA DT Binding Documentation
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
new file mode 100644
index 000..18e8bcc
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -0,0 +1,65 @@
+Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
+target devices. It can be configured to have one channel or two channels.
+If configured as two channels, one is to transmit to the device and another
+is to receive from the device.
+
+Required properties:
+- compatible: Should be "xlnx,axi-dma-1.00.a"
+- #dma-cells: Should be <1>, see "dmas" property below
+- reg: Should contain DMA registers location and length.
+- dma-channel child node: Should have atleast one channel and can have upto
+ two channels per device. This node specifies the properties of each
+ DMA channel (see child node properties below).
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+ the hardware.
+
+Required child node properties:
+- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
+ "xlnx,axi-dma-s2mm-channel".
+- interrupts: Should contain per channel DMA interrupts.
+- xlnx,data-width: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+ Realignment Engine.
+
+Example:
+
+
+axi_dma_0: axidma@4040 {
+ compatible = "xlnx,axi-dma-1.00.a";
+ #dma_cells = <1>;
+ reg = < 0x4040 0x1 >;
+ dma-channel@4040 {
+ compatible = "xlnx,axi-dma-mm2s-channel";
+ interrupts = < 0 59 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+ dma-channel@40400030 {
+ compatible = "xlnx,axi-dma-s2mm-channel";
+ interrupts = < 0 58 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per "dmas" entry
+
+Example:
+
+
+dmatest_0: dmatest@0 {
+ compatible ="xlnx,axi-dma-test-1.00.a";
+ dmas = <_dma_0 0
+ _dma_0 1>;
+ dma-names = "dma0", "dma1";
+} ;
--
1.7.9.5
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[PATCH v2 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
This is the driver for the AXI Direct Memory Access (AXI DMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type target peripherals. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala --- Note: - This driver patch is created on top of earlier series, 1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation" 2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support" - Rebased on v3.14.0-rc8 Changes in v2: - Simplified the logic to set SOP and APP words in prep_slave_sg(). - Corrected function description comments to match the return type. - Fixed some minor comments as suggested by Andy, Thanks. --- drivers/dma/Kconfig | 13 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_dma.c | 1225 +++ include/linux/amba/xilinx_dma.h | 17 + 4 files changed, 1256 insertions(+) create mode 100644 drivers/dma/xilinx/xilinx_dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 44b312e..8cfcc74 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -365,6 +365,19 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_DMA + tristate "Xilinx AXI DMA Engine" + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI DMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream type target peripherals. + It has two stream interfaces/channels, Memory Mapped to + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the + data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..6224a49 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c new file mode 100644 index 000..0500773 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -0,0 +1,1225 @@ +/* + * DMA driver for Xilinx DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access between memory and AXI4-Stream-type target peripherals. It can be + * configured to have one channel or two channels and if configured as two + * channels, one is to transmit data from memory to a device and another is + * to receive from a device. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../dmaengine.h" + +/* Register Offsets */ +#define XILINX_DMA_REG_CONTROL 0x00 +#define XILINX_DMA_REG_STATUS 0x04 +#define XILINX_DMA_REG_CURDESC 0x08 +#define XILINX_DMA_REG_TAILDESC0x10 +#define XILINX_DMA_REG_SRCADDR 0x18 +#define XILINX_DMA_REG_DSTADDR 0x20 +#define XILINX_DMA_REG_BTT 0x28 + +/* Channel/Descriptor Offsets */ +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 + +/* General register bits definitions */ +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_DMA_CR_RESET_MASK BIT(2) + +#define XILINX_DMA_CR_DELAY_SHIFT 24 +#define XILINX_DMA_CR_COALESCE_SHIFT 16 + +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) + +#define XILINX_DMA_SR_HALTED_MASK BIT(0) +#define XILINX_DMA_SR_IDLE_MASKBIT(1) + +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) + +/* BD definitions */ +#define XILINX_DMA_BD_STS_ALL_MASK GENMASK(31, 28) +#define XILINX_DMA_BD_SOP BIT(27) +#define XILINX_DMA_BD_EOP BIT(26) + +/* Hw specific definitions */ +#define XILINX_DMA_MAX_CHANS_PER_DEVICE0x2 +#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) + +/* Delay loop counter to prevent hardware failure */ +#define XILINX_DMA_LOOP_COUNT 100 + +/* Maximum number of Descriptors */ +#define XILINX_DMA_NUM_DESCS 64 + +/** + * struct xilinx_dma_desc_hw - Hardware Descriptor
[PATCH v2 1/2] dma: Add Xilinx AXI DMA DT Binding Documentation
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
new file mode 100644
index 000..18e8bcc
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -0,0 +1,65 @@
+Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
+target devices. It can be configured to have one channel or two channels.
+If configured as two channels, one is to transmit to the device and another
+is to receive from the device.
+
+Required properties:
+- compatible: Should be xlnx,axi-dma-1.00.a
+- #dma-cells: Should be 1, see dmas property below
+- reg: Should contain DMA registers location and length.
+- dma-channel child node: Should have atleast one channel and can have upto
+ two channels per device. This node specifies the properties of each
+ DMA channel (see child node properties below).
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+ the hardware.
+
+Required child node properties:
+- compatible: It should be either xlnx,axi-dma-mm2s-channel or
+ xlnx,axi-dma-s2mm-channel.
+- interrupts: Should contain per channel DMA interrupts.
+- xlnx,data-width: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+ Realignment Engine.
+
+Example:
+
+
+axi_dma_0: axidma@4040 {
+ compatible = xlnx,axi-dma-1.00.a;
+ #dma_cells = 1;
+ reg = 0x4040 0x1 ;
+ dma-channel@4040 {
+ compatible = xlnx,axi-dma-mm2s-channel;
+ interrupts = 0 59 4 ;
+ xlnx,datawidth = 0x40;
+ } ;
+ dma-channel@40400030 {
+ compatible = xlnx,axi-dma-s2mm-channel;
+ interrupts = 0 58 4 ;
+ xlnx,datawidth = 0x40;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of [DMA device phandle] [Channel ID] pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per dmas entry
+
+Example:
+
+
+dmatest_0: dmatest@0 {
+ compatible =xlnx,axi-dma-test-1.00.a;
+ dmas = axi_dma_0 0
+ axi_dma_0 1;
+ dma-names = dma0, dma1;
+} ;
--
1.7.9.5
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[PATCH v2 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
This is the driver for the AXI Direct Memory Access (AXI DMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type target peripherals. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala stho...@xilinx.com --- Note: - This driver patch is created on top of earlier series, 1/2 - dma: Add Xilinx Video DMA DT Binding Documentation 2/2 - dma: Add Xilinx AXI Video Direct Memory Access Engine driver support - Rebased on v3.14.0-rc8 Changes in v2: - Simplified the logic to set SOP and APP words in prep_slave_sg(). - Corrected function description comments to match the return type. - Fixed some minor comments as suggested by Andy, Thanks. --- drivers/dma/Kconfig | 13 + drivers/dma/xilinx/Makefile |1 + drivers/dma/xilinx/xilinx_dma.c | 1225 +++ include/linux/amba/xilinx_dma.h | 17 + 4 files changed, 1256 insertions(+) create mode 100644 drivers/dma/xilinx/xilinx_dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 44b312e..8cfcc74 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -365,6 +365,19 @@ config XILINX_VDMA channels, Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) for the data transfers. +config XILINX_DMA + tristate Xilinx AXI DMA Engine + depends on (ARCH_ZYNQ || MICROBLAZE) + select DMA_ENGINE + help + Enable support for Xilinx AXI DMA Soft IP. + + This engine provides high-bandwidth direct memory access + between memory and AXI4-Stream type target peripherals. + It has two stream interfaces/channels, Memory Mapped to + Stream (MM2S) and Stream to Memory Mapped (S2MM) for the + data transfers. + config DMA_ENGINE bool diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile index 3c4e9f2..6224a49 100644 --- a/drivers/dma/xilinx/Makefile +++ b/drivers/dma/xilinx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o +obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c new file mode 100644 index 000..0500773 --- /dev/null +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -0,0 +1,1225 @@ +/* + * DMA driver for Xilinx DMA Engine + * + * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI DMA, is a soft IP, which provides high-bandwidth Direct Memory + * Access between memory and AXI4-Stream-type target peripherals. It can be + * configured to have one channel or two channels and if configured as two + * channels, one is to transmit data from memory to a device and another is + * to receive from a device. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include linux/amba/xilinx_dma.h +#include linux/bitops.h +#include linux/init.h +#include linux/interrupt.h +#include linux/io.h +#include linux/module.h +#include linux/of_address.h +#include linux/of_dma.h +#include linux/of_irq.h +#include linux/of_platform.h +#include linux/slab.h + +#include ../dmaengine.h + +/* Register Offsets */ +#define XILINX_DMA_REG_CONTROL 0x00 +#define XILINX_DMA_REG_STATUS 0x04 +#define XILINX_DMA_REG_CURDESC 0x08 +#define XILINX_DMA_REG_TAILDESC0x10 +#define XILINX_DMA_REG_SRCADDR 0x18 +#define XILINX_DMA_REG_DSTADDR 0x20 +#define XILINX_DMA_REG_BTT 0x28 + +/* Channel/Descriptor Offsets */ +#define XILINX_DMA_MM2S_CTRL_OFFSET0x00 +#define XILINX_DMA_S2MM_CTRL_OFFSET0x30 + +/* General register bits definitions */ +#define XILINX_DMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_DMA_CR_RESET_MASK BIT(2) + +#define XILINX_DMA_CR_DELAY_SHIFT 24 +#define XILINX_DMA_CR_COALESCE_SHIFT 16 + +#define XILINX_DMA_CR_DELAY_MAXGENMASK(7, 0) +#define XILINX_DMA_CR_COALESCE_MAX GENMASK(7, 0) + +#define XILINX_DMA_SR_HALTED_MASK BIT(0) +#define XILINX_DMA_SR_IDLE_MASKBIT(1) + +#define XILINX_DMA_XR_IRQ_IOC_MASK BIT(12) +#define XILINX_DMA_XR_IRQ_DELAY_MASK BIT(13) +#define XILINX_DMA_XR_IRQ_ERROR_MASK BIT(14) +#define XILINX_DMA_XR_IRQ_ALL_MASK GENMASK(14, 12) + +/* BD definitions */ +#define XILINX_DMA_BD_STS_ALL_MASK GENMASK(31, 28) +#define XILINX_DMA_BD_SOP BIT(27) +#define XILINX_DMA_BD_EOP BIT(26) + +/* Hw specific definitions */ +#define XILINX_DMA_MAX_CHANS_PER_DEVICE0x2 +#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) + +/* Delay loop counter to prevent hardware failure */ +#define XILINX_DMA_LOOP_COUNT 100
[PATCH 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support
This is the driver for the AXI Central Direct Memory Access (AXI
CDMA) core, which is a soft Xilinx IP core that provides high-bandwidth
Direct Memory Access (DMA) between a memory-mapped source address and a
memory-mapped destination address.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
---
NOTE:
- This driver patch is created on top of earlier series,
1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support"
- Rebased on v3.14.0-rc8
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |1 +
drivers/dma/xilinx/xilinx_cdma.c | 998 ++
include/linux/amba/xilinx_dma.h | 15 +-
4 files changed, 1025 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma/xilinx/xilinx_cdma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 44b312e..e2c5cf2 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -365,6 +365,18 @@ config XILINX_VDMA
channels, Memory Mapped to Stream (MM2S) and Stream to
Memory Mapped (S2MM) for the data transfers.
+config XILINX_CDMA
+ tristate "Xilinx AXI CDMA Engine"
+ depends on (ARCH_ZYNQ || MICROBLAZE)
+ select DMA_ENGINE
+ help
+ Enable support for Xilinx AXI CDMA Soft IP.
+
+ The AXI CDMA is a soft IP which provides high-bandwidth
+ Direct Memory Access (DMA) between a memory-mapped source
+ address and a memory-mapped destination address using the
+ AXI4 protocol.
+
config DMA_ENGINE
bool
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 3c4e9f2..e1dee77 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o
+obj-$(CONFIG_XILINX_CDMA) += xilinx_cdma.o
diff --git a/drivers/dma/xilinx/xilinx_cdma.c b/drivers/dma/xilinx/xilinx_cdma.c
new file mode 100644
index 000..2ae7c77
--- /dev/null
+++ b/drivers/dma/xilinx/xilinx_cdma.c
@@ -0,0 +1,998 @@
+/*
+ * DMA driver for Xilinx Central DMA Engine
+ *
+ * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+ *
+ * Based on the Freescale DMA driver.
+ *
+ * Description:
+ * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
+ * Access (DMA) between a memory-mapped source address and a memory-mapped
+ * destination address.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../dmaengine.h"
+
+/* Register Offsets */
+#define XILINX_CDMA_CONTROL_OFFSET 0x00
+#define XILINX_CDMA_STATUS_OFFSET 0x04
+#define XILINX_CDMA_CDESC_OFFSET 0x08
+#define XILINX_CDMA_TDESC_OFFSET 0x10
+#define XILINX_CDMA_SRCADDR_OFFSET 0x18
+#define XILINX_CDMA_DSTADDR_OFFSET 0x20
+#define XILINX_CDMA_BTT_OFFSET 0x28
+
+/* General register bits definitions */
+#define XILINX_CDMA_CR_RESET BIT(2)
+#define XILINX_CDMA_CR_SGMODE BIT(3)
+
+#define XILINX_CDMA_SR_IDLEBIT(1)
+
+#define XILINX_CDMA_XR_IRQ_IOC_MASKBIT(12)
+#define XILINX_CDMA_XR_IRQ_DELAY_MASK BIT(13)
+#define XILINX_CDMA_XR_IRQ_ERROR_MASK BIT(14)
+#define XILINX_CDMA_XR_IRQ_ALL_MASKGENMASK(14, 12)
+
+#define XILINX_CDMA_XR_DELAY_MASK GENMASK(31, 24)
+#define XILINX_CDMA_XR_COALESCE_MASK GENMASK(23, 16)
+
+#define XILINX_CDMA_DELAY_MAX GENMASK(7, 0)
+#define XILINX_CDMA_DELAY_SHIFT24
+
+#define XILINX_CDMA_COALESCE_MAX GENMASK(7, 0)
+#define XILINX_CDMA_COALESCE_SHIFT 16
+
+/* Delay loop counter to prevent hardware failure */
+#define XILINX_CDMA_RESET_LOOP 100
+
+/* Maximum transfer length */
+#define XILINX_CDMA_MAX_TRANS_LEN GENMASK(22, 0)
+
+/**
+ * struct xilinx_cdma_desc_hw - Hardware Descriptor
+ * @next_desc: Next Descriptor Pointer @0x00
+ * @pad1: Reserved @0x04
+ * @src_addr: Source address @0x08
+ * @pad2: Reserved @0x0C
+ * @dest_addr: Destination address @0x10
+ * @pad3: Reserved @0x14
+ * @control: Control field @0x18
+ * @status: Status field @0x1C
+ */
+struct xilinx_cdma_desc_hw {
+ u32 next_desc;
+ u32 pad1;
+ u32 src_addr;
+ u32 pad2;
+ u32 dest_addr;
+ u32 pad3;
+ u32 control;
+ u32 status;
+} __aligned(64);
+
+/**
+ * struct xilinx_cdma_tx_segment - Descriptor segment
+ * @hw: Hardware descriptor
+ * @node: Node in the descriptor segments list
+ * @phys: Physical address of segment
+ */
+struct xilinx_cdma_tx_segment {
+ struct xilinx_cdma_d
[PATCH 1/2] dma: Add Xilinx Central DMA DT Binding Documentation
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
new file mode 100644
index 000..b04f76b
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
@@ -0,0 +1,54 @@
+Xilinx AXI CDMA engine, it does transfers between memory-mapped source
+address and a memory-mapped destination address.
+
+Required properties:
+- compatible: Should be "xlnx,axi-cdma-1.00.a"
+- #dma-cells: Should be <1>, see "dmas" property below
+- reg: Should contain cdma registers location and length.
+- dma-channel child node: Should have only one channel
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+ the hardware.
+
+Required child node properties:
+- compatible: It should be "xlnx,axi-cdma-channel".
+- interrupts: Should contain per channel CDMA interrupts.
+- xlnx,data-width: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+ Realignment Engine.
+
+Example:
+
+
+axi_cdma_0: axicdma@7e20 {
+ compatible = "xlnx,axi-cdma-1.00.a";
+ #dma_cells = <1>;
+ reg = < 0x7e20 0x1 >;
+ dma-channel@7e20 {
+ compatible = "xlnx,axi-cdma-channel";
+ interrupts = < 0 55 4 >;
+ xlnx,datawidth = <0x40>;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of <[Central DMA device phandle] [Channel ID]> pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per "dmas" entry
+
+Example:
+
+
+cdmatest_0: cdmatest@0 {
+ compatible ="xlnx,axi-cdma-test-1.00.a";
+ dmas = <_cdma_0 0>;
+ dma-names = "cdma0";
+} ;
--
1.7.9.5
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Re: [PATCH 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
On Mon, Mar 31, 2014 at 3:00 PM, Andy Shevchenko
wrote:
> On Sat, 2014-03-29 at 20:58 +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Direct Memory Access (AXI DMA)
>> core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct memory access between memory and AXI4-Stream
>> type target peripherals.
>>
>> This module works on Zynq (ARM Based SoC) and Microblaze platforms.
>
> Few nitpicks below.
>
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> - This driver patch is created on top of earlier series,
>> 1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
>> 2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver
>> support"
>> - Rebased on v3.14.0-rc8
[...]
>> +
>> + for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
>> + chan->seg_v[i].hw.next_desc =
>> + chan->seg_p + sizeof(*chan->seg_v) *
>> + ((i + 1) % XILINX_DMA_NUM_DESCS);
>> + chan->seg_v[i].phys =
>> + chan->seg_p + sizeof(*chan->seg_v) *
>> + (i % XILINX_DMA_NUM_DESCS);
>
> i can't be higher than NUM_DESCS - 1, thus, i % XILINX_DMA_NUM_DESCS =
> i.
I will correct it, Thanks.
>
>> + list_add_tail(>seg_v[i].node, >free_seg_list);
>> + }
>> +
>> + dma_cookie_init(dchan);
>> + return 0;
>> +}
>> +
[...]
>> +
>> +/**
>> + * xilinx_dma_is_running - Check if DMA channel is running
>> + * @chan: Driver specific DMA channel
>> + *
>> + * Return: '1' if running, '0' if not.
>
> true, false.
Ok.
>
>> + */
>> +static bool xilinx_dma_is_running(struct xilinx_dma_chan *chan)
>> +{
>> + return !(dma_ctrl_read(chan, XILINX_DMA_REG_STATUS) &
>> + XILINX_DMA_SR_HALTED_MASK) &&
>> + (dma_ctrl_read(chan, XILINX_DMA_REG_CONTROL) &
>> + XILINX_DMA_CR_RUNSTOP_MASK);
>> +}
>> +
>> +/**
>> + * xilinx_dma_is_idle - Check if DMA channel is idle
>> + * @chan: Driver specific DMA channel
>> + *
>> + * Return: '1' if idle, '0' if not.
>
> Ditto.
Ok.
>
>> + */
>> +static bool xilinx_dma_is_idle(struct xilinx_dma_chan *chan)
>> +{
>> + return dma_ctrl_read(chan, XILINX_DMA_REG_STATUS) &
>> + XILINX_DMA_SR_IDLE_MASK;
>> +}
>> +
>> +/**
>> + * xilinx_dma_halt - Halt DMA channel
[...]
>> + goto error;
>> +
>> + /*
>> + * Calculate the maximum number of bytes to transfer,
>> + * making sure it is less than the hw limit
>> + */
>> + copy = min((size_t)(sg_dma_len(sg) - sg_used),
>> + (size_t)XILINX_DMA_MAX_TRANS_LEN);
>
> min_t(size_t, ...)
Ok, I will correct it.
>
>
>> + hw = &(segment->hw);
>
> Seems useless parentheses.
Ok.
>
>> +
>> + /* Fill in the descriptor */
>> + hw->buf_addr = sg_dma_address(sg) + sg_used;
>> +
>> + hw->control = copy;
>> +
>> + if ((direction == DMA_MEM_TO_DEV) && app_w)
>> + memcpy(hw->app, app_w,
>> + sizeof(u32) *
>> XILINX_DMA_NUM_APP_WORDS);
>> +
>> + /* For the first DMA_MEM_TO_DEV transfer, set SOP */
>> + if (!i)
>> + if (direction == DMA_MEM_TO_DEV)
>> + hw->control |= XILINX_DMA_BD_SOP;
>
> You may group previous conditions like
> if (direction = ...) {
> if (app_w)
> ...
> if (!i)
> ...
> }
>
> But it's up to you.
I will organize them, Thanks.
>
>> +
>> + sg_used += copy;
>> +
>> + /*
>> + * Insert the segment into the descriptor segments
>> + * list.
>> + */
>> + list_add_tail(>node, >segments);
>> + }
>> + }
>> +
[...]
>> + return -EINVAL;
>> + }
>> +
>> + /* find the IRQ line, if it exists in the device tree */
>
> Maybe first letter should be capital across all comments in the code?
Ok, I will correct them in all places, if any.
Srikanth
[...]
>
>
> --
> Andy Shevchenko
> Intel Finland Oy
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
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Re: [PATCH 2/2] dma: Add Xilinx AXI Direct Memory Access Engine driver support
On Mon, Mar 31, 2014 at 3:00 PM, Andy Shevchenko
andriy.shevche...@linux.intel.com wrote:
On Sat, 2014-03-29 at 20:58 +0530, Srikanth Thokala wrote:
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Few nitpicks below.
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
- This driver patch is created on top of earlier series,
1/2 - dma: Add Xilinx Video DMA DT Binding Documentation
2/2 - dma: Add Xilinx AXI Video Direct Memory Access Engine driver
support
- Rebased on v3.14.0-rc8
[...]
+
+ for (i = 0; i XILINX_DMA_NUM_DESCS; i++) {
+ chan-seg_v[i].hw.next_desc =
+ chan-seg_p + sizeof(*chan-seg_v) *
+ ((i + 1) % XILINX_DMA_NUM_DESCS);
+ chan-seg_v[i].phys =
+ chan-seg_p + sizeof(*chan-seg_v) *
+ (i % XILINX_DMA_NUM_DESCS);
i can't be higher than NUM_DESCS - 1, thus, i % XILINX_DMA_NUM_DESCS =
i.
I will correct it, Thanks.
+ list_add_tail(chan-seg_v[i].node, chan-free_seg_list);
+ }
+
+ dma_cookie_init(dchan);
+ return 0;
+}
+
[...]
+
+/**
+ * xilinx_dma_is_running - Check if DMA channel is running
+ * @chan: Driver specific DMA channel
+ *
+ * Return: '1' if running, '0' if not.
true, false.
Ok.
+ */
+static bool xilinx_dma_is_running(struct xilinx_dma_chan *chan)
+{
+ return !(dma_ctrl_read(chan, XILINX_DMA_REG_STATUS)
+ XILINX_DMA_SR_HALTED_MASK)
+ (dma_ctrl_read(chan, XILINX_DMA_REG_CONTROL)
+ XILINX_DMA_CR_RUNSTOP_MASK);
+}
+
+/**
+ * xilinx_dma_is_idle - Check if DMA channel is idle
+ * @chan: Driver specific DMA channel
+ *
+ * Return: '1' if idle, '0' if not.
Ditto.
Ok.
+ */
+static bool xilinx_dma_is_idle(struct xilinx_dma_chan *chan)
+{
+ return dma_ctrl_read(chan, XILINX_DMA_REG_STATUS)
+ XILINX_DMA_SR_IDLE_MASK;
+}
+
+/**
+ * xilinx_dma_halt - Halt DMA channel
[...]
+ goto error;
+
+ /*
+ * Calculate the maximum number of bytes to transfer,
+ * making sure it is less than the hw limit
+ */
+ copy = min((size_t)(sg_dma_len(sg) - sg_used),
+ (size_t)XILINX_DMA_MAX_TRANS_LEN);
min_t(size_t, ...)
Ok, I will correct it.
+ hw = (segment-hw);
Seems useless parentheses.
Ok.
+
+ /* Fill in the descriptor */
+ hw-buf_addr = sg_dma_address(sg) + sg_used;
+
+ hw-control = copy;
+
+ if ((direction == DMA_MEM_TO_DEV) app_w)
+ memcpy(hw-app, app_w,
+ sizeof(u32) *
XILINX_DMA_NUM_APP_WORDS);
+
+ /* For the first DMA_MEM_TO_DEV transfer, set SOP */
+ if (!i)
+ if (direction == DMA_MEM_TO_DEV)
+ hw-control |= XILINX_DMA_BD_SOP;
You may group previous conditions like
if (direction = ...) {
if (app_w)
...
if (!i)
...
}
But it's up to you.
I will organize them, Thanks.
+
+ sg_used += copy;
+
+ /*
+ * Insert the segment into the descriptor segments
+ * list.
+ */
+ list_add_tail(segment-node, desc-segments);
+ }
+ }
+
[...]
+ return -EINVAL;
+ }
+
+ /* find the IRQ line, if it exists in the device tree */
Maybe first letter should be capital across all comments in the code?
Ok, I will correct them in all places, if any.
Srikanth
[...]
--
Andy Shevchenko andriy.shevche...@linux.intel.com
Intel Finland Oy
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[PATCH 1/2] dma: Add Xilinx Central DMA DT Binding Documentation
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
new file mode 100644
index 000..b04f76b
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
@@ -0,0 +1,54 @@
+Xilinx AXI CDMA engine, it does transfers between memory-mapped source
+address and a memory-mapped destination address.
+
+Required properties:
+- compatible: Should be xlnx,axi-cdma-1.00.a
+- #dma-cells: Should be 1, see dmas property below
+- reg: Should contain cdma registers location and length.
+- dma-channel child node: Should have only one channel
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+ the hardware.
+
+Required child node properties:
+- compatible: It should be xlnx,axi-cdma-channel.
+- interrupts: Should contain per channel CDMA interrupts.
+- xlnx,data-width: Should contain the stream data width, take values
+ {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+ Realignment Engine.
+
+Example:
+
+
+axi_cdma_0: axicdma@7e20 {
+ compatible = xlnx,axi-cdma-1.00.a;
+ #dma_cells = 1;
+ reg = 0x7e20 0x1 ;
+ dma-channel@7e20 {
+ compatible = xlnx,axi-cdma-channel;
+ interrupts = 0 55 4 ;
+ xlnx,datawidth = 0x40;
+ } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of [Central DMA device phandle] [Channel ID] pairs,
+ where Channel ID is '0' for write/tx and '1' for read/rx
+ channel.
+- dma-names: a list of DMA channel names, one per dmas entry
+
+Example:
+
+
+cdmatest_0: cdmatest@0 {
+ compatible =xlnx,axi-cdma-test-1.00.a;
+ dmas = axi_cdma_0 0;
+ dma-names = cdma0;
+} ;
--
1.7.9.5
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[PATCH 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support
This is the driver for the AXI Central Direct Memory Access (AXI
CDMA) core, which is a soft Xilinx IP core that provides high-bandwidth
Direct Memory Access (DMA) between a memory-mapped source address and a
memory-mapped destination address.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
NOTE:
- This driver patch is created on top of earlier series,
1/2 - dma: Add Xilinx Video DMA DT Binding Documentation
2/2 - dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
- Rebased on v3.14.0-rc8
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |1 +
drivers/dma/xilinx/xilinx_cdma.c | 998 ++
include/linux/amba/xilinx_dma.h | 15 +-
4 files changed, 1025 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma/xilinx/xilinx_cdma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 44b312e..e2c5cf2 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -365,6 +365,18 @@ config XILINX_VDMA
channels, Memory Mapped to Stream (MM2S) and Stream to
Memory Mapped (S2MM) for the data transfers.
+config XILINX_CDMA
+ tristate Xilinx AXI CDMA Engine
+ depends on (ARCH_ZYNQ || MICROBLAZE)
+ select DMA_ENGINE
+ help
+ Enable support for Xilinx AXI CDMA Soft IP.
+
+ The AXI CDMA is a soft IP which provides high-bandwidth
+ Direct Memory Access (DMA) between a memory-mapped source
+ address and a memory-mapped destination address using the
+ AXI4 protocol.
+
config DMA_ENGINE
bool
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 3c4e9f2..e1dee77 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o
+obj-$(CONFIG_XILINX_CDMA) += xilinx_cdma.o
diff --git a/drivers/dma/xilinx/xilinx_cdma.c b/drivers/dma/xilinx/xilinx_cdma.c
new file mode 100644
index 000..2ae7c77
--- /dev/null
+++ b/drivers/dma/xilinx/xilinx_cdma.c
@@ -0,0 +1,998 @@
+/*
+ * DMA driver for Xilinx Central DMA Engine
+ *
+ * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+ *
+ * Based on the Freescale DMA driver.
+ *
+ * Description:
+ * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
+ * Access (DMA) between a memory-mapped source address and a memory-mapped
+ * destination address.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/amba/xilinx_dma.h
+#include linux/bitops.h
+#include linux/dmapool.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of_address.h
+#include linux/of_dma.h
+#include linux/of_irq.h
+#include linux/of_platform.h
+#include linux/slab.h
+
+#include ../dmaengine.h
+
+/* Register Offsets */
+#define XILINX_CDMA_CONTROL_OFFSET 0x00
+#define XILINX_CDMA_STATUS_OFFSET 0x04
+#define XILINX_CDMA_CDESC_OFFSET 0x08
+#define XILINX_CDMA_TDESC_OFFSET 0x10
+#define XILINX_CDMA_SRCADDR_OFFSET 0x18
+#define XILINX_CDMA_DSTADDR_OFFSET 0x20
+#define XILINX_CDMA_BTT_OFFSET 0x28
+
+/* General register bits definitions */
+#define XILINX_CDMA_CR_RESET BIT(2)
+#define XILINX_CDMA_CR_SGMODE BIT(3)
+
+#define XILINX_CDMA_SR_IDLEBIT(1)
+
+#define XILINX_CDMA_XR_IRQ_IOC_MASKBIT(12)
+#define XILINX_CDMA_XR_IRQ_DELAY_MASK BIT(13)
+#define XILINX_CDMA_XR_IRQ_ERROR_MASK BIT(14)
+#define XILINX_CDMA_XR_IRQ_ALL_MASKGENMASK(14, 12)
+
+#define XILINX_CDMA_XR_DELAY_MASK GENMASK(31, 24)
+#define XILINX_CDMA_XR_COALESCE_MASK GENMASK(23, 16)
+
+#define XILINX_CDMA_DELAY_MAX GENMASK(7, 0)
+#define XILINX_CDMA_DELAY_SHIFT24
+
+#define XILINX_CDMA_COALESCE_MAX GENMASK(7, 0)
+#define XILINX_CDMA_COALESCE_SHIFT 16
+
+/* Delay loop counter to prevent hardware failure */
+#define XILINX_CDMA_RESET_LOOP 100
+
+/* Maximum transfer length */
+#define XILINX_CDMA_MAX_TRANS_LEN GENMASK(22, 0)
+
+/**
+ * struct xilinx_cdma_desc_hw - Hardware Descriptor
+ * @next_desc: Next Descriptor Pointer @0x00
+ * @pad1: Reserved @0x04
+ * @src_addr: Source address @0x08
+ * @pad2: Reserved @0x0C
+ * @dest_addr: Destination address @0x10
+ * @pad3: Reserved @0x14
+ * @control: Control field @0x18
+ * @status: Status field @0x1C
+ */
+struct xilinx_cdma_desc_hw {
+ u32 next_desc;
+ u32 pad1;
+ u32 src_addr;
+ u32 pad2;
+ u32 dest_addr;
+ u32 pad3;
+ u32 control;
+ u32 status;
+} __aligned(64);
+
+/**
+ * struct xilinx_cdma_tx_segment - Descriptor segment
+ * @hw: Hardware descriptor
+ * @node
