Re: [PATCH] serial: Fix an invalid comparing statement
Hi,
On 2019/06/11 1:56, Greg Kroah-Hartman wrote:
On Mon, May 27, 2019 at 02:01:27PM +0900, Sugaya Taichi wrote:
Drop the if-statement which refers to 8th bit field of u8 variable.
The bit field is no longer used.
Fixes: ba44dc043004 ("serial: Add Milbeaut serial control")
Reported-by: Colin Ian King
Signed-off-by: Sugaya Taichi
---
drivers/tty/serial/milbeaut_usio.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/tty/serial/milbeaut_usio.c
b/drivers/tty/serial/milbeaut_usio.c
index 949ab7e..d7207ab 100644
--- a/drivers/tty/serial/milbeaut_usio.c
+++ b/drivers/tty/serial/milbeaut_usio.c
@@ -56,7 +56,6 @@
#define MLB_USIO_SSR_FRE BIT(4)
#define MLB_USIO_SSR_PE BIT(5)
#define MLB_USIO_SSR_REC BIT(7)
-#define MLB_USIO_SSR_BRK BIT(8)
#define MLB_USIO_FCR_FE1 BIT(0)
#define MLB_USIO_FCR_FE2 BIT(1)
#define MLB_USIO_FCR_FCL1 BIT(2)
@@ -180,18 +179,14 @@ static void mlb_usio_rx_chars(struct uart_port *port)
if (status & MLB_USIO_SSR_ORE)
port->icount.overrun++;
status &= port->read_status_mask;
- if (status & MLB_USIO_SSR_BRK) {
- flag = TTY_BREAK;
+ if (status & MLB_USIO_SSR_PE) {
+ flag = TTY_PARITY;
ch = 0;
} else
- if (status & MLB_USIO_SSR_PE) {
- flag = TTY_PARITY;
+ if (status & MLB_USIO_SSR_FRE) {
+ flag = TTY_FRAME;
ch = 0;
- } else
- if (status & MLB_USIO_SSR_FRE) {
- flag = TTY_FRAME;
- ch = 0;
- }
+ }
if (flag)
uart_insert_char(port, status, MLB_USIO_SSR_ORE,
ch, flag);
While the code never actually supported Break, you are explicitly
removing that logic now. So shouldn't you instead _fix_ break handling?
The code before and after your change does not work any differently, so
this patch isn't really needed at this point.
According to research, MLB_USIO_SSR_BRK was a remnant of old HW.
Since current one does not handle the Break, all logic related it should be
removed. I try to make a new fix patch.
Thanks,
Sugaya Taichi
thanks,
greg k-h
Re: [PATCH] serial: Fix an invalid comparing statement
Hi
Does anyone have comments?
On 2019/05/27 14:01, Sugaya Taichi wrote:
Drop the if-statement which refers to 8th bit field of u8 variable.
The bit field is no longer used.
Fixes: ba44dc043004 ("serial: Add Milbeaut serial control")
Reported-by: Colin Ian King
Signed-off-by: Sugaya Taichi
---
drivers/tty/serial/milbeaut_usio.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/tty/serial/milbeaut_usio.c
b/drivers/tty/serial/milbeaut_usio.c
index 949ab7e..d7207ab 100644
--- a/drivers/tty/serial/milbeaut_usio.c
+++ b/drivers/tty/serial/milbeaut_usio.c
@@ -56,7 +56,6 @@
#define MLB_USIO_SSR_FRE BIT(4)
#define MLB_USIO_SSR_PE BIT(5)
#define MLB_USIO_SSR_REC BIT(7)
-#define MLB_USIO_SSR_BRK BIT(8)
#define MLB_USIO_FCR_FE1 BIT(0)
#define MLB_USIO_FCR_FE2 BIT(1)
#define MLB_USIO_FCR_FCL1 BIT(2)
@@ -180,18 +179,14 @@ static void mlb_usio_rx_chars(struct uart_port *port)
if (status & MLB_USIO_SSR_ORE)
port->icount.overrun++;
status &= port->read_status_mask;
- if (status & MLB_USIO_SSR_BRK) {
- flag = TTY_BREAK;
+ if (status & MLB_USIO_SSR_PE) {
+ flag = TTY_PARITY;
ch = 0;
} else
- if (status & MLB_USIO_SSR_PE) {
- flag = TTY_PARITY;
+ if (status & MLB_USIO_SSR_FRE) {
+ flag = TTY_FRAME;
ch = 0;
- } else
- if (status & MLB_USIO_SSR_FRE) {
- flag = TTY_FRAME;
- ch = 0;
- }
+ }
if (flag)
uart_insert_char(port, status, MLB_USIO_SSR_ORE,
ch, flag);
[PATCH] serial: Fix an invalid comparing statement
Drop the if-statement which refers to 8th bit field of u8 variable.
The bit field is no longer used.
Fixes: ba44dc043004 ("serial: Add Milbeaut serial control")
Reported-by: Colin Ian King
Signed-off-by: Sugaya Taichi
---
drivers/tty/serial/milbeaut_usio.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/tty/serial/milbeaut_usio.c
b/drivers/tty/serial/milbeaut_usio.c
index 949ab7e..d7207ab 100644
--- a/drivers/tty/serial/milbeaut_usio.c
+++ b/drivers/tty/serial/milbeaut_usio.c
@@ -56,7 +56,6 @@
#define MLB_USIO_SSR_FRE BIT(4)
#define MLB_USIO_SSR_PEBIT(5)
#define MLB_USIO_SSR_REC BIT(7)
-#define MLB_USIO_SSR_BRK BIT(8)
#define MLB_USIO_FCR_FE1 BIT(0)
#define MLB_USIO_FCR_FE2 BIT(1)
#define MLB_USIO_FCR_FCL1 BIT(2)
@@ -180,18 +179,14 @@ static void mlb_usio_rx_chars(struct uart_port *port)
if (status & MLB_USIO_SSR_ORE)
port->icount.overrun++;
status &= port->read_status_mask;
- if (status & MLB_USIO_SSR_BRK) {
- flag = TTY_BREAK;
+ if (status & MLB_USIO_SSR_PE) {
+ flag = TTY_PARITY;
ch = 0;
} else
- if (status & MLB_USIO_SSR_PE) {
- flag = TTY_PARITY;
+ if (status & MLB_USIO_SSR_FRE) {
+ flag = TTY_FRAME;
ch = 0;
- } else
- if (status & MLB_USIO_SSR_FRE) {
- flag = TTY_FRAME;
- ch = 0;
- }
+ }
if (flag)
uart_insert_char(port, status, MLB_USIO_SSR_ORE,
ch, flag);
--
1.9.1
Re: serial: Add Milbeaut serial control
Hi, Thank you for pointing out. On 2019/05/02 20:47, Colin Ian King wrote: Hi, Static analysis with Coverity has picked up an issue in commit: commit ba44dc04300441b47618f9933bf36e75a280e5fe Author: Sugaya Taichi Date: Mon Apr 15 20:31:40 2019 +0900 serial: Add Milbeaut serial control In function mlb_usio_rx_chars() the u8 status is being bit-wise AND'd with MLB_USIO_SSR_BRK (which is 1UL << 8) and hence the result is always false, which looks incorrect to me. Is this intentional? No. It is always false so should be dropped. I will send a fixes patch. Thanks, Sugaya Taichi Colin
Re: [PATCH v3] serial: Add Milbeaut serial control
Hi,
Thank you for pointing out.
On 2019/04/27 3:15, Alan Cox wrote:
O
+static void mlb_usio_set_termios(struct uart_port *port,
+ struct ktermios *termios, struct ktermios *old)
+{
+ unsigned int escr, smr = MLB_USIO_SMR_SOE;
+ unsigned long flags, baud, quot;
+
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ escr = MLB_USIO_ESCR_L_5BIT;
+ break;
+ case CS6:
+ escr = MLB_USIO_ESCR_L_6BIT;
+ break;
+ case CS7:
+ escr = MLB_USIO_ESCR_L_7BIT;
+ break;
+ case CS8:
+ default:
+ escr = MLB_USIO_ESCR_L_8BIT;
+ break;
+ }
+
+ if (termios->c_cflag & CSTOPB)
+ smr |= MLB_USIO_SMR_SBL;
+
+ if (termios->c_cflag & PARENB) {
+ escr |= MLB_USIO_ESCR_PEN;
+ if (termios->c_cflag & PARODD)
+ escr |= MLB_USIO_ESCR_P;
+ }
If you don't suport CMSPAR then clear that bit in termios as well
OK, clear the bit because of not supported.
+ /* Set hard flow control */
+ if (of_property_read_bool(port->dev->of_node, "auto-flow-control") ||
+ (termios->c_cflag & CRTSCTS))
+ escr |= MLB_USIO_ESCR_FLWEN;
That's just broken. The termios bits are the definitive things for the
port, and in addition even if they are forced you need to correct the
termios data.
You might want to control flow control *at boot* with an OF property but
doing it post boot is just busted.
Ah, Yes.
I think OF property should not be here, and it may only be used to determine
the characteristics of the port.
I try to make a fixes patch.
Thanks,
Sugaya Taichi
Alan
Re: [PATCH] serial: Fix using plain integer instead of Null pointer
Hi,
On 2019/04/18 15:40, Greg Kroah-Hartman wrote:
On Thu, Apr 18, 2019 at 03:21:25PM +0900, Sugaya Taichi wrote:
Fix build warning that using plain integer as Null pointer.
This is reported by kbuild test robot.
Fixes: ba44dc043004 ("serial: Add Milbeaut serial control")
Signed-off-by: Sugaya Taichi
---
drivers/tty/serial/milbeaut_usio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Using a "Reported-by:" tag is usually a good idea. I'll add it when I
apply the patch, but for next time can you please add it?
Yes, of course!
I will add the tag in the next chance.
Thanks a lot!
Sugaya Taichi
thanks,
greg k-h
[PATCH] serial: Fix using plain integer instead of Null pointer
Fix build warning that using plain integer as Null pointer.
This is reported by kbuild test robot.
Fixes: ba44dc043004 ("serial: Add Milbeaut serial control")
Signed-off-by: Sugaya Taichi
---
drivers/tty/serial/milbeaut_usio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/milbeaut_usio.c
b/drivers/tty/serial/milbeaut_usio.c
index d303b7d..4a10604 100644
--- a/drivers/tty/serial/milbeaut_usio.c
+++ b/drivers/tty/serial/milbeaut_usio.c
@@ -500,7 +500,7 @@ static int __init mlb_usio_early_console_setup(struct
earlycon_device *device,
static int mlb_usio_probe(struct platform_device *pdev)
{
- struct clk *clk = devm_clk_get(>dev, 0);
+ struct clk *clk = devm_clk_get(>dev, NULL);
struct uart_port *port;
struct resource *res;
int index = 0;
--
1.9.1
Re: [PATCH v3] serial: Add Milbeaut serial control
Hi, On 2019/04/18 14:17, Greg Kroah-Hartman wrote: On Thu, Apr 18, 2019 at 11:51:56AM +0900, Sugaya Taichi wrote: Add Milbeaut serial control including earlycon and console. Signed-off-by: Sugaya Taichi --- Changes from v2: - Fix build warning. No, I only need an incremental patch fixing the one sparse warning found, not a whole new patch as I have already merged your original patch, right? Sorry for my misunderstanding. I got it. Thanks, Sugaya Taichi thanks, greg k-h
[PATCH v3] serial: Add Milbeaut serial control
Add Milbeaut serial control including earlycon and console. Signed-off-by: Sugaya Taichi --- Changes from v2: - Fix build warning. Changes from v1: - Add "COMPILE_TEST" dependency for coverage test. drivers/tty/serial/Kconfig | 26 ++ drivers/tty/serial/Makefile| 1 + drivers/tty/serial/milbeaut_usio.c | 621 + include/uapi/linux/serial_core.h | 3 + 4 files changed, 651 insertions(+) create mode 100644 drivers/tty/serial/milbeaut_usio.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 72966bc..d1971a8 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1582,6 +1582,32 @@ config SERIAL_RDA_CONSOLE Say 'Y' here if you wish to use the RDA8810PL UART as the system console. Only earlycon is implemented currently. +config SERIAL_MILBEAUT_USIO + tristate "Milbeaut USIO/UART serial port support" + depends on ARCH_MILBEAUT || (COMPILE_TEST && OF) + default ARCH_MILBEAUT + select SERIAL_CORE + help + This selects the USIO/UART IP found in Socionext Milbeaut SoCs. + +config SERIAL_MILBEAUT_USIO_PORTS + int "Maximum number of CSIO/UART ports (1-8)" + range 1 8 + depends on SERIAL_MILBEAUT_USIO + default "4" + +config SERIAL_MILBEAUT_USIO_CONSOLE + bool "Support for console on MILBEAUT USIO/UART serial port" + depends on SERIAL_MILBEAUT_USIO=y + default y + select SERIAL_CORE_CONSOLE + select SERIAL_EARLYCON + help + Say 'Y' here if you wish to use a USIO/UART of Socionext Milbeaut + SoCs as the system console (the system console is the device which + receives all kernel messages and warnings and which allows logins in + single user mode). + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 40b702a..43ca2d0 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_SERIAL_PIC32)+= pic32_uart.o obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o obj-$(CONFIG_SERIAL_OWL) += owl-uart.o obj-$(CONFIG_SERIAL_RDA) += rda-uart.o +obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o # GPIOLIB helpers for modem control lines obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o diff --git a/drivers/tty/serial/milbeaut_usio.c b/drivers/tty/serial/milbeaut_usio.c new file mode 100644 index 000..4a10604 --- /dev/null +++ b/drivers/tty/serial/milbeaut_usio.c @@ -0,0 +1,621 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + */ + +#if defined(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#define USIO_NAME "mlb-usio-uart" +#define USIO_UART_DEV_NAME "ttyUSI" + +static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS]; + +#define RX 0 +#define TX 1 +static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2]; + +#define MLB_USIO_REG_SMR 0 +#define MLB_USIO_REG_SCR 1 +#define MLB_USIO_REG_ESCR 2 +#define MLB_USIO_REG_SSR 3 +#define MLB_USIO_REG_DR4 +#define MLB_USIO_REG_BGR 6 +#define MLB_USIO_REG_FCR 12 +#define MLB_USIO_REG_FBYTE 14 + +#define MLB_USIO_SMR_SOE BIT(0) +#define MLB_USIO_SMR_SBL BIT(3) +#define MLB_USIO_SCR_TXE BIT(0) +#define MLB_USIO_SCR_RXE BIT(1) +#define MLB_USIO_SCR_TBIE BIT(2) +#define MLB_USIO_SCR_TIE BIT(3) +#define MLB_USIO_SCR_RIE BIT(4) +#define MLB_USIO_SCR_UPCL BIT(7) +#define MLB_USIO_ESCR_L_8BIT 0 +#define MLB_USIO_ESCR_L_5BIT 1 +#define MLB_USIO_ESCR_L_6BIT 2 +#define MLB_USIO_ESCR_L_7BIT 3 +#define MLB_USIO_ESCR_PBIT(3) +#define MLB_USIO_ESCR_PEN BIT(4) +#define MLB_USIO_ESCR_FLWENBIT(7) +#define MLB_USIO_SSR_TBI BIT(0) +#define MLB_USIO_SSR_TDRE BIT(1) +#define MLB_USIO_SSR_RDRF BIT(2) +#define MLB_USIO_SSR_ORE BIT(3) +#define MLB_USIO_SSR_FRE BIT(4) +#define MLB_USIO_SSR_PEBIT(5) +#define MLB_USIO_SSR_REC BIT(7) +#define MLB_USIO_SSR_BRK BIT(8) +#define MLB_USIO_FCR_FE1 BIT(0) +#define MLB_USIO_FCR_FE2 BIT(1) +#define MLB_USIO_FCR_FCL1 BIT(2) +#define MLB_USIO_FCR_FCL2 BIT(3) +#define MLB_USIO_FCR_FSET BIT(4) +#define MLB_USIO_FCR_FTIE BIT(9) +#define MLB_USIO_FCR_FDRQ B
[PATCH v2] serial: Add Milbeaut serial control
Add Milbeaut serial control including earlycon and console. Signed-off-by: Sugaya Taichi --- Changes from v1: - Add "COMPILE_TEST" dependency for coverage test. drivers/tty/serial/Kconfig | 26 ++ drivers/tty/serial/Makefile| 1 + drivers/tty/serial/milbeaut_usio.c | 621 + include/uapi/linux/serial_core.h | 3 + 4 files changed, 651 insertions(+) create mode 100644 drivers/tty/serial/milbeaut_usio.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 72966bc..d1971a8 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1582,6 +1582,32 @@ config SERIAL_RDA_CONSOLE Say 'Y' here if you wish to use the RDA8810PL UART as the system console. Only earlycon is implemented currently. +config SERIAL_MILBEAUT_USIO + tristate "Milbeaut USIO/UART serial port support" + depends on ARCH_MILBEAUT || (COMPILE_TEST && OF) + default ARCH_MILBEAUT + select SERIAL_CORE + help + This selects the USIO/UART IP found in Socionext Milbeaut SoCs. + +config SERIAL_MILBEAUT_USIO_PORTS + int "Maximum number of CSIO/UART ports (1-8)" + range 1 8 + depends on SERIAL_MILBEAUT_USIO + default "4" + +config SERIAL_MILBEAUT_USIO_CONSOLE + bool "Support for console on MILBEAUT USIO/UART serial port" + depends on SERIAL_MILBEAUT_USIO=y + default y + select SERIAL_CORE_CONSOLE + select SERIAL_EARLYCON + help + Say 'Y' here if you wish to use a USIO/UART of Socionext Milbeaut + SoCs as the system console (the system console is the device which + receives all kernel messages and warnings and which allows logins in + single user mode). + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 40b702a..43ca2d0 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_SERIAL_PIC32)+= pic32_uart.o obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o obj-$(CONFIG_SERIAL_OWL) += owl-uart.o obj-$(CONFIG_SERIAL_RDA) += rda-uart.o +obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o # GPIOLIB helpers for modem control lines obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o diff --git a/drivers/tty/serial/milbeaut_usio.c b/drivers/tty/serial/milbeaut_usio.c new file mode 100644 index 000..d303b7d --- /dev/null +++ b/drivers/tty/serial/milbeaut_usio.c @@ -0,0 +1,621 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + */ + +#if defined(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#define USIO_NAME "mlb-usio-uart" +#define USIO_UART_DEV_NAME "ttyUSI" + +static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS]; + +#define RX 0 +#define TX 1 +static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2]; + +#define MLB_USIO_REG_SMR 0 +#define MLB_USIO_REG_SCR 1 +#define MLB_USIO_REG_ESCR 2 +#define MLB_USIO_REG_SSR 3 +#define MLB_USIO_REG_DR4 +#define MLB_USIO_REG_BGR 6 +#define MLB_USIO_REG_FCR 12 +#define MLB_USIO_REG_FBYTE 14 + +#define MLB_USIO_SMR_SOE BIT(0) +#define MLB_USIO_SMR_SBL BIT(3) +#define MLB_USIO_SCR_TXE BIT(0) +#define MLB_USIO_SCR_RXE BIT(1) +#define MLB_USIO_SCR_TBIE BIT(2) +#define MLB_USIO_SCR_TIE BIT(3) +#define MLB_USIO_SCR_RIE BIT(4) +#define MLB_USIO_SCR_UPCL BIT(7) +#define MLB_USIO_ESCR_L_8BIT 0 +#define MLB_USIO_ESCR_L_5BIT 1 +#define MLB_USIO_ESCR_L_6BIT 2 +#define MLB_USIO_ESCR_L_7BIT 3 +#define MLB_USIO_ESCR_PBIT(3) +#define MLB_USIO_ESCR_PEN BIT(4) +#define MLB_USIO_ESCR_FLWENBIT(7) +#define MLB_USIO_SSR_TBI BIT(0) +#define MLB_USIO_SSR_TDRE BIT(1) +#define MLB_USIO_SSR_RDRF BIT(2) +#define MLB_USIO_SSR_ORE BIT(3) +#define MLB_USIO_SSR_FRE BIT(4) +#define MLB_USIO_SSR_PEBIT(5) +#define MLB_USIO_SSR_REC BIT(7) +#define MLB_USIO_SSR_BRK BIT(8) +#define MLB_USIO_FCR_FE1 BIT(0) +#define MLB_USIO_FCR_FE2 BIT(1) +#define MLB_USIO_FCR_FCL1 BIT(2) +#define MLB_USIO_FCR_FCL2 BIT(3) +#define MLB_USIO_FCR_FSET BIT(4) +#define MLB_USIO_FCR_FTIE BIT(9) +#define MLB_USIO_FCR_FDRQ BIT(10) +#define MLB_USI
Re: [PATCH v2 0/3] Bugfix and cleanup the timer driver for Milbeaut M10V
Hi, On 2019/04/12 20:09, Daniel Lezcano wrote: On 12/04/2019 09:36, Sugaya Taichi wrote: This series fixes a bug and cleanup code about timer driver for Milbeaut M10V. Since it is difficult to separate, it is integrated into a series. Changes from v1: -Add "Fixes" tag. Sugaya Taichi (3): clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer clocksource/drivers/timer-milbeaut: Add shutdown function clocksource/drivers/timer-milbeaut: Cleanup common register accesses drivers/clocksource/timer-milbeaut.c | 66 +--- 1 file changed, 47 insertions(+), 19 deletions(-) Series applied for 5.2 Thanks -- Daniel Thank you!
[PATCH v2 3/3] clocksource/drivers/timer-milbeaut: Cleanup common register accesses
Aggregate common register accesses into shared functions for
maintainability.
Signed-off-by: Sugaya Taichi
---
drivers/clocksource/timer-milbeaut.c | 62 +++-
1 file changed, 39 insertions(+), 23 deletions(-)
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
index f478061..fa9fb4e 100644
--- a/drivers/clocksource/timer-milbeaut.c
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -26,8 +26,8 @@
#define MLB_TMR_TMCSR_CSL_DIV2 0
#define MLB_TMR_DIV_CNT2
-#define MLB_TMR_SRC_CH (1)
-#define MLB_TMR_EVT_CH (0)
+#define MLB_TMR_SRC_CH 1
+#define MLB_TMR_EVT_CH 0
#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
@@ -43,6 +43,8 @@
#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
#define MLB_TIMER_RATING 500
+#define MLB_TIMER_ONESHOT 0
+#define MLB_TIMER_PERIODIC 1
static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
{
@@ -59,38 +61,53 @@ static irqreturn_t mlb_timer_interrupt(int irq, void
*dev_id)
return IRQ_HANDLED;
}
-static int mlb_set_state_periodic(struct clock_event_device *clk)
+static void mlb_evt_timer_start(struct timer_of *to, bool periodic)
{
- struct timer_of *to = to_timer_of(clk);
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+ val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ if (periodic)
+ val |= MLB_TMR_TMCSR_RELD;
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+}
+
+static void mlb_evt_timer_stop(struct timer_of *to)
+{
+ u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
- writel_relaxed(to->of_clk.period, timer_of_base(to) +
- MLB_TMR_EVT_TMRLR1_OFS);
- val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
- MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ val &= ~MLB_TMR_TMCSR_CNTE;
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+}
+
+static void mlb_evt_timer_register_count(struct timer_of *to, unsigned long
cnt)
+{
+ writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
+}
+
+static int mlb_set_state_periodic(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ mlb_evt_timer_stop(to);
+ mlb_evt_timer_register_count(to, to->of_clk.period);
+ mlb_evt_timer_start(to, MLB_TIMER_PERIODIC);
return 0;
}
static int mlb_set_state_oneshot(struct clock_event_device *clk)
{
struct timer_of *to = to_timer_of(clk);
- u32 val = MLB_TMR_TMCSR_CSL_DIV2;
- writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
- val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
- writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ mlb_evt_timer_stop(to);
+ mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
return 0;
}
static int mlb_set_state_shutdown(struct clock_event_device *clk)
{
struct timer_of *to = to_timer_of(clk);
- u32 val = MLB_TMR_TMCSR_CSL_DIV2;
- writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ mlb_evt_timer_stop(to);
return 0;
}
@@ -99,22 +116,21 @@ static int mlb_clkevt_next_event(unsigned long event,
{
struct timer_of *to = to_timer_of(clk);
- writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
- writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
- MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
- MLB_TMR_TMCSR_TRG, timer_of_base(to) +
- MLB_TMR_EVT_TMCSR_OFS);
+ mlb_evt_timer_stop(to);
+ mlb_evt_timer_register_count(to, event);
+ mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
return 0;
}
static int mlb_config_clock_source(struct timer_of *to)
{
- writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
- writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
- writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
- MLB_TMR_SRC_TMCSR_OFS);
+ val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
return 0;
}
--
1.9.1
[PATCH v2 1/3] clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer
Fix mlb_set_oneshot_state() to enable one-shot timer.
The function should stop and start a timer, but "start" statement was
dropped. Kick the register to start one-shot timer.
Fixes: b58f28f306db ("clocksource/drivers/timer-milbeaut: Introduce timer for
Milbeaut SoCs")
Signed-off-by: Sugaya Taichi
---
drivers/clocksource/timer-milbeaut.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
index f2019a8..9fd5d08 100644
--- a/drivers/clocksource/timer-milbeaut.c
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -80,6 +80,8 @@ static int mlb_set_state_oneshot(struct clock_event_device
*clk)
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
return 0;
}
--
1.9.1
[PATCH v2 2/3] clocksource/drivers/timer-milbeaut: Add shutdown function
Add a shutdown operation to support shutdown timer.
Signed-off-by: Sugaya Taichi
---
drivers/clocksource/timer-milbeaut.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
index 9fd5d08..f478061 100644
--- a/drivers/clocksource/timer-milbeaut.c
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -85,6 +85,15 @@ static int mlb_set_state_oneshot(struct clock_event_device
*clk)
return 0;
}
+static int mlb_set_state_shutdown(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
static int mlb_clkevt_next_event(unsigned long event,
struct clock_event_device *clk)
{
@@ -125,6 +134,7 @@ static int mlb_config_clock_event(struct timer_of *to)
.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
.set_state_oneshot = mlb_set_state_oneshot,
.set_state_periodic = mlb_set_state_periodic,
+ .set_state_shutdown = mlb_set_state_shutdown,
.set_next_event = mlb_clkevt_next_event,
},
--
1.9.1
[PATCH v2 0/3] Bugfix and cleanup the timer driver for Milbeaut M10V
This series fixes a bug and cleanup code about timer driver for Milbeaut M10V. Since it is difficult to separate, it is integrated into a series. Changes from v1: -Add "Fixes" tag. Sugaya Taichi (3): clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer clocksource/drivers/timer-milbeaut: Add shutdown function clocksource/drivers/timer-milbeaut: Cleanup common register accesses drivers/clocksource/timer-milbeaut.c | 66 +--- 1 file changed, 47 insertions(+), 19 deletions(-) -- 1.9.1
Re: [PATCH 1/3] clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer
Hi, Thank you for your comment. On 2019/04/12 5:08, Daniel Lezcano wrote: On 25/03/2019 04:05, Sugaya Taichi wrote: Fix mlb_set_oneshot_state() to enable one-shot timer. The function should stop and start a timer, but "start" statement was dropped. Kick the register to start one-shot timer. Can you add the "Fixes" tag please. I got it, will resend with correct form. Thanks, Sugaya Taichi Signed-off-by: Sugaya Taichi --- drivers/clocksource/timer-milbeaut.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clocksource/timer-milbeaut.c b/drivers/clocksource/timer-milbeaut.c index f2019a8..9fd5d08 100644 --- a/drivers/clocksource/timer-milbeaut.c +++ b/drivers/clocksource/timer-milbeaut.c @@ -80,6 +80,8 @@ static int mlb_set_state_oneshot(struct clock_event_device *clk) u32 val = MLB_TMR_TMCSR_CSL_DIV2; writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); return 0; }
Re: [PATCH 0/3] Bugfix and cleanup the timer driver for Milbeaut M10V
This is ping.. Does anyone have any comments? On 2019/03/25 12:05, Sugaya Taichi wrote: This series fixes a bug and cleanup code about timer driver for Milbeaut M10V. Since it is difficult to separate, it is integrated into a series. Sugaya Taichi (3): clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer clocksource/drivers/timer-milbeaut: Add shutdown function clocksource/drivers/timer-milbeaut: Cleanup common register accesses drivers/clocksource/timer-milbeaut.c | 66 +--- 1 file changed, 47 insertions(+), 19 deletions(-)
Re: [PATCH] dt-bindings: cpu: Fix JSON schema
On 2019/04/08 7:13, Olof Johansson wrote:
On Tue, Apr 02, 2019 at 08:42:02PM +0900, Sugaya, Taichi wrote:
Hi,
On 2019/04/01 22:02, Sugaya, Taichi wrote:
Hi,
On 2019/04/01 20:35, Maxime Ripard wrote:
Hi,
On Mon, Apr 01, 2019 at 07:52:06PM +0900, Sugaya, Taichi wrote:
On 2019/04/01 18:10, Maxime Ripard wrote:
Hi Sugaya, Arnd, Olof,
On Thu, Mar 28, 2019 at 02:35:54PM -0500, Rob Herring wrote:
+arm-soc
On Mon, Mar 18, 2019 at 5:05 AM Maxime Ripard wrote:
Commit fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for
Milbeaut") added support for a new cpu enable-method, but did so using
tabulations to ident. This is however invalid in the syntax, and resulted
in a failure when trying to use that schemas for validation.
Use spaces instead of tabs to indent to fix this.
Fixes: fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for Milbeaut")
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rob Herring
This should be applied to arm-soc tree having the commit.
Could you pick up that patch?
I got it.
My mission is to resubmit your fix-patch added my singned-off tag and
Rob's reviewed tag...right?
If you are part of arm-soc and send your pull requests to Arnd and
Olof, simply pick it up in the same branch than the initial patch was
in. And when you apply that patch, you indeed need to add your
Signed-off-by (note that most commands to commit have an option to do
that automatically: -s and that includes git am) and the Rob's
reviewed-by.
Then, send a new pull request to arm-soc.
Okay, thanks for your suggestion.
I try to make pull request!
Sorry I realized that I couldn't make a private repository, so I'll send my Ack
instead.
Acked-by: Sugaya Taichi
Applied to arm/fixes now. Thanks!
-Olof
Thank you for appling!
Re: [PATCH] dt-bindings: cpu: Fix JSON schema
On 2019/04/02 20:42, Sugaya, Taichi wrote:
Hi,
On 2019/04/01 22:02, Sugaya, Taichi wrote:
Hi,
On 2019/04/01 20:35, Maxime Ripard wrote:
Hi,
On Mon, Apr 01, 2019 at 07:52:06PM +0900, Sugaya, Taichi wrote:
On 2019/04/01 18:10, Maxime Ripard wrote:
Hi Sugaya, Arnd, Olof,
On Thu, Mar 28, 2019 at 02:35:54PM -0500, Rob Herring wrote:
+arm-soc
On Mon, Mar 18, 2019 at 5:05 AM Maxime Ripard wrote:
Commit fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for
Milbeaut") added support for a new cpu enable-method, but did so using
tabulations to ident. This is however invalid in the syntax, and resulted
in a failure when trying to use that schemas for validation.
Use spaces instead of tabs to indent to fix this.
Fixes: fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for Milbeaut")
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rob Herring
This should be applied to arm-soc tree having the commit.
Could you pick up that patch?
I got it.
My mission is to resubmit your fix-patch added my singned-off tag and
Rob's reviewed tag...right?
If you are part of arm-soc and send your pull requests to Arnd and
Olof, simply pick it up in the same branch than the initial patch was
in. And when you apply that patch, you indeed need to add your
Signed-off-by (note that most commands to commit have an option to do
that automatically: -s and that includes git am) and the Rob's
reviewed-by.
Then, send a new pull request to arm-soc.
Okay, thanks for your suggestion.
I try to make pull request!
Sorry I realized that I couldn't make a private repository, so I'll send my Ack
instead.
One correction: "a public repository"
Acked-by: Sugaya Taichi
Thanks,
Sugaya Taichi
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Re: [PATCH] dt-bindings: cpu: Fix JSON schema
Hi,
On 2019/04/01 22:02, Sugaya, Taichi wrote:
Hi,
On 2019/04/01 20:35, Maxime Ripard wrote:
Hi,
On Mon, Apr 01, 2019 at 07:52:06PM +0900, Sugaya, Taichi wrote:
On 2019/04/01 18:10, Maxime Ripard wrote:
Hi Sugaya, Arnd, Olof,
On Thu, Mar 28, 2019 at 02:35:54PM -0500, Rob Herring wrote:
+arm-soc
On Mon, Mar 18, 2019 at 5:05 AM Maxime Ripard wrote:
Commit fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for
Milbeaut") added support for a new cpu enable-method, but did so using
tabulations to ident. This is however invalid in the syntax, and resulted
in a failure when trying to use that schemas for validation.
Use spaces instead of tabs to indent to fix this.
Fixes: fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for Milbeaut")
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rob Herring
This should be applied to arm-soc tree having the commit.
Could you pick up that patch?
I got it.
My mission is to resubmit your fix-patch added my singned-off tag and
Rob's reviewed tag...right?
If you are part of arm-soc and send your pull requests to Arnd and
Olof, simply pick it up in the same branch than the initial patch was
in. And when you apply that patch, you indeed need to add your
Signed-off-by (note that most commands to commit have an option to do
that automatically: -s and that includes git am) and the Rob's
reviewed-by.
Then, send a new pull request to arm-soc.
Okay, thanks for your suggestion.
I try to make pull request!
Sorry I realized that I couldn't make a private repository, so I'll send my Ack
instead.
Acked-by: Sugaya Taichi
Thanks,
Sugaya Taichi
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Re: [PATCH] dt-bindings: cpu: Fix JSON schema
Hi,
On 2019/04/01 20:35, Maxime Ripard wrote:
Hi,
On Mon, Apr 01, 2019 at 07:52:06PM +0900, Sugaya, Taichi wrote:
On 2019/04/01 18:10, Maxime Ripard wrote:
Hi Sugaya, Arnd, Olof,
On Thu, Mar 28, 2019 at 02:35:54PM -0500, Rob Herring wrote:
+arm-soc
On Mon, Mar 18, 2019 at 5:05 AM Maxime Ripard wrote:
Commit fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for
Milbeaut") added support for a new cpu enable-method, but did so using
tabulations to ident. This is however invalid in the syntax, and resulted
in a failure when trying to use that schemas for validation.
Use spaces instead of tabs to indent to fix this.
Fixes: fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for Milbeaut")
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rob Herring
This should be applied to arm-soc tree having the commit.
Could you pick up that patch?
I got it.
My mission is to resubmit your fix-patch added my singned-off tag and
Rob's reviewed tag...right?
If you are part of arm-soc and send your pull requests to Arnd and
Olof, simply pick it up in the same branch than the initial patch was
in. And when you apply that patch, you indeed need to add your
Signed-off-by (note that most commands to commit have an option to do
that automatically: -s and that includes git am) and the Rob's
reviewed-by.
Then, send a new pull request to arm-soc.
Okay, thanks for your suggestion.
I try to make pull request!
Thanks,
Sugaya Taichi
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Re: [PATCH] dt-bindings: cpu: Fix JSON schema
Hi Maxime,
Thanks for pointing my bug.
On 2019/04/01 18:10, Maxime Ripard wrote:
Hi Sugaya, Arnd, Olof,
On Thu, Mar 28, 2019 at 02:35:54PM -0500, Rob Herring wrote:
+arm-soc
On Mon, Mar 18, 2019 at 5:05 AM Maxime Ripard wrote:
Commit fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for
Milbeaut") added support for a new cpu enable-method, but did so using
tabulations to ident. This is however invalid in the syntax, and resulted
in a failure when trying to use that schemas for validation.
Use spaces instead of tabs to indent to fix this.
Fixes: fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for Milbeaut")
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rob Herring
This should be applied to arm-soc tree having the commit.
Could you pick up that patch?
I got it.
My mission is to resubmit your fix-patch added my singned-off tag and
Rob's reviewed tag...right?
Thanks,
Sugaya Taichi
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Re: [PATCH] serial: Add Milbeaut serial control
Hi Thank you for your comments. On 2019/03/26 18:57, Arnd Bergmann wrote: On Tue, Mar 26, 2019 at 10:13 AM Sugaya Taichi wrote: diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 72966bc..961519b 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1582,6 +1582,32 @@ config SERIAL_RDA_CONSOLE Say 'Y' here if you wish to use the RDA8810PL UART as the system console. Only earlycon is implemented currently. +config SERIAL_MILBEAUT_USIO + tristate "Milbeaut USIO/UART serial port support" + depends on ARCH_MILBEAUT + default y + select SERIAL_CORE + help + This selects the USIO/UART IP found in Socionext Milbeaut SoCs. In general, it would be good to make it possible to build this on other architectures for better compile test coverage, e.g. like config SERIAL_MILBEAUT_USIO tristate "Milbeaut USIO/UART serial port support" depends on ARCH_MILBEAUT || COMPILE_TEST default ARCH_MILBEAUT All right. I agree with the style. You might need additional dependencies like 'depends on OF' to make this work reliably. I got it. I think the way is inserting "depends on OF" as a new line. Thanks, Sugaya Taichi Arnd
[PATCH] serial: Add Milbeaut serial control
Add Milbeaut serial control including earlycon and console.
Signed-off-by: Sugaya Taichi
---
drivers/tty/serial/Kconfig | 26 ++
drivers/tty/serial/Makefile| 1 +
drivers/tty/serial/milbeaut_usio.c | 621 +
include/uapi/linux/serial_core.h | 3 +
4 files changed, 651 insertions(+)
create mode 100644 drivers/tty/serial/milbeaut_usio.c
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 72966bc..961519b 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1582,6 +1582,32 @@ config SERIAL_RDA_CONSOLE
Say 'Y' here if you wish to use the RDA8810PL UART as the system
console. Only earlycon is implemented currently.
+config SERIAL_MILBEAUT_USIO
+ tristate "Milbeaut USIO/UART serial port support"
+ depends on ARCH_MILBEAUT
+ default y
+ select SERIAL_CORE
+ help
+ This selects the USIO/UART IP found in Socionext Milbeaut SoCs.
+
+config SERIAL_MILBEAUT_USIO_PORTS
+ int "Maximum number of CSIO/UART ports (1-8)"
+ range 1 8
+ depends on SERIAL_MILBEAUT_USIO
+ default "4"
+
+config SERIAL_MILBEAUT_USIO_CONSOLE
+ bool "Support for console on MILBEAUT USIO/UART serial port"
+ depends on SERIAL_MILBEAUT_USIO=y
+ default y
+ select SERIAL_CORE_CONSOLE
+ select SERIAL_EARLYCON
+ help
+ Say 'Y' here if you wish to use a USIO/UART of Socionext Milbeaut
+ SoCs as the system console (the system console is the device which
+ receives all kernel messages and warnings and which allows logins in
+ single user mode).
+
endmenu
config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 40b702a..43ca2d0 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_SERIAL_PIC32)+= pic32_uart.o
obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
obj-$(CONFIG_SERIAL_OWL) += owl-uart.o
obj-$(CONFIG_SERIAL_RDA) += rda-uart.o
+obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
# GPIOLIB helpers for modem control lines
obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/milbeaut_usio.c
b/drivers/tty/serial/milbeaut_usio.c
new file mode 100644
index 000..d303b7d
--- /dev/null
+++ b/drivers/tty/serial/milbeaut_usio.c
@@ -0,0 +1,621 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ */
+
+#if defined(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define USIO_NAME "mlb-usio-uart"
+#define USIO_UART_DEV_NAME "ttyUSI"
+
+static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS];
+
+#define RX 0
+#define TX 1
+static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2];
+
+#define MLB_USIO_REG_SMR 0
+#define MLB_USIO_REG_SCR 1
+#define MLB_USIO_REG_ESCR 2
+#define MLB_USIO_REG_SSR 3
+#define MLB_USIO_REG_DR4
+#define MLB_USIO_REG_BGR 6
+#define MLB_USIO_REG_FCR 12
+#define MLB_USIO_REG_FBYTE 14
+
+#define MLB_USIO_SMR_SOE BIT(0)
+#define MLB_USIO_SMR_SBL BIT(3)
+#define MLB_USIO_SCR_TXE BIT(0)
+#define MLB_USIO_SCR_RXE BIT(1)
+#define MLB_USIO_SCR_TBIE BIT(2)
+#define MLB_USIO_SCR_TIE BIT(3)
+#define MLB_USIO_SCR_RIE BIT(4)
+#define MLB_USIO_SCR_UPCL BIT(7)
+#define MLB_USIO_ESCR_L_8BIT 0
+#define MLB_USIO_ESCR_L_5BIT 1
+#define MLB_USIO_ESCR_L_6BIT 2
+#define MLB_USIO_ESCR_L_7BIT 3
+#define MLB_USIO_ESCR_PBIT(3)
+#define MLB_USIO_ESCR_PEN BIT(4)
+#define MLB_USIO_ESCR_FLWENBIT(7)
+#define MLB_USIO_SSR_TBI BIT(0)
+#define MLB_USIO_SSR_TDRE BIT(1)
+#define MLB_USIO_SSR_RDRF BIT(2)
+#define MLB_USIO_SSR_ORE BIT(3)
+#define MLB_USIO_SSR_FRE BIT(4)
+#define MLB_USIO_SSR_PEBIT(5)
+#define MLB_USIO_SSR_REC BIT(7)
+#define MLB_USIO_SSR_BRK BIT(8)
+#define MLB_USIO_FCR_FE1 BIT(0)
+#define MLB_USIO_FCR_FE2 BIT(1)
+#define MLB_USIO_FCR_FCL1 BIT(2)
+#define MLB_USIO_FCR_FCL2 BIT(3)
+#define MLB_USIO_FCR_FSET BIT(4)
+#define MLB_USIO_FCR_FTIE BIT(9)
+#define MLB_USIO_FCR_FDRQ BIT(10)
+#define MLB_USIO_FCR_FRIIE BIT(11)
+
+static void mlb_usio_stop_tx(struct uart_port *port)
+{
+ writew(readw(port->membase
[PATCH 3/3] clocksource/drivers/timer-milbeaut: Cleanup common register accesses
Aggregate common register accesses into shared functions for
maintainability.
Signed-off-by: Sugaya Taichi
---
drivers/clocksource/timer-milbeaut.c | 62 +++-
1 file changed, 39 insertions(+), 23 deletions(-)
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
index f478061..fa9fb4e 100644
--- a/drivers/clocksource/timer-milbeaut.c
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -26,8 +26,8 @@
#define MLB_TMR_TMCSR_CSL_DIV2 0
#define MLB_TMR_DIV_CNT2
-#define MLB_TMR_SRC_CH (1)
-#define MLB_TMR_EVT_CH (0)
+#define MLB_TMR_SRC_CH 1
+#define MLB_TMR_EVT_CH 0
#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
@@ -43,6 +43,8 @@
#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
#define MLB_TIMER_RATING 500
+#define MLB_TIMER_ONESHOT 0
+#define MLB_TIMER_PERIODIC 1
static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
{
@@ -59,38 +61,53 @@ static irqreturn_t mlb_timer_interrupt(int irq, void
*dev_id)
return IRQ_HANDLED;
}
-static int mlb_set_state_periodic(struct clock_event_device *clk)
+static void mlb_evt_timer_start(struct timer_of *to, bool periodic)
{
- struct timer_of *to = to_timer_of(clk);
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+ val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ if (periodic)
+ val |= MLB_TMR_TMCSR_RELD;
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+}
+
+static void mlb_evt_timer_stop(struct timer_of *to)
+{
+ u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
- writel_relaxed(to->of_clk.period, timer_of_base(to) +
- MLB_TMR_EVT_TMRLR1_OFS);
- val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
- MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ val &= ~MLB_TMR_TMCSR_CNTE;
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+}
+
+static void mlb_evt_timer_register_count(struct timer_of *to, unsigned long
cnt)
+{
+ writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
+}
+
+static int mlb_set_state_periodic(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ mlb_evt_timer_stop(to);
+ mlb_evt_timer_register_count(to, to->of_clk.period);
+ mlb_evt_timer_start(to, MLB_TIMER_PERIODIC);
return 0;
}
static int mlb_set_state_oneshot(struct clock_event_device *clk)
{
struct timer_of *to = to_timer_of(clk);
- u32 val = MLB_TMR_TMCSR_CSL_DIV2;
- writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
- val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
- writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ mlb_evt_timer_stop(to);
+ mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
return 0;
}
static int mlb_set_state_shutdown(struct clock_event_device *clk)
{
struct timer_of *to = to_timer_of(clk);
- u32 val = MLB_TMR_TMCSR_CSL_DIV2;
- writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ mlb_evt_timer_stop(to);
return 0;
}
@@ -99,22 +116,21 @@ static int mlb_clkevt_next_event(unsigned long event,
{
struct timer_of *to = to_timer_of(clk);
- writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
- writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
- MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
- MLB_TMR_TMCSR_TRG, timer_of_base(to) +
- MLB_TMR_EVT_TMCSR_OFS);
+ mlb_evt_timer_stop(to);
+ mlb_evt_timer_register_count(to, event);
+ mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
return 0;
}
static int mlb_config_clock_source(struct timer_of *to)
{
- writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
- writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
- writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
- MLB_TMR_SRC_TMCSR_OFS);
+ val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
return 0;
}
--
1.9.1
[PATCH 0/3] Bugfix and cleanup the timer driver for Milbeaut M10V
This series fixes a bug and cleanup code about timer driver for Milbeaut M10V. Since it is difficult to separate, it is integrated into a series. Sugaya Taichi (3): clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer clocksource/drivers/timer-milbeaut: Add shutdown function clocksource/drivers/timer-milbeaut: Cleanup common register accesses drivers/clocksource/timer-milbeaut.c | 66 +--- 1 file changed, 47 insertions(+), 19 deletions(-) -- 1.9.1
[PATCH 2/3] clocksource/drivers/timer-milbeaut: Add shutdown function
Add a shutdown operation to support shutdown timer.
Signed-off-by: Sugaya Taichi
---
drivers/clocksource/timer-milbeaut.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
index 9fd5d08..f478061 100644
--- a/drivers/clocksource/timer-milbeaut.c
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -85,6 +85,15 @@ static int mlb_set_state_oneshot(struct clock_event_device
*clk)
return 0;
}
+static int mlb_set_state_shutdown(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
static int mlb_clkevt_next_event(unsigned long event,
struct clock_event_device *clk)
{
@@ -125,6 +134,7 @@ static int mlb_config_clock_event(struct timer_of *to)
.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
.set_state_oneshot = mlb_set_state_oneshot,
.set_state_periodic = mlb_set_state_periodic,
+ .set_state_shutdown = mlb_set_state_shutdown,
.set_next_event = mlb_clkevt_next_event,
},
--
1.9.1
[PATCH 1/3] clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer
Fix mlb_set_oneshot_state() to enable one-shot timer. The function should stop and start a timer, but "start" statement was dropped. Kick the register to start one-shot timer. Signed-off-by: Sugaya Taichi --- drivers/clocksource/timer-milbeaut.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clocksource/timer-milbeaut.c b/drivers/clocksource/timer-milbeaut.c index f2019a8..9fd5d08 100644 --- a/drivers/clocksource/timer-milbeaut.c +++ b/drivers/clocksource/timer-milbeaut.c @@ -80,6 +80,8 @@ static int mlb_set_state_oneshot(struct clock_event_device *clk) u32 val = MLB_TMR_TMCSR_CSL_DIV2; writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); return 0; } -- 1.9.1
Re: [PATCH v4 00/10] Add basic support for Socionext Milbeaut M10V SoC
Hi, On 2019/03/01 23:34, Arnd Bergmann wrote: On Wed, Feb 27, 2019 at 5:51 AM Sugaya Taichi wrote: Hi, Here is the series of patches the initial support for SC2000(M10V) of Milbeaut SoCs. "M10V" is the internal name of SC2000, so commonly used in source code. SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for computer vision. It also features advanced functionalities such as 360-degree, real-time spherical stitching with multi cameras, image stabilization for without mechanical gimbals, and rolling shutter correction. More detail is below: https://www.socionext.com/en/products/assp/milbeaut/SC2000.html Specifications for developers are below: - Quad-core 32bit Cortex-A7 on ARMv7-A architecture - NEON support - DSP - GPU - MAX 3GB DDR3 - Cortex-M0 for power control - NAND Flash Interface - SD UHS-I - SD UHS-II - SDIO - USB2.0 HOST / Device - USB3.0 HOST / Device - PCI express Gen2 - Ethernet Engine - I2C - UART - SPI - PWM Support is quite minimal for now, since it only includes timer, clock, pictrl and serial controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals will come eventually. I've merged these all into the arm/newsoc branch now, with the exception of the patch that Greg has already taken. I'll do a little more build testing before that branch will be sent, but I expect it will be fine. Arnd Thanks a lot!
Re: [PATCH v4 07/10] dt-bindings: serial: Add Milbeaut serial driver description
Hi, On 2019/02/28 0:04, Greg Kroah-Hartman wrote: On Wed, Feb 27, 2019 at 01:53:30PM +0900, Sugaya Taichi wrote: Add DT bindings document for Milbeaut serial driver. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../devicetree/bindings/serial/milbeaut-uart.txt| 21 + 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt I have already queued this up in my tty tree for merging in 5.1-rc1. thanks, greg k-h I see. Thank you!
Re: [PATCH v4 03/10] dt-bindings: Add documentation for Milbeaut SoCs
Hi, On 2019/02/27 23:47, Rob Herring wrote: On Tue, Feb 26, 2019 at 10:51 PM Sugaya Taichi wrote: This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- .../bindings/arm/socionext/milbeaut.yaml | 22 ++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml Reviewed-by: Rob Herring Thank you!
[PATCH v4 10/10] ARM: multi_v7_defconfig: add ARCH_MILBEAUT and ARCH_MILBEAUT_M10V
Add and enable the Milbeaut M10V architecture. These configs select those of the clock, timer and serial driver for M10V. Signed-off-by: Sugaya Taichi --- arch/arm/configs/multi_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5bee34a..6753805 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -54,6 +54,8 @@ CONFIG_SOC_VF610=y CONFIG_ARCH_KEYSTONE=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MESON=y +CONFIG_ARCH_MILBEAUT=y +CONFIG_ARCH_MILBEAUT_M10V=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_375=y -- 1.9.1
[PATCH v4 07/10] dt-bindings: serial: Add Milbeaut serial driver description
Add DT bindings document for Milbeaut serial driver.
Signed-off-by: Sugaya Taichi
Reviewed-by: Rob Herring
---
.../devicetree/bindings/serial/milbeaut-uart.txt| 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt
diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
new file mode 100644
index 000..3d2fb1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
@@ -0,0 +1,21 @@
+Socionext Milbeaut UART controller
+
+Required properties:
+- compatible: should be "socionext,milbeaut-usio-uart".
+- reg: offset and length of the register set for the device.
+- interrupts: two interrupts specifier.
+- interrupt-names: should be "rx", "tx".
+- clocks: phandle to the input clock.
+
+Optional properties:
+- auto-flow-control: flow control enable.
+
+Example:
+ usio1: usio_uart@1e700010 {
+ compatible = "socionext,milbeaut-usio-uart";
+ reg = <0x1e700010 0x10>;
+ interrupts = <0 141 0x4>, <0 149 0x4>;
+ interrupt-names = "rx", "tx";
+ clocks = < 2>;
+ auto-flow-control;
+ };
--
1.9.1
[PATCH v4 06/10] clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs
Add timer driver for Milbeaut SoCs series.
The timer has two 32-bit width down counters, one of which is configured
as a clockevent device and the other is configured as a clock source.
Signed-off-by: Sugaya Taichi
Acked-by: Daniel Lezcano
---
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-milbeaut.c | 161 +++
3 files changed, 171 insertions(+)
create mode 100644 drivers/clocksource/timer-milbeaut.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a9e26f6..9101b8f 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -634,4 +634,13 @@ config GX6605S_TIMER
help
This option enables support for gx6605s SOC's timer.
+config MILBEAUT_TIMER
+ bool "Milbeaut timer driver" if COMPILE_TEST
+ depends on OF
+ depends on ARM
+ select TIMER_OF
+ select CLKSRC_MMIO
+ help
+ Enables the support for Milbeaut timer driver.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index cdd210f..6f2543b 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
obj-$(CONFIG_OWL_TIMER)+= timer-owl.o
+obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
obj-$(CONFIG_NPCM7XX_TIMER)+= timer-npcm7xx.o
obj-$(CONFIG_RDA_TIMER)+= timer-rda.o
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
new file mode 100644
index 000..f2019a8
--- /dev/null
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "timer-of.h"
+
+#define MLB_TMR_TMCSR_OFS 0x0
+#define MLB_TMR_TMR_OFS0x4
+#define MLB_TMR_TMRLR1_OFS 0x8
+#define MLB_TMR_TMRLR2_OFS 0xc
+#define MLB_TMR_REGSZPCH 0x10
+
+#define MLB_TMR_TMCSR_OUTL BIT(5)
+#define MLB_TMR_TMCSR_RELD BIT(4)
+#define MLB_TMR_TMCSR_INTE BIT(3)
+#define MLB_TMR_TMCSR_UF BIT(2)
+#define MLB_TMR_TMCSR_CNTE BIT(1)
+#define MLB_TMR_TMCSR_TRG BIT(0)
+
+#define MLB_TMR_TMCSR_CSL_DIV2 0
+#define MLB_TMR_DIV_CNT2
+
+#define MLB_TMR_SRC_CH (1)
+#define MLB_TMR_EVT_CH (0)
+
+#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
+#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
+
+#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_SRC_TMR_OFS(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_EVT_TMR_OFS(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TIMER_RATING 500
+
+static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *clk = dev_id;
+ struct timer_of *to = to_timer_of(clk);
+ u32 val;
+
+ val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ val &= ~MLB_TMR_TMCSR_UF;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ clk->event_handler(clk);
+
+ return IRQ_HANDLED;
+}
+
+static int mlb_set_state_periodic(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ writel_relaxed(to->of_clk.period, timer_of_base(to) +
+ MLB_TMR_EVT_TMRLR1_OFS);
+ val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
+ MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_set_state_oneshot(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_clkevt_next_event(unsigned long event,
+ struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
+ writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
+ MLB_TMR_T
[PATCH v4 09/10] ARM: configs: Add Milbeaut M10V defconfig
This patch adds the minimal defconfig for the Milbeaut M10V. Signed-off-by: Sugaya Taichi --- arch/arm/configs/milbeaut_m10v_defconfig | 119 +++ 1 file changed, 119 insertions(+) create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig new file mode 100644 index 000..7c07f98 --- /dev/null +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -0,0 +1,119 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_CGROUPS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +CONFIG_ARCH_MILBEAUT=y +CONFIG_ARCH_MILBEAUT_M10V=y +CONFIG_ARM_THUMBEE=y +# CONFIG_VDSO is not set +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_ERRATA_798181=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_NR_CPUS=16 +CONFIG_THUMB2_KERNEL=y +# CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 is not set +# CONFIG_ARM_PATCH_IDIV is not set +CONFIG_HIGHMEM=y +CONFIG_FORCE_MAX_ZONEORDER=12 +CONFIG_SECCOMP=y +CONFIG_KEXEC=y +CONFIG_EFI=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_QORIQ_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_EFI_VARS=m +CONFIG_EFI_CAPSULE_LOADER=m +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA1_ARM_CE=m +CONFIG_CRYPTO_SHA2_ARM_CE=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_CRC32_ARM_CE=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_CMA=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_SRAM=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_MATRIXKMAP=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM is not set +CONFIG_GPIOLIB=y +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_HWMON is not set +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_HID is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_SYNC_FILE=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_SOC_BRCMSTB=y +CONFIG_MEMORY=y +# CONFIG_ARM_PMU is not set +CONFIG_EXT4_FS=y +CONFIG_AUTOFS4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_KEYS=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_SEQIV=m +# CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_CCITT=m +CONFIG_CRC_ITU_T=m +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y -- 1.9.1
[PATCH v4 08/10] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
Add devicetree for Milbeaut M10V SoC and M10V Evaluation board.
Signed-off-by: Sugaya Taichi
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32 +++
arch/arm/boot/dts/milbeaut-m10v.dtsi| 95 +
3 files changed, 128 insertions(+)
create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts
create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bd40148..f697d87 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1233,6 +1233,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
+dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts
b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
new file mode 100644
index 000..614f60c
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Socionext Milbeaut M10V Evaluation Board */
+/dts-v1/;
+#include "milbeaut-m10v.dtsi"
+
+/ {
+ model = "Socionext M10V EVB";
+ compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ bootargs = "rootwait earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ uclk40xi: uclk40xi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000>;
+ };
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x8000>;
+ };
+
+};
diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi
b/arch/arm/boot/dts/milbeaut-m10v.dtsi
new file mode 100644
index 000..aa7c6ca
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "socionext,sc2000a";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "socionext,milbeaut-m10v-smp";
+ cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ };
+ cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ };
+ cpu@f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ };
+ cpu@f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ };
+ };
+
+ timer { /* The Generic Timer */
+ compatible = "arm,armv7-timer";
+ interrupts = ,
+ ,
+ ,
+ ;
+ clock-frequency = <4000>;
+ always-on;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <>;
+
+ gic: interrupt-controller@1d00 {
+ compatible = "arm,cortex-a7-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x1d001000 0x1000>,
+ <0x1d002000 0x1000>; /* CPU I/f base and size */
+ };
+
+ timer@1e50 { /* 32-bit Reload Timers */
+ compatible = "socionext,milbeaut-timer";
+ reg = <0x1e50 0x20>;
+ interrupts = <0 91 4>;
+ };
+
+ uart1: serial@1e700010 { /* PE4, PE5 */
+ /* Enable this as ttyUSI0 */
+ compatible = "socionext,milbeaut-usio-uart";
+ reg = <0x1e700010 0x10>;
+ interrupts = <0 141 0x4>, <0 149 0x4>;
+
[PATCH v4 04/10] ARM: milbeaut: Add basic support for Milbeaut m10v SoC
This adds the basic M10V SoC support under arch/arm.
Since all cores are activated in the custom bootloader before booting
linux, it is necessary to wait for the secondary-cores using cpu-enable-
method and special sram.
Signed-off-by: Sugaya Taichi
---
arch/arm/Kconfig | 2 +
arch/arm/Makefile| 1 +
arch/arm/mach-milbeaut/Kconfig | 20 ++
arch/arm/mach-milbeaut/Makefile | 1 +
arch/arm/mach-milbeaut/platsmp.c | 143 +++
5 files changed, 167 insertions(+)
create mode 100644 arch/arm/mach-milbeaut/Kconfig
create mode 100644 arch/arm/mach-milbeaut/Makefile
create mode 100644 arch/arm/mach-milbeaut/platsmp.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 26524b7..bf46372 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -750,6 +750,8 @@ source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-meson/Kconfig"
+source "arch/arm/mach-milbeaut/Kconfig"
+
source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-moxart/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9db3c58..0e9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_MXC) += imx
machine-$(CONFIG_ARCH_MEDIATEK)+= mediatek
+machine-$(CONFIG_ARCH_MILBEAUT)+= milbeaut
machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_NETX)+= netx
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
diff --git a/arch/arm/mach-milbeaut/Kconfig b/arch/arm/mach-milbeaut/Kconfig
new file mode 100644
index 000..6a576fd
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Kconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0
+menuconfig ARCH_MILBEAUT
+ bool "Socionext Milbeaut SoCs"
+ depends on ARCH_MULTI_V7
+ select ARM_GIC
+ help
+ This enables support for Socionext Milbeaut SoCs
+
+if ARCH_MILBEAUT
+
+config ARCH_MILBEAUT_M10V
+ bool "Milbeaut SC2000/M10V platform"
+ select ARM_ARCH_TIMER
+ select MILBEAUT_TIMER
+ select PINCTRL
+ select PINCTRL_MILBEAUT
+ help
+ Support for Socionext's MILBEAUT M10V based systems
+
+endif
diff --git a/arch/arm/mach-milbeaut/Makefile b/arch/arm/mach-milbeaut/Makefile
new file mode 100644
index 000..ce5ea06
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-milbeaut/platsmp.c b/arch/arm/mach-milbeaut/platsmp.c
new file mode 100644
index 000..591543c
--- /dev/null
+++ b/arch/arm/mach-milbeaut/platsmp.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright: (C) 2018 Socionext Inc.
+ * Copyright: (C) 2015 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define M10V_MAX_CPU 4
+#define KERNEL_UNBOOT_FLAG 0x12345678
+
+static void __iomem *m10v_smp_base;
+
+static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
+{
+ unsigned int mpidr, cpu, cluster;
+
+ if (!m10v_smp_base)
+ return -ENXIO;
+
+ mpidr = cpu_logical_map(l_cpu);
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ if (cpu >= M10V_MAX_CPU)
+ return -EINVAL;
+
+ pr_info("%s: cpu %u l_cpu %u cluster %u\n",
+ __func__, cpu, l_cpu, cluster);
+
+ writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);
+ arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
+
+ return 0;
+}
+
+static void m10v_smp_init(unsigned int max_cpus)
+{
+ unsigned int mpidr, cpu, cluster;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram");
+ if (!np)
+ return;
+
+ m10v_smp_base = of_iomap(np, 0);
+ if (!m10v_smp_base)
+ return;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster);
+
+ for (cpu = 0; cpu < M10V_MAX_CPU; cpu++)
+ writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+}
+
+static void m10v_cpu_die(unsigned int l_cpu)
+{
+ gic_cpu_if_down(0);
+ v7_exit_coherency_flush(louis);
+ wfi();
+}
+
+static int m10v_cpu_kill(unsigned int l_cpu)
+{
+ unsigned int mpidr, cpu;
+
+ mpidr = cpu_logical_map(l_cpu);
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
+ writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+
+ return 1;
+}
+
+static struct smp_operations m10v_smp_ops __initdata = {
+ .smp_p
[PATCH v4 02/10] dt-bindings: arm: Add SMP enable-method for Milbeaut
This adds a compatible string "socionext,milbeaut-m10v-smp" for Milbeaut M10V to the 32 bit ARM CPU device tree binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 298c17b..365dcf3 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -228,6 +228,7 @@ patternProperties: - renesas,r9a06g032-smp - rockchip,rk3036-smp - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp - ste,dbx500-smp cpu-release-addr: -- 1.9.1
[PATCH v4 03/10] dt-bindings: Add documentation for Milbeaut SoCs
This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- .../bindings/arm/socionext/milbeaut.yaml | 22 ++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml diff --git a/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml new file mode 100644 index 000..aae53fc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/milbeaut.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Milbeaut platforms device tree bindings + +maintainers: + - Taichi Sugaya + - Takao Orito + +properties: + $nodename: +const: '/' + compatible: +oneOf: + - items: + - enum: + - socionext,milbeaut-m10v-evb + - const: socionext,sc2000a +... -- 1.9.1
[PATCH v4 01/10] dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram
The Milbeaut M10V SoC needs a part of sram for smp, so this adds the
M10V sram compatible and binding.
Signed-off-by: Sugaya Taichi
Reviewed-by: Rob Herring
---
.../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
diff --git a/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
new file mode 100644
index 000..194f6a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
@@ -0,0 +1,24 @@
+Milbeaut SRAM for smp bringup
+
+Milbeaut SoCs use a part of the sram for the bringup of the secondary cores.
+Once they get powered up in the bootloader, they stay at the specific part
+of the sram.
+Therefore the part needs to be added as the sub-node of mmio-sram.
+
+Required sub-node properties:
+- compatible : should be "socionext,milbeaut-smp-sram"
+
+Example:
+
+sram: sram@0 {
+compatible = "mmio-sram";
+reg = <0x0 0x1>;
+#address-cells = <1>;
+#size-cells = <1>;
+ranges = <0 0x0 0x1>;
+
+smp-sram@f100 {
+compatible = "socionext,milbeaut-smp-sram";
+reg = <0xf100 0x20>;
+};
+};
--
1.9.1
[PATCH v4 05/10] dt-bindings: timer: Add Milbeaut M10V timer description
Add DT bindings document for Milbeaut M10V timer.
Signed-off-by: Sugaya Taichi
Reviewed-by: Rob Herring
---
.../bindings/timer/socionext,milbeaut-timer.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
diff --git
a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
new file mode 100644
index 000..ac44c4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
@@ -0,0 +1,17 @@
+Milbeaut SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "socionext,milbeaut-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer.
+- clocks: phandle to the input clk.
+
+Example:
+
+timer {
+ compatible = "socionext,milbeaut-timer";
+ reg = <0x1e50 0x20>
+ interrupts = <0 91 4>;
+ clocks = < 4>;
+};
--
1.9.1
[PATCH v4 00/10] Add basic support for Socionext Milbeaut M10V SoC
Hi, Here is the series of patches the initial support for SC2000(M10V) of Milbeaut SoCs. "M10V" is the internal name of SC2000, so commonly used in source code. SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for computer vision. It also features advanced functionalities such as 360-degree, real-time spherical stitching with multi cameras, image stabilization for without mechanical gimbals, and rolling shutter correction. More detail is below: https://www.socionext.com/en/products/assp/milbeaut/SC2000.html Specifications for developers are below: - Quad-core 32bit Cortex-A7 on ARMv7-A architecture - NEON support - DSP - GPU - MAX 3GB DDR3 - Cortex-M0 for power control - NAND Flash Interface - SD UHS-I - SD UHS-II - SDIO - USB2.0 HOST / Device - USB3.0 HOST / Device - PCI express Gen2 - Ethernet Engine - I2C - UART - SPI - PWM Support is quite minimal for now, since it only includes timer, clock, pictrl and serial controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals will come eventually. Changes since v3: * Add "Reviewed" tag to the dt-binding of the serial driver. * Fix schema string in milbeaut soc binding. * Refine defconfig for milbeaut M10V. * Add milbeaut architecture config to multi_v7_defconfig. Changes since v2: * Drop clk, pinctrl, and serial driver. * Drop unneeded options from defconfig. * Convert milbeaut soc binding to yaml. * Fix serial driver binding. * Change serial id of aliases in DT. * Add platform checking when entering suspend/resume. * Drop pr_err()s. Changes since v1: * Change file names. * Change #define names. * Refine cpu-enable-method and bindigs. * Add documentation for Milbeaut SoCs. * Add more infomation for timer driver. * Add sched_clock to timer driver. * Refine whole of clk driver. * Add earlycon instead of earlyprintk. * Refine Device Tree. Sugaya Taichi (10): dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram dt-bindings: arm: Add SMP enable-method for Milbeaut dt-bindings: Add documentation for Milbeaut SoCs ARM: milbeaut: Add basic support for Milbeaut m10v SoC dt-bindings: timer: Add Milbeaut M10V timer description clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs dt-bindings: serial: Add Milbeaut serial driver description ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board ARM: configs: Add Milbeaut M10V defconfig ARM: multi_v7_defconfig: add ARCH_MILBEAUT and ARCH_MILBEAUT_M10V Documentation/devicetree/bindings/arm/cpus.yaml| 1 + .../bindings/arm/socionext/milbeaut.yaml | 22 +++ .../devicetree/bindings/serial/milbeaut-uart.txt | 21 +++ .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 +++ .../bindings/timer/socionext,milbeaut-timer.txt| 17 +++ arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/milbeaut-m10v-evb.dts| 32 arch/arm/boot/dts/milbeaut-m10v.dtsi | 95 arch/arm/configs/milbeaut_m10v_defconfig | 119 +++ arch/arm/configs/multi_v7_defconfig| 2 + arch/arm/mach-milbeaut/Kconfig | 20 +++ arch/arm/mach-milbeaut/Makefile| 1 + arch/arm/mach-milbeaut/platsmp.c | 143 ++ drivers/clocksource/Kconfig| 9 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-milbeaut.c | 161 + 18 files changed, 672 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig create mode 100644 arch/arm/mach-milbeaut/Kconfig create mode 100644 arch/arm/mach-milbeaut/Makefile create mode 100644 arch/arm/mach-milbeaut/platsmp.c create mode 100644 drivers/clocksource/timer-milbeaut.c -- 1.9.1
Re: [PATCH v3 7/9] dt-bindings: serial: Add Milbeaut serial driver description
Hi Rob, On 2019/02/23 3:38, Rob Herring wrote: On Wed, 20 Feb 2019 16:44:37 +0900, Sugaya Taichi wrote: Add DT bindings document for Milbeaut serial driver. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/serial/milbeaut-uart.txt| 21 + 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt Reviewed-by: Rob Herring Thank you!
Re: [PATCH v2 08/15] clock: milbeaut: Add Milbeaut M10V clock controller
Hi,
Thank you for your comments.
On 2019/02/23 8:57, Stephen Boyd wrote:
Quoting Sugaya Taichi (2019-02-08 04:27:17)
diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c
new file mode 100644
index 000..f798939
--- /dev/null
+++ b/drivers/clk/clk-milbeaut.c
@@ -0,0 +1,626 @@
[]
+struct m10v_clk_div_fixed_data {
+ const char *name;
+ const char *parent_name;
+ u8 div;
+ u8 mult;
+ int onecell_idx;
+};
+struct m10v_clk_mux_factors {
+ const char *name;
+ const char * const *parent_names;
+ u8 num_parents;
+ u32 offset;
+ u8 shift;
+ u8 mask;
+ u32 *table;
+ unsigned long mux_flags;
+ int onecell_idx;
+};
Please add newlines between struct definitions. It also wouldn't hurt to
have kernel-doc on these.
I got it.
+
+static const struct clk_div_table emmcclk_table[] = {
+ { .val = 0, .div = 8 },
+ { .val = 1, .div = 9 },
+ { .val = 2, .div = 10 },
+ { .val = 3, .div = 15 },
+ { .div = 0 },
+};
+static const struct clk_div_table mclk400_table[] = {
+ { .val = 1, .div = 2 },
+ { .val = 3, .div = 4 },
+ { .div = 0 },
+};
+static const struct clk_div_table mclk200_table[] = {
+ { .val = 3, .div = 4 },
+ { .val = 7, .div = 8 },
+ { .div = 0 },
+};
+static const struct clk_div_table aclk400_table[] = {
+ { .val = 1, .div = 2 },
+ { .val = 3, .div = 4 },
+ { .div = 0 },
+};
+static const struct clk_div_table aclk300_table[] = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 3 },
+ { .div = 0 },
+};
+static const struct clk_div_table aclk_table[] = {
+ { .val = 3, .div = 4 },
+ { .val = 7, .div = 8 },
+ { .div = 0 },
+};
+static const struct clk_div_table aclkexs_table[] = {
+ { .val = 3, .div = 4 },
+ { .val = 4, .div = 5 },
+ { .val = 5, .div = 6 },
+ { .val = 7, .div = 8 },
+ { .div = 0 },
+};
+static const struct clk_div_table hclk_table[] = {
+ { .val = 7, .div = 8 },
+ { .val = 15, .div = 16 },
+ { .div = 0 },
+};
+static const struct clk_div_table hclkbmh_table[] = {
+ { .val = 3, .div = 4 },
+ { .val = 7, .div = 8 },
+ { .div = 0 },
+};
+static const struct clk_div_table pclk_table[] = {
+ { .val = 15, .div = 16 },
+ { .val = 31, .div = 32 },
+ { .div = 0 },
+};
+static const struct clk_div_table rclk_table[] = {
+ { .val = 0, .div = 8 },
+ { .val = 1, .div = 16 },
+ { .val = 2, .div = 24 },
+ { .val = 3, .div = 32 },
+ { .div = 0 },
+};
+static const struct clk_div_table uhs1clk0_table[] = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 3 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 8 },
+ { .val = 4, .div = 16 },
+ { .div = 0 },
+};
+static const struct clk_div_table uhs2clk_table[] = {
+ { .val = 0, .div = 9 },
+ { .val = 1, .div = 10 },
+ { .val = 2, .div = 11 },
+ { .val = 3, .div = 12 },
+ { .val = 4, .div = 13 },
+ { .val = 5, .div = 14 },
+ { .val = 6, .div = 16 },
+ { .val = 7, .div = 18 },
+ { .div = 0 },
+};
Same comment applies here. Newlines between tables please.
OK.
+
+static u32 spi_mux_table[] = {0, 1, 2};
+static const char * const spi_mux_names[] = {
+ M10V_SPI_PARENT0, M10V_SPI_PARENT1, M10V_SPI_PARENT2
+};
+
+static u32 uhs1clk2_mux_table[] = {2, 3, 4, 8};
+static const char * const uhs1clk2_mux_names[] = {
+ M10V_UHS1CLK2_PARENT0, M10V_UHS1CLK2_PARENT1,
+ M10V_UHS1CLK2_PARENT2, M10V_PLL6DIV2
+};
+
+static u32 uhs1clk1_mux_table[] = {3, 4, 8};
+static const char * const uhs1clk1_mux_names[] = {
+ M10V_UHS1CLK1_PARENT0, M10V_UHS1CLK1_PARENT1, M10V_PLL6DIV2
+};
+
[...]
+
+static const struct m10v_clk_mux_factors m10v_mux_factor_data[] = {
+ {"spi", spi_mux_names, ARRAY_SIZE(spi_mux_names),
+ CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID},
+ {"uhs1clk2", uhs1clk2_mux_names, ARRAY_SIZE(uhs1clk2_mux_names),
+ CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, -1},
+ {"uhs1clk1", uhs1clk1_mux_names, ARRAY_SIZE(uhs1clk1_mux_names),
+ CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
+ {"nfclk", nfclk_mux_names, ARRAY_SIZE(nfclk_mux_names),
+ CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID},
+};
+
+static u8 m10v_mux_get_parent(struct clk_hw *hw)
+{
+ struct clk_mux *mux = to_clk_mux(hw);
+ u32 val;
+
+ val = clk_readl(mux->reg) >> mux->shift;
Please don't use clk_readl() unless you absolutely need it.
OK, I try to use "readl()" simply.
+ val &= mux->m
Re: [PATCH v3 3/9] dt-bindings: Add documentation for Milbeaut SoCs
Hi, On 2019/02/20 22:33, Rob Herring wrote: On Wed, Feb 20, 2019 at 1:43 AM Sugaya Taichi wrote: This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- .../bindings/arm/socionext/milbeaut.yaml | 22 ++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml diff --git a/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml new file mode 100644 index 000..522396f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/milbeaut.yaml# +$schema: http://devicetree.org/meta-schemas/milbeaut.yaml# This line is wrong. All DT schema should be: http://devicetree.org/meta-schemas/core.yaml# Ah, OK. Fix it soon. Thanks, Sugaya Taichi + +title: Milbeaut platforms device tree bindings + +maintainers: + - Taichi Sugaya + - Takao Orito + +properties: + $nodename: +const: '/' + compatible: +oneOf: + - items: + - enum: + - socionext,milbeaut-m10v-evb + - const: socionext,sc2000a +... -- 1.9.1
Re: [PATCH v3 9/9] ARM: configs: Add Milbeaut M10V defconfig
Hi, On 2019/02/20 22:23, Masami Hiramatsu wrote: Hi Arnd, 2019年2月20日(水) 22:18 Arnd Bergmann : On Wed, Feb 20, 2019 at 2:16 PM Masami Hiramatsu wrote: 2019年2月20日(水) 21:28 Arnd Bergmann : On Wed, Feb 20, 2019 at 12:27 PM Sugaya, Taichi wrote: On 2019/02/20 18:28, Arnd Bergmann wrote: On Wed, Feb 20, 2019 at 8:44 AM Sugaya Taichi wrote: diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig new file mode 100644 index 000..a263211 --- /dev/null +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -0,0 +1,175 @@ I no longer see anything here that should be turned off, but you might want to run 'make savedefconfig' and use the output of that, to make it easier to keep it up to date. I got it, I use the output of 'make savedefconfig'. One question, is that OK to add some options on it? -Because "CONFIG_ARCH_MILBEAUT" was not listed. What I'd do here is to apply all the patches you want to get merged in the next few releases before running 'savedefconfig' and use the output of that. Let me check. Would you mean that the defconfig will include all those drivers configs, which will not appear at this moment? Correct. If you already know that you will need the options, including them now means you don't have to update the defconfig file as much in the future. I just concern that if other subsystem maintainer comments on the config name. Even in that case, can we just update the defconfig with new name? Yes, that's easy enough. OK, I got it :) Thank you! Thank you for the detail. I got it too. Arnd
Re: [PATCH v3 9/9] ARM: configs: Add Milbeaut M10V defconfig
Hi On 2019/02/20 18:28, Arnd Bergmann wrote: On Wed, Feb 20, 2019 at 8:44 AM Sugaya Taichi wrote: diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig new file mode 100644 index 000..a263211 --- /dev/null +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -0,0 +1,175 @@ I no longer see anything here that should be turned off, but you might want to run 'make savedefconfig' and use the output of that, to make it easier to keep it up to date. I got it, I use the output of 'make savedefconfig'. One question, is that OK to add some options on it? -Because "CONFIG_ARCH_MILBEAUT" was not listed. diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5bee34a..6753805 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -54,6 +54,8 @@ CONFIG_SOC_VF610=y CONFIG_ARCH_KEYSTONE=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MESON=y +CONFIG_ARCH_MILBEAUT=y +CONFIG_ARCH_MILBEAUT_M10V=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_375=y I'm surprised that you don't need to enable any drivers. Does this actually boot on your hardware? Yes, but not exactly. The series has not serial driver, so I add the driver temporarily and confirm the boot log through earlycon. The timer driver is selected by "CONFIG_ARCH_MILBEAUT_M10V", no need to add the the"CONFIG_MILBEAUT_TIMER". Here one more question. Is this OK to submit a core support patch without any serial drivers? Thanks, Sugaya Taichi Arnd ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
[PATCH v3 8/9] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
Add devicetree for Milbeaut M10V SoC and M10V Evaluation board.
Signed-off-by: Sugaya Taichi
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32 +++
arch/arm/boot/dts/milbeaut-m10v.dtsi| 95 +
3 files changed, 128 insertions(+)
create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts
create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bd40148..f697d87 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1233,6 +1233,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
+dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts
b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
new file mode 100644
index 000..614f60c
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Socionext Milbeaut M10V Evaluation Board */
+/dts-v1/;
+#include "milbeaut-m10v.dtsi"
+
+/ {
+ model = "Socionext M10V EVB";
+ compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ bootargs = "rootwait earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ uclk40xi: uclk40xi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000>;
+ };
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x8000>;
+ };
+
+};
diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi
b/arch/arm/boot/dts/milbeaut-m10v.dtsi
new file mode 100644
index 000..aa7c6ca
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "socionext,sc2000a";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "socionext,milbeaut-m10v-smp";
+ cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ };
+ cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ };
+ cpu@f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ };
+ cpu@f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ };
+ };
+
+ timer { /* The Generic Timer */
+ compatible = "arm,armv7-timer";
+ interrupts = ,
+ ,
+ ,
+ ;
+ clock-frequency = <4000>;
+ always-on;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <>;
+
+ gic: interrupt-controller@1d00 {
+ compatible = "arm,cortex-a7-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x1d001000 0x1000>,
+ <0x1d002000 0x1000>; /* CPU I/f base and size */
+ };
+
+ timer@1e50 { /* 32-bit Reload Timers */
+ compatible = "socionext,milbeaut-timer";
+ reg = <0x1e50 0x20>;
+ interrupts = <0 91 4>;
+ };
+
+ uart1: serial@1e700010 { /* PE4, PE5 */
+ /* Enable this as ttyUSI0 */
+ compatible = "socionext,milbeaut-usio-uart";
+ reg = <0x1e700010 0x10>;
+ interrupts = <0 141 0x4>, <0 149 0x4>;
+
[PATCH v3 9/9] ARM: configs: Add Milbeaut M10V defconfig
This patch adds the minimal defconfig for the Milbeaut M10V. Signed-off-by: Sugaya Taichi --- arch/arm/configs/milbeaut_m10v_defconfig | 175 +++ arch/arm/configs/multi_v7_defconfig | 2 + 2 files changed, 177 insertions(+) create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig new file mode 100644 index 000..a263211 --- /dev/null +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -0,0 +1,175 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEBUG_SEMIHOSTING=y +CONFIG_DEFAULT_HOSTNAME="mlbel" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ_FULL=y +CONFIG_NO_HZ_FULL_ALL=y +CONFIG_NO_HZ_FULL_SYSIDLE=y +CONFIG_NO_HZ_FULL_SYSIDLE_SMALL=4 +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_PROFILING=y +# CONFIG_OPROFILE=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_ARCH_MILBEAUT=y +CONFIG_ARCH_MILBEAUT_M10V=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_SMP=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_PREEMPT=y +CONFIG_THUMB2_KERNEL=y +CONFIG_HIGHMEM=y +# CONFIG_COMPACTION is not set +CONFIG_CMA=y +# CONFIG_ATAGS is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_UNIX=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=2 +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_VETH=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_LEGACY_PTY_COUNT=4 +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_S6AP412=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_PLATFORM=y +# CONFIG_VGA_ARB is not set +CONFIG_DMADEVICES=y +CONFIG_UIO=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_EXT4_FS=y +# CONFIG_EXT4_USE_FOR_EXT23 is not set +# CONFIG_XFS_FS is not set +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=932 +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_NFS_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_MAC_ROMAN=y +CONFIG_NLS_MAC_CELTIC=y +CONFIG_NLS_MAC_CENTEURO=y +CONFIG_NLS_MAC_CROATIAN=y +CONFIG_NLS_MAC_CYRILLIC=y +CONFIG_NLS_MAC_GAELIC=y +CONFIG_NLS_MAC_GREEK=y +CONFIG_NLS_MAC_ICELAND=y +CONFIG_NLS_MAC_INUIT=y +CONFIG_NLS_MAC_ROMANIAN=y +CONFIG_NLS_MAC_TURKISH=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_HEADERS_CHECK=y +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_KGDB=y +CONFIG_KEYS=y +CONFIG_ENCRYPTED_KEYS=y +CONFIG_SECURITY=y +CONFIG_FONTS=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5bee34a..6753805 100644 --- a/arch/arm/configs/multi_v7
[PATCH v3 7/9] dt-bindings: serial: Add Milbeaut serial driver description
Add DT bindings document for Milbeaut serial driver.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/serial/milbeaut-uart.txt| 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt
diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
new file mode 100644
index 000..3d2fb1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
@@ -0,0 +1,21 @@
+Socionext Milbeaut UART controller
+
+Required properties:
+- compatible: should be "socionext,milbeaut-usio-uart".
+- reg: offset and length of the register set for the device.
+- interrupts: two interrupts specifier.
+- interrupt-names: should be "rx", "tx".
+- clocks: phandle to the input clock.
+
+Optional properties:
+- auto-flow-control: flow control enable.
+
+Example:
+ usio1: usio_uart@1e700010 {
+ compatible = "socionext,milbeaut-usio-uart";
+ reg = <0x1e700010 0x10>;
+ interrupts = <0 141 0x4>, <0 149 0x4>;
+ interrupt-names = "rx", "tx";
+ clocks = < 2>;
+ auto-flow-control;
+ };
--
1.9.1
[PATCH v3 6/9] clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs
Add timer driver for Milbeaut SoCs series.
The timer has two 32-bit width down counters, one of which is configured
as a clockevent device and the other is configured as a clock source.
Signed-off-by: Sugaya Taichi
Acked-by: Daniel Lezcano
---
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-milbeaut.c | 161 +++
3 files changed, 171 insertions(+)
create mode 100644 drivers/clocksource/timer-milbeaut.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a9e26f6..9101b8f 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -634,4 +634,13 @@ config GX6605S_TIMER
help
This option enables support for gx6605s SOC's timer.
+config MILBEAUT_TIMER
+ bool "Milbeaut timer driver" if COMPILE_TEST
+ depends on OF
+ depends on ARM
+ select TIMER_OF
+ select CLKSRC_MMIO
+ help
+ Enables the support for Milbeaut timer driver.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index cdd210f..6f2543b 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
obj-$(CONFIG_OWL_TIMER)+= timer-owl.o
+obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
obj-$(CONFIG_NPCM7XX_TIMER)+= timer-npcm7xx.o
obj-$(CONFIG_RDA_TIMER)+= timer-rda.o
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
new file mode 100644
index 000..f2019a8
--- /dev/null
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "timer-of.h"
+
+#define MLB_TMR_TMCSR_OFS 0x0
+#define MLB_TMR_TMR_OFS0x4
+#define MLB_TMR_TMRLR1_OFS 0x8
+#define MLB_TMR_TMRLR2_OFS 0xc
+#define MLB_TMR_REGSZPCH 0x10
+
+#define MLB_TMR_TMCSR_OUTL BIT(5)
+#define MLB_TMR_TMCSR_RELD BIT(4)
+#define MLB_TMR_TMCSR_INTE BIT(3)
+#define MLB_TMR_TMCSR_UF BIT(2)
+#define MLB_TMR_TMCSR_CNTE BIT(1)
+#define MLB_TMR_TMCSR_TRG BIT(0)
+
+#define MLB_TMR_TMCSR_CSL_DIV2 0
+#define MLB_TMR_DIV_CNT2
+
+#define MLB_TMR_SRC_CH (1)
+#define MLB_TMR_EVT_CH (0)
+
+#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
+#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
+
+#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_SRC_TMR_OFS(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_EVT_TMR_OFS(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TIMER_RATING 500
+
+static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *clk = dev_id;
+ struct timer_of *to = to_timer_of(clk);
+ u32 val;
+
+ val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ val &= ~MLB_TMR_TMCSR_UF;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ clk->event_handler(clk);
+
+ return IRQ_HANDLED;
+}
+
+static int mlb_set_state_periodic(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ writel_relaxed(to->of_clk.period, timer_of_base(to) +
+ MLB_TMR_EVT_TMRLR1_OFS);
+ val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
+ MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_set_state_oneshot(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_clkevt_next_event(unsigned long event,
+ struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
+ writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
+ MLB_TMR_T
[PATCH v3 5/9] dt-bindings: timer: Add Milbeaut M10V timer description
Add DT bindings document for Milbeaut M10V timer.
Signed-off-by: Sugaya Taichi
Reviewed-by: Rob Herring
---
.../bindings/timer/socionext,milbeaut-timer.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
diff --git
a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
new file mode 100644
index 000..ac44c4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
@@ -0,0 +1,17 @@
+Milbeaut SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "socionext,milbeaut-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer.
+- clocks: phandle to the input clk.
+
+Example:
+
+timer {
+ compatible = "socionext,milbeaut-timer";
+ reg = <0x1e50 0x20>
+ interrupts = <0 91 4>;
+ clocks = < 4>;
+};
--
1.9.1
[PATCH v3 4/9] ARM: milbeaut: Add basic support for Milbeaut m10v SoC
This adds the basic M10V SoC support under arch/arm.
Since all cores are activated in the custom bootloader before booting
linux, it is necessary to wait for the secondary-cores using cpu-enable-
method and special sram.
Signed-off-by: Sugaya Taichi
---
arch/arm/Kconfig | 2 +
arch/arm/Makefile| 1 +
arch/arm/mach-milbeaut/Kconfig | 20 ++
arch/arm/mach-milbeaut/Makefile | 1 +
arch/arm/mach-milbeaut/platsmp.c | 143 +++
5 files changed, 167 insertions(+)
create mode 100644 arch/arm/mach-milbeaut/Kconfig
create mode 100644 arch/arm/mach-milbeaut/Makefile
create mode 100644 arch/arm/mach-milbeaut/platsmp.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 664e918..c8cb752 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -750,6 +750,8 @@ source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-meson/Kconfig"
+source "arch/arm/mach-milbeaut/Kconfig"
+
source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-moxart/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9db3c58..0e9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_MXC) += imx
machine-$(CONFIG_ARCH_MEDIATEK)+= mediatek
+machine-$(CONFIG_ARCH_MILBEAUT)+= milbeaut
machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_NETX)+= netx
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
diff --git a/arch/arm/mach-milbeaut/Kconfig b/arch/arm/mach-milbeaut/Kconfig
new file mode 100644
index 000..6a576fd
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Kconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0
+menuconfig ARCH_MILBEAUT
+ bool "Socionext Milbeaut SoCs"
+ depends on ARCH_MULTI_V7
+ select ARM_GIC
+ help
+ This enables support for Socionext Milbeaut SoCs
+
+if ARCH_MILBEAUT
+
+config ARCH_MILBEAUT_M10V
+ bool "Milbeaut SC2000/M10V platform"
+ select ARM_ARCH_TIMER
+ select MILBEAUT_TIMER
+ select PINCTRL
+ select PINCTRL_MILBEAUT
+ help
+ Support for Socionext's MILBEAUT M10V based systems
+
+endif
diff --git a/arch/arm/mach-milbeaut/Makefile b/arch/arm/mach-milbeaut/Makefile
new file mode 100644
index 000..ce5ea06
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-milbeaut/platsmp.c b/arch/arm/mach-milbeaut/platsmp.c
new file mode 100644
index 000..591543c
--- /dev/null
+++ b/arch/arm/mach-milbeaut/platsmp.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright: (C) 2018 Socionext Inc.
+ * Copyright: (C) 2015 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define M10V_MAX_CPU 4
+#define KERNEL_UNBOOT_FLAG 0x12345678
+
+static void __iomem *m10v_smp_base;
+
+static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
+{
+ unsigned int mpidr, cpu, cluster;
+
+ if (!m10v_smp_base)
+ return -ENXIO;
+
+ mpidr = cpu_logical_map(l_cpu);
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ if (cpu >= M10V_MAX_CPU)
+ return -EINVAL;
+
+ pr_info("%s: cpu %u l_cpu %u cluster %u\n",
+ __func__, cpu, l_cpu, cluster);
+
+ writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);
+ arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
+
+ return 0;
+}
+
+static void m10v_smp_init(unsigned int max_cpus)
+{
+ unsigned int mpidr, cpu, cluster;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram");
+ if (!np)
+ return;
+
+ m10v_smp_base = of_iomap(np, 0);
+ if (!m10v_smp_base)
+ return;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster);
+
+ for (cpu = 0; cpu < M10V_MAX_CPU; cpu++)
+ writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+}
+
+static void m10v_cpu_die(unsigned int l_cpu)
+{
+ gic_cpu_if_down(0);
+ v7_exit_coherency_flush(louis);
+ wfi();
+}
+
+static int m10v_cpu_kill(unsigned int l_cpu)
+{
+ unsigned int mpidr, cpu;
+
+ mpidr = cpu_logical_map(l_cpu);
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
+ writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+
+ return 1;
+}
+
+static struct smp_operations m10v_smp_ops __initdata = {
+ .smp_p
[PATCH v3 1/9] dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram
The Milbeaut M10V SoC needs a part of sram for smp, so this adds the
M10V sram compatible and binding.
Signed-off-by: Sugaya Taichi
Reviewed-by: Rob Herring
---
.../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
diff --git a/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
new file mode 100644
index 000..194f6a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
@@ -0,0 +1,24 @@
+Milbeaut SRAM for smp bringup
+
+Milbeaut SoCs use a part of the sram for the bringup of the secondary cores.
+Once they get powered up in the bootloader, they stay at the specific part
+of the sram.
+Therefore the part needs to be added as the sub-node of mmio-sram.
+
+Required sub-node properties:
+- compatible : should be "socionext,milbeaut-smp-sram"
+
+Example:
+
+sram: sram@0 {
+compatible = "mmio-sram";
+reg = <0x0 0x1>;
+#address-cells = <1>;
+#size-cells = <1>;
+ranges = <0 0x0 0x1>;
+
+smp-sram@f100 {
+compatible = "socionext,milbeaut-smp-sram";
+reg = <0xf100 0x20>;
+};
+};
--
1.9.1
[PATCH v3 2/9] dt-bindings: arm: Add SMP enable-method for Milbeaut
This adds a compatible string "socionext,milbeaut-m10v-smp" for Milbeaut M10V to the 32 bit ARM CPU device tree binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 298c17b..365dcf3 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -228,6 +228,7 @@ patternProperties: - renesas,r9a06g032-smp - rockchip,rk3036-smp - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp - ste,dbx500-smp cpu-release-addr: -- 1.9.1
[PATCH v3 3/9] dt-bindings: Add documentation for Milbeaut SoCs
This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- .../bindings/arm/socionext/milbeaut.yaml | 22 ++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml diff --git a/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml new file mode 100644 index 000..522396f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/milbeaut.yaml# +$schema: http://devicetree.org/meta-schemas/milbeaut.yaml# + +title: Milbeaut platforms device tree bindings + +maintainers: + - Taichi Sugaya + - Takao Orito + +properties: + $nodename: +const: '/' + compatible: +oneOf: + - items: + - enum: + - socionext,milbeaut-m10v-evb + - const: socionext,sc2000a +... -- 1.9.1
[PATCH v3 0/9] Add basic support for Socionext Milbeaut M10V SoC
Hi, Here is the series of patches the initial support for SC2000(M10V) of Milbeaut SoCs. "M10V" is the internal name of SC2000, so commonly used in source code. SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for computer vision. It also features advanced functionalities such as 360-degree, real-time spherical stitching with multi cameras, image stabilization for without mechanical gimbals, and rolling shutter correction. More detail is below: https://www.socionext.com/en/products/assp/milbeaut/SC2000.html Specifications for developers are below: - Quad-core 32bit Cortex-A7 on ARMv7-A architecture - NEON support - DSP - GPU - MAX 3GB DDR3 - Cortex-M0 for power control - NAND Flash Interface - SD UHS-I - SD UHS-II - SDIO - USB2.0 HOST / Device - USB3.0 HOST / Device - PCI express Gen2 - Ethernet Engine - I2C - UART - SPI - PWM Support is quite minimal for now, since it only includes timer, clock, pictrl and serial controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals will come eventually. Changes since v2: * Drop clk, pinctrl, and serial driver. * Drop unneeded options from defconfig. * Convert milbeaut soc binding to yaml. * Fix serial driver binding. * Change serial id of aliases in DT. * Add platform checking when entering suspend/resume. * Drop pr_err()s. Changes since v1: * Change file names. * Change #define names. * Refine cpu-enable-method and bindigs. * Add documentation for Milbeaut SoCs. * Add more infomation for timer driver. * Add sched_clock to timer driver. * Refine whole of clk driver. * Add earlycon instead of earlyprintk. * Refine Device Tree. Sugaya Taichi (9): dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram dt-bindings: arm: Add SMP enable-method for Milbeaut dt-bindings: Add documentation for Milbeaut SoCs ARM: milbeaut: Add basic support for Milbeaut m10v SoC dt-bindings: timer: Add Milbeaut M10V timer description clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs dt-bindings: serial: Add Milbeaut serial driver description ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board ARM: configs: Add Milbeaut M10V defconfig Documentation/devicetree/bindings/arm/cpus.yaml| 1 + .../bindings/arm/socionext/milbeaut.yaml | 22 +++ .../devicetree/bindings/serial/milbeaut-uart.txt | 21 +++ .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 +++ .../bindings/timer/socionext,milbeaut-timer.txt| 17 ++ arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/milbeaut-m10v-evb.dts| 32 arch/arm/boot/dts/milbeaut-m10v.dtsi | 95 +++ arch/arm/configs/milbeaut_m10v_defconfig | 175 + arch/arm/configs/multi_v7_defconfig| 2 + arch/arm/mach-milbeaut/Kconfig | 20 +++ arch/arm/mach-milbeaut/Makefile| 1 + arch/arm/mach-milbeaut/platsmp.c | 143 + drivers/clocksource/Kconfig| 9 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-milbeaut.c | 161 +++ 18 files changed, 728 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig create mode 100644 arch/arm/mach-milbeaut/Kconfig create mode 100644 arch/arm/mach-milbeaut/Makefile create mode 100644 arch/arm/mach-milbeaut/platsmp.c create mode 100644 drivers/clocksource/timer-milbeaut.c -- 1.9.1
Re: [PATCH v2 13/15] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
Hi,
On 2019/02/19 19:11, Arnd Bergmann wrote:
On Tue, Feb 19, 2019 at 6:11 AM Sugaya, Taichi
wrote:
Hi,
Thank you for you comments.
On 2019/02/18 21:09, Arnd Bergmann wrote:
On Fri, Feb 8, 2019 at 1:28 PM Sugaya Taichi
wrote:
+
+ aliases {
+ serial1 =
+ };
Maybe start with serial0 here? It seems unusual to start
counting at 1.
The M10V evaluation board(EVB) uses a console with uart ch1, so this
alias number is derived from the used channel one.
Therefore it is no problem to change the alias number to 0.
The alias should normally reflect whatever is printed on the board,
if there are no labels, the convention is to start with zero, regardless
of what internal uart is connected to it.
I got it.
I use a "serial0" beacause there are no labels about uart ch on M10V EVB.
Thanks,
Sugaya Taichi
Arnd
Re: [PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC
Hi,
On 2019/02/19 18:21, Arnd Bergmann wrote:
On Tue, Feb 19, 2019 at 8:12 AM Sugaya, Taichi
wrote:
On 2019/02/18 21:15, Arnd Bergmann wrote:
On Fri, Feb 8, 2019 at 1:26 PM Sugaya Taichi
wrote:
+static int __init m10v_pm_init(void)
+{
+ suspend_set_ops(_pm_ops);
+
+ return 0;
+}
+late_initcall(m10v_pm_init);
This requires a check to ensure you are actually on the right platform,
otherwise you break suspend/resume in a multiplatform kernel running
on anything other than milbeaut.
OK.
I think the solution is adding a "if statement with mlbeaut compatible"
above suspend_set_ops(_pm_ops).
Right, you can either use a call to of_machine_is_compatible(),
or you add a machine descriptor with OF_MACHINE_START()
and use this as the init_late() callback.
Yeah, I will use "of_machine_is_compatible()".
Thanks,
Sugaya Taichi
Arnd
Re: [PATCH v2 03/15] dt-bindings: Add documentation for Milbeaut SoCs
Hi, On 2019/02/19 10:25, Masahiro Yamada wrote: On Fri, Feb 8, 2019 at 9:26 PM Sugaya Taichi wrote: This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- Documentation/devicetree/bindings/arm/milbeaut.txt | 6 ++ 1 file changed, 6 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/milbeaut.txt diff --git a/Documentation/devicetree/bindings/arm/milbeaut.txt b/Documentation/devicetree/bindings/arm/milbeaut.txt I added uniphier SoC/board binding into Documentation/devicetree/bindings/arm/socionext/uniphier.txt You can milbeaut.txt to the socionext directory as well. Thank you for informing. I found the directory there. I will add the "milbeaut.txt(yaml)" there. Thanks, Sugaya Taichi new file mode 100644 index 000..9fd053a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/milbeaut.txt @@ -0,0 +1,6 @@ +Milbeaut platforms device tree bindings +--- + +- Milbeaut M10V Evaluation Board +Required root node properties: + - compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; -- 1.9.1
Re: [PATCH v2 09/15] dt-bindings: serial: Add Milbeaut serial driver description
Hi,
On 2019/02/19 4:57, Rob Herring wrote:
On Fri, Feb 08, 2019 at 09:27:29PM +0900, Sugaya Taichi wrote:
Add DT bindings document for Milbeaut serial driver.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/serial/milbeaut-uart.txt| 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt
diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
new file mode 100644
index 000..8f61c38
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
@@ -0,0 +1,21 @@
+Socionext Milbeaut UART controller
+
+Required properties:
+- compatible: should be "socionext,milbeaut-usio-uart".
+- reg: offset and length of the register set for the device.
+- interrupts: two interrupts specifier.
+- clocks: phandle to the input clock.
+- interrupt-names: should be "rx", "tx".
Put this next to 'interrupts'
OK, change the order.
+
+Optional properties:
+- uart-flow-enable: flow control enable.
We already have a standard property for this: auto-flow-control
Okay, I change the property name to "auto-flow-control"
+
+Example:
+ usio1: usio_uart@1e700010 {
serial@...
I got it.
Thanks,
Sugaya Taichi
+ compatible = "socionext,milbeaut-usio-uart";
+ reg = <0x1e700010 0x10>;
+ interrupts = <0 141 0x4>, <0 149 0x4>;
+ interrupt-names = "rx", "tx";
+ clocks = < 2>;
+ uart-flow-enable;
+ };
--
1.9.1
Re: [PATCH v2 05/15] dt-bindings: timer: Add Milbeaut M10V timer description
Hi, On 2019/02/19 4:53, Rob Herring wrote: On Fri, 8 Feb 2019 21:26:30 +0900, Sugaya Taichi wrote: Add DT bindings document for Milbeaut M10V timer. Signed-off-by: Sugaya Taichi --- .../bindings/timer/socionext,milbeaut-timer.txt | 17 + 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt Reviewed-by: Rob Herring Thank you!
Re: [PATCH v2 03/15] dt-bindings: Add documentation for Milbeaut SoCs
Hi, On 2019/02/19 4:52, Rob Herring wrote: On Fri, Feb 08, 2019 at 09:26:04PM +0900, Sugaya Taichi wrote: This adds a DT binding documentation for the M10V and its evaluation board. Most boards/soc bindings are using DT schema (yaml) now. We're not requiring that just yet, but I'd like to not add more. So can you convert this to schema. Probably yes. I try to convert with looking at references. Thanks, Sugaya Taichi Rob Signed-off-by: Sugaya Taichi --- Documentation/devicetree/bindings/arm/milbeaut.txt | 6 ++ 1 file changed, 6 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/milbeaut.txt diff --git a/Documentation/devicetree/bindings/arm/milbeaut.txt b/Documentation/devicetree/bindings/arm/milbeaut.txt new file mode 100644 index 000..9fd053a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/milbeaut.txt @@ -0,0 +1,6 @@ +Milbeaut platforms device tree bindings +--- + +- Milbeaut M10V Evaluation Board +Required root node properties: + - compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; -- 1.9.1
Re: [PATCH v2 01/15] dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram
Hi, On 2019/02/19 4:49, Rob Herring wrote: On Fri, 8 Feb 2019 21:25:33 +0900, Sugaya Taichi wrote: The Milbeaut M10V SoC needs a part of sram for smp, so this adds the M10V sram compatible and binding. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt Reviewed-by: Rob Herring Thank you!
Re: [PATCH v2 00/15] Add basic support for Socionext Milbeaut M10V SoC
Hi, Thank you for your comments. On 2019/02/18 21:20, Arnd Bergmann wrote: On Fri, Feb 8, 2019 at 1:24 PM Sugaya Taichi wrote: Hi, Here is the series of patches the initial support for SC2000(M10V) of Milbeaut SoCs. "M10V" is the internal name of SC2000, so commonly used in source code. SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for computer vision. It also features advanced functionalities such as 360-degree, real-time spherical stitching with multi cameras, image stabilization for without mechanical gimbals, and rolling shutter correction. More detail is below: https://www.socionext.com/en/products/assp/milbeaut/SC2000.html Specifications for developers are below: - Quad-core 32bit Cortex-A7 on ARMv7-A architecture - NEON support - DSP - GPU - MAX 3GB DDR3 - Cortex-M0 for power control - NAND Flash Interface - SD UHS-I - SD UHS-II - SDIO - USB2.0 HOST / Device - USB3.0 HOST / Device - PCI express Gen2 - Ethernet Engine - I2C - UART - SPI - PWM Support is quite minimal for now, since it only includes timer, clock, pictrl and serial controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals will come eventually. I've looked over the platform once more. Overall, it looks very good, and I'd still like to merge this for linux-5.1, but we are running out of time there. If you send the patches to s...@kernel.org quickly, we can try to still merge them in, but if anything goes wrong, it will have to wait until we start merging patches for 5.2, directly after 5.1 is out. I see. I do my best to make it. I did not look at the device driver patches (clk, clocksource, pinctrl, serial) in much detail. If you have an Ack from the maintainers, feel free to include them in the series, otherwise let's merge the rest now and then you can send the updated patches for inclusion through the subsystem trees in 5.2. OK, I'll add the patches with "Acked" or "Reviewed" tag. I have sent a few comments. The only one that is really important here is the missing platform check in the suspend options. Please try to address most of the other commentsm, either by changing the code, or by explaining why your version is correct. Okay, try to address them. I send the next version as soon as possible. Thanks. Sugaya Taichi Arnd
Re: [PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC
Hi,
Thank you for your comments.
On 2019/02/18 21:15, Arnd Bergmann wrote:
On Fri, Feb 8, 2019 at 1:26 PM Sugaya Taichi
wrote:
+static int m10v_pm_enter(suspend_state_t state)
+{
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ pr_err("STANDBY\n");
+ asm("wfi");
+ break;
+ case PM_SUSPEND_MEM:
+ pr_err("SUSPEND\n");
+ cpu_pm_enter();
+ cpu_suspend(0, m10v_die);
+ cpu_pm_exit();
+ break;
+ }
+ return 0;
+}
It looks like you left the pr_err() messages from bringup, they should probably
be removed now.
OK. remove the pr_err()s.
+static int __init m10v_pm_init(void)
+{
+ suspend_set_ops(_pm_ops);
+
+ return 0;
+}
+late_initcall(m10v_pm_init);
This requires a check to ensure you are actually on the right platform,
otherwise you break suspend/resume in a multiplatform kernel running
on anything other than milbeaut.
OK.
I think the solution is adding a "if statement with mlbeaut compatible"
above suspend_set_ops(_pm_ops).
Thanks,
Sugaya Taichi
Arnd
Re: [PATCH v2 13/15] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
Hi,
Thank you for you comments.
On 2019/02/18 21:09, Arnd Bergmann wrote:
On Fri, Feb 8, 2019 at 1:28 PM Sugaya Taichi
wrote:
+
+ aliases {
+ serial1 =
+ };
Maybe start with serial0 here? It seems unusual to start
counting at 1.
The M10V evaluation board(EVB) uses a console with uart ch1, so this
alias number is derived from the used channel one.
Therefore it is no problem to change the alias number to 0.
+ chosen {
+ bootargs = "init=/sbin/finit rootwait earlycon";
The /sbin/finit argument seems user space specific, so you probably don't
want this in the dts file but rather pass it from the boot loader.
Possible drop the bootargs entirely.
Okay, remove the arg from the dts and add to bootargs instead.
Thanks,
Sugaya Taichi
Arnd
Re: [PATCH v2 14/15] ARM: configs: Add Milbeaut M10V defconfig
Hi, Thank you for comments. On 2019/02/18 21:06, Arnd Bergmann wrote: On Fri, Feb 8, 2019 at 1:30 PM Sugaya Taichi wrote: This patch adds the minimal defconfig for the Milbeaut M10V. Signed-off-by: Sugaya Taichi --- arch/arm/configs/milbeaut_m10v_defconfig | 366 +++ 1 file changed, 366 insertions(+) I think it would be good to reduce this a little bit. Please also add any options you need for booting to multi_v7_defconfig. Device drivers you don't need for booting but for additional features should be loadable modules there. Yeah, I should have refined more. OK, add aome options to multi_v7_defconfig also. +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y CONFIG_EMBEDDED should not normally be set on device configurations. Despite the name it's not something for general embedded computing, but it's rather an option that lets you turn other option that one should normally not have to change. OK, drop it. +CONFIG_PROFILING=y +CONFIG_OPROFILE=m Oprofile is rarely used these days, maybe change the default to PERF_EVENTS=y? I see. I try to use PERF_EVENTS instead. +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_THUMB2_KERNEL=y I think this will be the first armv8-a platform with thumb2 by default, and it's probably a good thing to start testing that more. I still leave it in the next patch. +CONFIG_HIGHMEM=y It's unusual to have both VMSPLIT_2G and HIGHMEM. OK. try to drop either. +CONFIG_ARM_APPENDED_DTB=y If you are able to fix the boot loaders, this should be turned off The boot loader is fixed, so I think it can be turned off. +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_DEVELOPER_WARNINGS=y +CONFIG_CFG80211_REG_DEBUG=y That seems like more debugging that you should need. Yes, drop entirely. +# CONFIG_I2C is not set +# CONFIG_I2C_BOARDINFO is not set +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_SNI_M10V is not set If I2C is disabled, you shoulnd't need any of the later options here. I2C is disable now... drop entirely. +CONFIG_FB=y +# CONFIG_VGA_ARB is not set Since you don't have a framebuffer driver, and likely won't add one (new drivers should use drivers/gpu/drm), I'd drop this. framebuffer is disable too... drop it. +# CONFIG_USB is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set ... +# CONFIG_MMC is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_F_EMMC50 is not set Also for USB and MMC: if you don't have the subsystem, you should not need to list the other options. USB, MMC, and more peripherals are disable now. I will drop them in the next patch. +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +# CONFIG_RTC_SYSTOHC is not set +CONFIG_RTC_DEBUG=y +CONFIG_RTC_DRV_RX8025=y +CONFIG_DMADEVICES=y +CONFIG_MB86S7X_HDMAC=y +CONFIG_MB8AC0300_XDMAC=y +CONFIG_UIO=y +CONFIG_UIO_SNI=y +# CONFIG_IOMMU_SUPPORT is not set +#CONFIG_PWM=y is not set +# CONFIG_PWM_SYSFS is not set +#CONFIG_PWM_M10V=y is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_EXFAT=y CONFIG_EXFAT does not exist in mainline kernels. Yes. drop it. +CONFIG_IPCU_FS=y +# CONFIG_TEST_IPCU_FS is not set same for IPCU_FS, and probably a lot of other options. Yes. I will check again for unnecessary options. Thanks, Sugaya Taichi Arnd ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH v2 06/15] clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs
Hi, Daniel
On 2019/02/15 0:22, Daniel Lezcano wrote:
On 08/02/2019 13:26, Sugaya Taichi wrote:
Add timer driver for Milbeaut SoCs series.
The timer has two 32-bit width down counters, one of which is configured
as a clockevent device and the other is configured as a clock source.
Signed-off-by: Sugaya Taichi
Acked-by: Daniel Lezcano
Thank you!
---
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-milbeaut.c | 161 +++
3 files changed, 171 insertions(+)
create mode 100644 drivers/clocksource/timer-milbeaut.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a9e26f6..9101b8f 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -634,4 +634,13 @@ config GX6605S_TIMER
help
This option enables support for gx6605s SOC's timer.
+config MILBEAUT_TIMER
+ bool "Milbeaut timer driver" if COMPILE_TEST
+ depends on OF
+ depends on ARM
+ select TIMER_OF
+ select CLKSRC_MMIO
+ help
+ Enables the support for Milbeaut timer driver.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index cdd210f..6f2543b 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
obj-$(CONFIG_OWL_TIMER) += timer-owl.o
+obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
obj-$(CONFIG_RDA_TIMER) += timer-rda.o
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
new file mode 100644
index 000..f2019a8
--- /dev/null
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "timer-of.h"
+
+#define MLB_TMR_TMCSR_OFS 0x0
+#define MLB_TMR_TMR_OFS0x4
+#define MLB_TMR_TMRLR1_OFS 0x8
+#define MLB_TMR_TMRLR2_OFS 0xc
+#define MLB_TMR_REGSZPCH 0x10
+
+#define MLB_TMR_TMCSR_OUTL BIT(5)
+#define MLB_TMR_TMCSR_RELD BIT(4)
+#define MLB_TMR_TMCSR_INTE BIT(3)
+#define MLB_TMR_TMCSR_UF BIT(2)
+#define MLB_TMR_TMCSR_CNTE BIT(1)
+#define MLB_TMR_TMCSR_TRG BIT(0)
+
+#define MLB_TMR_TMCSR_CSL_DIV2 0
+#define MLB_TMR_DIV_CNT2
+
+#define MLB_TMR_SRC_CH (1)
+#define MLB_TMR_EVT_CH (0)
+
+#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
+#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
+
+#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_SRC_TMR_OFS(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_EVT_TMR_OFS(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TIMER_RATING 500
+
+static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *clk = dev_id;
+ struct timer_of *to = to_timer_of(clk);
+ u32 val;
+
+ val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ val &= ~MLB_TMR_TMCSR_UF;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ clk->event_handler(clk);
+
+ return IRQ_HANDLED;
+}
+
+static int mlb_set_state_periodic(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ writel_relaxed(to->of_clk.period, timer_of_base(to) +
+ MLB_TMR_EVT_TMRLR1_OFS);
+ val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
+ MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_set_state_oneshot(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_clkevt_next_event(unsigned long event,
+ struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ writel_relaxed(event, timer_of_bas
Re: [PATCH v2 06/15] clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs
Hi, On 2019/02/15 0:18, Arnd Bergmann wrote: On Thu, Feb 14, 2019 at 3:44 PM Daniel Lezcano wrote: On 13/02/2019 11:34, Sugaya, Taichi wrote: Hi, On 2019/02/12 18:06, Daniel Lezcano wrote: On 08/02/2019 13:26, Sugaya Taichi wrote: Add timer driver for Milbeaut SoCs series. The timer has two 32-bit width down counters, one of which is configured as a clockevent device and the other is configured as a clock source. Signed-off-by: Sugaya Taichi Do want me to take it through my tree? Yes, please. By the way, the patch series includes other sub-system drivers, so should it be splitted into each driver patch ? Well usually changes are per sub-systems but in case of first submission you may ask linux-soc@ team to take all the patches together with the acked-by tags from those subsystems maintainer. Added in Cc: Arnd@ and linux-soc@ I'll wait a bit before applying the patch you clarify this. Yes, I think merging them all together is best here. I saw the patches fly past but did not do a complete review, but if all other review comments are addressed, I'd suggest sending the entire series for inclusion to linux-...@vger.kernel.org with the Acked-by/Reviewed-by tags from subsystem maintainers added in. Arnd Thank you for suggestion. OK. I will send the series to the ML with the Acked-by/Reviewed-by tags. Thanks, Sugaya Taichi
Re: [PATCH v2 07/15] ndings: clock: milbeaut: add Milbeaut clock description
Hi,
On 2019/02/14 3:07, Stephen Boyd wrote:
Quoting Stephen Boyd (2019-02-13 09:55:34)
The subject seems to have been cut off? "ndings"?
Quoting Sugaya Taichi (2019-02-08 04:27:03)
diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.txt
b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt
new file mode 100644
index 000..bcfc5df
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt
@@ -0,0 +1,49 @@
+Milbeaut SoCs Clock Controller Binding
+
+Milbeaut SoCs Clock controller is an integrated clock controller, which
+generates and supplies to all modules.
+
+This binding uses common clock bindings
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,milbeaut-m10v-ccu" - for M10V SoC
+- reg: shall contain base address and length of clock registers
+- #clock-cells: shall be 1
+- clocks: shall be an external clock
+
+Example: Clock controller node:
+
+ clk: m10v-clk-ctrl@1d021000 {
+ compatible = "socionext,milbeaut-m10v-clk-ccu";
I thought there was some length limit on compatible string names. 32
bytes? Just barely under!
Ah I'm wrong. Compatible is 128. Good.
Seems I was thinking of DT property names.
Sorry confusing you.
I accidently deleted "dt-bi" from subject when committing.
I repair the string in the next version.
Thanks,
Sugaya Taichi
Re: [PATCH v2 06/15] clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs
Hi,
On 2019/02/12 18:06, Daniel Lezcano wrote:
On 08/02/2019 13:26, Sugaya Taichi wrote:
Add timer driver for Milbeaut SoCs series.
The timer has two 32-bit width down counters, one of which is configured
as a clockevent device and the other is configured as a clock source.
Signed-off-by: Sugaya Taichi
Do want me to take it through my tree?
Yes, please.
By the way, the patch series includes other sub-system drivers, so
should it be splitted into each driver patch ?
Thanks,
Sugaya Taichi
---
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-milbeaut.c | 161 +++
3 files changed, 171 insertions(+)
create mode 100644 drivers/clocksource/timer-milbeaut.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a9e26f6..9101b8f 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -634,4 +634,13 @@ config GX6605S_TIMER
help
This option enables support for gx6605s SOC's timer.
+config MILBEAUT_TIMER
+ bool "Milbeaut timer driver" if COMPILE_TEST
+ depends on OF
+ depends on ARM
+ select TIMER_OF
+ select CLKSRC_MMIO
+ help
+ Enables the support for Milbeaut timer driver.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index cdd210f..6f2543b 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
obj-$(CONFIG_OWL_TIMER) += timer-owl.o
+obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
obj-$(CONFIG_RDA_TIMER) += timer-rda.o
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
new file mode 100644
index 000..f2019a8
--- /dev/null
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "timer-of.h"
+
+#define MLB_TMR_TMCSR_OFS 0x0
+#define MLB_TMR_TMR_OFS0x4
+#define MLB_TMR_TMRLR1_OFS 0x8
+#define MLB_TMR_TMRLR2_OFS 0xc
+#define MLB_TMR_REGSZPCH 0x10
+
+#define MLB_TMR_TMCSR_OUTL BIT(5)
+#define MLB_TMR_TMCSR_RELD BIT(4)
+#define MLB_TMR_TMCSR_INTE BIT(3)
+#define MLB_TMR_TMCSR_UF BIT(2)
+#define MLB_TMR_TMCSR_CNTE BIT(1)
+#define MLB_TMR_TMCSR_TRG BIT(0)
+
+#define MLB_TMR_TMCSR_CSL_DIV2 0
+#define MLB_TMR_DIV_CNT2
+
+#define MLB_TMR_SRC_CH (1)
+#define MLB_TMR_EVT_CH (0)
+
+#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
+#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
+
+#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_SRC_TMR_OFS(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_EVT_TMR_OFS(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TIMER_RATING 500
+
+static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *clk = dev_id;
+ struct timer_of *to = to_timer_of(clk);
+ u32 val;
+
+ val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ val &= ~MLB_TMR_TMCSR_UF;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ clk->event_handler(clk);
+
+ return IRQ_HANDLED;
+}
+
+static int mlb_set_state_periodic(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ writel_relaxed(to->of_clk.period, timer_of_base(to) +
+ MLB_TMR_EVT_TMRLR1_OFS);
+ val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
+ MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_set_state_oneshot(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_clkevt_next_event(unsigned long event,
+
Re: [PATCH v2 11/15] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description
Hi, Thank you for your comments. On 2019/02/08 22:32, Linus Walleij wrote: Hi Sugaya, thanks for your patch! On Fri, Feb 8, 2019 at 1:32 PM Sugaya Taichi wrote: Add DT bindings document for Milbeaut M10V pinctrl. Signed-off-by: Sugaya Taichi (...) +- interrupts: three interrupts specifer. +- interrupt-names: corresponds "interrupts" factor. (...) + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>, + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>, + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>, + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>; + interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51", + "pin-52", "pin-53", "pin-54", "pin-55", + "pin-56", "pin-57", "pin-58", "pin-59", + "pin-60", "pin-61", "pin-62", "pin-63"; As mentioned in the review of the driver, don't do this. This is a hierarchical interrupt controller, so these GIC-offset-to-GPIO-interrupt-offests should be hardcoded in the driver. If these interrupt offsets differ between difference instances of this pin controller, they should have different compatible strings. Yours, Linus Walleij I understand. I am sure the content of bindings will change as a whole as driver changes. Try it. Thanks, Sugaya Taichi
Re: [PATCH v2 12/15] pinctrl: milbeaut: Add Milbeaut M10V pinctrl
Hi,
Thank you for your comments.
On 2019/02/08 22:26, Linus Walleij wrote:
Hi Sugaya,
thank you for the patch!
Since Masahiro has previously added the Uniphier pin control driver
I would like him to provide a review of this patch, if possible. I also
want to make sure that the hardware is different enough from the
existing Uniphier pin control so that it really needs a new
driver, else I suppose it should be refactored to be part of
the pinctrl/uniphier drivers (we can of course rename it
pinctrl/socionext if only naming is an issue).
As Masahiro mentioned Millbeaut is totally different from UniPhier. So I
would like to put files individually.
On Fri, Feb 8, 2019 at 1:27 PM Sugaya Taichi
wrote:
Add Milbeaut M10V pinctrl.
The M10V has the pins that can be used GPIOs or take multiple other
functions.
Signed-off-by: Sugaya Taichi
This file seems to be mostly authored by Jassi Brar
That's right.
as he is
listed as author in the top of the source code.
Please at least add Signed-off-by: Jassi Brar
above your signed-off-by to reflect the delivery path.
Also usually author is set to indicate the person who wrote
the majority of the code so consider:
git commit --amend --author="Jassi Brar "
if Jassi wrote the majority of the code.
Since I will ask you to change a bunch of stuff in the driver
I don't know who the majority author will be in the end.
When you send out the patches this will reflect in a
From: ... line at the top of the patch.
I'm not overly sensitive about credits but this seems like
a simple thing to fix.
I will decide the author in discussion with him. If Jassi will be,
I remember to add a "From:..." line.
+config PINCTRL_MILBEAUT
+ bool
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ select OF_GPIO
+ select REGMAP_MMIO
+ select GPIOLIB_IRQCHIP
Nice reuse of the frameworks! But this driver doesn't
really use GPIOLIB_IRQCHIP, at least not as it looks now.
I got it, drop this line.
+#include
Please use only on new code.
It should be just as fine.
OK, use it instead.
+#include
This include should not be needed.
I got it, drop this line.
+struct pin_irq_map {
+ int pin; /* offset of pin in the managed range */
+ int irq; /* virq of the pin as fpint */
+ int type;
+ char irqname[8];
+};
If pins are mapped 1-to-1 to IRQs from another irqchip,
we are dealing with a hierarchical interrupt controller.
But I guess I learn more as I read the code.
Yes, some pins of GPIO are available to be used as external interrupt.
+static void _set_mux(struct m10v_pinctrl *pctl, unsigned int pin, bool gpio)
I don't like __underscore_prefix on functions since they
are semantically ambiguous. Try to find the perfect name that
reflects what the function is really doing. m10v_pmx_commit_mux_setting()
if nothing else.
OK, consider perfect name.
I do not understand the "gpio" argument for this function so please
explain it:
+ if (gpio)
+ val &= ~BIT(offset);
+ else
+ val |= BIT(offset);
So this bit is set if "gpio" is true, and that comes from here:
+static int m10v_pmx_set_mux(struct pinctrl_dev *pctldev,
+unsigned int function,
+unsigned int group)
+{
+ struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ u32 pin = pctl->gpins[group][0]; /* each group has exactly 1 pin */
+
+ _set_mux(pctl, pin, !function);
So if no special function is passed to the .set_mux() callback,
we assume that the pin is used for GPIO. Write this in a comment
if I understand it correctly, so it gets easy to read the code.
That's right!!
OK, add a comment about "gpio".
+static int _set_direction(struct m10v_pinctrl *pctl,
+ unsigned int pin, bool input)
Same issue with __underscore.
m10v_set_direction_commit()?
I got it too.
Try to consider nice name.
+static int
+m10v_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin, bool input)
+{
+ struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return _set_direction(pctl, pin, input);
+}
+
+static int
+m10v_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ _set_mux(pctl, pin, true);
+ return 0;
+}
This is a good solution.
Thank you.
+static const struct pinmux_ops m10v_pmx_ops = {
+ .get_functions_count= m10v_pmx_get_funcs_cnt,
+ .get_function_name = m10v_pmx_get_func_name,
+ .get_function_groups= m10v_pmx_get_func_groups,
+ .set_mux= m10v_pmx_set_mux,
+
[PATCH v2 11/15] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description
Add DT bindings document for Milbeaut M10V pinctrl.
Signed-off-by: Sugaya Taichi
---
.../pinctrl/socionext,milbeaut-pinctrl.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
diff --git
a/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
new file mode 100644
index 000..6b54191
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
@@ -0,0 +1,35 @@
+Milbeaut SoCs pin controller
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,milbeaut-m10v-pinctrl" - for m10v SoC
+- reg: offset and length of the register set.
+- reg-names: should be "pinctrl", "exiu".
+- gpio-controller: marks the device node as a gpio controller.
+- gpio-cells: should be 2.
+- interrupt-controller: marks the device node as a interrupt controller.
+- interrupt-cells: should be 2.
+- clocks: phandle to the input clock.
+- interrupts: three interrupts specifer.
+- interrupt-names: corresponds "interrupts" factor.
+
+Example:
+ pinctrl: pinctrl@1d022000 {
+ compatible = "socionext,milbeaut-m10v-pinctrl";
+ reg = <0x1d022000 0x1000>,
+ <0x1c26f000 0x1000>;
+ reg-names = "pinctrl", "exiu";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = < 2>;
+ interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>,
+ <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>,
+ <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>,
+ <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>;
+ interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51",
+ "pin-52", "pin-53", "pin-54", "pin-55",
+ "pin-56", "pin-57", "pin-58", "pin-59",
+ "pin-60", "pin-61", "pin-62", "pin-63";
+ }
--
1.9.1
[PATCH v2 15/15] MAINTAINERS: Add entry to MAINTAINERS for Milbeaut
Add entry to MAINTAINERS for Milbeaut that supported minimal drivers. Signed-off-by: Sugaya Taichi --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8c68de3c..50e0479 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1806,6 +1806,15 @@ F: drivers/watchdog/sama5d4_wdt.c X: drivers/input/touchscreen/atmel_mxt_ts.c X: drivers/net/wireless/atmel/ +ARM/MILBEAUT ARCHITECTURE +M: Taichi Sugaya +M: Takao Orito +L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm/boot/dts/milbeaut* +F: arch/arm/mach-milbeaut/ +N: milbeaut + ARM/MIOA701 MACHINE SUPPORT M: Robert Jarzmik L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) -- 1.9.1
[PATCH v2 14/15] ARM: configs: Add Milbeaut M10V defconfig
This patch adds the minimal defconfig for the Milbeaut M10V. Signed-off-by: Sugaya Taichi --- arch/arm/configs/milbeaut_m10v_defconfig | 366 +++ 1 file changed, 366 insertions(+) create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig new file mode 100644 index 000..c67c87f --- /dev/null +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -0,0 +1,366 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEBUG_SEMIHOSTING=y +CONFIG_DEFAULT_HOSTNAME="mlbel" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ_FULL=y +CONFIG_NO_HZ_FULL_ALL=y +CONFIG_NO_HZ_FULL_SYSIDLE=y +CONFIG_NO_HZ_FULL_SYSIDLE_SMALL=4 +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_ARCH_MILBEAUT=y +CONFIG_ARCH_MILBEAUT_M10V=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_PCI is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_SN_DW_PLAT is not set +# CONFIG_PCI_MSI is not set +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCIEAER is not set +# CONFIG_PCIEASPM is not set +CONFIG_SMP=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_THUMB2_KERNEL=y +CONFIG_HIGHMEM=y +# CONFIG_COMPACTION is not set +CONFIG_CMA=y +# CONFIG_ATAGS is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_UDP_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_IP_SCTP=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_TIPC=y +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_IPX=m +CONFIG_NETLINK_MMAP=y +CONFIG_NETLINK_DIAG=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_DEVELOPER_WARNINGS=y +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +# CONFIG_MAC80211_RC_MINSTREL is not set +CONFIG_MAC80211_LEDS=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_REGULATOR=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_CDN_HPNFC=y +CONFIG_MTD_NAND_CDN_HPNFC_DT=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=3 +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=2 +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=y +CONFIG_TUN=y +CONFIG_VETH=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_R8169=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_SOCIONEXT_OGMA=y +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_REALTEK_PHY=y +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_LEGACY_PTY_COUNT=4 +# CONFIG_DEVKMEM is not set +#CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +#CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +#CONFIG_SERIAL_8250_EXTENDED=y +#CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_MILBEAUT_USIO=y +CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_I2C is not set +# CONFIG_I2C_BOARDINFO
[PATCH v2 13/15] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
Add devicetree for Milbeaut M10V SoC and M10V Evaluation board.
Signed-off-by: Sugaya Taichi
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32
arch/arm/boot/dts/milbeaut-m10v.dtsi| 131
3 files changed, 164 insertions(+)
create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts
create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bd40148..f697d87 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1233,6 +1233,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
+dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts
b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
new file mode 100644
index 000..59e8d73
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Socionext Milbeaut M10V Evaluation Board */
+/dts-v1/;
+#include "milbeaut-m10v.dtsi"
+
+/ {
+ model = "Socionext M10V EVB";
+ compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a";
+
+ aliases {
+ serial1 =
+ };
+
+ chosen {
+ bootargs = "init=/sbin/finit rootwait earlycon";
+ stdout-path = "serial1:115200n8";
+ };
+
+ clocks {
+ uclk40xi: uclk40xi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000>;
+ };
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x8000>;
+ };
+
+};
diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi
b/arch/arm/boot/dts/milbeaut-m10v.dtsi
new file mode 100644
index 000..4fc2f8b
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "socionext,sc2000a";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "socionext,milbeaut-m10v-smp";
+ cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ };
+ cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ };
+ cpu@f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ };
+ cpu@f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ };
+ };
+
+ timer { /* The Generic Timer */
+ compatible = "arm,armv7-timer";
+ interrupts = ,
+ ,
+ ,
+ ;
+ clock-frequency = <4000>;
+ always-on;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <>;
+
+ gic: interrupt-controller@1d00 {
+ compatible = "arm,cortex-a7-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x1d001000 0x1000>,
+ <0x1d002000 0x1000>; /* CPU I/f base and size */
+ };
+
+ clk: m10v-clock-ctrl@1d021000 {
+ compatible = "socionext,milbeaut-m10v-ccu";
+ #clock-cells = <1>;
+ reg = <0x1d021000 0x1000>;
+ clocks = <>;
+ };
+
+ timer@1e50 { /* 32-bit Reload Timers */
+ compatible = "socionext,milbeaut-timer";
+ reg = <0x1e50 0x20>;
+ interrupts = <0 91 4>;
+ clock
[PATCH v2 12/15] pinctrl: milbeaut: Add Milbeaut M10V pinctrl
Add Milbeaut M10V pinctrl.
The M10V has the pins that can be used GPIOs or take multiple other
functions.
Signed-off-by: Sugaya Taichi
---
drivers/pinctrl/Kconfig| 9 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-milbeaut.c | 759 +
3 files changed, 769 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-milbeaut.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 2764d71..d968910 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -177,6 +177,15 @@ config PINCTRL_OXNAS
select GPIOLIB_IRQCHIP
select MFD_SYSCON
+config PINCTRL_MILBEAUT
+ bool
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ select OF_GPIO
+ select REGMAP_MMIO
+ select GPIOLIB_IRQCHIP
+
config PINCTRL_ROCKCHIP
bool
select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 712184b..ade9aea 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-$(CONFIG_PINCTRL_MILBEAUT) += pinctrl-milbeaut.o
obj-$(CONFIG_PINCTRL_OXNAS)+= pinctrl-oxnas.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl-pic32.o
diff --git a/drivers/pinctrl/pinctrl-milbeaut.c
b/drivers/pinctrl/pinctrl-milbeaut.c
new file mode 100644
index 000..c9a7da4
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-milbeaut.c
@@ -0,0 +1,759 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Jassi Brar
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-utils.h"
+
+#define EIMASK 0x0
+#define EISRCSEL 0x4
+#define EIREQSTA 0x8
+#define EIRAWREQSTA0xc
+#define EIREQCLR 0x10
+#define EILVL 0x14
+#define EIEDG 0x18
+#define EISIR 0x1c
+
+#define PDR0x0
+#define PDR_S 0x50
+#define PDR_C 0xa0
+#define DDR0x100
+#define EPCR 0x200
+#define PUDER 0x300
+#define PUDCR 0x400
+
+#define M10V_BANKS 26
+#define PINS_PER_BANK 8
+#define M10V_TOTAL_PINS(M10V_BANKS * PINS_PER_BANK)
+#define PINS_PER_REG 16
+
+struct pin_irq_map {
+ int pin; /* offset of pin in the managed range */
+ int irq; /* virq of the pin as fpint */
+ int type;
+ char irqname[8];
+};
+
+struct m10v_pinctrl {
+ void __iomem *base;
+ void __iomem *exiu;
+ struct gpio_chip gc;
+ struct pinctrl_desc pd;
+ char pin_names[4 * M10V_TOTAL_PINS];
+ struct pinctrl_pin_desc pins[M10V_TOTAL_PINS];
+ unsigned int gpins[M10V_TOTAL_PINS][1]; /* 1 pin-per-group */
+ struct irq_domain *irqdom;
+ spinlock_t irq_lock, lock;
+ int extints;
+ struct pin_irq_map fpint[]; /* keep at end */
+};
+
+struct milbeaut_function {
+ const char *name;
+ const char * const *groups;
+ unsigned intngroups;
+};
+
+static const char m10v_bank_name[] = {'0', '1', '2', '3', '4', '5', '6', '7',
+'8', '9', 'A', 'B', 'C', 'D', 'E', 'F',
+'G', 'H', 'W', 'J', 'K', 'L', 'M', 'N',
+'Y', 'P'};
+static const char * const usio0_m10v_grps[] = {"PE2", "PE3", "PF0"};
+static const char * const usio1_m10v_grps[] = {"PE4", "PE5", "PF1"};
+static const char * const usio2_m10v_grps[] = {"PE0", "PE1"};
+static const char * const usio3_m10v_grps[] = {"PY0", "PY1", "PY2"};
+static const char * const usio4_m10v_grps[] = {"PP0", "PP1", "PP2"};
+static const char * const usio5_m10v_grps[] = {"PM0", "PM1", "PM3"};
+static const char * const usio6_m10v_grps[] = {"PN0", "PN1", "PN3"};
+static const char * const usio7_m10v_grps[] = {"PY3", "PY5", "PY6"};
+static const char *gpio_m10v_grps[M10V_TOTAL_PINS];
+
+static const struct milbeaut_function m10v_functions[] = {
+#define FUNC_M10V(fname) \
+ { \
+ .name = #fname, \
+ .groups = fname##_m10v_grps,\
+ .ngroups = ARRAY_SIZE(fname##_m10v_grps), \
+ }
+ FUNC_M10V(gpio), /* GPIO always at index 0 */
+ FUNC_M10V(usio0),
+ FUNC_M10V
[PATCH v2 08/15] clock: milbeaut: Add Milbeaut M10V clock controller
The M10V of the Milbeaut SoCs has an on-chip controller that derive
mostly clocks from a single external clock, using PLLs, dividers,
multiplexers and gates. Since the PLLs have already been started and
will not stop / restart, they are fixed factor. Gates will be added in
later patch (all gates are off state).
Signed-off-by: Sugaya Taichi
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-milbeaut.c | 626 +
2 files changed, 627 insertions(+)
create mode 100644 drivers/clk/clk-milbeaut.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8a9440a..84a78e8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_COMMON_CLK_ASPEED)+= clk-aspeed.o
obj-$(CONFIG_ARCH_HIGHBANK)+= clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
+obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c
new file mode 100644
index 000..f798939
--- /dev/null
+++ b/drivers/clk/clk-milbeaut.c
@@ -0,0 +1,626 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ * Copyright (C) 2016 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define M10V_CLKSEL1 0x0
+#define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
+
+#define M10V_PLL1 "pll1"
+#define M10V_PLL1DIV2 "pll1-2"
+#define M10V_PLL2 "pll2"
+#define M10V_PLL2DIV2 "pll2-2"
+#define M10V_PLL6 "pll6"
+#define M10V_PLL6DIV2 "pll6-2"
+#define M10V_PLL6DIV3 "pll6-3"
+#define M10V_PLL7 "pll7"
+#define M10V_PLL7DIV2 "pll7-2"
+#define M10V_PLL7DIV5 "pll7-5"
+#define M10V_PLL9 "pll9"
+#define M10V_PLL10 "pll10"
+#define M10V_PLL10DIV2 "pll10-2"
+#define M10V_PLL11 "pll11"
+
+#define M10V_SPI_PARENT0 "spi-parent0"
+#define M10V_SPI_PARENT1 "spi-parent1"
+#define M10V_SPI_PARENT2 "spi-parent2"
+#define M10V_UHS1CLK2_PARENT0 "uhs1clk2-parent0"
+#define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1"
+#define M10V_UHS1CLK2_PARENT2 "uhs1clk2-parent2"
+#define M10V_UHS1CLK1_PARENT0 "uhs1clk1-parent0"
+#define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1"
+#define M10V_NFCLK_PARENT0 "nfclk-parent0"
+#define M10V_NFCLK_PARENT1 "nfclk-parent1"
+#define M10V_NFCLK_PARENT2 "nfclk-parent2"
+#define M10V_NFCLK_PARENT3 "nfclk-parent3"
+#define M10V_NFCLK_PARENT4 "nfclk-parent4"
+#define M10V_NFCLK_PARENT5 "nfclk-parent5"
+
+#define M10V_DCHREQ1
+#define M10V_UPOLL_RATE1
+#define M10V_UTIMEOUT 250
+
+#define M10V_EMMCCLK_ID0
+#define M10V_ACLK_ID 1
+#define M10V_HCLK_ID 2
+#define M10V_PCLK_ID 3
+#define M10V_RCLK_ID 4
+#define M10V_SPICLK_ID 5
+#define M10V_NFCLK_ID 6
+#define M10V_NUM_CLKS 7
+
+#define to_m10v_div(_hw)container_of(_hw, struct m10v_clk_divider, hw)
+
+static struct clk_hw_onecell_data *m10v_clk_data;
+
+static DEFINE_SPINLOCK(m10v_crglock);
+
+struct m10v_clk_pll_factors {
+ const char *name;
+ const char *parent_name;
+ u32 div;
+ u32 mult;
+};
+struct m10v_clk_div_factors {
+ const char *name;
+ const char *parent_name;
+ u32 offset;
+ u8 shift;
+ u8 width;
+ const struct clk_div_table *table;
+ unsigned long div_flags;
+ int onecell_idx;
+};
+struct m10v_clk_div_fixed_data {
+ const char *name;
+ const char *parent_name;
+ u8 div;
+ u8 mult;
+ int onecell_idx;
+};
+struct m10v_clk_mux_factors {
+ const char *name;
+ const char * const *parent_names;
+ u8 num_parents;
+ u32 offset;
+ u8 shift;
+ u8 mask;
+ u32 *table;
+ unsigned long mux_flags;
+ int onecell_idx;
+};
+
+static const
[PATCH v2 09/15] dt-bindings: serial: Add Milbeaut serial driver description
Add DT bindings document for Milbeaut serial driver.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/serial/milbeaut-uart.txt| 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt
diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
new file mode 100644
index 000..8f61c38
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
@@ -0,0 +1,21 @@
+Socionext Milbeaut UART controller
+
+Required properties:
+- compatible: should be "socionext,milbeaut-usio-uart".
+- reg: offset and length of the register set for the device.
+- interrupts: two interrupts specifier.
+- clocks: phandle to the input clock.
+- interrupt-names: should be "rx", "tx".
+
+Optional properties:
+- uart-flow-enable: flow control enable.
+
+Example:
+ usio1: usio_uart@1e700010 {
+ compatible = "socionext,milbeaut-usio-uart";
+ reg = <0x1e700010 0x10>;
+ interrupts = <0 141 0x4>, <0 149 0x4>;
+ interrupt-names = "rx", "tx";
+ clocks = < 2>;
+ uart-flow-enable;
+ };
--
1.9.1
[PATCH v2 10/15] serial: Add Milbeaut serial control
Add Milbeaut serial control including earlycon and console.
Signed-off-by: Sugaya Taichi
---
drivers/tty/serial/Kconfig | 25 ++
drivers/tty/serial/Makefile| 1 +
drivers/tty/serial/milbeaut_usio.c | 621 +
include/uapi/linux/serial_core.h | 3 +
4 files changed, 650 insertions(+)
create mode 100644 drivers/tty/serial/milbeaut_usio.c
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 089a6f2..1420195 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1560,6 +1560,31 @@ config SERIAL_RDA_CONSOLE
Say 'Y' here if you wish to use the RDA8810PL UART as the system
console. Only earlycon is implemented currently.
+config SERIAL_MILBEAUT_USIO
+ tristate "Milbeaut USIO/UART serial port support"
+ depends on ARCH_MILBEAUT
+ default y
+ select SERIAL_CORE
+ help
+ This selects the USIO/UART IP found in Socionext Milbeaut SoCs.
+
+config SERIAL_MILBEAUT_USIO_PORTS
+ int "Maximum number of CSIO/UART ports (1-8)"
+ range 1 8
+ depends on SERIAL_MILBEAUT_USIO
+ default "4"
+
+config SERIAL_MILBEAUT_USIO_CONSOLE
+ bool "Support for console on MILBEAUT USIO/UART serial port"
+ depends on SERIAL_MILBEAUT_USIO=y
+ select SERIAL_CORE_CONSOLE
+ select SERIAL_EARLYCON
+ help
+ Say 'Y' here if you wish to use a USIO/UART of Socionext Milbeaut
+ SoCs as the system console (the system console is the device which
+ receives all kernel messages and warnings and which allows logins in
+ single user mode).
+
endmenu
config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 1511e8a..fd6fdbe 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_PIC32)+= pic32_uart.o
obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
obj-$(CONFIG_SERIAL_OWL) += owl-uart.o
obj-$(CONFIG_SERIAL_RDA) += rda-uart.o
+obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
# GPIOLIB helpers for modem control lines
obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/milbeaut_usio.c
b/drivers/tty/serial/milbeaut_usio.c
new file mode 100644
index 000..43729ee
--- /dev/null
+++ b/drivers/tty/serial/milbeaut_usio.c
@@ -0,0 +1,621 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ */
+
+#if defined(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define USIO_NAME "mlb-usio-uart"
+#define USIO_UART_DEV_NAME "ttyUSI"
+
+static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS];
+
+#define RX 0
+#define TX 1
+static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2];
+
+#define MLB_USIO_REG_SMR 0
+#define MLB_USIO_REG_SCR 1
+#define MLB_USIO_REG_ESCR 2
+#define MLB_USIO_REG_SSR 3
+#define MLB_USIO_REG_DR4
+#define MLB_USIO_REG_BGR 6
+#define MLB_USIO_REG_FCR 12
+#define MLB_USIO_REG_FBYTE 14
+
+#define MLB_USIO_SMR_SOE BIT(0)
+#define MLB_USIO_SMR_SBL BIT(3)
+#define MLB_USIO_SCR_TXE BIT(0)
+#define MLB_USIO_SCR_RXE BIT(1)
+#define MLB_USIO_SCR_TBIE BIT(2)
+#define MLB_USIO_SCR_TIE BIT(3)
+#define MLB_USIO_SCR_RIE BIT(4)
+#define MLB_USIO_SCR_UPCL BIT(7)
+#define MLB_USIO_ESCR_L_8BIT 0
+#define MLB_USIO_ESCR_L_5BIT 1
+#define MLB_USIO_ESCR_L_6BIT 2
+#define MLB_USIO_ESCR_L_7BIT 3
+#define MLB_USIO_ESCR_PBIT(3)
+#define MLB_USIO_ESCR_PEN BIT(4)
+#define MLB_USIO_ESCR_FLWENBIT(7)
+#define MLB_USIO_SSR_TBI BIT(0)
+#define MLB_USIO_SSR_TDRE BIT(1)
+#define MLB_USIO_SSR_RDRF BIT(2)
+#define MLB_USIO_SSR_ORE BIT(3)
+#define MLB_USIO_SSR_FRE BIT(4)
+#define MLB_USIO_SSR_PEBIT(5)
+#define MLB_USIO_SSR_REC BIT(7)
+#define MLB_USIO_SSR_BRK BIT(8)
+#define MLB_USIO_FCR_FE1 BIT(0)
+#define MLB_USIO_FCR_FE2 BIT(1)
+#define MLB_USIO_FCR_FCL1 BIT(2)
+#define MLB_USIO_FCR_FCL2 BIT(3)
+#define MLB_USIO_FCR_FSET BIT(4)
+#define MLB_USIO_FCR_FTIE BIT(9)
+#define MLB_USIO_FCR_FDRQ BIT(10)
+#define MLB_USIO_FCR_FRIIE BIT(11)
+
+static void mlb_usio_stop_tx(struct uart_port *port)
+{
+ writew(readw(port->membase + MLB_USIO_REG_FCR
[PATCH v2 03/15] dt-bindings: Add documentation for Milbeaut SoCs
This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- Documentation/devicetree/bindings/arm/milbeaut.txt | 6 ++ 1 file changed, 6 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/milbeaut.txt diff --git a/Documentation/devicetree/bindings/arm/milbeaut.txt b/Documentation/devicetree/bindings/arm/milbeaut.txt new file mode 100644 index 000..9fd053a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/milbeaut.txt @@ -0,0 +1,6 @@ +Milbeaut platforms device tree bindings +--- + +- Milbeaut M10V Evaluation Board +Required root node properties: + - compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; -- 1.9.1
[PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC
This adds the basic M10V SoC support under arch/arm.
Since all cores are activated in the custom bootloader before booting
linux, it is necessary to wait for the secondary-cores using cpu-enable-
method and special sram.
Signed-off-by: Sugaya Taichi
---
arch/arm/Kconfig | 2 +
arch/arm/Makefile| 1 +
arch/arm/mach-milbeaut/Kconfig | 20 ++
arch/arm/mach-milbeaut/Makefile | 1 +
arch/arm/mach-milbeaut/platsmp.c | 144 +++
5 files changed, 168 insertions(+)
create mode 100644 arch/arm/mach-milbeaut/Kconfig
create mode 100644 arch/arm/mach-milbeaut/Makefile
create mode 100644 arch/arm/mach-milbeaut/platsmp.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 664e918..c8cb752 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -750,6 +750,8 @@ source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-meson/Kconfig"
+source "arch/arm/mach-milbeaut/Kconfig"
+
source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-moxart/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9db3c58..0e9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_MXC) += imx
machine-$(CONFIG_ARCH_MEDIATEK)+= mediatek
+machine-$(CONFIG_ARCH_MILBEAUT)+= milbeaut
machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_NETX)+= netx
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
diff --git a/arch/arm/mach-milbeaut/Kconfig b/arch/arm/mach-milbeaut/Kconfig
new file mode 100644
index 000..6a576fd
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Kconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0
+menuconfig ARCH_MILBEAUT
+ bool "Socionext Milbeaut SoCs"
+ depends on ARCH_MULTI_V7
+ select ARM_GIC
+ help
+ This enables support for Socionext Milbeaut SoCs
+
+if ARCH_MILBEAUT
+
+config ARCH_MILBEAUT_M10V
+ bool "Milbeaut SC2000/M10V platform"
+ select ARM_ARCH_TIMER
+ select MILBEAUT_TIMER
+ select PINCTRL
+ select PINCTRL_MILBEAUT
+ help
+ Support for Socionext's MILBEAUT M10V based systems
+
+endif
diff --git a/arch/arm/mach-milbeaut/Makefile b/arch/arm/mach-milbeaut/Makefile
new file mode 100644
index 000..ce5ea06
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-milbeaut/platsmp.c b/arch/arm/mach-milbeaut/platsmp.c
new file mode 100644
index 000..bdcd98e
--- /dev/null
+++ b/arch/arm/mach-milbeaut/platsmp.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright: (C) 2018 Socionext Inc.
+ * Copyright: (C) 2015 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define M10V_MAX_CPU 4
+#define KERNEL_UNBOOT_FLAG 0x12345678
+
+static void __iomem *m10v_smp_base;
+
+static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
+{
+ unsigned int mpidr, cpu, cluster;
+
+ if (!m10v_smp_base)
+ return -ENXIO;
+
+ mpidr = cpu_logical_map(l_cpu);
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ if (cpu >= M10V_MAX_CPU)
+ return -EINVAL;
+
+ pr_info("%s: cpu %u l_cpu %u cluster %u\n",
+ __func__, cpu, l_cpu, cluster);
+
+ writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);
+ arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
+
+ return 0;
+}
+
+static void m10v_smp_init(unsigned int max_cpus)
+{
+ unsigned int mpidr, cpu, cluster;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram");
+ if (!np)
+ return;
+
+ m10v_smp_base = of_iomap(np, 0);
+ if (!m10v_smp_base)
+ return;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster);
+
+ for (cpu = 0; cpu < M10V_MAX_CPU; cpu++)
+ writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+}
+
+static void m10v_cpu_die(unsigned int l_cpu)
+{
+ gic_cpu_if_down(0);
+ v7_exit_coherency_flush(louis);
+ wfi();
+}
+
+static int m10v_cpu_kill(unsigned int l_cpu)
+{
+ unsigned int mpidr, cpu;
+
+ mpidr = cpu_logical_map(l_cpu);
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
+ writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+
+ return 1;
+}
+
+static struct smp_operations m10v_smp_ops __initdata = {
+ .smp_p
[PATCH v2 06/15] clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs
Add timer driver for Milbeaut SoCs series.
The timer has two 32-bit width down counters, one of which is configured
as a clockevent device and the other is configured as a clock source.
Signed-off-by: Sugaya Taichi
---
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-milbeaut.c | 161 +++
3 files changed, 171 insertions(+)
create mode 100644 drivers/clocksource/timer-milbeaut.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a9e26f6..9101b8f 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -634,4 +634,13 @@ config GX6605S_TIMER
help
This option enables support for gx6605s SOC's timer.
+config MILBEAUT_TIMER
+ bool "Milbeaut timer driver" if COMPILE_TEST
+ depends on OF
+ depends on ARM
+ select TIMER_OF
+ select CLKSRC_MMIO
+ help
+ Enables the support for Milbeaut timer driver.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index cdd210f..6f2543b 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
obj-$(CONFIG_OWL_TIMER)+= timer-owl.o
+obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
obj-$(CONFIG_NPCM7XX_TIMER)+= timer-npcm7xx.o
obj-$(CONFIG_RDA_TIMER)+= timer-rda.o
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
new file mode 100644
index 000..f2019a8
--- /dev/null
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "timer-of.h"
+
+#define MLB_TMR_TMCSR_OFS 0x0
+#define MLB_TMR_TMR_OFS0x4
+#define MLB_TMR_TMRLR1_OFS 0x8
+#define MLB_TMR_TMRLR2_OFS 0xc
+#define MLB_TMR_REGSZPCH 0x10
+
+#define MLB_TMR_TMCSR_OUTL BIT(5)
+#define MLB_TMR_TMCSR_RELD BIT(4)
+#define MLB_TMR_TMCSR_INTE BIT(3)
+#define MLB_TMR_TMCSR_UF BIT(2)
+#define MLB_TMR_TMCSR_CNTE BIT(1)
+#define MLB_TMR_TMCSR_TRG BIT(0)
+
+#define MLB_TMR_TMCSR_CSL_DIV2 0
+#define MLB_TMR_DIV_CNT2
+
+#define MLB_TMR_SRC_CH (1)
+#define MLB_TMR_EVT_CH (0)
+
+#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
+#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
+
+#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_SRC_TMR_OFS(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
+#define MLB_TMR_EVT_TMR_OFS(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
+#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
+#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
+
+#define MLB_TIMER_RATING 500
+
+static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *clk = dev_id;
+ struct timer_of *to = to_timer_of(clk);
+ u32 val;
+
+ val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ val &= ~MLB_TMR_TMCSR_UF;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ clk->event_handler(clk);
+
+ return IRQ_HANDLED;
+}
+
+static int mlb_set_state_periodic(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+
+ writel_relaxed(to->of_clk.period, timer_of_base(to) +
+ MLB_TMR_EVT_TMRLR1_OFS);
+ val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
+ MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_set_state_oneshot(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
+static int mlb_clkevt_next_event(unsigned long event,
+ struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
+ writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
+ MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
+
[PATCH v2 07/15] ndings: clock: milbeaut: add Milbeaut clock description
Add DT bindings document for Milbeaut clock.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/clock/milbeaut-clock.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/milbeaut-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.txt
b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt
new file mode 100644
index 000..bcfc5df
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt
@@ -0,0 +1,49 @@
+Milbeaut SoCs Clock Controller Binding
+
+Milbeaut SoCs Clock controller is an integrated clock controller, which
+generates and supplies to all modules.
+
+This binding uses common clock bindings
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,milbeaut-m10v-ccu" - for M10V SoC
+- reg: shall contain base address and length of clock registers
+- #clock-cells: shall be 1
+- clocks: shall be an external clock
+
+Example: Clock controller node:
+
+ clk: m10v-clk-ctrl@1d021000 {
+ compatible = "socionext,milbeaut-m10v-clk-ccu";
+ reg = <0x1d021000 0x4000>;
+ #clock-cells = <1>
+ clocks = <>
+ };
+
+Example: Required an external clock for Clock controller node:
+
+ clocks {
+ clki40mhz: clki40mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000>;
+ };
+
+ /* other clocks */
+ };
+
+The clock consumer shall specify the desired clock-output of the clock
+controller as below by specifying output-id in its "clk" phandle cell.
+2: uart
+4: 32-bit timer
+
+Example: uart1 node:
+ uart1: serial@1e700010 {
+ compatible = "socionext,milbeaut-usio-uart";
+ reg = <0x1e700010 0x10>;
+ interrupts = <0 141 0x4>, <0 149 0x4>;
+ interrupt-names = "rx", "tx";
+ clocks = < 2>;
+ };
--
1.9.1
[PATCH v2 02/15] dt-bindings: arm: Add SMP enable-method for Milbeaut
This adds a compatible string "socionext,milbeaut-m10v-smp" for Milbeaut M10V to the 32 bit ARM CPU device tree binding. Signed-off-by: Sugaya Taichi --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 298c17b..365dcf3 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -228,6 +228,7 @@ patternProperties: - renesas,r9a06g032-smp - rockchip,rk3036-smp - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp - ste,dbx500-smp cpu-release-addr: -- 1.9.1
[PATCH v2 00/15] Add basic support for Socionext Milbeaut M10V SoC
Hi, Here is the series of patches the initial support for SC2000(M10V) of Milbeaut SoCs. "M10V" is the internal name of SC2000, so commonly used in source code. SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for computer vision. It also features advanced functionalities such as 360-degree, real-time spherical stitching with multi cameras, image stabilization for without mechanical gimbals, and rolling shutter correction. More detail is below: https://www.socionext.com/en/products/assp/milbeaut/SC2000.html Specifications for developers are below: - Quad-core 32bit Cortex-A7 on ARMv7-A architecture - NEON support - DSP - GPU - MAX 3GB DDR3 - Cortex-M0 for power control - NAND Flash Interface - SD UHS-I - SD UHS-II - SDIO - USB2.0 HOST / Device - USB3.0 HOST / Device - PCI express Gen2 - Ethernet Engine - I2C - UART - SPI - PWM Support is quite minimal for now, since it only includes timer, clock, pictrl and serial controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals will come eventually. Changes since v1: * Change file names. * Change #define names. * Refine cpu-enable-method and bindigs. * Add documentation for Milbeaut SoCs. * Add more infomation for timer driver. * Add sched_clock to timer driver. * Refine whole of clk driver. * Add earlycon instead of earlyprintk. * Refine Device Tree. Sugaya Taichi (15): dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram dt-bindings: arm: Add SMP enable-method for Milbeaut dt-bindings: Add documentation for Milbeaut SoCs ARM: milbeaut: Add basic support for Milbeaut m10v SoC dt-bindings: timer: Add Milbeaut M10V timer description clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs ndings: clock: milbeaut: add Milbeaut clock description clock: milbeaut: Add Milbeaut M10V clock controller dt-bindings: serial: Add Milbeaut serial driver description serial: Add Milbeaut serial control dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description pinctrl: milbeaut: Add Milbeaut M10V pinctrl ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board ARM: configs: Add Milbeaut M10V defconfig MAINTAINERS: Add entry to MAINTAINERS for Milbeaut Documentation/devicetree/bindings/arm/cpus.yaml| 1 + Documentation/devicetree/bindings/arm/milbeaut.txt | 6 + .../devicetree/bindings/clock/milbeaut-clock.txt | 49 ++ .../pinctrl/socionext,milbeaut-pinctrl.txt | 35 + .../devicetree/bindings/serial/milbeaut-uart.txt | 21 + .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 + .../bindings/timer/socionext,milbeaut-timer.txt| 17 + MAINTAINERS| 9 + arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/milbeaut-m10v-evb.dts| 32 + arch/arm/boot/dts/milbeaut-m10v.dtsi | 131 arch/arm/configs/milbeaut_m10v_defconfig | 366 ++ arch/arm/mach-milbeaut/Kconfig | 20 + arch/arm/mach-milbeaut/Makefile| 1 + arch/arm/mach-milbeaut/platsmp.c | 144 drivers/clk/Makefile | 1 + drivers/clk/clk-milbeaut.c | 626 + drivers/clocksource/Kconfig| 9 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-milbeaut.c | 161 + drivers/pinctrl/Kconfig| 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-milbeaut.c | 759 + drivers/tty/serial/Kconfig | 25 + drivers/tty/serial/Makefile| 1 + drivers/tty/serial/milbeaut_usio.c | 621 + include/uapi/linux/serial_core.h | 3 + 29 files changed, 3077 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/milbeaut.txt create mode 100644 Documentation/devicetree/bindings/clock/milbeaut-clock.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig create mode 100644 arch/arm/mach-milbeaut/Kconfig create mode 100644 arch/arm/mach-milbeaut/Makefile create mode 100644 arch/arm/mach-milbeaut/platsmp.c create mode 100644 d
[PATCH v2 05/15] dt-bindings: timer: Add Milbeaut M10V timer description
Add DT bindings document for Milbeaut M10V timer.
Signed-off-by: Sugaya Taichi
---
.../bindings/timer/socionext,milbeaut-timer.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
diff --git
a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
new file mode 100644
index 000..ac44c4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
@@ -0,0 +1,17 @@
+Milbeaut SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "socionext,milbeaut-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer.
+- clocks: phandle to the input clk.
+
+Example:
+
+timer {
+ compatible = "socionext,milbeaut-timer";
+ reg = <0x1e50 0x20>
+ interrupts = <0 91 4>;
+ clocks = < 4>;
+};
--
1.9.1
[PATCH v2 01/15] dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram
The Milbeaut M10V SoC needs a part of sram for smp, so this adds the
M10V sram compatible and binding.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
diff --git a/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
new file mode 100644
index 000..194f6a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
@@ -0,0 +1,24 @@
+Milbeaut SRAM for smp bringup
+
+Milbeaut SoCs use a part of the sram for the bringup of the secondary cores.
+Once they get powered up in the bootloader, they stay at the specific part
+of the sram.
+Therefore the part needs to be added as the sub-node of mmio-sram.
+
+Required sub-node properties:
+- compatible : should be "socionext,milbeaut-smp-sram"
+
+Example:
+
+sram: sram@0 {
+compatible = "mmio-sram";
+reg = <0x0 0x1>;
+#address-cells = <1>;
+#size-cells = <1>;
+ranges = <0 0x0 0x1>;
+
+smp-sram@f100 {
+compatible = "socionext,milbeaut-smp-sram";
+reg = <0xf100 0x20>;
+};
+};
--
1.9.1
Re: [PATCH 02/14] dt-bindings: soc: milbeaut: Add Milbeaut trampoline description
Hi,
On 2019/01/22 20:50, Russell King - ARM Linux admin wrote:
On Tue, Jan 22, 2019 at 08:36:03PM +0900, Sugaya, Taichi wrote:
Hi
On 2018/12/04 22:32, Rob Herring wrote:
On Tue, Dec 4, 2018 at 5:30 AM Sugaya, Taichi
wrote:
Hi
On 2018/12/04 0:49, Rob Herring wrote:
On Mon, Dec 3, 2018 at 1:42 AM Sugaya, Taichi
wrote:
Hi,
On 2018/11/30 17:16, Stephen Boyd wrote:
Quoting Sugaya, Taichi (2018-11-29 04:24:51)
On 2018/11/28 11:01, Stephen Boyd wrote:
Quoting Sugaya Taichi (2018-11-18 17:01:07)
create mode 100644
Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt
b/Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt
new file mode 100644
index 000..f5d906c
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt
@@ -0,0 +1,12 @@
+Socionext M10V SMP trampoline driver binding
+
+This is a driver to wait for sub-cores while boot process.
+
+- compatible: should be "socionext,smp-trampoline"
+- reg: should be <0x4C000100 0x100>
+
+EXAMPLE
+ trampoline: trampoline@0x4C000100 {
Drop the 0x part of unit addresses.
Okay.
+ compatible = "socionext,smp-trampoline";
+ reg = <0x4C000100 0x100>;
Looks like a software construct, which we wouldn't want to put into DT
this way. DT doesn't describe drivers.
We would like to use this node only getting the address of the
trampoline area
in which sub-cores wait. (They have finished to go to this area in previous
bootloader process.)
Is this area part of memory, or a special SRAM? If it's part of memory,
I would expect this node to be under the reserved-memory node and
pointed to by some other node that uses this region. Could even be the
CPU nodes.
Yes, 0x4C000100 is a part of memory under the reserved-memory node. So
we would like to use the SRAM ( allocated 0x ) area instead.
BTW, sorry, the trampoline address of this example is simply wrong. We
were going to use a part of the SRAM from the beginning.
So should we embed the constant value in source codes instead of getting
from
DT because the address is constant at the moment? Or is there other
approach?
If it's constant then that also works. Why does it need to come from DT
at all then?
We think it is not good to embed constant value in driver codes and do
not have another way...
Are there better ways?
If this is just memory, can you use the standard spin-table binding in
the DT spec? There are some requirements like 64-bit values even on
32-bit machines (though this gets violated).
The spin-table seems to be used on only 64-bit arch. Have it ever worked
on 32-bit machine?
Yes.
And I would like not to use it because avoid violation.
The issue now that I remember is cpu-release-addr is defined to always
be a 64-bit value while some platforms made it a 32-bit value.
'cpu-release-addr' is also used for some other enable-methods.
I have a question about the spin-table.
The code "smp_spin_table.c" is only in "arch/arm64/kernel" directory so can
not be compiled in arm-v7 arch. That means the spin-table can not be used
arm-v7 arch..? , or is there the way to compile the code in arm-v7 arch?
Why do you think you need it? Do you have no way to control individual
CPUs?
We are going through a process in 32-bit eliminating the "spin table"
stuff from platforms.
Not always necessary to us and considering the history I think it is not
suitable to use the spin-table.
I try to use another way.
Re: [PATCH 02/14] dt-bindings: soc: milbeaut: Add Milbeaut trampoline description
Hi
On 2018/12/04 22:32, Rob Herring wrote:
On Tue, Dec 4, 2018 at 5:30 AM Sugaya, Taichi
wrote:
Hi
On 2018/12/04 0:49, Rob Herring wrote:
On Mon, Dec 3, 2018 at 1:42 AM Sugaya, Taichi
wrote:
Hi,
On 2018/11/30 17:16, Stephen Boyd wrote:
Quoting Sugaya, Taichi (2018-11-29 04:24:51)
On 2018/11/28 11:01, Stephen Boyd wrote:
Quoting Sugaya Taichi (2018-11-18 17:01:07)
create mode 100644
Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt
b/Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt
new file mode 100644
index 000..f5d906c
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt
@@ -0,0 +1,12 @@
+Socionext M10V SMP trampoline driver binding
+
+This is a driver to wait for sub-cores while boot process.
+
+- compatible: should be "socionext,smp-trampoline"
+- reg: should be <0x4C000100 0x100>
+
+EXAMPLE
+ trampoline: trampoline@0x4C000100 {
Drop the 0x part of unit addresses.
Okay.
+ compatible = "socionext,smp-trampoline";
+ reg = <0x4C000100 0x100>;
Looks like a software construct, which we wouldn't want to put into DT
this way. DT doesn't describe drivers.
We would like to use this node only getting the address of the
trampoline area
in which sub-cores wait. (They have finished to go to this area in previous
bootloader process.)
Is this area part of memory, or a special SRAM? If it's part of memory,
I would expect this node to be under the reserved-memory node and
pointed to by some other node that uses this region. Could even be the
CPU nodes.
Yes, 0x4C000100 is a part of memory under the reserved-memory node. So
we would like to use the SRAM ( allocated 0x ) area instead.
BTW, sorry, the trampoline address of this example is simply wrong. We
were going to use a part of the SRAM from the beginning.
So should we embed the constant value in source codes instead of getting
from
DT because the address is constant at the moment? Or is there other
approach?
If it's constant then that also works. Why does it need to come from DT
at all then?
We think it is not good to embed constant value in driver codes and do
not have another way...
Are there better ways?
If this is just memory, can you use the standard spin-table binding in
the DT spec? There are some requirements like 64-bit values even on
32-bit machines (though this gets violated).
The spin-table seems to be used on only 64-bit arch. Have it ever worked
on 32-bit machine?
Yes.
And I would like not to use it because avoid violation.
The issue now that I remember is cpu-release-addr is defined to always
be a 64-bit value while some platforms made it a 32-bit value.
'cpu-release-addr' is also used for some other enable-methods.
I have a question about the spin-table.
The code "smp_spin_table.c" is only in "arch/arm64/kernel" directory so
can not be compiled in arm-v7 arch. That means the spin-table can not be
used arm-v7 arch..? , or is there the way to compile the code in arm-v7
arch?
Thanks,
Sugaya Taichi
Rob
Re: [PATCH 07/14] clock: milbeaut: Add Milbeaut M10V clock control
Hi On 2018/12/28 9:39, Stephen Boyd wrote: Quoting Sugaya, Taichi (2018-12-25 17:35:27) Hi On 2018/11/30 17:31, Stephen Boyd wrote: + init.num_parents = parents; + init.parent_names = parent_names; + + mcm->cname = clk_name; + mcm->parent = 0; + mcm->hw.init = + + clk = clk_register(NULL, >hw); + if (IS_ERR(clk)) + goto err_clk; + + of_clk_add_provider(node, of_clk_src_simple_get, clk); + return; + +err_clk: + kfree(mcm); +err_mcm: + kfree(parent_names); +} +CLK_OF_DECLARE(m10v_clk_mux, "socionext,milbeaut-m10v-clk-mux", + m10v_clk_mux_setup); Any chance you can use a platform driver? Excuse me to re-ask you. Why do you recommend to use a platform driver? Is that current fad? Not exactly a fad. We've been doing it for some time now. From an older email on the list: Reasons (in no particular order): 1. We get a dev pointer to use with clk_hw_register() 2. We can handle probe defer if some resource is not available 3. Using device model gets us a hook into power management frameworks like runtime PM and system PM for things like suspend and hibernate 4. It encourages a single DT node clk controller style binding instead of a single node per clk style binding 5. We can use non-DT specific functions like devm_ioremap_resource() to map registers and acquire other resources, leading to more portable and generic code 6. We may be able to make the device driver a module, which will make distros happy if we don't have to compile in all these clk drivers to the resulting vmlinux Great thanks for answering. I strongly understand. #It takes a bit of time to send v2. Best Regards, Sugaya Taichi
Re: [PATCH 07/14] clock: milbeaut: Add Milbeaut M10V clock control
Hi On 2018/11/30 17:31, Stephen Boyd wrote: + init.num_parents = parents; + init.parent_names = parent_names; + + mcm->cname = clk_name; + mcm->parent = 0; + mcm->hw.init = + + clk = clk_register(NULL, >hw); + if (IS_ERR(clk)) + goto err_clk; + + of_clk_add_provider(node, of_clk_src_simple_get, clk); + return; + +err_clk: + kfree(mcm); +err_mcm: + kfree(parent_names); +} +CLK_OF_DECLARE(m10v_clk_mux, "socionext,milbeaut-m10v-clk-mux", + m10v_clk_mux_setup); Any chance you can use a platform driver? Excuse me to re-ask you. Why do you recommend to use a platform driver? Is that current fad? Thanks Sugaya Taichi
Re: [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description
Hi,
Thank you for your comments.
On 2018/12/05 8:11, Rob Herring wrote:
On Mon, Nov 19, 2018 at 10:02:12AM +0900, Sugaya Taichi wrote:
Add DT bindings document for Milbeaut M10V pinctrl.
Signed-off-by: Sugaya Taichi
---
.../pinctrl/socionext,milbeaut-pinctrl.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
diff --git
a/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
new file mode 100644
index 000..7469189
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
@@ -0,0 +1,33 @@
+Milbeaut SoCs pin controller
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,milbeaut-m10v-pinctrl" - for m10v SoC
+- reg: offset and length of the register set.
+- reg-names: should be "pinctrl", "exiu".
+- gpio-cells; should be 2.
#gpio-cells
gpio-controller?
Ah yes. I forgot to add it.
Add it.
+- interrupt-cells: should be 2.
#interrupt-cells
interrupt-controller?
Add it also.
Thanks,
Sugaya Taichi
+- clocks: phandle to the input clock.
+- interrupts: three interrupts specifer.
+- interrupt-names: corresponds "interrupts" factor.
+
+Example:
+ pinctrl: pinctrl@1d022000 {
+ compatible = "socionext,milbeaut-m10v-pinctrl";
+ reg = <0x1d022000 0x1000>,
+ <0x1c26f000 0x1000>;
+ reg-names = "pinctrl", "exiu";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <_clk>;
+ interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>,
+ <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>,
+ <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>,
+ <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>;
+ interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51",
+ "pin-52", "pin-53", "pin-54", "pin-55",
+ "pin-56", "pin-57", "pin-58", "pin-59",
+ "pin-60", "pin-61", "pin-62", "pin-63";
+ }
--
1.9.1
Re: [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description
Hi,
Thank you for your comments.
On 2018/12/05 8:11, Rob Herring wrote:
On Mon, Nov 19, 2018 at 10:02:12AM +0900, Sugaya Taichi wrote:
Add DT bindings document for Milbeaut M10V pinctrl.
Signed-off-by: Sugaya Taichi
---
.../pinctrl/socionext,milbeaut-pinctrl.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
diff --git
a/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
new file mode 100644
index 000..7469189
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
@@ -0,0 +1,33 @@
+Milbeaut SoCs pin controller
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,milbeaut-m10v-pinctrl" - for m10v SoC
+- reg: offset and length of the register set.
+- reg-names: should be "pinctrl", "exiu".
+- gpio-cells; should be 2.
#gpio-cells
gpio-controller?
Ah yes. I forgot to add it.
Add it.
+- interrupt-cells: should be 2.
#interrupt-cells
interrupt-controller?
Add it also.
Thanks,
Sugaya Taichi
+- clocks: phandle to the input clock.
+- interrupts: three interrupts specifer.
+- interrupt-names: corresponds "interrupts" factor.
+
+Example:
+ pinctrl: pinctrl@1d022000 {
+ compatible = "socionext,milbeaut-m10v-pinctrl";
+ reg = <0x1d022000 0x1000>,
+ <0x1c26f000 0x1000>;
+ reg-names = "pinctrl", "exiu";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <_clk>;
+ interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>,
+ <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>,
+ <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>,
+ <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>;
+ interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51",
+ "pin-52", "pin-53", "pin-54", "pin-55",
+ "pin-56", "pin-57", "pin-58", "pin-59",
+ "pin-60", "pin-61", "pin-62", "pin-63";
+ }
--
1.9.1
Re: [PATCH 04/14] dt-bindings: timer: Add Milbeaut M10V timer description
Hi,
Thank you for your comments.
On 2018/12/05 8:03, Rob Herring wrote:
On Mon, Nov 19, 2018 at 10:01:09AM +0900, Sugaya Taichi wrote:
Add DT bindings document for Milbeaut M10V timer.
Signed-off-by: Sugaya Taichi
---
.../bindings/timer/socionext,milbeaut-timer.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
diff --git
a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
new file mode 100644
index 000..ddb1b31
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
@@ -0,0 +1,17 @@
+Milbeaut SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "socionext,milbeaut-m10v-timer"
+- reg : Specifies base physical address and size of the registers.
How many register ranges? Looks like 2.
Yes, has two ranges.
So add the description about it.
+- interrupts : The interrupt of the first timer
+- clocks: should be "rclk"
+
+Example:
+
+timer {
timer@1e000050
Okay.
Thanks
Sugaya Taichi
+ compatible = "socionext,milbeaut-m10v-timer";
+ reg = <0x1e50 0x10>, <0x1e60 0x10>;
+ interrupts = <0 91 4>;
+ clocks = <>;
+};
--
1.9.1
Re: [PATCH 04/14] dt-bindings: timer: Add Milbeaut M10V timer description
Hi,
Thank you for your comments.
On 2018/12/05 8:03, Rob Herring wrote:
On Mon, Nov 19, 2018 at 10:01:09AM +0900, Sugaya Taichi wrote:
Add DT bindings document for Milbeaut M10V timer.
Signed-off-by: Sugaya Taichi
---
.../bindings/timer/socionext,milbeaut-timer.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
diff --git
a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
new file mode 100644
index 000..ddb1b31
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
@@ -0,0 +1,17 @@
+Milbeaut SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "socionext,milbeaut-m10v-timer"
+- reg : Specifies base physical address and size of the registers.
How many register ranges? Looks like 2.
Yes, has two ranges.
So add the description about it.
+- interrupts : The interrupt of the first timer
+- clocks: should be "rclk"
+
+Example:
+
+timer {
timer@1e000050
Okay.
Thanks
Sugaya Taichi
+ compatible = "socionext,milbeaut-m10v-timer";
+ reg = <0x1e50 0x10>, <0x1e60 0x10>;
+ interrupts = <0 91 4>;
+ clocks = <>;
+};
--
1.9.1
Re: [PATCH 07/14] clock: milbeaut: Add Milbeaut M10V clock control
Hi
On 2018/12/05 3:15, Stephen Boyd wrote:
Quoting Sugaya, Taichi (2018-12-04 00:26:16)
On 2018/11/30 17:31, Stephen Boyd wrote:
Quoting Sugaya Taichi (2018-11-18 17:01:12)
+void __init m10v_clk_mux_setup(struct device_node *node)
+{
+ const char *clk_name = node->name;
+ struct clk_init_data init;
+ const char **parent_names;
+ struct m10v_mux *mcm;
+ struct clk *clk;
+ int i, parents;
+
+ if (!m10v_clk_iomap())
+ return;
+
+ of_property_read_string(node, "clock-output-names", _name);
+
+ parents = of_clk_get_parent_count(node);
+ if (parents < 2) {
+ pr_err("%s: not a mux\n", clk_name);
How is this possible?
When the node has more than 1 clks...
Or I am misunderstanding your question?
This looks like code that's checking DT for correctness. We don't
typically do that in the kernel because the kernel isn't a DT validator.
That's all I'm saying. I think this comment is not useful if the driver
design is done to specify parent linkages in C code instead of DT, so
don't worry about this too much.
I understand.
Thank you for additional information.
Sugaya Taichi
Re: [PATCH 07/14] clock: milbeaut: Add Milbeaut M10V clock control
Hi
On 2018/12/05 3:15, Stephen Boyd wrote:
Quoting Sugaya, Taichi (2018-12-04 00:26:16)
On 2018/11/30 17:31, Stephen Boyd wrote:
Quoting Sugaya Taichi (2018-11-18 17:01:12)
+void __init m10v_clk_mux_setup(struct device_node *node)
+{
+ const char *clk_name = node->name;
+ struct clk_init_data init;
+ const char **parent_names;
+ struct m10v_mux *mcm;
+ struct clk *clk;
+ int i, parents;
+
+ if (!m10v_clk_iomap())
+ return;
+
+ of_property_read_string(node, "clock-output-names", _name);
+
+ parents = of_clk_get_parent_count(node);
+ if (parents < 2) {
+ pr_err("%s: not a mux\n", clk_name);
How is this possible?
When the node has more than 1 clks...
Or I am misunderstanding your question?
This looks like code that's checking DT for correctness. We don't
typically do that in the kernel because the kernel isn't a DT validator.
That's all I'm saying. I think this comment is not useful if the driver
design is done to specify parent linkages in C code instead of DT, so
don't worry about this too much.
I understand.
Thank you for additional information.
Sugaya Taichi
