Re: [PATCH v1 1/1] ARM: EXYNOS: fix DEBUG_LL on Cortex-A7.
Hi Chanho, On Mon, May 18, 2015 at 4:52 AM, Chanho Park wrote: > > Please see previous Joonyoung's patch. Your patch could break > exynos3250 because it has not only two cortex-a7 cpus but also uses > EXYOS4_PA_UART. > > http://www.spinics.net/lists/linux-samsung-soc/msg37318.html > Thanks, Joonyoung's patch works for me and it seems really reasonable to check cluster id. Best regards, Tarek -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1 1/1] ARM: EXYNOS: fix DEBUG_LL on Cortex-A7.
Hi Chanho, On Mon, May 18, 2015 at 4:52 AM, Chanho Park parkc...@gmail.com wrote: Please see previous Joonyoung's patch. Your patch could break exynos3250 because it has not only two cortex-a7 cpus but also uses EXYOS4_PA_UART. http://www.spinics.net/lists/linux-samsung-soc/msg37318.html Thanks, Joonyoung's patch works for me and it seems really reasonable to check cluster id. Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/1] ARM: EXYNOS: fix DEBUG_LL on Cortex-A7.
Cortex-A7 has EXYNOS5_PA_UART base address for UART. If system boots from Cortex-A7 CPU addruart loads wrong address. This patch fixex this. Signed-off-by: Tarek Dakhran --- arch/arm/include/debug/exynos.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/debug/exynos.S b/arch/arm/include/debug/exynos.S index b17fdb7..a61b3ea 100644 --- a/arch/arm/include/debug/exynos.S +++ b/arch/arm/include/debug/exynos.S @@ -24,6 +24,7 @@ mrc p15, 0, \tmp, c0, c0, 0 and \tmp, \tmp, #0xf0 teq \tmp, #0xf0 @@ A15 + teqne \tmp, #0x70 @@ A7 ldreq \rp, =EXYNOS5_PA_UART movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4 ldr \rv, =S3C_VA_UART -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 0/1] fix DEBUG_LL on Cortex-A7.
When system boots from Cortex-A7 addruart loads wrong base UART address. This patch fixex problem. Patch tested on Hardkernel Odroid-XU3 board on linux kernel v4.0. Tarek Dakhran (1): ARM: EXYNOS: fix DEBUG_LL on Cortex-A7. arch/arm/include/debug/exynos.S | 1 + 1 file changed, 1 insertion(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/1] ARM: EXYNOS: fix DEBUG_LL on Cortex-A7.
Cortex-A7 has EXYNOS5_PA_UART base address for UART. If system boots from Cortex-A7 CPU addruart loads wrong address. This patch fixex this. Signed-off-by: Tarek Dakhran t.dakh...@gmail.com --- arch/arm/include/debug/exynos.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/debug/exynos.S b/arch/arm/include/debug/exynos.S index b17fdb7..a61b3ea 100644 --- a/arch/arm/include/debug/exynos.S +++ b/arch/arm/include/debug/exynos.S @@ -24,6 +24,7 @@ mrc p15, 0, \tmp, c0, c0, 0 and \tmp, \tmp, #0xf0 teq \tmp, #0xf0 @@ A15 + teqne \tmp, #0x70 @@ A7 ldreq \rp, =EXYNOS5_PA_UART movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4 ldr \rv, =S3C_VA_UART -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 0/1] fix DEBUG_LL on Cortex-A7.
When system boots from Cortex-A7 addruart loads wrong base UART address. This patch fixex problem. Patch tested on Hardkernel Odroid-XU3 board on linux kernel v4.0. Tarek Dakhran (1): ARM: EXYNOS: fix DEBUG_LL on Cortex-A7. arch/arm/include/debug/exynos.S | 1 + 1 file changed, 1 insertion(+) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: exynos5410: Fill in CPU clock-frequency
On 06/22/2014 11:49 PM, Andreas Färber wrote: It's 1.6 GHz for the Cortex-A15. Avoids warnings like "/cpus/cpu@0 missing clock-frequency property". Signed-off-by: Andreas Färber --- arch/arm/boot/dts/exynos5410.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 3839c26..9d0b8cc 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -28,24 +28,28 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + clock-frequency = <160000>; Reviewed-by: Tarek Dakhran -- Best regards, Tarek Dakhran -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: exynos5410: Fill in CPU clock-frequency
On 06/22/2014 11:49 PM, Andreas Färber wrote: It's 1.6 GHz for the Cortex-A15. Avoids warnings like /cpus/cpu@0 missing clock-frequency property. Signed-off-by: Andreas Färber afaer...@suse.de --- arch/arm/boot/dts/exynos5410.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 3839c26..9d0b8cc 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -28,24 +28,28 @@ device_type = cpu; compatible = arm,cortex-a15; reg = 0x0; + clock-frequency = 16; Reviewed-by: Tarek Dakhrant.dakh...@samsung.com -- Best regards, Tarek Dakhran -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v11 0/3] Exynos 5410 support
Hi all, On Fri, May 30, 2014 at 10:16 PM, Sachin Kamat wrote: > > > On Friday, 30 May 2014, Tushar Behera wrote: >> >> On Thu, May 29, 2014 at 11:30 PM, Andreas Färber wrote: >> > Hi Tarek, >> > >> > >> > And I reproducibly get failures for CPUs 1-3, resulting in only one CPU >> > in /proc/cpuinfo (compared to 4 on downstream 3.14): >> > >> > [0.045778] CPU: Testing write buffer coherency: ok >> > [0.045968] /cpus/cpu@0 missing clock-frequency property >> > [0.045993] /cpus/cpu@1 missing clock-frequency property >> > [0.046016] /cpus/cpu@2 missing clock-frequency property >> > [0.046040] /cpus/cpu@3 missing clock-frequency property >> > [0.046059] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 >> > [0.046135] Setting up static identity map for 0x403a8920 - >> > 0x403a8978 >> > [2.075052] CPU1: failed to come online >> > [4.085095] CPU2: failed to come online >> > [6.095142] CPU3: failed to come online >> > [6.095237] Brought up 1 CPUs >> > [6.095269] SMP: Total of 1 processors activated. >> > [6.095303] CPU: All CPU(s) started in HYP mode. >> > [6.095336] CPU: Virtualization extensions available. >> > >> > I also notice another apparent device tree issue: >> > >> > [7.341814] of_get_named_gpiod_flags: can't parse gpios property of >> > node '/soc/mmc@1222/slot@0[0]' >> > [7.341850] of_get_named_gpiod_flags: can't parse gpios property of >> > node '/soc/mmc@1222/slot@0[0]' >> > >> > Are any of those known issues and being worked on? >> > (The CPU failures affected 5420 Arndale Octa as well iirc.) >> > [snip] >> >> [1] http://www.spinics.net/lists/linux-samsung-soc/msg31776.html >> >> [PATCH v2 Resend 1/2] ARM: EXYNOS: Update secondary boot addr for secure >> mode >> >> [2] http://www.spinics.net/lists/linux-samsung-soc/msg31777.html >> >> [PATCH v2 Resend 2/2] ARM: dts: Add secure firmware support for >> Arndale-octa >> >> >> Kukjin, > > Can you please apply the above patches? > Patches [1], [2] tested on ODROID-XU, SMDK5410 and Arndale Octa boards. Tested-by: Tarek Dakhran Best regards, Tarek -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v11 0/3] Exynos 5410 support
Hi, On Fri, May 30, 2014 at 7:41 AM, Tushar Behera wrote: > On Thu, May 29, 2014 at 11:30 PM, Andreas Färber wrote: >> Hi Tarek, >> >> >> And I reproducibly get failures for CPUs 1-3, resulting in only one CPU >> in /proc/cpuinfo (compared to 4 on downstream 3.14): >> >> [0.045778] CPU: Testing write buffer coherency: ok >> [0.045968] /cpus/cpu@0 missing clock-frequency property >> [0.045993] /cpus/cpu@1 missing clock-frequency property >> [0.046016] /cpus/cpu@2 missing clock-frequency property >> [0.046040] /cpus/cpu@3 missing clock-frequency property >> [0.046059] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 >> [0.046135] Setting up static identity map for 0x403a8920 - 0x403a8978 >> [2.075052] CPU1: failed to come online >> [4.085095] CPU2: failed to come online >> [6.095142] CPU3: failed to come online >> [6.095237] Brought up 1 CPUs >> [6.095269] SMP: Total of 1 processors activated. >> [6.095303] CPU: All CPU(s) started in HYP mode. >> [6.095336] CPU: Virtualization extensions available. >> >> I also notice another apparent device tree issue: >> >> [7.341814] of_get_named_gpiod_flags: can't parse gpios property of >> node '/soc/mmc@1222/slot@0[0]' >> [7.341850] of_get_named_gpiod_flags: can't parse gpios property of >> node '/soc/mmc@1222/slot@0[0]' >> >> Are any of those known issues and being worked on? >> (The CPU failures affected 5420 Arndale Octa as well iirc.) >> > > Can you check after applying following two patches for Arndale-Octa > ([1],[2])? In other words, a patch similar to [2] might be required > for this board too if it is booting under secure mode. Firmware node already present into exynos5410-smdk5410.dts So with only patch[1] 4xA15 cores will boot on ODROID-XU and SMDK5410. > > [1] http://www.spinics.net/lists/linux-samsung-soc/msg31776.html > > [PATCH v2 Resend 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode > > [2] http://www.spinics.net/lists/linux-samsung-soc/msg31777.html > > [PATCH v2 Resend 2/2] ARM: dts: Add secure firmware support for Arndale-octa > > > -- > Tushar Behera Best regards, Tarek -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v11 0/3] Exynos 5410 support
Hi, On Fri, May 30, 2014 at 7:41 AM, Tushar Behera trbli...@gmail.com wrote: On Thu, May 29, 2014 at 11:30 PM, Andreas Färber afaer...@suse.de wrote: Hi Tarek, And I reproducibly get failures for CPUs 1-3, resulting in only one CPU in /proc/cpuinfo (compared to 4 on downstream 3.14): [0.045778] CPU: Testing write buffer coherency: ok [0.045968] /cpus/cpu@0 missing clock-frequency property [0.045993] /cpus/cpu@1 missing clock-frequency property [0.046016] /cpus/cpu@2 missing clock-frequency property [0.046040] /cpus/cpu@3 missing clock-frequency property [0.046059] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 [0.046135] Setting up static identity map for 0x403a8920 - 0x403a8978 [2.075052] CPU1: failed to come online [4.085095] CPU2: failed to come online [6.095142] CPU3: failed to come online [6.095237] Brought up 1 CPUs [6.095269] SMP: Total of 1 processors activated. [6.095303] CPU: All CPU(s) started in HYP mode. [6.095336] CPU: Virtualization extensions available. I also notice another apparent device tree issue: [7.341814] of_get_named_gpiod_flags: can't parse gpios property of node '/soc/mmc@1222/slot@0[0]' [7.341850] of_get_named_gpiod_flags: can't parse gpios property of node '/soc/mmc@1222/slot@0[0]' Are any of those known issues and being worked on? (The CPU failures affected 5420 Arndale Octa as well iirc.) Can you check after applying following two patches for Arndale-Octa ([1],[2])? In other words, a patch similar to [2] might be required for this board too if it is booting under secure mode. Firmware node already present into exynos5410-smdk5410.dts So with only patch[1] 4xA15 cores will boot on ODROID-XU and SMDK5410. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31776.html [PATCH v2 Resend 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode [2] http://www.spinics.net/lists/linux-samsung-soc/msg31777.html [PATCH v2 Resend 2/2] ARM: dts: Add secure firmware support for Arndale-octa -- Tushar Behera Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v11 0/3] Exynos 5410 support
Hi all, On Fri, May 30, 2014 at 10:16 PM, Sachin Kamat sachin.ka...@linaro.org wrote: On Friday, 30 May 2014, Tushar Behera trbli...@gmail.com wrote: On Thu, May 29, 2014 at 11:30 PM, Andreas Färber afaer...@suse.de wrote: Hi Tarek, And I reproducibly get failures for CPUs 1-3, resulting in only one CPU in /proc/cpuinfo (compared to 4 on downstream 3.14): [0.045778] CPU: Testing write buffer coherency: ok [0.045968] /cpus/cpu@0 missing clock-frequency property [0.045993] /cpus/cpu@1 missing clock-frequency property [0.046016] /cpus/cpu@2 missing clock-frequency property [0.046040] /cpus/cpu@3 missing clock-frequency property [0.046059] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 [0.046135] Setting up static identity map for 0x403a8920 - 0x403a8978 [2.075052] CPU1: failed to come online [4.085095] CPU2: failed to come online [6.095142] CPU3: failed to come online [6.095237] Brought up 1 CPUs [6.095269] SMP: Total of 1 processors activated. [6.095303] CPU: All CPU(s) started in HYP mode. [6.095336] CPU: Virtualization extensions available. I also notice another apparent device tree issue: [7.341814] of_get_named_gpiod_flags: can't parse gpios property of node '/soc/mmc@1222/slot@0[0]' [7.341850] of_get_named_gpiod_flags: can't parse gpios property of node '/soc/mmc@1222/slot@0[0]' Are any of those known issues and being worked on? (The CPU failures affected 5420 Arndale Octa as well iirc.) [snip] [1] http://www.spinics.net/lists/linux-samsung-soc/msg31776.html [PATCH v2 Resend 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode [2] http://www.spinics.net/lists/linux-samsung-soc/msg31777.html [PATCH v2 Resend 2/2] ARM: dts: Add secure firmware support for Arndale-octa Kukjin, Can you please apply the above patches? Patches [1], [2] tested on ODROID-XU, SMDK5410 and Arndale Octa boards. Tested-by: Tarek Dakhran t.dakh...@samsung.com Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v11 0/3] Exynos 5410 support
Hi Andreas, On 05/29/2014 05:36 PM, Andreas Färber wrote: Hi Tarek and Kevin, Am 27.05.2014 19:06, schrieb Kevin Hilman: Tarek Dakhran writes: The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: 97eae6c Merge branch 'v3.16-next/multiplatform' into for-next) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Exynos 5410 reference board (multi_v7_defconfig) 3) Odroid-XU board (exynos_defconfig) 4) Odroid-XU board (multi_v7_defconfig) Tested-by: Kevin Hilman FYI, I boot tested this on an odroid-xu (exynos_defconfig and multi_v7_defconfig.) Could you clarify: Are you using exynos5410-smdk5410.dts with the ODROID-XU or do you have some upcoming exynos5410-odroidxu.dts based on exynos5410.dtsi? We use exynos5410-smdk5410.dts for booting ODROID-XU. Thanks, Andreas -- Best regards, Tarek Dakhran -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v11 0/3] Exynos 5410 support
Hi Andreas, On 05/29/2014 05:36 PM, Andreas Färber wrote: Hi Tarek and Kevin, Am 27.05.2014 19:06, schrieb Kevin Hilman: Tarek Dakhran t.dakh...@samsung.com writes: The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: 97eae6c Merge branch 'v3.16-next/multiplatform' into for-next) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Exynos 5410 reference board (multi_v7_defconfig) 3) Odroid-XU board (exynos_defconfig) 4) Odroid-XU board (multi_v7_defconfig) Tested-by: Kevin Hilman khil...@linaro.org FYI, I boot tested this on an odroid-xu (exynos_defconfig and multi_v7_defconfig.) Could you clarify: Are you using exynos5410-smdk5410.dts with the ODROID-XU or do you have some upcoming exynos5410-odroidxu.dts based on exynos5410.dtsi? We use exynos5410-smdk5410.dts for booting ODROID-XU. Thanks, Andreas -- Best regards, Tarek Dakhran -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v11 2/3] clk: exynos5410: register clocks using common clock framework
Hi Mike,
On Wed, May 28, 2014 at 4:41 AM, Mike Turquette wrote:
> Quoting Tarek Dakhran (2014-05-25 20:23:32)
>> The EXYNOS5410 clocks are statically listed and registered
>> using the Samsung specific common clock helper functions.
>>
>> Signed-off-by: Tarek Dakhran
>> Signed-off-by: Vyacheslav Tyrtov
>> ---
>> .../devicetree/bindings/clock/exynos5410-clock.txt | 45 +
>> drivers/clk/samsung/Makefile |1 +
>> drivers/clk/samsung/clk-exynos5410.c | 209
>>
>> include/dt-bindings/clock/exynos5410.h | 33
>> 4 files changed, 288 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> create mode 100644 drivers/clk/samsung/clk-exynos5410.c
>> create mode 100644 include/dt-bindings/clock/exynos5410.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> new file mode 100644
>> index 000..aeab635
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> @@ -0,0 +1,45 @@
>> +* Samsung Exynos5410 Clock Controller
>> +
>> +The Exynos5410 clock controller generates and supplies clock to various
>> +controllers within the Exynos5410 SoC.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "samsung,exynos5410-clock"
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> + region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +All available clocks are defined as preprocessor macros in
>> +dt-bindings/clock/exynos5410.h header and can be used in device
>> +tree sources.
>> +
>> +External clock:
>> +
>> +There is clock that is generated outside the SoC. It
>> +is expected that it is defined using standard clock bindings
>> +with following clock-output-name:
>> +
>> + - "fin_pll" - PLL input clock from XXTI
>
> Does fin_pll feed into the exynos5410-clock controller? If so, should
> the example clock-controller node below have a clocks and clock-names
> property?
fin_pll does not feed into exynos5410-clock controller, but into mct do.
> diff --git a/arch/arm/boot/dts/exynos5410.dtsi
> b/arch/arm/boot/dts/exynos5410.dtsi
> new file mode 100644
> index 000..3839c26
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5410.dtsi
> @@ -0,0 +1,206 @@
> +/*
> + * SAMSUNG EXYNOS5410 SoC device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
> + * EXYNOS5410 based board files can include this file and provide
> + * values for board specfic bindings.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "skeleton.dtsi"
> +#include
> +
> +/ {
> + compatible = "samsung,exynos5410", "samsung,exynos5";
> + interrupt-parent = <>;
[snip]
> + mct: mct@101C {
> + compatible = "samsung,exynos4210-mct";
> + reg = <0x101C 0xB00>;
> + interrupt-parent = <_map>;
> + interrupts = <0>, <1>, <2>, <3>,
> + <4>, <5>, <6>, <7>,
> + <8>, <9>, <10>, <11>;
> + clocks = <_pll>, < CLK_MCT>;
> + clock-names = "fin_pll", "mct";
> +
> + interrupt_map: interrupt-map {
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + #size-cells = <0>;
> + interrupt-map = <0 23 3>,
> + <1 23 4>,
> + <2 25 2>,
> + <3 25 3>,
> + <4 0 120 0>,
> + <5 0 121 0>,
> + <6 0 122 0>,
> + <7 0 123 0>,
> + <8 0 128 0>,
> + <9 0 129 0>,
> + <10 0 130 0>,
> + <11 0 131 0>;
> + };
> + };
> +
That's why I documented fin_pll. Should I add mct binding example to
documentation too?
Best regards,
Tarek
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Re: [PATCH v11 0/3] Exynos 5410 support
Hi, On Tue, May 27, 2014 at 9:44 PM, Kevin Hilman wrote: > Kevin Hilman writes: > >> Tarek Dakhran writes: >> >>> The series of patches represent support of Exynos 5410 SoC >>> >>> The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture >>> >>> Patches add new platform description, support of clock controller and device >>> tree for Exynos 5410. >>> >>> Has been build on Samsung Linux Kernel >>> (branch: for-next, commit: 97eae6c Merge branch >>> 'v3.16-next/multiplatform' into for-next) >>> >>> Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) >>> 2) Exynos 5410 reference board (multi_v7_defconfig) >>> 3) Odroid-XU board (exynos_defconfig) >>> 4) Odroid-XU board (multi_v7_defconfig) >> >> Tested-by: Kevin Hilman >> >> FYI, I boot tested this on an odroid-xu (exynos_defconfig and >> multi_v7_defconfig.) > > Oops, I may have spoke to soon. There seem to be some problems with > multi_v7_defconfig. > > Applying this series directly on the commit mentioned above and testing, > it works just fine using multi_v7_defconfig. Thank you for testing. > However, if I directly test the current contents of the samsung for-next > branch (where this series has been merged) it no longer boots on the > odroid-xu. > A quick diff shows that there are some other changes to > multi_v7_defconfig in the samsung/for-next branch that may be causing > problems here. Yes. Right you are. There is no ARCH_EXYNOS defined in multi_v7_defconfig at current state (branch: for-next commit: ca610da Merge branch 'v3.16-next/dt-samsung-3' into for-next). So booting kernel on 5410 SoC is not possible with multi_v7_defconfig. Please use exynos_defconfig. > > Kevin Best regards, Tarek -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v11 0/3] Exynos 5410 support
Hi, On Tue, May 27, 2014 at 9:44 PM, Kevin Hilman khil...@linaro.org wrote: Kevin Hilman khil...@linaro.org writes: Tarek Dakhran t.dakh...@samsung.com writes: The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: 97eae6c Merge branch 'v3.16-next/multiplatform' into for-next) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Exynos 5410 reference board (multi_v7_defconfig) 3) Odroid-XU board (exynos_defconfig) 4) Odroid-XU board (multi_v7_defconfig) Tested-by: Kevin Hilman khil...@linaro.org FYI, I boot tested this on an odroid-xu (exynos_defconfig and multi_v7_defconfig.) Oops, I may have spoke to soon. There seem to be some problems with multi_v7_defconfig. Applying this series directly on the commit mentioned above and testing, it works just fine using multi_v7_defconfig. Thank you for testing. However, if I directly test the current contents of the samsung for-next branch (where this series has been merged) it no longer boots on the odroid-xu. A quick diff shows that there are some other changes to multi_v7_defconfig in the samsung/for-next branch that may be causing problems here. Yes. Right you are. There is no ARCH_EXYNOS defined in multi_v7_defconfig at current state (branch: for-next commit: ca610da Merge branch 'v3.16-next/dt-samsung-3' into for-next). So booting kernel on 5410 SoC is not possible with multi_v7_defconfig. Please use exynos_defconfig. Kevin Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v11 2/3] clk: exynos5410: register clocks using common clock framework
Hi Mike,
On Wed, May 28, 2014 at 4:41 AM, Mike Turquette mturque...@linaro.org wrote:
Quoting Tarek Dakhran (2014-05-25 20:23:32)
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 45 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 209
include/dt-bindings/clock/exynos5410.h | 33
4 files changed, 288 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..aeab635
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,45 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It
+is expected that it is defined using standard clock bindings
+with following clock-output-name:
+
+ - fin_pll - PLL input clock from XXTI
Does fin_pll feed into the exynos5410-clock controller? If so, should
the example clock-controller node below have a clocks and clock-names
property?
fin_pll does not feed into exynos5410-clock controller, but into mct do.
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..3839c26
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,206 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include skeleton.dtsi
+#include dt-bindings/clock/exynos5410.h
+
+/ {
+ compatible = samsung,exynos5410, samsung,exynos5;
+ interrupt-parent = gic;
[snip]
+ mct: mct@101C {
+ compatible = samsung,exynos4210-mct;
+ reg = 0x101C 0xB00;
+ interrupt-parent = interrupt_map;
+ interrupts = 0, 1, 2, 3,
+ 4, 5, 6, 7,
+ 8, 9, 10, 11;
+ clocks = fin_pll, clock CLK_MCT;
+ clock-names = fin_pll, mct;
+
+ interrupt_map: interrupt-map {
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 combiner 23 3,
+ 1 combiner 23 4,
+ 2 combiner 25 2,
+ 3 combiner 25 3,
+ 4 gic 0 120 0,
+ 5 gic 0 121 0,
+ 6 gic 0 122 0,
+ 7 gic 0 123 0,
+ 8 gic 0 128 0,
+ 9 gic 0 129 0,
+ 10 gic 0 130 0,
+ 11 gic 0 131 0;
+ };
+ };
+
That's why I documented fin_pll. Should I add mct binding example to
documentation too?
Best regards,
Tarek
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[PATCH v11 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: Tarek Dakhran Signed-off-by: Vyacheslav Tyrtov --- arch/arm/mach-exynos/Kconfig |5 + arch/arm/mach-exynos/common.h | 12 ++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 15fa610..d58995c9 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -88,6 +88,11 @@ config SOC_EXYNOS5260 default y depends on ARCH_EXYNOS5 +config SOC_EXYNOS5410 + bool "SAMSUNG EXYNOS5410" + default y + depends on ARCH_EXYNOS5 + config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 9eb6258..80b90e3 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -24,6 +24,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE #define EXYNOS5250_SOC_ID 0x4352 +#define EXYNOS5410_SOC_ID 0xE541 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 #define EXYNOS5800_SOC_ID 0xE5422000 @@ -42,6 +43,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) @@ -80,6 +82,12 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5410) +# define soc_is_exynos5410() is_samsung_exynos5410() +#else +# define soc_is_exynos5410() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else @@ -100,8 +108,8 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420() || \ - soc_is_exynos5800()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ + soc_is_exynos5420() || soc_is_exynos5800()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v11 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 45 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 209
include/dt-bindings/clock/exynos5410.h | 33
4 files changed, 288 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..aeab635
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,45 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It
+is expected that it is defined using standard clock bindings
+with following clock-output-name:
+
+ - "fin_pll" - PLL input clock from XXTI
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 25646c6..69e8177 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_EXYNOS3250)+= clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..c9505ab
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX
[PATCH v11 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: 97eae6c Merge branch 'v3.16-next/multiplatform' into for-next) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Exynos 5410 reference board (multi_v7_defconfig) 3) Odroid-XU board (exynos_defconfig) 4) Odroid-XU board (multi_v7_defconfig) I hope this is clean and would be applied. Tarek. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 45 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 82 arch/arm/boot/dts/exynos5410.dtsi | 206 +++ arch/arm/mach-exynos/Kconfig |5 + arch/arm/mach-exynos/common.h | 12 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 209 include/dt-bindings/clock/exynos5410.h | 33 9 files changed, 592 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v11 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 82
arch/arm/boot/dts/exynos5410.dtsi | 206 +
3 files changed, 289 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cd399a2..709f862 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5260-xyref5260.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7275bbd
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,82 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410",
"samsung,exynos5";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ fin_pll: xxti {
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+
+ firmware@02037000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x02037000 0x1000>;
+ };
+
+};
+
+_0 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+};
+
+_2 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..3839c26
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,206 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include
+
+/ {
+ compatible = "samsung,exynos5410", "samsung,exynos5";
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x2>;
+
[PATCH v11 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 82
arch/arm/boot/dts/exynos5410.dtsi | 206 +
3 files changed, 289 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cd399a2..709f862 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5260-xyref5260.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7275bbd
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,82 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410,
samsung,exynos5;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ firmware@02037000 {
+ compatible = samsung,secure-firmware;
+ reg = 0x02037000 0x1000;
+ };
+
+};
+
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+};
+
+uart0 {
+ status = okay;
+};
+
+uart1 {
+ status = okay;
+};
+
+uart2 {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..3839c26
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,206 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include skeleton.dtsi
+#include dt-bindings/clock/exynos5410.h
+
+/ {
+ compatible = samsung,exynos5410, samsung,exynos5;
+ interrupt-parent = gic;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x0;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x1;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x2;
+ };
+
+ CPU3: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x3;
+ };
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1
[PATCH v11 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 45 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 209
include/dt-bindings/clock/exynos5410.h | 33
4 files changed, 288 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..aeab635
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,45 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It
+is expected that it is defined using standard clock bindings
+with following clock-output-name:
+
+ - fin_pll - PLL input clock from XXTI
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 25646c6..69e8177 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_EXYNOS3250)+= clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..c9505ab
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define
[PATCH v11 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: 97eae6c Merge branch 'v3.16-next/multiplatform' into for-next) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Exynos 5410 reference board (multi_v7_defconfig) 3) Odroid-XU board (exynos_defconfig) 4) Odroid-XU board (multi_v7_defconfig) I hope this is clean and would be applied. Tarek. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 45 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 82 arch/arm/boot/dts/exynos5410.dtsi | 206 +++ arch/arm/mach-exynos/Kconfig |5 + arch/arm/mach-exynos/common.h | 12 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 209 include/dt-bindings/clock/exynos5410.h | 33 9 files changed, 592 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v11 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com --- arch/arm/mach-exynos/Kconfig |5 + arch/arm/mach-exynos/common.h | 12 ++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 15fa610..d58995c9 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -88,6 +88,11 @@ config SOC_EXYNOS5260 default y depends on ARCH_EXYNOS5 +config SOC_EXYNOS5410 + bool SAMSUNG EXYNOS5410 + default y + depends on ARCH_EXYNOS5 + config SOC_EXYNOS5420 bool SAMSUNG EXYNOS5420 default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 9eb6258..80b90e3 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -24,6 +24,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE #define EXYNOS5250_SOC_ID 0x4352 +#define EXYNOS5410_SOC_ID 0xE541 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 #define EXYNOS5800_SOC_ID 0xE5422000 @@ -42,6 +43,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) @@ -80,6 +82,12 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5410) +# define soc_is_exynos5410() is_samsung_exynos5410() +#else +# define soc_is_exynos5410() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else @@ -100,8 +108,8 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420() || \ - soc_is_exynos5800()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ + soc_is_exynos5420() || soc_is_exynos5800()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
Hi Tomasz I faced another problem, while changing this patch. See below. On 05/24/2014 01:11 AM, Tomasz Figa wrote: Hi Tarek, With v2 of the series I mentioned in review of previous version [1], this patch can be skipped. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html Best regards, Tomasz On 23.05.2014 12:35, Tarek Dakhran wrote: EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: Tarek Dakhran Signed-off-by: Vyacheslav Tyrtov --- arch/arm/mach-exynos/Kconfig|8 arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/firmware.c |2 +- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 1602abc..79a3e85 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -84,6 +84,14 @@ config SOC_EXYNOS5250 help Enable EXYNOS5250 SoC support +config SOC_EXYNOS5410 + bool "SAMSUNG EXYNOS5410" + default y + depends on ARCH_EXYNOS5 + select PM_GENERIC_DOMAINS if PM_RUNTIME + help + Enable EXYNOS5410 SoC support + config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index e2d0954..d64c6de 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -21,6 +21,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE #define EXYNOS5250_SOC_ID 0x4352 +#define EXYNOS5410_SOC_ID 0xE541 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 #define EXYNOS5_SOC_MASK 0xF000 @@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5410) +# define soc_is_exynos5410() is_samsung_exynos5410() +#else +# define soc_is_exynos5410() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else @@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ + soc_is_exynos5420()) This is the place where we need it. Or this macro should be changed (maybe read compatible property from dt). -- Best regards, Tarek Dakhran -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
Hi Tomasz I faced another problem, while changing this patch. See below. On 05/24/2014 01:11 AM, Tomasz Figa wrote: Hi Tarek, With v2 of the series I mentioned in review of previous version [1], this patch can be skipped. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html Best regards, Tomasz On 23.05.2014 12:35, Tarek Dakhran wrote: EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com --- arch/arm/mach-exynos/Kconfig|8 arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/firmware.c |2 +- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 1602abc..79a3e85 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -84,6 +84,14 @@ config SOC_EXYNOS5250 help Enable EXYNOS5250 SoC support +config SOC_EXYNOS5410 + bool SAMSUNG EXYNOS5410 + default y + depends on ARCH_EXYNOS5 + select PM_GENERIC_DOMAINS if PM_RUNTIME + help + Enable EXYNOS5410 SoC support + config SOC_EXYNOS5420 bool SAMSUNG EXYNOS5420 default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index e2d0954..d64c6de 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -21,6 +21,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE #define EXYNOS5250_SOC_ID 0x4352 +#define EXYNOS5410_SOC_ID 0xE541 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 #define EXYNOS5_SOC_MASK 0xF000 @@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5410) +# define soc_is_exynos5410() is_samsung_exynos5410() +#else +# define soc_is_exynos5410() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else @@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ + soc_is_exynos5420()) This is the place where we need it. Or this macro should be changed (maybe read compatible property from dt). -- Best regards, Tarek Dakhran -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework
This is just my inattention. Will be corrected until Monday. On Sat, May 24, 2014 at 1:19 AM, Tomasz Figa wrote: > Hi Tarek, > > Thanks for keeping up with addressing my comments. See below. > > On 23.05.2014 12:35, Tarek Dakhran wrote: >> The EXYNOS5410 clocks are statically listed and registered >> using the Samsung specific common clock helper functions. >> >> Signed-off-by: Tarek Dakhran >> Signed-off-by: Vyacheslav Tyrtov >> --- >> .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + >> drivers/clk/samsung/Makefile |1 + >> drivers/clk/samsung/clk-exynos5410.c | 209 >> >> include/dt-bindings/clock/exynos5410.h | 33 >> 4 files changed, 294 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/clock/exynos5410-clock.txt >> create mode 100644 drivers/clk/samsung/clk-exynos5410.c >> create mode 100644 include/dt-bindings/clock/exynos5410.h >> > > The driver itself looks good, but binding documentation seems to be > outdated. The part about external clocks, more specifically. > >> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt >> b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt >> new file mode 100644 >> index 000..82337c4 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt >> @@ -0,0 +1,51 @@ >> +* Samsung Exynos5410 Clock Controller >> + >> +The Exynos5410 clock controller generates and supplies clock to various >> +controllers within the Exynos5410 SoC. >> + >> +Required Properties: >> + >> +- compatible: should be "samsung,exynos5410-clock" >> + >> +- reg: physical base address of the controller and length of memory mapped >> + region. >> + >> +- #clock-cells: should be 1. >> + >> +All available clocks are defined as preprocessor macros in >> +dt-bindings/clock/exynos5410.h header and can be used in device >> +tree sources. >> + >> +External clock: >> +There is clock that is generated outside the SoC. It is expected >> +that it is defined using standard clock bindings with following >> + - compatible: should be "samsung,exynos5410-oscclk" > > ^ Best regards, Tarek -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
Sorry, only now catch it! I agree, this patch is not needed anymore, except Kconfig option. config SOC_EXYNOS5410 is needed to build clock stuff. What is your opinion, Tomasz? On Sat, May 24, 2014 at 2:44 AM, Tarek Dakhran wrote: > Hi Tomazs, > > On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa wrote: >> Hi Tarek, >> >> With v2 of the series I mentioned in review of previous version [1], >> this patch can be skipped. >> >> [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html >> >> Best regards, >> Tomasz >> >> On 23.05.2014 12:35, Tarek Dakhran wrote: > [snip] >>> diff --git a/arch/arm/mach-exynos/firmware.c >>> b/arch/arm/mach-exynos/firmware.c >>> index 739bdc8..971baf0 100644 >>> --- a/arch/arm/mach-exynos/firmware.c >>> +++ b/arch/arm/mach-exynos/firmware.c >>> @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned >>> long boot_addr) >>> >>> boot_reg = sysram_ns_base_addr + 0x1c; >>> >>> - if (!soc_is_exynos4212()) >>> + if (!soc_is_exynos4212() && !soc_is_exynos5410()) >>> boot_reg += 4*cpu; >>> >>> __raw_writel(boot_addr, boot_reg); >>> > > I need to define SoC type to set correct bootreg in firmware, > otherwise only one cpu can be booted. > So, this stuff is needed. > > Best regards, > Tarek -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
Hi Tomazs, On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa wrote: > Hi Tarek, > > With v2 of the series I mentioned in review of previous version [1], > this patch can be skipped. > > [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html > > Best regards, > Tomasz > > On 23.05.2014 12:35, Tarek Dakhran wrote: [snip] >> diff --git a/arch/arm/mach-exynos/firmware.c >> b/arch/arm/mach-exynos/firmware.c >> index 739bdc8..971baf0 100644 >> --- a/arch/arm/mach-exynos/firmware.c >> +++ b/arch/arm/mach-exynos/firmware.c >> @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long >> boot_addr) >> >> boot_reg = sysram_ns_base_addr + 0x1c; >> >> - if (!soc_is_exynos4212()) >> + if (!soc_is_exynos4212() && !soc_is_exynos5410()) >> boot_reg += 4*cpu; >> >> __raw_writel(boot_addr, boot_reg); >> I need to define SoC type to set correct bootreg in firmware, otherwise only one cpu can be booted. So, this stuff is needed. Best regards, Tarek -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v10 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: 19307a0 Merge branch 'v3.16-next/dt-samsung-2' into for-next) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Odroid-XU board (exynos_defconfig) Many thanks for reviewing to Tomasz Figa. Tarek. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 82 arch/arm/boot/dts/exynos5410.dtsi | 206 +++ arch/arm/mach-exynos/Kconfig |8 + arch/arm/mach-exynos/common.h | 11 +- arch/arm/mach-exynos/firmware.c|2 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 209 include/dt-bindings/clock/exynos5410.h | 33 10 files changed, 602 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: Tarek Dakhran Signed-off-by: Vyacheslav Tyrtov --- arch/arm/mach-exynos/Kconfig|8 arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/firmware.c |2 +- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 1602abc..79a3e85 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -84,6 +84,14 @@ config SOC_EXYNOS5250 help Enable EXYNOS5250 SoC support +config SOC_EXYNOS5410 + bool "SAMSUNG EXYNOS5410" + default y + depends on ARCH_EXYNOS5 + select PM_GENERIC_DOMAINS if PM_RUNTIME + help + Enable EXYNOS5410 SoC support + config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index e2d0954..d64c6de 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -21,6 +21,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE #define EXYNOS5250_SOC_ID 0x4352 +#define EXYNOS5410_SOC_ID 0xE541 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 #define EXYNOS5_SOC_MASK 0xF000 @@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5410) +# define soc_is_exynos5410() is_samsung_exynos5410() +#else +# define soc_is_exynos5410() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else @@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ + soc_is_exynos5420()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..971baf0 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() && !soc_is_exynos5410()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 51 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 209
include/dt-bindings/clock/exynos5410.h | 33
4 files changed, 294 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..82337c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,51 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+ - compatible: should be "samsung,exynos5410-oscclk"
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: Required external clock.
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5410-oscclk";
+ clock-frequency = <2400>;
+ };
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 25646c6..69e8177 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_EXYNOS3250)+= clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..c9505ab
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_M
[PATCH v10 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 82
arch/arm/boot/dts/exynos5410.dtsi | 206 +
3 files changed, 289 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cd399a2..709f862 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5260-xyref5260.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7275bbd
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,82 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410",
"samsung,exynos5";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ fin_pll: xxti {
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+
+ firmware@02037000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x02037000 0x1000>;
+ };
+
+};
+
+_0 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+};
+
+_2 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..3839c26
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,206 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include
+
+/ {
+ compatible = "samsung,exynos5410", "samsung,exynos5";
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x2>;
+ };
+
+
[PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 51 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 209
include/dt-bindings/clock/exynos5410.h | 33
4 files changed, 294 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..82337c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,51 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+ - compatible: should be samsung,exynos5410-oscclk
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: Required external clock.
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5410-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 25646c6..69e8177 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_EXYNOS3250)+= clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..c9505ab
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
[PATCH v10 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 82
arch/arm/boot/dts/exynos5410.dtsi | 206 +
3 files changed, 289 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cd399a2..709f862 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5260-xyref5260.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7275bbd
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,82 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410,
samsung,exynos5;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ firmware@02037000 {
+ compatible = samsung,secure-firmware;
+ reg = 0x02037000 0x1000;
+ };
+
+};
+
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+};
+
+uart0 {
+ status = okay;
+};
+
+uart1 {
+ status = okay;
+};
+
+uart2 {
+ status = okay;
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..3839c26
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,206 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include skeleton.dtsi
+#include dt-bindings/clock/exynos5410.h
+
+/ {
+ compatible = samsung,exynos5410, samsung,exynos5;
+ interrupt-parent = gic;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x0;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x1;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x2;
+ };
+
+ CPU3: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x3;
+ };
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ combiner: interrupt
[PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com --- arch/arm/mach-exynos/Kconfig|8 arch/arm/mach-exynos/common.h | 11 ++- arch/arm/mach-exynos/firmware.c |2 +- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 1602abc..79a3e85 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -84,6 +84,14 @@ config SOC_EXYNOS5250 help Enable EXYNOS5250 SoC support +config SOC_EXYNOS5410 + bool SAMSUNG EXYNOS5410 + default y + depends on ARCH_EXYNOS5 + select PM_GENERIC_DOMAINS if PM_RUNTIME + help + Enable EXYNOS5410 SoC support + config SOC_EXYNOS5420 bool SAMSUNG EXYNOS5420 default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index e2d0954..d64c6de 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -21,6 +21,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE #define EXYNOS5250_SOC_ID 0x4352 +#define EXYNOS5410_SOC_ID 0xE541 #define EXYNOS5420_SOC_ID 0xE542 #define EXYNOS5440_SOC_ID 0xE544 #define EXYNOS5_SOC_MASK 0xF000 @@ -37,6 +38,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5410) +# define soc_is_exynos5410() is_samsung_exynos5410() +#else +# define soc_is_exynos5410() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else @@ -82,7 +90,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ + soc_is_exynos5420()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..971baf0 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() !soc_is_exynos5410()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v10 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: 19307a0 Merge branch 'v3.16-next/dt-samsung-2' into for-next) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Odroid-XU board (exynos_defconfig) Many thanks for reviewing to Tomasz Figa. Tarek. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 82 arch/arm/boot/dts/exynos5410.dtsi | 206 +++ arch/arm/mach-exynos/Kconfig |8 + arch/arm/mach-exynos/common.h | 11 +- arch/arm/mach-exynos/firmware.c|2 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 209 include/dt-bindings/clock/exynos5410.h | 33 10 files changed, 602 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
Hi Tomazs, On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Tarek, With v2 of the series I mentioned in review of previous version [1], this patch can be skipped. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html Best regards, Tomasz On 23.05.2014 12:35, Tarek Dakhran wrote: [snip] diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..971baf0 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() !soc_is_exynos5410()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); I need to define SoC type to set correct bootreg in firmware, otherwise only one cpu can be booted. So, this stuff is needed. Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v10 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
Sorry, only now catch it! I agree, this patch is not needed anymore, except Kconfig option. config SOC_EXYNOS5410 is needed to build clock stuff. What is your opinion, Tomasz? On Sat, May 24, 2014 at 2:44 AM, Tarek Dakhran t.dakh...@gmail.com wrote: Hi Tomazs, On Sat, May 24, 2014 at 1:11 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Tarek, With v2 of the series I mentioned in review of previous version [1], this patch can be skipped. [1] http://www.spinics.net/lists/linux-samsung-soc/msg31258.html Best regards, Tomasz On 23.05.2014 12:35, Tarek Dakhran wrote: [snip] diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..971baf0 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,7 +50,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() !soc_is_exynos5410()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); I need to define SoC type to set correct bootreg in firmware, otherwise only one cpu can be booted. So, this stuff is needed. Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v10 2/3] clk: exynos5410: register clocks using common clock framework
This is just my inattention. Will be corrected until Monday. On Sat, May 24, 2014 at 1:19 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Tarek, Thanks for keeping up with addressing my comments. See below. On 23.05.2014 12:35, Tarek Dakhran wrote: The EXYNOS5410 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com --- .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 209 include/dt-bindings/clock/exynos5410.h | 33 4 files changed, 294 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h The driver itself looks good, but binding documentation seems to be outdated. The part about external clocks, more specifically. diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt new file mode 100644 index 000..82337c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt @@ -0,0 +1,51 @@ +* Samsung Exynos5410 Clock Controller + +The Exynos5410 clock controller generates and supplies clock to various +controllers within the Exynos5410 SoC. + +Required Properties: + +- compatible: should be samsung,exynos5410-clock + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5410.h header and can be used in device +tree sources. + +External clock: +There is clock that is generated outside the SoC. It is expected +that it is defined using standard clock bindings with following + - compatible: should be samsung,exynos5410-oscclk ^ Best regards, Tarek -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/Kconfig |8
arch/arm/mach-exynos/exynos.c|1 +
arch/arm/mach-exynos/platsmp.c |4
arch/arm/plat-samsung/include/plat/cpu.h | 11 ++-
4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 1602abc..79a3e85 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,14 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index e973ff5..12db6cf 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -312,6 +312,7 @@ static char const *exynos_dt_compat[] __initconst = {
"samsung,exynos4412",
"samsung,exynos5",
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 78002c7..a95213d 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -60,6 +60,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return sysram_ns_base_addr;
return sysram_base_addr;
}
@@ -72,6 +74,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
return ERR_PTR(-ENODEV);
if (soc_is_exynos4412())
boot_reg += 4*cpu;
+ else if (soc_is_exynos5410())
+ boot_reg += (0x1c);
else if (soc_is_exynos5420())
boot_reg += 4;
return boot_reg;
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8d..21db380 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -49,6 +49,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE541
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -72,6 +73,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
@@ -154,6 +156,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
EXYNOS5_SOC_MASK)
# define soc_is_exynos5250() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5410)
+# define soc_is_exynos5410() is_samsung_exynos5410()
+#else
+# define soc_is_exynos5410() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
@@ -168,7 +176,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
EXYNOS5_SOC_MASK)
#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
soc_is_exynos4412())
-#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
+#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
+ soc_is_exynos5420())
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x,
__phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
--
1.7.9.5
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Acked-by: Tomasz Figa
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 51 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 223
include/dt-bindings/clock/exynos5410.h | 33 +++
4 files changed, 308 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..82337c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,51 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+ - compatible: should be "samsung,exynos5410-oscclk"
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: Required external clock.
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5410-oscclk";
+ clock-frequency = <2400>;
+ };
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..7fdc17a
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_M
[PATCH v9 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65
arch/arm/boot/dts/exynos5410.dtsi | 158 +
3 files changed, 224 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3220e29..2fcde9a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..d69e152
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5410-oscclk";
+ clock-frequency = <2400>;
+ };
+ };
+
+ mmc@1220 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..e134afc
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,158 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410", "samsung,exynos5";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <16>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <16>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ clock-frequency = <
[PATCH v9 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: ccf5511 ARM: EXYNOS: Add MCPM call-back functions) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Odroid-XU board (exynos_defconfig) Tarek. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++ arch/arm/boot/dts/exynos5410.dtsi | 158 ++ arch/arm/mach-exynos/Kconfig |8 + arch/arm/mach-exynos/exynos.c |1 + arch/arm/mach-exynos/platsmp.c |4 + arch/arm/plat-samsung/include/plat/cpu.h | 11 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 223 include/dt-bindings/clock/exynos5410.h | 33 +++ 11 files changed, 555 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Samsung Linux Kernel (branch: for-next, commit: ccf5511 ARM: EXYNOS: Add MCPM call-back functions) Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Odroid-XU board (exynos_defconfig) Tarek. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++ arch/arm/boot/dts/exynos5410.dtsi | 158 ++ arch/arm/mach-exynos/Kconfig |8 + arch/arm/mach-exynos/exynos.c |1 + arch/arm/mach-exynos/platsmp.c |4 + arch/arm/plat-samsung/include/plat/cpu.h | 11 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 223 include/dt-bindings/clock/exynos5410.h | 33 +++ 11 files changed, 555 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65
arch/arm/boot/dts/exynos5410.dtsi | 158 +
3 files changed, 224 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3220e29..2fcde9a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..d69e152
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5410-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..e134afc
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,158 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos5410.h
+#include exynos5.dtsi
+/ {
+ compatible = samsung,exynos5410, samsung,exynos5;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ clock-frequency = 16;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ clock-frequency = 16;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 2;
+ clock-frequency = 16;
+ };
+
+ CPU3: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 3;
+ clock-frequency = 16;
+ };
+ };
+
+ sysram@0202
[PATCH v9 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Acked-by: Tomasz Figa t.f...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 51 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 223
include/dt-bindings/clock/exynos5410.h | 33 +++
4 files changed, 308 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..82337c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,51 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+ - compatible: should be samsung,exynos5410-oscclk
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: Required external clock.
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5410-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..7fdc17a
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define
[PATCH v9 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/Kconfig |8
arch/arm/mach-exynos/exynos.c|1 +
arch/arm/mach-exynos/platsmp.c |4
arch/arm/plat-samsung/include/plat/cpu.h | 11 ++-
4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 1602abc..79a3e85 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,14 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool SAMSUNG EXYNOS5410
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index e973ff5..12db6cf 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -312,6 +312,7 @@ static char const *exynos_dt_compat[] __initconst = {
samsung,exynos4412,
samsung,exynos5,
samsung,exynos5250,
+ samsung,exynos5410,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 78002c7..a95213d 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -60,6 +60,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return sysram_ns_base_addr;
return sysram_base_addr;
}
@@ -72,6 +74,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
return ERR_PTR(-ENODEV);
if (soc_is_exynos4412())
boot_reg += 4*cpu;
+ else if (soc_is_exynos5410())
+ boot_reg += (0x1c);
else if (soc_is_exynos5420())
boot_reg += 4;
return boot_reg;
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8d..21db380 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -49,6 +49,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE541
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -72,6 +73,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
@@ -154,6 +156,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
EXYNOS5_SOC_MASK)
# define soc_is_exynos5250() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5410)
+# define soc_is_exynos5410() is_samsung_exynos5410()
+#else
+# define soc_is_exynos5410() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
@@ -168,7 +176,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
EXYNOS5_SOC_MASK)
#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
soc_is_exynos4412())
-#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
+#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
+ soc_is_exynos5420())
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x,
__phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
--
1.7.9.5
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Re: [PATCH v8 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Hi, Will be done in next version. Best regards, Tarek On Sat, Apr 26, 2014 at 3:41 PM, Tomasz Figa wrote: > Hi, > > Since I've started enforcing reference-based DT syntax due to multiple > advantages over the plain full-tree based one, you should do the same for > your dts/i files. You can take the series adding support for Exynos5260 as > an example: > > http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29360 > > Best regards, > Tomasz > > On 14.04.2014 09:17, Tarek Dakhran wrote: >> >> Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board. >> >> Signed-off-by: Tarek Dakhran >> Signed-off-by: Vyacheslav Tyrtov >> Reviewed-by: Tomasz Figa >> --- >> arch/arm/boot/dts/Makefile|1 + >> arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++ >> arch/arm/boot/dts/exynos5410.dtsi | 140 >> + >> 3 files changed, 206 insertions(+) >> create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts >> create mode 100644 arch/arm/boot/dts/exynos5410.dtsi >> > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Hi, Will be done in next version. Best regards, Tarek On Sat, Apr 26, 2014 at 3:41 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi, Since I've started enforcing reference-based DT syntax due to multiple advantages over the plain full-tree based one, you should do the same for your dts/i files. You can take the series adding support for Exynos5260 as an example: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29360 Best regards, Tomasz On 14.04.2014 09:17, Tarek Dakhran wrote: Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com Reviewed-by: Tomasz Figa t.f...@samsung.com --- arch/arm/boot/dts/Makefile|1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++ arch/arm/boot/dts/exynos5410.dtsi | 140 + 3 files changed, 206 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
On 04/14/2014 03:03 PM, Arnd Bergmann wrote:
On Monday 14 April 2014 11:17:38 Tarek Dakhran wrote:
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -159,6 +159,15 @@ static struct map_desc exynos5250_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5_iodesc[] __initdata = {
NAK
Why does this keep coming up?
Arnd
We need this memory region because boot address for exynos5410 located
here, same as for 5250.
--
Best regards,
Tarek Dakhran
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[PATCH v8 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++
arch/arm/boot/dts/exynos5410.dtsi | 140 +
3 files changed, 206 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35c146f..191dd19 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5420-arndale-octa.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..d69e152
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5410-oscclk";
+ clock-frequency = <2400>;
+ };
+ };
+
+ mmc@1220 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..e7cc930
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,140 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410", "samsung,exynos5";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <16>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <16>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ clock-frequency = <160
[PATCH v8 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Acked-by: Tomasz Figa
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 51 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 223
include/dt-bindings/clock/exynos5410.h | 33 +++
4 files changed, 308 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..82337c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,51 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+ - compatible: should be "samsung,exynos5410-oscclk"
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: Required external clock.
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5410-oscclk";
+ clock-frequency = <2400>;
+ };
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..7fdc17a
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_M
[PATCH v8 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/Kconfig |8
arch/arm/mach-exynos/exynos.c| 12
arch/arm/mach-exynos/hotplug.c |4 ++--
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/platsmp.c | 10 +++---
arch/arm/mach-exynos/regs-pmu.h |4 ++--
arch/arm/plat-samsung/include/plat/cpu.h | 11 ++-
7 files changed, 42 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18..92f2593 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,14 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b32a907..fdb3fb5 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -159,6 +159,15 @@ static struct map_desc exynos5250_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5_iodesc[] __initdata = {
{
.virtual= (unsigned long)S3C_VA_SYS,
@@ -294,6 +303,8 @@ static void __init exynos_map_io(void)
iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_io(void)
@@ -376,6 +387,7 @@ static char const *exynos_dt_compat[] __initconst = {
"samsung,exynos4412",
"samsung,exynos5",
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..83ae5fb 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -95,8 +95,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int
*spurious)
for (;;) {
/* make cpu1 to be turned off at next WFI command */
- if (cpu == 1)
- __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+ if (cpu > 0)
+ __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpu));
/*
* here's the WFI
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f..dce2841 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -37,6 +37,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return S5P_VA_SYSRAM_NS;
return S5P_VA_SYSRAM;
}
@@ -47,6 +49,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
boot_reg = cpu_boot_reg_base();
if (soc_is_exynos4412())
boot_reg += 4*cpu;
+ else if (soc_is_exynos5410())
+ boot_reg += (0x1c);
else if (soc_is_exynos5420())
boot_reg += 4;
return boot_reg;
@@ -107,14 +111,14 @@ static int exynos_boot_secondary(unsigned int cpu, struct
task_struct *idle)
*/
write_pen_release(phys_cpu);
- if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+ if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpu)) & S5P_CORE_LOCAL_PWR_EN)) {
[PATCH v8 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Linux Kernel v3.15-rc1 Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Odroid-XU board (exynos_defconfig) I hope, this will be commited to Linux v3.15... Tarek. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++ arch/arm/boot/dts/exynos5410.dtsi | 140 arch/arm/mach-exynos/Kconfig |8 + arch/arm/mach-exynos/exynos.c | 12 ++ arch/arm/mach-exynos/hotplug.c |4 +- arch/arm/mach-exynos/include/mach/map.h|1 + arch/arm/mach-exynos/platsmp.c | 10 +- arch/arm/mach-exynos/regs-pmu.h|4 +- arch/arm/plat-samsung/include/plat/cpu.h | 11 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 223 include/dt-bindings/clock/exynos5410.h | 33 +++ 14 files changed, 556 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/Kconfig |8
arch/arm/mach-exynos/exynos.c| 12
arch/arm/mach-exynos/hotplug.c |4 ++--
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/platsmp.c | 10 +++---
arch/arm/mach-exynos/regs-pmu.h |4 ++--
arch/arm/plat-samsung/include/plat/cpu.h | 11 ++-
7 files changed, 42 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18..92f2593 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,14 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool SAMSUNG EXYNOS5410
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b32a907..fdb3fb5 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -159,6 +159,15 @@ static struct map_desc exynos5250_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5_iodesc[] __initdata = {
{
.virtual= (unsigned long)S3C_VA_SYS,
@@ -294,6 +303,8 @@ static void __init exynos_map_io(void)
iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_io(void)
@@ -376,6 +387,7 @@ static char const *exynos_dt_compat[] __initconst = {
samsung,exynos4412,
samsung,exynos5,
samsung,exynos5250,
+ samsung,exynos5410,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..83ae5fb 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -95,8 +95,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int
*spurious)
for (;;) {
/* make cpu1 to be turned off at next WFI command */
- if (cpu == 1)
- __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+ if (cpu 0)
+ __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpu));
/*
* here's the WFI
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f..dce2841 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -37,6 +37,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return S5P_VA_SYSRAM_NS;
return S5P_VA_SYSRAM;
}
@@ -47,6 +49,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
boot_reg = cpu_boot_reg_base();
if (soc_is_exynos4412())
boot_reg += 4*cpu;
+ else if (soc_is_exynos5410())
+ boot_reg += (0x1c);
else if (soc_is_exynos5420())
boot_reg += 4;
return boot_reg;
@@ -107,14 +111,14 @@ static int exynos_boot_secondary(unsigned int cpu, struct
task_struct *idle)
*/
write_pen_release(phys_cpu);
- if (!(__raw_readl(S5P_ARM_CORE1_STATUS) S5P_CORE_LOCAL_PWR_EN)) {
+ if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpu)) S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION
[PATCH v8 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Linux Kernel v3.15-rc1 Has been tested on: 1) Exynos 5410 reference board (exynos_defconfig) 2) Odroid-XU board (exynos_defconfig) I hope, this will be commited to Linux v3.15... Tarek. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++ arch/arm/boot/dts/exynos5410.dtsi | 140 arch/arm/mach-exynos/Kconfig |8 + arch/arm/mach-exynos/exynos.c | 12 ++ arch/arm/mach-exynos/hotplug.c |4 +- arch/arm/mach-exynos/include/mach/map.h|1 + arch/arm/mach-exynos/platsmp.c | 10 +- arch/arm/mach-exynos/regs-pmu.h|4 +- arch/arm/plat-samsung/include/plat/cpu.h | 11 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 223 include/dt-bindings/clock/exynos5410.h | 33 +++ 14 files changed, 556 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Acked-by: Tomasz Figa t.f...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 51 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 223
include/dt-bindings/clock/exynos5410.h | 33 +++
4 files changed, 308 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..82337c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,51 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+ - compatible: should be samsung,exynos5410-oscclk
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: Required external clock.
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5410-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..7fdc17a
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define
[PATCH v8 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++
arch/arm/boot/dts/exynos5410.dtsi | 140 +
3 files changed, 206 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35c146f..191dd19 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5420-arndale-octa.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..d69e152
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5410-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..e7cc930
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,140 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos5410.h
+#include exynos5.dtsi
+/ {
+ compatible = samsung,exynos5410, samsung,exynos5;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ clock-frequency = 16;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ clock-frequency = 16;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 2;
+ clock-frequency = 16;
+ };
+
+ CPU3: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 3;
+ clock-frequency = 16;
+ };
+ };
+
+ clock: clock-controller@1001
Re: [PATCH v8 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
On 04/14/2014 03:03 PM, Arnd Bergmann wrote:
On Monday 14 April 2014 11:17:38 Tarek Dakhran wrote:
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -159,6 +159,15 @@ static struct map_desc exynos5250_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5_iodesc[] __initdata = {
NAK
Why does this keep coming up?
Arnd
We need this memory region because boot address for exynos5410 located
here, same as for 5250.
--
Best regards,
Tarek Dakhran
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Linux Kernel v3.14-rc1 (Samsung kernel, for-next branch, commit aaeeda6f57833c7c0e16fef3d76205f36882c21b, "Merge branch 'v3.15-next/cleanup-samsung' into for-next") Has been tested on Exynos 5410 reference board (exynos_defconfig) I hope, this is enough clean and hasn't any dependencies to go through Samsung tree. Tarek. Changelog: v7: small changes for resolving conflicts related to changes in Samsung tree. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 54 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++ arch/arm/boot/dts/exynos5410.dtsi | 140 + arch/arm/mach-exynos/Kconfig | 10 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/include/mach/map.h|1 + arch/arm/mach-exynos/mach-exynos5-dt.c |1 + arch/arm/mach-exynos/platsmp.c |2 + arch/arm/plat-samsung/include/plat/cpu.h |8 + arch/arm/plat-samsung/include/plat/map-s5p.h |3 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 208 include/dt-bindings/clock/exynos5410.h | 32 +++ 14 files changed, 551 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/Kconfig | 10 ++
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
arch/arm/mach-exynos/platsmp.c |2 ++
arch/arm/plat-samsung/include/plat/cpu.h |8
arch/arm/plat-samsung/include/plat/map-s5p.h |3 +++
7 files changed, 43 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c414af..97a06c3 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -91,6 +91,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 025fd82..5d53795 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -379,6 +395,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 37ea261..22245b2 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -51,6 +51,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..b681f89 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -39,6 +39,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return EXYNOS5410_BOOT_REG;
return S5P_VA_SYSRAM;
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/
[PATCH v7 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++
arch/arm/boot/dts/exynos5410.dtsi | 140 +
3 files changed, 213 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b..693dcdc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5420-arndale-octa.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+ };
+
+ mmc@1220 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..56b44d1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,140 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <16>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <16>;
+
[PATCH v7 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Acked-by: Tomasz Figa
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 208
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 295 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - "fin_pll" - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..adc4db6
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#defin
[PATCH v7 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Has been build on Linux Kernel v3.14-rc1 (Samsung kernel, for-next branch, commit aaeeda6f57833c7c0e16fef3d76205f36882c21b, Merge branch 'v3.15-next/cleanup-samsung' into for-next) Has been tested on Exynos 5410 reference board (exynos_defconfig) I hope, this is enough clean and hasn't any dependencies to go through Samsung tree. Tarek. Changelog: v7: small changes for resolving conflicts related to changes in Samsung tree. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 54 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++ arch/arm/boot/dts/exynos5410.dtsi | 140 + arch/arm/mach-exynos/Kconfig | 10 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/include/mach/map.h|1 + arch/arm/mach-exynos/mach-exynos5-dt.c |1 + arch/arm/mach-exynos/platsmp.c |2 + arch/arm/plat-samsung/include/plat/cpu.h |8 + arch/arm/plat-samsung/include/plat/map-s5p.h |3 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 208 include/dt-bindings/clock/exynos5410.h | 32 +++ 14 files changed, 551 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 10 ++
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
arch/arm/mach-exynos/platsmp.c |2 ++
arch/arm/plat-samsung/include/plat/cpu.h |8
arch/arm/plat-samsung/include/plat/map-s5p.h |3 +++
7 files changed, 43 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c414af..97a06c3 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -91,6 +91,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool SAMSUNG EXYNOS5410
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 025fd82..5d53795 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = EXYNOS4210;
static const char name_exynos4212[] = EXYNOS4212;
static const char name_exynos4412[] = EXYNOS4412;
static const char name_exynos5250[] = EXYNOS5250;
+static const char name_exynos5410[] = EXYNOS5410;
static const char name_exynos5420[] = EXYNOS5420;
static const char name_exynos5440[] = EXYNOS5440;
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -379,6 +395,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 37ea261..22245b2 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -51,6 +51,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
samsung,exynos5250,
+ samsung,exynos5410,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..b681f89 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -39,6 +39,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return EXYNOS5410_BOOT_REG;
return S5P_VA_SYSRAM;
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 31164b3..262ef86 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat
[PATCH v7 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++
arch/arm/boot/dts/exynos5410.dtsi | 140 +
3 files changed, 213 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b..693dcdc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5420-arndale-octa.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ fin_pll: clock-fin-pll {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ };
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..56b44d1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,140 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos5410.h
+#include exynos5.dtsi
+/ {
+ compatible = samsung,exynos5410;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ clock-frequency = 16;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ clock-frequency = 16;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 2;
+ clock-frequency = 16;
+ };
+
+ CPU3: cpu@3 {
+ device_type
[PATCH v7 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Acked-by: Tomasz Figa t.f...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 208
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 295 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - fin_pll - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..adc4db6
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
Re: [PATCH v1 0/2] exynos_mct driver: fix irq allocation and cleanup
On Thu, Feb 13, 2014 at 10:31 PM, Tarek Dakhran wrote: > Hi Tomasz, > > On Thursday, February 13, 2014, Tomasz Figa wrote: >> >> Hi Tarek, >> >> On 13.02.2014 04:08, Tarek Dakhran wrote: >>> >>> exynos4_local_timer_setup called on the secondary cpu before >>> irqs are enabled. request_irq can sleep, which produces next warning: >>> >>> on boot: >>> [0.37] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 >>> [0.37] Setting up static identity map for 0x403b5700 - 0x403b5758 >>> [0.395000] CPU1: Booted secondary processor >>> [0.395000] [ cut here ] >>> [0.395000] WARNING: CPU: 1 PID: 0 at kernel/locking/lockdep.c:2742 >>> lockdep_trace_alloc+0xe0/0xfc() >>> [0.395000] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags)) >>> [0.395000] Modules linked in: >>> [0.395000] CPU: 1 PID: 0 Comm: swapper/1 Not tainted >>> 3.14.0-rc2-4-g0db95f4 #128 >>> [0.395000] [] (unwind_backtrace) from [] >>> (show_stack+0x10/0x14) >>> [0.395000] [] (show_stack) from [] >>> (dump_stack+0x6c/0xb8) >>> [0.395000] [] (dump_stack) from [] >>> (warn_slowpath_common+0x68/0x8c) >>> [0.395000] [] (warn_slowpath_common) from [] >>> (warn_slowpath_fmt+0x30/0x40) >>> [0.395000] [] (warn_slowpath_fmt) from [] >>> (lockdep_trace_alloc+0xe0/0xfc) >>> [0.395000] [] (lockdep_trace_alloc) from [] >>> (kmem_cache_alloc+0x24/0x160) >>> [0.395000] [] (kmem_cache_alloc) from [] >>> (request_threaded_irq+0x64/0x130) >>> [0.395000] [] (request_threaded_irq) from [] >>> (exynos4_local_timer_setup+0xd0/0x124) >>> [0.395000] [] (exynos4_local_timer_setup) from [] >>> (exynos4_mct_cpu_notify+0x78/0xf0) >>> [0.395000] [] (exynos4_mct_cpu_notify) from [] >>> (notifier_call_chain+0x44/0x84) >>> [0.395000] [] (notifier_call_chain) from [] >>> (__cpu_notify+0x24/0x40) >>> [0.395000] [] (__cpu_notify) from [] >>> (secondary_start_kernel+0xe4/0x134) >>> [0.395000] [] (secondary_start_kernel) from [<40008624>] >>> (0x40008624) >>> [0.395000] ---[ end trace 347890460e745f50 ]--- >>> [0.42] CPU1: update cpu_power 1024 >>> [0.42] CPU1: thread -1, cpu 1, socket 0, mpidr 8001 >>> >>> on hotplug: >>> [ 108.04] CPU3: Booted secondary processor >>> [ 108.04] BUG: sleeping function called from invalid context at >>> mm/slub.c:965 >>> [ 108.04] in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: >>> swapper/3 >>> [ 108.04] INFO: lockdep is turned off. >>> [ 108.04] irq event stamp: 0 >>> [ 108.04] hardirqs last enabled at (0): [< (null)>] (null) >>> [ 108.04] hardirqs last disabled at (0): [] >>> copy_process.part.2+0x2a4/0x12f4 >>> [ 108.04] softirqs last enabled at (0): [] >>> copy_process.part.2+0x2a4/0x12f4 >>> [ 108.04] softirqs last disabled at (0): [< (null)>] (null) >>> [ 108.04] CPU: 3 PID: 0 Comm: swapper/3 Tainted: GW >>> 3.14.0-rc2-4-g0db95f4 #128 >>> [ 108.04] [] (unwind_backtrace) from [] >>> (show_stack+0x10/0x14) >>> [ 108.04] [] (show_stack) from [] >>> (dump_stack+0x6c/0xb8) >>> [ 108.04] [] (dump_stack) from [] >>> (kmem_cache_alloc+0xd4/0x160) >>> [ 108.04] [] (kmem_cache_alloc) from [] >>> (request_threaded_irq+0x64/0x130) >>> [ 108.04] [] (request_threaded_irq) from [] >>> (exynos4_local_timer_setup+0xd0/0x124) >>> [ 108.04] [] (exynos4_local_timer_setup) from [] >>> (exynos4_mct_cpu_notify+0x78/0xf0) >>> [ 108.04] [] (exynos4_mct_cpu_notify) from [] >>> (notifier_call_chain+0x44/0x84) >>> [ 108.04] [] (notifier_call_chain) from [] >>> (__cpu_notify+0x24/0x40) >>> [ 108.04] [] (__cpu_notify) from [] >>> (secondary_start_kernel+0xe4/0x134) >>> [ 108.04] [] (secondary_start_kernel) from [<40008624>] >>> (0x40008624) >>> >>> First patch fixes this problem by removing request_irq from >>> exynos4_local_timer_setup >>> Second removes non-dt stuff. >>> >>> Tested on linux kernel v3.14-rc2. >> >> >> It would be nice to say on which boards it has been tested. Let me check >> this on our boards anyway. >> >> Best regards, >> Tomasz > > > Tested on smdk5410 reference board with lockdep enabled. > I think the problem will present on all boards due to call sleeping function > in irq_disabled context. > > Best Regards, > Tarek > Has anyone else tested this patches? if yes, what is the result? Best regards, . Tarek -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1 0/2] exynos_mct driver: fix irq allocation and cleanup
On Thu, Feb 13, 2014 at 10:31 PM, Tarek Dakhran t.dakh...@gmail.com wrote: Hi Tomasz, On Thursday, February 13, 2014, Tomasz Figa t.f...@samsung.com wrote: Hi Tarek, On 13.02.2014 04:08, Tarek Dakhran wrote: exynos4_local_timer_setup called on the secondary cpu before irqs are enabled. request_irq can sleep, which produces next warning: on boot: [0.37] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 [0.37] Setting up static identity map for 0x403b5700 - 0x403b5758 [0.395000] CPU1: Booted secondary processor [0.395000] [ cut here ] [0.395000] WARNING: CPU: 1 PID: 0 at kernel/locking/lockdep.c:2742 lockdep_trace_alloc+0xe0/0xfc() [0.395000] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags)) [0.395000] Modules linked in: [0.395000] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.14.0-rc2-4-g0db95f4 #128 [0.395000] [c0014308] (unwind_backtrace) from [c0011690] (show_stack+0x10/0x14) [0.395000] [c0011690] (show_stack) from [c03ae7d0] (dump_stack+0x6c/0xb8) [0.395000] [c03ae7d0] (dump_stack) from [c001d504] (warn_slowpath_common+0x68/0x8c) [0.395000] [c001d504] (warn_slowpath_common) from [c001d5bc] (warn_slowpath_fmt+0x30/0x40) [0.395000] [c001d5bc] (warn_slowpath_fmt) from [c0059824] (lockdep_trace_alloc+0xe0/0xfc) [0.395000] [c0059824] (lockdep_trace_alloc) from [c00bee24] (kmem_cache_alloc+0x24/0x160) [0.395000] [c00bee24] (kmem_cache_alloc) from [c0068174] (request_threaded_irq+0x64/0x130) [0.395000] [c0068174] (request_threaded_irq) from [c02efaf8] (exynos4_local_timer_setup+0xd0/0x124) [0.395000] [c02efaf8] (exynos4_local_timer_setup) from [c02efc34] (exynos4_mct_cpu_notify+0x78/0xf0) [0.395000] [c02efc34] (exynos4_mct_cpu_notify) from [c003d318] (notifier_call_chain+0x44/0x84) [0.395000] [c003d318] (notifier_call_chain) from [c001d61c] (__cpu_notify+0x24/0x40) [0.395000] [c001d61c] (__cpu_notify) from [c0013314] (secondary_start_kernel+0xe4/0x134) [0.395000] [c0013314] (secondary_start_kernel) from [40008624] (0x40008624) [0.395000] ---[ end trace 347890460e745f50 ]--- [0.42] CPU1: update cpu_power 1024 [0.42] CPU1: thread -1, cpu 1, socket 0, mpidr 8001 on hotplug: [ 108.04] CPU3: Booted secondary processor [ 108.04] BUG: sleeping function called from invalid context at mm/slub.c:965 [ 108.04] in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/3 [ 108.04] INFO: lockdep is turned off. [ 108.04] irq event stamp: 0 [ 108.04] hardirqs last enabled at (0): [ (null)] (null) [ 108.04] hardirqs last disabled at (0): [c001b768] copy_process.part.2+0x2a4/0x12f4 [ 108.04] softirqs last enabled at (0): [c001b768] copy_process.part.2+0x2a4/0x12f4 [ 108.04] softirqs last disabled at (0): [ (null)] (null) [ 108.04] CPU: 3 PID: 0 Comm: swapper/3 Tainted: GW 3.14.0-rc2-4-g0db95f4 #128 [ 108.04] [c0014308] (unwind_backtrace) from [c0011690] (show_stack+0x10/0x14) [ 108.04] [c0011690] (show_stack) from [c03ae7d0] (dump_stack+0x6c/0xb8) [ 108.04] [c03ae7d0] (dump_stack) from [c00beed4] (kmem_cache_alloc+0xd4/0x160) [ 108.04] [c00beed4] (kmem_cache_alloc) from [c0068174] (request_threaded_irq+0x64/0x130) [ 108.04] [c0068174] (request_threaded_irq) from [c02efaf8] (exynos4_local_timer_setup+0xd0/0x124) [ 108.04] [c02efaf8] (exynos4_local_timer_setup) from [c02efc34] (exynos4_mct_cpu_notify+0x78/0xf0) [ 108.04] [c02efc34] (exynos4_mct_cpu_notify) from [c003d318] (notifier_call_chain+0x44/0x84) [ 108.04] [c003d318] (notifier_call_chain) from [c001d61c] (__cpu_notify+0x24/0x40) [ 108.04] [c001d61c] (__cpu_notify) from [c0013314] (secondary_start_kernel+0xe4/0x134) [ 108.04] [c0013314] (secondary_start_kernel) from [40008624] (0x40008624) First patch fixes this problem by removing request_irq from exynos4_local_timer_setup Second removes non-dt stuff. Tested on linux kernel v3.14-rc2. It would be nice to say on which boards it has been tested. Let me check this on our boards anyway. Best regards, Tomasz Tested on smdk5410 reference board with lockdep enabled. I think the problem will present on all boards due to call sleeping function in irq_disabled context. Best Regards, Tarek Has anyone else tested this patches? if yes, what is the result? Best regards, . Tarek -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 0/2] exynos_mct driver: fix irq allocation and cleanup
exynos4_local_timer_setup called on the secondary cpu before
irqs are enabled. request_irq can sleep, which produces next warning:
on boot:
[0.37] CPU0: thread -1, cpu 0, socket 0, mpidr 8000
[0.37] Setting up static identity map for 0x403b5700 - 0x403b5758
[0.395000] CPU1: Booted secondary processor
[0.395000] [ cut here ]
[0.395000] WARNING: CPU: 1 PID: 0 at kernel/locking/lockdep.c:2742
lockdep_trace_alloc+0xe0/0xfc()
[0.395000] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
[0.395000] Modules linked in:
[0.395000] CPU: 1 PID: 0 Comm: swapper/1 Not tainted
3.14.0-rc2-4-g0db95f4 #128
[0.395000] [] (unwind_backtrace) from []
(show_stack+0x10/0x14)
[0.395000] [] (show_stack) from []
(dump_stack+0x6c/0xb8)
[0.395000] [] (dump_stack) from []
(warn_slowpath_common+0x68/0x8c)
[0.395000] [] (warn_slowpath_common) from []
(warn_slowpath_fmt+0x30/0x40)
[0.395000] [] (warn_slowpath_fmt) from []
(lockdep_trace_alloc+0xe0/0xfc)
[0.395000] [] (lockdep_trace_alloc) from []
(kmem_cache_alloc+0x24/0x160)
[0.395000] [] (kmem_cache_alloc) from []
(request_threaded_irq+0x64/0x130)
[0.395000] [] (request_threaded_irq) from []
(exynos4_local_timer_setup+0xd0/0x124)
[0.395000] [] (exynos4_local_timer_setup) from []
(exynos4_mct_cpu_notify+0x78/0xf0)
[0.395000] [] (exynos4_mct_cpu_notify) from []
(notifier_call_chain+0x44/0x84)
[0.395000] [] (notifier_call_chain) from []
(__cpu_notify+0x24/0x40)
[0.395000] [] (__cpu_notify) from []
(secondary_start_kernel+0xe4/0x134)
[0.395000] [] (secondary_start_kernel) from [<40008624>]
(0x40008624)
[0.395000] ---[ end trace 347890460e745f50 ]---
[0.42] CPU1: update cpu_power 1024
[0.42] CPU1: thread -1, cpu 1, socket 0, mpidr 8001
on hotplug:
[ 108.04] CPU3: Booted secondary processor
[ 108.04] BUG: sleeping function called from invalid context at
mm/slub.c:965
[ 108.04] in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/3
[ 108.04] INFO: lockdep is turned off.
[ 108.04] irq event stamp: 0
[ 108.04] hardirqs last enabled at (0): [< (null)>] (null)
[ 108.04] hardirqs last disabled at (0): []
copy_process.part.2+0x2a4/0x12f4
[ 108.04] softirqs last enabled at (0): []
copy_process.part.2+0x2a4/0x12f4
[ 108.04] softirqs last disabled at (0): [< (null)>] (null)
[ 108.04] CPU: 3 PID: 0 Comm: swapper/3 Tainted: GW
3.14.0-rc2-4-g0db95f4 #128
[ 108.04] [] (unwind_backtrace) from []
(show_stack+0x10/0x14)
[ 108.04] [] (show_stack) from []
(dump_stack+0x6c/0xb8)
[ 108.04] [] (dump_stack) from []
(kmem_cache_alloc+0xd4/0x160)
[ 108.04] [] (kmem_cache_alloc) from []
(request_threaded_irq+0x64/0x130)
[ 108.04] [] (request_threaded_irq) from []
(exynos4_local_timer_setup+0xd0/0x124)
[ 108.04] [] (exynos4_local_timer_setup) from []
(exynos4_mct_cpu_notify+0x78/0xf0)
[ 108.04] [] (exynos4_mct_cpu_notify) from []
(notifier_call_chain+0x44/0x84)
[ 108.04] [] (notifier_call_chain) from []
(__cpu_notify+0x24/0x40)
[ 108.04] [] (__cpu_notify) from []
(secondary_start_kernel+0xe4/0x134)
[ 108.04] [] (secondary_start_kernel) from [<40008624>]
(0x40008624)
First patch fixes this problem by removing request_irq from
exynos4_local_timer_setup
Second removes non-dt stuff.
Tested on linux kernel v3.14-rc2.
Comments and additions would be appreciated.
Thank you.
Tarek.
Tarek Dakhran (2):
clocksource: mct: remove request_irq from exynos4_local_timer_setup
clocksource: mct: cleanup, remove non-dt stuff from mct
arch/arm/mach-exynos/common.h|2 --
drivers/clocksource/exynos_mct.c | 55 +-
2 files changed, 31 insertions(+), 26 deletions(-)
--
1.7.10.4
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 2/2] clocksource: mct: cleanup, remove non-dt stuff from mct
mct_init not used anywhere, remove this non-dt stuff.
also remove declaration of mct_init
in arch/arm/mach-exynos/common.h
Signed-off-by: Tarek Dakhran
---
arch/arm/mach-exynos/common.h|2 --
drivers/clocksource/exynos_mct.c | 17 +
2 files changed, 1 insertion(+), 18 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f76967b..8945170 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -15,8 +15,6 @@
#include
#include
-void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
-
struct map_desc;
void exynos_init_io(void);
void exynos4_restart(enum reboot_mode mode, const char *cmd);
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 1cde3de..a94a908 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -548,18 +548,6 @@ out_irq:
free_percpu_irq(mct_irqs[MCT_L0_IRQ], _mct_tick);
}
-void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
-{
- mct_irqs[MCT_G0_IRQ] = irq_g0;
- mct_irqs[MCT_L0_IRQ] = irq_l0;
- mct_irqs[MCT_L1_IRQ] = irq_l1;
- mct_int_type = MCT_INT_SPI;
-
- exynos4_timer_resources(NULL, base);
- exynos4_clocksource_init();
- exynos4_clockevent_init();
-}
-
static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
{
u32 nr_irqs, i;
@@ -574,11 +562,8 @@ static void __init mct_init_dt(struct device_node *np,
unsigned int int_type)
* timer irqs are specified after the four global timer
* irqs are specified.
*/
-#ifdef CONFIG_OF
nr_irqs = of_irq_count(np);
-#else
- nr_irqs = 0;
-#endif
+
for (i = MCT_L0_IRQ; i < nr_irqs; i++)
mct_irqs[i] = irq_of_parse_and_map(np, i);
--
1.7.10.4
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/2] clocksource: mct: remove request_irq from exynos4_local_timer_setup
exynos4_local_timer_setup called on the secondary cpu before
irqs are enabled. request_irq can sleep, which produces next warning:
BUG: sleeping function called from invalid context at mm/slub.c:965
in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/3
Call setup_irq for each local timer in exynos4_timer_resources,
and only call enable_irq during percpu timer setup.
Signed-off-by: Tarek Dakhran
---
drivers/clocksource/exynos_mct.c | 38 ++
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 48f76bc..1cde3de 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -82,6 +82,7 @@ static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
static int mct_irqs[MCT_NR_IRQS];
+static struct irqaction __percpu *mct_LX_irqaction;
struct mct_clock_event_device {
struct clock_event_device evt;
@@ -402,6 +403,25 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void
*dev_id)
return IRQ_HANDLED;
}
+static void exynos4_setup_irqaction_spi(unsigned int cpu)
+{
+ struct irqaction *pcpu_irqaction = per_cpu_ptr(mct_LX_irqaction, cpu);
+ unsigned int irq = mct_irqs[MCT_L0_IRQ + cpu];
+ int err;
+
+ pcpu_irqaction->name = per_cpu(percpu_mct_tick, cpu).name;
+ pcpu_irqaction->flags = IRQF_TIMER | IRQF_NOBALANCING;
+ pcpu_irqaction->handler = exynos4_mct_tick_isr;
+ pcpu_irqaction->dev_id = _cpu(percpu_mct_tick, cpu);
+
+ err = setup_irq(irq, pcpu_irqaction);
+ if (err) {
+ pr_err("MCT: can't setup IRQ %d (%d)\n", irq, err);
+ return;
+ }
+ disable_irq(irq);
+}
+
static int exynos4_local_timer_setup(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
@@ -425,13 +445,7 @@ static int exynos4_local_timer_setup(struct
clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
- if (request_irq(evt->irq, exynos4_mct_tick_isr,
- IRQF_TIMER | IRQF_NOBALANCING,
- evt->name, mevt)) {
- pr_err("exynos-mct: cannot register IRQ %d\n",
- evt->irq);
- return -EIO;
- }
+ enable_irq(evt->irq);
} else {
enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
}
@@ -443,7 +457,7 @@ static void exynos4_local_timer_stop(struct
clock_event_device *evt)
{
evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
if (mct_int_type == MCT_INT_SPI)
- free_irq(evt->irq, this_cpu_ptr(_mct_tick));
+ disable_irq(evt->irq);
else
disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}
@@ -485,9 +499,12 @@ static struct notifier_block exynos4_mct_cpu_nb = {
static void __init exynos4_timer_resources(struct device_node *np, void
__iomem *base)
{
int err;
+ u32 i, cpu, nr_irqs;
struct mct_clock_event_device *mevt = this_cpu_ptr(_mct_tick);
struct clk *mct_clk, *tick_clk;
+ nr_irqs = of_irq_count(np);
+
tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
clk_get(NULL, "fin_pll");
if (IS_ERR(tick_clk))
@@ -511,6 +528,11 @@ static void __init exynos4_timer_resources(struct
device_node *np, void __iomem
WARN(err, "MCT: can't request IRQ %d (%d)\n",
mct_irqs[MCT_L0_IRQ], err);
} else {
+ mct_LX_irqaction = alloc_percpu(struct irqaction);
+ BUG_ON(!mct_LX_irqaction);
+
+ for (i = MCT_L0_IRQ, cpu = 0; i < nr_irqs; i++, cpu++)
+ exynos4_setup_irqaction_spi(cpu);
irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
}
--
1.7.10.4
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[PATCH v1 1/2] clocksource: mct: remove request_irq from exynos4_local_timer_setup
exynos4_local_timer_setup called on the secondary cpu before
irqs are enabled. request_irq can sleep, which produces next warning:
BUG: sleeping function called from invalid context at mm/slub.c:965
in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/3
Call setup_irq for each local timer in exynos4_timer_resources,
and only call enable_irq during percpu timer setup.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
---
drivers/clocksource/exynos_mct.c | 38 ++
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 48f76bc..1cde3de 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -82,6 +82,7 @@ static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
static int mct_irqs[MCT_NR_IRQS];
+static struct irqaction __percpu *mct_LX_irqaction;
struct mct_clock_event_device {
struct clock_event_device evt;
@@ -402,6 +403,25 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void
*dev_id)
return IRQ_HANDLED;
}
+static void exynos4_setup_irqaction_spi(unsigned int cpu)
+{
+ struct irqaction *pcpu_irqaction = per_cpu_ptr(mct_LX_irqaction, cpu);
+ unsigned int irq = mct_irqs[MCT_L0_IRQ + cpu];
+ int err;
+
+ pcpu_irqaction-name = per_cpu(percpu_mct_tick, cpu).name;
+ pcpu_irqaction-flags = IRQF_TIMER | IRQF_NOBALANCING;
+ pcpu_irqaction-handler = exynos4_mct_tick_isr;
+ pcpu_irqaction-dev_id = per_cpu(percpu_mct_tick, cpu);
+
+ err = setup_irq(irq, pcpu_irqaction);
+ if (err) {
+ pr_err(MCT: can't setup IRQ %d (%d)\n, irq, err);
+ return;
+ }
+ disable_irq(irq);
+}
+
static int exynos4_local_timer_setup(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
@@ -425,13 +445,7 @@ static int exynos4_local_timer_setup(struct
clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
evt-irq = mct_irqs[MCT_L0_IRQ + cpu];
- if (request_irq(evt-irq, exynos4_mct_tick_isr,
- IRQF_TIMER | IRQF_NOBALANCING,
- evt-name, mevt)) {
- pr_err(exynos-mct: cannot register IRQ %d\n,
- evt-irq);
- return -EIO;
- }
+ enable_irq(evt-irq);
} else {
enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
}
@@ -443,7 +457,7 @@ static void exynos4_local_timer_stop(struct
clock_event_device *evt)
{
evt-set_mode(CLOCK_EVT_MODE_UNUSED, evt);
if (mct_int_type == MCT_INT_SPI)
- free_irq(evt-irq, this_cpu_ptr(percpu_mct_tick));
+ disable_irq(evt-irq);
else
disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}
@@ -485,9 +499,12 @@ static struct notifier_block exynos4_mct_cpu_nb = {
static void __init exynos4_timer_resources(struct device_node *np, void
__iomem *base)
{
int err;
+ u32 i, cpu, nr_irqs;
struct mct_clock_event_device *mevt = this_cpu_ptr(percpu_mct_tick);
struct clk *mct_clk, *tick_clk;
+ nr_irqs = of_irq_count(np);
+
tick_clk = np ? of_clk_get_by_name(np, fin_pll) :
clk_get(NULL, fin_pll);
if (IS_ERR(tick_clk))
@@ -511,6 +528,11 @@ static void __init exynos4_timer_resources(struct
device_node *np, void __iomem
WARN(err, MCT: can't request IRQ %d (%d)\n,
mct_irqs[MCT_L0_IRQ], err);
} else {
+ mct_LX_irqaction = alloc_percpu(struct irqaction);
+ BUG_ON(!mct_LX_irqaction);
+
+ for (i = MCT_L0_IRQ, cpu = 0; i nr_irqs; i++, cpu++)
+ exynos4_setup_irqaction_spi(cpu);
irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
}
--
1.7.10.4
--
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[PATCH v1 2/2] clocksource: mct: cleanup, remove non-dt stuff from mct
mct_init not used anywhere, remove this non-dt stuff.
also remove declaration of mct_init
in arch/arm/mach-exynos/common.h
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
---
arch/arm/mach-exynos/common.h|2 --
drivers/clocksource/exynos_mct.c | 17 +
2 files changed, 1 insertion(+), 18 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f76967b..8945170 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -15,8 +15,6 @@
#include linux/reboot.h
#include linux/of.h
-void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
-
struct map_desc;
void exynos_init_io(void);
void exynos4_restart(enum reboot_mode mode, const char *cmd);
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 1cde3de..a94a908 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -548,18 +548,6 @@ out_irq:
free_percpu_irq(mct_irqs[MCT_L0_IRQ], percpu_mct_tick);
}
-void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
-{
- mct_irqs[MCT_G0_IRQ] = irq_g0;
- mct_irqs[MCT_L0_IRQ] = irq_l0;
- mct_irqs[MCT_L1_IRQ] = irq_l1;
- mct_int_type = MCT_INT_SPI;
-
- exynos4_timer_resources(NULL, base);
- exynos4_clocksource_init();
- exynos4_clockevent_init();
-}
-
static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
{
u32 nr_irqs, i;
@@ -574,11 +562,8 @@ static void __init mct_init_dt(struct device_node *np,
unsigned int int_type)
* timer irqs are specified after the four global timer
* irqs are specified.
*/
-#ifdef CONFIG_OF
nr_irqs = of_irq_count(np);
-#else
- nr_irqs = 0;
-#endif
+
for (i = MCT_L0_IRQ; i nr_irqs; i++)
mct_irqs[i] = irq_of_parse_and_map(np, i);
--
1.7.10.4
--
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[PATCH v1 0/2] exynos_mct driver: fix irq allocation and cleanup
exynos4_local_timer_setup called on the secondary cpu before irqs are enabled. request_irq can sleep, which produces next warning: on boot: [0.37] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 [0.37] Setting up static identity map for 0x403b5700 - 0x403b5758 [0.395000] CPU1: Booted secondary processor [0.395000] [ cut here ] [0.395000] WARNING: CPU: 1 PID: 0 at kernel/locking/lockdep.c:2742 lockdep_trace_alloc+0xe0/0xfc() [0.395000] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags)) [0.395000] Modules linked in: [0.395000] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.14.0-rc2-4-g0db95f4 #128 [0.395000] [c0014308] (unwind_backtrace) from [c0011690] (show_stack+0x10/0x14) [0.395000] [c0011690] (show_stack) from [c03ae7d0] (dump_stack+0x6c/0xb8) [0.395000] [c03ae7d0] (dump_stack) from [c001d504] (warn_slowpath_common+0x68/0x8c) [0.395000] [c001d504] (warn_slowpath_common) from [c001d5bc] (warn_slowpath_fmt+0x30/0x40) [0.395000] [c001d5bc] (warn_slowpath_fmt) from [c0059824] (lockdep_trace_alloc+0xe0/0xfc) [0.395000] [c0059824] (lockdep_trace_alloc) from [c00bee24] (kmem_cache_alloc+0x24/0x160) [0.395000] [c00bee24] (kmem_cache_alloc) from [c0068174] (request_threaded_irq+0x64/0x130) [0.395000] [c0068174] (request_threaded_irq) from [c02efaf8] (exynos4_local_timer_setup+0xd0/0x124) [0.395000] [c02efaf8] (exynos4_local_timer_setup) from [c02efc34] (exynos4_mct_cpu_notify+0x78/0xf0) [0.395000] [c02efc34] (exynos4_mct_cpu_notify) from [c003d318] (notifier_call_chain+0x44/0x84) [0.395000] [c003d318] (notifier_call_chain) from [c001d61c] (__cpu_notify+0x24/0x40) [0.395000] [c001d61c] (__cpu_notify) from [c0013314] (secondary_start_kernel+0xe4/0x134) [0.395000] [c0013314] (secondary_start_kernel) from [40008624] (0x40008624) [0.395000] ---[ end trace 347890460e745f50 ]--- [0.42] CPU1: update cpu_power 1024 [0.42] CPU1: thread -1, cpu 1, socket 0, mpidr 8001 on hotplug: [ 108.04] CPU3: Booted secondary processor [ 108.04] BUG: sleeping function called from invalid context at mm/slub.c:965 [ 108.04] in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/3 [ 108.04] INFO: lockdep is turned off. [ 108.04] irq event stamp: 0 [ 108.04] hardirqs last enabled at (0): [ (null)] (null) [ 108.04] hardirqs last disabled at (0): [c001b768] copy_process.part.2+0x2a4/0x12f4 [ 108.04] softirqs last enabled at (0): [c001b768] copy_process.part.2+0x2a4/0x12f4 [ 108.04] softirqs last disabled at (0): [ (null)] (null) [ 108.04] CPU: 3 PID: 0 Comm: swapper/3 Tainted: GW 3.14.0-rc2-4-g0db95f4 #128 [ 108.04] [c0014308] (unwind_backtrace) from [c0011690] (show_stack+0x10/0x14) [ 108.04] [c0011690] (show_stack) from [c03ae7d0] (dump_stack+0x6c/0xb8) [ 108.04] [c03ae7d0] (dump_stack) from [c00beed4] (kmem_cache_alloc+0xd4/0x160) [ 108.04] [c00beed4] (kmem_cache_alloc) from [c0068174] (request_threaded_irq+0x64/0x130) [ 108.04] [c0068174] (request_threaded_irq) from [c02efaf8] (exynos4_local_timer_setup+0xd0/0x124) [ 108.04] [c02efaf8] (exynos4_local_timer_setup) from [c02efc34] (exynos4_mct_cpu_notify+0x78/0xf0) [ 108.04] [c02efc34] (exynos4_mct_cpu_notify) from [c003d318] (notifier_call_chain+0x44/0x84) [ 108.04] [c003d318] (notifier_call_chain) from [c001d61c] (__cpu_notify+0x24/0x40) [ 108.04] [c001d61c] (__cpu_notify) from [c0013314] (secondary_start_kernel+0xe4/0x134) [ 108.04] [c0013314] (secondary_start_kernel) from [40008624] (0x40008624) First patch fixes this problem by removing request_irq from exynos4_local_timer_setup Second removes non-dt stuff. Tested on linux kernel v3.14-rc2. Comments and additions would be appreciated. Thank you. Tarek. Tarek Dakhran (2): clocksource: mct: remove request_irq from exynos4_local_timer_setup clocksource: mct: cleanup, remove non-dt stuff from mct arch/arm/mach-exynos/common.h|2 -- drivers/clocksource/exynos_mct.c | 55 +- 2 files changed, 31 insertions(+), 26 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 0/1] Boot all secondary cores on Exynos SoC's
Due to implementation of exynos_boot_secondary function only one secondary core boots on Exynos SoC's. Two new functions added to power up and power down secondary cores: static int exynos_core_power_up(unsigned int cpu); static int exynos_core_power_down(unsigned int cpu). Tested on linux kernel v3.14-rc2. Comments and additions would be appreciated. Thank you. Tarek. Tarek Dakhran (1): ARM: EXYNOS: enable boot all secondary cpus instead 2 arch/arm/mach-exynos/hotplug.c | 11 -- arch/arm/mach-exynos/platsmp.c | 75 --- arch/arm/mach-exynos/regs-pmu.h |5 +++ 3 files changed, 68 insertions(+), 23 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/1] ARM: EXYNOS: enable boot all secondary cpus instead 2
Functions to boot secondary cpus added.
exynos_core_power_up(unsigned int cpu) added for power up any cpu.
exynos_core_power_down(unsigned int cpu) for power down any cpu.
Signed-off-by: Tarek Dakhran
---
arch/arm/mach-exynos/hotplug.c | 11 --
arch/arm/mach-exynos/platsmp.c | 75 ---
arch/arm/mach-exynos/regs-pmu.h |5 +++
3 files changed, 68 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..71982fa 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -90,13 +90,18 @@ static inline void cpu_leave_lowpower(void)
: "cc");
}
+static void exynos_core_power_down(unsigned int cpu)
+{
+ writel_relaxed(0, S5P_ARM_CORE_CONFIGURATION(cpu));
+}
+
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
for (;;) {
- /* make cpu1 to be turned off at next WFI command */
- if (cpu == 1)
- __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+ /* make cpu to be turned off at next WFI command */
+ if (cpu)
+ exynos_core_power_down(cpu);
/*
* here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..4008fc8 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -88,10 +88,61 @@ static void exynos_secondary_init(unsigned int cpu)
spin_unlock(_lock);
}
+/*
+ * core_power_state is used to get core power state.
+ * returns:
+ *0x0 - powered off;
+ *0x3 - powered on;
+ *other values - in process;
+ */
+static unsigned int core_power_state(unsigned int cpu)
+{
+ unsigned int status = readl_relaxed(S5P_ARM_CORE_STATUS(cpu));
+
+ return status & CORE_PWR_STATE_MASK;
+}
+
+#define TIMEOUT 10
+#define DELAY_TIME 1
+
+static int wait_core_power_up(unsigned int cpu)
+{
+ int timeout = TIMEOUT;
+
+ do {
+ /* checking if power controller in reset */
+ if (core_power_state(cpu) == S5P_CORE_LOCAL_PWR_EN)
+ return 0;
+ mdelay(DELAY_TIME);
+ timeout -= DELAY_TIME;
+ } while (timeout > 0);
+
+ return -ETIMEDOUT; /* timeout */
+}
+
+static int exynos_core_power_up(unsigned int cpu)
+{
+ int ret;
+
+ if (core_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
+ writel_relaxed(S5P_CORE_LOCAL_PWR_EN,
+ S5P_ARM_CORE_CONFIGURATION(cpu));
+
+ ret = wait_core_power_up(cpu);
+ if (ret) {
+ pr_debug("timeout powering on CPU%d\n", cpu);
+ return ret; /* timeout */
+ }
+ }
+
+ return 0;
+}
+
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
+ int ret;
/*
* Set synchronisation state between this boot processor
@@ -109,26 +160,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct
task_struct *idle)
*/
write_pen_release(phys_cpu);
- if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
-
- timeout = 10;
-
- /* wait max 10 ms until cpu1 is on */
- while ((__raw_readl(S5P_ARM_CORE1_STATUS)
- & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
- if (timeout-- == 0)
- break;
-
- mdelay(1);
- }
-
- if (timeout == 0) {
- printk(KERN_ERR "cpu1 power enable failed");
- spin_unlock(_lock);
- return -ETIMEDOUT;
- }
+ ret = exynos_core_power_up(cpu);
+ if (ret) {
+ spin_unlock(_lock);
+ return ret;
}
/*
* Send the secondary CPU a soft interrupt, thereby causing
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 7c029ce..4fc1e8f 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -104,6 +104,11 @@
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
+#define CORE_PWR_STATE_MASK0x3
+
+#define S5P_ARM_CORE_CONFIGURATION(_nr)(S5P_PMUREG(0x2000) + ((_nr) *
0x80))
+#define S5P_ARM_CORE_STATUS(_nr) (S5P_PMUREG(0x2004) + ((_nr) * 0x80))
+
#define S5P_ARM_CORE1_CONFIGURATIONS5P
[PATCH v6 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++
arch/arm/boot/dts/exynos5410.dtsi | 140 +
3 files changed, 213 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b..693dcdc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5420-arndale-octa.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+ };
+
+ mmc@1220 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..56b44d1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,140 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <16>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <16>;
+
[PATCH v6 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/Kconfig | 10 ++
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
arch/arm/mach-exynos/platsmp.c |2 ++
arch/arm/plat-samsung/include/plat/cpu.h |8
arch/arm/plat-samsung/include/plat/map-s5p.h |3 +++
7 files changed, 43 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c414af..97a06c3 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -91,6 +91,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f18be40..f1483bd 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -379,6 +395,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 37ea261..22245b2 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -51,6 +51,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..b681f89 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -39,6 +39,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return EXYNOS5410_BOOT_REG;
return S5P_VA_SYSRAM;
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/
[PATCH v6 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Dual cluster support for Exynos 5410 (EDCS) has been removed from this series This patches is activating only the big cluster (2xA15 cores) EDCS patch, which allows all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time, will be released separately Has been build on v3.14-rc1 Has been tested on Exynos 5410 reference board (exynos_defconfig) Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre. I hope, this is enough clean and hasn't any dependencies to go through Samsung tree. Tarek. Changelog: v6: small changes in Makefiles for resolving conflicts related to changes in Samsung tree. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 54 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 ++ arch/arm/boot/dts/exynos5410.dtsi | 140 arch/arm/mach-exynos/Kconfig | 10 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/include/mach/map.h|1 + arch/arm/mach-exynos/mach-exynos5-dt.c |1 + arch/arm/mach-exynos/platsmp.c |2 + arch/arm/plat-samsung/include/plat/cpu.h |8 + arch/arm/plat-samsung/include/plat/map-s5p.h |3 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 239 include/dt-bindings/clock/exynos5410.h | 32 +++ 14 files changed, 582 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Acked-by: Tomasz Figa
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 239
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 326 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - "fin_pll" - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#defin
[PATCH v6 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 10 ++
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
arch/arm/mach-exynos/platsmp.c |2 ++
arch/arm/plat-samsung/include/plat/cpu.h |8
arch/arm/plat-samsung/include/plat/map-s5p.h |3 +++
7 files changed, 43 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c414af..97a06c3 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -91,6 +91,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool SAMSUNG EXYNOS5410
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f18be40..f1483bd 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = EXYNOS4210;
static const char name_exynos4212[] = EXYNOS4212;
static const char name_exynos4412[] = EXYNOS4412;
static const char name_exynos5250[] = EXYNOS5250;
+static const char name_exynos5410[] = EXYNOS5410;
static const char name_exynos5420[] = EXYNOS5420;
static const char name_exynos5440[] = EXYNOS5440;
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -379,6 +395,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 37ea261..22245b2 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -51,6 +51,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
samsung,exynos5250,
+ samsung,exynos5410,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..b681f89 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -39,6 +39,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return EXYNOS5410_BOOT_REG;
return S5P_VA_SYSRAM;
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb3..8f09488 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat
[PATCH v6 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Dual cluster support for Exynos 5410 (EDCS) has been removed from this series This patches is activating only the big cluster (2xA15 cores) EDCS patch, which allows all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time, will be released separately Has been build on v3.14-rc1 Has been tested on Exynos 5410 reference board (exynos_defconfig) Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre. I hope, this is enough clean and hasn't any dependencies to go through Samsung tree. Tarek. Changelog: v6: small changes in Makefiles for resolving conflicts related to changes in Samsung tree. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 54 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 ++ arch/arm/boot/dts/exynos5410.dtsi | 140 arch/arm/mach-exynos/Kconfig | 10 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/include/mach/map.h|1 + arch/arm/mach-exynos/mach-exynos5-dt.c |1 + arch/arm/mach-exynos/platsmp.c |2 + arch/arm/plat-samsung/include/plat/cpu.h |8 + arch/arm/plat-samsung/include/plat/map-s5p.h |3 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 239 include/dt-bindings/clock/exynos5410.h | 32 +++ 14 files changed, 582 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Acked-by: Tomasz Figa t.f...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos5410.c | 239
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 326 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - fin_pll - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
[PATCH v6 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/Makefile|1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++
arch/arm/boot/dts/exynos5410.dtsi | 140 +
3 files changed, 213 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b..693dcdc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5420-arndale-octa.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ fin_pll: clock-fin-pll {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ };
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..56b44d1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,140 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos5410.h
+#include exynos5.dtsi
+/ {
+ compatible = samsung,exynos5410;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ clock-frequency = 16;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ clock-frequency = 16;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 2;
+ clock-frequency = 16;
+ };
+
+ CPU3: cpu@3 {
+ device_type
[PATCH v1 1/1] ARM: EXYNOS: enable boot all secondary cpus instead 2
Functions to boot secondary cpus added.
exynos_core_power_up(unsigned int cpu) added for power up any cpu.
exynos_core_power_down(unsigned int cpu) for power down any cpu.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
---
arch/arm/mach-exynos/hotplug.c | 11 --
arch/arm/mach-exynos/platsmp.c | 75 ---
arch/arm/mach-exynos/regs-pmu.h |5 +++
3 files changed, 68 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..71982fa 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -90,13 +90,18 @@ static inline void cpu_leave_lowpower(void)
: cc);
}
+static void exynos_core_power_down(unsigned int cpu)
+{
+ writel_relaxed(0, S5P_ARM_CORE_CONFIGURATION(cpu));
+}
+
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
for (;;) {
- /* make cpu1 to be turned off at next WFI command */
- if (cpu == 1)
- __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+ /* make cpu to be turned off at next WFI command */
+ if (cpu)
+ exynos_core_power_down(cpu);
/*
* here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..4008fc8 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -88,10 +88,61 @@ static void exynos_secondary_init(unsigned int cpu)
spin_unlock(boot_lock);
}
+/*
+ * core_power_state is used to get core power state.
+ * returns:
+ *0x0 - powered off;
+ *0x3 - powered on;
+ *other values - in process;
+ */
+static unsigned int core_power_state(unsigned int cpu)
+{
+ unsigned int status = readl_relaxed(S5P_ARM_CORE_STATUS(cpu));
+
+ return status CORE_PWR_STATE_MASK;
+}
+
+#define TIMEOUT 10
+#define DELAY_TIME 1
+
+static int wait_core_power_up(unsigned int cpu)
+{
+ int timeout = TIMEOUT;
+
+ do {
+ /* checking if power controller in reset */
+ if (core_power_state(cpu) == S5P_CORE_LOCAL_PWR_EN)
+ return 0;
+ mdelay(DELAY_TIME);
+ timeout -= DELAY_TIME;
+ } while (timeout 0);
+
+ return -ETIMEDOUT; /* timeout */
+}
+
+static int exynos_core_power_up(unsigned int cpu)
+{
+ int ret;
+
+ if (core_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
+ writel_relaxed(S5P_CORE_LOCAL_PWR_EN,
+ S5P_ARM_CORE_CONFIGURATION(cpu));
+
+ ret = wait_core_power_up(cpu);
+ if (ret) {
+ pr_debug(timeout powering on CPU%d\n, cpu);
+ return ret; /* timeout */
+ }
+ }
+
+ return 0;
+}
+
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
+ int ret;
/*
* Set synchronisation state between this boot processor
@@ -109,26 +160,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct
task_struct *idle)
*/
write_pen_release(phys_cpu);
- if (!(__raw_readl(S5P_ARM_CORE1_STATUS) S5P_CORE_LOCAL_PWR_EN)) {
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
-
- timeout = 10;
-
- /* wait max 10 ms until cpu1 is on */
- while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
- if (timeout-- == 0)
- break;
-
- mdelay(1);
- }
-
- if (timeout == 0) {
- printk(KERN_ERR cpu1 power enable failed);
- spin_unlock(boot_lock);
- return -ETIMEDOUT;
- }
+ ret = exynos_core_power_up(cpu);
+ if (ret) {
+ spin_unlock(boot_lock);
+ return ret;
}
/*
* Send the secondary CPU a soft interrupt, thereby causing
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 7c029ce..4fc1e8f 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -104,6 +104,11 @@
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
+#define CORE_PWR_STATE_MASK0x3
+
+#define S5P_ARM_CORE_CONFIGURATION(_nr)(S5P_PMUREG(0x2000) + ((_nr) *
0x80))
+#define S5P_ARM_CORE_STATUS(_nr) (S5P_PMUREG(0x2004) + ((_nr) * 0x80))
+
#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
#define S5P_ARM_CORE1_STATUS
[PATCH v1 0/1] Boot all secondary cores on Exynos SoC's
Due to implementation of exynos_boot_secondary function only one secondary core boots on Exynos SoC's. Two new functions added to power up and power down secondary cores: static int exynos_core_power_up(unsigned int cpu); static int exynos_core_power_down(unsigned int cpu). Tested on linux kernel v3.14-rc2. Comments and additions would be appreciated. Thank you. Tarek. Tarek Dakhran (1): ARM: EXYNOS: enable boot all secondary cpus instead 2 arch/arm/mach-exynos/hotplug.c | 11 -- arch/arm/mach-exynos/platsmp.c | 75 --- arch/arm/mach-exynos/regs-pmu.h |5 +++ 3 files changed, 68 insertions(+), 23 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 0/3] Exynos 5410 support
On 12/10/2013 08:40 PM, Kevin Hilman wrote: Vyacheslav Tyrtov writes: The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Dual cluster support for Exynos 5410 (EDCS) has been removed from this series This patches is activating only the big cluster (all A15 cores) Testing this series on top of v3.13-rc3, plus a couple of other necessary changes (which should've probably been noted in the changelog): 1) change CONFIG_NR_CPUS=8 in .config 2) add the exynos combiner patch from Chander: [PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value I'm still only seeing 2 out of 4 cores come up on my odroid-xu: [0.045000] CPU: Testing write buffer coherency: ok [0.045000] CPU0: update cpu_power 1024 [0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 [0.045000] Setting up static identity map for 0x403717d8 - 0x40371830 [0.045000] CPU1: Booted secondary processor [0.065000] CPU1: update cpu_power 1024 [0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 8001 [1.075000] CPU2: failed to boot: -38 [2.075000] CPU3: failed to boot: -38 [2.075000] Brought up 2 CPUs [2.075000] SMP: Total of 2 processors activated. [2.075000] CPU: All CPU(s) started in SVC mode. Hi Kevin, EDCS(exynos dual cluster support) moved to separate patch now. This patches introduce only base SoC support (2xA15). Patches tested on samsung smdk5410 board. Next version of EDCS patches will be available soon. They allow power on and boot all 8 cores. Best regards, Tarek Dakhran. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 0/3] Exynos 5410 support
On 12/10/2013 08:40 PM, Kevin Hilman wrote: Vyacheslav Tyrtov v.tyr...@samsung.com writes: The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Dual cluster support for Exynos 5410 (EDCS) has been removed from this series This patches is activating only the big cluster (all A15 cores) Testing this series on top of v3.13-rc3, plus a couple of other necessary changes (which should've probably been noted in the changelog): 1) change CONFIG_NR_CPUS=8 in .config 2) add the exynos combiner patch from Chander: [PATCH v2] irqchip: exynos-combiner: remove hard-coded irq_base value I'm still only seeing 2 out of 4 cores come up on my odroid-xu: [0.045000] CPU: Testing write buffer coherency: ok [0.045000] CPU0: update cpu_power 1024 [0.045000] CPU0: thread -1, cpu 0, socket 0, mpidr 8000 [0.045000] Setting up static identity map for 0x403717d8 - 0x40371830 [0.045000] CPU1: Booted secondary processor [0.065000] CPU1: update cpu_power 1024 [0.065000] CPU1: thread -1, cpu 1, socket 0, mpidr 8001 [1.075000] CPU2: failed to boot: -38 [2.075000] CPU3: failed to boot: -38 [2.075000] Brought up 2 CPUs [2.075000] SMP: Total of 2 processors activated. [2.075000] CPU: All CPU(s) started in SVC mode. Hi Kevin, EDCS(exynos dual cluster support) moved to separate patch now. This patches introduce only base SoC support (2xA15). Patches tested on samsung smdk5410 board. Next version of EDCS patches will be available soon. They allow power on and boot all 8 cores. Best regards, Tarek Dakhran. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 2/4] clk: exynos5410: register clocks using common clock framework
On 12/10/2013 12:37 AM, Kukjin Kim wrote: On 12/10/13 01:34, Tomasz Figa wrote: Hi Vyacheslav, Tarek, On Tuesday 26 of November 2013 12:58:06 Vyacheslav Tyrtov wrote: From: Tarek Dakhran The EXYNOS5410 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Tarek Dakhran Signed-off-by: Vyacheslav Tyrtov --- .../devicetree/bindings/clock/exynos5410-clock.txt | 54 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 239 + include/dt-bindings/clock/exynos5410.h | 32 +++ 4 files changed, 326 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h Acked-by: Tomasz Figa Tomasz, thanks for your ack on clk stuff. This should go through Samsung tree, I guess, since it's a dependency of other patches in this series and doesn't depend on any things from clock tree. Mike, Kukjin, are you okay with this? Yeah, I'm fine on this series but 4th patch for supporting dual cluster. Let me take 1 to 3 patches firstly. Thanks. - Kukjin Hi, Today (10/12/2013) I will release [PATCH v5] without dual cluster support. EDCS (exynos dual cluster support) will be moved to separate patch. Best regards, Tarek Dakhran. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 2/4] clk: exynos5410: register clocks using common clock framework
On 12/10/2013 12:37 AM, Kukjin Kim wrote: On 12/10/13 01:34, Tomasz Figa wrote: Hi Vyacheslav, Tarek, On Tuesday 26 of November 2013 12:58:06 Vyacheslav Tyrtov wrote: From: Tarek Dakhrant.dakh...@samsung.com The EXYNOS5410 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Tarek Dakhrant.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtovv.tyr...@samsung.com --- .../devicetree/bindings/clock/exynos5410-clock.txt | 54 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 239 + include/dt-bindings/clock/exynos5410.h | 32 +++ 4 files changed, 326 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h Acked-by: Tomasz Figat.f...@samsung.com Tomasz, thanks for your ack on clk stuff. This should go through Samsung tree, I guess, since it's a dependency of other patches in this series and doesn't depend on any things from clock tree. Mike, Kukjin, are you okay with this? Yeah, I'm fine on this series but 4th patch for supporting dual cluster. Let me take 1 to 3 patches firstly. Thanks. - Kukjin Hi, Today (10/12/2013) I will release [PATCH v5] without dual cluster support. EDCS (exynos dual cluster support) will be moved to separate patch. Best regards, Tarek Dakhran. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 0/4] Exynos 5410 Dual cluster support
Hi,
On 20.11.2013 03:23, Tomasz Figa wrote:
Hi,
On Thursday 07 of November 2013 12:12:45 Vyacheslav Tyrtov wrote:
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
Patches add new platform description, support of clock controller,
dual cluster support and device tree for Exynos 5410
Has been build on v3.12.
Has been tested on Exynos 5410 reference board (exynos_defconfig).
I've applied the patches on top of today's linux-next and tried to boot
my ODROID-XU using exynos5410-smdk5410.dts and exynos_defconfig, but all
I can get is an imprecise external abort, when the kernel tries to jump
to init. Full boot log below. Any ideas?
Best regards,
Tomasz
8><
U-Boot 2012.07-g2bcb371 (Nov 19 2013 - 20:17:37) for Exynos5410
CPU: Exynos5410 Rev2.3 [Samsung SOC on SMP Platform Base on ARM CortexA15]
APLL = 900MHz, KPLL = 600MHz
[snip]
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
[0.00] Booting Linux on physical CPU 0x0
[0.00] Initializing cgroup subsys cpuset
[0.00] Initializing cgroup subsys cpu
[0.00] Initializing cgroup subsys cpuacct
[0.00] Linux version 3.12.0-next-20131119-4-g27f3f5f-dirty
(tom3q@flatron) (gcc version 4.7.2 (Gentoo 4.7.2-r1 p1.6, pie-0.5.5) ) #11 SMP
PREEMPT Wed Nov 20 00:08:02 CET 2013
[0.00] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7), cr=10c5387d
[0.00] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[0.00] Machine model: Hardkernel ODROID-XU board based on EXYNOS5410
[0.00] bootconsole [earlycon0] enabled
[0.00] debug: ignoring loglevel setting.
[0.00] Memory policy: Data cache writealloc
[0.00] CPU EXYNOS5410 (id 0xe5410023)
[0.00] On node 0 totalpages: 262144
[snip]
[5.04] isa bounce pool size: 16 pages
[5.045000] mmcblk0: mmc1:e624 SU16G 14.8 GiB
[5.05] mmcblk0: p1
[5.12] EXT3-fs (mmcblk0p1): error: couldn't mount because of
unsupported optional features (240)
[5.125000] EXT2-fs (mmcblk0p1): error: couldn't mount because of
unsupported optional features (240)
[5.145000] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode.
Opts: (null)
[5.15] VFS: Mounted root (ext4 filesystem) readonly on device 179:1.
[5.165000] devtmpfs: mounted
[5.17] Freeing unused kernel memory: 228K (c0513000 - c054c000)
[5.195000] Unhandled fault: imprecise external abort (0x1406) at 0x
[5.21] Kernel panic - not syncing: Attempted to kill init!
exitcode=0x0007
[5.21]
[5.21] CPU: 2 PID: 1 Comm: init Not tainted
3.12.0-next-20131119-4-g27f3f5f-dirty #11
[5.21] [] (unwind_backtrace+0x0/0xf8) from []
(show_stack+0x10/0x14)
[5.21] [] (show_stack+0x10/0x14) from []
(dump_stack+0x7c/0xbc)
[5.21] [] (dump_stack+0x7c/0xbc) from []
(panic+0x8c/0x1e4)
[5.21] [] (panic+0x8c/0x1e4) from []
(do_exit+0x850/0x920)
[5.21] [] (do_exit+0x850/0x920) from []
(do_group_exit+0x3c/0xb0)
[5.21] [] (do_group_exit+0x3c/0xb0) from []
(get_signal_to_deliver+0x1d4/0x538)
[5.21] [] (get_signal_to_deliver+0x1d4/0x538) from
[] (do_signal+0x100/0x40c)
[5.21] [] (do_signal+0x100/0x40c) from []
(do_work_pending+0x68/0xa8)
[5.21] [] (do_work_pending+0x68/0xa8) from []
(work_pending+0xc/0x20)
[5.30] CPU3: stopping
[5.30] CPU: 3 PID: 0 Comm: swapper/3 Not tainted
3.12.0-next-20131119-4-g27f3f5f-dirty #11
Tomasz, there is CCI on/off switcher on smdk5410 board, also there is
XOMCCI pin on SoC.
Looks like switcher on board controls the XOMCCI SoC pin.
When I turn switcher OFF, I getting the same problem you got.
Please, check the cci state on Odroid-XU Board, maybe it is turned off.
Best regards,
Tarek Dakhran
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Re: [PATCH v3 0/4] Exynos 5410 Dual cluster support
Hi, On 20.11.2013 03:23, Tomasz Figa wrote: Hi, On Thursday 07 of November 2013 12:12:45 Vyacheslav Tyrtov wrote: The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support and device tree for Exynos 5410 Has been build on v3.12. Has been tested on Exynos 5410 reference board (exynos_defconfig). I've applied the patches on top of today's linux-next and tried to boot my ODROID-XU using exynos5410-smdk5410.dts and exynos_defconfig, but all I can get is an imprecise external abort, when the kernel tries to jump to init. Full boot log below. Any ideas? Best regards, Tomasz 8 U-Boot 2012.07-g2bcb371 (Nov 19 2013 - 20:17:37) for Exynos5410 CPU: Exynos5410 Rev2.3 [Samsung SOC on SMP Platform Base on ARM CortexA15] APLL = 900MHz, KPLL = 600MHz [snip] Starting kernel ... Uncompressing Linux... done, booting the kernel. [0.00] Booting Linux on physical CPU 0x0 [0.00] Initializing cgroup subsys cpuset [0.00] Initializing cgroup subsys cpu [0.00] Initializing cgroup subsys cpuacct [0.00] Linux version 3.12.0-next-20131119-4-g27f3f5f-dirty (tom3q@flatron) (gcc version 4.7.2 (Gentoo 4.7.2-r1 p1.6, pie-0.5.5) ) #11 SMP PREEMPT Wed Nov 20 00:08:02 CET 2013 [0.00] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7), cr=10c5387d [0.00] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache [0.00] Machine model: Hardkernel ODROID-XU board based on EXYNOS5410 [0.00] bootconsole [earlycon0] enabled [0.00] debug: ignoring loglevel setting. [0.00] Memory policy: Data cache writealloc [0.00] CPU EXYNOS5410 (id 0xe5410023) [0.00] On node 0 totalpages: 262144 [snip] [5.04] isa bounce pool size: 16 pages [5.045000] mmcblk0: mmc1:e624 SU16G 14.8 GiB [5.05] mmcblk0: p1 [5.12] EXT3-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240) [5.125000] EXT2-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240) [5.145000] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode. Opts: (null) [5.15] VFS: Mounted root (ext4 filesystem) readonly on device 179:1. [5.165000] devtmpfs: mounted [5.17] Freeing unused kernel memory: 228K (c0513000 - c054c000) [5.195000] Unhandled fault: imprecise external abort (0x1406) at 0x [5.21] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0007 [5.21] [5.21] CPU: 2 PID: 1 Comm: init Not tainted 3.12.0-next-20131119-4-g27f3f5f-dirty #11 [5.21] [c0014068] (unwind_backtrace+0x0/0xf8) from [c0011438] (show_stack+0x10/0x14) [5.21] [c0011438] (show_stack+0x10/0x14) from [c03a486c] (dump_stack+0x7c/0xbc) [5.21] [c03a486c] (dump_stack+0x7c/0xbc) from [c03a1e78] (panic+0x8c/0x1e4) [5.21] [c03a1e78] (panic+0x8c/0x1e4) from [c001f504] (do_exit+0x850/0x920) [5.21] [c001f504] (do_exit+0x850/0x920) from [c001f63c] (do_group_exit+0x3c/0xb0) [5.21] [c001f63c] (do_group_exit+0x3c/0xb0) from [c0029e1c] (get_signal_to_deliver+0x1d4/0x538) [5.21] [c0029e1c] (get_signal_to_deliver+0x1d4/0x538) from [c0010974] (do_signal+0x100/0x40c) [5.21] [c0010974] (do_signal+0x100/0x40c) from [c0010fb4] (do_work_pending+0x68/0xa8) [5.21] [c0010fb4] (do_work_pending+0x68/0xa8) from [c000e620] (work_pending+0xc/0x20) [5.30] CPU3: stopping [5.30] CPU: 3 PID: 0 Comm: swapper/3 Not tainted 3.12.0-next-20131119-4-g27f3f5f-dirty #11 Tomasz, there is CCI on/off switcher on smdk5410 board, also there is XOMCCI pin on SoC. Looks like switcher on board controls the XOMCCI SoC pin. When I turn switcher OFF, I getting the same problem you got. Please, check the cci state on Odroid-XU Board, maybe it is turned off. Best regards, Tarek Dakhran -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
Hi,
On 11.11.2013 11:58, Tarek Dakhran wrote:
On Thu, Nov 07, 2013 at 11:51:49AM -0500, Nicolas Pitre wrote:
Samsung people: could you give us more info on the behavior of the power
controller please?
Nicolas
This is how the power controller works on exynos5410. For example for
CORE0.
ARM_CORE0_STATUS register indicates the power state of Core 0 part of
processor core.
0x3 indicates that power to Core 0 is turned-on. 0x0 indicates that
power to Core 0 is turned-off.
All other values indicate that the power On/Off sequence of Core 0 in
progress.
To turn Off the power of Core 0 power domain:
1. Set the LOCAL_POWER_CFG field of ARM_CORE0_CONFIGURATION register
to 0x3.
2. After PMU detects a change in the LOCAL_POWER_CFG field, it waits
for the execution of WFI.
3. After Core 0 executes the WFI instruction, PMU starts the
power-down sequence.
4. The Status field of ARM_CORE0_STATUS register indicates the
completion of the sequence.
That's why in the v1 of this patch exynos_core_power_control function
was implemented as:
static int exynos_core_power_control(unsigned int cpu, unsigned int
cluster, int enable)
{
unsigned long timeout = jiffies + msecs_to_jiffies(10);
unsigned int offset = cluster * MAX_CPUS_PER_CLUSTER + cpu;
int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
if ((__raw_readl(EXYNOS5410_CORE_STATUS(offset)) & 0x3) == value)
return 0;
__raw_writel(value, EXYNOS5410_CORE_CONFIGURATION(offset));
do {
if ((__raw_readl(EXYNOS5410_CORE_STATUS(offset)) & 0x3)
== value)
return 0;
} while (time_before(jiffies, timeout));
return -EDEADLK;
}
But, as i mentioned, this is no good using while here.
Now thinking about the problem.
Thank you,
Tarek Dakhran
What do you think about this way of solving the problem with races?
Add new edcs_power_controller_wait function.
static void edcs_power_controller_wait(unsigned int cpu, unsigned int
cluster){
unsigned long timeout = jiffies + msecs_to_jiffies(10);
unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
void __iomem *status_reg = EDCS_CORE_STATUS(offset);
/* wait till core power controller finish the work */
do {
if ((readl_relaxed(status_reg) & 3) ==
edcs_use_count[cpu][cluster] ? 3 : 0)
return;
} while (time_before(jiffies, timeout));
/* Should never get here */
BUG();
}
Use it in:
static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
{
exynos_core_power_control(cpu, cluster, true);
edcs_power_controller_wait(cpu, cluster);
}
and in:
static void exynos_power_down(void)
{
bool last_man = false, skip_wfi = false;
unsigned int mpidr = read_cpuid_mpidr();
unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
pr_debug("%s: CORE%d on CLUSTER %d\n", __func__, cpu, cluster);
BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
__mcpm_cpu_going_down(cpu, cluster);
arch_spin_lock(_lock);
BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
edcs_use_count[cpu][cluster]--;
if (edcs_use_count[cpu][cluster] == 0) {
exynos_core_power_down(cpu, cluster);
--core_count[cluster];
if (core_count[cluster] == 0)
last_man = true;
[snip]
__mcpm_cpu_down(cpu, cluster);
if (!skip_wfi){
wfi();
}
edcs_power_controller_wait(cpu, cluster);
}
Comments appreciated. Thanks.
Best regards,
Tarek Dakhran.
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Re: [PATCH v3 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
On 07.11.2013 17:01, Dave Martin wrote:
On Thu, Nov 07, 2013 at 08:12:48AM +, Vyacheslav Tyrtov wrote:
From: Tarek Dakhran
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c | 278 ++
2 files changed, 280 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..ba6efdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..980bfdd
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,278 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#define EDCS_CPUS_PER_CLUSTER 4
+#define EDCS_CLUSTERS 2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION\
+ + ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0(S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr)(REG_CPU_STATE_ADDR0 + \
+(_nr) * EDCS_CPUS_PER_CLUSTER)
+
+#define SECONDARY_RESET(1 << 1)
+#define REG_ENTRY_ADDR (S5P_VA_SYSRAM_NS + 0x1c)
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+ bool enable)
+{
+ unsigned int offset = cluster * MAX_CPUS_PER_CLUSTER + cpu;
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((readl_relaxed(EDCS_CORE_STATUS(offset)) & 0x3) != value) {
I wonder if there is a race here.
If there is a pending powerdown which has reached the __mcpm_cpu_down()
stage, then the kernel has no way to know what is still pending. This
means that when calling exynos_power_up(cpu, cluster) after a successful
call to exynos_power_down(same cpu, cluster), there is a chance that
the CPU still gets powered down, because of the pending
exynos_core_power_control() on the outbound side.
This isn't an issue for TC2, because TC2's power controller queues
requests and services them in order, so a new powerup request cannot
race with a powerdown request in that way.
For exynos5410, it looks like the kernel needs to do that sequencing,
based on my guess about what the EDCS_CORE_STATUS() bits tell us.
I think that for correct behaviour we would need to wait for the race to
be resolved here, but only if a powerdown might be pending.
This implies that something like a call to the power_down_finish()
method (which you would need to write -- see my comments below) is
needed in exynos_core_power_up().
It might make sense to have a per-cpu flag that tracks whether a
powerdown is pending. The flag could be set after
__mcpm_cpu_going_down() is called, and cleared in the powered_up()
method (which you would need to add).
Maybe we should always just poll and wait, though. exynos_power_up()
should never be called for a CPU that the kernel thinks is already up,
so it should either be down already (in which case we will poll the
status once and then continue), or a power down is pending (in which
case we must wait, but we know the wait will terminate). This would
be simpler than tracking a "power down pending" flag for each CPU.
+ wmb();
+ writel_relaxed(value, EDCS_CORE_CONFIGURATION(offset));
+ }
+}
+
+static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, true);
+}
+
+static void exynos_core_power_down(unsigned int cpu,
Re: [PATCH v3 4/4] ARM: dts: Add initial device tree support for EXYNOS5410
Hi,
On 10.11.2013 22:02, Tomasz Figa wrote:
Hi,
Please see my comments inline.
On Thursday 07 of November 2013 12:12:49 Vyacheslav Tyrtov wrote:
From: Tarek Dakhran
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++
arch/arm/boot/dts/exynos5410.dtsi | 209 ++
3 files changed, 275 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
[snip]
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..06ae479
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ oscclk: oscclk {
coding style: According to ePAPR recommendation, node name should
represent hardware type, not particular instance of hardware.
So instead, the preferred way would be to specify the clock using
following layout:
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
oscclk: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <2400>;
clock-output-names = "fin_pll";
};
};
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
[snip]
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..9921b66
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,209 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
[snip]
+ clock: clock-controller@1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+ mct@101C {
A generic name would be: timer@101C
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x101C 0xB00>;
+ interrupt-controller;
+ #interrups-cells = <1>;
MCT is not an interrupt controller, so both interrupt-controller and
#interrupt-cells properties are incorrect. I guess that's due to the
broken example in the documentation, that I already posted patches to fix.
+ interrupt-parent = <_map>;
+ interrupts = <0>, <1>, <2>, <3>,
+ <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>;
+ clocks = <>, < CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+
+ mct_map: mct-map {
Again, interrupt-map would be a better name for this node.
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 23 3>,
+ <1 23 4>,
+ <2 25 2>,
+ <3 25 3>,
+
Re: [PATCH v3 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
0;
} while (time_before(jiffies, timeout));
return -EDEADLK;
}
But, as i mentioned, this is no good using while here.
Now thinking about the problem.
Thank you,
Tarek Dakhran
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