[PATCH] net: eth: altera: Resolve false errors from MSGDMA to TSE

2015-04-24 Thread Vince Bridgers
From: Chee Nouk Phoon 

This patch resolves false errors from MSGDMA in TX mSGDMA MM to ST
mode, and is a continuation of the patch recently submitted by Andrea
Oetken. The MSGDMA had a logic bug that masked detection of this issue
prior to Quartus 14.1/Build 164. When the MSGDMA logic bug was addressed
in Quartus 14.1/Build 164, the driver problem was exposed.

The problem is corrected by making sure MSGDMA_DESC_CTL_TR_ERR_IRQ is not
set for any of the transmit DMA descriptors, and only used for receive
descriptors.

Fixes: 71cd26e altera tse: Error-Bit on tx-avalon-stream always set.

Signed-off-by: Chee Nouk Phoon 
Signed-off-by: Vince Bridgers a
Cc: Andreas Oetken 
---
 drivers/net/ethernet/altera/altera_msgdmahw.h | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_msgdmahw.h 
b/drivers/net/ethernet/altera/altera_msgdmahw.h
index eba070f..89cd11d 100644
--- a/drivers/net/ethernet/altera/altera_msgdmahw.h
+++ b/drivers/net/ethernet/altera/altera_msgdmahw.h
@@ -58,15 +58,12 @@ struct msgdma_extended_desc {
 /* Tx buffer control flags
  */
 #define MSGDMA_DESC_CTL_TX_FIRST   (MSGDMA_DESC_CTL_GEN_SOP |  \
-MSGDMA_DESC_CTL_TR_ERR_IRQ |   \
 MSGDMA_DESC_CTL_GO)
 
-#define MSGDMA_DESC_CTL_TX_MIDDLE  (MSGDMA_DESC_CTL_TR_ERR_IRQ |   \
-MSGDMA_DESC_CTL_GO)
+#define MSGDMA_DESC_CTL_TX_MIDDLE  (MSGDMA_DESC_CTL_GO)
 
 #define MSGDMA_DESC_CTL_TX_LAST(MSGDMA_DESC_CTL_GEN_EOP |  
\
 MSGDMA_DESC_CTL_TR_COMP_IRQ |  \
-MSGDMA_DESC_CTL_TR_ERR_IRQ |   \
 MSGDMA_DESC_CTL_GO)
 
 #define MSGDMA_DESC_CTL_TX_SINGLE  (MSGDMA_DESC_CTL_GEN_SOP |  \
-- 
1.9.1

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[PATCH] net: eth: altera: Resolve false errors from MSGDMA to TSE

2015-04-24 Thread Vince Bridgers
From: Chee Nouk Phoon cnph...@altera.com

This patch resolves false errors from MSGDMA in TX mSGDMA MM to ST
mode, and is a continuation of the patch recently submitted by Andrea
Oetken. The MSGDMA had a logic bug that masked detection of this issue
prior to Quartus 14.1/Build 164. When the MSGDMA logic bug was addressed
in Quartus 14.1/Build 164, the driver problem was exposed.

The problem is corrected by making sure MSGDMA_DESC_CTL_TR_ERR_IRQ is not
set for any of the transmit DMA descriptors, and only used for receive
descriptors.

Fixes: 71cd26e altera tse: Error-Bit on tx-avalon-stream always set.

Signed-off-by: Chee Nouk Phoon cnph...@altera.com
Signed-off-by: Vince Bridgers vbrid...@opensource.altera.coma
Cc: Andreas Oetken ennoerlan...@gmail.com
---
 drivers/net/ethernet/altera/altera_msgdmahw.h | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_msgdmahw.h 
b/drivers/net/ethernet/altera/altera_msgdmahw.h
index eba070f..89cd11d 100644
--- a/drivers/net/ethernet/altera/altera_msgdmahw.h
+++ b/drivers/net/ethernet/altera/altera_msgdmahw.h
@@ -58,15 +58,12 @@ struct msgdma_extended_desc {
 /* Tx buffer control flags
  */
 #define MSGDMA_DESC_CTL_TX_FIRST   (MSGDMA_DESC_CTL_GEN_SOP |  \
-MSGDMA_DESC_CTL_TR_ERR_IRQ |   \
 MSGDMA_DESC_CTL_GO)
 
-#define MSGDMA_DESC_CTL_TX_MIDDLE  (MSGDMA_DESC_CTL_TR_ERR_IRQ |   \
-MSGDMA_DESC_CTL_GO)
+#define MSGDMA_DESC_CTL_TX_MIDDLE  (MSGDMA_DESC_CTL_GO)
 
 #define MSGDMA_DESC_CTL_TX_LAST(MSGDMA_DESC_CTL_GEN_EOP |  
\
 MSGDMA_DESC_CTL_TR_COMP_IRQ |  \
-MSGDMA_DESC_CTL_TR_ERR_IRQ |   \
 MSGDMA_DESC_CTL_GO)
 
 #define MSGDMA_DESC_CTL_TX_SINGLE  (MSGDMA_DESC_CTL_GEN_SOP |  \
-- 
1.9.1

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[PATCH 2/2] ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties

2015-04-20 Thread Vince Bridgers
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga
stmmac. These devicetree properties will be used to configure certain
features of the stmmac on the socfpga.

Signed-off-by: Vince Bridgers 
---
This patch is based on patches
http://www.spinics.net/lists/devicetree/msg75270.html
http://www.spinics.net/lists/devicetree/msg75273.html
---
 arch/arm/boot/dts/socfpga.dtsi | 4 
 arch/arm/boot/dts/socfpga_arria10.dtsi | 6 ++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index d9176e6..4721a9d 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -488,6 +488,8 @@
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+   tx-fifo-depth = <4096>;
+   rx-fifo-depth = <4096>;
status = "disabled";
};
 
@@ -504,6 +506,8 @@
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+   tx-fifo-depth = <4096>;
+   rx-fifo-depth = <4096>;
status = "disabled";
};
 
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index d2ef52b..9c6dcff 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -397,6 +397,8 @@
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+   tx-fifo-depth = <4096>;
+   rx-fifo-depth = <16384>;
clocks = <_mp_clk>;
clock-names = "stmmaceth";
status = "disabled";
@@ -412,6 +414,8 @@
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+   tx-fifo-depth = <4096>;
+   rx-fifo-depth = <16384>;
status = "disabled";
};
 
@@ -425,6 +429,8 @@
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+   tx-fifo-depth = <4096>;
+   rx-fifo-depth = <16384>;
status = "disabled";
};
 
-- 
1.9.1

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[PATCH 1/2] ARM: socfpga: dts: Add multicast bins and unicast filter entries

2015-04-20 Thread Vince Bridgers
Add multicast-filter-bins and perfect-filter-entries configuration properties
to the socfpga devicetree for the Arria 10 socfpga.

Signed-off-by: Vince Bridgers 
---
This patch is based on patches
http://www.spinics.net/lists/devicetree/msg75270.html
http://www.spinics.net/lists/devicetree/msg75273.html
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index e121661..d2ef52b 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -395,6 +395,8 @@
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
+   snps,multicast-filter-bins = <256>;
+   snps,perfect-filter-entries = <128>;
clocks = <_mp_clk>;
clock-names = "stmmaceth";
status = "disabled";
@@ -408,6 +410,8 @@
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
+   snps,multicast-filter-bins = <256>;
+   snps,perfect-filter-entries = <128>;
status = "disabled";
};
 
@@ -419,6 +423,8 @@
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
+   snps,multicast-filter-bins = <256>;
+   snps,perfect-filter-entries = <128>;
status = "disabled";
};
 
-- 
1.9.1

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[PATCH 1/2] ARM: socfpga: dts: Add multicast bins and unicast filter entries

2015-04-20 Thread Vince Bridgers
Add multicast-filter-bins and perfect-filter-entries configuration properties
to the socfpga devicetree for the Arria 10 socfpga.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
This patch is based on patches
http://www.spinics.net/lists/devicetree/msg75270.html
http://www.spinics.net/lists/devicetree/msg75273.html
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index e121661..d2ef52b 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -395,6 +395,8 @@
interrupt-names = macirq;
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
+   snps,multicast-filter-bins = 256;
+   snps,perfect-filter-entries = 128;
clocks = l4_mp_clk;
clock-names = stmmaceth;
status = disabled;
@@ -408,6 +410,8 @@
interrupt-names = macirq;
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
+   snps,multicast-filter-bins = 256;
+   snps,perfect-filter-entries = 128;
status = disabled;
};
 
@@ -419,6 +423,8 @@
interrupt-names = macirq;
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
+   snps,multicast-filter-bins = 256;
+   snps,perfect-filter-entries = 128;
status = disabled;
};
 
-- 
1.9.1

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[PATCH 2/2] ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties

2015-04-20 Thread Vince Bridgers
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga
stmmac. These devicetree properties will be used to configure certain
features of the stmmac on the socfpga.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
This patch is based on patches
http://www.spinics.net/lists/devicetree/msg75270.html
http://www.spinics.net/lists/devicetree/msg75273.html
---
 arch/arm/boot/dts/socfpga.dtsi | 4 
 arch/arm/boot/dts/socfpga_arria10.dtsi | 6 ++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index d9176e6..4721a9d 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -488,6 +488,8 @@
reset-names = stmmaceth;
snps,multicast-filter-bins = 256;
snps,perfect-filter-entries = 128;
+   tx-fifo-depth = 4096;
+   rx-fifo-depth = 4096;
status = disabled;
};
 
@@ -504,6 +506,8 @@
reset-names = stmmaceth;
snps,multicast-filter-bins = 256;
snps,perfect-filter-entries = 128;
+   tx-fifo-depth = 4096;
+   rx-fifo-depth = 4096;
status = disabled;
};
 
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index d2ef52b..9c6dcff 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -397,6 +397,8 @@
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = 256;
snps,perfect-filter-entries = 128;
+   tx-fifo-depth = 4096;
+   rx-fifo-depth = 16384;
clocks = l4_mp_clk;
clock-names = stmmaceth;
status = disabled;
@@ -412,6 +414,8 @@
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = 256;
snps,perfect-filter-entries = 128;
+   tx-fifo-depth = 4096;
+   rx-fifo-depth = 16384;
status = disabled;
};
 
@@ -425,6 +429,8 @@
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = 256;
snps,perfect-filter-entries = 128;
+   tx-fifo-depth = 4096;
+   rx-fifo-depth = 16384;
status = disabled;
};
 
-- 
1.9.1

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[PATCH net 2/5] stmmac: Add defines and documentation for enabling flow control

2015-04-15 Thread Vince Bridgers
Add defines and documentation for enabling flow control on the stmmac. Flow
control was not implemented correctly on the stmmac driver and is currently
non-functional as a result. This is the first in a series of small patches
to correctly implement this feature.

Signed-off-by: Vince Bridgers 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 51 +
 1 file changed, 51 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h 
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
index 64d8f56..b3fe057 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
@@ -172,6 +172,7 @@ enum inter_frame_gap {
 /* GMAC FLOW CTRL defines */
 #define GMAC_FLOW_CTRL_PT_MASK 0x  /* Pause Time Mask */
 #define GMAC_FLOW_CTRL_PT_SHIFT16
+#define GMAC_FLOW_CTRL_UP  0x0008  /* Unicast pause frame enable */
 #define GMAC_FLOW_CTRL_RFE 0x0004  /* Rx Flow Control Enable */
 #define GMAC_FLOW_CTRL_TFE 0x0002  /* Tx Flow Control Enable */
 #define GMAC_FLOW_CTRL_FCB_BPA 0x0001  /* Flow Control Busy ... */
@@ -246,6 +247,56 @@ enum ttc_control {
 #define DMA_CONTROL_FEF0x0080
 #define DMA_CONTROL_FUF0x0040
 
+/* Receive flow control activation field
+ * RFA field in DMA control register, bits 23,10:9
+ */
+#define DMA_CONTROL_RFA_MASK   0x00800600
+
+/* Receive flow control deactivation field
+ * RFD field in DMA control register, bits 22,12:11
+ */
+#define DMA_CONTROL_RFD_MASK   0x00401800
+
+/* RFD and RFA fields are encoded as follows
+ *
+ *   Bit Field
+ *   0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
+ *   0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
+ *   0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
+ *   0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
+ *   1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
+ *   1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
+ *   1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
+ *   1,11 - Reserved
+ *
+ * RFD should always be > RFA for a given FIFO size. RFD == RFA may work,
+ * but packet throughput performance may not be as expected.
+ *
+ * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame
+ * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause
+ * Description).
+ *
+ * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),
+ * is set to 0. This allows pause frames with a quanta of 0 to be sent
+ * as an XOFF message to the link peer.
+ */
+
+#define RFA_FULL_MINUS_1K  0x
+#define RFA_FULL_MINUS_2K  0x0200
+#define RFA_FULL_MINUS_3K  0x0400
+#define RFA_FULL_MINUS_4K  0x0600
+#define RFA_FULL_MINUS_5K  0x0080
+#define RFA_FULL_MINUS_6K  0x00800200
+#define RFA_FULL_MINUS_7K  0x00800400
+
+#define RFD_FULL_MINUS_1K  0x
+#define RFD_FULL_MINUS_2K  0x0800
+#define RFD_FULL_MINUS_3K  0x1000
+#define RFD_FULL_MINUS_4K  0x1800
+#define RFD_FULL_MINUS_5K  0x0040
+#define RFD_FULL_MINUS_6K  0x00400800
+#define RFD_FULL_MINUS_7K  0x00401000
+
 enum rtc_control {
DMA_CONTROL_RTC_64 = 0x,
DMA_CONTROL_RTC_32 = 0x0008,
-- 
1.9.1

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[PATCH net 1/5] stmmac: Add properties for transmit and receive fifo sizes

2015-04-15 Thread Vince Bridgers
The Synopsys stmmac fifo sizes are configurable, and need to be known
in order to configure certain controller features. This patch adds
tx-fifo-depth and rx-fifo-depth properties to the stmmac document
file.

Signed-off-by: Vince Bridgers 
---
 Documentation/devicetree/bindings/net/ethernet.txt | 6 ++
 Documentation/devicetree/bindings/net/stmmac.txt   | 4 
 2 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/ethernet.txt 
b/Documentation/devicetree/bindings/net/ethernet.txt
index 3fc3605..41b3f3f 100644
--- a/Documentation/devicetree/bindings/net/ethernet.txt
+++ b/Documentation/devicetree/bindings/net/ethernet.txt
@@ -19,6 +19,12 @@ The following properties are common to the Ethernet 
controllers:
 - phy: the same as "phy-handle" property, not recommended for new bindings.
 - phy-device: the same as "phy-handle" property, not recommended for new
   bindings.
+- rx-fifo-depth: the size of the controller's receive fifo in bytes. This
+  is used for components that can have configurable receive fifo sizes,
+  and is useful for determining certain configuration settings such as
+  flow control thresholds.
+- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
+  is used for components that can have configurable fifo sizes.
 
 Child nodes of the Ethernet controller are typically the individual PHY devices
 connected via the MDIO bus (sometimes the MDIO bus controller is separate).
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt 
b/Documentation/devicetree/bindings/net/stmmac.txt
index 8ca65ce..524c185 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -44,6 +44,8 @@ Optional properties:
   If not passed then the system clock will be used and this is fine on some
   platforms.
 - snps,burst_len: The AXI burst lenth value of the AXI BUS MODE register.
+- tx-fifo-depth: See ethernet.txt file in the same directory
+- rx-fifo-depth: See ethernet.txt file in the same directory
 
 Examples:
 
@@ -58,6 +60,8 @@ Examples:
phy-mode = "gmii";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+   rx-fifo-depth = <16384>;
+   tx-fifo-depth = <16384>;
clocks = <>;
clock-names = "stmmaceth";
};
-- 
1.9.1

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[PATCH net 4/5] stmmac: Enable unicast pause frame detect in GMAC Register 6

2015-04-15 Thread Vince Bridgers
Unicast pause frame detect was not being enabled for the Synopsys stmmac. This
patch sets Unicast pause frame detect in MAC register 6 so that pause frame
detection by the stmmac conforms to IEEE 802.3, Annex 31B.3.3 Receive
Operation - Specifically, a MAC shall respond to pause frames containing
either the reserved multicast address or the unique physical address
associated with this station.

Signed-off-by: Vince Bridgers 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index 0adcf73..371a669 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -201,7 +201,10 @@ static void dwmac1000_flow_ctrl(struct mac_device_info 
*hw, unsigned int duplex,
unsigned int fc, unsigned int pause_time)
 {
void __iomem *ioaddr = hw->pcsr;
-   unsigned int flow = 0;
+   /* Set flow such that DZPQ in Mac Register 6 is 0,
+* and unicast pause detect is enabled.
+*/
+   unsigned int flow = GMAC_FLOW_CTRL_UP;
 
pr_debug("GMAC Flow-Control:\n");
if (fc & FLOW_RX) {
-- 
1.9.1

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[PATCH net 5/5] stmmac: Configure Flow Control to work correctly based on rxfifo size

2015-04-15 Thread Vince Bridgers
Configure flow control correctly, and based on the receive fifo size read
as a property from the devicetree since the Synopsys stmmac fifo sizes are
configurable based on a particular chip's implementation. This patch maintains
the previous incorrect behavior unless the receive fifo size is found in the
devicetree.

Signed-off-by: Vince Bridgers 
---
 drivers/net/ethernet/stmicro/stmmac/common.h   |  5 +++--
 .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c| 26 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c |  2 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 16 -
 4 files changed, 40 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h 
b/drivers/net/ethernet/stmicro/stmmac/common.h
index cd77289..623c6ed 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -150,7 +150,7 @@ struct stmmac_extra_stats {
 #defineMAC_CSR_H_FRQ_MASK  0x20
 
 #define HASH_TABLE_SIZE 64
-#define PAUSE_TIME 0x200
+#define PAUSE_TIME 0x
 
 /* Flow Control defines */
 #define FLOW_OFF   0
@@ -357,7 +357,8 @@ struct stmmac_dma_ops {
void (*dump_regs) (void __iomem *ioaddr);
/* Set tx/rx threshold in the csr6 register
 * An invalid value enables the store-and-forward mode */
-   void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
+   void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
+int rxfifosz);
/* To track extra statistic (if supported) */
void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
   void __iomem *ioaddr);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index 59d92e8..0e8937c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -106,8 +106,29 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int 
pbl, int fb, int mb,
return 0;
 }
 
+static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
+{
+   csr6 &= ~DMA_CONTROL_RFA_MASK;
+   csr6 &= ~DMA_CONTROL_RFD_MASK;
+
+   /* Leave flow control disabled if receive fifo size is less than
+* 4K or 0. Otherwise, send XOFF when fifo is 1K less than full,
+* and send XON when 2K less than full.
+*/
+   if (rxfifosz < 4096) {
+   csr6 &= ~DMA_CONTROL_EFC;
+   pr_debug("GMAC: disabling flow control, rxfifo too small(%d)\n",
+rxfifosz);
+   } else {
+   csr6 |= DMA_CONTROL_EFC;
+   csr6 |= RFA_FULL_MINUS_1K;
+   csr6 |= RFD_FULL_MINUS_2K;
+   }
+   return csr6;
+}
+
 static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
-int rxmode)
+int rxmode, int rxfifosz)
 {
u32 csr6 = readl(ioaddr + DMA_CONTROL);
 
@@ -153,6 +174,9 @@ static void dwmac1000_dma_operation_mode(void __iomem 
*ioaddr, int txmode,
csr6 |= DMA_CONTROL_RTC_128;
}
 
+   /* Configure flow control based on rx fifo size */
+   csr6 = dwmac1000_configure_fc(csr6, rxfifosz);
+
writel(csr6, ioaddr + DMA_CONTROL);
 }
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
index 7d1dce9..9d0971c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
@@ -72,7 +72,7 @@ static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, 
int fb, int mb,
  * control register.
  */
 static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode,
-   int rxmode)
+   int rxmode, int rxfifosz)
 {
u32 csr6 = readl(ioaddr + DMA_CONTROL);
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index a0ea84f..73d104f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1277,8 +1277,10 @@ static void free_dma_desc_resources(struct stmmac_priv 
*priv)
  */
 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 {
+   int rxfifosz = priv->plat->rx_fifo_size;
+
if (priv->plat->force_thresh_dma_mode)
-   priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
+   priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
/*
 * In case of GMAC, SF mode can be enabled
@@ -1287,10 +1289,12 @@ static void stmmac_dma_operation_mode(struct 
stmmac

[PATCH net 3/5] stmmac: Read tx-fifo-depth and rx-fifo-depth from the devicetree

2015-04-15 Thread Vince Bridgers
Read the tx-fifo-depth and rx-fifo-depth from the devicetree. The Synopsys
stmmac controller fifos are configurable per product instance, and the fifo
sizes are needed to configure certain features correctly such as flow control.

Signed-off-by: Vince Bridgers 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 
 include/linux/stmmac.h| 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index f9b42f1..705bbdf 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -181,6 +181,10 @@ static int stmmac_probe_config_dt(struct platform_device 
*pdev,
 sizeof(struct stmmac_mdio_bus_data),
 GFP_KERNEL);
 
+   of_property_read_u32(np, "tx-fifo-depth", >tx_fifo_size);
+
+   of_property_read_u32(np, "rx-fifo-depth", >rx_fifo_size);
+
plat->force_sf_dma_mode =
of_property_read_bool(np, "snps,force_sf_dma_mode");
 
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index cd63851..7f484a2 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -114,6 +114,8 @@ struct plat_stmmacenet_data {
int maxmtu;
int multicast_filter_bins;
int unicast_filter_entries;
+   int tx_fifo_size;
+   int rx_fifo_size;
void (*fix_mac_speed)(void *priv, unsigned int speed);
void (*bus_setup)(void __iomem *ioaddr);
void *(*setup)(struct platform_device *pdev);
-- 
1.9.1

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[PATCH net 0/5] stmmac: Correct flow control configuration

2015-04-15 Thread Vince Bridgers
This series of patches corrects flow control configuration for the Synopsys
GMAC driver.

Flow control is configured based on a configurable receive fifo size. If
less than 4Kbytes flow control is left disabled and a warning is presented. If
a receive fifo size is not specified, flow control is left disabled to
maintain current behavior. Unicast pause detection was disabled, but is now 
enabled. The pause time was modified to be maximum time per a XON/XOFF
flow control mode of operation.

This patch was tested on an Altera Cyclone 5 and an Altera Arria 10 devkit,
and verified that flow control operates as expected when enabled.

Please consider this series for inclusion so that flow control will
function as expected for the Synopsys GMAC controller. 

Vince Bridgers (5):
  stmmac: Add properties for transmit and receive fifo sizes
  stmmac: Add defines and documentation for enabling flow control
  stmmac: Read tx-fifo-depth and rx-fifo-depth from the devicetree
  stmmac: Enable unicast pause frame detect in GMAC Register 6
  stmmac: Configure Flow Control to work correctly based on rxfifo size

 Documentation/devicetree/bindings/net/ethernet.txt |  6 +++
 Documentation/devicetree/bindings/net/stmmac.txt   |  4 ++
 drivers/net/ethernet/stmicro/stmmac/common.h   |  5 ++-
 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h| 51 ++
 .../net/ethernet/stmicro/stmmac/dwmac1000_core.c   |  5 ++-
 .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c| 26 ++-
 drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c |  2 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 16 ---
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |  4 ++
 include/linux/stmmac.h |  2 +
 10 files changed, 111 insertions(+), 10 deletions(-)

-- 
1.9.1

--
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[PATCH net 0/5] stmmac: Correct flow control configuration

2015-04-15 Thread Vince Bridgers
This series of patches corrects flow control configuration for the Synopsys
GMAC driver.

Flow control is configured based on a configurable receive fifo size. If
less than 4Kbytes flow control is left disabled and a warning is presented. If
a receive fifo size is not specified, flow control is left disabled to
maintain current behavior. Unicast pause detection was disabled, but is now 
enabled. The pause time was modified to be maximum time per a XON/XOFF
flow control mode of operation.

This patch was tested on an Altera Cyclone 5 and an Altera Arria 10 devkit,
and verified that flow control operates as expected when enabled.

Please consider this series for inclusion so that flow control will
function as expected for the Synopsys GMAC controller. 

Vince Bridgers (5):
  stmmac: Add properties for transmit and receive fifo sizes
  stmmac: Add defines and documentation for enabling flow control
  stmmac: Read tx-fifo-depth and rx-fifo-depth from the devicetree
  stmmac: Enable unicast pause frame detect in GMAC Register 6
  stmmac: Configure Flow Control to work correctly based on rxfifo size

 Documentation/devicetree/bindings/net/ethernet.txt |  6 +++
 Documentation/devicetree/bindings/net/stmmac.txt   |  4 ++
 drivers/net/ethernet/stmicro/stmmac/common.h   |  5 ++-
 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h| 51 ++
 .../net/ethernet/stmicro/stmmac/dwmac1000_core.c   |  5 ++-
 .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c| 26 ++-
 drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c |  2 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 16 ---
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |  4 ++
 include/linux/stmmac.h |  2 +
 10 files changed, 111 insertions(+), 10 deletions(-)

-- 
1.9.1

--
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Please read the FAQ at  http://www.tux.org/lkml/


[PATCH net 3/5] stmmac: Read tx-fifo-depth and rx-fifo-depth from the devicetree

2015-04-15 Thread Vince Bridgers
Read the tx-fifo-depth and rx-fifo-depth from the devicetree. The Synopsys
stmmac controller fifos are configurable per product instance, and the fifo
sizes are needed to configure certain features correctly such as flow control.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 
 include/linux/stmmac.h| 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index f9b42f1..705bbdf 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -181,6 +181,10 @@ static int stmmac_probe_config_dt(struct platform_device 
*pdev,
 sizeof(struct stmmac_mdio_bus_data),
 GFP_KERNEL);
 
+   of_property_read_u32(np, tx-fifo-depth, plat-tx_fifo_size);
+
+   of_property_read_u32(np, rx-fifo-depth, plat-rx_fifo_size);
+
plat-force_sf_dma_mode =
of_property_read_bool(np, snps,force_sf_dma_mode);
 
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index cd63851..7f484a2 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -114,6 +114,8 @@ struct plat_stmmacenet_data {
int maxmtu;
int multicast_filter_bins;
int unicast_filter_entries;
+   int tx_fifo_size;
+   int rx_fifo_size;
void (*fix_mac_speed)(void *priv, unsigned int speed);
void (*bus_setup)(void __iomem *ioaddr);
void *(*setup)(struct platform_device *pdev);
-- 
1.9.1

--
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Please read the FAQ at  http://www.tux.org/lkml/


[PATCH net 5/5] stmmac: Configure Flow Control to work correctly based on rxfifo size

2015-04-15 Thread Vince Bridgers
Configure flow control correctly, and based on the receive fifo size read
as a property from the devicetree since the Synopsys stmmac fifo sizes are
configurable based on a particular chip's implementation. This patch maintains
the previous incorrect behavior unless the receive fifo size is found in the
devicetree.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 drivers/net/ethernet/stmicro/stmmac/common.h   |  5 +++--
 .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c| 26 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c |  2 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 16 -
 4 files changed, 40 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h 
b/drivers/net/ethernet/stmicro/stmmac/common.h
index cd77289..623c6ed 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -150,7 +150,7 @@ struct stmmac_extra_stats {
 #defineMAC_CSR_H_FRQ_MASK  0x20
 
 #define HASH_TABLE_SIZE 64
-#define PAUSE_TIME 0x200
+#define PAUSE_TIME 0x
 
 /* Flow Control defines */
 #define FLOW_OFF   0
@@ -357,7 +357,8 @@ struct stmmac_dma_ops {
void (*dump_regs) (void __iomem *ioaddr);
/* Set tx/rx threshold in the csr6 register
 * An invalid value enables the store-and-forward mode */
-   void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
+   void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
+int rxfifosz);
/* To track extra statistic (if supported) */
void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
   void __iomem *ioaddr);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index 59d92e8..0e8937c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -106,8 +106,29 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int 
pbl, int fb, int mb,
return 0;
 }
 
+static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
+{
+   csr6 = ~DMA_CONTROL_RFA_MASK;
+   csr6 = ~DMA_CONTROL_RFD_MASK;
+
+   /* Leave flow control disabled if receive fifo size is less than
+* 4K or 0. Otherwise, send XOFF when fifo is 1K less than full,
+* and send XON when 2K less than full.
+*/
+   if (rxfifosz  4096) {
+   csr6 = ~DMA_CONTROL_EFC;
+   pr_debug(GMAC: disabling flow control, rxfifo too small(%d)\n,
+rxfifosz);
+   } else {
+   csr6 |= DMA_CONTROL_EFC;
+   csr6 |= RFA_FULL_MINUS_1K;
+   csr6 |= RFD_FULL_MINUS_2K;
+   }
+   return csr6;
+}
+
 static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
-int rxmode)
+int rxmode, int rxfifosz)
 {
u32 csr6 = readl(ioaddr + DMA_CONTROL);
 
@@ -153,6 +174,9 @@ static void dwmac1000_dma_operation_mode(void __iomem 
*ioaddr, int txmode,
csr6 |= DMA_CONTROL_RTC_128;
}
 
+   /* Configure flow control based on rx fifo size */
+   csr6 = dwmac1000_configure_fc(csr6, rxfifosz);
+
writel(csr6, ioaddr + DMA_CONTROL);
 }
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
index 7d1dce9..9d0971c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
@@ -72,7 +72,7 @@ static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, 
int fb, int mb,
  * control register.
  */
 static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode,
-   int rxmode)
+   int rxmode, int rxfifosz)
 {
u32 csr6 = readl(ioaddr + DMA_CONTROL);
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index a0ea84f..73d104f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1277,8 +1277,10 @@ static void free_dma_desc_resources(struct stmmac_priv 
*priv)
  */
 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 {
+   int rxfifosz = priv-plat-rx_fifo_size;
+
if (priv-plat-force_thresh_dma_mode)
-   priv-hw-dma-dma_mode(priv-ioaddr, tc, tc);
+   priv-hw-dma-dma_mode(priv-ioaddr, tc, tc, rxfifosz);
else if (priv-plat-force_sf_dma_mode || priv-plat-tx_coe) {
/*
 * In case of GMAC, SF mode can be enabled
@@ -1287,10 +1289,12 @@ static void stmmac_dma_operation_mode(struct 
stmmac_priv *priv)
 * 2) There is no bugged Jumbo frame

[PATCH net 4/5] stmmac: Enable unicast pause frame detect in GMAC Register 6

2015-04-15 Thread Vince Bridgers
Unicast pause frame detect was not being enabled for the Synopsys stmmac. This
patch sets Unicast pause frame detect in MAC register 6 so that pause frame
detection by the stmmac conforms to IEEE 802.3, Annex 31B.3.3 Receive
Operation - Specifically, a MAC shall respond to pause frames containing
either the reserved multicast address or the unique physical address
associated with this station.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index 0adcf73..371a669 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -201,7 +201,10 @@ static void dwmac1000_flow_ctrl(struct mac_device_info 
*hw, unsigned int duplex,
unsigned int fc, unsigned int pause_time)
 {
void __iomem *ioaddr = hw-pcsr;
-   unsigned int flow = 0;
+   /* Set flow such that DZPQ in Mac Register 6 is 0,
+* and unicast pause detect is enabled.
+*/
+   unsigned int flow = GMAC_FLOW_CTRL_UP;
 
pr_debug(GMAC Flow-Control:\n);
if (fc  FLOW_RX) {
-- 
1.9.1

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[PATCH net 2/5] stmmac: Add defines and documentation for enabling flow control

2015-04-15 Thread Vince Bridgers
Add defines and documentation for enabling flow control on the stmmac. Flow
control was not implemented correctly on the stmmac driver and is currently
non-functional as a result. This is the first in a series of small patches
to correctly implement this feature.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 51 +
 1 file changed, 51 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h 
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
index 64d8f56..b3fe057 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
@@ -172,6 +172,7 @@ enum inter_frame_gap {
 /* GMAC FLOW CTRL defines */
 #define GMAC_FLOW_CTRL_PT_MASK 0x  /* Pause Time Mask */
 #define GMAC_FLOW_CTRL_PT_SHIFT16
+#define GMAC_FLOW_CTRL_UP  0x0008  /* Unicast pause frame enable */
 #define GMAC_FLOW_CTRL_RFE 0x0004  /* Rx Flow Control Enable */
 #define GMAC_FLOW_CTRL_TFE 0x0002  /* Tx Flow Control Enable */
 #define GMAC_FLOW_CTRL_FCB_BPA 0x0001  /* Flow Control Busy ... */
@@ -246,6 +247,56 @@ enum ttc_control {
 #define DMA_CONTROL_FEF0x0080
 #define DMA_CONTROL_FUF0x0040
 
+/* Receive flow control activation field
+ * RFA field in DMA control register, bits 23,10:9
+ */
+#define DMA_CONTROL_RFA_MASK   0x00800600
+
+/* Receive flow control deactivation field
+ * RFD field in DMA control register, bits 22,12:11
+ */
+#define DMA_CONTROL_RFD_MASK   0x00401800
+
+/* RFD and RFA fields are encoded as follows
+ *
+ *   Bit Field
+ *   0,00 - Full minus 1KB (only valid when rxfifo = 4KB and EFC enabled)
+ *   0,01 - Full minus 2KB (only valid when rxfifo = 4KB and EFC enabled)
+ *   0,10 - Full minus 3KB (only valid when rxfifo = 4KB and EFC enabled)
+ *   0,11 - Full minus 4KB (only valid when rxfifo  4KB and EFC enabled)
+ *   1,00 - Full minus 5KB (only valid when rxfifo  8KB and EFC enabled)
+ *   1,01 - Full minus 6KB (only valid when rxfifo  8KB and EFC enabled)
+ *   1,10 - Full minus 7KB (only valid when rxfifo  8KB and EFC enabled)
+ *   1,11 - Reserved
+ *
+ * RFD should always be  RFA for a given FIFO size. RFD == RFA may work,
+ * but packet throughput performance may not be as expected.
+ *
+ * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame
+ * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause
+ * Description).
+ *
+ * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),
+ * is set to 0. This allows pause frames with a quanta of 0 to be sent
+ * as an XOFF message to the link peer.
+ */
+
+#define RFA_FULL_MINUS_1K  0x
+#define RFA_FULL_MINUS_2K  0x0200
+#define RFA_FULL_MINUS_3K  0x0400
+#define RFA_FULL_MINUS_4K  0x0600
+#define RFA_FULL_MINUS_5K  0x0080
+#define RFA_FULL_MINUS_6K  0x00800200
+#define RFA_FULL_MINUS_7K  0x00800400
+
+#define RFD_FULL_MINUS_1K  0x
+#define RFD_FULL_MINUS_2K  0x0800
+#define RFD_FULL_MINUS_3K  0x1000
+#define RFD_FULL_MINUS_4K  0x1800
+#define RFD_FULL_MINUS_5K  0x0040
+#define RFD_FULL_MINUS_6K  0x00400800
+#define RFD_FULL_MINUS_7K  0x00401000
+
 enum rtc_control {
DMA_CONTROL_RTC_64 = 0x,
DMA_CONTROL_RTC_32 = 0x0008,
-- 
1.9.1

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[PATCH net 1/5] stmmac: Add properties for transmit and receive fifo sizes

2015-04-15 Thread Vince Bridgers
The Synopsys stmmac fifo sizes are configurable, and need to be known
in order to configure certain controller features. This patch adds
tx-fifo-depth and rx-fifo-depth properties to the stmmac document
file.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 Documentation/devicetree/bindings/net/ethernet.txt | 6 ++
 Documentation/devicetree/bindings/net/stmmac.txt   | 4 
 2 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/ethernet.txt 
b/Documentation/devicetree/bindings/net/ethernet.txt
index 3fc3605..41b3f3f 100644
--- a/Documentation/devicetree/bindings/net/ethernet.txt
+++ b/Documentation/devicetree/bindings/net/ethernet.txt
@@ -19,6 +19,12 @@ The following properties are common to the Ethernet 
controllers:
 - phy: the same as phy-handle property, not recommended for new bindings.
 - phy-device: the same as phy-handle property, not recommended for new
   bindings.
+- rx-fifo-depth: the size of the controller's receive fifo in bytes. This
+  is used for components that can have configurable receive fifo sizes,
+  and is useful for determining certain configuration settings such as
+  flow control thresholds.
+- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
+  is used for components that can have configurable fifo sizes.
 
 Child nodes of the Ethernet controller are typically the individual PHY devices
 connected via the MDIO bus (sometimes the MDIO bus controller is separate).
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt 
b/Documentation/devicetree/bindings/net/stmmac.txt
index 8ca65ce..524c185 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -44,6 +44,8 @@ Optional properties:
   If not passed then the system clock will be used and this is fine on some
   platforms.
 - snps,burst_len: The AXI burst lenth value of the AXI BUS MODE register.
+- tx-fifo-depth: See ethernet.txt file in the same directory
+- rx-fifo-depth: See ethernet.txt file in the same directory
 
 Examples:
 
@@ -58,6 +60,8 @@ Examples:
phy-mode = gmii;
snps,multicast-filter-bins = 256;
snps,perfect-filter-entries = 128;
+   rx-fifo-depth = 16384;
+   tx-fifo-depth = 16384;
clocks = clock;
clock-names = stmmaceth;
};
-- 
1.9.1

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[PATCH net-next] altera_tse: Fixes in NAPI and interrupt handling paths

2015-02-23 Thread Vince Bridgers
From: Vlastimil Setka 

Incorrect NAPI polling caused WARNING at net/core/dev.c net_rx_action.
Some stability issues were also seen at high throughput and system
load before this patch.

This patch contains several changes in altera_tse_main.c:

- tse_rx() is fixed to not process more than `limit` frames

- tse_poll() is refactored to match NAPI logic
  - only received frames are counted for return value
  - removed bogus condition `(rxcomplete >= budget || txcomplete > 0)`
  - replace by: if (rxcomplete < budget) -> call __napi_complete and enable irq

- altera_isr()
  - replace spin_lock_irqsave() by spin_lock() - we are in isr
  - use spinlocks just over irq manipulation, not over __napi_schedule
  - reset IRQ first, then disable and schedule napi

This is a cleaned up resubmission from Vlastimil's recent submission.

Signed-off-by: Vlastimil Setka 
Signed-off-by: Roman Pisl 
Signed-off-by: Vince Bridgers 
---
 drivers/net/ethernet/altera/altera_tse_main.c | 45 +--
 1 file changed, 22 insertions(+), 23 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_tse_main.c 
b/drivers/net/ethernet/altera/altera_tse_main.c
index 91ad435..fd9296a 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -376,7 +376,8 @@ static int tse_rx(struct altera_tse_private *priv, int 
limit)
u16 pktlength;
u16 pktstatus;
 
-   while ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0) {
+   while (((rxstatus = priv->dmaops->get_rx_status(priv)) != 0) &&
+  (count < limit))  {
pktstatus = rxstatus >> 16;
pktlength = rxstatus & 0x;
 
@@ -491,28 +492,27 @@ static int tse_poll(struct napi_struct *napi, int budget)
struct altera_tse_private *priv =
container_of(napi, struct altera_tse_private, napi);
int rxcomplete = 0;
-   int txcomplete = 0;
unsigned long int flags;
 
-   txcomplete = tse_tx_complete(priv);
+   tse_tx_complete(priv);
 
rxcomplete = tse_rx(priv, budget);
 
-   if (rxcomplete >= budget || txcomplete > 0)
-   return rxcomplete;
+   if (rxcomplete < budget) {
 
-   napi_gro_flush(napi, false);
-   __napi_complete(napi);
+   napi_gro_flush(napi, false);
+   __napi_complete(napi);
 
-   netdev_dbg(priv->dev,
-  "NAPI Complete, did %d packets with budget %d\n",
-  txcomplete+rxcomplete, budget);
+   netdev_dbg(priv->dev,
+  "NAPI Complete, did %d packets with budget %d\n",
+  rxcomplete, budget);
 
-   spin_lock_irqsave(>rxdma_irq_lock, flags);
-   priv->dmaops->enable_rxirq(priv);
-   priv->dmaops->enable_txirq(priv);
-   spin_unlock_irqrestore(>rxdma_irq_lock, flags);
-   return rxcomplete + txcomplete;
+   spin_lock_irqsave(>rxdma_irq_lock, flags);
+   priv->dmaops->enable_rxirq(priv);
+   priv->dmaops->enable_txirq(priv);
+   spin_unlock_irqrestore(>rxdma_irq_lock, flags);
+   }
+   return rxcomplete;
 }
 
 /* DMA TX & RX FIFO interrupt routing
@@ -521,7 +521,6 @@ static irqreturn_t altera_isr(int irq, void *dev_id)
 {
struct net_device *dev = dev_id;
struct altera_tse_private *priv;
-   unsigned long int flags;
 
if (unlikely(!dev)) {
pr_err("%s: invalid dev pointer\n", __func__);
@@ -529,20 +528,20 @@ static irqreturn_t altera_isr(int irq, void *dev_id)
}
priv = netdev_priv(dev);
 
-   /* turn off desc irqs and enable napi rx */
-   spin_lock_irqsave(>rxdma_irq_lock, flags);
+   spin_lock(>rxdma_irq_lock);
+   /* reset IRQs */
+   priv->dmaops->clear_rxirq(priv);
+   priv->dmaops->clear_txirq(priv);
+   spin_unlock(>rxdma_irq_lock);
 
if (likely(napi_schedule_prep(>napi))) {
+   spin_lock(>rxdma_irq_lock);
priv->dmaops->disable_rxirq(priv);
priv->dmaops->disable_txirq(priv);
+   spin_unlock(>rxdma_irq_lock);
__napi_schedule(>napi);
}
 
-   /* reset IRQs */
-   priv->dmaops->clear_rxirq(priv);
-   priv->dmaops->clear_txirq(priv);
-
-   spin_unlock_irqrestore(>rxdma_irq_lock, flags);
 
return IRQ_HANDLED;
 }
-- 
1.9.1

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[PATCH net-next] altera_tse: Correct typo in obtaining tx_fifo_depth from devicetree

2015-02-23 Thread Vince Bridgers
From: Vlastimil Setka 

This patch corrects a typo in the way tx_fifo_depth is read from the
devicetree. This patch was submitted by Vlastimil about a week ago,
and is now cleaned up and resubmitted.

Signed-off-by: Vlastimil Setka 
Signed-off-by: Vince Bridgers 
---
 drivers/net/ethernet/altera/altera_tse_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/altera/altera_tse_main.c 
b/drivers/net/ethernet/altera/altera_tse_main.c
index a1ee261..91ad435 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -1407,7 +1407,7 @@ static int altera_tse_probe(struct platform_device *pdev)
}
 
if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
->rx_fifo_depth)) {
+>tx_fifo_depth)) {
dev_err(>dev, "cannot obtain tx-fifo-depth\n");
ret = -ENXIO;
goto err_free_netdev;
-- 
1.9.1

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[PATCH net-next] altera_tse: Correct typo in obtaining tx_fifo_depth from devicetree

2015-02-23 Thread Vince Bridgers
From: Vlastimil Setka se...@vsis.cz

This patch corrects a typo in the way tx_fifo_depth is read from the
devicetree. This patch was submitted by Vlastimil about a week ago,
and is now cleaned up and resubmitted.

Signed-off-by: Vlastimil Setka se...@vsis.cz
Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 drivers/net/ethernet/altera/altera_tse_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/altera/altera_tse_main.c 
b/drivers/net/ethernet/altera/altera_tse_main.c
index a1ee261..91ad435 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -1407,7 +1407,7 @@ static int altera_tse_probe(struct platform_device *pdev)
}
 
if (of_property_read_u32(pdev-dev.of_node, tx-fifo-depth,
-priv-rx_fifo_depth)) {
+priv-tx_fifo_depth)) {
dev_err(pdev-dev, cannot obtain tx-fifo-depth\n);
ret = -ENXIO;
goto err_free_netdev;
-- 
1.9.1

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[PATCH net-next] altera_tse: Fixes in NAPI and interrupt handling paths

2015-02-23 Thread Vince Bridgers
From: Vlastimil Setka se...@vsis.cz

Incorrect NAPI polling caused WARNING at net/core/dev.c net_rx_action.
Some stability issues were also seen at high throughput and system
load before this patch.

This patch contains several changes in altera_tse_main.c:

- tse_rx() is fixed to not process more than `limit` frames

- tse_poll() is refactored to match NAPI logic
  - only received frames are counted for return value
  - removed bogus condition `(rxcomplete = budget || txcomplete  0)`
  - replace by: if (rxcomplete  budget) - call __napi_complete and enable irq

- altera_isr()
  - replace spin_lock_irqsave() by spin_lock() - we are in isr
  - use spinlocks just over irq manipulation, not over __napi_schedule
  - reset IRQ first, then disable and schedule napi

This is a cleaned up resubmission from Vlastimil's recent submission.

Signed-off-by: Vlastimil Setka se...@vsis.cz
Signed-off-by: Roman Pisl rp...@kky.zcu.cz
Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 drivers/net/ethernet/altera/altera_tse_main.c | 45 +--
 1 file changed, 22 insertions(+), 23 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_tse_main.c 
b/drivers/net/ethernet/altera/altera_tse_main.c
index 91ad435..fd9296a 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -376,7 +376,8 @@ static int tse_rx(struct altera_tse_private *priv, int 
limit)
u16 pktlength;
u16 pktstatus;
 
-   while ((rxstatus = priv-dmaops-get_rx_status(priv)) != 0) {
+   while (((rxstatus = priv-dmaops-get_rx_status(priv)) != 0) 
+  (count  limit))  {
pktstatus = rxstatus  16;
pktlength = rxstatus  0x;
 
@@ -491,28 +492,27 @@ static int tse_poll(struct napi_struct *napi, int budget)
struct altera_tse_private *priv =
container_of(napi, struct altera_tse_private, napi);
int rxcomplete = 0;
-   int txcomplete = 0;
unsigned long int flags;
 
-   txcomplete = tse_tx_complete(priv);
+   tse_tx_complete(priv);
 
rxcomplete = tse_rx(priv, budget);
 
-   if (rxcomplete = budget || txcomplete  0)
-   return rxcomplete;
+   if (rxcomplete  budget) {
 
-   napi_gro_flush(napi, false);
-   __napi_complete(napi);
+   napi_gro_flush(napi, false);
+   __napi_complete(napi);
 
-   netdev_dbg(priv-dev,
-  NAPI Complete, did %d packets with budget %d\n,
-  txcomplete+rxcomplete, budget);
+   netdev_dbg(priv-dev,
+  NAPI Complete, did %d packets with budget %d\n,
+  rxcomplete, budget);
 
-   spin_lock_irqsave(priv-rxdma_irq_lock, flags);
-   priv-dmaops-enable_rxirq(priv);
-   priv-dmaops-enable_txirq(priv);
-   spin_unlock_irqrestore(priv-rxdma_irq_lock, flags);
-   return rxcomplete + txcomplete;
+   spin_lock_irqsave(priv-rxdma_irq_lock, flags);
+   priv-dmaops-enable_rxirq(priv);
+   priv-dmaops-enable_txirq(priv);
+   spin_unlock_irqrestore(priv-rxdma_irq_lock, flags);
+   }
+   return rxcomplete;
 }
 
 /* DMA TX  RX FIFO interrupt routing
@@ -521,7 +521,6 @@ static irqreturn_t altera_isr(int irq, void *dev_id)
 {
struct net_device *dev = dev_id;
struct altera_tse_private *priv;
-   unsigned long int flags;
 
if (unlikely(!dev)) {
pr_err(%s: invalid dev pointer\n, __func__);
@@ -529,20 +528,20 @@ static irqreturn_t altera_isr(int irq, void *dev_id)
}
priv = netdev_priv(dev);
 
-   /* turn off desc irqs and enable napi rx */
-   spin_lock_irqsave(priv-rxdma_irq_lock, flags);
+   spin_lock(priv-rxdma_irq_lock);
+   /* reset IRQs */
+   priv-dmaops-clear_rxirq(priv);
+   priv-dmaops-clear_txirq(priv);
+   spin_unlock(priv-rxdma_irq_lock);
 
if (likely(napi_schedule_prep(priv-napi))) {
+   spin_lock(priv-rxdma_irq_lock);
priv-dmaops-disable_rxirq(priv);
priv-dmaops-disable_txirq(priv);
+   spin_unlock(priv-rxdma_irq_lock);
__napi_schedule(priv-napi);
}
 
-   /* reset IRQs */
-   priv-dmaops-clear_rxirq(priv);
-   priv-dmaops-clear_txirq(priv);
-
-   spin_unlock_irqrestore(priv-rxdma_irq_lock, flags);
 
return IRQ_HANDLED;
 }
-- 
1.9.1

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[PATCH net] net: eth: altera: Change reset_mac failure message masks from err to dbg

2015-02-12 Thread Vince Bridgers
This debug output is not really an error message since mac reset can fail
if the phy clocks are gated, specifically when the phy has been placed in
a powered down or isolation mode. The netdev output masks were changed from
err to dbg, and comments added in the code.

Signed-off-by: Vince Bridgers 
---
 drivers/net/ethernet/altera/altera_tse_main.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_tse_main.c 
b/drivers/net/ethernet/altera/altera_tse_main.c
index 760c72c..996bdf1 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -1099,8 +1099,12 @@ static int tse_open(struct net_device *dev)
 
spin_lock(>mac_cfg_lock);
ret = reset_mac(priv);
+   /* Note that reset_mac will fail if the clocks are gated by the PHY
+* due to the PHY being put into isolation or power down mode.
+* This is not an error if reset fails due to no clock.
+*/
if (ret)
-   netdev_err(dev, "Cannot reset MAC core (error: %d)\n", ret);
+   netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
 
ret = init_mac(priv);
spin_unlock(>mac_cfg_lock);
@@ -1204,8 +1208,12 @@ static int tse_shutdown(struct net_device *dev)
spin_lock(>tx_lock);
 
ret = reset_mac(priv);
+   /* Note that reset_mac will fail if the clocks are gated by the PHY
+* due to the PHY being put into isolation or power down mode.
+* This is not an error if reset fails due to no clock.
+*/
if (ret)
-   netdev_err(dev, "Cannot reset MAC core (error: %d)\n", ret);
+   netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
priv->dmaops->reset_dma(priv);
free_skbufs(dev);
 
-- 
1.9.1

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[PATCH net] net: eth: altera: Change access ports to mdio for all xMII applications

2015-02-12 Thread Vince Bridgers
Change use of Altera TSE's MDIO access from phy 0 registers to phy 1
registers. This allows support for GMII, MII, RGMII, and SGMII
designs where the external PHY is always accesible through
Altera TSE's MDIO phy 1 registers and Altera's PCS is accessible
through MDIO phy 0 registers for SGMII applications.

Signed-off-by: Vince Bridgers 
Tested-by: Kai Lin Ng 
Tested-by: Dalon Westergreen 
---
 drivers/net/ethernet/altera/altera_tse_main.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_tse_main.c 
b/drivers/net/ethernet/altera/altera_tse_main.c
index 996bdf1..a1ee261 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -105,11 +105,11 @@ static int altera_tse_mdio_read(struct mii_bus *bus, int 
mii_id, int regnum)
 
/* set MDIO address */
csrwr32((mii_id & 0x1f), priv->mac_dev,
-   tse_csroffs(mdio_phy0_addr));
+   tse_csroffs(mdio_phy1_addr));
 
/* get the data */
return csrrd32(priv->mac_dev,
-  tse_csroffs(mdio_phy0) + regnum * 4) & 0x;
+  tse_csroffs(mdio_phy1) + regnum * 4) & 0x;
 }
 
 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
@@ -120,10 +120,10 @@ static int altera_tse_mdio_write(struct mii_bus *bus, int 
mii_id, int regnum,
 
/* set MDIO address */
csrwr32((mii_id & 0x1f), priv->mac_dev,
-   tse_csroffs(mdio_phy0_addr));
+   tse_csroffs(mdio_phy1_addr));
 
/* write the data */
-   csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy0) + regnum * 4);
+   csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
return 0;
 }
 
-- 
1.9.1

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[PATCH net] net: eth: altera: Change access ports to mdio for all xMII applications

2015-02-12 Thread Vince Bridgers
Change use of Altera TSE's MDIO access from phy 0 registers to phy 1
registers. This allows support for GMII, MII, RGMII, and SGMII
designs where the external PHY is always accesible through
Altera TSE's MDIO phy 1 registers and Altera's PCS is accessible
through MDIO phy 0 registers for SGMII applications.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
Tested-by: Kai Lin Ng kai...@altera.com
Tested-by: Dalon Westergreen dwest...@gmail.com
---
 drivers/net/ethernet/altera/altera_tse_main.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_tse_main.c 
b/drivers/net/ethernet/altera/altera_tse_main.c
index 996bdf1..a1ee261 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -105,11 +105,11 @@ static int altera_tse_mdio_read(struct mii_bus *bus, int 
mii_id, int regnum)
 
/* set MDIO address */
csrwr32((mii_id  0x1f), priv-mac_dev,
-   tse_csroffs(mdio_phy0_addr));
+   tse_csroffs(mdio_phy1_addr));
 
/* get the data */
return csrrd32(priv-mac_dev,
-  tse_csroffs(mdio_phy0) + regnum * 4)  0x;
+  tse_csroffs(mdio_phy1) + regnum * 4)  0x;
 }
 
 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
@@ -120,10 +120,10 @@ static int altera_tse_mdio_write(struct mii_bus *bus, int 
mii_id, int regnum,
 
/* set MDIO address */
csrwr32((mii_id  0x1f), priv-mac_dev,
-   tse_csroffs(mdio_phy0_addr));
+   tse_csroffs(mdio_phy1_addr));
 
/* write the data */
-   csrwr32(value, priv-mac_dev, tse_csroffs(mdio_phy0) + regnum * 4);
+   csrwr32(value, priv-mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
return 0;
 }
 
-- 
1.9.1

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[PATCH net] net: eth: altera: Change reset_mac failure message masks from err to dbg

2015-02-12 Thread Vince Bridgers
This debug output is not really an error message since mac reset can fail
if the phy clocks are gated, specifically when the phy has been placed in
a powered down or isolation mode. The netdev output masks were changed from
err to dbg, and comments added in the code.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 drivers/net/ethernet/altera/altera_tse_main.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/altera/altera_tse_main.c 
b/drivers/net/ethernet/altera/altera_tse_main.c
index 760c72c..996bdf1 100644
--- a/drivers/net/ethernet/altera/altera_tse_main.c
+++ b/drivers/net/ethernet/altera/altera_tse_main.c
@@ -1099,8 +1099,12 @@ static int tse_open(struct net_device *dev)
 
spin_lock(priv-mac_cfg_lock);
ret = reset_mac(priv);
+   /* Note that reset_mac will fail if the clocks are gated by the PHY
+* due to the PHY being put into isolation or power down mode.
+* This is not an error if reset fails due to no clock.
+*/
if (ret)
-   netdev_err(dev, Cannot reset MAC core (error: %d)\n, ret);
+   netdev_dbg(dev, Cannot reset MAC core (error: %d)\n, ret);
 
ret = init_mac(priv);
spin_unlock(priv-mac_cfg_lock);
@@ -1204,8 +1208,12 @@ static int tse_shutdown(struct net_device *dev)
spin_lock(priv-tx_lock);
 
ret = reset_mac(priv);
+   /* Note that reset_mac will fail if the clocks are gated by the PHY
+* due to the PHY being put into isolation or power down mode.
+* This is not an error if reset fails due to no clock.
+*/
if (ret)
-   netdev_err(dev, Cannot reset MAC core (error: %d)\n, ret);
+   netdev_dbg(dev, Cannot reset MAC core (error: %d)\n, ret);
priv-dmaops-reset_dma(priv);
free_skbufs(dev);
 
-- 
1.9.1

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[PATCH] arm: socfpga: Correct SCU virtual mapping in socfpga

2015-02-11 Thread Vince Bridgers
Correct SCU virtual mapping that was causing this BUG message:

"BUG: mapping for 0xfffec000 at 0xfffec000 out of vmalloc space"

Signed-off-by: Vince Bridgers 
---
 arch/arm/mach-socfpga/core.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 483cb46..a0f3b1c 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -45,6 +45,6 @@ extern char secondary_trampoline, secondary_trampoline_end;
 
 extern unsigned long socfpga_cpu1start_addr;
 
-#define SOCFPGA_SCU_VIRT_BASE   0xfffec000
+#define SOCFPGA_SCU_VIRT_BASE   0xfee0
 
 #endif
-- 
1.9.1

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[PATCH] arm: socfpga: Correct SCU virtual mapping in socfpga

2015-02-11 Thread Vince Bridgers
Correct SCU virtual mapping that was causing this BUG message:

BUG: mapping for 0xfffec000 at 0xfffec000 out of vmalloc space

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 arch/arm/mach-socfpga/core.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 483cb46..a0f3b1c 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -45,6 +45,6 @@ extern char secondary_trampoline, secondary_trampoline_end;
 
 extern unsigned long socfpga_cpu1start_addr;
 
-#define SOCFPGA_SCU_VIRT_BASE   0xfffec000
+#define SOCFPGA_SCU_VIRT_BASE   0xfee0
 
 #endif
-- 
1.9.1

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[PATCH] MAINTAINERS: Update contact information for Vince Bridgers

2014-10-09 Thread Vince Bridgers
Signed-off-by: Vince Bridgers 
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9e315a4..c0c7fe6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -564,7 +564,7 @@ L:  linux-al...@vger.kernel.org
 F: arch/alpha/
 
 ALTERA TRIPLE SPEED ETHERNET DRIVER
-M: Vince Bridgers 
+M: Vince Bridgers 
 L: net...@vger.kernel.org
 L: nios2-...@lists.rocketboards.org (moderated for non-subscribers)
 S: Maintained
-- 
1.9.1

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[PATCH net] stmmac: correct mc_filter local variable in set_filter and set_mac_addr call

2014-10-09 Thread Vince Bridgers
Testing revealed that the local variable mc_filter was dimensioned
incorrectly for all possible configurations and get_mac_addr should
have been set_mac_addr (a typo). Make sure mc_filter is dimensioned
to 8 32-bit unsigned longs - the largest size of the Synopsys
multicast filter register set.

Signed-off-by: Vince Bridgers 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index 5efe60e..0adcf73 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -134,7 +134,7 @@ static void dwmac1000_set_filter(struct mac_device_info *hw,
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
unsigned int value = 0;
unsigned int perfect_addr_number = hw->unicast_filter_entries;
-   u32 mc_filter[2];
+   u32 mc_filter[8];
int mcbitslog2 = hw->mcast_bits_log2;
 
pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
@@ -182,7 +182,7 @@ static void dwmac1000_set_filter(struct mac_device_info *hw,
struct netdev_hw_addr *ha;
 
netdev_for_each_uc_addr(ha, dev) {
-   stmmac_get_mac_addr(ioaddr, ha->addr,
+   stmmac_set_mac_addr(ioaddr, ha->addr,
GMAC_ADDR_HIGH(reg),
GMAC_ADDR_LOW(reg));
reg++;
-- 
1.9.1

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[PATCH net] stmmac: correct mc_filter local variable in set_filter and set_mac_addr call

2014-10-09 Thread Vince Bridgers
Testing revealed that the local variable mc_filter was dimensioned
incorrectly for all possible configurations and get_mac_addr should
have been set_mac_addr (a typo). Make sure mc_filter is dimensioned
to 8 32-bit unsigned longs - the largest size of the Synopsys
multicast filter register set.

Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index 5efe60e..0adcf73 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -134,7 +134,7 @@ static void dwmac1000_set_filter(struct mac_device_info *hw,
void __iomem *ioaddr = (void __iomem *)dev-base_addr;
unsigned int value = 0;
unsigned int perfect_addr_number = hw-unicast_filter_entries;
-   u32 mc_filter[2];
+   u32 mc_filter[8];
int mcbitslog2 = hw-mcast_bits_log2;
 
pr_debug(%s: # mcasts %d, # unicast %d\n, __func__,
@@ -182,7 +182,7 @@ static void dwmac1000_set_filter(struct mac_device_info *hw,
struct netdev_hw_addr *ha;
 
netdev_for_each_uc_addr(ha, dev) {
-   stmmac_get_mac_addr(ioaddr, ha-addr,
+   stmmac_set_mac_addr(ioaddr, ha-addr,
GMAC_ADDR_HIGH(reg),
GMAC_ADDR_LOW(reg));
reg++;
-- 
1.9.1

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[PATCH] MAINTAINERS: Update contact information for Vince Bridgers

2014-10-09 Thread Vince Bridgers
Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9e315a4..c0c7fe6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -564,7 +564,7 @@ L:  linux-al...@vger.kernel.org
 F: arch/alpha/
 
 ALTERA TRIPLE SPEED ETHERNET DRIVER
-M: Vince Bridgers vbridgers2...@gmail.com
+M: Vince Bridgers vbrid...@opensource.altera.com
 L: net...@vger.kernel.org
 L: nios2-...@lists.rocketboards.org (moderated for non-subscribers)
 S: Maintained
-- 
1.9.1

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Re: [PATCH] net: stmmac: add dcrs parameter

2014-08-26 Thread Vince Bridgers
Hi Peppe,

>>
>> In the Synopsys EMAC case, carrier sense is used to stop transmitting
>> if no carrier is sensed during a transmission. This is only useful if
>> the media in use is true half duplex media (like obsolete 10Base2 or
>> 10Base5). If no one in using true half duplex media, then is it
>> possible to set this disable by default? If we're not sure, then
>> having an option feels like the right thing to do.
>
>
> Indeed this is what I had done in the patch.
>
> http://git.stlinux.com/?p=stm/linux-sh4-2.6.32.y.git;a=commit;h=b0b863bf65c36dc593f6b7b4b418394fd880dae2
>
> Also in case of carrier sense the frame will be dropped in any case
> later.
>
> Let me know if you Acked this patch so I will rebase it on
> net.git and I send it soon
>
> peppe
>

Yes, this looks good to me. I don't expect anyone is using 10Base2 or
10Base5 anymore, so it's ok to disable DCRS by default.

ack

All the best,

Vince
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Re: [PATCH] net: stmmac: add dcrs parameter

2014-08-26 Thread Vince Bridgers
Hi Peppe,


 In the Synopsys EMAC case, carrier sense is used to stop transmitting
 if no carrier is sensed during a transmission. This is only useful if
 the media in use is true half duplex media (like obsolete 10Base2 or
 10Base5). If no one in using true half duplex media, then is it
 possible to set this disable by default? If we're not sure, then
 having an option feels like the right thing to do.


 Indeed this is what I had done in the patch.

 http://git.stlinux.com/?p=stm/linux-sh4-2.6.32.y.git;a=commit;h=b0b863bf65c36dc593f6b7b4b418394fd880dae2

 Also in case of carrier sense the frame will be dropped in any case
 later.

 Let me know if you Acked this patch so I will rebase it on
 net.git and I send it soon

 peppe


Yes, this looks good to me. I don't expect anyone is using 10Base2 or
10Base5 anymore, so it's ok to disable DCRS by default.

ack

All the best,

Vince
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Re: [PATCH] net: stmmac: add dcrs parameter

2014-08-25 Thread Vince Bridgers
Hi,

On Mon, Aug 25, 2014 at 7:51 AM, Giuseppe CAVALLARO
 wrote:
> On 8/25/2014 2:34 PM, Chen-Yu Tsai wrote:
>>
>> Hi,
>>
>> On Mon, Aug 25, 2014 at 7:50 PM, Ley Foon Tan  wrote:
>>>
>>> This patch add the option to enable DCRS bit in GMAC control register.
>>> Default is disabled if snps,dcrs is not defined.
>>>
>>> For MII, Carrier Sense (CRS) must be asserted during transmission
>>> whereas in RGMII, CRS is not. RGMII does not provide a way to signal
>>> loss of carrier during a transmission.

While technically true, from a practical point of view, this is only
useful if using true half-duplex media (like the now obsolete 10Base2
and 10Base5 - think old school coax with vampire taps).

>>>
>>> When DCRS bit set high in control register, the MAC transmitter
>>> ignore the (G)MII Carrier Sense signal during frame transmission
>>> in the half-duplex mode. This request results in no errors generated
>>> because of Loss of Carrier or No Carrier during such transmission.
>>>
>>> Signed-off-by: Ley Foon Tan 
>>> ---



>>
>> Since you know this is only required under (G)MII, could you not re-use
>> the "phy-mode" property, instead of adding another one?
>>
>> Better yet, use the "interface" field in the platform data. This way
>> you'll
>> fix non-DT devices as well. You could then avoid touching the platform
>> driver,
>> and just modify the driver core.
>
>
> yes this is what I asked. Thx ChenYu for the this detail.
> Ley Foon Tan, could you do that? Let me know
>
> peppe
>
>

In the Synopsys EMAC case, carrier sense is used to stop transmitting
if no carrier is sensed during a transmission. This is only useful if
the media in use is true half duplex media (like obsolete 10Base2 or
10Base5). If no one in using true half duplex media, then is it
possible to set this disable by default? If we're not sure, then
having an option feels like the right thing to do.

Vince
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Re: [PATCH] net: stmmac: add dcrs parameter

2014-08-25 Thread Vince Bridgers
Hi,

On Mon, Aug 25, 2014 at 7:51 AM, Giuseppe CAVALLARO
peppe.cavall...@st.com wrote:
 On 8/25/2014 2:34 PM, Chen-Yu Tsai wrote:

 Hi,

 On Mon, Aug 25, 2014 at 7:50 PM, Ley Foon Tan lf...@altera.com wrote:

 This patch add the option to enable DCRS bit in GMAC control register.
 Default is disabled if snps,dcrs is not defined.

 For MII, Carrier Sense (CRS) must be asserted during transmission
 whereas in RGMII, CRS is not. RGMII does not provide a way to signal
 loss of carrier during a transmission.

While technically true, from a practical point of view, this is only
useful if using true half-duplex media (like the now obsolete 10Base2
and 10Base5 - think old school coax with vampire taps).


 When DCRS bit set high in control register, the MAC transmitter
 ignore the (G)MII Carrier Sense signal during frame transmission
 in the half-duplex mode. This request results in no errors generated
 because of Loss of Carrier or No Carrier during such transmission.

 Signed-off-by: Ley Foon Tan lf...@altera.com
 ---

snip


 Since you know this is only required under (G)MII, could you not re-use
 the phy-mode property, instead of adding another one?

 Better yet, use the interface field in the platform data. This way
 you'll
 fix non-DT devices as well. You could then avoid touching the platform
 driver,
 and just modify the driver core.


 yes this is what I asked. Thx ChenYu for the this detail.
 Ley Foon Tan, could you do that? Let me know

 peppe



In the Synopsys EMAC case, carrier sense is used to stop transmitting
if no carrier is sensed during a transmission. This is only useful if
the media in use is true half duplex media (like obsolete 10Base2 or
10Base5). If no one in using true half duplex media, then is it
possible to set this disable by default? If we're not sure, then
having an option feels like the right thing to do.

Vince
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Re: linux-next: build failure after merge of the net tree

2014-07-23 Thread Vince Bridgers
On Wed, Jul 23, 2014 at 1:40 PM, Florian Fainelli  wrote:
> 2014-07-23 11:38 GMT-07:00 Vince Bridgers :
>> Hi all,
>>
>> On Mon, Jul 7, 2014 at 9:53 PM, David Miller  wrote:
>>> From: Stephen Rothwell 
>>> Date: Fri, 4 Jul 2014 11:39:07 +1000
>>>
>>>> After merging the net tree, today's linux-next build (x86_64
>>>> allmodconfig) failed like this:
>>>>
>>>> ERROR: "phy_resume" [drivers/net/ethernet/stmicro/stmmac/stmmac.ko] 
>>>> undefined!
>>>>
>>>> Caused by commit 0acf16768740 ("net: stmmac: add platform init/exit for
>>>> Altera's ARM socfpga").
>>>>
>>>> I reverted that commit for today.
>>>
>>> Vince you haven't made any effort to fix this build failure, so I am 
>>> reverting
>>> your changes.
>>
>> My apologies, I was out on vacation and I should have checked for this
>> before submitting. I have a corrected patch that I'm ready to submit.
>
> net-next does contain a change that adds EXPORT_SYMBOLE() to
> phy_resume and phy_suspend, you might be able to get along with just
> re-submitting your patches if they still apply cleanly?
> --
> Florian

Ok, I was just parsing the other email thread. I'll try that.

Cheers

Vince
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Re: linux-next: build failure after merge of the net tree

2014-07-23 Thread Vince Bridgers
Hi all,

On Mon, Jul 7, 2014 at 9:53 PM, David Miller  wrote:
> From: Stephen Rothwell 
> Date: Fri, 4 Jul 2014 11:39:07 +1000
>
>> After merging the net tree, today's linux-next build (x86_64
>> allmodconfig) failed like this:
>>
>> ERROR: "phy_resume" [drivers/net/ethernet/stmicro/stmmac/stmmac.ko] 
>> undefined!
>>
>> Caused by commit 0acf16768740 ("net: stmmac: add platform init/exit for
>> Altera's ARM socfpga").
>>
>> I reverted that commit for today.
>
> Vince you haven't made any effort to fix this build failure, so I am reverting
> your changes.

My apologies, I was out on vacation and I should have checked for this
before submitting. I have a corrected patch that I'm ready to submit.

Vince
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Re: linux-next: build failure after merge of the net tree

2014-07-23 Thread Vince Bridgers
Hi all,

On Mon, Jul 7, 2014 at 9:53 PM, David Miller da...@davemloft.net wrote:
 From: Stephen Rothwell s...@canb.auug.org.au
 Date: Fri, 4 Jul 2014 11:39:07 +1000

 After merging the net tree, today's linux-next build (x86_64
 allmodconfig) failed like this:

 ERROR: phy_resume [drivers/net/ethernet/stmicro/stmmac/stmmac.ko] 
 undefined!

 Caused by commit 0acf16768740 (net: stmmac: add platform init/exit for
 Altera's ARM socfpga).

 I reverted that commit for today.

 Vince you haven't made any effort to fix this build failure, so I am reverting
 your changes.

My apologies, I was out on vacation and I should have checked for this
before submitting. I have a corrected patch that I'm ready to submit.

Vince
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Re: linux-next: build failure after merge of the net tree

2014-07-23 Thread Vince Bridgers
On Wed, Jul 23, 2014 at 1:40 PM, Florian Fainelli f.faine...@gmail.com wrote:
 2014-07-23 11:38 GMT-07:00 Vince Bridgers vbridgers2...@gmail.com:
 Hi all,

 On Mon, Jul 7, 2014 at 9:53 PM, David Miller da...@davemloft.net wrote:
 From: Stephen Rothwell s...@canb.auug.org.au
 Date: Fri, 4 Jul 2014 11:39:07 +1000

 After merging the net tree, today's linux-next build (x86_64
 allmodconfig) failed like this:

 ERROR: phy_resume [drivers/net/ethernet/stmicro/stmmac/stmmac.ko] 
 undefined!

 Caused by commit 0acf16768740 (net: stmmac: add platform init/exit for
 Altera's ARM socfpga).

 I reverted that commit for today.

 Vince you haven't made any effort to fix this build failure, so I am 
 reverting
 your changes.

 My apologies, I was out on vacation and I should have checked for this
 before submitting. I have a corrected patch that I'm ready to submit.

 net-next does contain a change that adds EXPORT_SYMBOLE() to
 phy_resume and phy_suspend, you might be able to get along with just
 re-submitting your patches if they still apply cleanly?
 --
 Florian

Ok, I was just parsing the other email thread. I'll try that.

Cheers

Vince
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Re: [PATCH] Altera TSE: ALTERA_TSE should depend on HAS_DMA

2014-05-02 Thread Vince Bridgers
On Thu, May 1, 2014 at 11:29 PM, Geert Uytterhoeven
 wrote:
> If NO_DMA=y:
>
> drivers/built-in.o: In function `altera_tse_probe':
> altera_tse_main.c:(.text+0x25ec2e): undefined reference to `dma_set_mask'
> altera_tse_main.c:(.text+0x25ec78): undefined reference to `dma_supported'
> altera_tse_main.c:(.text+0x25ecb6): undefined reference to `dma_supported'
> drivers/built-in.o: In function `sgdma_async_read':
> altera_sgdma.c:(.text+0x25f620): undefined reference to 
> `dma_sync_single_for_cpu'
> drivers/built-in.o: In function `sgdma_uninitialize':
> (.text+0x25f678): undefined reference to `dma_unmap_single'
> drivers/built-in.o: In function `sgdma_uninitialize':
> (.text+0x25f696): undefined reference to `dma_unmap_single'
> drivers/built-in.o: In function `sgdma_initialize':
> (.text+0x25f6f0): undefined reference to `dma_map_single'
> drivers/built-in.o: In function `sgdma_initialize':
> (.text+0x25f702): undefined reference to `dma_mapping_error'
> drivers/built-in.o: In function `sgdma_tx_buffer':
> (.text+0x25f92a): undefined reference to `dma_sync_single_for_cpu'
> drivers/built-in.o: In function `sgdma_rx_status':
> (.text+0x25fa24): undefined reference to `dma_sync_single_for_cpu'
> make[3]: *** [vmlinux] Error 1
>
> Signed-off-by: Geert Uytterhoeven 
> ---

Acked-by: Vince Bridgers 

Thanks Geert,

Vince
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Re: [PATCH] Altera TSE: ALTERA_TSE should depend on HAS_DMA

2014-05-02 Thread Vince Bridgers
On Thu, May 1, 2014 at 11:29 PM, Geert Uytterhoeven
ge...@linux-m68k.org wrote:
 If NO_DMA=y:

 drivers/built-in.o: In function `altera_tse_probe':
 altera_tse_main.c:(.text+0x25ec2e): undefined reference to `dma_set_mask'
 altera_tse_main.c:(.text+0x25ec78): undefined reference to `dma_supported'
 altera_tse_main.c:(.text+0x25ecb6): undefined reference to `dma_supported'
 drivers/built-in.o: In function `sgdma_async_read':
 altera_sgdma.c:(.text+0x25f620): undefined reference to 
 `dma_sync_single_for_cpu'
 drivers/built-in.o: In function `sgdma_uninitialize':
 (.text+0x25f678): undefined reference to `dma_unmap_single'
 drivers/built-in.o: In function `sgdma_uninitialize':
 (.text+0x25f696): undefined reference to `dma_unmap_single'
 drivers/built-in.o: In function `sgdma_initialize':
 (.text+0x25f6f0): undefined reference to `dma_map_single'
 drivers/built-in.o: In function `sgdma_initialize':
 (.text+0x25f702): undefined reference to `dma_mapping_error'
 drivers/built-in.o: In function `sgdma_tx_buffer':
 (.text+0x25f92a): undefined reference to `dma_sync_single_for_cpu'
 drivers/built-in.o: In function `sgdma_rx_status':
 (.text+0x25fa24): undefined reference to `dma_sync_single_for_cpu'
 make[3]: *** [vmlinux] Error 1

 Signed-off-by: Geert Uytterhoeven ge...@linux-m68k.org
 ---

Acked-by: Vince Bridgers vbridgers2...@gmail.com

Thanks Geert,

Vince
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Re: [PATCH net-next 1/7] altera: Remove casts of pointer to same type

2014-03-24 Thread Vince Bridgers
Hi Joe, thanks for the patch.

On Mon, Mar 24, 2014 at 3:15 PM, Joe Perches  wrote:
> Casting a pointer to a pointer of the same type is pointless,
> so remove these unnecessary casts.
>
> Done via coccinelle script:
>
> $ cat typecast_2.cocci
> @@
> type T;
> T *foo;
> @@
>
> -   (T *)foo
> +   foo
>
> Signed-off-by: Joe Perches 
> ---

Acked-by: Vince Bridgers 

All the best,

Vince
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Re: [PATCH net-next 1/7] altera: Remove casts of pointer to same type

2014-03-24 Thread Vince Bridgers
Hi Joe, thanks for the patch.

On Mon, Mar 24, 2014 at 3:15 PM, Joe Perches j...@perches.com wrote:
 Casting a pointer to a pointer of the same type is pointless,
 so remove these unnecessary casts.

 Done via coccinelle script:

 $ cat typecast_2.cocci
 @@
 type T;
 T *foo;
 @@

 -   (T *)foo
 +   foo

 Signed-off-by: Joe Perches j...@perches.com
 ---

Acked-by: Vince Bridgers vbridgers2...@gmail.com

All the best,

Vince
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