Re: [PATCH v2 1/1] dmaengine: idxd: Add IDXD performance monitor support
On 03-04-21, 11:45, Tom Zanussi wrote:
> +config INTEL_IDXD_PERFMON
> + bool "Intel Data Accelerators performance monitor support"
> + depends on INTEL_IDXD
> + default y
default y..?
> /* IDXD software descriptor */
> @@ -369,4 +399,19 @@ int idxd_cdev_get_major(struct idxd_device *idxd);
> int idxd_wq_add_cdev(struct idxd_wq *wq);
> void idxd_wq_del_cdev(struct idxd_wq *wq);
>
> +/* perfmon */
> +#ifdef CONFIG_INTEL_IDXD_PERFMON
maybe use IS_ENABLED()
> @@ -556,6 +562,8 @@ static int __init idxd_init_module(void)
> for (i = 0; i < IDXD_TYPE_MAX; i++)
> idr_init(_idrs[i]);
>
> + perfmon_init();
> +
> err = idxd_register_bus_type();
> if (err < 0)
> return err;
> @@ -589,5 +597,6 @@ static void __exit idxd_exit_module(void)
> pci_unregister_driver(_pci_driver);
> idxd_cdev_remove();
> idxd_unregister_bus_type();
> + perfmon_exit();
Ideally would make sense to add perfmon module first and then add use in
idxd..
> +static ssize_t cpumask_show(struct device *dev, struct device_attribute
> *attr,
> + char *buf);
> +
> +static cpumask_t perfmon_dsa_cpu_mask;
> +static bool cpuhp_set_up;
> +static enum cpuhp_state cpuhp_slot;
> +
> +static DEVICE_ATTR_RO(cpumask);
Pls document these new attributes added
> +static int perfmon_collect_events(struct idxd_pmu *idxd_pmu,
> + struct perf_event *leader,
> + bool dogrp)
dogrp..?
> +static int perfmon_validate_group(struct idxd_pmu *pmu,
> + struct perf_event *event)
> +{
> + struct perf_event *leader = event->group_leader;
> + struct idxd_pmu *fake_pmu;
> + int i, ret = 0, n;
> +
> + fake_pmu = kzalloc(sizeof(*fake_pmu), GFP_KERNEL);
> + if (!fake_pmu)
> + return -ENOMEM;
> +
> + fake_pmu->pmu.name = pmu->pmu.name;
> + fake_pmu->n_counters = pmu->n_counters;
> +
> + n = perfmon_collect_events(fake_pmu, leader, true);
> + if (n < 0) {
> + ret = n;
> + goto out;
> + }
> +
> + fake_pmu->n_events = n;
> + n = perfmon_collect_events(fake_pmu, event, false);
> + if (n < 0) {
> + ret = n;
> + goto out;
> + }
> +
> + fake_pmu->n_events = n;
> +
> + for (i = 0; i < n; i++) {
> + int idx;
lets move it to top of the function please
> +static inline u64 perfmon_pmu_read_counter(struct perf_event *event)
> +{
> + struct hw_perf_event *hwc = >hw;
> + struct idxd_device *idxd;
> + int cntr = hwc->idx;
> + u64 cntrdata;
> +
> + idxd = event_to_idxd(event);
> +
> + cntrdata = ioread64(CNTRDATA_REG(idxd, cntr));
> +
> + return cntrdata;
return ioread64() ?
--
~Vinod
Re: [PATCH v2 -next] dmaengine: at_xdmac: Remove unused inline function at_xdmac_csize()
On 07-04-21, 21:25, YueHaibing wrote:
> commit 765c37d87669 ("dmaengine: at_xdmac: rework slave configuration part")
> left behind this, so can remove it.
Applied, thanks
--
~Vinod
Re: [PATCH] dmaengine: idxd: Fix potential null dereference on pointer status
On 15-04-21, 12:06, Colin King wrote: > From: Colin Ian King > > There are calls to idxd_cmd_exec that pass a null status pointer however > a recent commit has added an assignment to *status that can end up > with a null pointer dereference. The function expects a null status > pointer sometimes as there is a later assignment to *status where > status is first null checked. Fix the issue by null checking status > before making the assignment. Applied, thanks -- ~Vinod
[GIT PULL]: dmaengine fixes for 5.12
Hi Linus, Please pull to receive the fixes for dmaengine for v5.12. Mostly bunch of driver fixes. The following changes since commit a38fd8748464831584a19438cbb3082b5a2dab15: Linux 5.12-rc2 (2021-03-05 17:33:41 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git tags/dmaengine-fix-5.12 for you to fetch changes up to ea9aadc06a9f10ad20a90edc0a484f1147d88a7a: dmaengine: idxd: fix wq cleanup of WQCFG registers (2021-04-12 22:08:39 +0530) dmaengine fixes for v5.12 Couple of dmaengine driver fixes for: - race and descriptor issue for xilinx driver - fix interrupt handling, wq state & cleanup, field sizes for completion, msix permissions for idxd driver - rumtim pm fix for tegra driver - double free fix in dma_async_device_register Andy Shevchenko (1): dmaengine: dw: Make it dependent to HAS_IOMEM Dan Carpenter (1): dmaengine: plx_dma: add a missing put_device() on error path Dave Jiang (6): dmaengine: idxd: Fix clobbering of SWERR overflow bit on writeback dmaengine: idxd: fix delta_rec and crc size field for completion record dmaengine: idxd: fix opcap sysfs attribute output dmaengine: idxd: fix wq size store permission state dmaengine: idxd: clear MSIX permission entry on shutdown dmaengine: idxd: fix wq cleanup of WQCFG registers Dinghao Liu (1): dmaengine: tegra20: Fix runtime PM imbalance on error Laurent Pinchart (2): dmaengine: xilinx: dpdma: Fix descriptor issuing on video group dmaengine: xilinx: dpdma: Fix race condition in done IRQ Lv Yunlong (1): dmaengine: Fix a double free in dma_async_device_register drivers/dma/dmaengine.c | 1 + drivers/dma/dw/Kconfig| 2 ++ drivers/dma/idxd/device.c | 65 --- drivers/dma/idxd/idxd.h | 3 ++ drivers/dma/idxd/init.c | 11 ++- drivers/dma/idxd/irq.c| 4 ++- drivers/dma/idxd/sysfs.c | 19 ++-- drivers/dma/plx_dma.c | 18 ++- drivers/dma/tegra20-apb-dma.c | 4 +-- drivers/dma/xilinx/xilinx_dpdma.c | 31 +++ include/uapi/linux/idxd.h | 4 +-- 11 files changed, 109 insertions(+), 53 deletions(-) Thanks -- ~Vinod signature.asc Description: PGP signature
[GIT PULL]: Generic phy updates for v5.13 -second round
Hi Greg, As promised, here are some minor fixes for earlier pull request. This includes fixes which came in after the request was sent The following changes since commit cbc336c09b6d6dfb24d20c955599123308fa2fe2: phy: fix resource_size.cocci warnings (2021-04-06 10:39:20 +0530) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git tags/phy-for-5.13-second for you to fetch changes up to 8a6b85b14f082d266b0312562f7372e1a8f5dfb3: phy: Revert "phy: ti: j721e-wiz: add missing of_node_put" (2021-04-12 10:35:05 +0530) phy-for-5.13 second pull Driver fixes for: - Revert wrong of_node_put patch and add missing header for ti j721e driver - use-after-free fix for twl4030 Shixin Liu (1): phy: ti: j721e-wiz: Add missing include linux/slab.h Vinod Koul (1): phy: Revert "phy: ti: j721e-wiz: add missing of_node_put" Yang Yingliang (1): phy: phy-twl4030-usb: Fix possible use-after-free in twl4030_usb_remove() drivers/phy/ti/phy-j721e-wiz.c | 2 +- drivers/phy/ti/phy-twl4030-usb.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Thanks -- ~Vinod signature.asc Description: PGP signature
Re: [PATCH v2 2/3] soundwire: Intel: introduce DMI quirks for HP Spectre x360 Convertible
On 12-04-21, 14:37, Dave Hansen wrote: > On 3/1/21 11:51 PM, Bard Liao wrote: > > +++ b/drivers/soundwire/dmi-quirks.c > > @@ -0,0 +1,66 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > > +// Copyright(c) 2021 Intel Corporation. > > It looks like this is already in intel-next, so this may be moot. But, > is there a specific reason this is dual licensed? If so, can you please > include information about the license choice in the cover letter of any > future version? The soundwire module from Intel and core soundwire core was always dual licensed, so it kind of followed that.. > If there is no specific reason for this contribution to be dual > licensed, please make it GPL-2.0 only. This module, I would say NO. Unless someone from Intel disagree.. Pierre/Bard..? If all agree I dont see a reason why this cant be updated to GPL only. Thanks -- ~Vinod
Re: [PATCH v2] dmaengine: k3dma: use the correct HiSilicon copyright
On 01-04-21, 19:50, Hao Fang wrote: > s/Hisilicon/HiSilicon/g. > It should use capital S, according to the official website. Applied, thanks -- ~Vinod
Re: [PATCH] dmaengine: qcom_hidma: remove unused code
On 01-04-21, 17:53, Jiapeng Chong wrote: > Fix the following clang warning: > > drivers/dma/qcom/hidma.c:94:20: warning: unused function 'to_hidma_desc' > [-Wunused-function]. Applied, thanks -- ~Vinod
Re: [PATCH] dmaengine: plx_dma: add a missing put_device() on error path
On 23-03-21, 16:19, Dan Carpenter wrote: > Add a missing put_device(>dev) if the call to > dma_async_device_register(dma); fails. Applied, thanks -- ~Vinod
Re: [PATCH v14 12/12] dmaengine: imx-sdma: add terminated list for freed descriptor in worker
On 07-04-21, 23:30, Robin Gong wrote:
> Add terminated list for keeping descriptor so that it could be freed in
> worker without any potential involving next descriptor raised up before
> this descriptor freed, because vchan_get_all_descriptors get all
> descriptors including the last terminated descriptor and the next
> descriptor, hence, the next descriptor maybe freed unexpectly when it's
> done in worker without this patch.
> https://www.spinics.net/lists/dmaengine/msg23367.html
Sound like you should implement .device_synchronize() and do the actual
work there..?
>
> Signed-off-by: Robin Gong
> Reported-by: Richard Leitner
> ---
> drivers/dma/imx-sdma.c | 17 ++---
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 9519b41..4174580 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -381,6 +381,7 @@ struct sdma_channel {
> enum dma_status status;
> struct imx_dma_data data;
> struct work_struct terminate_worker;
> + struct list_headterminated;
> boolis_ram_script;
> };
>
> @@ -1041,9 +1042,6 @@ static void sdma_channel_terminate_work(struct
> work_struct *work)
> {
> struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
> terminate_worker);
> - unsigned long flags;
> - LIST_HEAD(head);
> -
> /*
>* According to NXP R team a delay of one BD SDMA cost time
>* (maximum is 1ms) should be added after disable of the channel
> @@ -1052,10 +1050,7 @@ static void sdma_channel_terminate_work(struct
> work_struct *work)
>*/
> usleep_range(1000, 2000);
>
> - spin_lock_irqsave(>vc.lock, flags);
> - vchan_get_all_descriptors(>vc, );
> - spin_unlock_irqrestore(>vc.lock, flags);
> - vchan_dma_desc_free_list(>vc, );
> + vchan_dma_desc_free_list(>vc, >terminated);
> }
>
> static int sdma_terminate_all(struct dma_chan *chan)
> @@ -1069,6 +1064,13 @@ static int sdma_terminate_all(struct dma_chan *chan)
>
> if (sdmac->desc) {
> vchan_terminate_vdesc(>desc->vd);
> + /*
> + * move out current descriptor into terminated list so that
> + * it could be free in sdma_channel_terminate_work alone
> + * later without potential involving next descriptor raised
> + * up before the last descriptor terminated.
> + */
> + vchan_get_all_descriptors(>vc, >terminated);
> sdmac->desc = NULL;
> schedule_work(>terminate_worker);
> }
> @@ -2075,6 +2077,7 @@ static int sdma_probe(struct platform_device *pdev)
>
> sdmac->channel = i;
> sdmac->vc.desc_free = sdma_desc_free;
> + INIT_LIST_HEAD(>terminated);
> INIT_WORK(>terminate_worker,
> sdma_channel_terminate_work);
> /*
> --
> 2.7.4
--
~Vinod
Re: [PATCH] [v2] dmaengine: tegra20: Fix runtime PM imbalance on error
On 09-04-21, 16:28, Dinghao Liu wrote: > pm_runtime_get_sync() will increase the runtime PM counter > even it returns an error. Thus a pairing decrement is needed > to prevent refcount leak. Fix this by replacing this API with > pm_runtime_resume_and_get(), which will not change the runtime > PM counter on error. Applied, thanks -- ~Vinod
Re: [PATCH v2] dma: Fix a double free in dma_async_device_register
On 30-03-21, 18:44, Lv Yunlong wrote: > In the first list_for_each_entry() macro of dma_async_device_register, > it gets the chan from list and calls __dma_async_device_channel_register > (..,chan). We can see that chan->local is allocated by alloc_percpu() and > it is freed chan->local by free_percpu(chan->local) when > __dma_async_device_channel_register() failed. > > But after __dma_async_device_channel_register() failed, the caller will > goto err_out and freed the chan->local in the second time by free_percpu(). > > The cause of this problem is forget to set chan->local to NULL when > chan->local was freed in __dma_async_device_channel_register(). My > patch sets chan->local to NULL when the callee failed to avoid double free. Applied after fixing subsystem name, thanks -- ~Vinod
Re: [PATCH v2 1/1] dmaengine: dw: Make it dependent to HAS_IOMEM
On 24-03-21, 16:17, Andy Shevchenko wrote: > Some architectures do not provide devm_*() APIs. Hence make the driver > dependent on HAVE_IOMEM. Applied, thanks -- ~Vinod
Re: [PATCH -next] phy: ti: j721e-wiz: Add missing include linux/slab.h
On 08-04-21, 09:28, Shixin Liu wrote: > When compiling with CONFIG_PHY_J721E_WIZ, Hulk Robot reported: > > drivers/phy/ti/phy-j721e-wiz.c: In function ‘wiz_mux_clk_register’: > drivers/phy/ti/phy-j721e-wiz.c:659:17: error: implicit declaration of > function ‘kzalloc’; did you mean ‘vzalloc’? > [-Werror=implicit-function-declaration] > 659 | parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); > | ^~~ > | vzalloc > drivers/phy/ti/phy-j721e-wiz.c:659:15: warning: assignment to ‘const char **’ > from ‘int’ makes pointer from integer without a cast [-Wint-conversion] > 659 | parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); > | ^ > drivers/phy/ti/phy-j721e-wiz.c:697:2: error: implicit declaration of function > ‘kfree’; did you mean ‘vfree’? [-Werror=implicit-function-declaration] > 697 | kfree(parent_names); > | ^ > | vfre Applied, thanks -- ~Vinod
Re: [PATCH -next] phy: phy-twl4030-usb: Fix possible use-after-free in twl4030_usb_remove()
On 07-04-21, 17:27, Yang Yingliang wrote: > This driver's remove path calls cancel_delayed_work(). However, that > function does not wait until the work function finishes. This means > that the callback function may still be running after the driver's > remove function has finished, which would result in a use-after-free. > > Fix by calling cancel_delayed_work_sync(), which ensures that > the work is properly cancelled, no longer running, and unable > to re-schedule itself. Applied, thanks -- ~Vinod
[GIT PULL]: Generic phy updates for v5.13-rc1
phy: tusb1210: use bitmasks to set VENDOR_SPECIFIC2 Manish Narani (1): phy: zynqmp: Handle the clock enable/disable properly Rafał Miłecki (4): phy: phy-brcm-usb: select SOC_BRCMSTB on brcmstb only dt-bindings: phy: brcm,brcmstb-usb-phy: add power-domains dt-bindings: phy: bcm-ns-usb2-phy: convert to yaml dt-bindings: phy: bcm-ns-usb3-phy: convert to yaml Randy Dunlap (1): phy: marvell: phy-mvebu-cp11i-utmi needs USB_COMMON Sandeep Maheswaram (1): dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SC7280 Seiya Wang (3): dt-bindings: phy: Add compatible for Mediatek MT8195 dt-bindings: phy: Add compatible for Mediatek MT8195 dt-bindings: phy: fix dt_binding_check warning in mediatek, ufs-phy.yaml Sergio Paracuellos (1): phy: ralink: phy-mt7621-pci: fix XTAL bitmask Steen Hegelund (4): dt-bindings: phy: Add sparx5-serdes bindings phy: Add media type and speed serdes configuration interfaces phy: Add Sparx5 ethernet serdes PHY driver phy: Sparx5 Eth SerDes: Use direct register operations Swapnil Jakhade (2): phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clock phy: cadence-torrent: Update PCIe + USB config for correct PLL1 clock Vinod Koul (2): MAINTAINERS: Add linux-phy list and patchwork Merge tag 'ti-serdes-for-5.13' into next Wei Yongjun (2): phy: ralink: phy-mt7621-pci: fix return value check in mt7621_pci_phy_probe() phy: ingenic: Fix a typo in ingenic_usb_phy_probe() Yang Li (1): phy: ti: j721e-wiz: add missing call to of_node_put() Zhang Yunkai (1): phy: qualcomm: remove duplicate argument kernel test robot (1): phy: fix resource_size.cocci warnings .../devicetree/bindings/phy/bcm-ns-usb2-phy.txt| 21 - .../devicetree/bindings/phy/bcm-ns-usb2-phy.yaml | 59 + .../devicetree/bindings/phy/bcm-ns-usb3-phy.txt| 34 - .../devicetree/bindings/phy/bcm-ns-usb3-phy.yaml | 62 + .../bindings/phy/brcm,brcmstb-usb-phy.yaml |3 + .../bindings/phy/marvell,armada-3700-utmi-phy.yaml | 57 + .../phy/marvell,armada-cp110-utmi-phy.yaml | 109 + .../devicetree/bindings/phy/mediatek,dsi-phy.yaml | 13 +- .../devicetree/bindings/phy/mediatek,hdmi-phy.yaml | 11 +- .../devicetree/bindings/phy/mediatek,tphy.yaml |3 +- .../devicetree/bindings/phy/mediatek,ufs-phy.yaml |7 +- .../bindings/phy/microchip,sparx5-serdes.yaml | 100 + .../bindings/phy/phy-cadence-sierra.yaml | 17 +- .../bindings/phy/phy-cadence-torrent.yaml | 22 +- .../devicetree/bindings/phy/phy-mvebu-utmi.txt | 38 - .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml |5 + .../devicetree/bindings/phy/qcom,qmp-phy.yaml |2 + .../bindings/phy/qcom,qmp-usb3-dp-phy.yaml |3 +- .../bindings/phy/qcom,usb-snps-femto-v2.yaml |1 + .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml |4 + MAINTAINERS|3 +- drivers/phy/Kconfig|1 + drivers/phy/Makefile |1 + drivers/phy/broadcom/Kconfig |2 +- drivers/phy/cadence/Kconfig|2 + drivers/phy/cadence/phy-cadence-sierra.c | 419 ++- drivers/phy/cadence/phy-cadence-torrent.c | 475 +++- drivers/phy/hisilicon/phy-hi6220-usb.c |2 +- drivers/phy/hisilicon/phy-hix5hd2-sata.c |2 +- drivers/phy/ingenic/phy-ingenic-usb.c |4 +- drivers/phy/intel/phy-intel-lgm-combo.c|2 +- drivers/phy/marvell/Kconfig| 12 +- drivers/phy/marvell/Makefile |1 + drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 384 +++ drivers/phy/microchip/Kconfig | 13 + drivers/phy/microchip/Makefile |6 + drivers/phy/microchip/sparx5_serdes.c | 2513 ++ drivers/phy/microchip/sparx5_serdes.h | 136 + drivers/phy/microchip/sparx5_serdes_regs.h | 2695 drivers/phy/phy-core.c | 30 + drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c|4 +- drivers/phy/qualcomm/phy-qcom-qmp.c| 528 +++- drivers/phy/qualcomm/phy-qcom-qmp.h| 77 +- drivers/phy/qualcomm/phy-qcom-usb-hs.c |1 + drivers/phy/ralink/phy-mt7621-pci.c|6 +- drivers/phy/rockchip/phy-rockchip-typec.c |1 + drivers/phy/st/Kconfig |1 + drivers/phy/st/phy-stm32-usbphyc.c | 65 + drivers/phy/ti/phy-j721e-wiz.c | 449 +++- drivers/phy/ti/phy-tusb1210.c | 27 +- drivers/phy/xilinx/phy-zynqmp.c| 58 +- include/dt-bindings/mux/ti-serdes.h
[GIT PULL]: soundwire updates for v5.13-rc1
Hello Greg, Here is the soundwire pull request for this cycle. Bunch of core cleanup and changes along with driver updates The following changes since commit a38fd8748464831584a19438cbb3082b5a2dab15: Linux 5.12-rc2 (2021-03-05 17:33:41 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire.git tags/soundwire-5.13-rc1 for you to fetch changes up to 14968dd36a507866be0edfc2a05d48c997da5d99: soundwire: intel_init: test link->cdns (2021-04-06 10:26:44 +0530) soundwire updates for 5.13-rc1 Updates for v5.13-rc1 are: Core: - Ability to add quirks for masters - static checker cleanup for bus code Drivers: - DMI quirks for Intel controllers - static checker cleanup for drivers - add auto enumeration support qcom controller Bard Liao (4): soundwire: add master quirks for bus clash and parity soundwire: bus: handle master quirks for bus clash and parity soundwire: intel: add master quirks for bus clash and parity soundwire: intel_init: test link->cdns Pierre-Louis Bossart (22): soundwire: Intel: introduce DMI quirks for HP Spectre x360 Convertible soundwire: Intel: add DMI quirk for Dell SKU 0A3E soundwire: intel: add missing \n in dev_err() soundwire: bandwidth_allocation: add missing \n in dev_err() soundwire: cadence: add missing \n in dev_err() soundwire: stream: add missing \n in dev_err() soundwire: qcom: add missing \n in dev_err() soundwire: bus: use correct driver name in error messages soundwire: bus: test read status soundwire: bus: use consistent tests for return values soundwire: bus: demote clock stop prepare log to dev_dbg() soundwire: bus: uniquify dev_err() for SCP_INT access soundwire: bus: remove useless initialization soundwire: generic_bandwidth_allocation: remove useless init soundwire: intel: remove useless readl soundwire: qcom: check of_property_read status soundwire: stream: remove useless initialization soundwire: stream: remove useless bus initializations soundwire: cadence_master: fix kernel-doc soundwire: add definition for DPn BlockPackingMode soundwire: generic_allocation: fix confusion between group and packing soundwire: cadence: only prepare attached devices on clock stop Rander Wang (1): soundwire: stream: fix memory leak in stream config error path Srinivas Kandagatla (16): soundwire: bus: Fix device found flag correctly dt-bindings: soundwire: qcom: clarify data port bus parameters soundwire: qcom: add support to missing transport params soundwire: qcom: set continue execution flag for ignored commands soundwire: qcom: start the clock during initialization soundwire: qcom: update register read/write routine soundwire: qcom: add support to new interrupts soundwire: export sdw_compare_devid, sdw_extract_slave_id and sdw_slave_add soundwire: qcom: add auto enumeration support soundwire: qcom: wait for enumeration to be complete in probe soundwire: add static port mapping support soundwire: qcom: update port map allocation bit mask soundwire: qcom: add static port map support soundwire: qcom: wait for fifo space to be available before read/write soundwire: qcom: cleanup internal port config indexing soundwire: qcom: handle return correctly in qcom_swrm_transport_params Vinod Koul (2): soundwire: add override addr ops soundwire: qcom: use signed variable for error return .../devicetree/bindings/soundwire/qcom,sdw.txt | 20 + drivers/soundwire/Makefile | 2 +- drivers/soundwire/bus.c| 100 +++- drivers/soundwire/bus.h| 2 + drivers/soundwire/bus_type.c | 15 +- drivers/soundwire/cadence_master.c | 16 +- drivers/soundwire/dmi-quirks.c | 96 +++ drivers/soundwire/generic_bandwidth_allocation.c | 15 +- drivers/soundwire/intel.c | 24 +- drivers/soundwire/intel_init.c | 9 + drivers/soundwire/qcom.c | 652 + drivers/soundwire/slave.c | 9 +- drivers/soundwire/stream.c | 28 +- include/linux/soundwire/sdw.h | 36 +- 14 files changed, 833 insertions(+), 191 deletions(-) create mode 100644 drivers/soundwire/dmi-quirks.c Thanks -- ~Vinod signature.asc Description: PGP signature
Re: [PATCH linux-next v2 1/1] phy: Sparx5 Eth SerDes: Use direct register operations
On 29-03-21, 16:13, Steen Hegelund wrote: > Use direct register operations instead of a table of register > information to lower the stack usage. Applied, thanks -- ~Vinod
Re: [PATCH v2] phy: hisilicon: Use the correct HiSilicon copyright
On 01-04-21, 20:02, Hao Fang wrote: > s/Hisilicon/HiSilicon/g. > It should use capital S, according to the official website. Applied, thanks -- ~Vinod
Re: [PATCH -next] phy: marvell: phy-mvebu-cp11i-utmi needs USB_COMMON
On 01-04-21, 14:00, Randy Dunlap wrote: > When USB and USB_COMMON are not enabled, phy-mvebu-cp110-utmi > suffers a build error due to a missing interface that is provided > by CONFIG_USB_COMMON, so make the driver depend on USB_COMMON. > > ld: drivers/phy/marvell/phy-mvebu-cp110-utmi.o: in function > `mvebu_cp110_utmi_phy_probe': > phy-mvebu-cp110-utmi.c:(.text+0x152): undefined reference to > `of_usb_get_dr_mode_by_phy' Applied, thanks -- ~Vinod
Re: [PATCH v2] soundwire: intel_init: test link->cdns
On 06-04-21, 09:01, Bard Liao wrote: > intel_link_probe() could return error and dev_get_drvdata() will return > null in such case. So we have to test link->cdns after > link->cdns = dev_get_drvdata(>auxdev.dev); > Otherwise, we will meet the "kernel NULL pointer dereference" error. Applied, thanks -- ~Vinod
Re: [PATCH] soundwire: qcom: handle return correctly in qcom_swrm_transport_params
On 01-04-21, 10:15, Srinivas Kandagatla wrote: > Looks like return from reg_write is set but not checked. > Fix this by adding error return path. Applied, thanks -- ~Vinod
Re: [PATCH v2] soundwire: qcom: wait for fifo space to be available before read/write
On 01-04-21, 10:00, Srinivas Kandagatla wrote: > If we write registers very fast we can endup in a situation where some > of the writes will be dropped without any notice. > > So wait for the fifo space to be available before reading/writing the > soundwire registers. Applied, thanks -- ~Vinod
Re: [PATCH] soundwire: qcom: cleanup internal port config indexing
On 01-04-21, 10:24, Srinivas Kandagatla wrote: > Internally used portconfig array for storing port bandwidth > params starts from offset zero. However port zero is not really > used and we also copy the bus parameters to offset zero. > So basically we endup with a code which has to subtract 1 from port > number to get to port parameters. > > This is bit confusing to the reader so, make this bit more obvious by only > copying the parameters to offset 1 instead of zero. This will avoid doing > -1 every time when we try to get port params. > > Similar thing has been recently done with din/dout_port_mask. Applied, thanks -- ~Vinod
Re: [PATCH v1] arm64: dts: qcom: sm8350: Add support for PRNG EE
On 01-04-21, 12:15, Robert Foss wrote: > RNG (Random Number Generator) in SM8350 features PRNG EE (Execution > Environment), hence add devicetree support for it. Reviewed-by: Vinod Koul -- ~Vinod
[PATCH] arm64: dts: qcom: sm8350: Add interconnects
Add interconnect nodes and add them for modem and cdsp nodes
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a0d459069211..72cd3e7574a0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -557,6 +558,62 @@ apps_smmu: iommu@1500 {
;
};
+ config_noc: interconnect@150 {
+ compatible = "qcom,sm8350-config-noc";
+ reg = <0 0x0150 0 0xa580>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
+ mc_virt: interconnect@158 {
+ compatible = "qcom,sm8350-mc-virt";
+ reg = <0 0x0158 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
+ system_noc: interconnect@168 {
+ compatible = "qcom,sm8350-system-noc";
+ reg = <0 0x0168 0 0x1c200>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e {
+ compatible = "qcom,sm8350-aggre1-noc";
+ reg = <0 0x016e 0 0x1f180>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@170 {
+ compatible = "qcom,sm8350-aggre2-noc";
+ reg = <0 0x0170 0 0x33000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@174 {
+ compatible = "qcom,sm8350-mmss-noc";
+ reg = <0 0x0174 0 0x1f080>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
+ lpass_ag_noc: interconnect@3c4 {
+ compatible = "qcom,sm8350-lpass-ag-noc";
+ reg = <0 0x03c4 0 0xf080>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
+ compute_noc: interconnect@a0c{
+ compatible = "qcom,sm8350-compute-noc";
+ reg = <0 0x0a0c 0 0xa180>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
tcsr_mutex: hwlock@1f4 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f4 0x0 0x4>;
@@ -584,6 +641,8 @@ mpss: remoteproc@408 {
< SM8350_MSS>;
power-domain-names = "load_state", "cx", "mss";
+ interconnects = <_virt 0 _virt 1>;
+
memory-region = <_modem_mem>;
qcom,smem-states = <_modem_out 0>;
@@ -787,6 +846,10 @@ rpmhpd_opp_turbo_l1: opp10 {
};
};
};
+
+ apps_bcm_voter: bcm_voter {
+ compatible = "qcom,bcm-voter";
+ };
};
ufs_mem_hc: ufshc@1d84000 {
@@ -925,6 +988,8 @@ cdsp: remoteproc@9890 {
< SM8350_MXC>;
power-domain-names = "load_state", "cx", "mxc";
+ interconnects = <_noc 1 _virt 1>;
+
memory-region = <_cdsp_mem>;
qcom,smem-states = <_cdsp_out 0>;
@@ -1036,6 +1101,20 @@ usb_2_ssphy: phy@88ebe00 {
};
};
+ dc_noc: interconnect@90e {
+ compatible = "qcom,sm8350-dc-noc";
+ reg = <0 0x090c 0 0x4200>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
+
Re: [PATCH 1/2] soundwire: add macro to selectively change error levels
On 31-03-21, 09:13, Bard Liao wrote:
> From: Pierre-Louis Bossart
>
> We sometimes discard -ENODATA when reporting errors and lose all
> traces of issues in the console log, add a macro to add use dev_dbg()
> in such cases.
>
> Signed-off-by: Pierre-Louis Bossart
> Reviewed-by: Rander Wang
> Reviewed-by: Guennadi Liakhovetski
> Signed-off-by: Bard Liao
> ---
> drivers/soundwire/bus.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/soundwire/bus.h b/drivers/soundwire/bus.h
> index 40354469860a..8370216f95d4 100644
> --- a/drivers/soundwire/bus.h
> +++ b/drivers/soundwire/bus.h
> @@ -227,4 +227,12 @@ int sdw_bwrite_no_pm_unlocked(struct sdw_bus *bus, u16
> dev_num, u32 addr, u8 val
> void sdw_clear_slave_status(struct sdw_bus *bus, u32 request);
> int sdw_slave_modalias(const struct sdw_slave *slave, char *buf, size_t
> size);
>
> +#define sdw_dev_dbg_or_err(dev, is_err, fmt, ...)\
> + do {\
> + if (is_err) \
> + dev_err(dev, fmt, __VA_ARGS__); \
> + else\
> + dev_dbg(dev, fmt, __VA_ARGS__); \
> + } while (0)
I see a variant in sof code and now here, why not add in a
dev_dbg_or_err() and use everywhere?
Thanks
--
~Vinod
Re: [PATCH v4 0/5] soundwire: add static port map support
On 15-03-21, 16:56, Srinivas Kandagatla wrote: > In some cases, SoundWire device ports are statically mapped to Controller > ports during design, however there is no way to expose this information > to the controller. Controllers like Qualcomm ones use this info to setup > static bandwidth parameters for those ports. > > A generic port allocation is not possible in this cases! > This patch adds a new member m_port_map to SoundWire device so that > it can populate the static master port map and share it with controller > to be able to setup correct bandwidth parameters. > > As a user of this feature this patchset also adds new bindings for > wsa881x smart speaker which has 4 ports which are statically mapped > to the 3 output and 1 input port of the controller. > > Tested it on DB845c and SM8250 MTP. > > thanks, > srini > > Changes since v3: > - updated kernel doc for more clarity on m_port_map > > Srinivas Kandagatla (5): > soundwire: add static port mapping support > soundwire: qcom: update port map allocation bit mask > soundwire: qcom: add static port map support Applied all sdw patches, thanks > ASoC: dt-bindings: wsa881x: add bindings for port mapping > ASoC: codecs: wsa881x: add static port map support > > .../bindings/sound/qcom,wsa881x.yaml | 9 ++ > drivers/soundwire/qcom.c | 31 +++ > include/linux/soundwire/sdw.h | 2 ++ > sound/soc/codecs/wsa881x.c| 7 + > 4 files changed, 43 insertions(+), 6 deletions(-) > > -- > 2.21.0 -- ~Vinod
Re: [PATCH] soundwire: intel_init: test link->cdns
On 31-03-21, 09:02, Bard Liao wrote: > intel_link_probe() could return error and dev_get_drvdata() will return > null in such case. So we have to test link->cdns after > link->cdns = dev_get_drvdata(>auxdev.dev); > Otherwise, we will meet the "kernel NULL pointer dereference" error. This fails to apply for me -- ~Vinod
Re: [PATCH] soundwire: stream: fix memory leak in stream config error path
On 31-03-21, 08:46, Bard Liao wrote: > From: Rander Wang > > When stream config is failed, master runtime will release all > slave runtime in the slave_rt_list, but slave runtime is not > added to the list at this time. This patch frees slave runtime > in the config error path to fix the memory leak. Applied, thanks -- ~Vinod
Re: [PATCH] soundwire: qcom: wait for fifo space to be available before read/write
On 31-03-21, 18:00, Srinivas Kandagatla wrote:
> If we write registers very fast we can endup in a situation where some
> of the writes will be dropped without any notice.
>
> So wait for the fifo space to be available before reading/writing the
> soundwire registers.
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/soundwire/qcom.c | 74
> 1 file changed, 74 insertions(+)
>
> diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
> index 6affa3cd4039..9b45717577f2 100644
> --- a/drivers/soundwire/qcom.c
> +++ b/drivers/soundwire/qcom.c
> @@ -24,6 +24,8 @@
> #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
> #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
> #define SWRM_COMP_PARAMS 0x100
> +#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH
> GENMASK(14, 10)
> +#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH
> GENMASK(19, 15)
> #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
> #define SWRM_COMP_PARAMS_DIN_PORTS_MASK
> GENMASK(9, 5)
> #define SWRM_INTERRUPT_STATUS0x200
> @@ -51,6 +53,8 @@
> #define SWRM_CMD_FIFO_CMD0x308
> #define SWRM_CMD_FIFO_FLUSH 0x1
> #define SWRM_CMD_FIFO_STATUS 0x30C
> +#define SWRM_RD_CMD_FIFO_CNT_MASKGENMASK(20, 16)
> +#define SWRM_WR_CMD_FIFO_CNT_MASKGENMASK(12, 8)
> #define SWRM_CMD_FIFO_CFG_ADDR 0x314
> #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
> #define SWRM_RD_WR_CMD_RETRIES 0x7
> @@ -104,6 +108,7 @@
> #define SWR_BROADCAST_CMD_ID0x0F
> #define SWR_MAX_CMD_ID 14
> #define MAX_FIFO_RD_RETRY 3
> +#define SWR_OVERFLOW_RETRY_COUNT 30
>
> struct qcom_swrm_port_config {
> u8 si;
> @@ -147,6 +152,8 @@ struct qcom_swrm_ctrl {
> int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
> int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
> u32 slave_status;
> + u32 wr_fifo_depth;
> + u32 rd_fifo_depth;
> };
>
> struct qcom_swrm_data {
> @@ -238,6 +245,63 @@ static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8
> cmd_data,
> return val;
> }
>
> +static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
> +{
> + u32 fifo_outstanding_cmd, value;
> + u8 fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
> +
> + /* Check for fifo underflow during read */
> + swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, );
> + fifo_outstanding_cmd = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
> +
> + /* Check number of outstanding commands in fifo before read */
> + if (fifo_outstanding_cmd)
> + return 0;
> +
> + do {
> + usleep_range(500, 510);
> + swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, );
> + fifo_outstanding_cmd = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK,
> value);
> + if (fifo_outstanding_cmd > 0)
> + break;
> + } while (fifo_retry_count--);
> +
> + if (fifo_outstanding_cmd == 0) {
> + dev_err_ratelimited(swrm->dev, "%s err read underflow\n",
> __func__);
> + return -ENOMEM;
ENOMEM ? that should be EIO, we expected data but didnt get it in read
fifo
> + }
> +
> + return 0;
> +}
> +
> +static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
> +{
> + u32 fifo_outstanding_cmd, value;
> + u8 fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
> +
> + /* Check for fifo overflow during write */
> + swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, );
> + fifo_outstanding_cmd = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
> +
> + /* Check number of outstanding commands in fifo before write */
> + if (fifo_outstanding_cmd != swrm->wr_fifo_depth)
> + return 0;
maybe the comment should say, check for space in write fifo?
> +
> + do {
> + usleep_range(500, 510);
> + swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, );
> + fifo_outstanding_cmd = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK,
> value);
> + if (fifo_outstanding_cmd < swrm->wr_fifo_depth)
> + break;
> + } while (fifo_retry_count--);
> +
> + if (fifo_outstanding_cmd == swrm->wr_fifo_depth) {
> + dev_err_ratelimited(swrm->dev, "%s err write overflow\n",
> __func__);
> + return -ENOMEM;
EIO or better error code here too
--
~Vinod
Re: [PATCH v6 0/7] phy: qcom-qmp: provide DP phy support for sm8250
On 31-03-21, 18:16, Dmitry Baryshkov wrote: > Changes since v5: > - Rebase on top of phy-next > - Rework 'move DP functions to callbacks' patch to leave most of the >code in place, using function prototypes. Applied 1 thru 5, thanks Bjorn you can pick the dts bits. -- ~Vinod
[PATCH V2] soundwire: qcom: use signed variable for error return
We get warning of using a unsigned variable being compared to less than zero. The comparison is correct as it checks for errors from previous call to qcom_swrm_get_alert_slave_dev_num(), so we should use a signed variable here. While at it, drop the superfluous initialization as well drivers/soundwire/qcom.c: qcom_swrm_irq_handler() warn: impossible condition '(devnum < 0) => (0-255 < 0)' Reported-by: kernel test robot Signed-off-by: Vinod Koul --- drivers/soundwire/qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index b08ecb9b418c..ec86c4e53fdb 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -428,7 +428,7 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) struct qcom_swrm_ctrl *swrm = dev_id; u32 value, intr_sts, intr_sts_masked, slave_status; u32 i; - u8 devnum = 0; + int devnum; int ret = IRQ_HANDLED; swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, _sts); -- 2.26.3
Re: [PATCH] soundwire: qcom: use signed variable for error return
On 31-03-21, 09:41, Pierre-Louis Bossart wrote: > > > On 3/31/21 2:21 AM, Vinod Koul wrote: > > We get warning for using a unsigned variable being compared to less than > > zero. The comparison is correct as it checks for errors from previous > > call to qcom_swrm_get_alert_slave_dev_num(), so we should use a signed > > variable instead. > > > > drivers/soundwire/qcom.c: qcom_swrm_irq_handler() warn: impossible > > condition '(devnum < 0) => (0-255 < 0)' > > > > Reported-by: kernel test robot > > Signed-off-by: Vinod Koul > > --- > > drivers/soundwire/qcom.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c > > index b08ecb9b418c..55ed133c6704 100644 > > --- a/drivers/soundwire/qcom.c > > +++ b/drivers/soundwire/qcom.c > > @@ -428,7 +428,7 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void > > *dev_id) > > struct qcom_swrm_ctrl *swrm = dev_id; > > u32 value, intr_sts, intr_sts_masked, slave_status; > > u32 i; > > - u8 devnum = 0; > > + s8 devnum = 0; > > it's not great to store negative error codes with s8. That works in this > specific case because the function only returns -EINVAL. Yeah I did check EINVAL was the case which would work but in general I agree that makes sense, I discussed with Srini on IRC and looks like I havent posted v2, should hit the pipes shortly -- ~Vinod
Re: [PATCH] phy: ti: j721e-wiz: Configure 'p_standard_mode' only for DP/QSGMII
On 31-03-21, 18:44, Kishon Vijay Abraham I wrote: > Configure 'p_standard_mode' only for DP/QSGMII as for other modes > it's not used as per the programming sequence. Add "continue" in the > else to prevent random value from being written to p_standard_mode. Applied, thanks -- ~Vinod
Re: [PATCH] dmaengine: k3dma: use the correct HiSilicon copyright
On 30-03-21, 14:44, Hao Fang wrote:
> s/Hisilicon/HiSilicon/g.
> It should use capital S, according to
> https://www.hisilicon.com/en/terms-of-use.
Again, dont agree to terms of use. Pls drop that
>
> Signed-off-by: Hao Fang
> ---
> drivers/dma/k3dma.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/k3dma.c b/drivers/dma/k3dma.c
> index d0b2e60..ecdaada9 100644
> --- a/drivers/dma/k3dma.c
> +++ b/drivers/dma/k3dma.c
> @@ -1,7 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> * Copyright (c) 2013 - 2015 Linaro Ltd.
> - * Copyright (c) 2013 Hisilicon Limited.
> + * Copyright (c) 2013 HiSilicon Limited.
> */
> #include
> #include
> @@ -1039,6 +1039,6 @@ static struct platform_driver k3_pdma_driver = {
>
> module_platform_driver(k3_pdma_driver);
>
> -MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
> +MODULE_DESCRIPTION("HiSilicon k3 DMA Driver");
> MODULE_ALIAS("platform:k3dma");
> MODULE_LICENSE("GPL v2");
> --
> 2.8.1
--
~Vinod
Re: [PATCH 00/16] CSI2RX support on J721E
On 31-03-21, 17:10, Pratyush Yadav wrote: > On 31/03/21 03:03PM, Vinod Koul wrote: > > On 30-03-21, 23:03, Pratyush Yadav wrote: > > > Hi, > > > > > > This series adds support for CSI2 capture on J721E. It includes some > > > fixes to the Cadence CSI2RX driver, adds Rx support to Cadence DPHY > > > driver, and finally adds the TI CSI2RX wrapper driver. > > > > > > Tested on TI's J721E with OV5640 sensor. > > > > > > Paul Kocialkowski (1): > > > phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes > > > > > > Pratyush Yadav (15): > > > phy: cdns-dphy: Prepare for Rx support > > > phy: cdns-dphy: Allow setting mode > > > phy: cdns-dphy: Add Rx support > > > media: cadence: csi2rx: Add external DPHY support > > > media: cadence: csi2rx: Soft reset the streams before starting capture > > > media: cadence: csi2rx: Set the STOP bit when stopping a stream > > > media: cadence: csi2rx: Fix stream data configuration > > > media: cadence: csi2rx: Turn subdev power on before starting stream > > > media: cadence: csi2rx: Add wrappers for subdev calls > > > dmaengine: ti: k3-psil-j721e: Add entry for CSI2RX > > > dt-bindings: media: Add DT bindings for TI CSI2RX driver > > > media: ti-vpe: csi2rx: Add CSI2RX support > > > dt-bindings: phy: Convert Cadence DPHY binding to YAML > > > dt-bindings: phy: cdns,dphy: make clocks optional > > > dt-bindings: phy: cdns,dphy: add power-domains property > > > > Is there any dependency between patches to various subsystems, if not > > please do consider sending a series per subsystem... > > Without patch 1, patch 5 and later won't build. Without patch 11, patch > 13 will not work. Cover letter is a good place to mention this! And what do you mean by not working, do we have compile time dependencies? I agree that for everything to work all the pieces need to land -- ~Vinod
Re: [PATCH v2 7/8] dt-bindings: phy: fix dt_binding_check warning in mediatek,ufs-phy.yaml
On 19-03-21, 10:34, Seiya Wang wrote: > This commit fixes the warning messages of make dt_binding_check from > newly added mediatek,mt8195-ufsphy in mediatek,ufs-phy.yaml Applied, thanks -- ~Vinod
Re: [PATCH v4] phy: zynqmp: Handle the clock enable/disable properly
On 24-03-21, 17:48, Manish Narani wrote: > The current driver is not handling the clock enable/disable operations > properly. The clocks need to be handled correctly by enabling or > disabling at appropriate places. This patch adds code to handle the > same. Applied, thanks -- ~Vinod
Re: [PATCH v5 (RESEND) 1/7] phy: phy-hi3670-usb3: move driver from staging into phy
On 25-03-21, 19:05, Mauro Carvalho Chehab wrote:
> The phy USB3 driver for Hisilicon 970 (hi3670) is ready
> for mainstream. Mode it from staging into the main driver's
> phy/ directory.
Overall lgtm, some nits below. With those fixed:
Acked-By: Vinod Koul
> +static int hi3670_phy_cr_clk(struct regmap *usb31misc)
> +{
> + int ret;
> +
> + /* Clock up */
> + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
> + CFG54_USB31PHY_CR_CLK, CFG54_USB31PHY_CR_CLK);
> + if (ret)
> + return ret;
> +
> + /* Clock down */
> + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
> + CFG54_USB31PHY_CR_CLK, 0);
> +
> + return ret;
return regmap_update_bits() ?
(i see few more in driver like this, pls change others as well)
> +static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val)
> +{
> + int reg;
> + int i;
> + int ret;
all these could be in a single line
--
~Vinod
Re: [PATCH] phy: hisilicon: Use the correct HiSilicon copyright
On 30-03-21, 14:47, Hao Fang wrote: > s/Hisilicon/HiSilicon/g. > It should use capital S, > according to https://www.hisilicon.com/en/terms-of-use. And I have not agreed to those terms of use! If you wish to change the name, please do send the patch dropping this terms of use link. I dont mind name appearing properly... Thanks > > Signed-off-by: Hao Fang > --- > drivers/phy/hisilicon/phy-hi6220-usb.c | 2 +- > drivers/phy/hisilicon/phy-hix5hd2-sata.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/hisilicon/phy-hi6220-usb.c > b/drivers/phy/hisilicon/phy-hi6220-usb.c > index be05292..e92ba78 100644 > --- a/drivers/phy/hisilicon/phy-hi6220-usb.c > +++ b/drivers/phy/hisilicon/phy-hi6220-usb.c > @@ -1,7 +1,7 @@ > // SPDX-License-Identifier: GPL-2.0-or-later > /* > * Copyright (c) 2015 Linaro Ltd. > - * Copyright (c) 2015 Hisilicon Limited. > + * Copyright (c) 2015 HiSilicon Limited. > */ > > #include > diff --git a/drivers/phy/hisilicon/phy-hix5hd2-sata.c > b/drivers/phy/hisilicon/phy-hix5hd2-sata.c > index c67b78c..b0f99a9 100644 > --- a/drivers/phy/hisilicon/phy-hix5hd2-sata.c > +++ b/drivers/phy/hisilicon/phy-hix5hd2-sata.c > @@ -1,7 +1,7 @@ > // SPDX-License-Identifier: GPL-2.0-or-later > /* > * Copyright (c) 2014 Linaro Ltd. > - * Copyright (c) 2014 Hisilicon Limited. > + * Copyright (c) 2014 HiSilicon Limited. > */ > > #include > -- > 2.8.1 -- ~Vinod
Re: [PATCH v5 0/7] phy: qcom-qmp: provide DP phy support for sm8250
On 28-03-21, 23:52, Dmitry Baryshkov wrote: > Changes since v4: > - Fix typo in the qcom,sc7180-qmp-usb3-phy name in the first patch > > Changes since v3: > - Move qcom,sc7180-qmp-usb3-phy and qcom,sdm845-qmp-usb3-phy from >qcom,qmp-usb3-dp.yaml to qcom,qmp-phy.yaml > - Do not touch qcom,sm8250-qmp-usb3-phy compatible > > Changes since v2: > - Drop unused qmp_v4_usb3_rx_tbl > > Changes since v1: > - Provide dt bindings > - Split register renaming from sm8250-dp-phy patch > - Add respective changes to sm8250 device tree > > The following changes since commit a38fd8748464831584a19438cbb3082b5a2dab15: > > Linux 5.12-rc2 (2021-03-05 17:33:41 -0800) This should be based on phy-next. This fails to apply for me. Can you please rebase and acks and resend Thanks -- ~Vinod
Re: [PATCH] phy: microchip: PHY_SPARX5_SERDES should depend on ARCH_SPARX5
On 31-03-21, 10:19, Geert Uytterhoeven wrote: > The Microchip Sparx5 SerDes PHY is present only Microchip Sparx5 SoCs. > Hence add a dependency on ARCH_SPARX5, to prevent asking the user about > this driver when configuring a kernel without support for Sparx5 SoCs. Applied, thanks -- ~Vinod
Re: [PATCH v2 0/5] j721e-wiz/cadence-torrent: Support to skip SERDES configuration
On 30-03-21, 16:31, Kishon Vijay Abraham I wrote: > Add support to skip SERDES configuration if it's already configured in > bootloader. > > The wiz part was initially sent in [1] but that was sent more in the > context of Sierra but this is in context of Torrent. The Sierra part > would be sent later. Applied, thanks -- ~Vinod
Re: [PATCH v7 00/13] PHY: Add support in Sierra to use external clock
On 19-03-21, 18:11, Kishon Vijay Abraham I wrote: > Patch series adds support in Sierra driver to use external clock. > > v1 of the patch series can be found @ [1] > v2 of the patch series can be found @ [2] > v3 of the patch series can be found @ [3] > v4 of the patch series can be found @ [5] > v5 of the patch series can be found @ [6] > v6 of the patch series can be found @ [7] Applied, thanks. I was able to resolve the conflict on patch 4, please check it was fine -- ~Vinod
Re: [PATCH 00/16] CSI2RX support on J721E
On 30-03-21, 23:03, Pratyush Yadav wrote: > Hi, > > This series adds support for CSI2 capture on J721E. It includes some > fixes to the Cadence CSI2RX driver, adds Rx support to Cadence DPHY > driver, and finally adds the TI CSI2RX wrapper driver. > > Tested on TI's J721E with OV5640 sensor. > > Paul Kocialkowski (1): > phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes > > Pratyush Yadav (15): > phy: cdns-dphy: Prepare for Rx support > phy: cdns-dphy: Allow setting mode > phy: cdns-dphy: Add Rx support > media: cadence: csi2rx: Add external DPHY support > media: cadence: csi2rx: Soft reset the streams before starting capture > media: cadence: csi2rx: Set the STOP bit when stopping a stream > media: cadence: csi2rx: Fix stream data configuration > media: cadence: csi2rx: Turn subdev power on before starting stream > media: cadence: csi2rx: Add wrappers for subdev calls > dmaengine: ti: k3-psil-j721e: Add entry for CSI2RX > dt-bindings: media: Add DT bindings for TI CSI2RX driver > media: ti-vpe: csi2rx: Add CSI2RX support > dt-bindings: phy: Convert Cadence DPHY binding to YAML > dt-bindings: phy: cdns,dphy: make clocks optional > dt-bindings: phy: cdns,dphy: add power-domains property Is there any dependency between patches to various subsystems, if not please do consider sending a series per subsystem... Thanks > > .../devicetree/bindings/media/ti,csi2rx.yaml | 70 ++ > .../devicetree/bindings/phy/cdns,dphy.txt | 20 - > .../devicetree/bindings/phy/cdns,dphy.yaml| 52 + > MAINTAINERS | 7 + > drivers/dma/ti/k3-psil-j721e.c| 10 + > drivers/media/platform/Kconfig| 11 + > drivers/media/platform/cadence/cdns-csi2rx.c | 269 - > drivers/media/platform/ti-vpe/Makefile| 1 + > drivers/media/platform/ti-vpe/ti-csi2rx.c | 964 ++ > drivers/phy/cadence/cdns-dphy.c | 407 +++- > include/linux/phy/phy-mipi-dphy.h | 13 + > 11 files changed, 1754 insertions(+), 70 deletions(-) > create mode 100644 Documentation/devicetree/bindings/media/ti,csi2rx.yaml > delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt > create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml > create mode 100644 drivers/media/platform/ti-vpe/ti-csi2rx.c > > -- > 2.30.0 -- ~Vinod
[PATCH] soundwire: qcom: use signed variable for error return
We get warning for using a unsigned variable being compared to less than zero. The comparison is correct as it checks for errors from previous call to qcom_swrm_get_alert_slave_dev_num(), so we should use a signed variable instead. drivers/soundwire/qcom.c: qcom_swrm_irq_handler() warn: impossible condition '(devnum < 0) => (0-255 < 0)' Reported-by: kernel test robot Signed-off-by: Vinod Koul --- drivers/soundwire/qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index b08ecb9b418c..55ed133c6704 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -428,7 +428,7 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) struct qcom_swrm_ctrl *swrm = dev_id; u32 value, intr_sts, intr_sts_masked, slave_status; u32 i; - u8 devnum = 0; + s8 devnum = 0; int ret = IRQ_HANDLED; swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, _sts); -- 2.26.3
Re: [PATCH 0/4] PHY: Update Cadence Torrent PHY multilink configurations specific to TI
On 04-03-21, 07:08, Swapnil Jakhade wrote: > This patch series updates Torrent PHY driver for multilink configurations > specific to TI platform. It also adds support for configuring QSGMII in > TI Wiz driver. > > This patch series is dependent on [1] and should be applied on > top of this. Applied, thanks -- ~Vinod
Re: [PATCH v3 0/6] AM64: Add SERDES driver support
On 10-03-21, 17:38, Kishon Vijay Abraham I wrote: > AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't > have a clock generator (unlike J7200 base board). Here the clock from > the SERDES has to be routed to the PCIE connector. This series adds > support to drive reference clock output from SERDES and also adds > SERDES (torrent) and SERDES wrapper (WIZ) bindings. > > v1 of the patch series can be found @ [1] > v2 of the patch series can be found @ [3] > > Changes from v2: > *) Sent the DT bindings as a separate series [4] > *) Remove enabling PHY output clock in isolation mode > > Changes from v1: > *) Model the internal clocks without device tree input (Add #clock-cells >to SERDES DT nodes for getting a reference to the clock using index >to phandle). This is in accordance with comment given by Rob [2]. >However the existing method to model clocks from device tree is not >removed to support upstreamed device tree. > *) Included a patch to fix modifying static data by instance specific >initializations. > *) Added a fix to delete "clk_div_sel" clk provider during cleanup Applied, thanks -- ~Vinod
Re: [PATCH v3 0/5] Add support for CP110 UTMI PHY
On 07-03-21, 18:33, kos...@marvell.com wrote: > From: Konstantin Porotchkin > > This series of patches adds a new PHY driver for supporting CP110 UTMI > PHY in Linux. Currently the functionality of USB ports connected to > this PHY depends on boot loader setup. > The new driver eliminates kernel configuration dependency from the boot > loader. Applied 1-3, thanks -- ~Vinod
Re: [PATCH 14/30] Revert "s3c24xx-dma.c: Fix a typo"
On 29-03-21, 05:23, Bhaskar Chowdhury wrote: > s/transferred/transfered/ > > This reverts commit a2ddb8aea8106bd5552f8516ad7a8a26b9282a8f. This is not upstream, why not squash in. Also would make sense to write sensible changelog and not phrases and use the right subsystem conventions! Droped the series now -- ~Vinod
Re: [PATCH v6 0/9] soundwire: qcom: various improvements
On 30-03-21, 15:47, Srinivas Kandagatla wrote: > Thanks for reviewing v5 of this patchset! > > During testing SoundWire controller on SM8250 MTP, we found > few issues like all the interrupts are not handled, > all transport parameters are not read from device tree. > Patch to add Auto Enumeration supported by the controller > is also part of this series. > > Other major issue was register read/writes which was interrupt based > was an overhead and puts lot of limitation on context it can be used from. > > With previous approach number of interrupts generated > after enumeration are around 130: > $ cat /proc/interrupts | grep soundwire > 21: 130 0 0 0 0 0 0 0 GICv3 234 Edge soundwire > > after this patch they are just 3 interrupts > $ cat /proc/interrupts | grep soundwire > 21: 3 0 0 0 0 0 0 0 GICv3 234 Edge soundwire > > So this patchset add various improvements to the existing driver > to address above issues. > > Tested it on SM8250 MTP with 2x WSA881x speakers, HeadPhones on > WCD938x via lpass-rx-macro and Analog MICs via lpass-tx-macro. > Also tested on DragonBoard DB845c with 2xWSA881x speakers. Applied, thanks -- ~Vinod
Re: [PATCH] soundwire: cadence: only prepare attached devices on clock stop
On 23-03-21, 09:37, Bard Liao wrote: > From: Pierre-Louis Bossart > > We sometimes see COMMAND_IGNORED responses during the clock stop > sequence. It turns out we already have information if devices are > present on a link, so we should only prepare those when they > are attached. > > In addition, even when COMMAND_IGNORED are received, we should still > proceed with the clock stop. The device will not be prepared but > that's not a problem. > > The only case where the clock stop will fail is if the Cadence IP > reports an error (including a timeout), or if the devices throw a > COMMAND_FAILED response. Applied, thanks -- ~Vinod
Re: [PATCH v4 4/5] ASoC: dt-bindings: wsa881x: add bindings for port mapping
On 15-03-21, 16:56, Srinivas Kandagatla wrote: > WSA881x SoundWire device ports are statically assigned to master ports > at design time. So add bindings required to specify these mappings! Mark, are you okay for 4, 5 to go thru sdw tree with your ack? The patches lgtm -- ~Vinod
Re: [PATCH v5 6/9] soundwire: qcom: add support to new interrupts
On 26-03-21, 06:39, Srinivas Kandagatla wrote:
> - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);
> + do {
> + for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
> + value = intr_sts_masked & (1 << i);
BIT(i) istead of shifiting?
> + if (!value)
> + continue;
> +
> + switch (value) {
> + case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
> + devnum =
> qcom_swrm_get_alert_slave_dev_num(swrm);
> + if (devnum < 0) {
> + dev_err_ratelimited(swrm->dev,
> + "no slave alert found.spurious
> interrupt\n");
> + } else {
> + sdw_handle_slave_status(>bus,
> swrm->status);
> + }
>
> - if (sts & SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED)
> - complete(>broadcast);
> + break;
> + case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
> + case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
> + dev_err_ratelimited(swrm->dev, "%s: SWR new
> slave attached\n",
> + __func__);
This should be debug
--
~Vinod
Re: [PATCH v5 5/9] soundwire: qcom: update register read/write routine
On 26-03-21, 06:39, Srinivas Kandagatla wrote:
> + swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
> +
> + /* version 1.3 or less */
> + if (swrm->version <= 0x0103)
> + usleep_range(150, 155);
> +
> + if (cmd_id == SWR_BROADCAST_CMD_ID) {
> + /*
> + * sleep for 10ms for MSM soundwire variant to allow broadcast
> + * command to complete.
> + */
> + ret = wait_for_completion_timeout(>broadcast,
> + msecs_to_jiffies(TIMEOUT_MS));
> + if (!ret)
> + ret = SDW_CMD_IGNORED;
> + else
> + ret = SDW_CMD_OK;
>
> - if (!ret) {
> - ret = SDW_CMD_IGNORED;
> - goto err;
> } else {
> ret = SDW_CMD_OK;
> }
Maybe add a comment here that we dont get status so write is assumed to
be OK
--
~Vinod
[PATCH] MAINTAINERS: icc: add interconnect tree
MAINTAINERS entry for ICC is missing the tree details, so add it Signed-off-by: Vinod Koul --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6de606aeb9b1..e3f37d0b6de9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9290,6 +9290,7 @@ INTERCONNECT API M: Georgi Djakov L: linux...@vger.kernel.org S: Maintained +T: git git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc.git F: Documentation/devicetree/bindings/interconnect/ F: Documentation/driver-api/interconnect.rst F: drivers/interconnect/ -- 2.26.3
Re: [PATCH v7 00/14] Tegra XHCI controller ELPG support
On 25-03-21, 15:00, Thierry Reding wrote: > On Thu, Mar 25, 2021 at 11:45:16AM +0530, Vinod Koul wrote: > > On 24-03-21, 14:32, Thierry Reding wrote: > > > Also adding Vinod for visibility and in case Kishon's too busy. > > > > Yes please CC me on all things phy (MAINTAINERS should have told you so) > > > > If you can resend me and cc linux-...@lists.infradead.org, I would take > > a look. FWIW since this goes thru Greg, the window closes earlier than > > merge window > > Greg already agreed that it might be best to take this through the Tegra > tree because there's a bunch of dependencies. For Tegra the patches go > through ARM SoC and that usually means I have to send pull requests by > -rc6. Ok, i dont mind ack'ing in that case once they hit my inbox > JC, do you have time to resend this batch this week? If not I can do it, > too. Thanks -- ~Vinod
Re: [PATCH v4 2/5] phy: Add LVDS configuration options
On 18-03-21, 10:22, Liu Ying wrote: > > Can we have these in kernel-doc style please, similar to style in > > linux/phy/phy.h > > I take this way of in-line member documentation comment for the below 3 > reasons: > > 1) Members of struct phy_configure_opts_mipi_dphy and > struct phy_configure_opts_dp use the same way of comment. > The structures are defined in linux/phy/phy-mipi-dphy.h and > linux/phy/phy-dp.h respectively. > Aligning to them makes a bit sense, IMHO. > > 2) In-line member documentation comments[1] are mentioned in kernel-doc > guide. It says 'The structure members may also be documented in-line > within the definition.'. > > 3) Even the 'configure' and 'validate' members of struct phy_ops use > the same way of comment. struct phy_ops is defined in linux/phy/phy.h. > > [1] > https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#in-line-member-documentation-comments It 'may be' but I would like all headers of a subsystem to display one style. As I said linux/phy/phy.h use a style which we should use everywhere. Thanks -- ~Vinod
Re: [PATCH] phy:qualcomm: remove duplicate argument
On 19-03-21, 04:36, menglong8.d...@gmail.com wrote: > From: Zhang Yunkai > > 'HSUSB_CTRL_DPSEHV_CLAMP' in 'val' is duplicated. Applied, thanks -- ~Vinod
Re: [PATCH] phy: intel: Fix a typo
On 21-03-21, 02:10, Bhaskar Chowdhury wrote: > > s/subsytem/subsystem/ Applied, thanks -- ~Vinod
Re: [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SC7280
On 17-03-21, 16:31, Sandeep Maheswaram wrote: > Add the compatible string for sc7280 SoC from Qualcomm Applied, thanks -- ~Vinod
Re: [PATCH v5 04/13] dt-bindings: phy: mediatek: tphy: change patternProperties
On 16-03-21, 17:22, Chunfeng Yun wrote: > The phy may be named as pcie-phy when the T-PHY only supports > PCIe mode, it's also the similar case for SATA, named as > sata-phy. Applied, thanks -- ~Vinod
Re: [PATCH v5 03/13] dt-bindings: phy: mediatek: hdmi-phy: modify compatible items
On 16-03-21, 17:22, Chunfeng Yun wrote: > mt7623-hdmi-tx is compatible to mt2701-hdmi-tx, and the compatible > "mediatek,mt7623-hdmi-tx" is not supported in driver, in fact uses > "mediatek,mt2701-hdmi-tx" instead on MT7623, so changes the > compatible items to make dependence clear. Applied, thanks -- ~Vinod
Re: [PATCH v5 02/13] dt-bindings: phy: mediatek: dsi-phy: modify compatible dependence
On 16-03-21, 17:22, Chunfeng Yun wrote: > mt7623-mipi-tx is compatible to mt2701-mipi-tx, and use > "mediatek,mt2701-mipi-tx" instead on MT7623, so modify > the compatible items to make dependence clear. Applied, thanks -- ~Vinod
Re: [PATCH v7 00/14] Tegra XHCI controller ELPG support
On 24-03-21, 14:32, Thierry Reding wrote: > On Wed, Mar 24, 2021 at 01:39:32PM +0100, Thierry Reding wrote: > > On Fri, Feb 05, 2021 at 05:22:29PM +0100, Greg KH wrote: > > > On Fri, Feb 05, 2021 at 05:15:21PM +0100, Thierry Reding wrote: > > > > On Wed, Jan 20, 2021 at 03:34:00PM +0800, JC Kuo wrote: > > > > > Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated) > > > > > state for power saving when all of the connected USB devices are in > > > > > suspended state. This patch series includes clk, phy and pmc changes > > > > > that are required for properly place controller in ELPG and bring > > > > > controller out of ELPG. > > > > > > > > > > JC Kuo (14): > > > > > clk: tegra: Add PLLE HW power sequencer control > > > > > clk: tegra: Don't enable PLLE HW sequencer at init > > > > > phy: tegra: xusb: Move usb3 port init for Tegra210 > > > > > phy: tegra: xusb: Rearrange UPHY init on Tegra210 > > > > > phy: tegra: xusb: Add Tegra210 lane_iddq operation > > > > > phy: tegra: xusb: Add sleepwalk and suspend/resume > > > > > soc/tegra: pmc: Provide USB sleepwalk register map > > > > > arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop > > > > > dt-bindings: phy: tegra-xusb: Add nvidia,pmc prop > > > > > phy: tegra: xusb: Add wake/sleepwalk for Tegra210 > > > > > phy: tegra: xusb: Tegra210 host mode VBUS control > > > > > phy: tegra: xusb: Add wake/sleepwalk for Tegra186 > > > > > usb: host: xhci-tegra: Unlink power domain devices > > > > > xhci: tegra: Enable ELPG for runtime/system PM > > > > > > > > > > .../phy/nvidia,tegra124-xusb-padctl.txt |1 + > > > > > arch/arm64/boot/dts/nvidia/tegra210.dtsi |1 + > > > > > drivers/clk/tegra/clk-pll.c | 12 - > > > > > drivers/clk/tegra/clk-tegra210.c | 53 +- > > > > > drivers/phy/tegra/xusb-tegra186.c | 558 - > > > > > drivers/phy/tegra/xusb-tegra210.c | 1889 > > > > > + > > > > > drivers/phy/tegra/xusb.c | 92 +- > > > > > drivers/phy/tegra/xusb.h | 22 +- > > > > > drivers/soc/tegra/pmc.c | 94 + > > > > > drivers/usb/host/xhci-tegra.c | 613 -- > > > > > include/linux/clk/tegra.h |4 +- > > > > > include/linux/phy/tegra/xusb.h| 10 +- > > > > > 12 files changed, 2784 insertions(+), 565 deletions(-) > > > > > > > > > > v5 "phy: tegra: xusb: tegra210: Do not reset UPHY PLL" is moved > > > > > into v6 "phy: tegra: xusb: Rearrange UPHY init on Tegra210" > > > > > > > > Mike, Stephen, > > > > > > > > could you guys take a look at the two clk patches here and give an > > > > Acked-by? There's build-time dependencies throughout the series, so it'd > > > > be good if they can all go through either the PHY or USB trees. > > > > > > > > Kishon, Greg, > > > > > > > > any comments on these patches? Unfortunately, the USB patches in this > > > > series have a build-time dependency on the PHY patches, so this should > > > > all go through one tree. Since this all culminates in the XHCI driver, > > > > merging this through the USB tree might be best, provided that Kishon > > > > provides his Acked-by on the PHY patches. > > > > > > > > Alternatively, I can create a set of branches with the correct > > > > dependencies and send out pull requests for the three subsystems if > > > > that's preferrable. > > > > > > I have no objection for the usb patches to go through your tree as they > > > are hardware-specific. > > > > Kishon, > > > > I haven't heard back from you on this yet. We missed v5.12 but I'd like > > to get this into v5.13 since it's the last missing piece to get suspend > > and resume working properly on a number of boards. > > > > Are you okay if I take this through the Tegra tree to satisfy the > > interdependencies between clk, PHY and USB patches? I've already got > > Acked-by's from the clock and USB maintainers. > > > > I want to tentatively take this into linux-next to give it a bit of soak > > time before the ARM SoC -rc6 cut-off. Please let me know if you'd prefer > > to apply these to your tree so I can back them out of the Tegra tree > > again. > > Also adding Vinod for visibility and in case Kishon's too busy. Yes please CC me on all things phy (MAINTAINERS should have told you so) If you can resend me and cc linux-...@lists.infradead.org, I would take a look. FWIW since this goes thru Greg, the window closes earlier than merge window -- ~Vinod
Re: [PATCH] dt-bindings: mailbox: Add compatible for SM8350 IPCC
On 12-03-21, 11:28, Bjorn Andersson wrote: > On Thu 11 Mar 23:12 CST 2021, Vinod Koul wrote: > > Adding Jassi as recipient. Please let Vinod know if you want him to > resend this patch to you. (I send a patch for MAINTAINERS yesterday) Jassi, should I resend or you can pick from lore? > > > Add the compatible string for SM8350 IPCC block on this SoC > > > > Reviewed-by: Bjorn Andersson > > Regards, > Bjorn > > > Signed-off-by: Vinod Koul > > --- > > Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml > > b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml > > index 168beeb7e9f7..fe17ba9b84f2 100644 > > --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml > > +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml > > @@ -25,6 +25,7 @@ properties: > > items: > >- enum: > >- qcom,sm8250-ipcc > > + - qcom,sm8350-ipcc > >- const: qcom,ipcc > > > >reg: > > -- > > 2.26.2 > > -- ~Vinod
Re: [PATCH] soundwire: intel: move to auxiliary bus
On 23-03-21, 12:29, Pierre-Louis Bossart wrote:
> Thanks Greg and Vinod for the reviews
>
> > > > -static int intel_master_probe(struct platform_device *pdev)
> > > > +static int intel_link_probe(struct auxiliary_device *auxdev, const
> > > > struct auxiliary_device_id *id)
> > > > {
> > > > - struct device *dev = >dev;
> > > > + struct device *dev = >dev;
> > > > + struct sdw_intel_link_dev *ldev =
> > > > auxiliary_dev_to_sdw_intel_link_dev(auxdev);
> > >
> > > Do we need another abstractions for resources here, why not aux dev
> > > creation set the resources required and we skip this step...
>
> Not sure what resources you are referring to?
Resources in the sdw_intel_link_dev which are sdw_intel_link_res. They
should be resources for auxdev and if you do that lets you get rid of
this abstraction.
>
> this is just a container_of() and the documented way of extending the auxbus
> (see
> https://www.kernel.org/doc/html/latest/driver-api/auxiliary_bus.html#example-usage)
>
>
> struct sdw_intel_link_dev {
> struct auxiliary_device auxdev;
> struct sdw_intel_link_res link_res;
> };
>
> #define auxiliary_dev_to_sdw_intel_link_dev(auxiliary_dev) \
> container_of(auxiliary_dev, struct sdw_intel_link_dev, auxdev)
>
> > > > struct sdw_intel *sdw;
> > > > struct sdw_cdns *cdns;
> > > > struct sdw_bus *bus;
> > > > @@ -1346,14 +1347,14 @@ static int intel_master_probe(struct
> > > > platform_device *pdev)
> > > > cdns = >cdns;
> > > > bus = >bus;
> > > > - sdw->instance = pdev->id;
> > > > - sdw->link_res = dev_get_platdata(dev);
> > > > + sdw->instance = auxdev->id;
> > >
> > > so auxdev has id and still we pass id as argument :( Not sure if folks
> > > can fix this now
> >
> > That's odd, yeah, it should be fixed.
>
> I think we are talking about different things?
>
> this is defined in mod_devicetable.h:
>
> struct auxiliary_device_id {
> char name[AUXILIARY_NAME_SIZE];
> kernel_ulong_t driver_data;
> };
>
> and used for the driver probe:
>
> ret = auxdrv->probe(auxdev, auxiliary_match_id(auxdrv->id_table,
> auxdev));
>
> but there is a separate id:
>
> struct auxiliary_device {
> struct device dev;
> const char *name;
> u32 id;
> };
>
> which is set during the device initialization in intel_init.c
>
> /* we don't use an IDA since we already have a link ID */
> auxdev->id = link_id;
>
> In the auxiliary bus design, the parent has to take care of managing this
> id, be it with an IDA or as we do here with a physical link ID that is
> unique.
Aha, maybe both of them should not be 'id' to avoid this confusion!
That also reminds me that we have duplicate info:
+ sdw->instance = auxdev->id;
+ bus->link_id = auxdev->id;
drop the local driver instance and use bus->link_id please
> in short, I don't see how I could change the code given the differences in
> concepts?
--
~Vinod
Re: [PATCH] soundwire: add slave device to linked list after device_register()
On 23-03-21, 10:25, Bard Liao wrote:
> From: Pierre-Louis Bossart
>
> We currently add the slave device to a linked list before
> device_register(), and then remove it if device_register() fails.
>
> It's not clear why this sequence was necessary, this patch moves the
> linked list management to after the device_register().
Maybe add a comment :-)
The reason here is that before calling device_register() we need to be
ready and completely initialized. device_register is absolutely the last
step in the flow, always.
The probe of the device can happen and before you get a chance to
add to list, many number of things can happen.. So adding after is not a
very good idea :)
HTH
>
> Suggested-by: Keyon Jie
> Signed-off-by: Pierre-Louis Bossart
> Reviewed-by: Guennadi Liakhovetski
> Signed-off-by: Bard Liao
> ---
> drivers/soundwire/slave.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soundwire/slave.c b/drivers/soundwire/slave.c
> index 112b21967c7a..0c92db2e1ddc 100644
> --- a/drivers/soundwire/slave.c
> +++ b/drivers/soundwire/slave.c
> @@ -65,9 +65,6 @@ int sdw_slave_add(struct sdw_bus *bus,
> for (i = 0; i < SDW_MAX_PORTS; i++)
> init_completion(>port_ready[i]);
>
> - mutex_lock(>bus_lock);
> - list_add_tail(>node, >slaves);
> - mutex_unlock(>bus_lock);
>
> ret = device_register(>dev);
> if (ret) {
> @@ -77,13 +74,15 @@ int sdw_slave_add(struct sdw_bus *bus,
>* On err, don't free but drop ref as this will be freed
>* when release method is invoked.
>*/
> - mutex_lock(>bus_lock);
> - list_del(>node);
> - mutex_unlock(>bus_lock);
> put_device(>dev);
>
> return ret;
> }
> +
> + mutex_lock(>bus_lock);
> + list_add_tail(>node, >slaves);
> + mutex_unlock(>bus_lock);
> +
> sdw_slave_debugfs_init(slave);
>
> return ret;
> --
> 2.17.1
--
~Vinod
Re: [PATCH 0/5] soundwire: add missing \n in dev_err()
On 23-03-21, 08:58, Bard Liao wrote: > We fixed a lot of warnings in 2019 but the magic of copy-paste keeps > adding new ones... Applied, thanks -- ~Vinod
Re: [PATCH] soundwire: intel: move to auxiliary bus
On 23-03-21, 08:43, Bard Liao wrote:
> From: Pierre-Louis Bossart
>
> Now that the auxiliary_bus exists, there's no reason to use platform
> devices as children of a PCI device any longer.
>
> This patch refactors the code by extending a basic auxiliary device
> with Intel link-specific structures that need to be passed between
> controller and link levels. This refactoring is much cleaner with no
> need for cross-pointers between device and link structures.
>
> Note that the auxiliary bus API has separate init and add steps, which
> requires more attention in the error unwinding paths. The main loop
> needs to deal with kfree() and auxiliary_device_uninit() for the
> current iteration before jumping to the common label which releases
> everything allocated in prior iterations.
>
> Signed-off-by: Pierre-Louis Bossart
> Reviewed-by: Guennadi Liakhovetski
> Reviewed-by: Ranjani Sridharan
> Signed-off-by: Bard Liao
> ---
> drivers/soundwire/Kconfig | 1 +
> drivers/soundwire/intel.c | 52
> drivers/soundwire/intel.h | 14 +-
> drivers/soundwire/intel_init.c | 190 +++-
> include/linux/soundwire/sdw_intel.h | 6 +-
> 5 files changed, 175 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/soundwire/Kconfig b/drivers/soundwire/Kconfig
> index 016e74230bb7..2b7795233282 100644
> --- a/drivers/soundwire/Kconfig
> +++ b/drivers/soundwire/Kconfig
> @@ -25,6 +25,7 @@ config SOUNDWIRE_INTEL
> tristate "Intel SoundWire Master driver"
> select SOUNDWIRE_CADENCE
> select SOUNDWIRE_GENERIC_ALLOCATION
> + select AUXILIARY_BUS
> depends on ACPI && SND_SOC
> help
> SoundWire Intel Master driver.
> diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
> index d2254ee2fee2..039a101982c9 100644
> --- a/drivers/soundwire/intel.c
> +++ b/drivers/soundwire/intel.c
> @@ -11,7 +11,7 @@
> #include
> #include
> #include
> -#include
> +#include
> #include
> #include
> #include
> @@ -1331,9 +1331,10 @@ static int intel_init(struct sdw_intel *sdw)
> /*
> * probe and init
> */
> -static int intel_master_probe(struct platform_device *pdev)
> +static int intel_link_probe(struct auxiliary_device *auxdev, const struct
> auxiliary_device_id *id)
> {
> - struct device *dev = >dev;
> + struct device *dev = >dev;
> + struct sdw_intel_link_dev *ldev =
> auxiliary_dev_to_sdw_intel_link_dev(auxdev);
Do we need another abstractions for resources here, why not aux dev
creation set the resources required and we skip this step...
> struct sdw_intel *sdw;
> struct sdw_cdns *cdns;
> struct sdw_bus *bus;
> @@ -1346,14 +1347,14 @@ static int intel_master_probe(struct platform_device
> *pdev)
> cdns = >cdns;
> bus = >bus;
>
> - sdw->instance = pdev->id;
> - sdw->link_res = dev_get_platdata(dev);
> + sdw->instance = auxdev->id;
so auxdev has id and still we pass id as argument :( Not sure if folks
can fix this now
> + sdw->link_res = >link_res;
> cdns->dev = dev;
> cdns->registers = sdw->link_res->registers;
> cdns->instance = sdw->instance;
> cdns->msg_count = 0;
>
> - bus->link_id = pdev->id;
> + bus->link_id = auxdev->id;
>
> sdw_cdns_probe(cdns);
>
> @@ -1386,10 +1387,10 @@ static int intel_master_probe(struct platform_device
> *pdev)
> return 0;
> }
>
> -int intel_master_startup(struct platform_device *pdev)
> +int intel_link_startup(struct auxiliary_device *auxdev)
> {
> struct sdw_cdns_stream_config config;
> - struct device *dev = >dev;
> + struct device *dev = >dev;
> struct sdw_cdns *cdns = dev_get_drvdata(dev);
> struct sdw_intel *sdw = cdns_to_intel(cdns);
> struct sdw_bus *bus = >bus;
> @@ -1526,9 +1527,9 @@ int intel_master_startup(struct platform_device *pdev)
> return ret;
> }
>
> -static int intel_master_remove(struct platform_device *pdev)
> +static void intel_link_remove(struct auxiliary_device *auxdev)
> {
> - struct device *dev = >dev;
> + struct device *dev = >dev;
> struct sdw_cdns *cdns = dev_get_drvdata(dev);
> struct sdw_intel *sdw = cdns_to_intel(cdns);
> struct sdw_bus *bus = >bus;
> @@ -1544,19 +1545,17 @@ static int intel_master_remove(struct platform_device
> *pdev)
> snd_soc_unregister_component(dev);
> }
> sdw_bus_master_delete(bus);
> -
> - return 0;
> }
>
> -int intel_master_process_wakeen_event(struct platform_device *pdev)
> +int intel_link_process_wakeen_event(struct auxiliary_device *auxdev)
> {
> - struct device *dev = >dev;
> + struct device *dev = >dev;
> struct sdw_intel *sdw;
> struct sdw_bus *bus;
> void __iomem *shim;
> u16 wake_sts;
>
> - sdw = platform_get_drvdata(pdev);
> + sdw = dev_get_drvdata(dev);
No auxdev_get_drvdata() ?
> bus = >cdns.bus;
>
> if
Re: [PATCH v2 1/2] dt-bindings: thermal: qcom-tsens: Add compatible for sm8350
On 22-03-21, 11:04, Robert Foss wrote: > Add tsens bindings for sm8350. Reviewed-by: Vinod Koul -- ~Vinod
Re: [PATCH v2 2/2] arm64: dts: qcom: sm8350: Add thermal zones and throttling support
On 22-03-21, 11:04, Robert Foss wrote: > sm8350 has 29 thermal sensors split across two tsens controllers. Add > the thermal zones to expose them and wireup the cpus to throttle their > frequencies on crossing passive temperature thresholds. Reviewed-by: Vinod Koul -- ~Vinod
Re: [RESEND PATCH v2] soundwire: bus: Fix device found flag correctly
On 09-03-21, 10:48, Srinivas Kandagatla wrote: > found flag is used to indicate SoundWire devices that are > both enumerated on the bus and available in the device list. > However this flag is not reset correctly after one iteration, > This could miss some of the devices that are enumerated on the > bus but not in device list. So reset this correctly to fix this issue! Applied, thanks -- ~Vinod
Re: [PATCH v2 0/3] soundwire: clear bus clash/parity interrupt before the mask is enabled
On 02-03-21, 16:27, Bard Liao wrote: > The SoundWire specification allows a Slave device to report a bus clash > or parity error with the in-band interrupt mechanism. > Unfortunately, on some platforms, these errors are randomly reported and > don't seem to be valid. > This series suggests the addition of a Master level quirk to discard such > interrupts. The quirk should in theory have been added at the Slave level, > but since the problem was detected with different generations of Slave > devices it's hard to point to a specific IP. The problem might also be > board-dependent and hence dealing with a Master quirk is simpler. I think this is fine approach to deal with quirks... Controllers can set the quirk as required. I have fixed up blank line in patch 1 and applied -- ~Vinod
Re: [PATCH v2 1/3] soundwire: add master quirks for bus clash and parity
On 02-03-21, 16:27, Bard Liao wrote:
> Currently quirks are only allowed for Slave devices. This patch
> describes the need for two quirks at the Master level.
>
> a) bus clash
> The SoundWire specification allows a Slave device to report a bus clash
> with the in-band interrupt mechanism when it detects a conflict while
> driving a bitSlot it owns. This can be a symptom of an electrical conflict
> or a programming error, and it's vital to detect reliably.
>
> Unfortunately, on some platforms, bus clashes are randomly reported by
> Slave devices after a bus reset, with an interrupt status set even before
> the bus clash interrupt is enabled. These initial spurious interrupts are
> not relevant and should optionally be filtered out, while leaving the
> interrupt mechanism enabled to detect 'true' issues.
>
> This patch suggests the addition of a Master level quirk to discard such
> interrupts. The quirk should in theory have been added at the Slave level,
> but since the problem was detected with different generations of Slave
> devices it's hard to point to a specific IP. The problem might also be
> board-dependent and hence dealing with a Master quirk is simpler.
>
> b) parity
>
> Additional tests on a new platform with the Maxim 98373 amplifier
> showed a rare case where the parity interrupt is also thrown on
> startup, at the same time as bus clashes. This issue only seems to
> happen infrequently and was only observed during suspend-resume stress
> tests while audio is streaming. We could make the problem go away by
> adding a Slave-level quirk, but there is no evidence that the issue is
> actually a Slave problem: the parity is provided by the Master, which
> could also set an invalid parity in corner cases.
>
> BugLink: https://github.com/thesofproject/linux/issues/2578
> BugLink: https://github.com/thesofproject/linux/issues/2533
>
Please do not add blank lines here
> Co-developed-by: Pierre-Louis Bossart
> Signed-off-by: Pierre-Louis Bossart
> Signed-off-by: Bard Liao
> Reviewed-by: Guennadi Liakhovetski
> ---
> include/linux/soundwire/sdw.h | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h
> index d08039d65825..25f2a14e2e83 100644
> --- a/include/linux/soundwire/sdw.h
> +++ b/include/linux/soundwire/sdw.h
> @@ -405,6 +405,7 @@ struct sdw_slave_prop {
> * command
> * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
> * @hw_disabled: if true, the Master is not functional, typically due to
> pin-mux
> + * @quirks: bitmask identifying optional behavior beyond the scope of the
> MIPI specification
> */
> struct sdw_master_prop {
> u32 revision;
> @@ -421,8 +422,29 @@ struct sdw_master_prop {
> u32 err_threshold;
> u32 mclk_freq;
> bool hw_disabled;
> + u64 quirks;
> };
>
> +/* Definitions for Master quirks */
> +
> +/*
> + * In a number of platforms bus clashes are reported after a hardware
> + * reset but without any explanations or evidence of a real problem.
> + * The following quirk will discard all initial bus clash interrupts
> + * but will leave the detection on should real bus clashes happen
> + */
> +#define SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASHBIT(0)
> +
> +/*
> + * Some Slave devices have known issues with incorrect parity errors
> + * reported after a hardware reset. However during integration unexplained
> + * parity errors can be reported by Slave devices, possibly due to electrical
> + * issues at the Master level.
> + * The following quirk will discard all initial parity errors but will leave
> + * the detection on should real parity errors happen.
> + */
> +#define SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY BIT(1)
> +
> int sdw_master_read_prop(struct sdw_bus *bus);
> int sdw_slave_read_prop(struct sdw_slave *slave);
>
> --
> 2.17.1
--
~Vinod
Re: [PATCH v2 0/3] soundwire: add DMI quirks for overridind addr
On 02-03-21, 15:51, Bard Liao wrote: > Platform firmware may have incorrect _ADR values causing the driver > probes to fail. Adding the override_ops allows people to override the > addr values. Applied, thanks -- ~Vinod
Re: [PATCH v7 1/3] dmaengine: ptdma: Initial driver for the AMD PTDMA
On 18-03-21, 16:16, Sanjay R Mehta wrote: > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > > > > why do you need sched.h here? > > > >> + > >> +#include "ptdma.h" > >> + > >> +/* Ever-increasing value to produce unique unit numbers */ > >> +static atomic_t pt_ordinal; > > > > What is the need of that? > > > [please wrap your emails within 80 chars] > The "pt_ordinal" is incremented for each DMA instances and its number > is used only to assign device name for each instances. This same > device name is passed as a string parameter in many places in code > like while using request_irq(), dma_pool_create() and in debugfs. Why do you need that, why not use device name which is unique..? > Also, I have implemented all of the comments for this patch except > this. if this is fine, will send the next version for review. Am not sure I remember all the comments I gave, it has been _quite_ a while since the feedback was provided. In order to have effective review it would be great to revert back on a reasonable timeline and discuss... Thanks -- ~Vinod
Re: [PATCH 2/3] arm64: dts: qcom: sm8150: add iommus to qups
On 20-03-21, 17:16, Caleb Connolly wrote: > Hi Vinod, > > On 16/03/2021 6:15 am, Vinod Koul wrote: > > On 10-03-21, 16:31, Caleb Connolly wrote: > >> Hook up the SMMU for doing DMA over i2c. Some peripherals like > >> touchscreens easily exceed 32-bytes per transfer, causing errors and > >> lockups without this. > > Why not squash this to patch 1..? > > I thought it made more sense to separate these patches to keep the > history a bit cleaner. I can squash them if you'd prefer. The nodes should be typically added in a single patch, maybe Bjorn is fine with this ;-) -- ~Vinod
Re: [PATCH 0/5] qcom: wcnss: Allow overriding firmware form DT
On 11-03-21, 16:33, Bjorn Andersson wrote: > The wireless subsystem found in Qualcomm MSM8974 and MSM8916 among others > needs > platform-, and perhaps even board-, specific firmware. Add support for > providing this in devicetree. Reviewed-by: Vinod Koul -- ~Vinod
[PATCH v3 2/2] interconnect: qcom: Add SM8350 interconnect provider driver
Add driver for the Qualcomm interconnect buses found in SM8350 based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Generated from downstream interconnect driver written by David Dai Signed-off-by: Vinod Koul --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/sm8350.c | 633 + drivers/interconnect/qcom/sm8350.h | 168 4 files changed, 812 insertions(+) create mode 100644 drivers/interconnect/qcom/sm8350.c create mode 100644 drivers/interconnect/qcom/sm8350.h diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index ca52647f8955..49bc8702782c 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -110,5 +110,14 @@ config INTERCONNECT_QCOM_SM8250 This is a driver for the Qualcomm Network-on-Chip on sm8250-based platforms. +config INTERCONNECT_QCOM_SM8350 + tristate "Qualcomm SM8350 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on SM8350-based + platforms. + config INTERCONNECT_QCOM_SMD_RPM tristate diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index c6a735df067e..93d97e590836 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -12,6 +12,7 @@ qnoc-sdm845-objs := sdm845.o qnoc-sdx55-objs:= sdx55.o qnoc-sm8150-objs := sm8150.o qnoc-sm8250-objs := sm8250.o +qnoc-sm8350-objs := sm8350.o icc-smd-rpm-objs := smd-rpm.o icc-rpm.o obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o @@ -26,4 +27,5 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o +obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c new file mode 100644 index ..f3aab02b8678 --- /dev/null +++ b/drivers/interconnect/qcom/sm8350.c @@ -0,0 +1,633 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + * + */ + +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" +#include "sm8350.h" + +DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A1NOC); +DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A2NOC); +DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC); +DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC); +DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM835
[PATCH v3 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings
The Qualcomm SM8350 platform has several bus fabrics that could be controlled and tuned dynamically according to the bandwidth demand. Signed-off-by: Vinod Koul --- .../bindings/interconnect/qcom,rpmh.yaml | 10 + .../dt-bindings/interconnect/qcom,sm8350.h| 172 ++ 2 files changed, 182 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,sm8350.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 799e73cdb90b..cb6498108b78 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -71,6 +71,16 @@ properties: - qcom,sm8250-mmss-noc - qcom,sm8250-npu-noc - qcom,sm8250-system-noc + - qcom,sm8350-aggre1-noc + - qcom,sm8350-aggre2-noc + - qcom,sm8350-config-noc + - qcom,sm8350-dc-noc + - qcom,sm8350-gem-noc + - qcom,sm8350-lpass-ag-noc + - qcom,sm8350-mc-virt + - qcom,sm8350-mmss-noc + - qcom,sm8350-compute-noc + - qcom,sm8350-system-noc '#interconnect-cells': enum: [ 1, 2 ] diff --git a/include/dt-bindings/interconnect/qcom,sm8350.h b/include/dt-bindings/interconnect/qcom,sm8350.h new file mode 100644 index ..c7f7ed315aeb --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm8350.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm SM8350 interconnect IDs + * + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_1 1 +#define MASTER_A1NOC_CFG 2 +#define MASTER_SDCC_4 3 +#define MASTER_UFS_MEM 4 +#define MASTER_USB3_0 5 +#define MASTER_USB3_1 6 +#define SLAVE_A1NOC_SNOC 7 +#define SLAVE_SERVICE_A1NOC8 + +#define MASTER_QDSS_BAM0 +#define MASTER_QUP_0 1 +#define MASTER_QUP_2 2 +#define MASTER_A2NOC_CFG 3 +#define MASTER_CRYPTO 4 +#define MASTER_IPA 5 +#define MASTER_PCIE_0 6 +#define MASTER_PCIE_1 7 +#define MASTER_QDSS_ETR8 +#define MASTER_SDCC_2 9 +#define MASTER_UFS_CARD10 +#define SLAVE_A2NOC_SNOC 11 +#define SLAVE_ANOC_PCIE_GEM_NOC12 +#define SLAVE_SERVICE_A2NOC13 + +#define MASTER_GEM_NOC_CNOC0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define MASTER_QDSS_DAP2 +#define SLAVE_AHB2PHY_SOUTH3 +#define SLAVE_AHB2PHY_NORTH4 +#define SLAVE_AOSS 5 +#define SLAVE_APPSS6 +#define SLAVE_CAMERA_CFG 7 +#define SLAVE_CLK_CTL 8 +#define SLAVE_CDSP_CFG 9 +#define SLAVE_RBCPR_CX_CFG 10 +#define SLAVE_RBCPR_MMCX_CFG 11 +#define SLAVE_RBCPR_MX_CFG 12 +#define SLAVE_CRYPTO_0_CFG 13 +#define SLAVE_CX_RDPM 14 +#define SLAVE_DCC_CFG 15 +#define SLAVE_DISPLAY_CFG 16 +#define SLAVE_GFX3D_CFG17 +#define SLAVE_HWKM 18 +#define SLAVE_IMEM_CFG 19 +#define SLAVE_IPA_CFG 20 +#define SLAVE_IPC_ROUTER_CFG 21 +#define SLAVE_LPASS22 +#define SLAVE_CNOC_MSS 23 +#define SLAVE_MX_RDPM 24 +#define SLAVE_PCIE_0_CFG 25 +#define SLAVE_PCIE_1_CFG 26 +#define SLAVE_PDM 27 +#define SLAVE_PIMEM_CFG28 +#define SLAVE_PKA_WRAPPER_CFG 29 +#define SLAVE_PMU_WRAPPER_CFG 30 +#define SLAVE_QDSS_CFG 31 +#define SLAVE_QSPI_0 32 +#define SLAVE_QUP_033 +#define SLAVE_QUP_134 +#define SLAVE_QUP_235 +#define SLAVE_SDCC_2 36 +#define SLAVE_SDCC_4 37 +#define SLAVE_SECURITY 38 +#define SLAVE_SPSS_CFG 39 +#define SLAVE_TCSR 40 +#define SLAVE_TLMM 41 +#define SLAVE_UFS_CARD_CFG 42 +#define SLAVE_UFS_MEM_CFG 43 +#define SLAVE_USB3_0 44 +#define SLAVE_USB3_1 45 +#define SLAVE_VENUS_CFG46 +#define SLAVE_VSENSE_CTRL_CFG 47 +#define SLAVE_A1NOC_CFG48 +#define SLAVE_A2NOC_CFG49 +#define SLAVE_DDRSS_CFG
[PATCH v3 0/2] interconnect: qcom: Add SM8350 support
This adds support for interconnect support for SM8350 SoC Changes since v2: - Plug gaps in indexes - fix typo in commit log for patch2 and kconfig depends (for real this time) Changes since v1: - Fix comments by Georgi, split the header - Fix the macro for qns_llcc Vinod Koul (2): dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings interconnect: qcom: Add SM8350 interconnect provider driver .../bindings/interconnect/qcom,rpmh.yaml | 10 + drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile| 2 + drivers/interconnect/qcom/sm8350.c| 633 ++ drivers/interconnect/qcom/sm8350.h| 168 + .../dt-bindings/interconnect/qcom,sm8350.h| 172 + 6 files changed, 994 insertions(+) create mode 100644 drivers/interconnect/qcom/sm8350.c create mode 100644 drivers/interconnect/qcom/sm8350.h create mode 100644 include/dt-bindings/interconnect/qcom,sm8350.h -- 2.26.3
Re: [PATCH v2 2/2] interconnect: qcom: Add SM8350 interconnect provider driver
On 18-03-21, 09:08, Georgi Djakov wrote: > Hi Vinod, > > On 3/2/21 15:43, Vinod Koul wrote: > > Add driver for the Qualcomm interconnect buses found in SM8i350 based > > Still SM8i350? Have you checked my comments on v1? Oops missed to fix the commit log :( > > +config INTERCONNECT_QCOM_SM8350 > > + tristate "Qualcomm SM8350 interconnect driver" > > + depends on INTERCONNECT_QCOM > > + depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST > > Again: depends on INTERCONNECT_QCOM_RPMH_POSSIBLE fixed now > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > Is this used? I need either of_device or of_platform, not both :) I decided to keep of_device and also get rid of device.h Also checked we can remove interconnect.h as interconnect-provider.h already has it. So will send these in next version shortly -- ~Vinod
Re: [PATCH v2 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings
Hello Georgi, On 18-03-21, 09:08, Georgi Djakov wrote: > Hi Vinod, > > +#define MASTER_GEM_NOC_CNOC1 > > Maybe start from zero? Yeah not sure how that got missed > > +#define MASTER_CAMNOC_HF 0 > > +#define MASTER_CAMNOC_ICP 2 > > Why jump from 0 to 2? Fixed now -- ~Vinod
Re: [PATCH v4 2/5] phy: Add LVDS configuration options
On 08-03-21, 11:52, Liu Ying wrote:
> This patch allows LVDS PHYs to be configured through
> the generic functions and through a custom structure
> added to the generic union.
>
> The parameters added here are based on common LVDS PHY
> implementation practices. The set of parameters
> should cover all potential users.
>
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Cc: NXP Linux Team
> Reviewed-by: Robert Foss
> Signed-off-by: Liu Ying
> ---
> v3->v4:
> * Add Robert's R-b tag.
>
> v2->v3:
> * No change.
>
> v1->v2:
> * No change.
>
> include/linux/phy/phy-lvds.h | 48
>
> include/linux/phy/phy.h | 4
> 2 files changed, 52 insertions(+)
> create mode 100644 include/linux/phy/phy-lvds.h
>
> diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h
> new file mode 100644
> index ..1b5b9d6
> --- /dev/null
> +++ b/include/linux/phy/phy-lvds.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2020 NXP
> + */
> +
> +#ifndef __PHY_LVDS_H_
> +#define __PHY_LVDS_H_
> +
> +/**
> + * struct phy_configure_opts_lvds - LVDS configuration set
> + *
> + * This structure is used to represent the configuration state of a
> + * LVDS phy.
> + */
> +struct phy_configure_opts_lvds {
> + /**
> + * @bits_per_lane_and_dclk_cycle:
> + *
> + * Number of bits per data lane and differential clock cycle.
> + */
Can we have these in kernel-doc style please, similar to style in
linux/phy/phy.h
> + unsigned int bits_per_lane_and_dclk_cycle;
> +
> + /**
> + * @differential_clk_rate:
> + *
> + * Clock rate, in Hertz, of the LVDS differential clock.
> + */
> + unsigned long differential_clk_rate;
> +
> + /**
> + * @lanes:
> + *
> + * Number of active, consecutive, data lanes, starting from
> + * lane 0, used for the transmissions.
> + */
> + unsigned int lanes;
> +
> + /**
> + * @is_slave:
> + *
> + * Boolean, true if the phy is a slave which works together
> + * with a master phy to support dual link transmission,
> + * otherwise a regular phy or a master phy.
> + */
> + bool is_slave;
> +};
> +
> +#endif /* __PHY_LVDS_H_ */
> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> index e435bdb..d450b44 100644
> --- a/include/linux/phy/phy.h
> +++ b/include/linux/phy/phy.h
> @@ -17,6 +17,7 @@
> #include
>
> #include
> +#include
> #include
>
> struct phy;
> @@ -51,10 +52,13 @@ enum phy_mode {
> * the MIPI_DPHY phy mode.
> * @dp: Configuration set applicable for phys supporting
> * the DisplayPort protocol.
> + * @lvds:Configuration set applicable for phys supporting
> + * the LVDS phy mode.
> */
> union phy_configure_opts {
> struct phy_configure_opts_mipi_dphy mipi_dphy;
> struct phy_configure_opts_dpdp;
> + struct phy_configure_opts_lvds lvds;
> };
>
> /**
> --
> 2.7.4
--
~Vinod
Re: [PATCH 2/2] phy/rockchip: add Innosilicon-based CSI dphy
On 10-02-21, 22:42, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> The CSI dphy found for example on the rk3326/px30 and rk3368 is based
> on an IP design from Innosilicon. Add a driver for it.
>
> Signed-off-by: Heiko Stuebner
> ---
> drivers/phy/rockchip/Kconfig | 9 +
> drivers/phy/rockchip/Makefile | 1 +
> .../phy/rockchip/phy-rockchip-inno-csidphy.c | 480 ++
> 3 files changed, 490 insertions(+)
> create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
>
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index 159285f42e5c..e812adad7242 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -48,6 +48,15 @@ config PHY_ROCKCHIP_INNO_USB2
> help
> Support for Rockchip USB2.0 PHY with Innosilicon IP block.
>
> +config PHY_ROCKCHIP_INNO_CSIDPHY
> + tristate "Rockchip Innosilicon MIPI CSI PHY driver"
> + depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
> + select GENERIC_PHY
> + select GENERIC_PHY_MIPI_DPHY
> + help
> + Enable this to support the Rockchip MIPI CSI PHY with
> + Innosilicon IP block.
> +
> config PHY_ROCKCHIP_INNO_DSIDPHY
> tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
> depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index c3cfc7f0af5c..f0eec212b2aa 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -2,6 +2,7 @@
> obj-$(CONFIG_PHY_ROCKCHIP_DP)+= phy-rockchip-dp.o
> obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
> obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
> +obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
> obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
> obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
> obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> new file mode 100644
> index ..b30bb2885029
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> @@ -0,0 +1,480 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Rockchip MIPI RX Innosilicon DPHY driver
> + *
> + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
We are in 2021 now :)
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* GRF */
> +#define RK1808_GRF_PD_VI_CON_OFFSET 0x0430
> +
> +#define RK3326_GRF_PD_VI_CON_OFFSET 0x0430
> +
> +#define RK3368_GRF_SOC_CON6_OFFSET 0x0418
> +
> +/* PHY */
> +#define CSIDPHY_CTRL_LANE_ENABLE 0x00
> +#define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6)
> +#define CSIDPHY_CTRL_LANE_ENABLE_LANE3 BIT(5)
> +#define CSIDPHY_CTRL_LANE_ENABLE_LANE2 BIT(4)
> +#define CSIDPHY_CTRL_LANE_ENABLE_LANE1 BIT(3)
> +#define CSIDPHY_CTRL_LANE_ENABLE_LANE0 BIT(2)
> +#define CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED BIT(0)
> +
> +#define CSIDPHY_CTRL_LANE_ENABLE_SHIFT 2
> +
> +/* not present on all variants */
> +#define CSIDPHY_CTRL_PWRCTL 0x04
> +#define CSIDPHY_CTRL_PWRCTL_UNDEFINEDGENMASK(7, 5)
> +#define CSIDPHY_CTRL_PWRCTL_SYNCRST BIT(2)
> +#define CSIDPHY_CTRL_PWRCTL_LDO_PD BIT(1)
> +#define CSIDPHY_CTRL_PWRCTL_PLL_PD BIT(0)
> +
> +#define CSIDPHY_CTRL_DIG_RST 0x80
> +#define CSIDPHY_CTRL_DIG_RST_UNDEFINED 0x1e
> +#define CSIDPHY_CTRL_DIG_RST_RESET BIT(0)
> +
> +/* offset after ths_settle_offset */
> +#define CSIDPHY_CLK_THS_SETTLE 0
> +#define CSIDPHY_LANE_THS_SETTLE(n) ((n + 1) * 0x80)
> +#define CSIDPHY_THS_SETTLE_MASK 0x7f
GENMASK for this?
> +
> +/* offset after calib_offset */
> +#define CSIDPHY_CLK_CALIB_EN 0
> +#define CSIDPHY_LANE_CALIB_EN(n) ((n + 1) * 0x80)
> +#define CSIDPHY_CALIB_EN BIT(7)
> +
> +/* Configure the count time of the THS-SETTLE by protocol. */
> +#define RK1808_CSIDPHY_CLK_WR_THS_SETTLE 0x160
> +#define RK3326_CSIDPHY_CLK_WR_THS_SETTLE 0x100
> +#define RK3368_CSIDPHY_CLK_WR_THS_SETTLE 0x100
> +
> +/* Calibration reception enable */
> +#define RK1808_CSIDPHY_CLK_CALIB_EN 0x168
> +
> +#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
> +
> +enum dphy_reg_id {
> + GRF_DPHY_RX0_TURNDISABLE = 0,
> + GRF_DPHY_RX0_FORCERXMODE,
> + GRF_DPHY_RX0_FORCETXSTOPMODE,
> + GRF_DPHY_RX0_ENABLE,
> + GRF_DPHY_RX0_TURNREQUEST,
> + GRF_DPHY_TX0_TURNDISABLE,
> + GRF_DPHY_TX0_FORCERXMODE,
> +
Re: [PATCH] dt-bindings: Clean-up undocumented compatible strings
On 16-03-21, 13:49, Rob Herring wrote: > --- > .../clock/allwinner,sun4i-a10-pll1-clk.yaml | 2 +- > .../bindings/clock/milbeaut-clock.yaml| 12 + > .../bindings/display/brcm,bcm2835-dsi0.yaml | 6 - > .../bindings/display/panel/panel-dpi.yaml | 2 +- > .../devicetree/bindings/dma/qcom,gpi.yaml | 2 +- ... > .../bindings/phy/ti,phy-j721e-wiz.yaml | 2 +- Acked-By: Vinod Koul -- ~Vinod
Re: [PATCH v15 0/4] Adding the Sparx5 Serdes driver
On 18-02-21, 17:14, Steen Hegelund wrote: > Adding the Sparx5 Serdes driver > > This series of patches provides the serdes driver for the Microchip Sparx5 > ethernet switch. > > The serdes driver supports the 10G and 25G serdes instances available in the > Sparx5. > > The Sparx5 serdes support several interface modes with several speeds and also > allows the client to change the mode and the speed according to changing in > the > environment such as changing cables from DAC to fiber. Applied patch 1 thru 3... thanks -- ~Vinod
Re: [PATCH 08/10] dt-bindings: phy: Add compatible for Mediatek MT8195
On 16-03-21, 19:14, Seiya Wang wrote: > This commit adds dt-binding documentation of UFS M-Phy for Mediatek MT8195 SoC > Platform. Applied, thanks -- ~Vinod
Re: [PATCH 07/10] dt-bindings: phy: Add compatible for Mediatek MT8195
On 16-03-21, 19:14, Seiya Wang wrote: > This commit adds dt-binding documentation of T-Phy for Mediatek MT8195 SoC > Platform. Applied, thanks -- ~Vinod
Re: [PATCH v3] phy: qcom-qmp: add hbr3_hbr2 voltage and premphasis swing table
On 16-03-21, 10:12, Kuogee Hsieh wrote: > Add hbr3_hbr2 voltage and premphasis swing table to support > HBR3 link rate. > > Changes in V2: > -- replaced upper case with lower case at hbr3_hbr2 table > > Changes in v3: > -- replace space with tab at hbr3_hbr2 table This should be after the --- line below > > Signed-off-by: Kuogee Hsieh No need of blank line here > > Reviewed-by: Stephen Boyd I took the liberty of fixing these two, applying the fixes tag and applied.. -- ~Vinod
Re: [PATCH 0/3] AM64: Add SERDES DT bindings
On 10-03-21, 16:57, Kishon Vijay Abraham I wrote: > Patch series adds device tree bindings to support SERDES in AM64 > platform. > > This is split from [1] since this binding is also required for AM64 > USB DT patches to be merged. > > Vinod, > > Once the 1st patch of the series is reviewed by Rob, can you merge and > prepare a immutable tag to be used by Nishant Menon so that he can merge > USB3 DT patches. Applied and tag: git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git tags/ti-serdes-for-5.13 -- ~Vinod
Re: [PATCH v2] scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings
Hello Martin, On 16-03-21, 21:21, Martin K. Petersen wrote: > > Vinod, > > >> Document "qcom,sm8250-ufshc" and "qcom,sm8350-ufshc" compatible string. > >> Use of "qcom,sm8250-ufshc" is already present upstream, so add misiing > >> documentation. "qcom,sm8350-ufshc" is for UFS HC found in SM8350 SoC. > > > > Gentle reminder for this patch, Rob has acked this > > Was not really expecting a DT patch to be routed through SCSI. But no > worries. I've queued it up. Thank you. You can blame MAINTAINERS for pointing it to you :) Typically DT binding go thru subsystem and dts thru soc trees -- ~Vinod
Re: [PATCH v7 00/15] dmaengine: dw-edma: HDMA support
On 18-02-21, 20:03, Gustavo Pimentel wrote: > This patch series adds the HDMA support, as long the IP design has set > the compatible register map parameter, which allows compatibility at > some degree for the existing Synopsys DesignWare eDMA driver that is > already available on the Kernel. > > The HDMA "Hyper-DMA" IP is an enhancement of the eDMA "embedded-DMA" IP. > > This new improvement comes with a PCI DVSEC that allows to the driver > recognize and switch behavior if it's an eDMA or an HDMA, becoming > retrocompatible, in the absence of this DVSEC, the driver will assume > that is an eDMA IP. > > It also adds the interleaved support, since it will be similar to the > current scatter-gather implementation. > > As well fixes/improves some abnormal behaviors not detected before, such as: > - crash on loading/unloading driver > - memory space definition for the data area and for the linked list space > - scatter-gather address calculation on 32 bits platforms > - minor comment and variable reordering Applied, thanks -- ~Vinod
Re: [PATCH 3/3] arm64: dts: qcom: sm8150: add i2c nodes
On 10-03-21, 16:31, Caleb Connolly wrote:
> Tested on the OnePlus 7 Pro (including DMA).
Lgtm:
Reviewed-by: Vinod Koul
But missing enabling nodes in board dts ..?
>
> Signed-off-by: Caleb Connolly
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 521 +++
> 1 file changed, 521 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 543417d74216..0a38ad54c715 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -588,6 +588,111 @@ qupv3_id_0: geniqup@8c {
> #size-cells = <2>;
> ranges;
> status = "disabled";
> +
> + i2c0: i2c@88 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0088 0 0x4000>;
> + clock-names = "se";
> + clocks = < GCC_QUPV3_WRAP0_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c0_default>;
> + interrupts = ;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@884000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00884000 0 0x4000>;
> + clock-names = "se";
> + clocks = < GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c1_default>;
> + interrupts = ;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@888000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00888000 0 0x4000>;
> + clock-names = "se";
> + clocks = < GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c2_default>;
> + interrupts = ;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@88c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0088c000 0 0x4000>;
> + clock-names = "se";
> + clocks = < GCC_QUPV3_WRAP0_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c3_default>;
> + interrupts = ;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@89 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0089 0 0x4000>;
> + clock-names = "se";
> + clocks = < GCC_QUPV3_WRAP0_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_i2c4_default>;
> + interrupts = ;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c5: i2c@894000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00894000 0 0x4000>;
> + clock-names = "se";
> + clocks = < GCC_QUPV3_WRAP0_S5_CLK>;
> + pinctrl-names = "default";
> +
Re: [PATCH 2/3] arm64: dts: qcom: sm8150: add iommus to qups
On 10-03-21, 16:31, Caleb Connolly wrote:
> Hook up the SMMU for doing DMA over i2c. Some peripherals like
> touchscreens easily exceed 32-bytes per transfer, causing errors and
> lockups without this.
Why not squash this to patch 1..?
>
> Signed-off-by: Caleb Connolly
> ---
> Fixes i2c on the OnePlus 7, without this touching the screen with more
> than 4 fingers causes the device to lock up and reboot.
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 03e05d98daf2..543417d74216 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -583,6 +583,7 @@ qupv3_id_0: geniqup@8c {
> clock-names = "m-ahb", "s-ahb";
> clocks = < GCC_QUPV3_WRAP_0_M_AHB_CLK>,
>< GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + iommus = <_smmu 0xc3 0x0>;
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> @@ -595,6 +596,7 @@ qupv3_id_1: geniqup@ac {
> clock-names = "m-ahb", "s-ahb";
> clocks = < GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>< GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> + iommus = <_smmu 0x603 0x0>;
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> @@ -617,6 +619,7 @@ qupv3_id_2: geniqup@cc {
> clock-names = "m-ahb", "s-ahb";
> clocks = < GCC_QUPV3_WRAP_2_M_AHB_CLK>,
>< GCC_QUPV3_WRAP_2_S_AHB_CLK>;
> + iommus = <_smmu 0x7a3 0x0>;
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> --
> 2.29.2
>
--
~Vinod
Re: [PATCH v15 0/4] Adding the Sparx5 Serdes driver
Hello Steen, On 15-03-21, 16:04, Steen Hegelund wrote: > Hi Kishon, Vinod, Andrew, Jacub, and David, > > I just wanted to know if you think that the Generic PHY subsystem might > not be the right place for this Ethernet SerDes PHY driver after all. > > Originally I chose this subsystem for historic reasons: The > Microchip/Microsemi Ocelot SerDes driver was added here when it was > upstreamed. > On the other hand the Ocelot Serdes can do both PCIe and Ethernet, so > it might fit the signature of a generic PHY better. > > At the moment the acceptance of the Sparx5 Serdes driver is blocking us > from adding the Sparx5 SwitchDev driver (to net), so it is really > important for us to resolve which subsystem the Serdes driver belongs > to. > > I am very much looking forward to your response. Generic PHY IMO is the right place for this series, I shall review it shortly and do the needful. I have asked Kishon to check the new phy API and ack it... Thanks -- ~Vinod
Re: [PATCH] dt-bindings: phy: bcm-ns-usb3-phy: convert to yaml
On 11-03-21, 21:31, Rafał Miłecki wrote: > Hi, > > On 16.11.2020 08:46, Rafał Miłecki wrote: > > From: Rafał Miłecki > > > > 1. Change syntax from txt to yaml > > 2. Drop "Driver for" from the title > > 3. Drop "reg = <0x0>;" from example (noticed by dt_binding_check) > > 4. Specify license > > > > Signed-off-by: Rafał Miłecki > > --- > > I think this should go through linux-phy tree. Kishon, Vinod, can you > > take this patch? > > > > This patch generates a false positive checkpatch.pl warning [0]. > > Please ignore: > > WARNING: DT binding docs and includes should be a separate patch. See: > > Documentation/devicetree/bindings/submitting-patches.rst > > > > [0] https://lkml.org/lkml/2020/2/18/1084 > > Kishon, Vinod: I sent this patch back in December, it was Reviewed-by > Rob, but never accepted. > > Could you push this patch to the linux-phy.git? Can you please rebase and resent me this patch. I am trying to streamline patches now using phy ml and pw instance so that we dont miss anything.. Thanks -- ~Vinod
Re: [PATCH -next] phy: ingenic: Fix a typo in ingenic_usb_phy_probe()
On 05-03-21, 03:49, 'Wei Yongjun wrote: > From: Wei Yongjun > > Fix the return value check typo which testing the wrong variable > in ingenic_usb_phy_probe(). Applied, thanks -- ~Vinod
