[PATCH 0/5] arm64: dts: hisi: add NIC, RoCE and SAS support for hip07

2017-04-06 Thread Wei.Xu 
This patch series adds Mbigen, NIC, RoCE and SAS nodes for the hip07
SoC and enables the NIC, RoCE and SAS on the hip07 d05 board.

Wei Xu (5):
  arm64: dts: hisi: add mbigen nodes for the hip07 SoC
  arm64: dts: hisi: add network related nodes for the hip07 SoC
  arm64: dts: hisi: add RoCE nodes for the hip07 SoC
  arm64: dts: hisi: add SAS nodes for the hip07 SoC
  arm64: dts: hisi: enalbe the NIC and SAS for the hip07-d05 board

 arch/arm64/boot/dts/hisilicon/hip07-d05.dts |  24 ++
 arch/arm64/boot/dts/hisilicon/hip07.dtsi| 479 
 2 files changed, 503 insertions(+)

-- 
1.9.1

[PATCH 0/5] arm64: dts: hisi: add NIC, RoCE and SAS support for hip07

2017-04-06 Thread Wei.Xu 
This patch series adds Mbigen, NIC, RoCE and SAS nodes for the hip07
SoC and enables the NIC, RoCE and SAS on the hip07 d05 board.

Wei Xu (5):
  arm64: dts: hisi: add mbigen nodes for the hip07 SoC
  arm64: dts: hisi: add network related nodes for the hip07 SoC
  arm64: dts: hisi: add RoCE nodes for the hip07 SoC
  arm64: dts: hisi: add SAS nodes for the hip07 SoC
  arm64: dts: hisi: enalbe the NIC and SAS for the hip07-d05 board

 arch/arm64/boot/dts/hisilicon/hip07-d05.dts |  24 ++
 arch/arm64/boot/dts/hisilicon/hip07.dtsi| 479 
 2 files changed, 503 insertions(+)

-- 
1.9.1

[PATCH 1/5] arm64: dts: hisi: add mbigen nodes for the hip07 SoC

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Add mbigen nodes for the hip07 SoC those will be used
for the SAS, XGE and PCIe host controllers.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 61 
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi 
b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 5144eb1..6077def 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1014,6 +1014,34 @@
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xa008 0x0 0x1>;
 
+   mbigen_pcie2_a: intc_pcie2_a {
+   msi-parent = <_its_dsa_a 0x40087>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <10>;
+   };
+
+   mbigen_sas1: intc_sas1 {
+   msi-parent = <_its_dsa_a 0x4>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <128>;
+   };
+
+   mbigen_sas2: intc_sas2 {
+   msi-parent = <_its_dsa_a 0x40040>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <128>;
+   };
+
+   mbigen_smmu_pcie: intc_smmu_pcie {
+   msi-parent = <_its_dsa_a 0x40b0c>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <3>;
+   };
+
mbigen_usb: intc_usb {
msi-parent = <_its_dsa_a 0x40080>;
interrupt-controller;
@@ -1022,6 +1050,39 @@
};
};
 
+   p0_mbigen_dsa_a: interrupt-controller@c008 {
+   compatible = "hisilicon,mbigen-v2";
+   reg = <0x0 0xc008 0x0 0x1>;
+
+   mbigen_dsaf0: intc_dsaf0 {
+   msi-parent = <_its_dsa_a 0x40800>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <409>;
+   };
+
+   mbigen_dsa_roce: intc-roce {
+   msi-parent = <_its_dsa_a 0x40B1E>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <34>;
+   };
+
+   mbigen_sas0: intc-sas0 {
+   msi-parent = <_its_dsa_a 0x40900>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <128>;
+   };
+
+   mbigen_smmu_dsa: intc_smmu_dsa {
+   msi-parent = <_its_dsa_a 0x40b20>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <3>;
+   };
+   };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
-- 
1.9.1

[PATCH 1/5] arm64: dts: hisi: add mbigen nodes for the hip07 SoC

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Add mbigen nodes for the hip07 SoC those will be used
for the SAS, XGE and PCIe host controllers.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 61 
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi 
b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 5144eb1..6077def 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1014,6 +1014,34 @@
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xa008 0x0 0x1>;
 
+   mbigen_pcie2_a: intc_pcie2_a {
+   msi-parent = <_its_dsa_a 0x40087>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <10>;
+   };
+
+   mbigen_sas1: intc_sas1 {
+   msi-parent = <_its_dsa_a 0x4>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <128>;
+   };
+
+   mbigen_sas2: intc_sas2 {
+   msi-parent = <_its_dsa_a 0x40040>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <128>;
+   };
+
+   mbigen_smmu_pcie: intc_smmu_pcie {
+   msi-parent = <_its_dsa_a 0x40b0c>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <3>;
+   };
+
mbigen_usb: intc_usb {
msi-parent = <_its_dsa_a 0x40080>;
interrupt-controller;
@@ -1022,6 +1050,39 @@
};
};
 
+   p0_mbigen_dsa_a: interrupt-controller@c008 {
+   compatible = "hisilicon,mbigen-v2";
+   reg = <0x0 0xc008 0x0 0x1>;
+
+   mbigen_dsaf0: intc_dsaf0 {
+   msi-parent = <_its_dsa_a 0x40800>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <409>;
+   };
+
+   mbigen_dsa_roce: intc-roce {
+   msi-parent = <_its_dsa_a 0x40B1E>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <34>;
+   };
+
+   mbigen_sas0: intc-sas0 {
+   msi-parent = <_its_dsa_a 0x40900>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <128>;
+   };
+
+   mbigen_smmu_dsa: intc_smmu_dsa {
+   msi-parent = <_its_dsa_a 0x40b20>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   num-pins = <3>;
+   };
+   };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
-- 
1.9.1

[PATCH 2/5] arm64: dts: hisi: add network related nodes for the hip07 SoC

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Add MDIO, SerDes, Port and realted HNS nodes to support the
network on the hip07 SoC.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 208 +++
 1 file changed, 208 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi 
b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 6077def..2feb362 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1116,5 +1116,213 @@
dma-coherent;
status = "disabled";
};
+
+   peri_c_subctrl: sub_ctrl_c@6000 {
+   compatible = "hisilicon,peri-subctrl","syscon";
+   reg = <0 0x6000 0x0 0x1>;
+   };
+
+   dsa_subctrl: dsa_subctrl@c000 {
+   compatible = "hisilicon,dsa-subctrl", "syscon";
+   reg = <0x0 0xc000 0x0 0x1>;
+   };
+
+   serdes_ctrl: sds_ctrl@c220 {
+   compatible = "syscon";
+   reg = <0 0xc220 0x0 0x8>;
+   };
+
+   mdio@603c {
+   compatible = "hisilicon,hns-mdio";
+   reg = <0x0 0x603c 0x0 0x1000>;
+   subctrl-vbase = <_c_subctrl 0x338 0xa38
+0x531c 0x5a1c>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   phy0: ethernet-phy@0 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <0>;
+   };
+
+   phy1: ethernet-phy@1 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <1>;
+   };
+   };
+
+   dsaf0: dsa@c700 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "hisilicon,hns-dsaf-v2";
+   mode = "6port-16rss";
+   reg = <0x0 0xc500 0x0 0x89
+  0x0 0xc700 0x0 0x60>;
+   reg-names = "ppe-base", "dsaf-base";
+   interrupt-parent = <_dsaf0>;
+   subctrl-syscon = <_subctrl>;
+   reset-field-offset = <0>;
+   interrupts =
+   <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
+   <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
+   <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
+   <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
+   <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
+   <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
+   <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
+   <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
+   <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
+   <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
+   <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
+   <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
+   <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
+   <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
+   <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
+   <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
+   <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
+   <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
+   <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
+   <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
+   <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
+   <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
+   <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
+   <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
+   <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
+   <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
+   <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
+   <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
+   <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
+   <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
+   <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
+   <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
+   <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
+

[PATCH 2/5] arm64: dts: hisi: add network related nodes for the hip07 SoC

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Add MDIO, SerDes, Port and realted HNS nodes to support the
network on the hip07 SoC.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 208 +++
 1 file changed, 208 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi 
b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 6077def..2feb362 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1116,5 +1116,213 @@
dma-coherent;
status = "disabled";
};
+
+   peri_c_subctrl: sub_ctrl_c@6000 {
+   compatible = "hisilicon,peri-subctrl","syscon";
+   reg = <0 0x6000 0x0 0x1>;
+   };
+
+   dsa_subctrl: dsa_subctrl@c000 {
+   compatible = "hisilicon,dsa-subctrl", "syscon";
+   reg = <0x0 0xc000 0x0 0x1>;
+   };
+
+   serdes_ctrl: sds_ctrl@c220 {
+   compatible = "syscon";
+   reg = <0 0xc220 0x0 0x8>;
+   };
+
+   mdio@603c {
+   compatible = "hisilicon,hns-mdio";
+   reg = <0x0 0x603c 0x0 0x1000>;
+   subctrl-vbase = <_c_subctrl 0x338 0xa38
+0x531c 0x5a1c>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   phy0: ethernet-phy@0 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <0>;
+   };
+
+   phy1: ethernet-phy@1 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <1>;
+   };
+   };
+
+   dsaf0: dsa@c700 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "hisilicon,hns-dsaf-v2";
+   mode = "6port-16rss";
+   reg = <0x0 0xc500 0x0 0x89
+  0x0 0xc700 0x0 0x60>;
+   reg-names = "ppe-base", "dsaf-base";
+   interrupt-parent = <_dsaf0>;
+   subctrl-syscon = <_subctrl>;
+   reset-field-offset = <0>;
+   interrupts =
+   <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
+   <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
+   <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
+   <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
+   <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
+   <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
+   <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
+   <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
+   <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
+   <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
+   <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
+   <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
+   <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
+   <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
+   <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
+   <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
+   <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
+   <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
+   <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
+   <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
+   <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
+   <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
+   <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
+   <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
+   <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
+   <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
+   <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
+   <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
+   <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
+   <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
+   <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
+   <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
+   <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
+   <1100 1>, <1101 1>, <1102 1>, <1103 1>,

[PATCH 3/5] arm64: dts: hisi: add RoCE nodes for the hip07 SoC

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Add the infiniband node to support the RoCE function
on the hip07 SoC.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 81 
 1 file changed, 81 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi 
b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 2feb362..bc54b61 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1324,5 +1324,86 @@
status = "disabled";
dma-coherent;
};
+
+   infiniband@c400 {
+   compatible = "hisilicon,hns-roce-v1";
+   reg = <0x0 0xc400 0x0 0x10>;
+   dma-coherent;
+   eth-handle = <  0 0  >;
+   dsaf-handle = <>;
+   node-guid = [00 9A CD 00 00 01 02 03];
+   #address-cells = <2>;
+   #size-cells = <2>;
+   interrupt-parent = <_dsa_roce>;
+   interrupts = <722 1>,
+<723 1>,
+<724 1>,
+<725 1>,
+<726 1>,
+<727 1>,
+<728 1>,
+<729 1>,
+<730 1>,
+<731 1>,
+<732 1>,
+<733 1>,
+<734 1>,
+<735 1>,
+<736 1>,
+<737 1>,
+<738 1>,
+<739 1>,
+<740 1>,
+<741 1>,
+<742 1>,
+<743 1>,
+<744 1>,
+<745 1>,
+<746 1>,
+<747 1>,
+<748 1>,
+<749 1>,
+<750 1>,
+<751 1>,
+<752 1>,
+<753 1>,
+<785 1>,
+<754 4>;
+
+   interrupt-names = "hns-roce-comp-0",
+ "hns-roce-comp-1",
+ "hns-roce-comp-2",
+ "hns-roce-comp-3",
+ "hns-roce-comp-4",
+ "hns-roce-comp-5",
+ "hns-roce-comp-6",
+ "hns-roce-comp-7",
+ "hns-roce-comp-8",
+ "hns-roce-comp-9",
+ "hns-roce-comp-10",
+ "hns-roce-comp-11",
+ "hns-roce-comp-12",
+ "hns-roce-comp-13",
+ "hns-roce-comp-14",
+ "hns-roce-comp-15",
+ "hns-roce-comp-16",
+ "hns-roce-comp-17",
+ "hns-roce-comp-18",
+ "hns-roce-comp-19",
+ "hns-roce-comp-20",
+ "hns-roce-comp-21",
+ "hns-roce-comp-22",
+ "hns-roce-comp-23",
+ "hns-roce-comp-24",
+ "hns-roce-comp-25",
+ "hns-roce-comp-26",
+ "hns-roce-comp-27",
+ "hns-roce-comp-28",
+ "hns-roce-comp-29",
+ "hns-roce-comp-30",
+ "hns-roce-comp-31",
+ "hns-roce-async",
+ "hns-roce-common";
+   };
};
 };
-- 
1.9.1

[PATCH 4/5] arm64: dts: hisi: add SAS nodes for the hip07 SoC

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Add 3 SAS host controller nodes and the dependent subctrl node
to enable the SAS and SATA function for the hip07 SoC.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 129 +++
 1 file changed, 129 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi 
b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index bc54b61..9512f3a 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1127,6 +1127,11 @@
reg = <0x0 0xc000 0x0 0x1>;
};
 
+   pcie_subctl: pcie_subctl@a000 {
+   compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+   reg = <0x0 0xa000 0x0 0x1>;
+   };
+
serdes_ctrl: sds_ctrl@c220 {
compatible = "syscon";
reg = <0 0xc220 0x0 0x8>;
@@ -1405,5 +1410,129 @@
  "hns-roce-async",
  "hns-roce-common";
};
+
+   sas0: sas@c300 {
+   compatible = "hisilicon,hip07-sas-v2";
+   reg = <0 0xc300 0 0x1>;
+   sas-addr = [50 01 88 20 16 00 00 00];
+   hisilicon,sas-syscon = <_subctrl>;
+   ctrl-reset-reg = <0xa60>;
+   ctrl-reset-sts-reg = <0x5a30>;
+   ctrl-clock-ena-reg = <0x338>;
+   queue-count = <16>;
+   phy-count = <8>;
+   dma-coherent;
+   interrupt-parent = <_sas0>;
+   interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+   <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+   <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
+   <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
+   <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
+   <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
+   <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
+   <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
+   <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
+   <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
+   <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
+   <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
+   <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
+   <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
+   <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
+   <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
+   <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
+   <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
+   <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
+   <159 4>,<601 1>,<602 1>,<603 1>,<604 1>,
+   <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
+   <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
+   <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
+   <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
+   <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
+   <630 1>,<631 1>,<632 1>;
+   status = "disabled";
+   };
+
+   sas1: sas@a200 {
+   compatible = "hisilicon,hip07-sas-v2";
+   reg = <0 0xa200 0 0x1>;
+   sas-addr = [50 01 88 20 16 00 00 00];
+   hisilicon,sas-syscon = <_subctl>;
+   hip06-sas-v2-quirk-amt;
+   ctrl-reset-reg = <0xa18>;
+   ctrl-reset-sts-reg = <0x5a0c>;
+   ctrl-clock-ena-reg = <0x318>;
+   queue-count = <16>;
+   phy-count = <8>;
+   dma-coherent;
+   interrupt-parent = <_sas1>;
+   interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+<69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+<74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
+<79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
+<84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
+<89 4>,<90 4>,<91 4>,<92 4>,<93

[PATCH 5/5] arm64: dts: hisi: enalbe the NIC and SAS for the hip07-d05 board

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Enalbe the NIC and SAS nodes for the hip07-d05 board
to support related functions.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 24 
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts 
b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
index e058442..5bdca80 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
@@ -64,3 +64,27 @@
 _ehci {
status = "ok";
 };
+
+ {
+   status = "ok";
+};
+
+ {
+   status = "ok";
+};
+
+ {
+   status = "ok";
+};
+
+ {
+   status = "ok";
+};
+
+_pcie2_a {
+   status = "ok";
+};
+
+ {
+   status = "ok";
+};
-- 
1.9.1

[PATCH 3/5] arm64: dts: hisi: add RoCE nodes for the hip07 SoC

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Add the infiniband node to support the RoCE function
on the hip07 SoC.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 81 
 1 file changed, 81 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi 
b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 2feb362..bc54b61 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1324,5 +1324,86 @@
status = "disabled";
dma-coherent;
};
+
+   infiniband@c400 {
+   compatible = "hisilicon,hns-roce-v1";
+   reg = <0x0 0xc400 0x0 0x10>;
+   dma-coherent;
+   eth-handle = <  0 0  >;
+   dsaf-handle = <>;
+   node-guid = [00 9A CD 00 00 01 02 03];
+   #address-cells = <2>;
+   #size-cells = <2>;
+   interrupt-parent = <_dsa_roce>;
+   interrupts = <722 1>,
+<723 1>,
+<724 1>,
+<725 1>,
+<726 1>,
+<727 1>,
+<728 1>,
+<729 1>,
+<730 1>,
+<731 1>,
+<732 1>,
+<733 1>,
+<734 1>,
+<735 1>,
+<736 1>,
+<737 1>,
+<738 1>,
+<739 1>,
+<740 1>,
+<741 1>,
+<742 1>,
+<743 1>,
+<744 1>,
+<745 1>,
+<746 1>,
+<747 1>,
+<748 1>,
+<749 1>,
+<750 1>,
+<751 1>,
+<752 1>,
+<753 1>,
+<785 1>,
+<754 4>;
+
+   interrupt-names = "hns-roce-comp-0",
+ "hns-roce-comp-1",
+ "hns-roce-comp-2",
+ "hns-roce-comp-3",
+ "hns-roce-comp-4",
+ "hns-roce-comp-5",
+ "hns-roce-comp-6",
+ "hns-roce-comp-7",
+ "hns-roce-comp-8",
+ "hns-roce-comp-9",
+ "hns-roce-comp-10",
+ "hns-roce-comp-11",
+ "hns-roce-comp-12",
+ "hns-roce-comp-13",
+ "hns-roce-comp-14",
+ "hns-roce-comp-15",
+ "hns-roce-comp-16",
+ "hns-roce-comp-17",
+ "hns-roce-comp-18",
+ "hns-roce-comp-19",
+ "hns-roce-comp-20",
+ "hns-roce-comp-21",
+ "hns-roce-comp-22",
+ "hns-roce-comp-23",
+ "hns-roce-comp-24",
+ "hns-roce-comp-25",
+ "hns-roce-comp-26",
+ "hns-roce-comp-27",
+ "hns-roce-comp-28",
+ "hns-roce-comp-29",
+ "hns-roce-comp-30",
+ "hns-roce-comp-31",
+ "hns-roce-async",
+ "hns-roce-common";
+   };
};
 };
-- 
1.9.1

[PATCH 4/5] arm64: dts: hisi: add SAS nodes for the hip07 SoC

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Add 3 SAS host controller nodes and the dependent subctrl node
to enable the SAS and SATA function for the hip07 SoC.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 129 +++
 1 file changed, 129 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi 
b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index bc54b61..9512f3a 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1127,6 +1127,11 @@
reg = <0x0 0xc000 0x0 0x1>;
};
 
+   pcie_subctl: pcie_subctl@a000 {
+   compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+   reg = <0x0 0xa000 0x0 0x1>;
+   };
+
serdes_ctrl: sds_ctrl@c220 {
compatible = "syscon";
reg = <0 0xc220 0x0 0x8>;
@@ -1405,5 +1410,129 @@
  "hns-roce-async",
  "hns-roce-common";
};
+
+   sas0: sas@c300 {
+   compatible = "hisilicon,hip07-sas-v2";
+   reg = <0 0xc300 0 0x1>;
+   sas-addr = [50 01 88 20 16 00 00 00];
+   hisilicon,sas-syscon = <_subctrl>;
+   ctrl-reset-reg = <0xa60>;
+   ctrl-reset-sts-reg = <0x5a30>;
+   ctrl-clock-ena-reg = <0x338>;
+   queue-count = <16>;
+   phy-count = <8>;
+   dma-coherent;
+   interrupt-parent = <_sas0>;
+   interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+   <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+   <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
+   <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
+   <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
+   <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
+   <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
+   <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
+   <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
+   <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
+   <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
+   <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
+   <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
+   <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
+   <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
+   <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
+   <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
+   <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
+   <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
+   <159 4>,<601 1>,<602 1>,<603 1>,<604 1>,
+   <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
+   <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
+   <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
+   <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
+   <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
+   <630 1>,<631 1>,<632 1>;
+   status = "disabled";
+   };
+
+   sas1: sas@a200 {
+   compatible = "hisilicon,hip07-sas-v2";
+   reg = <0 0xa200 0 0x1>;
+   sas-addr = [50 01 88 20 16 00 00 00];
+   hisilicon,sas-syscon = <_subctl>;
+   hip06-sas-v2-quirk-amt;
+   ctrl-reset-reg = <0xa18>;
+   ctrl-reset-sts-reg = <0x5a0c>;
+   ctrl-clock-ena-reg = <0x318>;
+   queue-count = <16>;
+   phy-count = <8>;
+   dma-coherent;
+   interrupt-parent = <_sas1>;
+   interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+<69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+<74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
+<79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
+<84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
+<89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
+<94

[PATCH 5/5] arm64: dts: hisi: enalbe the NIC and SAS for the hip07-d05 board

2017-04-06 Thread Wei.Xu 
From: Wei Xu 

Enalbe the NIC and SAS nodes for the hip07-d05 board
to support related functions.

Signed-off-by: Wei Xu 
---
 arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 24 
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts 
b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
index e058442..5bdca80 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
@@ -64,3 +64,27 @@
 _ehci {
status = "ok";
 };
+
+ {
+   status = "ok";
+};
+
+ {
+   status = "ok";
+};
+
+ {
+   status = "ok";
+};
+
+ {
+   status = "ok";
+};
+
+_pcie2_a {
+   status = "ok";
+};
+
+ {
+   status = "ok";
+};
-- 
1.9.1