[PATCH v1] usb: gadget: Correct NULL pointer checking in fsl gadget

[Yinbo Zhu]

From: Nikhil Badola 

Correct NULL pointer checking for endpoint descriptor
before it gets dereferenced

Signed-off-by: Nikhil Badola 
Signed-off-by: Ran Wang 
Reviewed-by: Peter Chen 
---
 drivers/usb/gadget/udc/fsl_udc_core.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c 
b/drivers/usb/gadget/udc/fsl_udc_core.c
index 381fdff12d4e..980cb1382851 100644
--- a/drivers/usb/gadget/udc/fsl_udc_core.c
+++ b/drivers/usb/gadget/udc/fsl_udc_core.c
@@ -1052,10 +1052,11 @@ static int fsl_ep_fifo_status(struct usb_ep *_ep)
u32 bitmask;
struct ep_queue_head *qh;
 
-   ep = container_of(_ep, struct fsl_ep, ep);
-   if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
+   if (!_ep || _ep->desc || !(_ep->desc->bEndpointAddress&0xF))
return -ENODEV;
 
+   ep = container_of(_ep, struct fsl_ep, ep);
+
udc = (struct fsl_udc *)ep->udc;
 
if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
-- 
2.17.1

[PATCH v1] usb: fsl: Check memory resource before releasing it

[Yinbo Zhu]

From: Nikhil Badola 

Check memory resource existence before releasing it to avoid NULL
pointer dereference

Signed-off-by: Nikhil Badola 
Reviewed-by: Ran Wang 
Reviewed-by: Peter Chen 
---
 drivers/usb/gadget/udc/fsl_udc_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c 
b/drivers/usb/gadget/udc/fsl_udc_core.c
index 20141c3096f6..9a05863b2876 100644
--- a/drivers/usb/gadget/udc/fsl_udc_core.c
+++ b/drivers/usb/gadget/udc/fsl_udc_core.c
@@ -2576,7 +2576,7 @@ static int fsl_udc_remove(struct platform_device *pdev)
dma_pool_destroy(udc_controller->td_pool);
free_irq(udc_controller->irq, udc_controller);
iounmap(dr_regs);
-   if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
+   if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
release_mem_region(res->start, resource_size(res));
 
/* free udc --wait for the release() finished */
-- 
2.17.1

[PATCH v1] usb: fsl: Remove unused variable

[Yinbo Zhu]

From: Nikhil Badola 

Remove unused variable td_complete

Signed-off-by: Nikhil Badola 
Reviewed-by: Ran Wang 
Reviewed-by: Peter Chen 
---
 drivers/usb/gadget/udc/fsl_udc_core.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c 
b/drivers/usb/gadget/udc/fsl_udc_core.c
index 9a05863b2876..381fdff12d4e 100644
--- a/drivers/usb/gadget/udc/fsl_udc_core.c
+++ b/drivers/usb/gadget/udc/fsl_udc_core.c
@@ -1595,14 +1595,13 @@ static int process_ep_req(struct fsl_udc *udc, int pipe,
struct fsl_req *curr_req)
 {
struct ep_td_struct *curr_td;
-   int td_complete, actual, remaining_length, j, tmp;
+   int actual, remaining_length, j, tmp;
int status = 0;
int errors = 0;
struct  ep_queue_head *curr_qh = >ep_qh[pipe];
int direction = pipe % 2;
 
curr_td = curr_req->head;
-   td_complete = 0;
actual = curr_req->req.length;
 
for (j = 0; j < curr_req->dtd_count; j++) {
@@ -1647,11 +1646,9 @@ static int process_ep_req(struct fsl_udc *udc, int pipe,
status = -EPROTO;
break;
} else {
-   td_complete++;
break;
}
} else {
-   td_complete++;
VDBG("dTD transmitted successful");
}
 
-- 
2.17.1

RE: [PATCH v3] arm64: dts: enable otg mode for dwc3 usb ip on layerscape

[Yinbo Zhu]

Hi Shawn Guo,

Please check this version code patch.

Thanks,
Regards,
Yinbo Zhu

-Original Message-
From: Yinbo Zhu  
Sent: 2019年10月8日 10:57
To: Shawn Guo ; Leo Li ; Rob Herring 
; Mark Rutland 
Cc: Yinbo Zhu ; Xiaobo Xie ; Jiafei Pan 
; Ran Wang ; 
linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; 
linux-kernel@vger.kernel.org
Subject: [PATCH v3] arm64: dts: enable otg mode for dwc3 usb ip on layerscape

layerscape otg function should be supported HNP SRP and ADP protocol accroing 
to rm doc, but dwc3 code not realize it and use id pin to detect who is host or 
device(0 is host 1 is device) this patch is to enable OTG mode on ls1028ardb 
ls1088ardb and ls1046ardb in dts

Signed-off-by: Yinbo Zhu 
---
Changed in v3:
updated the patch title with "arm64: dts"

 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4   
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4   
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 1 +
 3 files changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 9fb9113..076cac6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -171,3 +171,7 @@
  {
status = "okay";
 };
+
+ {
+   dr_mode = "otg";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 6a6514d..0c742be 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -122,6 +122,10 @@
};
 };
 
+ {
+   dr_mode = "otg";
+};
+
 #include "fsl-ls1046-post.dtsi"
 
  {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 8e925df..90b1989 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -95,5 +95,6 @@
 };
 
  {
+   dr_mode = "otg";
status = "okay";
 };
--
2.9.5

RE: [EXT] Re: [PATCH v2] usb: dwc3: enable otg mode for dwc3 usb ip on layerscape

[Yinbo Zhu]

-Original Message-
From: Shawn Guo  
Sent: 2019年10月14日 14:52
To: Yinbo Zhu 
Cc: Leo Li ; Rob Herring ; Mark Rutland 
; Xiaobo Xie ; Jiafei Pan 
; Ran Wang ; 
linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; 
linux-kernel@vger.kernel.org
Subject: [EXT] Re: [PATCH v2] usb: dwc3: enable otg mode for dwc3 usb ip on 
layerscape

Caution: EXT Email

On Tue, Sep 24, 2019 at 11:29:03AM +0800, Yinbo Zhu wrote:
> layerscape otg function should be supported HNP SRP and ADP protocol 
> accroing to rm doc, but dwc3 code not realize it and use id pin to 
> detect who is host or device(0 is host 1 is device) this patch is to 
> enable OTG mode on ls1028ardb ls1088ardb and ls1046ardb in dts
>
> Signed-off-by: Yinbo Zhu 
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4   
> arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4   
> arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 1 +

> this is an arm64 DTS patch, so the patch prefix should be something like 
> 'arm64 dts: fsl: ...'

> Shawn 
Hi Shawn guo,

This patch I had updated to v3, please check that v3 version.

Regards,
Yinbo Zhu.
>  3 files changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> index 9fb9113..076cac6 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> @@ -171,3 +171,7 @@
>   {
>   status = "okay";
>  };
> +
> + {
> + dr_mode = "otg";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts 
> b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> index 6a6514d..0c742be 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> @@ -122,6 +122,10 @@
>   };
>  };
>
> + {
> + dr_mode = "otg";
> +};
> +
>  #include "fsl-ls1046-post.dtsi"
>
>   {
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts 
> b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> index 8e925df..90b1989 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> @@ -95,5 +95,6 @@
>  };
>
>   {
> + dr_mode = "otg";
>   status = "okay";
>  };
> --
> 2.9.5
>

[PATCH v3] arm64: dts: enable otg mode for dwc3 usb ip on layerscape

[Yinbo Zhu]

layerscape otg function should be supported HNP SRP and ADP protocol
accroing to rm doc, but dwc3 code not realize it and use id pin to
detect who is host or device(0 is host 1 is device) this patch is to
enable OTG mode on ls1028ardb ls1088ardb and ls1046ardb in dts

Signed-off-by: Yinbo Zhu 
---
Changed in v3:
updated the patch title with "arm64: dts"

 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 
 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 
 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 1 +
 3 files changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 9fb9113..076cac6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -171,3 +171,7 @@
  {
status = "okay";
 };
+
+ {
+   dr_mode = "otg";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 6a6514d..0c742be 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -122,6 +122,10 @@
};
 };
 
+ {
+   dr_mode = "otg";
+};
+
 #include "fsl-ls1046-post.dtsi"
 
  {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 8e925df..90b1989 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -95,5 +95,6 @@
 };
 
  {
+   dr_mode = "otg";
status = "okay";
 };
-- 
2.9.5

RE: [PATCH v2] usb: dwc3: enable otg mode for dwc3 usb ip on layerscape

[Yinbo Zhu]

Hi,

Change in v2:
move the otg property from dtsi to dts.

Regards,
Yinbo Zhu.

-Original Message-
From: Yinbo Zhu  
Sent: 2019年9月24日 11:29
To: Shawn Guo ; Leo Li ; Rob Herring 
; Mark Rutland 
Cc: Yinbo Zhu ; Xiaobo Xie ; Jiafei Pan 
; Ran Wang ; 
linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; 
linux-kernel@vger.kernel.org
Subject: [PATCH v2] usb: dwc3: enable otg mode for dwc3 usb ip on layerscape

layerscape otg function should be supported HNP SRP and ADP protocol accroing 
to rm doc, but dwc3 code not realize it and use id pin to detect who is host or 
device(0 is host 1 is device) this patch is to enable OTG mode on ls1028ardb 
ls1088ardb and ls1046ardb in dts

Signed-off-by: Yinbo Zhu 
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4   
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4   
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 1 +
 3 files changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 9fb9113..076cac6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -171,3 +171,7 @@
  {
status = "okay";
 };
+
+ {
+   dr_mode = "otg";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 6a6514d..0c742be 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -122,6 +122,10 @@
};
 };
 
+ {
+   dr_mode = "otg";
+};
+
 #include "fsl-ls1046-post.dtsi"
 
  {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 8e925df..90b1989 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -95,5 +95,6 @@
 };
 
  {
+   dr_mode = "otg";
status = "okay";
 };
--
2.9.5

[PATCH v2] usb: dwc3: enable otg mode for dwc3 usb ip on layerscape

[Yinbo Zhu]

layerscape otg function should be supported HNP SRP and ADP protocol
accroing to rm doc, but dwc3 code not realize it and use id pin to
detect who is host or device(0 is host 1 is device) this patch is to
enable OTG mode on ls1028ardb ls1088ardb and ls1046ardb in dts

Signed-off-by: Yinbo Zhu 
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 
 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 
 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 1 +
 3 files changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 9fb9113..076cac6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -171,3 +171,7 @@
  {
status = "okay";
 };
+
+ {
+   dr_mode = "otg";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 6a6514d..0c742be 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -122,6 +122,10 @@
};
 };
 
+ {
+   dr_mode = "otg";
+};
+
 #include "fsl-ls1046-post.dtsi"
 
  {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 8e925df..90b1989 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -95,5 +95,6 @@
 };
 
  {
+   dr_mode = "otg";
status = "okay";
 };
-- 
2.9.5

RE: [EXT] Re: [PATCH v5] arm64: dts: ls1028a: Add esdhc node in dts

[Yinbo Zhu]

Hi Shawn Guo,

I see that you had merged my patch, but I don't see that in 
url = git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git master 
branch.
Please help check.

Regards,
Yinbo Zhu
-Original Message-
From: Shawn Guo  
Sent: 2019年8月19日 21:11
To: Yinbo Zhu 
Cc: Leo Li ; Rob Herring ; Mark Rutland 
; linux-arm-ker...@lists.infradead.org; 
devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Xiaobo Xie 
; Jiafei Pan ; Y.b. Lu 
; Ashish Kumar 
Subject: [EXT] Re: [PATCH v5] arm64: dts: ls1028a: Add esdhc node in dts

Caution: EXT Email

On Thu, Aug 15, 2019 at 11:39:01AM +0800, Yinbo Zhu wrote:
> From: Ashish Kumar 
>
> This patch is to add esdhc node and enable SD UHS-I, eMMC HS200 for 
> ls1028ardb/ls1028aqds board.
>
> Signed-off-by: Ashish Kumar 
> Signed-off-by: Yangbo Lu 
> Signed-off-by: Yinbo Zhu 

Applied, thanks.

[PATCH v1] usb: dwc3: enable otg mode for dwc3 usb ip on layerscape

[Yinbo Zhu]

layerscape otg function should be supported HNP SRP and ADP protocol
accroing to rm doc, but dwc3 code not realize it and use id pin to
detect who is host or device(0 is host 1 is device) this patch is to
enable OTG mode on ls1028ardb ls1088ardb and ls1046ardb in dts

Signed-off-by: Yinbo Zhu 
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 7975519b4f56..5810d0400dbc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -320,7 +320,7 @@
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x311 0x0 0x1>;
interrupts = ;
-   dr_mode = "host";
+   dr_mode = "otg";
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index b0ef08b090dd..ecce6151b9b0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -582,7 +582,7 @@
compatible = "snps,dwc3";
reg = <0x0 0x300 0x0 0x1>;
interrupts = ;
-   dr_mode = "host";
+   dr_mode = "otg";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index dacd8cf03a7f..4b5413f7c90c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -385,7 +385,7 @@
compatible = "snps,dwc3";
reg = <0x0 0x311 0x0 0x1>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
-   dr_mode = "host";
+   dr_mode = "otg";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
status = "disabled";
-- 
2.17.1

RE: [EXT] Re: [PATCH v1] usb: dwc3: remove the call trace of USBx_GFLADJ

[Yinbo Zhu]

Hi Balbi,

If no other doubts, please help apply it.

Thanks,
Regards,
Yinbo Zhu.

-Original Message-
From: Felipe Balbi  
Sent: 2019年8月27日 19:55
To: Ran Wang ; Yinbo Zhu ; Greg 
Kroah-Hartman ; linux-...@vger.kernel.org; open 
list 
Cc: Xiaobo Xie ; Jiafei Pan 
Subject: RE: [EXT] Re: [PATCH v1] usb: dwc3: remove the call trace of 
USBx_GFLADJ


Hi,

Ran Wang  writes:
>> Yinbo Zhu  writes:
>> >> Yinbo Zhu  writes:
>> >> >> > diff --git a/drivers/usb/dwc3/core.c 
>> >> >> > b/drivers/usb/dwc3/core.c index
>> >> >> > 98bce85c29d0..a133d8490322 100644
>> >> >> > --- a/drivers/usb/dwc3/core.c
>> >> >> > +++ b/drivers/usb/dwc3/core.c
>> >> >> > @@ -300,8 +300,7 @@ static void 
>> >> >> > dwc3_frame_length_adjustment(struct
>> >> >> > dwc3 *dwc)
>> >> >> >
>> >> >> >   reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
>> >> >> >   dft = reg & DWC3_GFLADJ_30MHZ_MASK;
>> >> >> > - if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
>> >> >> > - "request value same as default, ignoring\n")) {
>> >> >> > + if (dft != dwc->fladj) {
>> >> >>
>> >> >> if the value isn't different, why do you want to change it?
>> >> >>
>> >> >> --
>> >> >> Balbi
>> >> > Hi Balbi,
>> >> >
>> >> > I don't change any value. I was remove that call trace.
>> >>
>> >> Sure you do. The splat only shows when you request a FLADJ value 
>> >> that's the same as the one already in the register. The reason you 
>> >> see the splat is because your requested value is what's already in the HW.
>> >>
>> >> So, again, why are you adding this device tree property if the 
>> >> value is already the correct one?
>> >>
>> >> > In addition that GFLADJ_30MHZ value intial value is 0, and it's 
>> >> > value must be 0x20, if not, usb will not work.
>> >>
>> >> it's not zero, otherwise the splat wouldn't trigger. You're 
>> >> requesting the value that's already in your register by default.
>> >>
>> >> --
>> >> Balbi
>> >
>> > Hi Balbi,
>> >
>> > According that rm doc that GFLADJ_30MHZ has a default value is 
>> > 0x20, when GFLADJ_30MHZ_REG_SEL is 0, this 0x20 is a hard-coded value.
>> >
>> > But in fact, that default value is 0, please you note!
>> >
>> > Then according that xhci spec 5.2.4, that register the sixth bit if 
>> > is 0, then that can support Frame Lenth Timing value.
>> >
>> > So set GFLADJ_30MHZ_REG_SEL to 1 for use FLADJ, then I find that it 
>> > must use 0x20 usb will work well, even thoug xhci can permit 
>> > GFLADJ_30MHZ use other value
>> 
>> You only get the splat because you try to sent GFLADJ to 0x20 and 
>> it's ALREADY 0x20. This means that you don't need the property in DTS.
>> 
>> > In addition about what you said is about dts patch, and that patch 
>> > had merged by upstream, patch owner isn't me,
>> 
>> Well, then remove the setting from DTS, since clearly it's not needed.
>
> Please considering below scenarios on the same board which needs GFLADJ 
> property on kernel DTS:
>
> 1. Board boot to U-Boot first, then load kernel. In this case, we need kernel 
> DTS
> help to get GFLADJ setting right, everything is as expected.
>
> 2. Board boot to U-Boot console, then execute 'usb start' under U-Boot 
> console to init
> DWC3 controller, then load kernel. In this case, actually GFLADJ is 
> correctly
> configured already, and the GFLADJ config double-checking is fine 
> (because kernel
> cannot know if U-Boot has initialized it or not), but warning looks not 
> necessary.
>
> 3. Board boot to kernel, GFLADJ get set from DTS, then system suspend & 
> resume. In this case
> when resuming, GFLADJ setting has been restored correctly, so here we 
> might not need
> send out the warning message (double-checking might be fine).
>
> So, what's your suggestion to remove this looks non-necessary warning message?

now this is well explained! So the value in the register is *NOT* 0x20 by 
default, however, u-boot _can_ use dwc3 if we're flashing, then it'll result in 
the splat.

Okay, this is a valid scenario that the kernel should consider. I agree that we 
should remove the WARN() from there.

Thanks

--
balbi

[PATCH v5] arm64: dts: ls1028a: Add esdhc node in dts

[Yinbo Zhu]

From: Ashish Kumar 

This patch is to add esdhc node and enable SD UHS-I,
eMMC HS200 for ls1028ardb/ls1028aqds board.

Signed-off-by: Ashish Kumar 
Signed-off-by: Yangbo Lu 
Signed-off-by: Yinbo Zhu 
---
Change in v5:
Fix indent.

 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |  8 +++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 13 +++
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi| 27 +++
 3 files changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index de6ef39..5e14e5a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -95,6 +95,14 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 9fb9113..1a69221 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -83,6 +83,19 @@
};
 };
 
+ {
+   sd-uhs-sdr104;
+   sd-uhs-sdr50;
+   sd-uhs-sdr25;
+   sd-uhs-sdr12;
+   status = "okay";
+};
+
+ {
+   mmc-hs200-1_8v;
+   status = "okay";
+};
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 7975519..f299075 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -245,6 +245,33 @@
status = "disabled";
};
 
+   esdhc: mmc@214 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x214 0x0 0x1>;
+   interrupts = ;
+   clock-frequency = <0>; /* fixed up by bootloader */
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
+   esdhc1: mmc@215 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x215 0x0 0x1>;
+   interrupts = ;
+   clock-frequency = <0>; /* fixed up by bootloader */
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   broken-cd;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
-- 
2.9.5

[PATCH v1 2/4] soc: fsl: guts: Add definition for LS1028A

[Yinbo Zhu]

Adding compatible string "ls1028a-dcfg" to initialize guts driver
for ls1028 and SoC die attribute definition for LS1028A

Signed-off-by: Yinbo Zhu 
---
 drivers/soc/fsl/guts.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 1ef8068c8dd3..34810f9bb2ee 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -102,6 +102,11 @@ static const struct fsl_soc_die_attr fsl_soc_die[] = {
  .svr  = 0x8736,
  .mask = 0xff3f,
},
+   /* Die: LS1028A, SoC: LS1028A */
+   { .die  = "LS1028A",
+ .svr  = 0x870b,
+ .mask = 0xff3f,
+   },
{ },
 };
 
@@ -224,6 +229,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
{ .compatible = "fsl,ls1012a-dcfg", },
{ .compatible = "fsl,ls1046a-dcfg", },
{ .compatible = "fsl,lx2160a-dcfg", },
+   { .compatible = "fsl,ls1028a-dcfg", },
{}
 };
 MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
-- 
2.17.1

[PATCH v1 1/4] arm64: dts: ls1028a-rdb: enable emmc hs400 mode

[Yinbo Zhu]

This patch is to enable emmc hs400 mode for ls1028ardb

Signed-off-by: Yinbo Zhu 
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 8a725409e881..f1e46cc4cea1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -92,8 +92,10 @@
};
 
  {
-   status = "okay";
mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   bus-width = <8>;
+   status = "okay";
};
 
  {
-- 
2.17.1

[PATCH v1 4/4] mmc: sdhci-of-esdhc: add erratum A011334 support in ls1028a 1.0 SoC

[Yinbo Zhu]

This patch is to add erratum A011334 support in ls1028a 1.0 SoC

Signed-off-by: Yinbo Zhu 
---
 drivers/mmc/host/sdhci-of-esdhc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c 
b/drivers/mmc/host/sdhci-of-esdhc.c
index b16f7d440f78..eb2b290447fc 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -1006,6 +1006,7 @@ static struct soc_device_attribute 
soc_incorrect_hostver[] = {
 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
{ .family = "QorIQ LX2160A", .revision = "1.0", },
{ .family = "QorIQ LX2160A", .revision = "2.0", },
+   { .family = "QorIQ LS1028A", .revision = "1.0", },
{ },
 };
 
-- 
2.17.1

[PATCH v1 3/4] arm64: dts: ls1028a: fix little-big endian issue for dcfg

[Yinbo Zhu]

dcfg use little endian that SoC register value will be correct

Signed-off-by: Yinbo Zhu 
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index b0d4f8916ede..5538e8e354b2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -162,7 +162,7 @@
dcfg: syscon@1e0 {
compatible = "fsl,ls1028a-dcfg", "syscon";
reg = <0x0 0x1e0 0x0 0x1>;
-   big-endian;
+   little-endian;
};
 
scfg: syscon@1fc {
-- 
2.17.1

[PATCH v4] arm64: dts: ls1028a: Add esdhc node in dts

[Yinbo Zhu]

From: Ashish Kumar 

This patch is to add esdhc node and enable SD UHS-I,
eMMC HS200 for ls1028ardb/ls1028aqds board.

Signed-off-by: Ashish Kumar 
Signed-off-by: Yangbo Lu 
Signed-off-by: Yinbo Zhu 
---
Change in v4:
put esdhc 'status' at end of property list.
sort the nodes in unit-address
Use IRQ_TYPE_LEVEL_HIGH represent 0x4 in "interrupts = <0 28 
0x4>"

 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |  8 +++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 13 +++
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi| 27 +++
 3 files changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index de6ef39..5e14e5a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -95,6 +95,14 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 9fb9113..12c9cd3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -83,6 +83,19 @@
};
 };
 
+ {
+   sd-uhs-sdr104;
+   sd-uhs-sdr50;
+   sd-uhs-sdr25;
+   sd-uhs-sdr12;
+   status = "okay";
+   };
+
+ {
+   mmc-hs200-1_8v;
+   status = "okay";
+   };
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 7975519..f299075 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -245,6 +245,33 @@
status = "disabled";
};
 
+   esdhc: mmc@214 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x214 0x0 0x1>;
+   interrupts = ;
+   clock-frequency = <0>; /* fixed up by bootloader */
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
+   esdhc1: mmc@215 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x215 0x0 0x1>;
+   interrupts = ;
+   clock-frequency = <0>; /* fixed up by bootloader */
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   broken-cd;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
-- 
2.9.5

RE: [PATCH v3] arm64: dts: ls1028a: Add esdhc node in dts

[Yinbo Zhu]

Hi, 

I just check mmc upstream code, that patch still not upstream.
Please help merge it to upstream tree.

Thanks
Regards,
Yinbo Zhu

> -Original Message-
> From: Yinbo Zhu [mailto:yinbo@nxp.com]
> Sent: 2019年5月15日 16:49
> To: Shawn Guo ; Leo Li ; Rob
> Herring 
> Cc: Yinbo Zhu ; Xiaobo Xie ; Mark
> Rutland ; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-...@vger.kernel.org; Y.b. Lu ; Jiafei Pan
> ; Ashish Kumar 
> Subject: [PATCH v3] arm64: dts: ls1028a: Add esdhc node in dts
> 
> From: Ashish Kumar 
> 
> This patch is to add esdhc node and enable SD UHS-I, eMMC HS200 for
> ls1028ardb/ls1028aqds board.
> 
> Signed-off-by: Ashish Kumar 
> Signed-off-by: Yangbo Lu 
> Signed-off-by: Yinbo Zhu 
> ---
> Change in v3:
>   replace "esdhc@" with "mmc@"
> 
>  arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |8 ++
>  arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts |   13 ++
>  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi|   27
> +
>  3 files changed, 48 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> index 14c79f4..180e5d2 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> @@ -42,6 +42,14 @@
>   status = "okay";
>  };
> 
> + {
> + status = "okay";
> +};
> +
> + {
> + status = "okay";
> +};
> +
>   {
>   status = "okay";
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> index f86b054..1bfaf42 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> @@ -30,6 +30,19 @@
>   };
>  };
> 
> + {
> + status = "okay";
> + sd-uhs-sdr104;
> + sd-uhs-sdr50;
> + sd-uhs-sdr25;
> + sd-uhs-sdr12;
> + };
> +
> + {
> + status = "okay";
> + mmc-hs200-1_8v;
> + };
> +
>   {
>   status = "okay";
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 2896bbc..462833c 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -274,6 +274,33 @@
>   status = "disabled";
>   };
> 
> + esdhc: mmc@214 {
> + compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
> + reg = <0x0 0x214 0x0 0x1>;
> + interrupts = <0 28 0x4>; /* Level high type */
> + clock-frequency = <0>; /* fixed up by bootloader */
> + clocks = < 2 1>;
> + voltage-ranges = <1800 1800 3300 3300>;
> + sdhci,auto-cmd12;
> + little-endian;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + esdhc1: mmc@215 {
> + compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
> + reg = <0x0 0x215 0x0 0x1>;
> + interrupts = <0 63 0x4>; /* Level high type */
> + clock-frequency = <0>; /* fixed up by bootloader */
> + clocks = < 2 1>;
> + voltage-ranges = <1800 1800 3300 3300>;
> + sdhci,auto-cmd12;
> + broken-cd;
> + little-endian;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
>   sata: sata@320 {
>   compatible = "fsl,ls1028a-ahci";
>   reg = <0x0 0x320 0x0 0x1>,
> --
> 1.7.1

[PATCH v8 1/5] usb: fsl: Set USB_EN bit to select ULPI phy

[Yinbo Zhu]

From: Nikhil Badola 

Set USB_EN bit to select ULPI phy for USB controller version 2.5

Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
Change in v2:
replace Yinbo.Zhu with Yinbo Zhu. 
Change in v3:
Code base already has patch[5/6], so remove it.
Change in v4:
Incorrect indentation of the continuation line.

 drivers/usb/host/ehci-fsl.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index e3d0c1c25160..38674b7aa51e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -122,6 +122,12 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
tmp |= 0x4;
iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
}
+
+   /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
+   if (pdata->controller_ver == FSL_USB_VER_2_5 &&
+   pdata->phy_mode == FSL_USB2_PHY_ULPI)
+   iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
+
/*
 * Enable UTMI phy and program PTS field in UTMI mode before asserting
 * controller reset for USB Controller version 2.5
-- 
2.17.1

[PATCH v8 2/5] usb: phy: Workaround for USB erratum-A005728

[Yinbo Zhu]

From: Suresh Gupta 

PHY_CLK_VALID bit for UTMI PHY in USBDR does not set even
if PHY is providing valid clock. Workaround for this
involves resetting of PHY and check PHY_CLK_VALID bit
multiple times. If PHY_CLK_VALID bit is still not set even
after 5 retries, it would be safe to deaclare that PHY
clock is not available.
This erratum is applicable for USBDR less then ver 2.4.

Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
Change in v2:
replace Yinbo.Zhu with Yinbo Zhu.
Change in v3:
replace in_be32 with ioread32be.
Change in v4:
Incorrect indentation of the continuation line.
replace pr_err with dev_err.
Change in v5:
remove dev_err function unnecessary parameters.

 drivers/usb/host/ehci-fsl.c | 37 ++---
 drivers/usb/host/ehci-fsl.h |  3 +++
 2 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 38674b7aa51e..8f3bf3efb038 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -183,6 +183,17 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
return retval;
 }
 
+static bool usb_phy_clk_valid(struct usb_hcd *hcd)
+{
+   void __iomem *non_ehci = hcd->regs;
+   bool ret = true;
+
+   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
+   ret = false;
+
+   return ret;
+}
+
 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
   enum fsl_usb2_phy_modes phy_mode,
   unsigned int port_offset)
@@ -226,6 +237,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
/* fall through */
case FSL_USB2_PHY_UTMI:
case FSL_USB2_PHY_UTMI_DUAL:
+   /* PHY_CLK_VALID bit is de-featured from all controller
+* versions below 2.4 and is to be checked only for
+* internal UTMI phy
+*/
+   if (pdata->controller_ver > FSL_USB_VER_2_4 &&
+   pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
+   dev_err(dev, "USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
@@ -249,17 +270,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
 
-   /*
-* check PHY_CLK_VALID to determine phy clock presence before writing
-* to portsc
-*/
-   if (pdata->check_phy_clk_valid) {
-   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
-   PHY_CLK_VALID)) {
-   dev_warn(hcd->self.controller,
-"USB PHY clock invalid\n");
-   return -EINVAL;
-   }
+   if (pdata->have_sysif_regs &&
+   pdata->controller_ver > FSL_USB_VER_1_6 &&
+   !usb_phy_clk_valid(hcd)) {
+   dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
+   return -EINVAL;
}
 
ehci_writel(ehci, portsc, >regs->port_status[port_offset]);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index cbc422032e50..9d18c6e6ab27 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -50,4 +50,7 @@
 #define UTMI_PHY_EN (1<<9)
 #define ULPI_PHY_CLK_SEL(1<<10)
 #define PHY_CLK_VALID  (1<<17)
+
+/* Retry count for checking UTMI PHY CLK validity */
+#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
 #endif /* _EHCI_FSL_H */
-- 
2.17.1

[PATCH v8 5/5] usb :fsl: Change string format for errata property

[Yinbo Zhu]

From: Nikhil Badola 

Remove USB errata checking code from driver. Applicability of erratum
is retrieved by reading corresponding property in device tree.
This property is written during device tree fixup.

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/fsl-mph-dr-of.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 762b97600ab0..ae8f60f6e6a5 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -226,11 +226,8 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device 
*ofdev)
of_property_read_bool(np, "fsl,usb_erratum-a005697");
pdata->has_fsl_erratum_a006918 =
of_property_read_bool(np, "fsl,usb_erratum-a006918");
-
-   if (of_get_property(np, "fsl,usb_erratum_14", NULL))
-   pdata->has_fsl_erratum_14 = 1;
-   else
-   pdata->has_fsl_erratum_14 = 0;
+   pdata->has_fsl_erratum_14 =
+   of_property_read_bool(np, "fsl,usb_erratum-14");
 
/*
 * Determine whether phy_clk_valid needs to be checked
-- 
2.17.1

[PATCH v8 3/5] usb: linux/fsl_device: Add platform member has_fsl_erratum_a006918

[Yinbo Zhu]

This patch is to add member has_fsl_erratum_a006918 in platform data

Signed-off-by: Yinbo Zhu 
---
 include/linux/fsl_devices.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index cb2b46f57af3..5d231ce8709b 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -98,6 +98,7 @@ struct fsl_usb2_platform_data {
unsignedhas_fsl_erratum_14:1;
unsignedhas_fsl_erratum_a005275:1;
unsignedhas_fsl_erratum_a005697:1;
+   unsignedhas_fsl_erratum_a006918:1;
unsignedcheck_phy_clk_valid:1;
 
/* register save area for suspend/resume */
-- 
2.17.1

[PATCH v8 4/5] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

From: Ramneek Mehresh 

USB erratum-A006918 workaround tries to start internal PHY inside
uboot (when PLL fails to lock). However, if the workaround also
fails, then USB initialization is also stopped inside Linux.
Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
node in device-tree. Presence of this node in device-tree is
used to stop USB controller initialization in Linux

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
Change in v2:
replace Yinbo.Zhu with Yinbo Zhu.
Change in v5:
add the erratum commont replace "/* fall through */".   
Change in v6:
remove "/* fall through */".
Change in v7:
keep v5 change.
Change in v8:
Add "/* fall through */" for case FSL_USB2_PHY_UTMIII.


 drivers/usb/host/ehci-fsl.c  | 9 +
 drivers/usb/host/fsl-mph-dr-of.c | 3 ++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 8f3bf3efb038..9e9c232e896f 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -236,6 +236,15 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+   /* Presence of this node "has_fsl_erratum_a006918"
+* in device-tree is used to stop USB controller
+* initialization in Linux
+*/
+   if (pdata->has_fsl_erratum_a006918) {
+   dev_warn(dev, "USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+   /* fall through */
case FSL_USB2_PHY_UTMI_DUAL:
/* PHY_CLK_VALID bit is de-featured from all controller
 * versions below 2.4 and is to be checked only for
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 4f8b8a08c914..762b97600ab0 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -224,13 +224,14 @@ static int fsl_usb2_mph_dr_of_probe(struct 
platform_device *ofdev)
of_property_read_bool(np, "fsl,usb-erratum-a005275");
pdata->has_fsl_erratum_a005697 =
of_property_read_bool(np, "fsl,usb_erratum-a005697");
+   pdata->has_fsl_erratum_a006918 =
+   of_property_read_bool(np, "fsl,usb_erratum-a006918");
 
if (of_get_property(np, "fsl,usb_erratum_14", NULL))
pdata->has_fsl_erratum_14 = 1;
else
pdata->has_fsl_erratum_14 = 0;
 
-
/*
 * Determine whether phy_clk_valid needs to be checked
 * by reading property in device tree
-- 
2.17.1

RE: [EXT] Re: [PATCH v7 1/5] usb: fsl: Set USB_EN bit to select ULPI phy

[Yinbo Zhu]

> -Original Message-
> From: Greg Kroah-Hartman [mailto:gre...@linuxfoundation.org]
> Sent: 2019年6月20日 20:11
> To: Yinbo Zhu 
> Cc: Alan Stern ; Xiaobo Xie ;
> Jiafei Pan ; Ramneek Mehresh
> ; Nikhil Badola
> ; Ran Wang ;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [EXT] Re: [PATCH v7 1/5] usb: fsl: Set USB_EN bit to select ULPI phy
> 
> Caution: EXT Email
> 
> On Fri, Jun 14, 2019 at 04:54:29PM +0800, Yinbo Zhu wrote:
> > From: Nikhil Badola 
> >
> > Set USB_EN bit to select ULPI phy for USB controller version 2.5
> >
> > Signed-off-by: Nikhil Badola 
> > Signed-off-by: Yinbo Zhu 
> > ---
> >  drivers/usb/host/ehci-fsl.c | 6 ++
> >  1 file changed, 6 insertions(+)
> 
> What changed from v1-v7?  That should always go below the --- line.
> 
> Please fix up when you resend v8.
Okay, I will do it, but I accustomed to do change version if the series of 
other patch has update, I still update patch series number for all series 
patch, but no updated history in nochange's patch in current series.

Thanks,
Best Regards,
Yinbo zhu.
> 
> thanks,
> 
> greg k-h

RE: [EXT] Re: [PATCH v7 4/5] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

> -Original Message-
> From: Greg Kroah-Hartman [mailto:gre...@linuxfoundation.org]
> Sent: 2019年6月20日 20:10
> To: Yinbo Zhu 
> Cc: Alan Stern ; Xiaobo Xie ;
> Jiafei Pan ; Ramneek Mehresh
> ; Nikhil Badola
> ; Ran Wang ;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [EXT] Re: [PATCH v7 4/5] usb: host: Stops USB controller init if PLL 
> fails to
> lock
> 
> Caution: EXT Email
> 
> On Fri, Jun 14, 2019 at 04:54:32PM +0800, Yinbo Zhu wrote:
> > From: Ramneek Mehresh 
> >
> > USB erratum-A006918 workaround tries to start internal PHY inside
> > uboot (when PLL fails to lock). However, if the workaround also fails,
> > then USB initialization is also stopped inside Linux.
> > Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
> > node in device-tree. Presence of this node in device-tree is used to
> > stop USB controller initialization in Linux
> >
> > Signed-off-by: Ramneek Mehresh 
> > Signed-off-by: Suresh Gupta 
> > Signed-off-by: Yinbo Zhu 
> > ---
> > Change in v7:
> >   keep v5 version "fall through"
> >
> >  drivers/usb/host/ehci-fsl.c  | 9 +
> >  drivers/usb/host/fsl-mph-dr-of.c | 3 ++-
> >  2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
> > index 8f3bf3efb038..ef3dfd33a62e 100644
> > --- a/drivers/usb/host/ehci-fsl.c
> > +++ b/drivers/usb/host/ehci-fsl.c
> > @@ -236,6 +236,15 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
> >   portsc |= PORT_PTS_PTW;
> >   /* fall through */
> >   case FSL_USB2_PHY_UTMI:
> > + /* Presence of this node "has_fsl_erratum_a006918"
> > +  * in device-tree is used to stop USB controller
> > +  * initialization in Linux
> > +  */
> > + if (pdata->has_fsl_erratum_a006918) {
> > + dev_warn(dev, "USB PHY clock invalid\n");
> > + return -EINVAL;
> > + }
> > +
> 
> You need a /* fall through */ comment here, right?
> 
HI greg k-h.

Thanks your feedback!

Yes ,it is needed, because this case doesn't have break, in addition I will add 
a "/* fall through*/" in
case FSL_USB2_PHY_UTMI, please you note.
Thanks

Best Regards,
Yinbo Zhu.

> thanks,
> 
> greg k-h

[PATCH v7 2/5] usb: phy: Workaround for USB erratum-A005728

[Yinbo Zhu]

From: Suresh Gupta 

PHY_CLK_VALID bit for UTMI PHY in USBDR does not set even
if PHY is providing valid clock. Workaround for this
involves resetting of PHY and check PHY_CLK_VALID bit
multiple times. If PHY_CLK_VALID bit is still not set even
after 5 retries, it would be safe to deaclare that PHY
clock is not available.
This erratum is applicable for USBDR less then ver 2.4.

Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/ehci-fsl.c | 37 ++---
 drivers/usb/host/ehci-fsl.h |  3 +++
 2 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 38674b7aa51e..8f3bf3efb038 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -183,6 +183,17 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
return retval;
 }
 
+static bool usb_phy_clk_valid(struct usb_hcd *hcd)
+{
+   void __iomem *non_ehci = hcd->regs;
+   bool ret = true;
+
+   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
+   ret = false;
+
+   return ret;
+}
+
 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
   enum fsl_usb2_phy_modes phy_mode,
   unsigned int port_offset)
@@ -226,6 +237,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
/* fall through */
case FSL_USB2_PHY_UTMI:
case FSL_USB2_PHY_UTMI_DUAL:
+   /* PHY_CLK_VALID bit is de-featured from all controller
+* versions below 2.4 and is to be checked only for
+* internal UTMI phy
+*/
+   if (pdata->controller_ver > FSL_USB_VER_2_4 &&
+   pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
+   dev_err(dev, "USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
@@ -249,17 +270,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
 
-   /*
-* check PHY_CLK_VALID to determine phy clock presence before writing
-* to portsc
-*/
-   if (pdata->check_phy_clk_valid) {
-   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
-   PHY_CLK_VALID)) {
-   dev_warn(hcd->self.controller,
-"USB PHY clock invalid\n");
-   return -EINVAL;
-   }
+   if (pdata->have_sysif_regs &&
+   pdata->controller_ver > FSL_USB_VER_1_6 &&
+   !usb_phy_clk_valid(hcd)) {
+   dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
+   return -EINVAL;
}
 
ehci_writel(ehci, portsc, >regs->port_status[port_offset]);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index cbc422032e50..9d18c6e6ab27 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -50,4 +50,7 @@
 #define UTMI_PHY_EN (1<<9)
 #define ULPI_PHY_CLK_SEL(1<<10)
 #define PHY_CLK_VALID  (1<<17)
+
+/* Retry count for checking UTMI PHY CLK validity */
+#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
 #endif /* _EHCI_FSL_H */
-- 
2.17.1

[PATCH v7 5/5] usb :fsl: Change string format for errata property

[Yinbo Zhu]

From: Nikhil Badola 

Remove USB errata checking code from driver. Applicability of erratum
is retrieved by reading corresponding property in device tree.
This property is written during device tree fixup.

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/fsl-mph-dr-of.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 762b97600ab0..ae8f60f6e6a5 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -226,11 +226,8 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device 
*ofdev)
of_property_read_bool(np, "fsl,usb_erratum-a005697");
pdata->has_fsl_erratum_a006918 =
of_property_read_bool(np, "fsl,usb_erratum-a006918");
-
-   if (of_get_property(np, "fsl,usb_erratum_14", NULL))
-   pdata->has_fsl_erratum_14 = 1;
-   else
-   pdata->has_fsl_erratum_14 = 0;
+   pdata->has_fsl_erratum_14 =
+   of_property_read_bool(np, "fsl,usb_erratum-14");
 
/*
 * Determine whether phy_clk_valid needs to be checked
-- 
2.17.1

[PATCH v7 4/5] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

From: Ramneek Mehresh 

USB erratum-A006918 workaround tries to start internal PHY inside
uboot (when PLL fails to lock). However, if the workaround also
fails, then USB initialization is also stopped inside Linux.
Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
node in device-tree. Presence of this node in device-tree is
used to stop USB controller initialization in Linux

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
Change in v7:
keep v5 version "fall through"

 drivers/usb/host/ehci-fsl.c  | 9 +
 drivers/usb/host/fsl-mph-dr-of.c | 3 ++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 8f3bf3efb038..ef3dfd33a62e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -236,6 +236,15 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+   /* Presence of this node "has_fsl_erratum_a006918"
+* in device-tree is used to stop USB controller
+* initialization in Linux
+*/
+   if (pdata->has_fsl_erratum_a006918) {
+   dev_warn(dev, "USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
case FSL_USB2_PHY_UTMI_DUAL:
/* PHY_CLK_VALID bit is de-featured from all controller
 * versions below 2.4 and is to be checked only for
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 4f8b8a08c914..762b97600ab0 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -224,13 +224,14 @@ static int fsl_usb2_mph_dr_of_probe(struct 
platform_device *ofdev)
of_property_read_bool(np, "fsl,usb-erratum-a005275");
pdata->has_fsl_erratum_a005697 =
of_property_read_bool(np, "fsl,usb_erratum-a005697");
+   pdata->has_fsl_erratum_a006918 =
+   of_property_read_bool(np, "fsl,usb_erratum-a006918");
 
if (of_get_property(np, "fsl,usb_erratum_14", NULL))
pdata->has_fsl_erratum_14 = 1;
else
pdata->has_fsl_erratum_14 = 0;
 
-
/*
 * Determine whether phy_clk_valid needs to be checked
 * by reading property in device tree
-- 
2.17.1

[PATCH v7 1/5] usb: fsl: Set USB_EN bit to select ULPI phy

[Yinbo Zhu]

From: Nikhil Badola 

Set USB_EN bit to select ULPI phy for USB controller version 2.5

Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/ehci-fsl.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index e3d0c1c25160..38674b7aa51e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -122,6 +122,12 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
tmp |= 0x4;
iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
}
+
+   /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
+   if (pdata->controller_ver == FSL_USB_VER_2_5 &&
+   pdata->phy_mode == FSL_USB2_PHY_ULPI)
+   iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
+
/*
 * Enable UTMI phy and program PTS field in UTMI mode before asserting
 * controller reset for USB Controller version 2.5
-- 
2.17.1

[PATCH v7 3/5] usb: linux/fsl_device: Add platform member has_fsl_erratum_a006918

[Yinbo Zhu]

This patch is to add member has_fsl_erratum_a006918 in platform data

Signed-off-by: Yinbo Zhu 
---
 include/linux/fsl_devices.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index cb2b46f57af3..5d231ce8709b 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -98,6 +98,7 @@ struct fsl_usb2_platform_data {
unsignedhas_fsl_erratum_14:1;
unsignedhas_fsl_erratum_a005275:1;
unsignedhas_fsl_erratum_a005697:1;
+   unsignedhas_fsl_erratum_a006918:1;
unsignedcheck_phy_clk_valid:1;
 
/* register save area for suspend/resume */
-- 
2.17.1

[PATCH v1] mmc: sdhci-of-esdhc: set the sd clock divisor value above 3

[Yinbo Zhu]

From: Yangbo Lu 

This patch is to set the sd clock divisor value above 3 in tuning mode

Signed-off-by: Yinbo Zhu 
Signed-off-by: Yangbo Lu 
---
 drivers/mmc/host/sdhci-of-esdhc.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c 
b/drivers/mmc/host/sdhci-of-esdhc.c
index d4ec0a959a75..c4af026c3fba 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -824,9 +824,17 @@ static int esdhc_execute_tuning(struct mmc_host *mmc, u32 
opcode)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
bool hs400_tuning;
+   unsigned int clk;
u32 val;
int ret;
 
+   /* For tuning mode, the sd clock divisor value
+* must be larger than 3 according to reference manual.
+*/
+   clk = esdhc->peripheral_clock / 3;
+   if (host->clock > clk)
+   esdhc_of_set_clock(host, clk);
+
if (esdhc->quirk_limited_clk_division &&
host->flags & SDHCI_HS400_TUNING)
esdhc_of_set_clock(host, host->clock);
-- 
2.17.1

[PATCH v1] mmc: sdhci-of-esdhc: use 1/2 periperhal clock for ls1028a

[Yinbo Zhu]

From: Yangbo Lu 

LS1028A used 1/2 periperhal clock as one reference clock.

Signed-off-by: Yangbo Lu 
---
 drivers/mmc/host/sdhci-of-esdhc.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c 
b/drivers/mmc/host/sdhci-of-esdhc.c
index c56c7d413a09..4dd43b1adf2c 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -1048,11 +1048,12 @@ static void esdhc_init(struct platform_device *pdev, 
struct sdhci_host *host)
/*
 * esdhc->peripheral_clock would be assigned with a value
 * which is eSDHC base clock when use periperal clock.
-* For ls1046a, the clock value got by common clk API is
-* peripheral clock while the eSDHC base clock is 1/2
-* peripheral clock.
+* For some platforms, the clock value got by common clk
+* API is peripheral clock while the eSDHC base clock is
+* 1/2 peripheral clock.
 */
-   if (of_device_is_compatible(np, "fsl,ls1046a-esdhc"))
+   if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||
+   of_device_is_compatible(np, "fsl,ls1028a-esdhc"))
esdhc->peripheral_clock = clk_get_rate(clk) / 2;
else
esdhc->peripheral_clock = clk_get_rate(clk);
-- 
2.17.1

RE: [EXT] Re: [PATCH v6 4/5] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

> -Original Message-
> From: Yinbo Zhu
> Sent: 2019年6月6日 14:35
> To: Alan Stern 
> Cc: Xiaobo Xie ; Greg Kroah-Hartman
> ; Ramneek Mehresh
> ; Nikhil Badola
> ; Ran Wang ;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Jiafei Pan
> 
> Subject: RE: [EXT] Re: [PATCH v6 4/5] usb: host: Stops USB controller init if 
> PLL
> fails to lock
> 
> 
> 
> > -Original Message-
> > From: Alan Stern [mailto:st...@rowland.harvard.edu]
> > Sent: 2019年6月5日 22:22
> > To: Yinbo Zhu 
> > Cc: Xiaobo Xie ; Greg Kroah-Hartman
> > ; Ramneek Mehresh
> > ; Nikhil Badola
> > ; Ran Wang ;
> > linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Jiafei Pan
> > 
> > Subject: [EXT] Re: [PATCH v6 4/5] usb: host: Stops USB controller init
> > if PLL fails to lock
> >
> > Caution: EXT Email
> >
> > On Wed, 5 Jun 2019, Yinbo Zhu wrote:
> >
> > > From: Ramneek Mehresh 
> > >
> > > USB erratum-A006918 workaround tries to start internal PHY inside
> > > uboot (when PLL fails to lock). However, if the workaround also
> > > fails, then USB initialization is also stopped inside Linux.
> > > Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
> > > node in device-tree. Presence of this node in device-tree is used to
> > > stop USB controller initialization in Linux
> > >
> > > Signed-off-by: Ramneek Mehresh 
> > > Signed-off-by: Suresh Gupta 
> > > Signed-off-by: Yinbo Zhu 
> > > ---
> > > Change in v6:
> > >   add a "Fall through" comment
> > >
> > >  drivers/usb/host/ehci-fsl.c  | 10 +-
> > >  drivers/usb/host/fsl-mph-dr-of.c |  3 ++-
> > >  2 files changed, 11 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/usb/host/ehci-fsl.c
> > > b/drivers/usb/host/ehci-fsl.c index 8f3bf3efb038..86ae37086a74
> > > 100644
> > > --- a/drivers/usb/host/ehci-fsl.c
> > > +++ b/drivers/usb/host/ehci-fsl.c
> > > @@ -234,8 +234,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
> > >   break;
> > >   case FSL_USB2_PHY_UTMI_WIDE:
> > >   portsc |= PORT_PTS_PTW;
> > > - /* fall through */
> > >   case FSL_USB2_PHY_UTMI:
> > > + /* Presence of this node "has_fsl_erratum_a006918"
> > > +  * in device-tree is used to stop USB controller
> > > +  * initialization in Linux
> > > +  */
> > > + if (pdata->has_fsl_erratum_a006918) {
> > > + dev_warn(dev, "USB PHY clock invalid\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > >   case FSL_USB2_PHY_UTMI_DUAL:
> >
> >
> > You need to add a "Fall through" comment between these two cases.
> > >   case FSL_USB2_PHY_UTMI_DUAL:
> > >   /* PHY_CLK_VALID bit is de-featured from all controller
> > >* versions below 2.4 and is to be checked only for
> >
> > Alan Stern
> > Hi Alan Stern,
> >
> > Your meaning is to remove "/* fall through*/" or add the erratum commont
> replace "/* fall through*/"
> >
> > Regards,
> > Yinbo
> > This is bad.  You got rid of a "fall through" comment that was needed,
> > and you failed to add another one where it was needed.
> >
> > Alan Stern
> I don't get your meaning.
> Yinbo
Hi Alan,

Your meaning is like following code change, isn't it? if no, could you give a 
example
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+   /* Presence of this node "has_fsl_erratum_a006918"
+* in device-tree is used to stop USB controller
+* initialization in Linux
+*/
+   if (pdata->has_fsl_erratum_a006918) {
+   dev_warn(dev, "USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
case FSL_USB2_PHY_UTMI_DUAL:
/* PHY_CLK_VALID bit is de-featured from all controller
Regards,
Yinbo.

> >
> > >   /* PHY_CLK_VALID bit is de-featured from all controller
> > >* versions below 2.4 and is to be checked only for
> > > diff --git a/drivers/usb/host/fsl-mph-dr-of.c
> > > b/drivers/usb/host/fsl-mph-dr-of.c
> > > index 4f8b8a08c914..762b

RE: [EXT] Re: [PATCH v6 4/5] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

> -Original Message-
> From: Alan Stern [mailto:st...@rowland.harvard.edu]
> Sent: 2019年6月5日 22:22
> To: Yinbo Zhu 
> Cc: Xiaobo Xie ; Greg Kroah-Hartman
> ; Ramneek Mehresh
> ; Nikhil Badola
> ; Ran Wang ;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Jiafei Pan
> 
> Subject: [EXT] Re: [PATCH v6 4/5] usb: host: Stops USB controller init if PLL 
> fails to
> lock
> 
> Caution: EXT Email
> 
> On Wed, 5 Jun 2019, Yinbo Zhu wrote:
> 
> > From: Ramneek Mehresh 
> >
> > USB erratum-A006918 workaround tries to start internal PHY inside
> > uboot (when PLL fails to lock). However, if the workaround also fails,
> > then USB initialization is also stopped inside Linux.
> > Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
> > node in device-tree. Presence of this node in device-tree is used to
> > stop USB controller initialization in Linux
> >
> > Signed-off-by: Ramneek Mehresh 
> > Signed-off-by: Suresh Gupta 
> > Signed-off-by: Yinbo Zhu 
> > ---
> > Change in v6:
> >   add a "Fall through" comment
> >
> >  drivers/usb/host/ehci-fsl.c  | 10 +-
> >  drivers/usb/host/fsl-mph-dr-of.c |  3 ++-
> >  2 files changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
> > index 8f3bf3efb038..86ae37086a74 100644
> > --- a/drivers/usb/host/ehci-fsl.c
> > +++ b/drivers/usb/host/ehci-fsl.c
> > @@ -234,8 +234,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
> >   break;
> >   case FSL_USB2_PHY_UTMI_WIDE:
> >   portsc |= PORT_PTS_PTW;
> > - /* fall through */
> >   case FSL_USB2_PHY_UTMI:
> > + /* Presence of this node "has_fsl_erratum_a006918"
> > +  * in device-tree is used to stop USB controller
> > +  * initialization in Linux
> > +  */
> > + if (pdata->has_fsl_erratum_a006918) {
> > + dev_warn(dev, "USB PHY clock invalid\n");
> > + return -EINVAL;
> > + }
> > +
> >   case FSL_USB2_PHY_UTMI_DUAL:
> 
> 
> You need to add a "Fall through" comment between these two cases.
> >   case FSL_USB2_PHY_UTMI_DUAL:
> >   /* PHY_CLK_VALID bit is de-featured from all controller
> >* versions below 2.4 and is to be checked only for
> 
> Alan Stern
> Hi Alan Stern,
>
> Your meaning is to remove "/* fall through*/" or add the erratum commont 
> replace "/* fall through*/"
>
> Regards,
> Yinbo
> This is bad.  You got rid of a "fall through" comment that was needed, and you
> failed to add another one where it was needed.
> 
> Alan Stern
I don't get your meaning.
Yinbo
> 
> >   /* PHY_CLK_VALID bit is de-featured from all controller
> >* versions below 2.4 and is to be checked only for diff
> > --git a/drivers/usb/host/fsl-mph-dr-of.c
> > b/drivers/usb/host/fsl-mph-dr-of.c
> > index 4f8b8a08c914..762b97600ab0 100644
> > --- a/drivers/usb/host/fsl-mph-dr-of.c
> > +++ b/drivers/usb/host/fsl-mph-dr-of.c
> > @@ -224,13 +224,14 @@ static int fsl_usb2_mph_dr_of_probe(struct
> platform_device *ofdev)
> >   of_property_read_bool(np, "fsl,usb-erratum-a005275");
> >   pdata->has_fsl_erratum_a005697 =
> >   of_property_read_bool(np, "fsl,usb_erratum-a005697");
> > + pdata->has_fsl_erratum_a006918 =
> > + of_property_read_bool(np, "fsl,usb_erratum-a006918");
> >
> >   if (of_get_property(np, "fsl,usb_erratum_14", NULL))
> >   pdata->has_fsl_erratum_14 = 1;
> >   else
> >   pdata->has_fsl_erratum_14 = 0;
> >
> > -
> >   /*
> >* Determine whether phy_clk_valid needs to be checked
> >* by reading property in device tree
> >

[PATCH v6 1/5] usb: fsl: Set USB_EN bit to select ULPI phy

[Yinbo Zhu]

From: Nikhil Badola 

Set USB_EN bit to select ULPI phy for USB controller version 2.5

Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/ehci-fsl.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index e3d0c1c25160..38674b7aa51e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -122,6 +122,12 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
tmp |= 0x4;
iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
}
+
+   /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
+   if (pdata->controller_ver == FSL_USB_VER_2_5 &&
+   pdata->phy_mode == FSL_USB2_PHY_ULPI)
+   iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
+
/*
 * Enable UTMI phy and program PTS field in UTMI mode before asserting
 * controller reset for USB Controller version 2.5
-- 
2.17.1

[PATCH v6 3/5] usb: linux/fsl_device: Add platform member has_fsl_erratum_a006918

[Yinbo Zhu]

This patch is to add member has_fsl_erratum_a006918 in platform data

Signed-off-by: Yinbo Zhu 
---
 include/linux/fsl_devices.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index cb2b46f57af3..5d231ce8709b 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -98,6 +98,7 @@ struct fsl_usb2_platform_data {
unsignedhas_fsl_erratum_14:1;
unsignedhas_fsl_erratum_a005275:1;
unsignedhas_fsl_erratum_a005697:1;
+   unsignedhas_fsl_erratum_a006918:1;
unsignedcheck_phy_clk_valid:1;
 
/* register save area for suspend/resume */
-- 
2.17.1

[PATCH v6 5/5] usb :fsl: Change string format for errata property

[Yinbo Zhu]

From: Nikhil Badola 

Remove USB errata checking code from driver. Applicability of erratum
is retrieved by reading corresponding property in device tree.
This property is written during device tree fixup.

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/fsl-mph-dr-of.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 762b97600ab0..ae8f60f6e6a5 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -226,11 +226,8 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device 
*ofdev)
of_property_read_bool(np, "fsl,usb_erratum-a005697");
pdata->has_fsl_erratum_a006918 =
of_property_read_bool(np, "fsl,usb_erratum-a006918");
-
-   if (of_get_property(np, "fsl,usb_erratum_14", NULL))
-   pdata->has_fsl_erratum_14 = 1;
-   else
-   pdata->has_fsl_erratum_14 = 0;
+   pdata->has_fsl_erratum_14 =
+   of_property_read_bool(np, "fsl,usb_erratum-14");
 
/*
 * Determine whether phy_clk_valid needs to be checked
-- 
2.17.1

[PATCH v6 4/5] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

From: Ramneek Mehresh 

USB erratum-A006918 workaround tries to start internal PHY inside
uboot (when PLL fails to lock). However, if the workaround also
fails, then USB initialization is also stopped inside Linux.
Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
node in device-tree. Presence of this node in device-tree is
used to stop USB controller initialization in Linux

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
Change in v6:
add a "Fall through" comment

 drivers/usb/host/ehci-fsl.c  | 10 +-
 drivers/usb/host/fsl-mph-dr-of.c |  3 ++-
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 8f3bf3efb038..86ae37086a74 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -234,8 +234,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
case FSL_USB2_PHY_UTMI_WIDE:
portsc |= PORT_PTS_PTW;
-   /* fall through */
case FSL_USB2_PHY_UTMI:
+   /* Presence of this node "has_fsl_erratum_a006918"
+* in device-tree is used to stop USB controller
+* initialization in Linux
+*/
+   if (pdata->has_fsl_erratum_a006918) {
+   dev_warn(dev, "USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
case FSL_USB2_PHY_UTMI_DUAL:
/* PHY_CLK_VALID bit is de-featured from all controller
 * versions below 2.4 and is to be checked only for
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 4f8b8a08c914..762b97600ab0 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -224,13 +224,14 @@ static int fsl_usb2_mph_dr_of_probe(struct 
platform_device *ofdev)
of_property_read_bool(np, "fsl,usb-erratum-a005275");
pdata->has_fsl_erratum_a005697 =
of_property_read_bool(np, "fsl,usb_erratum-a005697");
+   pdata->has_fsl_erratum_a006918 =
+   of_property_read_bool(np, "fsl,usb_erratum-a006918");
 
if (of_get_property(np, "fsl,usb_erratum_14", NULL))
pdata->has_fsl_erratum_14 = 1;
else
pdata->has_fsl_erratum_14 = 0;
 
-
/*
 * Determine whether phy_clk_valid needs to be checked
 * by reading property in device tree
-- 
2.17.1

[PATCH v6 2/5] usb: phy: Workaround for USB erratum-A005728

[Yinbo Zhu]

From: Suresh Gupta 

PHY_CLK_VALID bit for UTMI PHY in USBDR does not set even
if PHY is providing valid clock. Workaround for this
involves resetting of PHY and check PHY_CLK_VALID bit
multiple times. If PHY_CLK_VALID bit is still not set even
after 5 retries, it would be safe to deaclare that PHY
clock is not available.
This erratum is applicable for USBDR less then ver 2.4.

Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
Change in v6:
Indented the code in ehci-fsl.c 

 drivers/usb/host/ehci-fsl.c | 37 ++---
 drivers/usb/host/ehci-fsl.h |  3 +++
 2 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 38674b7aa51e..8f3bf3efb038 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -183,6 +183,17 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
return retval;
 }
 
+static bool usb_phy_clk_valid(struct usb_hcd *hcd)
+{
+   void __iomem *non_ehci = hcd->regs;
+   bool ret = true;
+
+   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
+   ret = false;
+
+   return ret;
+}
+
 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
   enum fsl_usb2_phy_modes phy_mode,
   unsigned int port_offset)
@@ -226,6 +237,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
/* fall through */
case FSL_USB2_PHY_UTMI:
case FSL_USB2_PHY_UTMI_DUAL:
+   /* PHY_CLK_VALID bit is de-featured from all controller
+* versions below 2.4 and is to be checked only for
+* internal UTMI phy
+*/
+   if (pdata->controller_ver > FSL_USB_VER_2_4 &&
+   pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
+   dev_err(dev, "USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
@@ -249,17 +270,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
 
-   /*
-* check PHY_CLK_VALID to determine phy clock presence before writing
-* to portsc
-*/
-   if (pdata->check_phy_clk_valid) {
-   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
-   PHY_CLK_VALID)) {
-   dev_warn(hcd->self.controller,
-"USB PHY clock invalid\n");
-   return -EINVAL;
-   }
+   if (pdata->have_sysif_regs &&
+   pdata->controller_ver > FSL_USB_VER_1_6 &&
+   !usb_phy_clk_valid(hcd)) {
+   dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
+   return -EINVAL;
}
 
ehci_writel(ehci, portsc, >regs->port_status[port_offset]);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index cbc422032e50..9d18c6e6ab27 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -50,4 +50,7 @@
 #define UTMI_PHY_EN (1<<9)
 #define ULPI_PHY_CLK_SEL(1<<10)
 #define PHY_CLK_VALID  (1<<17)
+
+/* Retry count for checking UTMI PHY CLK validity */
+#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
 #endif /* _EHCI_FSL_H */
-- 
2.17.1

[PATCH v3] arm64: dts: ls1028a: Add esdhc node in dts

[Yinbo Zhu]

From: Ashish Kumar 

This patch is to add esdhc node and enable SD UHS-I,
eMMC HS200 for ls1028ardb/ls1028aqds board.

Signed-off-by: Ashish Kumar 
Signed-off-by: Yangbo Lu 
Signed-off-by: Yinbo Zhu 
---
Change in v3:
replace "esdhc@" with "mmc@"

 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |8 ++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts |   13 ++
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi|   27 +
 3 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 14c79f4..180e5d2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -42,6 +42,14 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f86b054..1bfaf42 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -30,6 +30,19 @@
};
 };
 
+ {
+   status = "okay";
+   sd-uhs-sdr104;
+   sd-uhs-sdr50;
+   sd-uhs-sdr25;
+   sd-uhs-sdr12;
+   };
+
+ {
+   status = "okay";
+   mmc-hs200-1_8v;
+   };
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2896bbc..462833c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -274,6 +274,33 @@
status = "disabled";
};
 
+   esdhc: mmc@214 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x214 0x0 0x1>;
+   interrupts = <0 28 0x4>; /* Level high type */
+   clock-frequency = <0>; /* fixed up by bootloader */
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
+   esdhc1: mmc@215 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x215 0x0 0x1>;
+   interrupts = <0 63 0x4>; /* Level high type */
+   clock-frequency = <0>; /* fixed up by bootloader */
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   broken-cd;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
sata: sata@320 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x320 0x0 0x1>,
-- 
1.7.1

[PATCH v2] arm64: dts: ls1028a: Add esdhc node in dts

[Yinbo Zhu]

From: Ashish Kumar 

This patch is to add esdhc node and enable SD UHS-I,
eMMC HS200 for ls1028ardb/ls1028aqds board.

Signed-off-by: Ashish Kumar 
Signed-off-by: Yangbo Lu 
Signed-off-by: Yinbo Zhu 
---
Change in v2:
Update the patch title
Add a commont in dts code

 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |8 ++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts |   13 ++
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi|   27 +
 3 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 14c79f4..180e5d2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -42,6 +42,14 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f86b054..1bfaf42 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -30,6 +30,19 @@
};
 };
 
+ {
+   status = "okay";
+   sd-uhs-sdr104;
+   sd-uhs-sdr50;
+   sd-uhs-sdr25;
+   sd-uhs-sdr12;
+   };
+
+ {
+   status = "okay";
+   mmc-hs200-1_8v;
+   };
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2896bbc..5c7546f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -274,6 +274,33 @@
status = "disabled";
};
 
+   esdhc: esdhc@214 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x214 0x0 0x1>;
+   interrupts = <0 28 0x4>; /* Level high type */
+   clock-frequency = <0>; /* fixed up by bootloader */
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
+   esdhc1: esdhc@215 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x215 0x0 0x1>;
+   interrupts = <0 63 0x4>; /* Level high type */
+   clock-frequency = <0>; /* fixed up by bootloader */
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   broken-cd;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
sata: sata@320 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x320 0x0 0x1>,
-- 
1.7.1

RE: [EXT] Re: [PATCH v1] arm64: ls1028: dtsi: Add esdhc node in dtsi

[Yinbo Zhu]

> -Original Message-
> From: Yinbo Zhu
> Sent: 2019年5月5日 14:07
> To: Rob Herring 
> Cc: Shawn Guo ; Leo Li ; Xiaobo
> Xie ; Mark Rutland ;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; Y.b. Lu
> ; Jiafei Pan ; Ashish Kumar
> 
> Subject: RE: [EXT] Re: [PATCH v1] arm64: ls1028: dtsi: Add esdhc node in dtsi
> 
> 
> 
> > -Original Message-
> > From: Rob Herring [mailto:robh...@kernel.org]
> > Sent: 2019年5月2日 1:50
> > To: Yinbo Zhu 
> > Cc: Shawn Guo ; Leo Li ;
> > Xiaobo Xie ; Mark Rutland ;
> > linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; Y.b. Lu
> > ; Jiafei Pan ; Ashish Kumar
> > 
> > Subject: [EXT] Re: [PATCH v1] arm64: ls1028: dtsi: Add esdhc node in
> > dtsi
> >
> > Caution: EXT Email
> >
> > On Tue, Apr 23, 2019 at 6:42 AM Yinbo Zhu  wrote:
> > >
> > > From: Ashish Kumar 
> > >
> > > This patch is to add esdhc node and enable SD UHS-I, eMMC HS200 for
> > > ls1028ardb/ls1028aqds board.
> > >
> > > Signed-off-by: Ashish Kumar 
> > > Signed-off-by: Yangbo Lu 
> > > Signed-off-by: Yinbo Zhu 
> > > ---
> > >  .../boot/dts/freescale/fsl-ls1028a-qds.dts|  8 ++
> > >  .../boot/dts/freescale/fsl-ls1028a-rdb.dts| 13 +
> > >  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 27
> > > +++
> > >  3 files changed, 48 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > > index 14c79f4691ea..180e5d2a00d1 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > > @@ -42,6 +42,14 @@
> > > status = "okay";
> > >  };
> > >
> > > + {
> > > +   status = "okay";
> > > +};
> > > +
> > > + {
> > > +   status = "okay";
> > > +};
> > > +
> > >   {
> > > status = "okay";
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > > index f86b054a74ae..1bfaf4294db4 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > > @@ -30,6 +30,19 @@
> > > };
> > >  };
> > >
> > > + {
> > > +   status = "okay";
> > > +   sd-uhs-sdr104;
> > > +   sd-uhs-sdr50;
> > > +   sd-uhs-sdr25;
> > > +   sd-uhs-sdr12;
> > > +   };
> > > +
> > > + {
> > > +   status = "okay";
> > > +   mmc-hs200-1_8v;
> > > +   };
> > > +
> > >   {
> > > status = "okay";
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > > index 2896bbcfa3bb..d13cd3fb455b 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > > @@ -274,6 +274,33 @@
> > > status = "disabled";
> > > };
> > >
> > > +   esdhc: esdhc@214 {
> >
> > mmc@...
> >
> > > +   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
> > > +   reg = <0x0 0x214 0x0 0x1>;
> > > +   interrupts = <0 28 0x4>; /* Level high type */
> > > +   clock-frequency = <0>;
> >
> > Filled in by bootloader? If so, add a comment.
> Hi rob,
> Filled in by kernel, please you note.
> 
> Regards,
> Yinbo.

Hi rob,

I'm sorry, It is fixed up by bootloader actually.
And I will add a commont.

yinbo
> > > +   clocks = < 2 1>;
> > > +   voltage-ranges = <1800 1800 3300 3300>;
> > > +   sdhci,auto-cmd12;
> > > +   little-endian;
> > > +   bus-width = <4>;
> > > +   status = "disabled";
> > > +   };
> > > +
> > > +   esdhc1: esdhc@215 {
> >
> > mmc@...
> >
> > > +   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
> > > +   reg = <0x0 0x215 0x0 0x1>;
> > > +   interrupts = <0 63 0x4>; /* Level high type */
> > > +   clock-frequency = <0>;
> > > +   clocks = < 2 1>;
> > > +   voltage-ranges = <1800 1800 3300 3300>;
> > > +   sdhci,auto-cmd12;
> > > +   broken-cd;
> > > +   little-endian;
> > > +   bus-width = <4>;
> > > +   status = "disabled";
> > > +   };
> > > +
> > > sata: sata@320 {
> > > compatible = "fsl,ls1028a-ahci";
> > > reg = <0x0 0x320 0x0 0x1>,
> > > --
> > > 2.17.1
> > >

RE: [EXT] Re: [PATCH v1] arm64: ls1028: dtsi: Add esdhc node in dtsi

[Yinbo Zhu]

> -Original Message-
> From: Rob Herring [mailto:robh...@kernel.org]
> Sent: 2019年5月2日 1:50
> To: Yinbo Zhu 
> Cc: Shawn Guo ; Leo Li ; Xiaobo
> Xie ; Mark Rutland ;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; Y.b. Lu
> ; Jiafei Pan ; Ashish Kumar
> 
> Subject: [EXT] Re: [PATCH v1] arm64: ls1028: dtsi: Add esdhc node in dtsi
> 
> Caution: EXT Email
> 
> On Tue, Apr 23, 2019 at 6:42 AM Yinbo Zhu  wrote:
> >
> > From: Ashish Kumar 
> >
> > This patch is to add esdhc node and enable SD UHS-I, eMMC HS200 for
> > ls1028ardb/ls1028aqds board.
> >
> > Signed-off-by: Ashish Kumar 
> > Signed-off-by: Yangbo Lu 
> > Signed-off-by: Yinbo Zhu 
> > ---
> >  .../boot/dts/freescale/fsl-ls1028a-qds.dts|  8 ++
> >  .../boot/dts/freescale/fsl-ls1028a-rdb.dts| 13 +
> >  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 27
> > +++
> >  3 files changed, 48 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > index 14c79f4691ea..180e5d2a00d1 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > @@ -42,6 +42,14 @@
> > status = "okay";
> >  };
> >
> > + {
> > +   status = "okay";
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> >   {
> > status = "okay";
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > index f86b054a74ae..1bfaf4294db4 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > @@ -30,6 +30,19 @@
> > };
> >  };
> >
> > + {
> > +   status = "okay";
> > +   sd-uhs-sdr104;
> > +   sd-uhs-sdr50;
> > +   sd-uhs-sdr25;
> > +   sd-uhs-sdr12;
> > +   };
> > +
> > + {
> > +   status = "okay";
> > +   mmc-hs200-1_8v;
> > +   };
> > +
> >   {
> > status = "okay";
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index 2896bbcfa3bb..d13cd3fb455b 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -274,6 +274,33 @@
> > status = "disabled";
> > };
> >
> > +   esdhc: esdhc@214 {
> 
> mmc@...
> 
> > +   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
> > +   reg = <0x0 0x214 0x0 0x1>;
> > +   interrupts = <0 28 0x4>; /* Level high type */
> > +   clock-frequency = <0>;
> 
> Filled in by bootloader? If so, add a comment.
Hi rob,
Filled in by kernel, please you note.

Regards,
Yinbo.
> > +   clocks = < 2 1>;
> > +   voltage-ranges = <1800 1800 3300 3300>;
> > +   sdhci,auto-cmd12;
> > +   little-endian;
> > +   bus-width = <4>;
> > +   status = "disabled";
> > +   };
> > +
> > +   esdhc1: esdhc@215 {
> 
> mmc@...
> 
> > +   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
> > +   reg = <0x0 0x215 0x0 0x1>;
> > +   interrupts = <0 63 0x4>; /* Level high type */
> > +   clock-frequency = <0>;
> > +   clocks = < 2 1>;
> > +   voltage-ranges = <1800 1800 3300 3300>;
> > +   sdhci,auto-cmd12;
> > +   broken-cd;
> > +   little-endian;
> > +   bus-width = <4>;
> > +   status = "disabled";
> > +   };
> > +
> > sata: sata@320 {
> > compatible = "fsl,ls1028a-ahci";
> > reg = <0x0 0x320 0x0 0x1>,
> > --
> > 2.17.1
> >

[PATCH v2] dt-bindings: mmc: add DT bindings for ls1028a eSDHC host controller

[Yinbo Zhu]

From: Yinbo Zhu 

Add "fsl,ls1028a-esdhc" bindings for ls1028a eSDHC host controller

Signed-off-by: Yinbo Zhu 
---
Change in v2:
as alphabetical order to update dt-bindings
update the commit information.

 Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt 
b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index 99c5cf8507e8..edb8cadb9541 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -17,6 +17,7 @@ Required properties:
"fsl,t4240-esdhc"
 Possible compatibles for ARM:
"fsl,ls1012a-esdhc"
+   "fsl,ls1028a-esdhc"
"fsl,ls1088a-esdhc"
"fsl,ls1043a-esdhc"
"fsl,ls1046a-esdhc"
-- 
2.17.1

[PATCH v1] mmc: dt: add DT bindings for ls1028a eSDHC host controller

[Yinbo Zhu]

From: Yinbo Zhu 

Add "fsl,ls1028a-esdhc" bindings for ls1028a eSDHC host controller

Signed-off-by: Yinbo Zhu 
---
 .../devicetree/bindings/mmc/fsl-esdhc.txt  |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt 
b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index 99c5cf8..a7250b9 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -21,6 +21,7 @@ Required properties:
"fsl,ls1043a-esdhc"
"fsl,ls1046a-esdhc"
"fsl,ls2080a-esdhc"
+   "fsl,ls1028a-esdhc"
   - clock-frequency : specifies eSDHC base clock frequency.
 
 Optional properties:
-- 
1.7.1

[PATCH v1] arm64: ls1028: dtsi: Add esdhc node in dtsi

[Yinbo Zhu]

From: Ashish Kumar 

This patch is to add esdhc node and enable SD UHS-I,
eMMC HS200 for ls1028ardb/ls1028aqds board.

Signed-off-by: Ashish Kumar 
Signed-off-by: Yangbo Lu 
Signed-off-by: Yinbo Zhu 
---
 .../boot/dts/freescale/fsl-ls1028a-qds.dts|  8 ++
 .../boot/dts/freescale/fsl-ls1028a-rdb.dts| 13 +
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 27 +++
 3 files changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 14c79f4691ea..180e5d2a00d1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -42,6 +42,14 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f86b054a74ae..1bfaf4294db4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -30,6 +30,19 @@
};
 };
 
+ {
+   status = "okay";
+   sd-uhs-sdr104;
+   sd-uhs-sdr50;
+   sd-uhs-sdr25;
+   sd-uhs-sdr12;
+   };
+
+ {
+   status = "okay";
+   mmc-hs200-1_8v;
+   };
+
  {
status = "okay";
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2896bbcfa3bb..d13cd3fb455b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -274,6 +274,33 @@
status = "disabled";
};
 
+   esdhc: esdhc@214 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x214 0x0 0x1>;
+   interrupts = <0 28 0x4>; /* Level high type */
+   clock-frequency = <0>;
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
+   esdhc1: esdhc@215 {
+   compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
+   reg = <0x0 0x215 0x0 0x1>;
+   interrupts = <0 63 0x4>; /* Level high type */
+   clock-frequency = <0>;
+   clocks = < 2 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   broken-cd;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
sata: sata@320 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x320 0x0 0x1>,
-- 
2.17.1

[PATCH v2] ls1021aqds: enable esdhc controller

[Yinbo Zhu]

From: Yinbo Zhu 

This patch is to enable esdhc controller in ls1021aqds

Signed-off-by: Yinbo Zhu 
---
Change in v2:
Add patch code after  to keep them sort alphabetically.

 arch/arm/boot/dts/ls1021a-qds.dts |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts 
b/arch/arm/boot/dts/ls1021a-qds.dts
index dac61e7..ae26f8b 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -160,6 +160,10 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
-- 
1.7.1

[PATCH v4 2/5] usb: phy: Workaround for USB erratum-A005728

[Yinbo Zhu]

From: Suresh Gupta 

PHY_CLK_VALID bit for UTMI PHY in USBDR does not set even
if PHY is providing valid clock. Workaround for this
involves resetting of PHY and check PHY_CLK_VALID bit
multiple times. If PHY_CLK_VALID bit is still not set even
after 5 retries, it would be safe to deaclare that PHY
clock is not available.
This erratum is applicable for USBDR less then ver 2.4.

Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
Change in v4:
Incorrect indentation of the continuation line.
replace pr_err with dev_err.

 drivers/usb/host/ehci-fsl.c |   38 +++---
 drivers/usb/host/ehci-fsl.h |3 +++
 2 files changed, 30 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 38674b7..373a816 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -183,6 +183,17 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
return retval;
 }
 
+static bool usb_phy_clk_valid(struct usb_hcd *hcd)
+{
+   void __iomem *non_ehci = hcd->regs;
+   bool ret = true;
+
+   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
+   ret = false;
+
+   return ret;
+}
+
 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
   enum fsl_usb2_phy_modes phy_mode,
   unsigned int port_offset)
@@ -226,6 +237,17 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
/* fall through */
case FSL_USB2_PHY_UTMI:
case FSL_USB2_PHY_UTMI_DUAL:
+   /* PHY_CLK_VALID bit is de-featured from all controller
+* versions below 2.4 and is to be checked only for
+* internal UTMI phy
+*/
+   if (pdata->controller_ver > FSL_USB_VER_2_4 &&
+   pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
+   dev_err(dev,
+   "%s: USB PHY clock invalid\n", dev_name(dev));
+   return -EINVAL;
+   }
+
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
@@ -249,17 +271,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
 
-   /*
-* check PHY_CLK_VALID to determine phy clock presence before writing
-* to portsc
-*/
-   if (pdata->check_phy_clk_valid) {
-   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
-   PHY_CLK_VALID)) {
-   dev_warn(hcd->self.controller,
-"USB PHY clock invalid\n");
-   return -EINVAL;
-   }
+   if (pdata->have_sysif_regs &&
+   pdata->controller_ver > FSL_USB_VER_1_6 &&
+   !usb_phy_clk_valid(hcd)) {
+   dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
+   return -EINVAL;
}
 
ehci_writel(ehci, portsc, >regs->port_status[port_offset]);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index cbc4220..9d18c6e 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -50,4 +50,7 @@
 #define UTMI_PHY_EN (1<<9)
 #define ULPI_PHY_CLK_SEL(1<<10)
 #define PHY_CLK_VALID  (1<<17)
+
+/* Retry count for checking UTMI PHY CLK validity */
+#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
 #endif /* _EHCI_FSL_H */
-- 
1.7.1

[PATCH v4 4/5] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

From: Ramneek Mehresh 

USB erratum-A006918 workaround tries to start internal PHY inside
uboot (when PLL fails to lock). However, if the workaround also
fails, then USB initialization is also stopped inside Linux.
Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
node in device-tree. Presence of this node in device-tree is
used to stop USB controller initialization in Linux

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/ehci-fsl.c  |5 +
 drivers/usb/host/fsl-mph-dr-of.c |3 ++-
 2 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 373a816..8b47277 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -236,6 +236,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+   if (pdata->has_fsl_erratum_a006918) {
+   pr_warn("fsl-ehci: USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
case FSL_USB2_PHY_UTMI_DUAL:
/* PHY_CLK_VALID bit is de-featured from all controller
 * versions below 2.4 and is to be checked only for
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 4f8b8a0..762b976 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -224,13 +224,14 @@ static int fsl_usb2_mph_dr_of_probe(struct 
platform_device *ofdev)
of_property_read_bool(np, "fsl,usb-erratum-a005275");
pdata->has_fsl_erratum_a005697 =
of_property_read_bool(np, "fsl,usb_erratum-a005697");
+   pdata->has_fsl_erratum_a006918 =
+   of_property_read_bool(np, "fsl,usb_erratum-a006918");
 
if (of_get_property(np, "fsl,usb_erratum_14", NULL))
pdata->has_fsl_erratum_14 = 1;
else
pdata->has_fsl_erratum_14 = 0;
 
-
/*
 * Determine whether phy_clk_valid needs to be checked
 * by reading property in device tree
-- 
1.7.1

[PATCH v4 3/5] usb: linux/fsl_device: Add platform member has_fsl_erratum_a006918

[Yinbo Zhu]

From: Yinbo Zhu 

This patch is to add member has_fsl_erratum_a006918 in platform data

Signed-off-by: Yinbo Zhu 
---
 include/linux/fsl_devices.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 5da56a6..4c613da 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -102,6 +102,7 @@ struct fsl_usb2_platform_data {
unsignedhas_fsl_erratum_14:1;
unsignedhas_fsl_erratum_a005275:1;
unsignedhas_fsl_erratum_a005697:1;
+   unsignedhas_fsl_erratum_a006918:1;
unsignedcheck_phy_clk_valid:1;
 
/* register save area for suspend/resume */
-- 
1.7.1

[PATCH v4 5/5] usb :fsl: Change string format for errata property

[Yinbo Zhu]

From: Nikhil Badola 

Remove USB errata checking code from driver. Applicability of erratum
is retrieved by reading corresponding property in device tree.
This property is written during device tree fixup.

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/fsl-mph-dr-of.c |7 ++-
 1 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 762b976..ae8f60f 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -226,11 +226,8 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device 
*ofdev)
of_property_read_bool(np, "fsl,usb_erratum-a005697");
pdata->has_fsl_erratum_a006918 =
of_property_read_bool(np, "fsl,usb_erratum-a006918");
-
-   if (of_get_property(np, "fsl,usb_erratum_14", NULL))
-   pdata->has_fsl_erratum_14 = 1;
-   else
-   pdata->has_fsl_erratum_14 = 0;
+   pdata->has_fsl_erratum_14 =
+   of_property_read_bool(np, "fsl,usb_erratum-14");
 
/*
 * Determine whether phy_clk_valid needs to be checked
-- 
1.7.1

[PATCH v4 1/5] usb: fsl: Set USB_EN bit to select ULPI phy

[Yinbo Zhu]

From: Nikhil Badola 

Set USB_EN bit to select ULPI phy for USB controller version 2.5

Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
Change in v4:
Incorrect indentation of the continuation line

 drivers/usb/host/ehci-fsl.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index e3d0c1c..38674b7 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -122,6 +122,12 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
tmp |= 0x4;
iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
}
+
+   /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
+   if (pdata->controller_ver == FSL_USB_VER_2_5 &&
+   pdata->phy_mode == FSL_USB2_PHY_ULPI)
+   iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
+
/*
 * Enable UTMI phy and program PTS field in UTMI mode before asserting
 * controller reset for USB Controller version 2.5
-- 
1.7.1

[PATCH v3 3/5] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

From: Ramneek Mehresh 

USB erratum-A006918 workaround tries to start internal PHY inside
uboot (when PLL fails to lock). However, if the workaround also
fails, then USB initialization is also stopped inside Linux.
Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
node in device-tree. Presence of this node in device-tree is
used to stop USB controller initialization in Linux

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/ehci-fsl.c  |5 +
 drivers/usb/host/fsl-mph-dr-of.c |4 
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 8b0f3ed..e276067 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -236,6 +236,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+   if (pdata->has_fsl_erratum_a006918) {
+   pr_warn("fsl-ehci: USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
case FSL_USB2_PHY_UTMI_DUAL:
/* PHY_CLK_VALID bit is de-featured from all controller
 * versions below 2.4 and is to be checked only for
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 4f8b8a0..bdc8812 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -230,6 +230,10 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device 
*ofdev)
else
pdata->has_fsl_erratum_14 = 0;
 
+   if (of_get_property(np, "fsl,erratum_a006918", NULL))
+   pdata->has_fsl_erratum_a006918 = 1;
+   else
+   pdata->has_fsl_erratum_a006918 = 0;
 
/*
 * Determine whether phy_clk_valid needs to be checked
-- 
1.7.1

[PATCH v3 1/5] usb: fsl: Set USB_EN bit to select ULPI phy

[Yinbo Zhu]

From: Nikhil Badola 

Set USB_EN bit to select ULPI phy for USB controller version 2.5

Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
Change in v3:
Code base already has patch[5/6], so remove it.  

 drivers/usb/host/ehci-fsl.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index e3d0c1c..ea7e17b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -122,6 +122,12 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
tmp |= 0x4;
iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
}
+
+   /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
+   if (pdata->controller_ver == FSL_USB_VER_2_5 &&
+   pdata->phy_mode == FSL_USB2_PHY_ULPI)
+   iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
+
/*
 * Enable UTMI phy and program PTS field in UTMI mode before asserting
 * controller reset for USB Controller version 2.5
-- 
1.7.1

[PATCH v3 2/5] usb: phy: Workaround for USB erratum-A005728

[Yinbo Zhu]

From: Suresh Gupta 

PHY_CLK_VALID bit for UTMI PHY in USBDR does not set even
if PHY is providing valid clock. Workaround for this
involves resetting of PHY and check PHY_CLK_VALID bit
multiple times. If PHY_CLK_VALID bit is still not set even
after 5 retries, it would be safe to deaclare that PHY
clock is not available.
This erratum is applicable for USBDR less then ver 2.4.

Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
Change in v3:
replace in_be32 with ioread32be

 drivers/usb/host/ehci-fsl.c |   37 ++---
 drivers/usb/host/ehci-fsl.h |3 +++
 2 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index ea7e17b..8b0f3ed 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -183,6 +183,17 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
return retval;
 }
 
+static bool usb_phy_clk_valid(struct usb_hcd *hcd)
+{
+   void __iomem *non_ehci = hcd->regs;
+   bool ret = true;
+
+   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
+   ret = false;
+
+   return ret;
+}
+
 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
   enum fsl_usb2_phy_modes phy_mode,
   unsigned int port_offset)
@@ -226,6 +237,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
/* fall through */
case FSL_USB2_PHY_UTMI:
case FSL_USB2_PHY_UTMI_DUAL:
+   /* PHY_CLK_VALID bit is de-featured from all controller
+* versions below 2.4 and is to be checked only for
+* internal UTMI phy
+*/
+   if (pdata->controller_ver > FSL_USB_VER_2_4 &&
+   pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
+   pr_err("fsl-ehci: USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
@@ -249,17 +270,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
 
-   /*
-* check PHY_CLK_VALID to determine phy clock presence before writing
-* to portsc
-*/
-   if (pdata->check_phy_clk_valid) {
-   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
-   PHY_CLK_VALID)) {
-   dev_warn(hcd->self.controller,
-"USB PHY clock invalid\n");
-   return -EINVAL;
-   }
+   if (pdata->have_sysif_regs &&
+   pdata->controller_ver > FSL_USB_VER_1_6 &&
+   !usb_phy_clk_valid(hcd)) {
+   dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
+   return -EINVAL;
}
 
ehci_writel(ehci, portsc, >regs->port_status[port_offset]);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index cbc4220..9d18c6e 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -50,4 +50,7 @@
 #define UTMI_PHY_EN (1<<9)
 #define ULPI_PHY_CLK_SEL(1<<10)
 #define PHY_CLK_VALID  (1<<17)
+
+/* Retry count for checking UTMI PHY CLK validity */
+#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
 #endif /* _EHCI_FSL_H */
-- 
1.7.1

[PATCH v3 5/5] usb :fsl: Change string format for errata property

[Yinbo Zhu]

From: Nikhil Badola 

Remove USB errata checking code from driver. Applicability of erratum
is retrieved by reading corresponding property in device tree.
This property is written during device tree fixup.

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/fsl-mph-dr-of.c |   14 --
 1 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index bdc8812..ae8f60f 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -224,16 +224,10 @@ static int fsl_usb2_mph_dr_of_probe(struct 
platform_device *ofdev)
of_property_read_bool(np, "fsl,usb-erratum-a005275");
pdata->has_fsl_erratum_a005697 =
of_property_read_bool(np, "fsl,usb_erratum-a005697");
-
-   if (of_get_property(np, "fsl,usb_erratum_14", NULL))
-   pdata->has_fsl_erratum_14 = 1;
-   else
-   pdata->has_fsl_erratum_14 = 0;
-
-   if (of_get_property(np, "fsl,erratum_a006918", NULL))
-   pdata->has_fsl_erratum_a006918 = 1;
-   else
-   pdata->has_fsl_erratum_a006918 = 0;
+   pdata->has_fsl_erratum_a006918 =
+   of_property_read_bool(np, "fsl,usb_erratum-a006918");
+   pdata->has_fsl_erratum_14 =
+   of_property_read_bool(np, "fsl,usb_erratum-14");
 
/*
 * Determine whether phy_clk_valid needs to be checked
-- 
1.7.1

[PATCH v3 4/5] usb: linux/fsl_device: Add platform member has_fsl_erratum_a006918

[Yinbo Zhu]

From: Yinbo Zhu 

This patch is to add member has_fsl_erratum_a006918 in platform data

Signed-off-by: Yinbo Zhu 
---
 include/linux/fsl_devices.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 5da56a6..4c613da 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -102,6 +102,7 @@ struct fsl_usb2_platform_data {
unsignedhas_fsl_erratum_14:1;
unsignedhas_fsl_erratum_a005275:1;
unsignedhas_fsl_erratum_a005697:1;
+   unsignedhas_fsl_erratum_a006918:1;
unsignedcheck_phy_clk_valid:1;
 
/* register save area for suspend/resume */
-- 
1.7.1

[PATCH v2 5/6] usb: linux/fsl_device: Add platform member has_fsl_erratum_14

[Yinbo Zhu]

From: Yinbo Zhu 

This patch is to add member has_fsl_erratum_14 in platform data

Signed-off-by: Yinbo Zhu 
---
 include/linux/fsl_devices.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 7ea53c8..5c21a3a 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -102,6 +102,7 @@ struct fsl_usb2_platform_data {
unsignedhas_fsl_erratum_a005275:1;
unsignedhas_fsl_erratum_a005697:1;
unsignedhas_fsl_erratum_a006918:1;
+   unsignedhas_fsl_erratum_14:1;
unsignedcheck_phy_clk_valid:1;
 
/* register save area for suspend/resume */
-- 
1.7.1

[PATCH v2 4/6] usb: linux/fsl_device: Add platform member has_fsl_erratum_a006918

[Yinbo Zhu]

From: Yinbo Zhu 

This patch is to add member has_fsl_erratum_a006918 in platform data

Signed-off-by: Yinbo Zhu 
---
 include/linux/fsl_devices.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 60cef82..7ea53c8 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -101,6 +101,7 @@ struct fsl_usb2_platform_data {
unsignedhas_fsl_erratum_a007792:1;
unsignedhas_fsl_erratum_a005275:1;
unsignedhas_fsl_erratum_a005697:1;
+   unsignedhas_fsl_erratum_a006918:1;
unsignedcheck_phy_clk_valid:1;
 
/* register save area for suspend/resume */
-- 
1.7.1

[PATCH v2 6/6] usb :fsl: Change string format for errata property

[Yinbo Zhu]

From: Nikhil Badola 

Remove USB errata checking code from driver. Applicability of erratum
is retrieved by reading corresponding property in device tree.
This property is written during device tree fixup.

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
 drivers/usb/host/ehci-fsl.c  |7 +--
 drivers/usb/host/fsl-mph-dr-of.c |9 -
 2 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6884130..c71680e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -310,14 +310,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
return -EINVAL;
 
if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
-   unsigned int chip, rev, svr;
-
-   svr = mfspr(SPRN_SVR);
-   chip = svr >> 16;
-   rev = (svr >> 4) & 0xf;
 
/* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
-   if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
+   if (pdata->has_fsl_erratum_14 == 1)
ehci->has_fsl_port_bug = 1;
 
if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 7e07701..ae8f60f 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -224,11 +224,10 @@ static int fsl_usb2_mph_dr_of_probe(struct 
platform_device *ofdev)
of_property_read_bool(np, "fsl,usb-erratum-a005275");
pdata->has_fsl_erratum_a005697 =
of_property_read_bool(np, "fsl,usb_erratum-a005697");
-
-   if (of_get_property(np, "fsl,erratum_a006918", NULL))
-   pdata->has_fsl_erratum_a006918 = 1;
-   else
-   pdata->has_fsl_erratum_a006918 = 0;
+   pdata->has_fsl_erratum_a006918 =
+   of_property_read_bool(np, "fsl,usb_erratum-a006918");
+   pdata->has_fsl_erratum_14 =
+   of_property_read_bool(np, "fsl,usb_erratum-14");
 
/*
 * Determine whether phy_clk_valid needs to be checked
-- 
1.7.1

[PATCH v2 3/6] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

From: yinbo.zhu 

USB erratum-A006918 workaround tries to start internal PHY inside
uboot (when PLL fails to lock). However, if the workaround also
fails, then USB initialization is also stopped inside Linux.
Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
node in device-tree. Presence of this node in device-tree is
used to stop USB controller initialization in Linux

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
Change in v2:
replace Yinbo.Zhu with Yinbo Zhu

 drivers/usb/host/ehci-fsl.c  |5 +
 drivers/usb/host/fsl-mph-dr-of.c |5 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index a28ec1e..6884130 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -224,6 +224,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+   if (pdata->has_fsl_erratum_a006918) {
+   pr_warn("fsl-ehci: USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
case FSL_USB2_PHY_UTMI_DUAL:
/* PHY_CLK_VALID bit is de-featured from all controller
 * versions below 2.4 and is to be checked only for
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 677f9d5..7e07701 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -225,6 +225,11 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device 
*ofdev)
pdata->has_fsl_erratum_a005697 =
of_property_read_bool(np, "fsl,usb_erratum-a005697");
 
+   if (of_get_property(np, "fsl,erratum_a006918", NULL))
+   pdata->has_fsl_erratum_a006918 = 1;
+   else
+   pdata->has_fsl_erratum_a006918 = 0;
+
/*
 * Determine whether phy_clk_valid needs to be checked
 * by reading property in device tree
-- 
1.7.1

[PATCH v2 2/6] usb: phy: Workaround for USB erratum-A005728

[Yinbo Zhu]

From: Suresh Gupta 

PHY_CLK_VALID bit for UTMI PHY in USBDR does not set even
if PHY is providing valid clock. Workaround for this
involves resetting of PHY and check PHY_CLK_VALID bit
multiple times. If PHY_CLK_VALID bit is still not set even
after 5 retries, it would be safe to deaclare that PHY
clock is not available.
This erratum is applicable for USBDR less then ver 2.4.

Signed-off-by: Suresh Gupta 
Signed-off-by: Yinbo Zhu 
---
Change in v2:
replace Yinbo.Zhu with Yinbo Zhu

 drivers/usb/host/ehci-fsl.c |   37 ++---
 drivers/usb/host/ehci-fsl.h |3 +++
 2 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 71c4661..a28ec1e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -176,6 +176,17 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
return retval;
 }
 
+static bool usb_phy_clk_valid(struct usb_hcd *hcd)
+{
+   void __iomem *non_ehci = hcd->regs;
+   bool ret = true;
+
+   if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
+   ret = false;
+
+   return ret;
+}
+
 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
   enum fsl_usb2_phy_modes phy_mode,
   unsigned int port_offset)
@@ -214,6 +225,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
/* fall through */
case FSL_USB2_PHY_UTMI:
case FSL_USB2_PHY_UTMI_DUAL:
+   /* PHY_CLK_VALID bit is de-featured from all controller
+* versions below 2.4 and is to be checked only for
+* internal UTMI phy
+*/
+   if (pdata->controller_ver > FSL_USB_VER_2_4 &&
+   pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
+   pr_err("fsl-ehci: USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
@@ -232,17 +253,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
 
-   /*
-* check PHY_CLK_VALID to determine phy clock presence before writing
-* to portsc
-*/
-   if (pdata->check_phy_clk_valid) {
-   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
-   PHY_CLK_VALID)) {
-   dev_warn(hcd->self.controller,
-"USB PHY clock invalid\n");
-   return -EINVAL;
-   }
+   if (pdata->have_sysif_regs &&
+   pdata->controller_ver > FSL_USB_VER_1_6 &&
+   !usb_phy_clk_valid(hcd)) {
+   dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
+   return -EINVAL;
}
 
ehci_writel(ehci, portsc, >regs->port_status[port_offset]);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index cbc4220..9d18c6e 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -50,4 +50,7 @@
 #define UTMI_PHY_EN (1<<9)
 #define ULPI_PHY_CLK_SEL(1<<10)
 #define PHY_CLK_VALID  (1<<17)
+
+/* Retry count for checking UTMI PHY CLK validity */
+#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
 #endif /* _EHCI_FSL_H */
-- 
1.7.1

[PATCH v2 1/6] usb: fsl: Set USB_EN bit to select ULPI phy

[Yinbo Zhu]

From: Nikhil Badola 

Set USB_EN bit to select ULPI phy for USB controller version 2.5

Signed-off-by: Nikhil Badola 
Signed-off-by: Yinbo Zhu 
---
Change in v2:
replace Yinbo.Zhu with Yinbo Zhu 

 drivers/usb/host/ehci-fsl.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 0a9fd20..71c4661 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -118,6 +118,12 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
CONTROL_REGISTER_W1C_MASK, 0x4);
 
+   /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
+   if (pdata->controller_ver == FSL_USB_VER_2_5 &&
+   pdata->phy_mode == FSL_USB2_PHY_ULPI)
+   iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
+
+
/*
 * Enable UTMI phy and program PTS field in UTMI mode before asserting
 * controller reset for USB Controller version 2.5
-- 
1.7.1

RE: [PATCH v1 3/6] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

-Original Message-
From: Sergei Shtylyov [mailto:sergei.shtyl...@cogentembedded.com] 
Sent: 2019年1月21日 16:17
To: Yinbo Zhu ; Alan Stern 
Cc: Xiaobo Xie ; Jerry Huang ; Ran 
Wang ; Greg Kroah-Hartman ; 
Ramneek Mehresh ; Nikhil Badola 
; Suresh Gupta ; 
linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 3/6] usb: host: Stops USB controller init if PLL fails 
to lock

>Hello!

> On 21.01.2019 6:13, Yinbo Zhu wrote:

> From: yinbo.zhu 
> 
> USB erratum-A006918 workaround tries to start internal PHY inside 
> uboot (when PLL fails to lock). However, if the workaround also fails, 
> then USB initialization is also stopped inside Linux.
> Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
> node in device-tree. Presence of this node in device-tree is used to 
> stop USB controller initialization in Linux
> 
> Signed-off-by: Ramneek Mehresh 
> Signed-off-by: Suresh Gupta 
> Signed-off-by: yinbo.zhu 
> ---
>   drivers/usb/host/ehci-fsl.c  |5 +
>   drivers/usb/host/fsl-mph-dr-of.c |5 +
>   2 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c 
> index a28ec1e..6884130 100644
> --- a/drivers/usb/host/ehci-fsl.c
> +++ b/drivers/usb/host/ehci-fsl.c
> @@ -224,6 +224,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
>   portsc |= PORT_PTS_PTW;
>   /* fall through */
>   case FSL_USB2_PHY_UTMI:
> + if (pdata->has_fsl_erratum_a006918) {
> + pr_warn("fsl-ehci: USB PHY clock invalid\n");
> + return -EINVAL;
> + }
> +
>   case FSL_USB2_PHY_UTMI_DUAL:
>   /* PHY_CLK_VALID bit is de-featured from all controller
>* versions below 2.4 and is to be checked only for diff --git 
> a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
> index 677f9d5..7e07701 100644
> --- a/drivers/usb/host/fsl-mph-dr-of.c
> +++ b/drivers/usb/host/fsl-mph-dr-of.c
> @@ -225,6 +225,11 @@ static int fsl_usb2_mph_dr_of_probe(struct 
> platform_device *ofdev)
>   pdata->has_fsl_erratum_a005697 =
>   of_property_read_bool(np, "fsl,usb_erratum-a005697");
>   
> + if (of_get_property(np, "fsl,erratum_a006918", NULL))

>of_property_read_bool() perhaps?

Hi Sergei,

[PATCH v1 6/6] had modified it as this string format,
Please you note.

MBR, Yinbo
> + pdata->has_fsl_erratum_a006918 = 1;
> + else
> + pdata->has_fsl_erratum_a006918 = 0;
> +
>   /*
>* Determine whether phy_clk_valid needs to be checked
>* by reading property in device tree

> MBR, Sergei

[PATCH v1 2/6] usb: phy: Workaround for USB erratum-A005728

[Yinbo Zhu]

From: Suresh Gupta 

PHY_CLK_VALID bit for UTMI PHY in USBDR does not set even
if PHY is providing valid clock. Workaround for this
involves resetting of PHY and check PHY_CLK_VALID bit
multiple times. If PHY_CLK_VALID bit is still not set even
after 5 retries, it would be safe to deaclare that PHY
clock is not available.
This erratum is applicable for USBDR less then ver 2.4.

Signed-off-by: Suresh Gupta 
Signed-off-by: yinbo.zhu 
---
 drivers/usb/host/ehci-fsl.c |   37 ++---
 drivers/usb/host/ehci-fsl.h |3 +++
 2 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 71c4661..a28ec1e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -176,6 +176,17 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
return retval;
 }
 
+static bool usb_phy_clk_valid(struct usb_hcd *hcd)
+{
+   void __iomem *non_ehci = hcd->regs;
+   bool ret = true;
+
+   if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
+   ret = false;
+
+   return ret;
+}
+
 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
   enum fsl_usb2_phy_modes phy_mode,
   unsigned int port_offset)
@@ -214,6 +225,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
/* fall through */
case FSL_USB2_PHY_UTMI:
case FSL_USB2_PHY_UTMI_DUAL:
+   /* PHY_CLK_VALID bit is de-featured from all controller
+* versions below 2.4 and is to be checked only for
+* internal UTMI phy
+*/
+   if (pdata->controller_ver > FSL_USB_VER_2_4 &&
+   pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
+   pr_err("fsl-ehci: USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
@@ -232,17 +253,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
 
-   /*
-* check PHY_CLK_VALID to determine phy clock presence before writing
-* to portsc
-*/
-   if (pdata->check_phy_clk_valid) {
-   if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
-   PHY_CLK_VALID)) {
-   dev_warn(hcd->self.controller,
-"USB PHY clock invalid\n");
-   return -EINVAL;
-   }
+   if (pdata->have_sysif_regs &&
+   pdata->controller_ver > FSL_USB_VER_1_6 &&
+   !usb_phy_clk_valid(hcd)) {
+   dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
+   return -EINVAL;
}
 
ehci_writel(ehci, portsc, >regs->port_status[port_offset]);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index cbc4220..9d18c6e 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -50,4 +50,7 @@
 #define UTMI_PHY_EN (1<<9)
 #define ULPI_PHY_CLK_SEL(1<<10)
 #define PHY_CLK_VALID  (1<<17)
+
+/* Retry count for checking UTMI PHY CLK validity */
+#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
 #endif /* _EHCI_FSL_H */
-- 
1.7.1

[PATCH v1 5/6] usb: linux/fsl_device: Add platform member has_fsl_erratum_14

[Yinbo Zhu]

This patch is to add member has_fsl_erratum_14 in platform data

Signed-off-by: Yinbo Zhu 
---
 include/linux/fsl_devices.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 7ea53c8..5c21a3a 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -102,6 +102,7 @@ struct fsl_usb2_platform_data {
unsignedhas_fsl_erratum_a005275:1;
unsignedhas_fsl_erratum_a005697:1;
unsignedhas_fsl_erratum_a006918:1;
+   unsignedhas_fsl_erratum_14:1;
unsignedcheck_phy_clk_valid:1;
 
/* register save area for suspend/resume */
-- 
1.7.1

[PATCH v1 3/6] usb: host: Stops USB controller init if PLL fails to lock

[Yinbo Zhu]

From: yinbo.zhu 

USB erratum-A006918 workaround tries to start internal PHY inside
uboot (when PLL fails to lock). However, if the workaround also
fails, then USB initialization is also stopped inside Linux.
Erratum-A006918 workaround failure creates "fsl,erratum_a006918"
node in device-tree. Presence of this node in device-tree is
used to stop USB controller initialization in Linux

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Suresh Gupta 
Signed-off-by: yinbo.zhu 
---
 drivers/usb/host/ehci-fsl.c  |5 +
 drivers/usb/host/fsl-mph-dr-of.c |5 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index a28ec1e..6884130 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -224,6 +224,11 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+   if (pdata->has_fsl_erratum_a006918) {
+   pr_warn("fsl-ehci: USB PHY clock invalid\n");
+   return -EINVAL;
+   }
+
case FSL_USB2_PHY_UTMI_DUAL:
/* PHY_CLK_VALID bit is de-featured from all controller
 * versions below 2.4 and is to be checked only for
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 677f9d5..7e07701 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -225,6 +225,11 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device 
*ofdev)
pdata->has_fsl_erratum_a005697 =
of_property_read_bool(np, "fsl,usb_erratum-a005697");
 
+   if (of_get_property(np, "fsl,erratum_a006918", NULL))
+   pdata->has_fsl_erratum_a006918 = 1;
+   else
+   pdata->has_fsl_erratum_a006918 = 0;
+
/*
 * Determine whether phy_clk_valid needs to be checked
 * by reading property in device tree
-- 
1.7.1

[PATCH v1 4/6] usb: linux/fsl_device: Add platform member has_fsl_erratum_a006918

[Yinbo Zhu]

This patch is to add member has_fsl_erratum_a006918 in platform data

Signed-off-by: Yinbo Zhu 
---
 include/linux/fsl_devices.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 60cef82..7ea53c8 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -101,6 +101,7 @@ struct fsl_usb2_platform_data {
unsignedhas_fsl_erratum_a007792:1;
unsignedhas_fsl_erratum_a005275:1;
unsignedhas_fsl_erratum_a005697:1;
+   unsignedhas_fsl_erratum_a006918:1;
unsignedcheck_phy_clk_valid:1;
 
/* register save area for suspend/resume */
-- 
1.7.1

[PATCH v1 6/6] usb :fsl: Change string format for errata property

[Yinbo Zhu]

From: Nikhil Badola 

Remove USB errata checking code from driver. Applicability of erratum
is retrieved by reading corresponding property in device tree.
This property is written during device tree fixup.

Signed-off-by: Ramneek Mehresh 
Signed-off-by: Nikhil Badola 
Signed-off-by: yinbo.zhu 
---
 drivers/usb/host/ehci-fsl.c  |7 +--
 drivers/usb/host/fsl-mph-dr-of.c |9 -
 2 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6884130..c71680e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -310,14 +310,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
return -EINVAL;
 
if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
-   unsigned int chip, rev, svr;
-
-   svr = mfspr(SPRN_SVR);
-   chip = svr >> 16;
-   rev = (svr >> 4) & 0xf;
 
/* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
-   if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
+   if (pdata->has_fsl_erratum_14 == 1)
ehci->has_fsl_port_bug = 1;
 
if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 7e07701..ae8f60f 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -224,11 +224,10 @@ static int fsl_usb2_mph_dr_of_probe(struct 
platform_device *ofdev)
of_property_read_bool(np, "fsl,usb-erratum-a005275");
pdata->has_fsl_erratum_a005697 =
of_property_read_bool(np, "fsl,usb_erratum-a005697");
-
-   if (of_get_property(np, "fsl,erratum_a006918", NULL))
-   pdata->has_fsl_erratum_a006918 = 1;
-   else
-   pdata->has_fsl_erratum_a006918 = 0;
+   pdata->has_fsl_erratum_a006918 =
+   of_property_read_bool(np, "fsl,usb_erratum-a006918");
+   pdata->has_fsl_erratum_14 =
+   of_property_read_bool(np, "fsl,usb_erratum-14");
 
/*
 * Determine whether phy_clk_valid needs to be checked
-- 
1.7.1

[PATCH v1 1/6] usb: fsl: Set USB_EN bit to select ULPI phy

[Yinbo Zhu]

From: Nikhil Badola 

Set USB_EN bit to select ULPI phy for USB controller version 2.5

Signed-off-by: Nikhil Badola 
Signed-off-by: yinbo.zhu 
---
 drivers/usb/host/ehci-fsl.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 0a9fd20..71c4661 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -118,6 +118,12 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
CONTROL_REGISTER_W1C_MASK, 0x4);
 
+   /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
+   if (pdata->controller_ver == FSL_USB_VER_2_5 &&
+   pdata->phy_mode == FSL_USB2_PHY_ULPI)
+   iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
+
+
/*
 * Enable UTMI phy and program PTS field in UTMI mode before asserting
 * controller reset for USB Controller version 2.5
-- 
1.7.1

[PATCH v1] arch: arm64: add ARM64 specific fucntions required for ehci fsl driver

[Yinbo Zhu]

From: Rajesh Bhagat 

Add set/clear bits functions for ARM platform which are used by ehci fsl
driver

Signed-off-by: Rajesh Bhagat 
Signed-off-by: Yinbo Zhu 
---
 arch/arm64/include/asm/io.h |   29 +
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index e97b861..0dc4334 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -185,6 +185,35 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, 
size_t size);
 #define iowrite32be(v,p)   ({ __iowmb(); __raw_writel((__force 
__u32)cpu_to_be32(v), p); })
 #define iowrite64be(v,p)   ({ __iowmb(); __raw_writeq((__force 
__u64)cpu_to_be64(v), p); })
 
+/* access ports */
+#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
+#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
+
+#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
+#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
+
+#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
+#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
+
+/* Clear and set bits in one shot.  These macros can be used to clear and
+ * set multiple bits in a register using a single read-modify-write.  These
+ * macros can also be used to set a multiple-bit bit pattern using a mask,
+ * by specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrsetbits_be32(addr, clear, set) \
+   iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_le32(addr, clear, set) \
+   iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_be16(addr, clear, set) \
+   iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_le16(addr, clear, set) \
+   iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_8(addr, clear, set) \
+   iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
+
+
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  * access
-- 
1.7.1

[PATCH v1] arch: arm64: add ARM64 specific fucntions required for ehci fsl driver

[Yinbo Zhu]

From: Rajesh Bhagat 

Add set/clear bits functions for ARM platform which are used by ehci fsl
driver

Signed-off-by: Rajesh Bhagat 
Signed-off-by: Yinbo Zhu 
---
 arch/arm64/include/asm/io.h |   29 +
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index e97b861..0dc4334 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -185,6 +185,35 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, 
size_t size);
 #define iowrite32be(v,p)   ({ __iowmb(); __raw_writel((__force 
__u32)cpu_to_be32(v), p); })
 #define iowrite64be(v,p)   ({ __iowmb(); __raw_writeq((__force 
__u64)cpu_to_be64(v), p); })
 
+/* access ports */
+#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
+#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
+
+#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
+#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
+
+#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
+#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
+
+/* Clear and set bits in one shot.  These macros can be used to clear and
+ * set multiple bits in a register using a single read-modify-write.  These
+ * macros can also be used to set a multiple-bit bit pattern using a mask,
+ * by specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrsetbits_be32(addr, clear, set) \
+   iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_le32(addr, clear, set) \
+   iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_be16(addr, clear, set) \
+   iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_le16(addr, clear, set) \
+   iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_8(addr, clear, set) \
+   iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
+
+
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  * access
-- 
1.7.1

[PATCH v2] arm64: dts: lx2160a: enable eSDHC controller

[Yinbo Zhu]

There are two eSDHC controllers in lx2160a. This patch is to
enable eSDHC for RDB and QDS board.

Signed-off-by: Yinbo Zhu 
---
Change in v2:
squash all lx2160a esdhc dts patch into the original patch

 arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts |8 ++
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts |   15 
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi|   25 +
 3 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index bc30173..b58b96c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -294,6 +294,14 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
dflash0: n25q128a {
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 53b0e80..cbe8919 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -170,6 +170,21 @@
status = "okay";
 };
 
+ {
+   sd-uhs-sdr104;
+   sd-uhs-sdr50;
+   sd-uhs-sdr25;
+   sd-uhs-sdr12;
+   status = "okay";
+};
+
+ {
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   bus-width = <8>;
+   status = "okay";
+};
+
  {
status = "okay";
nxp,fspi-has-second-chip;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index fa4a1f8..174544a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -356,6 +356,31 @@
little-endian;
};
 
+   esdhc0: esdhc@214 {
+   compatible = "fsl,esdhc";
+   reg = <0x0 0x214 0x0 0x1>;
+   interrupts = <0 28 0x4>; /* Level high type */
+   clocks = < 4 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
+   esdhc1: esdhc@215 {
+   compatible = "fsl,esdhc";
+   reg = <0x0 0x215 0x0 0x1>;
+   interrupts = <0 63 0x4>; /* Level high type */
+   clocks = < 4 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   broken-cd;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
gpio0: gpio@230 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x230 0x0 0x1>;
-- 
1.7.1

[PATCH v2] arm64: dts: lx2160a: enable eSDHC controller

[Yinbo Zhu]

There are two eSDHC controllers in lx2160a. This patch is to
enable eSDHC for RDB and QDS board.

Signed-off-by: Yinbo Zhu 
---
Change in v2:
squash all lx2160a esdhc dts patch into the original patch

 arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts |8 ++
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts |   15 
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi|   25 +
 3 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index bc30173..b58b96c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -294,6 +294,14 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
dflash0: n25q128a {
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 53b0e80..cbe8919 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -170,6 +170,21 @@
status = "okay";
 };
 
+ {
+   sd-uhs-sdr104;
+   sd-uhs-sdr50;
+   sd-uhs-sdr25;
+   sd-uhs-sdr12;
+   status = "okay";
+};
+
+ {
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   bus-width = <8>;
+   status = "okay";
+};
+
  {
status = "okay";
nxp,fspi-has-second-chip;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index fa4a1f8..174544a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -356,6 +356,31 @@
little-endian;
};
 
+   esdhc0: esdhc@214 {
+   compatible = "fsl,esdhc";
+   reg = <0x0 0x214 0x0 0x1>;
+   interrupts = <0 28 0x4>; /* Level high type */
+   clocks = < 4 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
+   esdhc1: esdhc@215 {
+   compatible = "fsl,esdhc";
+   reg = <0x0 0x215 0x0 0x1>;
+   interrupts = <0 63 0x4>; /* Level high type */
+   clocks = < 4 1>;
+   voltage-ranges = <1800 1800 3300 3300>;
+   sdhci,auto-cmd12;
+   broken-cd;
+   little-endian;
+   bus-width = <4>;
+   status = "disabled";
+   };
+
gpio0: gpio@230 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x230 0x0 0x1>;
-- 
1.7.1

[PATCH v2] arm64: dts: ls1043a: Add configure-gfladj property to USB3 node

[Yinbo Zhu]

From: Rajesh Bhagat 

Add "configure-gfladj" boolean property to USB3 node. This property
is used to determine whether frame length adjustment is required or
not

Signed-off-by: Rajesh Bhagat 
Signed-off-by: Ran Wang 
Signed-off-by: Yinbo Zhu 
---
Change in v2:
Modified some word misspellings in commit information

 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 7881e3d..ed3fa79 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -609,6 +609,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   configure-gfladj;
};
 
usb1: usb3@300 {
@@ -618,6 +619,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   configure-gfladj;
};
 
usb2: usb3@310 {
@@ -627,6 +629,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   configure-gfladj;
};
 
sata: sata@320 {
-- 
1.7.1

[PATCH v2] arm64: dts: ls1043a: Add configure-gfladj property to USB3 node

[Yinbo Zhu]

From: Rajesh Bhagat 

Add "configure-gfladj" boolean property to USB3 node. This property
is used to determine whether frame length adjustment is required or
not

Signed-off-by: Rajesh Bhagat 
Signed-off-by: Ran Wang 
Signed-off-by: Yinbo Zhu 
---
Change in v2:
Modified some word misspellings in commit information

 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 7881e3d..ed3fa79 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -609,6 +609,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   configure-gfladj;
};
 
usb1: usb3@300 {
@@ -618,6 +619,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   configure-gfladj;
};
 
usb2: usb3@310 {
@@ -627,6 +629,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   configure-gfladj;
};
 
sata: sata@320 {
-- 
1.7.1

[PATCH v1] arm64: dts: ls1043a: Add configure-gfladj property to USB3 node

[Yinbo Zhu]

From: Rajesh Bhagat 

Add "configure-gfladj" boolean property to USB3 node. This property
is used to determine whether frame length adjustent is required or
not

Signed-off-by: Rajesh Bhagat 
Signed-off-by: Ran Wang 
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index a830a2e..a3c5165 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -610,6 +610,7 @@
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
dma-coherent;
+   configure-gfladj;
};
 
usb1: usb3@300 {
@@ -623,6 +624,7 @@
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
dma-coherent;
+   configure-gfladj;
};
 
usb2: usb3@310 {
@@ -636,6 +638,7 @@
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
dma-coherent;
+   configure-gfladj;
};
 
sata: sata@320 {
-- 
1.7.1

[PATCH v1] arm64: dts: ls1043a: Add configure-gfladj property to USB3 node

[Yinbo Zhu]

From: Rajesh Bhagat 

Add "configure-gfladj" boolean property to USB3 node. This property
is used to determine whether frame length adjustent is required or
not

Signed-off-by: Rajesh Bhagat 
Signed-off-by: Ran Wang 
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index a830a2e..a3c5165 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -610,6 +610,7 @@
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
dma-coherent;
+   configure-gfladj;
};
 
usb1: usb3@300 {
@@ -623,6 +624,7 @@
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
dma-coherent;
+   configure-gfladj;
};
 
usb2: usb3@310 {
@@ -636,6 +638,7 @@
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
dma-coherent;
+   configure-gfladj;
};
 
sata: sata@320 {
-- 
1.7.1

RE: [PATCH 3/9] soc: fsl: set rcpm bit for FTM

[Yinbo Zhu]

-Original Message-
From: Leo Li 
Sent: 2018年5月12日 1:00
To: Yinbo Zhu <yinbo@nxp.com>; Yinbo Zhu <yinbo@nxp.com>; Rob Herring 
<robh...@kernel.org>; Mark Rutland <mark.rutl...@arm.com>; Catalin Marinas ) 
<catalin.mari...@arm.com>; Will Deacon ) <will.dea...@arm.com>; Lorenzo 
Pieralisi ) <lorenzo.pieral...@arm.com>
Cc: Xiaobo Xie <xiaobo@nxp.com>; Ran Wang <ran.wan...@nxp.com>; Daniel 
Lezcano <daniel.lezc...@linaro.org>; Thomas Gleixner <t...@linutronix.de>; 
Shawn Guo <shawn...@kernel.org>; Madalin-cristian Bucur 
<madalin.bu...@nxp.com>; Z.q. Hou <zhiqiang@nxp.com>; Jerry Huang 
<jerry.hu...@nxp.com>; M.h. Lian <minghuan.l...@nxp.com>; Qiang Zhao 
<qiang.z...@nxp.com>; Fabio Estevam <fabio.este...@nxp.com>; Jiaheng Fan 
<jiaheng@nxp.com>; Po Liu <po@nxp.com>; Nipun Gupta 
<nipun.gu...@nxp.com>; Horia Geantă <horia.gea...@nxp.com>; Priyanka Jain 
<priyanka.j...@nxp.com>; Sumit Garg <sumit.g...@nxp.com>; costi 
<constantin.tu...@freescale.com>; Bogdan Purcareata 
<bogdan.purcare...@nxp.com>; open list:CLOCKSOURCE, CLOCKEVENT DRIVERS 
<linux-kernel@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE 
TREE BINDINGS <devicet...@vger.kernel.org>; 
linux-arm-ker...@lists.infradead.org; open list:FREESCALE SOC DRIVERS 
<linuxppc-...@lists.ozlabs.org>; Andy Tang <andy.t...@nxp.com>; Ying Zhang 
<ying.zhang22...@nxp.com>
Subject: RE: [PATCH 3/9] soc: fsl: set rcpm bit for FTM



> -Original Message-
> From: Yinbo Zhu [mailto:yinbo@nxp.com]
> Sent: Thursday, May 10, 2018 10:35 PM
> To: Yinbo Zhu <yinbo@nxp.com>; Rob Herring <robh...@kernel.org>; 
> Mark Rutland <mark.rutl...@arm.com>; Catalin Marinas ) 
> <catalin.mari...@arm.com>; Will Deacon ) <will.dea...@arm.com>; 
> Lorenzo Pieralisi ) <lorenzo.pieral...@arm.com>; Leo Li 
> <leoyang...@nxp.com>
> Cc: Xiaobo Xie <xiaobo@nxp.com>; Ran Wang <ran.wan...@nxp.com>; 
> Daniel Lezcano <daniel.lezc...@linaro.org>; Thomas Gleixner 
> <t...@linutronix.de>; Shawn Guo <shawn...@kernel.org>; 
> Madalin-cristian Bucur <madalin.bu...@nxp.com>; Z.q. Hou 
> <zhiqiang@nxp.com>; Jerry Huang <jerry.hu...@nxp.com>; M.h. Lian 
> <minghuan.l...@nxp.com>; Qiang Zhao <qiang.z...@nxp.com>; Fabio 
> Estevam <fabio.este...@nxp.com>; Jiaheng Fan <jiaheng@nxp.com>; Po 
> Liu <po@nxp.com>; Nipun Gupta <nipun.gu...@nxp.com>; Horia Geantă 
> <horia.gea...@nxp.com>; Priyanka Jain <priyanka.j...@nxp.com>; Sumit 
> Garg <sumit.g...@nxp.com>; costi <constantin.tu...@freescale.com>; 
> Bogdan Purcareata <bogdan.purcare...@nxp.com>; Meng Yi 
> <meng...@nxp.com>; Wang Dongsheng <dongsheng.w...@nxp.com>; open 
> list:CLOCKSOURCE, CLOCKEVENT DRIVERS <linux-kernel@vger.kernel.org>; 
> open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS 
> <devicet...@vger.kernel.org>; linux-arm-ker...@lists.infradead.org; 
> open list:FREESCALE SOC DRIVERS <linuxppc-...@lists.ozlabs.org>; Andy 
> Tang <andy.t...@nxp.com>; Ying Zhang <ying.zhang22...@nxp.com>
> Subject: [PATCH 3/9] soc: fsl: set rcpm bit for FTM
> 
> From: Zhang Ying-22455 <ying.zhang22...@nxp.com>
> 
> Set RCPM for FTM when using FTM as wakeup source. Because the RCPM 
> module of each platform has different big-end and little-end mode, 
> there need to set RCPM depending on the platform.
> 
> Signed-off-by: Zhang Ying-22455 <ying.zhang22...@nxp.com>
> Signed-off-by: Yinbo Zhu <yinbo@nxp.com>
> ---
>  .../devicetree/bindings/timer/fsl,ftm-timer.txt|7 ++
>  drivers/soc/fsl/layerscape/ftm_alarm.c |   92 ++-
>  2 files changed, 94 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> index aa8c402..15ead58 100644
> --- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> @@ -3,6 +3,13 @@ Freescale FlexTimer Module (FTM) Timer  Required
> properties:
> 
>  - compatible : should be "fsl,ftm-timer"

>Hi Yingbo,

>This is a change that breaks backward compatibility and not acceptable.
Hi leo,

This patch if I keep the change as inner patch and push it to dash-linnux but I 
will not push it to upstream, It's okay?
As far as I know, there was a other patch and file for replace the file and 
that the patch is already on the upstream 
https://patchwork.kernel.org/patch/9391293/

> + Possible 

RE: [PATCH 3/9] soc: fsl: set rcpm bit for FTM

[Yinbo Zhu]

-Original Message-
From: Leo Li 
Sent: 2018年5月12日 1:00
To: Yinbo Zhu ; Yinbo Zhu ; Rob Herring 
; Mark Rutland ; Catalin Marinas ) 
; Will Deacon ) ; Lorenzo 
Pieralisi ) 
Cc: Xiaobo Xie ; Ran Wang ; Daniel 
Lezcano ; Thomas Gleixner ; 
Shawn Guo ; Madalin-cristian Bucur 
; Z.q. Hou ; Jerry Huang 
; M.h. Lian ; Qiang Zhao 
; Fabio Estevam ; Jiaheng Fan 
; Po Liu ; Nipun Gupta 
; Horia Geantă ; Priyanka Jain 
; Sumit Garg ; costi 
; Bogdan Purcareata 
; open list:CLOCKSOURCE, CLOCKEVENT DRIVERS 
; open list:OPEN FIRMWARE AND FLATTENED DEVICE 
TREE BINDINGS ; 
linux-arm-ker...@lists.infradead.org; open list:FREESCALE SOC DRIVERS 
; Andy Tang ; Ying Zhang 

Subject: RE: [PATCH 3/9] soc: fsl: set rcpm bit for FTM



> -Original Message-
> From: Yinbo Zhu [mailto:yinbo@nxp.com]
> Sent: Thursday, May 10, 2018 10:35 PM
> To: Yinbo Zhu ; Rob Herring ; 
> Mark Rutland ; Catalin Marinas ) 
> ; Will Deacon ) ; 
> Lorenzo Pieralisi ) ; Leo Li 
> 
> Cc: Xiaobo Xie ; Ran Wang ; 
> Daniel Lezcano ; Thomas Gleixner 
> ; Shawn Guo ; 
> Madalin-cristian Bucur ; Z.q. Hou 
> ; Jerry Huang ; M.h. Lian 
> ; Qiang Zhao ; Fabio 
> Estevam ; Jiaheng Fan ; Po 
> Liu ; Nipun Gupta ; Horia Geantă 
> ; Priyanka Jain ; Sumit 
> Garg ; costi ; 
> Bogdan Purcareata ; Meng Yi 
> ; Wang Dongsheng ; open 
> list:CLOCKSOURCE, CLOCKEVENT DRIVERS ; 
> open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS 
> ; linux-arm-ker...@lists.infradead.org; 
> open list:FREESCALE SOC DRIVERS ; Andy 
> Tang ; Ying Zhang 
> Subject: [PATCH 3/9] soc: fsl: set rcpm bit for FTM
> 
> From: Zhang Ying-22455 
> 
> Set RCPM for FTM when using FTM as wakeup source. Because the RCPM 
> module of each platform has different big-end and little-end mode, 
> there need to set RCPM depending on the platform.
> 
> Signed-off-by: Zhang Ying-22455 
> Signed-off-by: Yinbo Zhu 
> ---
>  .../devicetree/bindings/timer/fsl,ftm-timer.txt|7 ++
>  drivers/soc/fsl/layerscape/ftm_alarm.c |   92 ++-
>  2 files changed, 94 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> index aa8c402..15ead58 100644
> --- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> @@ -3,6 +3,13 @@ Freescale FlexTimer Module (FTM) Timer  Required
> properties:
> 
>  - compatible : should be "fsl,ftm-timer"

>Hi Yingbo,

>This is a change that breaks backward compatibility and not acceptable.
Hi leo,

This patch if I keep the change as inner patch and push it to dash-linnux but I 
will not push it to upstream, It's okay?
As far as I know, there was a other patch and file for replace the file and 
that the patch is already on the upstream 
https://patchwork.kernel.org/patch/9391293/

> + Possible compatibles for ARM:
> + "fsl,ls1012a-ftm"
> + "fsl,ls1021a-ftm"
> + "fsl,ls1043a-ftm"
> + "fsl,ls1046a-ftm"
> + "fsl,ls1088a-ftm"
> + "fsl,ls208xa-ftm"
>  - reg : Specifies base physical address and size of the register sets for the
>clock event device and clock source device.
>  - interrupts : Should be the clock event device interrupt.
> diff --git a/drivers/soc/fsl/layerscape/ftm_alarm.c
> b/drivers/soc/fsl/layerscape/ftm_alarm.c
> index 6f9882f..811dcfa 100644
> --- a/drivers/soc/fsl/layerscape/ftm_alarm.c
> +++ b/drivers/soc/fsl/layerscape/ftm_alarm.c

>There is no such file in the mainline kernel.  So it looks like the patch set 
>is

> based on some internal git repo instead of the upstream Linux kernel.  This 
> kind of patches

> shouldn't be sent to the upstream mailing list for review.

>Regards,

>Leo
This patch will not to upstream.

Regards,

Yinbo.

[PATCH 4/9] arm64: dts: ls208xa: Add the identify of the platform to support to set rcpm bit

[Yinbo Zhu]

From: Zhang Ying-22455 

Add the identify of the platform to support set the rcpm with
big-endian or little-endian.

Signed-off-by: Zhang Ying-22455 
---
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index fec61af..973e646 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -896,9 +896,11 @@
};
 
ftm0: ftm0@280 {
-   compatible = "fsl,ftm-alarm";
-   reg = <0x0 0x280 0x0 0x1>;
+   compatible = "fsl,ls208xa-ftm";
+   reg = <0x0 0x280 0x0 0x1>,
+ <0x0 0x1e34050 0x0 0x4>;
interrupts = <0 44 4>;
+   reg-names = "ftm", "FlexTimer1";
};
};
 
-- 
1.7.1

[PATCH 4/9] arm64: dts: ls208xa: Add the identify of the platform to support to set rcpm bit

[Yinbo Zhu]

From: Zhang Ying-22455 

Add the identify of the platform to support set the rcpm with
big-endian or little-endian.

Signed-off-by: Zhang Ying-22455 
---
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index fec61af..973e646 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -896,9 +896,11 @@
};
 
ftm0: ftm0@280 {
-   compatible = "fsl,ftm-alarm";
-   reg = <0x0 0x280 0x0 0x1>;
+   compatible = "fsl,ls208xa-ftm";
+   reg = <0x0 0x280 0x0 0x1>,
+ <0x0 0x1e34050 0x0 0x4>;
interrupts = <0 44 4>;
+   reg-names = "ftm", "FlexTimer1";
};
};
 
-- 
1.7.1

[PATCH 8/9] arm64: dts: ls1046a: Add the identify of the platform to support to set rcpm bit

[Yinbo Zhu]

From: Zhang Ying-22455 

Add the identify of the platform to support set the rcpm with
big-endian or little-endian.

Signed-off-by: Zhang Ying-22455 
---
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 3e09bcb..1ce1153 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -575,7 +575,7 @@
};
 
ftm0: ftm0@29d {
-   compatible = "fsl,ftm-alarm";
+   compatible = "fsl,ls1046a-ftm";
reg = <0x0 0x29d 0x0 0x1>,
  <0x0 0x1ee2140 0x0 0x4>;
reg-names = "ftm", "FlexTimer1";
-- 
1.7.1

[PATCH 9/9] armv8: add psci 0.2 stardard support

[Yinbo Zhu]

From: Yuantian Tang 

In current kernel, only psci v1.0 is supported. But our psci firmware
only support psci v0.2. So update psci driver to support psci v0.2.

Signed-off-by: Tang Yuantian 
---
 drivers/firmware/psci.c |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index 0bd795f..c9ed9fb 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -468,6 +468,8 @@ static void __init psci_init_system_suspend(void)
if (!IS_ENABLED(CONFIG_SUSPEND))
return;
 
+   suspend_set_ops(_suspend_ops);
+
ret = psci_features(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND));
 
if (ret != PSCI_RET_NOT_SUPPORTED)
@@ -573,6 +575,8 @@ static void __init psci_0_2_set_functions(void)
 
pm_power_off = psci_sys_poweroff;
 
+   psci_init_system_suspend();
+
suspend_set_ops(_suspend_ops);
 }
 
-- 
1.7.1

[PATCH 8/9] arm64: dts: ls1046a: Add the identify of the platform to support to set rcpm bit

[Yinbo Zhu]

From: Zhang Ying-22455 

Add the identify of the platform to support set the rcpm with
big-endian or little-endian.

Signed-off-by: Zhang Ying-22455 
---
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 3e09bcb..1ce1153 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -575,7 +575,7 @@
};
 
ftm0: ftm0@29d {
-   compatible = "fsl,ftm-alarm";
+   compatible = "fsl,ls1046a-ftm";
reg = <0x0 0x29d 0x0 0x1>,
  <0x0 0x1ee2140 0x0 0x4>;
reg-names = "ftm", "FlexTimer1";
-- 
1.7.1

[PATCH 9/9] armv8: add psci 0.2 stardard support

[Yinbo Zhu]

From: Yuantian Tang 

In current kernel, only psci v1.0 is supported. But our psci firmware
only support psci v0.2. So update psci driver to support psci v0.2.

Signed-off-by: Tang Yuantian 
---
 drivers/firmware/psci.c |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index 0bd795f..c9ed9fb 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -468,6 +468,8 @@ static void __init psci_init_system_suspend(void)
if (!IS_ENABLED(CONFIG_SUSPEND))
return;
 
+   suspend_set_ops(_suspend_ops);
+
ret = psci_features(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND));
 
if (ret != PSCI_RET_NOT_SUPPORTED)
@@ -573,6 +575,8 @@ static void __init psci_0_2_set_functions(void)
 
pm_power_off = psci_sys_poweroff;
 
+   psci_init_system_suspend();
+
suspend_set_ops(_suspend_ops);
 }
 
-- 
1.7.1

[PATCH 6/9] soc: fsl: fix the compilation issue

[Yinbo Zhu]

From: Zhang Ying-22455 

Signed-off-by: Zhang Ying-22455 
---
 drivers/soc/fsl/layerscape/ftm_alarm.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/soc/fsl/layerscape/ftm_alarm.c 
b/drivers/soc/fsl/layerscape/ftm_alarm.c
index 811dcfa..c22ef49 100644
--- a/drivers/soc/fsl/layerscape/ftm_alarm.c
+++ b/drivers/soc/fsl/layerscape/ftm_alarm.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define FTM_SC 0x00
 #define FTM_SC_CLK_SHIFT   3
-- 
1.7.1

[PATCH 6/9] soc: fsl: fix the compilation issue

[Yinbo Zhu]

From: Zhang Ying-22455 

Signed-off-by: Zhang Ying-22455 
---
 drivers/soc/fsl/layerscape/ftm_alarm.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/soc/fsl/layerscape/ftm_alarm.c 
b/drivers/soc/fsl/layerscape/ftm_alarm.c
index 811dcfa..c22ef49 100644
--- a/drivers/soc/fsl/layerscape/ftm_alarm.c
+++ b/drivers/soc/fsl/layerscape/ftm_alarm.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define FTM_SC 0x00
 #define FTM_SC_CLK_SHIFT   3
-- 
1.7.1

[PATCH 7/9] arm64: dts: ls1043a: Add the identify of the platform to support to set rcpm bit

[Yinbo Zhu]

From: Zhang Ying-22455 

Add the identify of the platform to support set the rcpm with
big-endian or little-endian.

Signed-off-by: Zhang Ying-22455 
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index ffea97a..754ce0d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -679,7 +679,7 @@
};
 
ftm0: ftm0@29d {
-   compatible = "fsl,ftm-alarm";
+   compatible = "fsl,ls1043a-ftm";
reg = <0x0 0x29d 0x0 0x1>,
  <0x0 0x1ee2140 0x0 0x4>;
reg-names = "ftm", "FlexTimer1";
-- 
1.7.1

[PATCH 7/9] arm64: dts: ls1043a: Add the identify of the platform to support to set rcpm bit

[Yinbo Zhu]

From: Zhang Ying-22455 

Add the identify of the platform to support set the rcpm with
big-endian or little-endian.

Signed-off-by: Zhang Ying-22455 
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index ffea97a..754ce0d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -679,7 +679,7 @@
};
 
ftm0: ftm0@29d {
-   compatible = "fsl,ftm-alarm";
+   compatible = "fsl,ls1043a-ftm";
reg = <0x0 0x29d 0x0 0x1>,
  <0x0 0x1ee2140 0x0 0x4>;
reg-names = "ftm", "FlexTimer1";
-- 
1.7.1

[PATCH 5/9] drivers: firmware: psci: use psci v0.2 to implement sleep

[Yinbo Zhu]

From: Yuantian Tang <andy.t...@nxp.com>

Technically psci v0.2 can not support system sleep. Unfortunately
our PPA only supports psci v0.2. So workaround this by changing
psci v1.0 to v0.2 call to implement system sleep.

Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo@nxp.com>
---
 drivers/firmware/psci.c |   16 ++--
 1 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index c80ec1d..0bd795f 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -437,8 +437,18 @@ int psci_cpu_suspend_enter(unsigned long index)
 
 static int psci_system_suspend(unsigned long unused)
 {
-   return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
- __pa_symbol(cpu_resume), 0, 0);
+   u32 state;
+   u32 ver = psci_get_version();
+
+   if (PSCI_VERSION_MAJOR(ver) >= 1) {
+   return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
+   virt_to_phys(cpu_resume), 0, 0);
+   } else {
+   state = (2 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
+   (1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT);
+
+   return psci_cpu_suspend(state, virt_to_phys(cpu_resume));
+   }
 }
 
 static int psci_system_suspend_enter(suspend_state_t state)
@@ -562,6 +572,8 @@ static void __init psci_0_2_set_functions(void)
arm_pm_restart = psci_sys_reset;
 
pm_power_off = psci_sys_poweroff;
+
+   suspend_set_ops(_suspend_ops);
 }
 
 /*
-- 
1.7.1

[PATCH 5/9] drivers: firmware: psci: use psci v0.2 to implement sleep

[Yinbo Zhu]

From: Yuantian Tang 

Technically psci v0.2 can not support system sleep. Unfortunately
our PPA only supports psci v0.2. So workaround this by changing
psci v1.0 to v0.2 call to implement system sleep.

Signed-off-by: Tang Yuantian 
Signed-off-by: Yinbo Zhu 
---
 drivers/firmware/psci.c |   16 ++--
 1 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index c80ec1d..0bd795f 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -437,8 +437,18 @@ int psci_cpu_suspend_enter(unsigned long index)
 
 static int psci_system_suspend(unsigned long unused)
 {
-   return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
- __pa_symbol(cpu_resume), 0, 0);
+   u32 state;
+   u32 ver = psci_get_version();
+
+   if (PSCI_VERSION_MAJOR(ver) >= 1) {
+   return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
+   virt_to_phys(cpu_resume), 0, 0);
+   } else {
+   state = (2 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
+   (1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT);
+
+   return psci_cpu_suspend(state, virt_to_phys(cpu_resume));
+   }
 }
 
 static int psci_system_suspend_enter(suspend_state_t state)
@@ -562,6 +572,8 @@ static void __init psci_0_2_set_functions(void)
arm_pm_restart = psci_sys_reset;
 
pm_power_off = psci_sys_poweroff;
+
+   suspend_set_ops(_suspend_ops);
 }
 
 /*
-- 
1.7.1

[PATCH 2/9] armv8: pm: Fix issue of rcpm driver wrongly program other IP control bits

[Yinbo Zhu]

From: Ran Wang <ran.wan...@nxp.com>

When rcpm driver get target register data from DTS property 'fsl,
rcpm-wakeup' (second value), it directly write that data to register
RCPM_IPPDEXPCRx rather than 'OR' the value read from it before. This
operation will over-write those non-related IP control bit which
might have been programmed, should be prevented.

Signed-off-by: Ran Wang <ran.wan...@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo@nxp.com>
---
 drivers/soc/fsl/rcpm.c |   10 +++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c
index ff0477b..39eabfb 100644
--- a/drivers/soc/fsl/rcpm.c
+++ b/drivers/soc/fsl/rcpm.c
@@ -75,6 +75,7 @@ static void rcpm_wakeup_fixup(struct device *dev, void *data)
 static int rcpm_suspend_prepare(void)
 {
int i;
+   u32 val;
 
WARN_ON(!rcpm);
 
@@ -84,9 +85,12 @@ static int rcpm_suspend_prepare(void)
dpm_for_each_dev(NULL, rcpm_wakeup_fixup);
 
for (i = 0; i < rcpm->ipp_num; i++) {
-   rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
-  rcpm->ippdexpcr[i]);
-   pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
+   if (rcpm->ippdexpcr[i]) {
+   val = rcpm_reg_read(rcpm->ippdexpcr_offset + 4 * i);
+   rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
+  val | rcpm->ippdexpcr[i]);
+   pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
+   }
}
 
return 0;
-- 
1.7.1

[PATCH 3/9] soc: fsl: set rcpm bit for FTM

[Yinbo Zhu]

From: Zhang Ying-22455 <ying.zhang22...@nxp.com>

Set RCPM for FTM when using FTM as wakeup source. Because the RCPM
module of each platform has different big-end and little-end mode,
there need to set RCPM depending on the platform.

Signed-off-by: Zhang Ying-22455 <ying.zhang22...@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo@nxp.com>
---
 .../devicetree/bindings/timer/fsl,ftm-timer.txt|7 ++
 drivers/soc/fsl/layerscape/ftm_alarm.c |   92 ++-
 2 files changed, 94 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt 
b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
index aa8c402..15ead58 100644
--- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
+++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
@@ -3,6 +3,13 @@ Freescale FlexTimer Module (FTM) Timer
 Required properties:
 
 - compatible : should be "fsl,ftm-timer"
+ Possible compatibles for ARM:
+ "fsl,ls1012a-ftm"
+ "fsl,ls1021a-ftm"
+ "fsl,ls1043a-ftm"
+ "fsl,ls1046a-ftm"
+ "fsl,ls1088a-ftm"
+ "fsl,ls208xa-ftm"
 - reg : Specifies base physical address and size of the register sets for the
   clock event device and clock source device.
 - interrupts : Should be the clock event device interrupt.
diff --git a/drivers/soc/fsl/layerscape/ftm_alarm.c 
b/drivers/soc/fsl/layerscape/ftm_alarm.c
index 6f9882f..811dcfa 100644
--- a/drivers/soc/fsl/layerscape/ftm_alarm.c
+++ b/drivers/soc/fsl/layerscape/ftm_alarm.c
@@ -16,6 +16,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 #define FTM_SC 0x00
 #define FTM_SC_CLK_SHIFT   3
@@ -40,6 +43,59 @@
 static u32 alarm_freq;
 static bool big_endian;
 
+enum pmu_endian_type {
+   BIG_ENDIAN,
+   LITTLE_ENDIAN,
+};
+
+struct rcpm_cfg {
+   enum pmu_endian_type big_endian; /* Big/Little endian of PMU module */
+
+   /* FlexTimer1 is not powerdown during device LPM20 */
+   u32 flextimer_set_bit;
+};
+
+static struct rcpm_cfg ls1012a_rcpm_cfg = {
+   .big_endian = BIG_ENDIAN,
+   .flextimer_set_bit = 0x2,
+};
+
+static struct rcpm_cfg ls1021a_rcpm_cfg = {
+   .big_endian = BIG_ENDIAN,
+   .flextimer_set_bit = 0x2,
+};
+
+static struct rcpm_cfg ls1043a_rcpm_cfg = {
+   .big_endian = BIG_ENDIAN,
+   .flextimer_set_bit = 0x2,
+};
+
+static struct rcpm_cfg ls1046a_rcpm_cfg = {
+   .big_endian = BIG_ENDIAN,
+   .flextimer_set_bit = 0x2,
+};
+
+static struct rcpm_cfg ls1088a_rcpm_cfg = {
+   .big_endian = LITTLE_ENDIAN,
+   .flextimer_set_bit = 0x4000,
+};
+
+static struct rcpm_cfg ls208xa_rcpm_cfg = {
+   .big_endian = LITTLE_ENDIAN,
+   .flextimer_set_bit = 0x4000,
+};
+
+static const struct of_device_id ippdexpcr_of_match[] = {
+   { .compatible = "fsl,ls1012a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls1021a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls1043a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls1046a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls1088a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls208xa-ftm", .data = _rcpm_cfg},
+   {},
+};
+MODULE_DEVICE_TABLE(of, ippdexpcr_of_match);
+
 static inline u32 ftm_readl(void __iomem *addr)
 {
if (big_endian)
@@ -214,7 +270,10 @@ static int ftm_alarm_probe(struct platform_device *pdev)
struct resource *r;
int irq;
int ret;
-   u32 ippdexpcr;
+   struct rcpm_cfg *rcpm_cfg;
+   u32 ippdexpcr, flextimer;
+   const struct of_device_id *of_id;
+   enum pmu_endian_type endian;
 
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r)
@@ -224,14 +283,32 @@ static int ftm_alarm_probe(struct platform_device *pdev)
if (IS_ERR(ftm1_base))
return PTR_ERR(ftm1_base);
 
+   of_id = of_match_node(ippdexpcr_of_match, np);
+   if (!of_id)
+   return -ENODEV;
+
+   rcpm_cfg = devm_kzalloc(>dev, sizeof(*rcpm_cfg), GFP_KERNEL);
+   if (!rcpm_cfg)
+   return -ENOMEM;
+
+   rcpm_cfg = (struct rcpm_cfg *)of_id->data;
+   endian = rcpm_cfg->big_endian;
+   flextimer = rcpm_cfg->flextimer_set_bit;
+
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "FlexTimer1");
if (r) {
rcpm_ftm_addr = devm_ioremap_resource(>dev, r);
if (IS_ERR(rcpm_ftm_addr))
return PTR_ERR(rcpm_ftm_addr);
-   ippdexpcr = ioread32be(rcpm_ftm_addr);
-   ippdexpcr |= 0x2;
-   iowrite32be(ippdexpcr, rcpm_ftm_addr);
+   if (endian == BIG_ENDIAN)
+   ippdexpcr = ioread32be(rcpm_ftm_addr);
+   else
+   ippdex

[PATCH 2/9] armv8: pm: Fix issue of rcpm driver wrongly program other IP control bits

[Yinbo Zhu]

From: Ran Wang 

When rcpm driver get target register data from DTS property 'fsl,
rcpm-wakeup' (second value), it directly write that data to register
RCPM_IPPDEXPCRx rather than 'OR' the value read from it before. This
operation will over-write those non-related IP control bit which
might have been programmed, should be prevented.

Signed-off-by: Ran Wang 
Signed-off-by: Yinbo Zhu 
---
 drivers/soc/fsl/rcpm.c |   10 +++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c
index ff0477b..39eabfb 100644
--- a/drivers/soc/fsl/rcpm.c
+++ b/drivers/soc/fsl/rcpm.c
@@ -75,6 +75,7 @@ static void rcpm_wakeup_fixup(struct device *dev, void *data)
 static int rcpm_suspend_prepare(void)
 {
int i;
+   u32 val;
 
WARN_ON(!rcpm);
 
@@ -84,9 +85,12 @@ static int rcpm_suspend_prepare(void)
dpm_for_each_dev(NULL, rcpm_wakeup_fixup);
 
for (i = 0; i < rcpm->ipp_num; i++) {
-   rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
-  rcpm->ippdexpcr[i]);
-   pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
+   if (rcpm->ippdexpcr[i]) {
+   val = rcpm_reg_read(rcpm->ippdexpcr_offset + 4 * i);
+   rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
+  val | rcpm->ippdexpcr[i]);
+   pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
+   }
}
 
return 0;
-- 
1.7.1

[PATCH 3/9] soc: fsl: set rcpm bit for FTM

[Yinbo Zhu]

From: Zhang Ying-22455 

Set RCPM for FTM when using FTM as wakeup source. Because the RCPM
module of each platform has different big-end and little-end mode,
there need to set RCPM depending on the platform.

Signed-off-by: Zhang Ying-22455 
Signed-off-by: Yinbo Zhu 
---
 .../devicetree/bindings/timer/fsl,ftm-timer.txt|7 ++
 drivers/soc/fsl/layerscape/ftm_alarm.c |   92 ++-
 2 files changed, 94 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt 
b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
index aa8c402..15ead58 100644
--- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
+++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
@@ -3,6 +3,13 @@ Freescale FlexTimer Module (FTM) Timer
 Required properties:
 
 - compatible : should be "fsl,ftm-timer"
+ Possible compatibles for ARM:
+ "fsl,ls1012a-ftm"
+ "fsl,ls1021a-ftm"
+ "fsl,ls1043a-ftm"
+ "fsl,ls1046a-ftm"
+ "fsl,ls1088a-ftm"
+ "fsl,ls208xa-ftm"
 - reg : Specifies base physical address and size of the register sets for the
   clock event device and clock source device.
 - interrupts : Should be the clock event device interrupt.
diff --git a/drivers/soc/fsl/layerscape/ftm_alarm.c 
b/drivers/soc/fsl/layerscape/ftm_alarm.c
index 6f9882f..811dcfa 100644
--- a/drivers/soc/fsl/layerscape/ftm_alarm.c
+++ b/drivers/soc/fsl/layerscape/ftm_alarm.c
@@ -16,6 +16,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 #define FTM_SC 0x00
 #define FTM_SC_CLK_SHIFT   3
@@ -40,6 +43,59 @@
 static u32 alarm_freq;
 static bool big_endian;
 
+enum pmu_endian_type {
+   BIG_ENDIAN,
+   LITTLE_ENDIAN,
+};
+
+struct rcpm_cfg {
+   enum pmu_endian_type big_endian; /* Big/Little endian of PMU module */
+
+   /* FlexTimer1 is not powerdown during device LPM20 */
+   u32 flextimer_set_bit;
+};
+
+static struct rcpm_cfg ls1012a_rcpm_cfg = {
+   .big_endian = BIG_ENDIAN,
+   .flextimer_set_bit = 0x2,
+};
+
+static struct rcpm_cfg ls1021a_rcpm_cfg = {
+   .big_endian = BIG_ENDIAN,
+   .flextimer_set_bit = 0x2,
+};
+
+static struct rcpm_cfg ls1043a_rcpm_cfg = {
+   .big_endian = BIG_ENDIAN,
+   .flextimer_set_bit = 0x2,
+};
+
+static struct rcpm_cfg ls1046a_rcpm_cfg = {
+   .big_endian = BIG_ENDIAN,
+   .flextimer_set_bit = 0x2,
+};
+
+static struct rcpm_cfg ls1088a_rcpm_cfg = {
+   .big_endian = LITTLE_ENDIAN,
+   .flextimer_set_bit = 0x4000,
+};
+
+static struct rcpm_cfg ls208xa_rcpm_cfg = {
+   .big_endian = LITTLE_ENDIAN,
+   .flextimer_set_bit = 0x4000,
+};
+
+static const struct of_device_id ippdexpcr_of_match[] = {
+   { .compatible = "fsl,ls1012a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls1021a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls1043a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls1046a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls1088a-ftm", .data = _rcpm_cfg},
+   { .compatible = "fsl,ls208xa-ftm", .data = _rcpm_cfg},
+   {},
+};
+MODULE_DEVICE_TABLE(of, ippdexpcr_of_match);
+
 static inline u32 ftm_readl(void __iomem *addr)
 {
if (big_endian)
@@ -214,7 +270,10 @@ static int ftm_alarm_probe(struct platform_device *pdev)
struct resource *r;
int irq;
int ret;
-   u32 ippdexpcr;
+   struct rcpm_cfg *rcpm_cfg;
+   u32 ippdexpcr, flextimer;
+   const struct of_device_id *of_id;
+   enum pmu_endian_type endian;
 
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r)
@@ -224,14 +283,32 @@ static int ftm_alarm_probe(struct platform_device *pdev)
if (IS_ERR(ftm1_base))
return PTR_ERR(ftm1_base);
 
+   of_id = of_match_node(ippdexpcr_of_match, np);
+   if (!of_id)
+   return -ENODEV;
+
+   rcpm_cfg = devm_kzalloc(>dev, sizeof(*rcpm_cfg), GFP_KERNEL);
+   if (!rcpm_cfg)
+   return -ENOMEM;
+
+   rcpm_cfg = (struct rcpm_cfg *)of_id->data;
+   endian = rcpm_cfg->big_endian;
+   flextimer = rcpm_cfg->flextimer_set_bit;
+
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "FlexTimer1");
if (r) {
rcpm_ftm_addr = devm_ioremap_resource(>dev, r);
if (IS_ERR(rcpm_ftm_addr))
return PTR_ERR(rcpm_ftm_addr);
-   ippdexpcr = ioread32be(rcpm_ftm_addr);
-   ippdexpcr |= 0x2;
-   iowrite32be(ippdexpcr, rcpm_ftm_addr);
+   if (endian == BIG_ENDIAN)
+   ippdexpcr = ioread32be(rcpm_ftm_addr);
+   else
+   ippdexpcr = ioread32(rcpm_ftm_addr);
+   ippdexpcr |= flextimer;
+ 

[PATCH 1/9] armv8: pm: add rcpm module support

[Yinbo Zhu]

From: Yuantian Tang <andy.t...@nxp.com>

The Run Control and Power Management (RCPM) module communicates
with embedded cores, coherency modules, and other device platform
module to provide run control and power management functionality

Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo@nxp.com>
---
 drivers/soc/fsl/Makefile |1 +
 drivers/soc/fsl/rcpm.c   |  153 ++
 2 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 drivers/soc/fsl/rcpm.c

diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
index 629dab8..68fcd71 100644
--- a/drivers/soc/fsl/Makefile
+++ b/drivers/soc/fsl/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_FSL_DPAA) += qbman/
 obj-$(CONFIG_QUICC_ENGINE) += qe/
 obj-$(CONFIG_CPM)  += qe/
+obj-$(CONFIG_SUSPEND)  += rcpm.o
 obj-$(CONFIG_FSL_GUTS) += guts.o
 obj-$(CONFIG_FSL_LS2_CONSOLE)  += ls2-console/
 obj-$(CONFIG_LS_SOC_DRIVERS)   += layerscape/
diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c
new file mode 100644
index 000..ff0477b
--- /dev/null
+++ b/drivers/soc/fsl/rcpm.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2016 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#define pr_fmt(fmt) "RCPM: %s: " fmt, __func__
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* RCPM register offset */
+#define RCPM_IPPDEXPCR00x140
+
+#define RCPM_WAKEUP_CELL_SIZE  2
+
+struct rcpm_config {
+   int ipp_num;
+   int ippdexpcr_offset;
+   u32 ippdexpcr[2];
+   void *rcpm_reg_base;
+};
+
+static struct rcpm_config *rcpm;
+
+static inline void rcpm_reg_write(u32 offset, u32 value)
+{
+   iowrite32be(value, rcpm->rcpm_reg_base + offset);
+}
+
+static inline u32 rcpm_reg_read(u32 offset)
+{
+   return ioread32be(rcpm->rcpm_reg_base + offset);
+}
+
+static void rcpm_wakeup_fixup(struct device *dev, void *data)
+{
+   struct device_node *node = dev ? dev->of_node : NULL;
+   u32 value[RCPM_WAKEUP_CELL_SIZE];
+   int ret, i;
+
+   if (!dev || !node || !device_may_wakeup(dev))
+   return;
+
+   /*
+* Get the values in the "rcpm-wakeup" property.
+* Three values are:
+* The first is a pointer to the RCPM node.
+* The second is the value of the ippdexpcr0 register.
+* The third is the value of the ippdexpcr1 register.
+*/
+   ret = of_property_read_u32_array(node, "fsl,rcpm-wakeup",
+value, RCPM_WAKEUP_CELL_SIZE);
+   if (ret)
+   return;
+
+   pr_debug("wakeup source: the device %s\n", node->full_name);
+
+   for (i = 0; i < rcpm->ipp_num; i++)
+   rcpm->ippdexpcr[i] |= value[i + 1];
+}
+
+static int rcpm_suspend_prepare(void)
+{
+   int i;
+
+   WARN_ON(!rcpm);
+
+   for (i = 0; i < rcpm->ipp_num; i++)
+   rcpm->ippdexpcr[i] = 0;
+
+   dpm_for_each_dev(NULL, rcpm_wakeup_fixup);
+
+   for (i = 0; i < rcpm->ipp_num; i++) {
+   rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
+  rcpm->ippdexpcr[i]);
+   pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
+   }
+
+   return 0;
+}
+
+static int rcpm_suspend_notifier_call(struct notifier_block *bl,
+ unsigned long state,
+ void *unused)
+{
+   switch (state) {
+   case PM_SUSPEND_PREPARE:
+   rcpm_suspend_prepare();
+   break;
+   }
+
+   return NOTIFY_DONE;
+}
+
+static struct rcpm_config rcpm_default_config = {
+   .ipp_num = 1,
+   .ippdexpcr_offset = RCPM_IPPDEXPCR0,
+};
+
+static const struct of_device_id rcpm_matches[] = {
+   {
+   .compatible = "fsl,qoriq-rcpm-2.1",
+   .data = _default_config,
+   },
+   {}
+};
+
+static struct notifier_block rcpm_suspend_notifier = {
+   .notifier_call = rcpm_suspend_notifier_call,
+};
+
+static int __init layerscape_rcpm_init(void)
+{
+   const struct of_device_id *match;
+   struct device_node *np;
+
+   np = of_find_matching_node_and_match(NULL, rcpm_matches, );
+   if (!np) {
+   pr_err("Ca

[PATCH 1/9] armv8: pm: add rcpm module support

[Yinbo Zhu]

From: Yuantian Tang 

The Run Control and Power Management (RCPM) module communicates
with embedded cores, coherency modules, and other device platform
module to provide run control and power management functionality

Signed-off-by: Tang Yuantian 
Signed-off-by: Yinbo Zhu 
---
 drivers/soc/fsl/Makefile |1 +
 drivers/soc/fsl/rcpm.c   |  153 ++
 2 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 drivers/soc/fsl/rcpm.c

diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
index 629dab8..68fcd71 100644
--- a/drivers/soc/fsl/Makefile
+++ b/drivers/soc/fsl/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_FSL_DPAA) += qbman/
 obj-$(CONFIG_QUICC_ENGINE) += qe/
 obj-$(CONFIG_CPM)  += qe/
+obj-$(CONFIG_SUSPEND)  += rcpm.o
 obj-$(CONFIG_FSL_GUTS) += guts.o
 obj-$(CONFIG_FSL_LS2_CONSOLE)  += ls2-console/
 obj-$(CONFIG_LS_SOC_DRIVERS)   += layerscape/
diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c
new file mode 100644
index 000..ff0477b
--- /dev/null
+++ b/drivers/soc/fsl/rcpm.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2016 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#define pr_fmt(fmt) "RCPM: %s: " fmt, __func__
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* RCPM register offset */
+#define RCPM_IPPDEXPCR00x140
+
+#define RCPM_WAKEUP_CELL_SIZE  2
+
+struct rcpm_config {
+   int ipp_num;
+   int ippdexpcr_offset;
+   u32 ippdexpcr[2];
+   void *rcpm_reg_base;
+};
+
+static struct rcpm_config *rcpm;
+
+static inline void rcpm_reg_write(u32 offset, u32 value)
+{
+   iowrite32be(value, rcpm->rcpm_reg_base + offset);
+}
+
+static inline u32 rcpm_reg_read(u32 offset)
+{
+   return ioread32be(rcpm->rcpm_reg_base + offset);
+}
+
+static void rcpm_wakeup_fixup(struct device *dev, void *data)
+{
+   struct device_node *node = dev ? dev->of_node : NULL;
+   u32 value[RCPM_WAKEUP_CELL_SIZE];
+   int ret, i;
+
+   if (!dev || !node || !device_may_wakeup(dev))
+   return;
+
+   /*
+* Get the values in the "rcpm-wakeup" property.
+* Three values are:
+* The first is a pointer to the RCPM node.
+* The second is the value of the ippdexpcr0 register.
+* The third is the value of the ippdexpcr1 register.
+*/
+   ret = of_property_read_u32_array(node, "fsl,rcpm-wakeup",
+value, RCPM_WAKEUP_CELL_SIZE);
+   if (ret)
+   return;
+
+   pr_debug("wakeup source: the device %s\n", node->full_name);
+
+   for (i = 0; i < rcpm->ipp_num; i++)
+   rcpm->ippdexpcr[i] |= value[i + 1];
+}
+
+static int rcpm_suspend_prepare(void)
+{
+   int i;
+
+   WARN_ON(!rcpm);
+
+   for (i = 0; i < rcpm->ipp_num; i++)
+   rcpm->ippdexpcr[i] = 0;
+
+   dpm_for_each_dev(NULL, rcpm_wakeup_fixup);
+
+   for (i = 0; i < rcpm->ipp_num; i++) {
+   rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
+  rcpm->ippdexpcr[i]);
+   pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
+   }
+
+   return 0;
+}
+
+static int rcpm_suspend_notifier_call(struct notifier_block *bl,
+ unsigned long state,
+ void *unused)
+{
+   switch (state) {
+   case PM_SUSPEND_PREPARE:
+   rcpm_suspend_prepare();
+   break;
+   }
+
+   return NOTIFY_DONE;
+}
+
+static struct rcpm_config rcpm_default_config = {
+   .ipp_num = 1,
+   .ippdexpcr_offset = RCPM_IPPDEXPCR0,
+};
+
+static const struct of_device_id rcpm_matches[] = {
+   {
+   .compatible = "fsl,qoriq-rcpm-2.1",
+   .data = _default_config,
+   },
+   {}
+};
+
+static struct notifier_block rcpm_suspend_notifier = {
+   .notifier_call = rcpm_suspend_notifier_call,
+};
+
+static int __init layerscape_rcpm_init(void)
+{
+   const struct of_device_id *match;
+   struct device_node *np;
+
+   np = of_find_matching_node_and_match(NULL, rcpm_matches, );
+   if (!np) {
+   pr_err("Can't find the RCPM node.\n");
+   return -

RE: [PATCH v2] arm64: dts: ls1088a: Add USB support

[Yinbo Zhu]

-Original Message-
From: Shawn Guo [mailto:shawn...@kernel.org] 
Sent: Wednesday, December 20, 2017 10:53 AM
To: Yinbo Zhu <yinbo@nxp.com>
Cc: Rob Herring <robh...@kernel.org>; Mark Rutland <mark.rutl...@arm.com>; 
Catalin Marinas ) <catalin.mari...@arm.com>; Will Deacon ) 
<will.dea...@arm.com>; Harninder Rai <harninder@nxp.com>; Raghav Dogra 
<raghav.do...@nxp.com>; Ashish Kumar <ashish.ku...@nxp.com>; Andy Tang 
<andy.t...@nxp.com>; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS 
<devicet...@vger.kernel.org>; linux-arm-ker...@lists.infradead.org; open list 
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] arm64: dts: ls1088a: Add USB support

On Thu, Dec 07, 2017 at 07:33:28AM +, Yinbo Zhu wrote:
> Hi shawn guo,
> 
> If my patch has no other issue,
> Can you help me push it to upstream.

>Are you talking about v4 patch?  First of all, I cannot find v4 in my mailbox. 
> That said, it seems you did not send 

>the patch to me.
>Secondly, by checking the patch on patchwork, the usb nodes in 
>fsl-ls1088a-rdb.dts do not sorted alphabetically 

>in label name.

>Shawn

Hi shawn, 
 I will change the code as follows, right?

 {
status = "okay";
 };
...
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
https://patchwork.kernel.org/patch/10059097/

Thanks
Yinbo.

RE: [PATCH v2] arm64: dts: ls1088a: Add USB support

[Yinbo Zhu]

-Original Message-
From: Shawn Guo [mailto:shawn...@kernel.org] 
Sent: Wednesday, December 20, 2017 10:53 AM
To: Yinbo Zhu 
Cc: Rob Herring ; Mark Rutland ; 
Catalin Marinas ) ; Will Deacon ) 
; Harninder Rai ; Raghav Dogra 
; Ashish Kumar ; Andy Tang 
; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS 
; linux-arm-ker...@lists.infradead.org; open list 

Subject: Re: [PATCH v2] arm64: dts: ls1088a: Add USB support

On Thu, Dec 07, 2017 at 07:33:28AM +, Yinbo Zhu wrote:
> Hi shawn guo,
> 
> If my patch has no other issue,
> Can you help me push it to upstream.

>Are you talking about v4 patch?  First of all, I cannot find v4 in my mailbox. 
> That said, it seems you did not send 

>the patch to me.
>Secondly, by checking the patch on patchwork, the usb nodes in 
>fsl-ls1088a-rdb.dts do not sorted alphabetically 

>in label name.

>Shawn

Hi shawn, 
 I will change the code as follows, right?

 {
status = "okay";
 };
...
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
https://patchwork.kernel.org/patch/10059097/

Thanks
Yinbo.