Re: [PATCH v2 01/11] KVM: x86: Add helper functions for illegal GPA checking and page fault injection

[Yuan Yao]

On Fri, Jun 19, 2020 at 05:39:15PM +0200, Mohammed Gamal wrote:
> This patch adds two helper functions that will be used to support virtualizing
> MAXPHYADDR in both kvm-intel.ko and kvm.ko.
> 
> kvm_fixup_and_inject_pf_error() injects a page fault for a user-specified GVA,
> while kvm_mmu_is_illegal_gpa() checks whether a GPA exceeds vCPU address 
> limits.
> 
> Signed-off-by: Mohammed Gamal 
> Signed-off-by: Paolo Bonzini 
> ---
>  arch/x86/kvm/mmu.h |  6 ++
>  arch/x86/kvm/x86.c | 21 +
>  arch/x86/kvm/x86.h |  1 +
>  3 files changed, 28 insertions(+)
> 
> diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
> index 0ad06bfe2c2c..555237dfb91c 100644
> --- a/arch/x86/kvm/mmu.h
> +++ b/arch/x86/kvm/mmu.h
> @@ -4,6 +4,7 @@
>  
>  #include 
>  #include "kvm_cache_regs.h"
> +#include "cpuid.h"
>  
>  #define PT64_PT_BITS 9
>  #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
> @@ -158,6 +159,11 @@ static inline bool is_write_protection(struct kvm_vcpu 
> *vcpu)
>   return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
>  }
>  
> +static inline bool kvm_mmu_is_illegal_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
> +{
> +return (gpa >= BIT_ULL(cpuid_maxphyaddr(vcpu)));
> +}
> +
>  /*
>   * Check if a given access (described through the I/D, W/R and U/S bits of a
>   * page fault error code pfec) causes a permission fault with the given PTE
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 00c88c2f34e4..ac8642e890b1 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -10693,6 +10693,27 @@ u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
>  }
>  EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
>  
> +void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 
> error_code)
> +{
> + struct x86_exception fault;
> +
> + if (!(error_code & PFERR_PRESENT_MASK) ||
> + vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, error_code, ) != 
> UNMAPPED_GVA) {
> + /*
> +  * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
> +  * tables probably do not match the TLB.  Just proceed
> +  * with the error code that the processor gave.
> +  */
> + fault.vector = PF_VECTOR;
> + fault.error_code_valid = true;
> + fault.error_code = error_code;
> + fault.nested_page_fault = false;
> + fault.address = gva;
> + }
> + vcpu->arch.walk_mmu->inject_page_fault(vcpu, );

Should this "vcpu->arch.walk_mmu->inject_page_fault(vcpu, )" inside the 
last brace?
Otherwise an uninitialized fault variable will be passed to the 
walk_mmu->inject_page_fault.

> +}
> +EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
> +
>  EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
>  EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
>  EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
> diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
> index 6eb62e97e59f..239ae0f3e40b 100644
> --- a/arch/x86/kvm/x86.h
> +++ b/arch/x86/kvm/x86.h
> @@ -272,6 +272,7 @@ int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 
> *pdata);
>  bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
> int page_num);
>  bool kvm_vector_hashing_enabled(void);
> +void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 
> error_code);
>  int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
>   int emulation_type, void *insn, int insn_len);
>  fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
> -- 
> 2.26.2
> 

Re: [PATCH v2 00/11] KVM: Support guest MAXPHYADDR < host MAXPHYADDR

[Yuan Yao]

  On Fri, Jun 19, 2020 at 05:39:14PM +0200, Mohammed Gamal wrote:
> When EPT/NPT is enabled, KVM does not really look at guest physical
> address size. Address bits above maximum physical memory size are reserved.
> Because KVM does not look at these guest physical addresses, it currently
> effectively supports guest physical address sizes equal to the host.
> 
> This can be problem when having a mixed setup of machines with 5-level page
> tables and machines with 4-level page tables, as live migration can change
> MAXPHYADDR while the guest runs, which can theoretically introduce bugs.
> 
> In this patch series we add checks on guest physical addresses in EPT
> violation/misconfig and NPF vmexits and if needed inject the proper
> page faults in the guest.
> 
> A more subtle issue is when the host MAXPHYADDR is larger than that of the
> guest. Page faults caused by reserved bits on the guest won't cause an EPT
> violation/NPF and hence we also check guest MAXPHYADDR and add PFERR_RSVD_MASK
> error code to the page fault if needed.
> 
> The last 3 patches (i.e. SVM bits and patch 11) are not intended for
> immediate inclusion and probably need more discussion.
> We've been noticing some unexpected behavior in handling NPF vmexits
> on AMD CPUs (see individual patches for details), and thus we are
> proposing a workaround (see last patch) that adds a capability that
> userspace can use to decide who to deal with hosts that might have
> issues supprting guest MAXPHYADDR < host MAXPHYADDR.
> 
> 
> Mohammed Gamal (7):
>   KVM: x86: Add helper functions for illegal GPA checking and page fault
> injection
>   KVM: x86: mmu: Move translate_gpa() to mmu.c
>   KVM: x86: mmu: Add guest physical address check in translate_gpa()
>   KVM: VMX: Add guest physical address check in EPT violation and
> misconfig
>   KVM: SVM: introduce svm_need_pf_intercept
>   KVM: SVM: Add guest physical address check in NPF/PF interception
>   KVM: x86: SVM: VMX: Make GUEST_MAXPHYADDR < HOST_MAXPHYADDR support
> configurable
> 
> Paolo Bonzini (4):
>   KVM: x86: rename update_bp_intercept to update_exception_bitmap
>   KVM: x86: update exception bitmap on CPUID changes
>   KVM: VMX: introduce vmx_need_pf_intercept
>   KVM: VMX: optimize #PF injection when MAXPHYADDR does not match
> 
>  arch/x86/include/asm/kvm_host.h | 10 ++--
>  arch/x86/kvm/cpuid.c|  2 ++
>  arch/x86/kvm/mmu.h  |  6 +
>  arch/x86/kvm/mmu/mmu.c  | 12 +
>  arch/x86/kvm/svm/svm.c  | 41 +++---
>  arch/x86/kvm/svm/svm.h  |  6 +
>  arch/x86/kvm/vmx/nested.c   | 28 
>  arch/x86/kvm/vmx/vmx.c  | 45 +
>  arch/x86/kvm/vmx/vmx.h  |  6 +
>  arch/x86/kvm/x86.c  | 29 -
>  arch/x86/kvm/x86.h  |  1 +
>  include/uapi/linux/kvm.h|  1 +
>  12 files changed, 158 insertions(+), 29 deletions(-)
> 
> -- 
> 2.26.2
> 

Re: [PATCH] kernel, resource: use resource_overlaps() to simplify region_intersects()

[Yuan Yao]

Looks good to me.

Reviewed-by: Yuan Yao 


On Mon, Jan 21, 2019 at 09:20:28AM +0800, Wei Yang wrote:
> The three checks in region_intersects() is to see whether two resources
> overlap. This means it could be simplified with one resource_overlaps().
> 
> Also fix two typo in related function.
> 
> Signed-off-by: Wei Yang 
> ---
>  kernel/iomem.c|  4 ++--
>  kernel/resource.c | 11 +--
>  2 files changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/kernel/iomem.c b/kernel/iomem.c
> index f7525e14ebc6..93c26510 100644
> --- a/kernel/iomem.c
> +++ b/kernel/iomem.c
> @@ -55,7 +55,7 @@ static void *try_ram_remap(resource_size_t offset, size_t 
> size,
>   *
>   * MEMREMAP_WB - matches the default mapping for System RAM on
>   * the architecture.  This is usually a read-allocate write-back cache.
> - * Morever, if MEMREMAP_WB is specified and the requested remap region is RAM
> + * Moreover, if MEMREMAP_WB is specified and the requested remap region is 
> RAM
>   * memremap() will bypass establishing a new mapping and instead return
>   * a pointer into the direct map.
>   *
> @@ -86,7 +86,7 @@ void *memremap(resource_size_t offset, size_t size, 
> unsigned long flags)
>   /* Try all mapping types requested until one returns non-NULL */
>   if (flags & MEMREMAP_WB) {
>   /*
> -  * MEMREMAP_WB is special in that it can be satisifed
> +  * MEMREMAP_WB is special in that it can be satisfied
>* from the direct map.  Some archs depend on the
>* capability of memremap() to autodetect cases where
>* the requested range is potentially in System RAM.
> diff --git a/kernel/resource.c b/kernel/resource.c
> index b0fbf685c77a..34dfb94305bb 100644
> --- a/kernel/resource.c
> +++ b/kernel/resource.c
> @@ -521,21 +521,20 @@ EXPORT_SYMBOL_GPL(page_is_ram);
>  int region_intersects(resource_size_t start, size_t size, unsigned long 
> flags,
> unsigned long desc)
>  {
> - resource_size_t end = start + size - 1;
> + struct resource res;
>   int type = 0; int other = 0;
>   struct resource *p;
>  
> + res.start = start;
> + res.end = start + size - 1;
> +
>   read_lock(_lock);
>   for (p = iomem_resource.child; p ; p = p->sibling) {
>   bool is_type = (((p->flags & flags) == flags) &&
>   ((desc == IORES_DESC_NONE) ||
>(desc == p->desc)));
>  
> - if (start >= p->start && start <= p->end)
> - is_type ? type++ : other++;
> - if (end >= p->start && end <= p->end)
> - is_type ? type++ : other++;
> - if (p->start >= start && p->end <= end)
> + if (resource_overlaps(p, ))
>   is_type ? type++ : other++;
>   }
>   read_unlock(_lock);
> -- 
> 2.19.1

Re: [RFC][PATCH v2 11/21] kvm: allocate page table pages from DRAM

[Yuan Yao]

On Tue, Jan 01, 2019 at 02:53:07PM +0530, Aneesh Kumar K.V wrote:
> Fengguang Wu  writes:
> 
> > From: Yao Yuan 
> >
> > Signed-off-by: Yao Yuan 
> > Signed-off-by: Fengguang Wu 
> > ---
> > arch/x86/kvm/mmu.c |   12 +++-
> > 1 file changed, 11 insertions(+), 1 deletion(-)
> >
> > --- linux.orig/arch/x86/kvm/mmu.c   2018-12-26 20:54:48.846720344 +0800
> > +++ linux/arch/x86/kvm/mmu.c2018-12-26 20:54:48.842719614 +0800
> > @@ -950,6 +950,16 @@ static void mmu_free_memory_cache(struct
> > kmem_cache_free(cache, mc->objects[--mc->nobjs]);
> >  }
> >  
> > +static unsigned long __get_dram_free_pages(gfp_t gfp_mask)
> > +{
> > +   struct page *page;
> > +
> > +   page = __alloc_pages(GFP_KERNEL_ACCOUNT, 0, numa_node_id());
> > +   if (!page)
> > +  return 0;
> > +   return (unsigned long) page_address(page);
> > +}
> > +
> 
> May be it is explained in other patches. What is preventing the
> allocation from pmem here? Is it that we are not using the memory
> policy prefered node id and hence the zone list we built won't have the
> PMEM node?

That because the PMEM nodes are memory-only node in the patchset,
so numa_node_id() will always return the node id from DRAM nodes.

About the zone list, yes in patch 10/21 we build the PMEM nodes to
seperate zonelist, so DRAM nodes will not fall back to PMEM nodes.

> 
> >  static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
> >int min)
> >  {
> > @@ -958,7 +968,7 @@ static int mmu_topup_memory_cache_page(s
> > if (cache->nobjs >= min)
> > return 0;
> > while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
> > -   page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
> > +   page = (void *)__get_dram_free_pages(GFP_KERNEL_ACCOUNT);
> > if (!page)
> > return cache->nobjs >= min ? 0 : -ENOMEM;
> > cache->objects[cache->nobjs++] = page;
> 
> -aneesh
> 

[PATCH] serial: fsl_lpuart: Remove the alias node dependence

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Numbering the ttyLPn space should not depend on the generic name
"serial".

If don't add the alias node like:"serial0 = ", then lpuart
will probe failed:
[0.773410] fsl-lpuart 295.serial: failed to get alias id, errno -19

So remove the alias node dependence, and add the support for allocate the
line port automatically.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/tty/serial/fsl_lpuart.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index a1c6519..c6d639f 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -231,6 +231,8 @@
 #define DEV_NAME   "ttyLP"
 #define UART_NR6
 
+static DECLARE_BITMAP(linemap, UART_NR);
+
 struct lpuart_port {
struct uart_portport;
struct clk  *clk;
@@ -1963,9 +1965,13 @@ static int lpuart_probe(struct platform_device *pdev)
 
ret = of_alias_get_id(np, "serial");
if (ret < 0) {
-   dev_err(>dev, "failed to get alias id, errno %d\n", ret);
-   return ret;
+   ret = find_first_zero_bit(linemap, UART_NR);
+   if (ret >= UART_NR) {
+   dev_err(>dev, "port line is full, add device 
failed\n");
+   return ret;
+   }
}
+   set_bit(ret, linemap);
sport->port.line = ret;
sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
 
@@ -2047,6 +2053,7 @@ static int lpuart_remove(struct platform_device *pdev)
struct lpuart_port *sport = platform_get_drvdata(pdev);
 
uart_remove_one_port(_reg, >port);
+   clear_bit(sport->port.line, linemap);
 
clk_disable_unprepare(sport->clk);
 
-- 
2.1.0.27.g96db324

[PATCH] serial: fsl_lpuart: Remove the alias node dependence

[Yuan Yao]

From: Yuan Yao 

Numbering the ttyLPn space should not depend on the generic name
"serial".

If don't add the alias node like:"serial0 = ", then lpuart
will probe failed:
[0.773410] fsl-lpuart 295.serial: failed to get alias id, errno -19

So remove the alias node dependence, and add the support for allocate the
line port automatically.

Signed-off-by: Yuan Yao 
---
 drivers/tty/serial/fsl_lpuart.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index a1c6519..c6d639f 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -231,6 +231,8 @@
 #define DEV_NAME   "ttyLP"
 #define UART_NR6
 
+static DECLARE_BITMAP(linemap, UART_NR);
+
 struct lpuart_port {
struct uart_portport;
struct clk  *clk;
@@ -1963,9 +1965,13 @@ static int lpuart_probe(struct platform_device *pdev)
 
ret = of_alias_get_id(np, "serial");
if (ret < 0) {
-   dev_err(>dev, "failed to get alias id, errno %d\n", ret);
-   return ret;
+   ret = find_first_zero_bit(linemap, UART_NR);
+   if (ret >= UART_NR) {
+   dev_err(>dev, "port line is full, add device 
failed\n");
+   return ret;
+   }
}
+   set_bit(ret, linemap);
sport->port.line = ret;
sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
 
@@ -2047,6 +2053,7 @@ static int lpuart_remove(struct platform_device *pdev)
struct lpuart_port *sport = platform_get_drvdata(pdev);
 
uart_remove_one_port(_reg, >port);
+   clear_bit(sport->port.line, linemap);
 
clk_disable_unprepare(sport->clk);
 
-- 
2.1.0.27.g96db324

[PATCH 2/5] Documentation: fsl: dspi: Add fsl,ls1012a-dspi compatible string

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

new compatible string: "fsl,ls1012a-dspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index ff5893d..800c483 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -5,6 +5,7 @@ Required properties:
"fsl,ls2085a-dspi"
or
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
+   "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH 2/5] Documentation: fsl: dspi: Add fsl,ls1012a-dspi compatible string

[Yuan Yao]

From: Yuan Yao 

new compatible string: "fsl,ls1012a-dspi".

Signed-off-by: Yuan Yao 
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index ff5893d..800c483 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -5,6 +5,7 @@ Required properties:
"fsl,ls2085a-dspi"
or
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
+   "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH 5/5] Documentation: fsl-quadspi: Add fsl,ls1012a-qspi compatible string

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

new compatible string: "fsl,ls1012a-qspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index c34aa6f..a2ed621 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -7,6 +7,7 @@ Required properties:
 or
 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
+"fsl,ls1012a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH 5/5] Documentation: fsl-quadspi: Add fsl,ls1012a-qspi compatible string

[Yuan Yao]

From: Yuan Yao 

new compatible string: "fsl,ls1012a-qspi".

Signed-off-by: Yuan Yao 
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index c34aa6f..a2ed621 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -7,6 +7,7 @@ Required properties:
 or
 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
+"fsl,ls1012a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH 4/5] arm64: dts: ls1012a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

There is a s25fs512s qspi flash on QDS, RDB and FRDM board.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 14 ++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  | 15 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts  | 15 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 15 +++
 4 files changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
index 81bd689..34f9e76 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -110,6 +110,20 @@
};
 };
 
+ {
+   num-cs = <2>;
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs512s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
index 3d32c76..0e5befa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -156,6 +156,21 @@
};
 };
 
+ {
+   num-cs = <2>;
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs512s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   m25p,fast-read;
+   reg = <0>;
+   };
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
index 62c5c71..c20bfd3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -57,3 +57,18 @@
  {
status = "okay";
 };
+
+ {
+   num-cs = <2>;
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs512s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   m25p,fast-read;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index c917a87..72e61c5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -195,6 +195,21 @@
#interrupt-cells = <2>;
};
 
+   qspi: quadspi@155 {
+   compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x155 0x0 0x1>,
+   <0x0 0x4000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
+   clock-names = "qspi_en", "qspi";
+   clocks = < 4 0>, < 4 0>;
+   big-endian;
+   fsl,qspi-has-second-chip;
+   status = "disabled";
+   };
+
wdog0: wdog@2ad {
compatible = "fsl,ls1012a-wdt",
 "fsl,imx21-wdt";
-- 
2.1.0.27.g96db324

[PATCH 1/5] arm64: dts: ls1012a: add the DTS node for DSPI support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 33 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi| 13 +
 2 files changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
index b841251..3d32c76 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -93,6 +93,39 @@
};
 };
 
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "n25q128a11", "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+
+   flash@1 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "sst25wf040b", "jedec,spi-nor";
+   spi-cpol;
+   spi-cpha;
+   reg = <1>;
+   spi-max-frequency = <1000>;
+   };
+
+   flash@2 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "en25s64", "jedec,spi-nor";
+   spi-cpol;
+   spi-cpha;
+   reg = <2>;
+   spi-max-frequency = <1000>;
+   };
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 92e64f3..c917a87 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -148,6 +148,19 @@
status = "disabled";
};
 
+   dspi: dspi@210 {
+   compatible = "fsl,ls1012a-dspi", 
"fsl,ls1021a-v1.0-dspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x210 0x0 0x1>;
+   interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
+   clock-names = "dspi";
+   clocks = < 4 0>;
+   spi-num-chipselects = <5>;
+   big-endian;
+   status = "disabled";
+   };
+
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
-- 
2.1.0.27.g96db324

[PATCH 1/5] arm64: dts: ls1012a: add the DTS node for DSPI support

[Yuan Yao]

From: Yuan Yao 

Signed-off-by: Yuan Yao 
---
 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 33 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi| 13 +
 2 files changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
index b841251..3d32c76 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -93,6 +93,39 @@
};
 };
 
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "n25q128a11", "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+
+   flash@1 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "sst25wf040b", "jedec,spi-nor";
+   spi-cpol;
+   spi-cpha;
+   reg = <1>;
+   spi-max-frequency = <1000>;
+   };
+
+   flash@2 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "en25s64", "jedec,spi-nor";
+   spi-cpol;
+   spi-cpha;
+   reg = <2>;
+   spi-max-frequency = <1000>;
+   };
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 92e64f3..c917a87 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -148,6 +148,19 @@
status = "disabled";
};
 
+   dspi: dspi@210 {
+   compatible = "fsl,ls1012a-dspi", 
"fsl,ls1021a-v1.0-dspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x210 0x0 0x1>;
+   interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
+   clock-names = "dspi";
+   clocks = < 4 0>;
+   spi-num-chipselects = <5>;
+   big-endian;
+   status = "disabled";
+   };
+
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
-- 
2.1.0.27.g96db324

[PATCH 4/5] arm64: dts: ls1012a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao 

There is a s25fs512s qspi flash on QDS, RDB and FRDM board.

Signed-off-by: Yuan Yao 
---
 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 14 ++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  | 15 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts  | 15 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 15 +++
 4 files changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
index 81bd689..34f9e76 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -110,6 +110,20 @@
};
 };
 
+ {
+   num-cs = <2>;
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs512s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
index 3d32c76..0e5befa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -156,6 +156,21 @@
};
 };
 
+ {
+   num-cs = <2>;
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs512s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   m25p,fast-read;
+   reg = <0>;
+   };
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
index 62c5c71..c20bfd3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -57,3 +57,18 @@
  {
status = "okay";
 };
+
+ {
+   num-cs = <2>;
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs512s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   m25p,fast-read;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index c917a87..72e61c5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -195,6 +195,21 @@
#interrupt-cells = <2>;
};
 
+   qspi: quadspi@155 {
+   compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x155 0x0 0x1>,
+   <0x0 0x4000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
+   clock-names = "qspi_en", "qspi";
+   clocks = < 4 0>, < 4 0>;
+   big-endian;
+   fsl,qspi-has-second-chip;
+   status = "disabled";
+   };
+
wdog0: wdog@2ad {
compatible = "fsl,ls1012a-wdt",
 "fsl,imx21-wdt";
-- 
2.1.0.27.g96db324

[PATCH 0/5] arm64: dts: ls1012a: add the DTS node for QSPI/DSPI support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

LS1012A also support QSPI and DSPI.
This patch set is used to add the QSPI/DSPI node for LS1012A.

This patch set is depend on the patch for add LS1012A platform dts support:
arm64: Add DTS support for FSL's LS1012A SoC

The patchwork link:
https://patchwork.kernel.org/patch/9462399/

Yuan Yao (5):
  arm64: dts: ls1012a: add the DTS node for DSPI support
  Documentation: fsl: dspi: Add fsl,ls1012a-dspi compatible string
  Documentation: dt: mtd: add chip support for "jedec, spi-nor"
  arm64: dts: ls1012a: add the DTS node for QSPI support
  Documentation: fsl-quadspi: Add fsl,ls1012a-qspi compatible string

 .../devicetree/bindings/mtd/fsl-quadspi.txt|  1 +
 .../devicetree/bindings/mtd/jedec,spi-nor.txt  |  2 +
 .../devicetree/bindings/spi/spi-fsl-dspi.txt   |  1 +
 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 14 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  | 48 ++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts  | 15 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 28 +
 7 files changed, 109 insertions(+)

-- 
2.1.0.27.g96db324

[PATCH 0/5] arm64: dts: ls1012a: add the DTS node for QSPI/DSPI support

[Yuan Yao]

From: Yuan Yao 

LS1012A also support QSPI and DSPI.
This patch set is used to add the QSPI/DSPI node for LS1012A.

This patch set is depend on the patch for add LS1012A platform dts support:
arm64: Add DTS support for FSL's LS1012A SoC

The patchwork link:
https://patchwork.kernel.org/patch/9462399/

Yuan Yao (5):
  arm64: dts: ls1012a: add the DTS node for DSPI support
  Documentation: fsl: dspi: Add fsl,ls1012a-dspi compatible string
  Documentation: dt: mtd: add chip support for "jedec, spi-nor"
  arm64: dts: ls1012a: add the DTS node for QSPI support
  Documentation: fsl-quadspi: Add fsl,ls1012a-qspi compatible string

 .../devicetree/bindings/mtd/fsl-quadspi.txt|  1 +
 .../devicetree/bindings/mtd/jedec,spi-nor.txt  |  2 +
 .../devicetree/bindings/spi/spi-fsl-dspi.txt   |  1 +
 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 14 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  | 48 ++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts  | 15 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 28 +
 7 files changed, 109 insertions(+)

-- 
2.1.0.27.g96db324

[PATCH 3/5] Documentation: dt: mtd: add chip support for "jedec, spi-nor"

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

"sst25wf040b" and "en25s64" are also chip compatible with SPI NOR flash.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt 
b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
index 2c91c03..86614ee 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
@@ -13,6 +13,7 @@ Required properties:
  at25df321a
  at25df641
  at26df081a
+ en25s64
  mr25h256
  mx25l4005a
  mx25l1606e
@@ -29,6 +30,7 @@ Required properties:
  s25fl008k
  s25fl064k
  sst25vf040b
+ sst25wf040b
  m25p40
  m25p80
  m25p16
-- 
2.1.0.27.g96db324

[PATCH 3/5] Documentation: dt: mtd: add chip support for "jedec, spi-nor"

[Yuan Yao]

From: Yuan Yao 

"sst25wf040b" and "en25s64" are also chip compatible with SPI NOR flash.

Signed-off-by: Yuan Yao 
---
 Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt 
b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
index 2c91c03..86614ee 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
@@ -13,6 +13,7 @@ Required properties:
  at25df321a
  at25df641
  at26df081a
+ en25s64
  mr25h256
  mx25l4005a
  mx25l1606e
@@ -29,6 +30,7 @@ Required properties:
  s25fl008k
  s25fl064k
  sst25vf040b
+ sst25wf040b
  m25p40
  m25p80
  m25p16
-- 
2.1.0.27.g96db324

[PATCH] spi: dspi: clear SPI_SR before enable interrupt

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Once dspi is used in uboot, the SPI_SR have been set by some value.
At this time, if kernel enable the interrupt before clear the
status flag, that will trigger the wrong interrupt.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/spi/spi-fsl-dspi.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 35c0dd9..a67b0ff 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -70,6 +70,7 @@
 #define SPI_SR 0x2c
 #define SPI_SR_EOQF0x1000
 #define SPI_SR_TCFQF   0x8000
+#define SPI_SR_CLEAR   0xdaad
 
 #define SPI_RSER   0x30
 #define SPI_RSER_EOQFE 0x1000
@@ -646,6 +647,11 @@ static const struct regmap_config dspi_regmap_config = {
.max_register = 0x88,
 };
 
+static void dspi_init(struct fsl_dspi *dspi)
+{
+   regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
+}
+
 static int dspi_probe(struct platform_device *pdev)
 {
struct device_node *np = pdev->dev.of_node;
@@ -709,6 +715,7 @@ static int dspi_probe(struct platform_device *pdev)
return PTR_ERR(dspi->regmap);
}
 
+   dspi_init(dspi);
dspi->irq = platform_get_irq(pdev, 0);
if (dspi->irq < 0) {
dev_err(>dev, "can't get platform irq\n");
-- 
2.1.0.27.g96db324

[PATCH] spi: dspi: clear SPI_SR before enable interrupt

[Yuan Yao]

From: Yuan Yao 

Once dspi is used in uboot, the SPI_SR have been set by some value.
At this time, if kernel enable the interrupt before clear the
status flag, that will trigger the wrong interrupt.

Signed-off-by: Yuan Yao 
---
 drivers/spi/spi-fsl-dspi.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 35c0dd9..a67b0ff 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -70,6 +70,7 @@
 #define SPI_SR 0x2c
 #define SPI_SR_EOQF0x1000
 #define SPI_SR_TCFQF   0x8000
+#define SPI_SR_CLEAR   0xdaad
 
 #define SPI_RSER   0x30
 #define SPI_RSER_EOQFE 0x1000
@@ -646,6 +647,11 @@ static const struct regmap_config dspi_regmap_config = {
.max_register = 0x88,
 };
 
+static void dspi_init(struct fsl_dspi *dspi)
+{
+   regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
+}
+
 static int dspi_probe(struct platform_device *pdev)
 {
struct device_node *np = pdev->dev.of_node;
@@ -709,6 +715,7 @@ static int dspi_probe(struct platform_device *pdev)
return PTR_ERR(dspi->regmap);
}
 
+   dspi_init(dspi);
dspi->irq = platform_get_irq(pdev, 0);
if (dspi->irq < 0) {
dev_err(>dev, "can't get platform irq\n");
-- 
2.1.0.27.g96db324

[PATCH v1 0/5] dma: Add QorIQ qDMA engine driver support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

dma: Add QorIQ qDMA engine driver support

Yuan Yao (5):
  dma: Add QorIQ qDMA engine driver support
  dma: Add device tree binding for QorIQ qDMA driver
  MAINTAINERS: add maintainer entry for QorIQ QDMA driver
  ARM: dts: ls1043a: add qDMA node
  ARM: dts: ls1021a: add qDMA node

 .../devicetree/bindings/dma/qoriq-qdma.txt |  38 +
 MAINTAINERS|   7 +
 arch/arm/boot/dts/ls1021a.dtsi |  10 +
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  10 +
 drivers/dma/Kconfig|  12 +
 drivers/dma/Makefile   |   1 +
 drivers/dma/qoriq-qdma.c   | 900 +
 drivers/dma/qoriq-qdma.h   | 272 +++
 8 files changed, 1250 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/qoriq-qdma.txt
 create mode 100644 drivers/dma/qoriq-qdma.c
 create mode 100644 drivers/dma/qoriq-qdma.h

-- 
2.1.0.27.g96db324

[PATCH v1 0/5] dma: Add QorIQ qDMA engine driver support

[Yuan Yao]

From: Yuan Yao 

dma: Add QorIQ qDMA engine driver support

Yuan Yao (5):
  dma: Add QorIQ qDMA engine driver support
  dma: Add device tree binding for QorIQ qDMA driver
  MAINTAINERS: add maintainer entry for QorIQ QDMA driver
  ARM: dts: ls1043a: add qDMA node
  ARM: dts: ls1021a: add qDMA node

 .../devicetree/bindings/dma/qoriq-qdma.txt |  38 +
 MAINTAINERS|   7 +
 arch/arm/boot/dts/ls1021a.dtsi |  10 +
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  10 +
 drivers/dma/Kconfig|  12 +
 drivers/dma/Makefile   |   1 +
 drivers/dma/qoriq-qdma.c   | 900 +
 drivers/dma/qoriq-qdma.h   | 272 +++
 8 files changed, 1250 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/qoriq-qdma.txt
 create mode 100644 drivers/dma/qoriq-qdma.c
 create mode 100644 drivers/dma/qoriq-qdma.h

-- 
2.1.0.27.g96db324

[PATCH v1 2/5] dma: Add device tree binding for QorIQ qDMA driver

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Adding devicetree binding for QorIQ queue direct memory access(QDMA).
This module can be found on QorIQ LS1021A and LS1043A SoCs.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 .../devicetree/bindings/dma/qoriq-qdma.txt | 38 ++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/qoriq-qdma.txt

diff --git a/Documentation/devicetree/bindings/dma/qoriq-qdma.txt 
b/Documentation/devicetree/bindings/dma/qoriq-qdma.txt
new file mode 100644
index 000..dfa286e
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/qoriq-qdma.txt
@@ -0,0 +1,38 @@
+* QorIQ queue Direct Memory Access Controller(qDMA) Controller
+
+  The QorIQ qDMA controller transfers blocks of data between one source and 
one or more
+destinations. The blocks of data transferred can be represented in memory as 
contiguous
+or non-contiguous using scatter/gather table(s). Channel virtualization is 
supported
+through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
+queues.
+
+* qDMA Controller
+Required properties:
+- compatible :
+   - "fsl,ls1021a-qdma",
+   Or "fsl,ls1043a-qdma" followed by "fsl,ls1021a-qdma",
+- reg : Specifies base physical address(s) and size of the qDMA registers.
+   The region is qDMA control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+   interrupt-names.
+- interrupt-names : Should contain:
+   "qdma-error" - the error interrupt
+   "qdma-queue" - the queue interrupt
+
+Optional properties:
+- big-endian: If present registers and hardware scatter/gather descriptors
+   of the qDMA are implemented in big endian mode, otherwise in little
+   mode.
+
+
+Examples:
+
+   qdma: qdma@839 {
+   compatible = "fsl,ls1021a-qdma";
+   reg = <0x0 0x8398000 0x0 0x2000 /* Controller registers */
+  0x0 0x839a000 0x0 0x2000>; /* Block registers */
+   interrupts = ,
+   ;
+   interrupt-names = "qdma-error", "qdma-queue";
+   big-endian;
+   };
-- 
2.1.0.27.g96db324

[PATCH v1 2/5] dma: Add device tree binding for QorIQ qDMA driver

[Yuan Yao]

From: Yuan Yao 

Adding devicetree binding for QorIQ queue direct memory access(QDMA).
This module can be found on QorIQ LS1021A and LS1043A SoCs.

Signed-off-by: Yuan Yao 
---
 .../devicetree/bindings/dma/qoriq-qdma.txt | 38 ++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/qoriq-qdma.txt

diff --git a/Documentation/devicetree/bindings/dma/qoriq-qdma.txt 
b/Documentation/devicetree/bindings/dma/qoriq-qdma.txt
new file mode 100644
index 000..dfa286e
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/qoriq-qdma.txt
@@ -0,0 +1,38 @@
+* QorIQ queue Direct Memory Access Controller(qDMA) Controller
+
+  The QorIQ qDMA controller transfers blocks of data between one source and 
one or more
+destinations. The blocks of data transferred can be represented in memory as 
contiguous
+or non-contiguous using scatter/gather table(s). Channel virtualization is 
supported
+through enqueuing of DMA jobs to, or dequeuing DMA jobs from, different work
+queues.
+
+* qDMA Controller
+Required properties:
+- compatible :
+   - "fsl,ls1021a-qdma",
+   Or "fsl,ls1043a-qdma" followed by "fsl,ls1021a-qdma",
+- reg : Specifies base physical address(s) and size of the qDMA registers.
+   The region is qDMA control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+   interrupt-names.
+- interrupt-names : Should contain:
+   "qdma-error" - the error interrupt
+   "qdma-queue" - the queue interrupt
+
+Optional properties:
+- big-endian: If present registers and hardware scatter/gather descriptors
+   of the qDMA are implemented in big endian mode, otherwise in little
+   mode.
+
+
+Examples:
+
+   qdma: qdma@839 {
+   compatible = "fsl,ls1021a-qdma";
+   reg = <0x0 0x8398000 0x0 0x2000 /* Controller registers */
+  0x0 0x839a000 0x0 0x2000>; /* Block registers */
+   interrupts = ,
+   ;
+   interrupt-names = "qdma-error", "qdma-queue";
+   big-endian;
+   };
-- 
2.1.0.27.g96db324

[PATCH v1 4/5] ARM: dts: ls1043a: add qDMA node

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Add the QDMA node for ls1043a platform to
support QDMA driver.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e8e4c3e..e463074 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -467,6 +467,16 @@
 < 4 0>;
};
 
+   qdma: qdma@839 {
+   compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
+   reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */
+  0x0 0x83a 0x0 0x4>; /* Block regs */
+   interrupts = <0 153 0x4>,
+   <0 39 0x4>;
+   interrupt-names = "qdma-error", "qdma-queue";
+   big-endian;
+   };
+
usb0: usb3@2f0 {
compatible = "snps,dwc3";
reg = <0x0 0x2f0 0x0 0x1>;
-- 
2.1.0.27.g96db324

[PATCH v1 4/5] ARM: dts: ls1043a: add qDMA node

[Yuan Yao]

From: Yuan Yao 

Add the QDMA node for ls1043a platform to
support QDMA driver.

Signed-off-by: Yuan Yao 
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e8e4c3e..e463074 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -467,6 +467,16 @@
 < 4 0>;
};
 
+   qdma: qdma@839 {
+   compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
+   reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */
+  0x0 0x83a 0x0 0x4>; /* Block regs */
+   interrupts = <0 153 0x4>,
+   <0 39 0x4>;
+   interrupt-names = "qdma-error", "qdma-queue";
+   big-endian;
+   };
+
usb0: usb3@2f0 {
compatible = "snps,dwc3";
reg = <0x0 0x2f0 0x0 0x1>;
-- 
2.1.0.27.g96db324

[PATCH v1 1/5] dma: Add QorIQ qDMA engine driver support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Add QorIQ queue direct memory access(QDMA) controller support.
This module can be found on QorIQ LS1021A and LS1043A SoCs.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 drivers/dma/Kconfig  |  12 +
 drivers/dma/Makefile |   1 +
 drivers/dma/qoriq-qdma.c | 900 +++
 drivers/dma/qoriq-qdma.h | 272 ++
 4 files changed, 1185 insertions(+)
 create mode 100644 drivers/dma/qoriq-qdma.c
 create mode 100644 drivers/dma/qoriq-qdma.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 739f797..a1d8c05 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -193,6 +193,18 @@ config FSL_EDMA
  multiplexing capability for DMA request sources(slot).
  This module can be found on Freescale Vybrid and LS-1 SoCs.
 
+config QORIQ_QDMA
+   tristate "QorIQ qDMA engine support"
+   select DMA_ENGINE
+   select DMA_VIRTUAL_CHANNELS
+   select DMA_ENGINE_RAID
+   select ASYNC_TX_ENABLE_CHANNEL_SWITCH
+   help
+ Support the QorIQ qDMA engine with command queue mode.
+ Channel virtualization is supported through enqueuing of DMA jobs to,
+ or dequeuing DMA jobs from, different work queues.
+ This module can be found on some QorIQ SoCs.
+
 config FSL_RAID
 tristate "Freescale RAID engine Support"
 depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index e4dc9ca..9c8d0a7 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
 obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
 obj-$(CONFIG_FSL_DMA) += fsldma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_QORIQ_QDMA) += qoriq-qdma.o
 obj-$(CONFIG_FSL_RAID) += fsl_raid.o
 obj-$(CONFIG_HSU_DMA) += hsu/
 obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/qoriq-qdma.c b/drivers/dma/qoriq-qdma.c
new file mode 100644
index 000..53d8809
--- /dev/null
+++ b/drivers/dma/qoriq-qdma.c
@@ -0,0 +1,900 @@
+/*
+ * drivers/dma/qoriq-qdma.c
+ *
+ * Copyright 2015-2016 NXP Semiconductor, Inc.
+ *
+ * Driver for the QorIQ qDMA engine with software command queue mode.
+ * Channel virtualization is supported through enqueuing of DMA jobs to,
+ * or dequeuing DMA jobs from, different work queues.
+ * This module can be found on some QorIQ SoCs.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "qoriq-qdma.h"
+
+static unsigned int channels = 2;
+module_param(channels, uint, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(channels, "Number of channels supported by driver");
+
+static unsigned int status_sizes[FSL_QDMA_MAX_BLOCK], status_num;
+module_param_array(status_sizes, uint, _num,
+   S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(status_sizes, "Size of each status queue in bytes");
+
+static unsigned int queue_sizes[FSL_QDMA_MAX_QUEUE], queue_num;
+module_param_array(queue_sizes, uint, _num,
+   S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(queue_sizes, "Size of each command queue in bytes");
+
+static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
+{
+   struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+   unsigned long flags;
+   LIST_HEAD(head);
+
+   spin_lock_irqsave(_chan->vchan.lock, flags);
+   vchan_get_all_descriptors(_chan->vchan, );
+   spin_unlock_irqrestore(_chan->vchan.lock, flags);
+
+   vchan_dma_desc_free_list(_chan->vchan, );
+}
+
+static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
+   dma_addr_t dst, dma_addr_t src, u32 len)
+{
+   struct fsl_qdma_frame *frame;
+
+   memset(fsl_comp->virt_addr, 0, FSL_QDMA_BASE_BUFFER_SIZE);
+   frame = (struct fsl_qdma_frame *)fsl_comp->virt_addr;
+   /* Head Command Descriptor(Frame Descriptor) */
+   frame->ccdf.addr_low = lower_32_bits(fsl_comp->bus_addr + 16);
+   frame->ccdf.dd_q_addr_high = (upper_32_bits(fsl_comp->bus_addr + 16))
+& QDMA_CCDF_ADDR_HIGH_MASK;
+   /* Compound S/G format */
+   frame->ccdf.format_offset = (0 << QDMA_CCDF_OFFSET_SHIFT) |
+   (0x1 << QDMA_CCDF_FORMAT_SHIFT);
+   /* Status notification is enqueued to status queue. */
+   frame->ccdf.ser_status = QDMA_CCDF_SER;
+
+   /* Compound Command Descriptor(Frame List Table) */
+   frame->

[PATCH v1 5/5] ARM: dts: ls1021a: add qDMA node

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Add the QDMA node for ls1021a platform to
support QDMA driver.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm/boot/dts/ls1021a.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..a1ca071 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -493,6 +493,16 @@
 <_clk 1>;
};
 
+   qdma: qdma@839 {
+   compatible = "fsl,ls1021a-qdma";
+   reg = <0x0 0x8398000 0x0 0x2000 /* Controller regs */
+  0x0 0x839a000 0x0 0x2000>; /* Block regs */
+   interrupts = ,
+   ;
+   interrupt-names = "qdma-error", "qdma-queue";
+   big-endian;
+   };
+
dcu: dcu@2ce {
compatible = "fsl,ls1021a-dcu";
reg = <0x0 0x2ce 0x0 0x1>;
-- 
2.1.0.27.g96db324

[PATCH v1 5/5] ARM: dts: ls1021a: add qDMA node

[Yuan Yao]

From: Yuan Yao 

Add the QDMA node for ls1021a platform to
support QDMA driver.

Signed-off-by: Yuan Yao 
---
 arch/arm/boot/dts/ls1021a.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..a1ca071 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -493,6 +493,16 @@
 <_clk 1>;
};
 
+   qdma: qdma@839 {
+   compatible = "fsl,ls1021a-qdma";
+   reg = <0x0 0x8398000 0x0 0x2000 /* Controller regs */
+  0x0 0x839a000 0x0 0x2000>; /* Block regs */
+   interrupts = ,
+   ;
+   interrupt-names = "qdma-error", "qdma-queue";
+   big-endian;
+   };
+
dcu: dcu@2ce {
compatible = "fsl,ls1021a-dcu";
reg = <0x0 0x2ce 0x0 0x1>;
-- 
2.1.0.27.g96db324

[PATCH v1 1/5] dma: Add QorIQ qDMA engine driver support

[Yuan Yao]

From: Yuan Yao 

Add QorIQ queue direct memory access(QDMA) controller support.
This module can be found on QorIQ LS1021A and LS1043A SoCs.

Signed-off-by: Yuan Yao 
---
 drivers/dma/Kconfig  |  12 +
 drivers/dma/Makefile |   1 +
 drivers/dma/qoriq-qdma.c | 900 +++
 drivers/dma/qoriq-qdma.h | 272 ++
 4 files changed, 1185 insertions(+)
 create mode 100644 drivers/dma/qoriq-qdma.c
 create mode 100644 drivers/dma/qoriq-qdma.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 739f797..a1d8c05 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -193,6 +193,18 @@ config FSL_EDMA
  multiplexing capability for DMA request sources(slot).
  This module can be found on Freescale Vybrid and LS-1 SoCs.
 
+config QORIQ_QDMA
+   tristate "QorIQ qDMA engine support"
+   select DMA_ENGINE
+   select DMA_VIRTUAL_CHANNELS
+   select DMA_ENGINE_RAID
+   select ASYNC_TX_ENABLE_CHANNEL_SWITCH
+   help
+ Support the QorIQ qDMA engine with command queue mode.
+ Channel virtualization is supported through enqueuing of DMA jobs to,
+ or dequeuing DMA jobs from, different work queues.
+ This module can be found on some QorIQ SoCs.
+
 config FSL_RAID
 tristate "Freescale RAID engine Support"
 depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index e4dc9ca..9c8d0a7 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
 obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
 obj-$(CONFIG_FSL_DMA) += fsldma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_QORIQ_QDMA) += qoriq-qdma.o
 obj-$(CONFIG_FSL_RAID) += fsl_raid.o
 obj-$(CONFIG_HSU_DMA) += hsu/
 obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/qoriq-qdma.c b/drivers/dma/qoriq-qdma.c
new file mode 100644
index 000..53d8809
--- /dev/null
+++ b/drivers/dma/qoriq-qdma.c
@@ -0,0 +1,900 @@
+/*
+ * drivers/dma/qoriq-qdma.c
+ *
+ * Copyright 2015-2016 NXP Semiconductor, Inc.
+ *
+ * Driver for the QorIQ qDMA engine with software command queue mode.
+ * Channel virtualization is supported through enqueuing of DMA jobs to,
+ * or dequeuing DMA jobs from, different work queues.
+ * This module can be found on some QorIQ SoCs.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "qoriq-qdma.h"
+
+static unsigned int channels = 2;
+module_param(channels, uint, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(channels, "Number of channels supported by driver");
+
+static unsigned int status_sizes[FSL_QDMA_MAX_BLOCK], status_num;
+module_param_array(status_sizes, uint, _num,
+   S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(status_sizes, "Size of each status queue in bytes");
+
+static unsigned int queue_sizes[FSL_QDMA_MAX_QUEUE], queue_num;
+module_param_array(queue_sizes, uint, _num,
+   S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(queue_sizes, "Size of each command queue in bytes");
+
+static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
+{
+   struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
+   unsigned long flags;
+   LIST_HEAD(head);
+
+   spin_lock_irqsave(_chan->vchan.lock, flags);
+   vchan_get_all_descriptors(_chan->vchan, );
+   spin_unlock_irqrestore(_chan->vchan.lock, flags);
+
+   vchan_dma_desc_free_list(_chan->vchan, );
+}
+
+static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
+   dma_addr_t dst, dma_addr_t src, u32 len)
+{
+   struct fsl_qdma_frame *frame;
+
+   memset(fsl_comp->virt_addr, 0, FSL_QDMA_BASE_BUFFER_SIZE);
+   frame = (struct fsl_qdma_frame *)fsl_comp->virt_addr;
+   /* Head Command Descriptor(Frame Descriptor) */
+   frame->ccdf.addr_low = lower_32_bits(fsl_comp->bus_addr + 16);
+   frame->ccdf.dd_q_addr_high = (upper_32_bits(fsl_comp->bus_addr + 16))
+& QDMA_CCDF_ADDR_HIGH_MASK;
+   /* Compound S/G format */
+   frame->ccdf.format_offset = (0 << QDMA_CCDF_OFFSET_SHIFT) |
+   (0x1 << QDMA_CCDF_FORMAT_SHIFT);
+   /* Status notification is enqueued to status queue. */
+   frame->ccdf.ser_status = QDMA_CCDF_SER;
+
+   /* Compound Command Descriptor(Frame List Table) */
+   frame->csgf_desc.addr_low = lower_32_bits(fsl_comp->bus_add

[PATCH v1 3/5] MAINTAINERS: add maintainer entry for QorIQ QDMA driver

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Add a maintainer entry for QorIQ QDMA driver and add myself
as a maintainer.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 MAINTAINERS | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0a309db..278d2f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4934,6 +4934,13 @@ L:   linuxppc-...@lists.ozlabs.org
 S: Maintained
 F: drivers/dma/fsldma.*
 
+QorIQ QDMA DRIVER
+M: Yuan Yao <yao.y...@nxp.com>
+L: linux-arm-ker...@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/dma/qoriq-qdma.txt
+F: drivers/dma/qoriq-qdma.*
+
 FREESCALE GPMI NAND DRIVER
 M: Han Xu <han...@nxp.com>
 L: linux-...@lists.infradead.org
-- 
2.1.0.27.g96db324

[PATCH v1 3/5] MAINTAINERS: add maintainer entry for QorIQ QDMA driver

[Yuan Yao]

From: Yuan Yao 

Add a maintainer entry for QorIQ QDMA driver and add myself
as a maintainer.

Signed-off-by: Yuan Yao 
---
 MAINTAINERS | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0a309db..278d2f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4934,6 +4934,13 @@ L:   linuxppc-...@lists.ozlabs.org
 S: Maintained
 F: drivers/dma/fsldma.*
 
+QorIQ QDMA DRIVER
+M: Yuan Yao 
+L: linux-arm-ker...@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/dma/qoriq-qdma.txt
+F: drivers/dma/qoriq-qdma.*
+
 FREESCALE GPMI NAND DRIVER
 M: Han Xu 
 L: linux-...@lists.infradead.org
-- 
2.1.0.27.g96db324

[PATCH v2 2/2] arm64: dts: ls1043a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v2:
Remove unused property.
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 13 +
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 14 ++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index 80688ac..9d3e9fe 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -166,3 +166,16 @@
  {
status = "okay";
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fl128s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index be72bf5..e70b7f2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -171,6 +171,20 @@
interrupts = <0 43 0x4>;
};
 
+   qspi: quadspi@155 {
+   compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x155 0x0 0x1>,
+   <0x0 0x4000 0x0 0x400>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   interrupts = <0 99 0x4>;
+   clock-names = "qspi_en", "qspi";
+   clocks = < 4 0>, < 4 0>;
+   big-endian;
+   status = "disabled";
+   };
+
esdhc: esdhc@156 {
compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
reg = <0x0 0x156 0x0 0x1>;
-- 
2.1.0.27.g96db324

[PATCH v2 2/2] arm64: dts: ls1043a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao 

Signed-off-by: Yuan Yao 
---
Changed in v2:
Remove unused property.
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 13 +
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 14 ++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index 80688ac..9d3e9fe 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -166,3 +166,16 @@
  {
status = "okay";
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fl128s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index be72bf5..e70b7f2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -171,6 +171,20 @@
interrupts = <0 43 0x4>;
};
 
+   qspi: quadspi@155 {
+   compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x155 0x0 0x1>,
+   <0x0 0x4000 0x0 0x400>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   interrupts = <0 99 0x4>;
+   clock-names = "qspi_en", "qspi";
+   clocks = < 4 0>, < 4 0>;
+   big-endian;
+   status = "disabled";
+   };
+
esdhc: esdhc@156 {
compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
reg = <0x0 0x156 0x0 0x1>;
-- 
2.1.0.27.g96db324

[PATCH v2 0/2] arm64: dts: ls1043a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Yuan Yao (2):
  Documentation: fsl-quadspi: Add fsl, ls1043a-qspi compatible string
Changed in v2: Remove unused property.
  arm64: dts: ls1043a: add the DTS node for QSPI support

 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt |  3 ++-
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 13 +
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 14 ++
 3 files changed, 29 insertions(+), 1 deletion(-)

-- 
2.1.0.27.g96db324

[PATCH v2 1/2] Documentation: fsl-quadspi: Add fsl, ls1043a-qspi compatible string

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

new compatible string: "fsl,ls1043a-qspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 0333ec8..c34aa6f 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -5,7 +5,8 @@ Required properties:
 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
 "fsl,ls1021a-qspi"
 or
-"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
+"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
+"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH v2 0/2] arm64: dts: ls1043a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao 

Yuan Yao (2):
  Documentation: fsl-quadspi: Add fsl, ls1043a-qspi compatible string
Changed in v2: Remove unused property.
  arm64: dts: ls1043a: add the DTS node for QSPI support

 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt |  3 ++-
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 13 +
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 14 ++
 3 files changed, 29 insertions(+), 1 deletion(-)

-- 
2.1.0.27.g96db324

[PATCH v2 1/2] Documentation: fsl-quadspi: Add fsl, ls1043a-qspi compatible string

[Yuan Yao]

From: Yuan Yao 

new compatible string: "fsl,ls1043a-qspi".

Signed-off-by: Yuan Yao 
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 0333ec8..c34aa6f 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -5,7 +5,8 @@ Required properties:
 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
 "fsl,ls1021a-qspi"
 or
-"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
+"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
+"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH 2/2] dts/ls1043a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 16 
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 14 ++
 2 files changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index 97e9906..c8303a3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -100,6 +100,22 @@
};
 };
 
+ {
+   num-cs = <2>;
+   bus-num = <0>;
+   status = "okay";
+   fsl,ddr-sampling-point = <4>;
+
+   qflash0: s25fl128s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   ddr-quad-read;
+   reg = <0>;
+   };
+};
+
  {
status = "okay";
pca9547@77 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index be72bf5..49b1aeb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -208,6 +208,20 @@
status = "disabled";
};
 
+   qspi: quadspi@155 {
+   compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x155 0x0 0x1>,
+   <0x0 0x4000 0x0 0x400>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   interrupts = <0 99 0x4>;
+   clock-names = "qspi_en", "qspi";
+   clocks = < 4 0>, < 4 0>;
+   big-endian;
+   status = "disabled";
+   };
+
i2c0: i2c@218 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
-- 
2.1.0.27.g96db324

[PATCH 0/2] dts/ls1043a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

The QSPI controller on LS1043A is the same with the QSPI on LS1021A.
We shuld add the QSPI support on LS1043A.

So this patch try to add the dts node and binding Documentation.

Depend on the patch:
arm64: dts: add LS1043a-QDS board support
https://patchwork.kernel.org/patch/8528821/

Yuan Yao (2):
  Documentation: fsl-quadspi: Add fsl, ls1043a-qspi compatible string
  dts/ls1043a: add the DTS node for QSPI support

 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt |  3 ++-
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 16 
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 14 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

-- 
2.1.0.27.g96db324

[PATCH 2/2] dts/ls1043a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao 

Signed-off-by: Yuan Yao 
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 16 
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 14 ++
 2 files changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index 97e9906..c8303a3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -100,6 +100,22 @@
};
 };
 
+ {
+   num-cs = <2>;
+   bus-num = <0>;
+   status = "okay";
+   fsl,ddr-sampling-point = <4>;
+
+   qflash0: s25fl128s@0 {
+   compatible = "spansion,m25p80";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-max-frequency = <2000>;
+   ddr-quad-read;
+   reg = <0>;
+   };
+};
+
  {
status = "okay";
pca9547@77 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index be72bf5..49b1aeb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -208,6 +208,20 @@
status = "disabled";
};
 
+   qspi: quadspi@155 {
+   compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x155 0x0 0x1>,
+   <0x0 0x4000 0x0 0x400>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   interrupts = <0 99 0x4>;
+   clock-names = "qspi_en", "qspi";
+   clocks = < 4 0>, < 4 0>;
+   big-endian;
+   status = "disabled";
+   };
+
i2c0: i2c@218 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
-- 
2.1.0.27.g96db324

[PATCH 0/2] dts/ls1043a: add the DTS node for QSPI support

[Yuan Yao]

From: Yuan Yao 

The QSPI controller on LS1043A is the same with the QSPI on LS1021A.
We shuld add the QSPI support on LS1043A.

So this patch try to add the dts node and binding Documentation.

Depend on the patch:
arm64: dts: add LS1043a-QDS board support
https://patchwork.kernel.org/patch/8528821/

Yuan Yao (2):
  Documentation: fsl-quadspi: Add fsl, ls1043a-qspi compatible string
  dts/ls1043a: add the DTS node for QSPI support

 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt |  3 ++-
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 16 
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 14 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

-- 
2.1.0.27.g96db324

[PATCH 1/2] Documentation: fsl-quadspi: Add fsl, ls1043a-qspi compatible string

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

new compatible string: "fsl,ls1043a-qspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 0333ec8..c34aa6f 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -5,7 +5,8 @@ Required properties:
 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
 "fsl,ls1021a-qspi"
 or
-"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
+"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
+"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH 1/2] Documentation: fsl-quadspi: Add fsl, ls1043a-qspi compatible string

[Yuan Yao]

From: Yuan Yao 

new compatible string: "fsl,ls1043a-qspi".

Signed-off-by: Yuan Yao 
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 0333ec8..c34aa6f 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -5,7 +5,8 @@ Required properties:
 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
 "fsl,ls1021a-qspi"
 or
-"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
+"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
+"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH v6 1/2] Documentation: fsl: dspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-dspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changed in v6:
No changes.

Changed in v5:
Fix the subject and commit message.

Changed in v4:
No changes.

Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..1ad0fe3 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,10 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi"
+   or
+   "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH v6 1/2] Documentation: fsl: dspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-dspi".

Signed-off-by: Yuan Yao 
Acked-by: Rob Herring 
---
Changed in v6:
No changes.

Changed in v5:
Fix the subject and commit message.

Changed in v4:
No changes.

Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"

Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..1ad0fe3 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,10 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi"
+   or
+   "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH v6 2/2] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Han xu <han...@nxp.com>
---
Changed in v6:
No changes.

Changed in v5:
Resend base on arm-soc.

Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi| 4 ++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index 4cb996d..e8801fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -178,7 +178,14 @@
 
  {
status = "okay";
-   qflash0: s25fl008k {
+   flash0: s25fl256s1@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,m25p80";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+   flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 2b23d03..65e612a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -318,7 +318,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
@@ -444,7 +444,7 @@
 
qspi: quadspi@20c {
status = "disabled";
-   compatible = "fsl,vf610-qspi";
+   compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c 0x0 0x1>,
-- 
2.1.0.27.g96db324

[PATCH v6 2/2] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

Signed-off-by: Yuan Yao 
Acked-by: Han xu 
---
Changed in v6:
No changes.

Changed in v5:
Resend base on arm-soc.

Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to 
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi| 4 ++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index 4cb996d..e8801fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -178,7 +178,14 @@
 
  {
status = "okay";
-   qflash0: s25fl008k {
+   flash0: s25fl256s1@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,m25p80";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+   flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 2b23d03..65e612a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -318,7 +318,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
@@ -444,7 +444,7 @@
 
qspi: quadspi@20c {
status = "disabled";
-   compatible = "fsl,vf610-qspi";
+   compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c 0x0 0x1>,
-- 
2.1.0.27.g96db324

[PATCH v6 0/2] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Both of the patches are already send out to l2-mtd as a part of the set
for add QSPI support on Freescale new SOC before.

But those two patch should not be merged into l2-mtd, so I have to resend them.

Yuan Yao (2):
  dts/ls2080a: update the DTS for QSPI and DSPI support
  Documentation: fsl: dspi: Add fsl,ls2080a-dspi compatible string

 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts  | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++--
 3 files changed, 14 insertions(+), 4 deletions(-)

-- 
2.1.0.27.g96db324

[PATCH v6 0/2] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

From: Yuan Yao 

Both of the patches are already send out to l2-mtd as a part of the set
for add QSPI support on Freescale new SOC before.

But those two patch should not be merged into l2-mtd, so I have to resend them.

Yuan Yao (2):
  dts/ls2080a: update the DTS for QSPI and DSPI support
  Documentation: fsl: dspi: Add fsl,ls2080a-dspi compatible string

 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts  | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++--
 3 files changed, 14 insertions(+), 4 deletions(-)

-- 
2.1.0.27.g96db324

[PATCH v5 1/2] Documentation: fsl: dspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-dspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changed in v5:
Fix the subject and commit message.

Changed in v4:
No changes.

Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..1ad0fe3 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,10 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi"
+   or
+   "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH v5 1/2] Documentation: fsl: dspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-dspi".

Signed-off-by: Yuan Yao 
Acked-by: Rob Herring 
---
Changed in v5:
Fix the subject and commit message.

Changed in v4:
No changes.

Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"

Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..1ad0fe3 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,10 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi"
+   or
+   "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH 2/2] dts/ls2080a: Update DSPI compatible

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

The patch adds LS2085a to DSPI compatible.
The DSPI driver on LS2080A should use TCFQ mode.
It's different from on vf610.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 9d746c6..122c517 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -318,7 +318,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
-- 
2.1.0.27.g96db324

[PATCH 2/2] dts/ls2080a: Update DSPI compatible

[Yuan Yao]

From: Yuan Yao 

The patch adds LS2085a to DSPI compatible.
The DSPI driver on LS2080A should use TCFQ mode.
It's different from on vf610.

Signed-off-by: Yuan Yao 
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 9d746c6..122c517 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -318,7 +318,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
-- 
2.1.0.27.g96db324

[PATCH] dts/ls1021a: add the DTS for QSPI support

[Yuan Yao]

From: Yuan Yao 

Signed-off-by: Yuan Yao 
---
Add in v1:
Can merge, but the function depend on the patch:
https://patchwork.kernel.org/patch/8118251/

mtd: spi-nor: fsl-quadspi: add support for ls1021a

LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.

---
 arch/arm/boot/dts/ls1021a.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 9430a99..c764fa5 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -252,6 +252,21 @@
status = "disabled";
};
 
+   qspi: quadspi@155 {
+   compatible = "fsl,ls1021a-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x155 0x0 0x1>,
+   <0x0 0x4000 0x0 0x400>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   interrupts = ;
+   clock-names = "qspi_en", "qspi";
+   clocks = <_clk 1>, <_clk 1>;
+   big-endian;
+   amba-base = <0x4000>;
+   status = "disabled";
+   };
+
i2c0: i2c@218 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
-- 
2.1.0.27.g96db324

[PATCH] dts/ls1021a: add the DTS for QSPI support

[Yuan Yao]

From: Yuan Yao <yao.y...@nxp.com>

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Add in v1:
Can merge, but the function depend on the patch:
https://patchwork.kernel.org/patch/8118251/

mtd: spi-nor: fsl-quadspi: add support for ls1021a

LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.

---
 arch/arm/boot/dts/ls1021a.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 9430a99..c764fa5 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -252,6 +252,21 @@
status = "disabled";
};
 
+   qspi: quadspi@155 {
+   compatible = "fsl,ls1021a-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x155 0x0 0x1>,
+   <0x0 0x4000 0x0 0x400>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   interrupts = ;
+   clock-names = "qspi_en", "qspi";
+   clocks = <_clk 1>, <_clk 1>;
+   big-endian;
+   amba-base = <0x4000>;
+   status = "disabled";
+   };
+
i2c0: i2c@218 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
-- 
2.1.0.27.g96db324

[PATCH v4 3/7] mtd: spi-nor: fsl-quadspi: add support for layerscape

[Yuan Yao]

LS1043a and LS2080A in the Layerscape family also support Freescale Quad
SPI, make Quad SPI selectable for these hardwares.

Signed-off-by: Yuan Yao 
---
Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to 
---
 drivers/mtd/spi-nor/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index a28c278..6b53deb 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
-- 
2.1.0.27.g96db324

[PATCH v4 5/7] Documentation: fsl-quadspi: Add fsl, ls2080a-qspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao 
Acked-by: Rob Herring 
---
Changed in v4:
No changes.

Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"

Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 00c587b..0df2f3a 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -3,7 +3,9 @@
 Required properties:
   - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
-"fsl,ls1021-qspi"
+"fsl,ls1021a-qspi"
+or
+"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH v4 6/7] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

Signed-off-by: Yuan Yao 
---
Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to 
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi| 4 ++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index 4cb996d..e8801fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -178,7 +178,14 @@
 
  {
status = "okay";
-   qflash0: s25fl008k {
+   flash0: s25fl256s1@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,m25p80";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+   flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 2b23d03..65e612a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -318,7 +318,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
@@ -444,7 +444,7 @@
 
qspi: quadspi@20c {
status = "disabled";
-   compatible = "fsl,vf610-qspi";
+   compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c 0x0 0x1>,
-- 
2.1.0.27.g96db324

[PATCH v4 2/7] mtd: spi-nor: fsl-quadspi: add support for ls1021a

[Yuan Yao]

LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.

Signed-off-by: Yuan Yao 
Acked-by: Han xu 
---
Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to 
---
 drivers/mtd/spi-nor/Kconfig   |  2 +-
 drivers/mtd/spi-nor/fsl-quadspi.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 0dc9275..a28c278 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 04e8a93..9ab2b51 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -213,6 +213,7 @@ enum fsl_qspi_devtype {
FSL_QUADSPI_IMX6SX,
FSL_QUADSPI_IMX7D,
FSL_QUADSPI_IMX6UL,
+   FSL_QUADSPI_LS1021A,
 };
 
 struct fsl_qspi_devtype_data {
@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6ul_data = {
   | QUADSPI_QUIRK_4X_INT_CLK,
 };
 
+static struct fsl_qspi_devtype_data ls1021a_data = {
+   .devtype = FSL_QUADSPI_LS1021A,
+   .rxfifo = 128,
+   .txfifo = 64,
+   .ahb_buf_size = 1024,
+   .driver_data = 0,
+};
+
 #define FSL_QSPI_MAX_CHIP  4
 struct fsl_qspi {
struct spi_nor nor[FSL_QSPI_MAX_CHIP];
@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
{ .compatible = "fsl,imx6sx-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx7d-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)_data, },
+   { .compatible = "fsl,ls1021a-qspi", .data = (void *)_data, },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
2.1.0.27.g96db324

[PATCH v4 7/7] Documentation: fsl-quadspi: Add optional properties

[Yuan Yao]

Add optional properties for QSPI:
big-endian
if the register is big endian on this platform.

Signed-off-by: Yuan Yao 
Acked-by: Rob Herring 
---
Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 0df2f3a..0333ec8 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -21,6 +21,7 @@ Optional properties:
  But if there are two NOR flashes connected to the
  bus, you should enable this property.
  (Please check the board's schematic.)
+  - big-endian : That means the IP register is big endian
 
 Example:
 
-- 
2.1.0.27.g96db324

[PATCH v4 4/7] Documentation: fsl-quadspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao 
Acked-by: Rob Herring 
---
Changed in v4:
No changes.

Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"

Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..1ad0fe3 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,10 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi"
+   or
+   "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH v4 1/7] mtd: spi-nor: fsl-quadspi: add big-endian support

[Yuan Yao]

Add R/W functions for big- or little-endian registers:
The qSPI controller's endian is independent of the CPU core's endian.
So far, the qSPI have two versions for big-endian and little-endian.

Signed-off-by: Yuan Yao 
Acked-by: Han xu 
---
Changed in v4:
No changes.

Changed in v3:
Update my email to 

Changed in v2:
Rebase to the lastest code.
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++---
 1 file changed, 97 insertions(+), 60 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 54640f1..04e8a93 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -275,6 +275,7 @@ struct fsl_qspi {
u32 clk_rate;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
+   bool big_endian;
struct mutex lock;
struct pm_qos_request pm_qos_req;
 };
@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
*q)
 }
 
 /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+ * So far, although the CPU core is little-endian but the qSPI have two
+ * versions for big-endian and little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+   if (q->big_endian)
+   iowrite32be(val, addr);
+   else
+   iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+   if (q->big_endian)
+   return ioread32be(addr);
+   else
+   return ioread32(addr);
+}
+
+/*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
  */
@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
*q, u32 a)
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
*dev_id)
u32 reg;
 
/* clear interrupt */
-   reg = readl(q->iobase + QUADSPI_FR);
-   writel(reg, q->iobase + QUADSPI_FR);
+   reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+   qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
if (reg & QUADSPI_FR_TFF_MASK)
complete(>c);
@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
/* Clear all the LUT table */
for (i = 0; i < QUADSPI_LUT_NUM; i++)
-   writel(0, base + QUADSPI_LUT_BASE + i * 4);
+   qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
dummy = 8;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+   qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
 
/* Write enable */
lut_base = SEQID_WREN * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+   base + QUADSPI_LUT(lut_base));
 
/* Page Program */
lut_base = SEQID_PP * 4;
@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
addrlen = ADDR32BIT;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+   base + QUADSPI_LUT(lut_base + 1));
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
+   LUT

[PATCH v4 3/7] mtd: spi-nor: fsl-quadspi: add support for layerscape

[Yuan Yao]

LS1043a and LS2080A in the Layerscape family also support Freescale Quad
SPI, make Quad SPI selectable for these hardwares.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 drivers/mtd/spi-nor/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index a28c278..6b53deb 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
-- 
2.1.0.27.g96db324

[PATCH v4 1/7] mtd: spi-nor: fsl-quadspi: add big-endian support

[Yuan Yao]

Add R/W functions for big- or little-endian registers:
The qSPI controller's endian is independent of the CPU core's endian.
So far, the qSPI have two versions for big-endian and little-endian.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Han xu <han...@freescale.com>
---
Changed in v4:
No changes.

Changed in v3:
Update my email to <yao.y...@nxp.com>

Changed in v2:
Rebase to the lastest code.
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++---
 1 file changed, 97 insertions(+), 60 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 54640f1..04e8a93 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -275,6 +275,7 @@ struct fsl_qspi {
u32 clk_rate;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
+   bool big_endian;
struct mutex lock;
struct pm_qos_request pm_qos_req;
 };
@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
*q)
 }
 
 /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+ * So far, although the CPU core is little-endian but the qSPI have two
+ * versions for big-endian and little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+   if (q->big_endian)
+   iowrite32be(val, addr);
+   else
+   iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+   if (q->big_endian)
+   return ioread32be(addr);
+   else
+   return ioread32(addr);
+}
+
+/*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
  */
@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
*q, u32 a)
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
*dev_id)
u32 reg;
 
/* clear interrupt */
-   reg = readl(q->iobase + QUADSPI_FR);
-   writel(reg, q->iobase + QUADSPI_FR);
+   reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+   qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
if (reg & QUADSPI_FR_TFF_MASK)
complete(>c);
@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
/* Clear all the LUT table */
for (i = 0; i < QUADSPI_LUT_NUM; i++)
-   writel(0, base + QUADSPI_LUT_BASE + i * 4);
+   qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
dummy = 8;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+   qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
 
/* Write enable */
lut_base = SEQID_WREN * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+   base + QUADSPI_LUT(lut_base));
 
/* Page Program */
lut_base = SEQID_PP * 4;
@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
addrlen = ADDR32BIT;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+   base + QUADSPI_LUT(lut_base + 1));
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_R

[PATCH v4 7/7] Documentation: fsl-quadspi: Add optional properties

[Yuan Yao]

Add optional properties for QSPI:
big-endian
if the register is big endian on this platform.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 0df2f3a..0333ec8 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -21,6 +21,7 @@ Optional properties:
  But if there are two NOR flashes connected to the
  bus, you should enable this property.
  (Please check the board's schematic.)
+  - big-endian : That means the IP register is big endian
 
 Example:
 
-- 
2.1.0.27.g96db324

[PATCH v4 4/7] Documentation: fsl-quadspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changed in v4:
No changes.

Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..1ad0fe3 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,10 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi"
+   or
+   "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH v4 2/7] mtd: spi-nor: fsl-quadspi: add support for ls1021a

[Yuan Yao]

LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Han xu <han...@freescale.com>
---
Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 drivers/mtd/spi-nor/Kconfig   |  2 +-
 drivers/mtd/spi-nor/fsl-quadspi.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 0dc9275..a28c278 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 04e8a93..9ab2b51 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -213,6 +213,7 @@ enum fsl_qspi_devtype {
FSL_QUADSPI_IMX6SX,
FSL_QUADSPI_IMX7D,
FSL_QUADSPI_IMX6UL,
+   FSL_QUADSPI_LS1021A,
 };
 
 struct fsl_qspi_devtype_data {
@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6ul_data = {
   | QUADSPI_QUIRK_4X_INT_CLK,
 };
 
+static struct fsl_qspi_devtype_data ls1021a_data = {
+   .devtype = FSL_QUADSPI_LS1021A,
+   .rxfifo = 128,
+   .txfifo = 64,
+   .ahb_buf_size = 1024,
+   .driver_data = 0,
+};
+
 #define FSL_QSPI_MAX_CHIP  4
 struct fsl_qspi {
struct spi_nor nor[FSL_QSPI_MAX_CHIP];
@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
{ .compatible = "fsl,imx6sx-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx7d-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)_data, },
+   { .compatible = "fsl,ls1021a-qspi", .data = (void *)_data, },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
2.1.0.27.g96db324

[PATCH v4 6/7] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v4:
No changes.

Changed in v3:
No changes.

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi| 4 ++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index 4cb996d..e8801fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -178,7 +178,14 @@
 
  {
status = "okay";
-   qflash0: s25fl008k {
+   flash0: s25fl256s1@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,m25p80";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+   flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 2b23d03..65e612a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -318,7 +318,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
@@ -444,7 +444,7 @@
 
qspi: quadspi@20c {
status = "disabled";
-   compatible = "fsl,vf610-qspi";
+   compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c 0x0 0x1>,
-- 
2.1.0.27.g96db324

[PATCH v4 5/7] Documentation: fsl-quadspi: Add fsl, ls2080a-qspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changed in v4:
No changes.

Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 00c587b..0df2f3a 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -3,7 +3,9 @@
 Required properties:
   - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
-"fsl,ls1021-qspi"
+"fsl,ls1021a-qspi"
+or
+"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH v3 3/3] mtd: spi-nor: fsl-quadspi: add support for layerscape

[Yuan Yao]

LS1043a and LS2080A in the Layerscape family also support Freescale Quad
SPI, make Quad SPI selectable for these hardwares.

Signed-off-by: Yuan Yao 
---
Changed in v3:
No changes.

Changed in v2:
Update my email to 
---
 drivers/mtd/spi-nor/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index a28c278..6b53deb 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
-- 
2.1.0.27.g96db324

[PATCH v3 1/3] mtd: spi-nor: fsl-quadspi: add big-endian support

[Yuan Yao]

Add R/W functions for big- or little-endian registers:
The qSPI controller's endian is independent of the CPU core's endian.
So far, the qSPI have two versions for big-endian and little-endian.

Signed-off-by: Yuan Yao 
Acked-by: Han xu 
---
Changed in v3:
Update my email to 

Changed in v2:
Rebase to the lastest code.
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++---
 1 file changed, 97 insertions(+), 60 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 54640f1..04e8a93 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -275,6 +275,7 @@ struct fsl_qspi {
u32 clk_rate;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
+   bool big_endian;
struct mutex lock;
struct pm_qos_request pm_qos_req;
 };
@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
*q)
 }
 
 /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+ * So far, although the CPU core is little-endian but the qSPI have two
+ * versions for big-endian and little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+   if (q->big_endian)
+   iowrite32be(val, addr);
+   else
+   iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+   if (q->big_endian)
+   return ioread32be(addr);
+   else
+   return ioread32(addr);
+}
+
+/*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
  */
@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
*q, u32 a)
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
*dev_id)
u32 reg;
 
/* clear interrupt */
-   reg = readl(q->iobase + QUADSPI_FR);
-   writel(reg, q->iobase + QUADSPI_FR);
+   reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+   qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
if (reg & QUADSPI_FR_TFF_MASK)
complete(>c);
@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
/* Clear all the LUT table */
for (i = 0; i < QUADSPI_LUT_NUM; i++)
-   writel(0, base + QUADSPI_LUT_BASE + i * 4);
+   qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
dummy = 8;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+   qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
 
/* Write enable */
lut_base = SEQID_WREN * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+   base + QUADSPI_LUT(lut_base));
 
/* Page Program */
lut_base = SEQID_PP * 4;
@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
addrlen = ADDR32BIT;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+   base + QUADSPI_LUT(lut_base + 1));
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
+   LUT1(FSL_READ, PAD1, 0x1),

[PATCH v3 2/3] mtd: spi-nor: fsl-quadspi: add support for ls1021a

[Yuan Yao]

LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.

Signed-off-by: Yuan Yao 
Acked-by: Han xu 
---
Changed in v3:
No changes.

Changed in v2:
Update my email to 
---
 drivers/mtd/spi-nor/Kconfig   |  2 +-
 drivers/mtd/spi-nor/fsl-quadspi.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 0dc9275..a28c278 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 04e8a93..9ab2b51 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -213,6 +213,7 @@ enum fsl_qspi_devtype {
FSL_QUADSPI_IMX6SX,
FSL_QUADSPI_IMX7D,
FSL_QUADSPI_IMX6UL,
+   FSL_QUADSPI_LS1021A,
 };
 
 struct fsl_qspi_devtype_data {
@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6ul_data = {
   | QUADSPI_QUIRK_4X_INT_CLK,
 };
 
+static struct fsl_qspi_devtype_data ls1021a_data = {
+   .devtype = FSL_QUADSPI_LS1021A,
+   .rxfifo = 128,
+   .txfifo = 64,
+   .ahb_buf_size = 1024,
+   .driver_data = 0,
+};
+
 #define FSL_QSPI_MAX_CHIP  4
 struct fsl_qspi {
struct spi_nor nor[FSL_QSPI_MAX_CHIP];
@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
{ .compatible = "fsl,imx6sx-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx7d-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)_data, },
+   { .compatible = "fsl,ls1021a-qspi", .data = (void *)_data, },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
2.1.0.27.g96db324

mtd: spi-nor: fsl-quadspi: add support for ls1021a

[Yuan Yao]

This patch set is used for add the fsl-quadspi support for ls1021a and
ls1043a, so remove the patch:
mtd: spi-nor: fsl-quadspi: extend support for some special requerment.

This patch will be send with anther patch set for add QSPI support on LS2080A.

All the new property are document in anther patch set which is already
send to linux-kernel@vger.kernel.org and devicet...@vger.kernel.org.
Here is the patch name:
0001-Documentation-fsl-quadspi-Add-fsl-ls2080a-dspi-compa.patch
0002-Documentation-fsl-quadspi-Add-fsl-ls2080a-qspi-compa.patch
0003-dts-ls2080a-update-the-DTS-for-QSPI-and-DSPI-support.patch
0004-Documentation-fsl-quadspi-Add-optional-properties.patch

Any extra information you can find them on the patchwork:
https://patchwork.kernel.org/patch/8078931/
https://patchwork.kernel.org/patch/8078951/
https://patchwork.kernel.org/patch/8079091/
https://patchwork.kernel.org/patch/8078941/

Thanks.

Yuan Yao.

mtd: spi-nor: fsl-quadspi: add support for ls1021a

[Yuan Yao]

This patch set is used for add the fsl-quadspi support for ls1021a and
ls1043a, so remove the patch:
mtd: spi-nor: fsl-quadspi: extend support for some special requerment.

This patch will be send with anther patch set for add QSPI support on LS2080A.

All the new property are document in anther patch set which is already
send to linux-kernel@vger.kernel.org and devicet...@vger.kernel.org.
Here is the patch name:
0001-Documentation-fsl-quadspi-Add-fsl-ls2080a-dspi-compa.patch
0002-Documentation-fsl-quadspi-Add-fsl-ls2080a-qspi-compa.patch
0003-dts-ls2080a-update-the-DTS-for-QSPI-and-DSPI-support.patch
0004-Documentation-fsl-quadspi-Add-optional-properties.patch

Any extra information you can find them on the patchwork:
https://patchwork.kernel.org/patch/8078931/
https://patchwork.kernel.org/patch/8078951/
https://patchwork.kernel.org/patch/8079091/
https://patchwork.kernel.org/patch/8078941/

Thanks.

Yuan Yao.

[PATCH v3 1/3] mtd: spi-nor: fsl-quadspi: add big-endian support

[Yuan Yao]

Add R/W functions for big- or little-endian registers:
The qSPI controller's endian is independent of the CPU core's endian.
So far, the qSPI have two versions for big-endian and little-endian.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Han xu <han...@freescale.com>
---
Changed in v3:
Update my email to <yao.y...@nxp.com>

Changed in v2:
Rebase to the lastest code.
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++---
 1 file changed, 97 insertions(+), 60 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 54640f1..04e8a93 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -275,6 +275,7 @@ struct fsl_qspi {
u32 clk_rate;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
+   bool big_endian;
struct mutex lock;
struct pm_qos_request pm_qos_req;
 };
@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
*q)
 }
 
 /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+ * So far, although the CPU core is little-endian but the qSPI have two
+ * versions for big-endian and little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+   if (q->big_endian)
+   iowrite32be(val, addr);
+   else
+   iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+   if (q->big_endian)
+   return ioread32be(addr);
+   else
+   return ioread32(addr);
+}
+
+/*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
  */
@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
*q, u32 a)
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
*dev_id)
u32 reg;
 
/* clear interrupt */
-   reg = readl(q->iobase + QUADSPI_FR);
-   writel(reg, q->iobase + QUADSPI_FR);
+   reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+   qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
if (reg & QUADSPI_FR_TFF_MASK)
complete(>c);
@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
/* Clear all the LUT table */
for (i = 0; i < QUADSPI_LUT_NUM; i++)
-   writel(0, base + QUADSPI_LUT_BASE + i * 4);
+   qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
dummy = 8;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+   qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
 
/* Write enable */
lut_base = SEQID_WREN * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+   base + QUADSPI_LUT(lut_base));
 
/* Page Program */
lut_base = SEQID_PP * 4;
@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
addrlen = ADDR32BIT;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+   base + QUADSPI_LUT(lut_base + 1));
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
+   qspi_writel(q, LUT0(CMD, PA

[PATCH v3 2/3] mtd: spi-nor: fsl-quadspi: add support for ls1021a

[Yuan Yao]

LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Han xu <han...@freescale.com>
---
Changed in v3:
No changes.

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 drivers/mtd/spi-nor/Kconfig   |  2 +-
 drivers/mtd/spi-nor/fsl-quadspi.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 0dc9275..a28c278 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 04e8a93..9ab2b51 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -213,6 +213,7 @@ enum fsl_qspi_devtype {
FSL_QUADSPI_IMX6SX,
FSL_QUADSPI_IMX7D,
FSL_QUADSPI_IMX6UL,
+   FSL_QUADSPI_LS1021A,
 };
 
 struct fsl_qspi_devtype_data {
@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6ul_data = {
   | QUADSPI_QUIRK_4X_INT_CLK,
 };
 
+static struct fsl_qspi_devtype_data ls1021a_data = {
+   .devtype = FSL_QUADSPI_LS1021A,
+   .rxfifo = 128,
+   .txfifo = 64,
+   .ahb_buf_size = 1024,
+   .driver_data = 0,
+};
+
 #define FSL_QSPI_MAX_CHIP  4
 struct fsl_qspi {
struct spi_nor nor[FSL_QSPI_MAX_CHIP];
@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
{ .compatible = "fsl,imx6sx-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx7d-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)_data, },
+   { .compatible = "fsl,ls1021a-qspi", .data = (void *)_data, },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
2.1.0.27.g96db324

[PATCH v3 3/3] mtd: spi-nor: fsl-quadspi: add support for layerscape

[Yuan Yao]

LS1043a and LS2080A in the Layerscape family also support Freescale Quad
SPI, make Quad SPI selectable for these hardwares.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
No changes.

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 drivers/mtd/spi-nor/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index a28c278..6b53deb 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
-- 
2.1.0.27.g96db324

[PATCH v3 3/4] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

Signed-off-by: Yuan Yao 
---
Changed in v3:
No changes.

Changed in v2:
Update my email to 
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi| 4 ++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index 4cb996d..e8801fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -178,7 +178,14 @@
 
  {
status = "okay";
-   qflash0: s25fl008k {
+   flash0: s25fl256s1@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,m25p80";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+   flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 2b23d03..65e612a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -318,7 +318,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
@@ -444,7 +444,7 @@
 
qspi: quadspi@20c {
status = "disabled";
-   compatible = "fsl,vf610-qspi";
+   compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c 0x0 0x1>,
-- 
2.1.0.27.g96db324

[PATCH v3 2/4] Documentation: fsl-quadspi: Add fsl, ls2080a-qspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao 
---
Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"

Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 00c587b..0df2f3a 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -3,7 +3,9 @@
 Required properties:
   - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
-"fsl,ls1021-qspi"
+"fsl,ls1021a-qspi"
+or
+"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH v3 4/4] Documentation: fsl-quadspi: Add optional properties

[Yuan Yao]

Add optional properties for QSPI:
big-endian
if the register is big endian on this platform.

Signed-off-by: Yuan Yao 
---
Changed in v3:
No changes.

Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 0df2f3a..0333ec8 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -21,6 +21,7 @@ Optional properties:
  But if there are two NOR flashes connected to the
  bus, you should enable this property.
  (Please check the board's schematic.)
+  - big-endian : That means the IP register is big endian
 
 Example:
 
-- 
2.1.0.27.g96db324

[PATCH v3 1/4] Documentation: fsl-quadspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao 
---
Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"

Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..1ad0fe3 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,10 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi"
+   or
+   "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH v3 3/4] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
No changes.

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi| 4 ++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index 4cb996d..e8801fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -178,7 +178,14 @@
 
  {
status = "okay";
-   qflash0: s25fl008k {
+   flash0: s25fl256s1@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,m25p80";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+   flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 2b23d03..65e612a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -318,7 +318,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
@@ -444,7 +444,7 @@
 
qspi: quadspi@20c {
status = "disabled";
-   compatible = "fsl,vf610-qspi";
+   compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c 0x0 0x1>,
-- 
2.1.0.27.g96db324

[PATCH v3 4/4] Documentation: fsl-quadspi: Add optional properties

[Yuan Yao]

Add optional properties for QSPI:
big-endian
if the register is big endian on this platform.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
No changes.

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 0df2f3a..0333ec8 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -21,6 +21,7 @@ Optional properties:
  But if there are two NOR flashes connected to the
  bus, you should enable this property.
  (Please check the board's schematic.)
+  - big-endian : That means the IP register is big endian
 
 Example:
 
-- 
2.1.0.27.g96db324

[PATCH v3 1/4] Documentation: fsl-quadspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..1ad0fe3 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,10 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi"
+   or
+   "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

[PATCH v3 2/4] Documentation: fsl-quadspi: Add fsl, ls2080a-qspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"

Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 00c587b..0df2f3a 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -3,7 +3,9 @@
 Required properties:
   - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
-"fsl,ls1021-qspi"
+"fsl,ls1021a-qspi"
+or
+"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

[PATCH v2 3/4] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

Signed-off-by: Yuan Yao 
---
Changed in v2:
Update my email to 
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi| 4 ++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index 4cb996d..e8801fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -178,7 +178,14 @@
 
  {
status = "okay";
-   qflash0: s25fl008k {
+   flash0: s25fl256s1@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,m25p80";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+   flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index e81cd48..7a80666 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -250,7 +250,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2085a-dspi", "fsl,ls2080a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
@@ -371,7 +371,7 @@
 
qspi: quadspi@20c {
status = "disabled";
-   compatible = "fsl,vf610-qspi";
+   compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c 0x0 0x1>,
-- 
2.1.0.27.g96db324

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 4/4] mtd: spi-nor: fsl-quadspi: extend support for some special requerment.

[Yuan Yao]

Add extra info in LUT table to support some special requerments.
Spansion S25FS-S family flash need some special operations.

Signed-off-by: Yuan Yao 
---
Changed in v2:
Update my email to 
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 41 +--
 include/linux/mtd/spi-nor.h   |  4 
 2 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 9ab2b51..081ae85 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -205,6 +205,8 @@
 #define SEQID_RDCR 9
 #define SEQID_EN4B 10
 #define SEQID_BRWR 11
+#define SEQID_RDAR 12
+#define SEQID_WRAR 13
 
 #define QUADSPI_MIN_IOMAP SZ_4M
 
@@ -476,6 +478,28 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
base + QUADSPI_LUT(lut_base));
 
+   /*
+* Read any device register.
+* Used for Spansion S25FS-S family flash only.
+*/
+   lut_base = SEQID_RDAR * 4;
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
+   LUT1(ADDR, PAD1, ADDR24BIT),
+   base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
+   base + QUADSPI_LUT(lut_base + 1));
+
+   /*
+* Write any device register.
+* Used for Spansion S25FS-S family flash only.
+*/
+   lut_base = SEQID_WRAR * 4;
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
+   LUT1(ADDR, PAD1, ADDR24BIT),
+   base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
+   base + QUADSPI_LUT(lut_base + 1));
+
fsl_qspi_lock_lut(q);
 }
 
@@ -484,7 +508,12 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
 {
switch (cmd) {
case SPINOR_OP_READ_1_1_4:
+   case SPINOR_OP_READ4_1_1_4:
return SEQID_QUAD_READ;
+   case SPINOR_OP_SPANSION_RDAR:
+   return SEQID_RDAR;
+   case SPINOR_OP_SPANSION_WRAR:
+   return SEQID_WRAR;
case SPINOR_OP_WREN:
return SEQID_WREN;
case SPINOR_OP_WRDI:
@@ -835,8 +864,12 @@ static int fsl_qspi_read_reg(struct spi_nor *nor, u8 
opcode, u8 *buf, int len)
 {
int ret;
struct fsl_qspi *q = nor->priv;
+   u32 to = 0;
+
+   if (opcode == SPINOR_OP_SPANSION_RDAR)
+   memcpy(, nor->cmd_buf, 4);
 
-   ret = fsl_qspi_runcmd(q, opcode, 0, len);
+   ret = fsl_qspi_runcmd(q, opcode, to, len);
if (ret)
return ret;
 
@@ -848,9 +881,13 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 
opcode, u8 *buf, int len)
 {
struct fsl_qspi *q = nor->priv;
int ret;
+   u32 to = 0;
+
+   if (opcode == SPINOR_OP_SPANSION_RDAR)
+   memcpy(, nor->cmd_buf, 4);
 
if (!buf) {
-   ret = fsl_qspi_runcmd(q, opcode, 0, 1);
+   ret = fsl_qspi_runcmd(q, opcode, to, 1);
if (ret)
return ret;
 
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fac3f6f..7a2f193 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -74,6 +74,10 @@
 /* Used for Spansion flashes only. */
 #define SPINOR_OP_BRWR 0x17/* Bank register write */
 
+/* Used for Spansion S25FS-S family flash only. */
+#define SPINOR_OP_SPANSION_RDAR0x65/* Read any device register */
+#define SPINOR_OP_SPANSION_WRAR0x71/* Write any device register */
+
 /* Used for Micron flashes only. */
 #define SPINOR_OP_RD_EVCR  0x65/* Read EVCR register */
 #define SPINOR_OP_WD_EVCR  0x61/* Write EVCR register */
-- 
2.1.0.27.g96db324

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 3/4] mtd: spi-nor: fsl-quadspi: add support for layerscape

[Yuan Yao]

LS1043a and LS2080A in the Layerscape family also support Freescale Quad
SPI, make Quad SPI selectable for these hardwares.

Signed-off-by: Yuan Yao 
---
Changed in v2:
Update my email to 
---
 drivers/mtd/spi-nor/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index a28c278..6b53deb 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
-- 
2.1.0.27.g96db324

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 2/4] Documentation: fsl-quadspi: Add fsl, ls2080a-qspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao 
---
Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 6585ac7..2bef0dc 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -3,7 +3,7 @@
 Required properties:
   - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
-"fsl,ls1021-qspi"
+"fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
   - reg : the first contains the register location and length,
   the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

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[PATCH 4/4] Documentation: fsl-quadspi: Add optional properties

[Yuan Yao]

Add optional properties for QSPI:
big-endian
if the register is big endian on this platform.

Signed-off-by: Yuan Yao 
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 2bef0dc..1371612 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -19,6 +19,7 @@ Optional properties:
  But if there are two NOR flashes connected to the
  bus, you should enable this property.
  (Please check the board's schematic.)
+  - big-endian : That means the IP register is big endian
 
 Example:
 
-- 
2.1.0.27.g96db324

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[PATCH v2 1/4] Documentation: fsl-quadspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao 
---
Changed in v2:
Update my email to 
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..2fe51d6 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,8 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi", "fsl,ls2080a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

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[PATCH v3 1/4] mtd: spi-nor: fsl-quadspi: add big-endian support

[Yuan Yao]

Add R/W functions for big- or little-endian registers:
The qSPI controller's endian is independent of the CPU core's endian.
So far, the qSPI have two versions for big-endian and little-endian.

Signed-off-by: Yuan Yao 
---
Changed in v3:
Update my email to 

Changed in v2:
Rebase to the lastest code.
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++---
 1 file changed, 97 insertions(+), 60 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 54640f1..04e8a93 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -275,6 +275,7 @@ struct fsl_qspi {
u32 clk_rate;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
+   bool big_endian;
struct mutex lock;
struct pm_qos_request pm_qos_req;
 };
@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
*q)
 }
 
 /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+ * So far, although the CPU core is little-endian but the qSPI have two
+ * versions for big-endian and little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+   if (q->big_endian)
+   iowrite32be(val, addr);
+   else
+   iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+   if (q->big_endian)
+   return ioread32be(addr);
+   else
+   return ioread32(addr);
+}
+
+/*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
  */
@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
*q, u32 a)
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
*dev_id)
u32 reg;
 
/* clear interrupt */
-   reg = readl(q->iobase + QUADSPI_FR);
-   writel(reg, q->iobase + QUADSPI_FR);
+   reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+   qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
if (reg & QUADSPI_FR_TFF_MASK)
complete(>c);
@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
/* Clear all the LUT table */
for (i = 0; i < QUADSPI_LUT_NUM; i++)
-   writel(0, base + QUADSPI_LUT_BASE + i * 4);
+   qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
dummy = 8;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+   qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
 
/* Write enable */
lut_base = SEQID_WREN * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+   base + QUADSPI_LUT(lut_base));
 
/* Page Program */
lut_base = SEQID_PP * 4;
@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
addrlen = ADDR32BIT;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+   base + QUADSPI_LUT(lut_base + 1));
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
+   LUT1(FSL_READ, PAD1, 0x1),
 

[PATCH v2 2/4] mtd: spi-nor: fsl-quadspi: add support for ls1021a

[Yuan Yao]

LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.

Signed-off-by: Yuan Yao 
Acked-by: Han xu 
---
Changed in v2:
Update my email to 
---
 drivers/mtd/spi-nor/Kconfig   |  2 +-
 drivers/mtd/spi-nor/fsl-quadspi.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 0dc9275..a28c278 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 04e8a93..9ab2b51 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -213,6 +213,7 @@ enum fsl_qspi_devtype {
FSL_QUADSPI_IMX6SX,
FSL_QUADSPI_IMX7D,
FSL_QUADSPI_IMX6UL,
+   FSL_QUADSPI_LS1021A,
 };
 
 struct fsl_qspi_devtype_data {
@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6ul_data = {
   | QUADSPI_QUIRK_4X_INT_CLK,
 };
 
+static struct fsl_qspi_devtype_data ls1021a_data = {
+   .devtype = FSL_QUADSPI_LS1021A,
+   .rxfifo = 128,
+   .txfifo = 64,
+   .ahb_buf_size = 1024,
+   .driver_data = 0,
+};
+
 #define FSL_QSPI_MAX_CHIP  4
 struct fsl_qspi {
struct spi_nor nor[FSL_QSPI_MAX_CHIP];
@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
{ .compatible = "fsl,imx6sx-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx7d-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)_data, },
+   { .compatible = "fsl,ls1021a-qspi", .data = (void *)_data, },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
2.1.0.27.g96db324

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[PATCH v2 2/4] mtd: spi-nor: fsl-quadspi: add support for ls1021a

[Yuan Yao]

LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
Acked-by: Han xu <han...@freescale.com>
---
Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 drivers/mtd/spi-nor/Kconfig   |  2 +-
 drivers/mtd/spi-nor/fsl-quadspi.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 0dc9275..a28c278 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -30,7 +30,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 
 config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
-   depends on ARCH_MXC || COMPILE_TEST
+   depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
depends on HAS_IOMEM
help
  This enables support for the Quad SPI controller in master mode.
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 04e8a93..9ab2b51 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -213,6 +213,7 @@ enum fsl_qspi_devtype {
FSL_QUADSPI_IMX6SX,
FSL_QUADSPI_IMX7D,
FSL_QUADSPI_IMX6UL,
+   FSL_QUADSPI_LS1021A,
 };
 
 struct fsl_qspi_devtype_data {
@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6ul_data = {
   | QUADSPI_QUIRK_4X_INT_CLK,
 };
 
+static struct fsl_qspi_devtype_data ls1021a_data = {
+   .devtype = FSL_QUADSPI_LS1021A,
+   .rxfifo = 128,
+   .txfifo = 64,
+   .ahb_buf_size = 1024,
+   .driver_data = 0,
+};
+
 #define FSL_QSPI_MAX_CHIP  4
 struct fsl_qspi {
struct spi_nor nor[FSL_QSPI_MAX_CHIP];
@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
{ .compatible = "fsl,imx6sx-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx7d-qspi", .data = (void *)_data, },
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)_data, },
+   { .compatible = "fsl,ls1021a-qspi", .data = (void *)_data, },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
2.1.0.27.g96db324

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v3 1/4] mtd: spi-nor: fsl-quadspi: add big-endian support

[Yuan Yao]

Add R/W functions for big- or little-endian registers:
The qSPI controller's endian is independent of the CPU core's endian.
So far, the qSPI have two versions for big-endian and little-endian.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v3:
Update my email to <yao.y...@nxp.com>

Changed in v2:
Rebase to the lastest code.
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++---
 1 file changed, 97 insertions(+), 60 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 54640f1..04e8a93 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -275,6 +275,7 @@ struct fsl_qspi {
u32 clk_rate;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
+   bool big_endian;
struct mutex lock;
struct pm_qos_request pm_qos_req;
 };
@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
*q)
 }
 
 /*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+ * So far, although the CPU core is little-endian but the qSPI have two
+ * versions for big-endian and little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+   if (q->big_endian)
+   iowrite32be(val, addr);
+   else
+   iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+   if (q->big_endian)
+   return ioread32be(addr);
+   else
+   return ioread32(addr);
+}
+
+/*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
  */
@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi 
*q, u32 a)
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
 {
-   writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-   writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+   qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+   qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void 
*dev_id)
u32 reg;
 
/* clear interrupt */
-   reg = readl(q->iobase + QUADSPI_FR);
-   writel(reg, q->iobase + QUADSPI_FR);
+   reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+   qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
if (reg & QUADSPI_FR_TFF_MASK)
complete(>c);
@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
/* Clear all the LUT table */
for (i = 0; i < QUADSPI_LUT_NUM; i++)
-   writel(0, base + QUADSPI_LUT_BASE + i * 4);
+   qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
dummy = 8;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+   qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
 
/* Write enable */
lut_base = SEQID_WREN * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+   base + QUADSPI_LUT(lut_base));
 
/* Page Program */
lut_base = SEQID_PP * 4;
@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
addrlen = ADDR32BIT;
}
 
-   writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+   qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
-   writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+   base + QUADSPI_LUT(lut_base + 1));
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
+   LUT1(

[PATCH 4/4] Documentation: fsl-quadspi: Add optional properties

[Yuan Yao]

Add optional properties for QSPI:
big-endian
if the register is big endian on this platform.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 2bef0dc..1371612 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -19,6 +19,7 @@ Optional properties:
  But if there are two NOR flashes connected to the
  bus, you should enable this property.
  (Please check the board's schematic.)
+  - big-endian : That means the IP register is big endian
 
 Example:
 
-- 
2.1.0.27.g96db324

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To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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[PATCH v2 1/4] Documentation: fsl-quadspi: Add fsl,ls2080a-dspi compatible string

[Yuan Yao]

new compatible string: "fsl,ls2080a-qspi".

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt 
b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index fa77f87..2fe51d6 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,8 @@
 ARM Freescale DSPI controller
 
 Required properties:
-- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+   "fsl,ls2085a-dspi", "fsl,ls2080a-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
-- 
2.1.0.27.g96db324

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[PATCH v2 4/4] mtd: spi-nor: fsl-quadspi: extend support for some special requerment.

[Yuan Yao]

Add extra info in LUT table to support some special requerments.
Spansion S25FS-S family flash need some special operations.

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 41 +--
 include/linux/mtd/spi-nor.h   |  4 
 2 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
b/drivers/mtd/spi-nor/fsl-quadspi.c
index 9ab2b51..081ae85 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -205,6 +205,8 @@
 #define SEQID_RDCR 9
 #define SEQID_EN4B 10
 #define SEQID_BRWR 11
+#define SEQID_RDAR 12
+#define SEQID_WRAR 13
 
 #define QUADSPI_MIN_IOMAP SZ_4M
 
@@ -476,6 +478,28 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
base + QUADSPI_LUT(lut_base));
 
+   /*
+* Read any device register.
+* Used for Spansion S25FS-S family flash only.
+*/
+   lut_base = SEQID_RDAR * 4;
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
+   LUT1(ADDR, PAD1, ADDR24BIT),
+   base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
+   base + QUADSPI_LUT(lut_base + 1));
+
+   /*
+* Write any device register.
+* Used for Spansion S25FS-S family flash only.
+*/
+   lut_base = SEQID_WRAR * 4;
+   qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
+   LUT1(ADDR, PAD1, ADDR24BIT),
+   base + QUADSPI_LUT(lut_base));
+   qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
+   base + QUADSPI_LUT(lut_base + 1));
+
fsl_qspi_lock_lut(q);
 }
 
@@ -484,7 +508,12 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
 {
switch (cmd) {
case SPINOR_OP_READ_1_1_4:
+   case SPINOR_OP_READ4_1_1_4:
return SEQID_QUAD_READ;
+   case SPINOR_OP_SPANSION_RDAR:
+   return SEQID_RDAR;
+   case SPINOR_OP_SPANSION_WRAR:
+   return SEQID_WRAR;
case SPINOR_OP_WREN:
return SEQID_WREN;
case SPINOR_OP_WRDI:
@@ -835,8 +864,12 @@ static int fsl_qspi_read_reg(struct spi_nor *nor, u8 
opcode, u8 *buf, int len)
 {
int ret;
struct fsl_qspi *q = nor->priv;
+   u32 to = 0;
+
+   if (opcode == SPINOR_OP_SPANSION_RDAR)
+   memcpy(, nor->cmd_buf, 4);
 
-   ret = fsl_qspi_runcmd(q, opcode, 0, len);
+   ret = fsl_qspi_runcmd(q, opcode, to, len);
if (ret)
return ret;
 
@@ -848,9 +881,13 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 
opcode, u8 *buf, int len)
 {
struct fsl_qspi *q = nor->priv;
int ret;
+   u32 to = 0;
+
+   if (opcode == SPINOR_OP_SPANSION_RDAR)
+   memcpy(, nor->cmd_buf, 4);
 
if (!buf) {
-   ret = fsl_qspi_runcmd(q, opcode, 0, 1);
+   ret = fsl_qspi_runcmd(q, opcode, to, 1);
if (ret)
return ret;
 
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fac3f6f..7a2f193 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -74,6 +74,10 @@
 /* Used for Spansion flashes only. */
 #define SPINOR_OP_BRWR 0x17/* Bank register write */
 
+/* Used for Spansion S25FS-S family flash only. */
+#define SPINOR_OP_SPANSION_RDAR0x65/* Read any device register */
+#define SPINOR_OP_SPANSION_WRAR0x71/* Write any device register */
+
 /* Used for Micron flashes only. */
 #define SPINOR_OP_RD_EVCR  0x65/* Read EVCR register */
 #define SPINOR_OP_WD_EVCR  0x61/* Write EVCR register */
-- 
2.1.0.27.g96db324

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[PATCH v2 3/4] dts/ls2080a: update the DTS for QSPI and DSPI support

[Yuan Yao]

Signed-off-by: Yuan Yao <yao.y...@nxp.com>
---
Changed in v2:
Update my email to <yao.y...@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 9 -
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi| 4 ++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index 4cb996d..e8801fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -178,7 +178,14 @@
 
  {
status = "okay";
-   qflash0: s25fl008k {
+   flash0: s25fl256s1@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,m25p80";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+   flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index e81cd48..7a80666 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -250,7 +250,7 @@
 
dspi: dspi@210 {
status = "disabled";
-   compatible = "fsl,vf610-dspi";
+   compatible = "fsl,ls2085a-dspi", "fsl,ls2080a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x210 0x0 0x1>;
@@ -371,7 +371,7 @@
 
qspi: quadspi@20c {
status = "disabled";
-   compatible = "fsl,vf610-qspi";
+   compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c 0x0 0x1>,
-- 
2.1.0.27.g96db324

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