[PATCH 1/1] char: hpet: Remove unused local variable 'm' in hpet_interrupt()
Commit 273ef9509b79 ("drivers/char/hpet.c: fix periodic-emulation for
delayed interrupt") removed the reference to local variable 'm', but
forgot to remove the definition and assignment of it. Due to
read_counter() indirectly calls "read barrier", the performance is
slightly degraded.
Since the following comments give some description based on 'm', so move
the assignment of 'm' into it.
Fixes: 273ef9509b79 ("drivers/char/hpet.c: fix periodic-emulation for delayed
interrupt")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/char/hpet.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/char/hpet.c b/drivers/char/hpet.c
index ed3b7dab678dbd1..46950a0cda181a1 100644
--- a/drivers/char/hpet.c
+++ b/drivers/char/hpet.c
@@ -156,14 +156,16 @@ static irqreturn_t hpet_interrupt(int irq, void *data)
* This has the effect of treating non-periodic like periodic.
*/
if ((devp->hd_flags & (HPET_IE | HPET_PERIODIC)) == HPET_IE) {
- unsigned long m, t, mc, base, k;
+ unsigned long t, mc, base, k;
struct hpet __iomem *hpet = devp->hd_hpet;
struct hpets *hpetp = devp->hd_hpets;
t = devp->hd_ireqfreq;
- m = read_counter(>hd_timer->hpet_compare);
mc = read_counter(>hpet_mc);
- /* The time for the next interrupt would logically be t + m,
+ /*
+* m = read_counter(>hd_timer->hpet_compare);
+*
+* The time for the next interrupt would logically be t + m,
* however, if we are very unlucky and the interrupt is delayed
* for longer than t then we will completely miss the next
* interrupt if we set t + m and an application will hang.
--
2.26.0.106.g9fadedd
[PATCH 1/1] perf map: Fix error return code in maps__clone()
Although 'err' has been initialized to -ENOMEM, but it will be reassigned
by the "err = unwind__prepare_access(...)" statement in the for loop. So
that, the value of 'err' is unknown when map__clone() failed.
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
tools/perf/util/map.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c
index fbc40a2c17d4dca..8af693d9678cefe 100644
--- a/tools/perf/util/map.c
+++ b/tools/perf/util/map.c
@@ -840,15 +840,18 @@ int maps__fixup_overlappings(struct maps *maps, struct
map *map, FILE *fp)
int maps__clone(struct thread *thread, struct maps *parent)
{
struct maps *maps = thread->maps;
- int err = -ENOMEM;
+ int err;
struct map *map;
down_read(>lock);
maps__for_each_entry(parent, map) {
struct map *new = map__clone(map);
- if (new == NULL)
+
+ if (new == NULL) {
+ err = -ENOMEM;
goto out_unlock;
+ }
err = unwind__prepare_access(maps, new, NULL);
if (err)
--
2.26.0.106.g9fadedd
[PATCH 1/1] perf data: Fix error return code in perf_data__create_dir()
Although 'ret' has been initialized to -1, but it will be reassigned by
the "ret = open(...)" statement in the for loop. So that, the value of
'ret' is unknown when asprintf() failed.
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
tools/perf/util/data.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/tools/perf/util/data.c b/tools/perf/util/data.c
index f29af4fc3d09390..8fca4779ae6a8e9 100644
--- a/tools/perf/util/data.c
+++ b/tools/perf/util/data.c
@@ -35,7 +35,7 @@ void perf_data__close_dir(struct perf_data *data)
int perf_data__create_dir(struct perf_data *data, int nr)
{
struct perf_data_file *files = NULL;
- int i, ret = -1;
+ int i, ret;
if (WARN_ON(!data->is_dir))
return -EINVAL;
@@ -51,7 +51,8 @@ int perf_data__create_dir(struct perf_data *data, int nr)
for (i = 0; i < nr; i++) {
struct perf_data_file *file = [i];
- if (asprintf(>path, "%s/data.%d", data->path, i) < 0)
+ ret = asprintf(>path, "%s/data.%d", data->path, i);
+ if (ret < 0)
goto out_err;
ret = open(file->path, O_RDWR|O_CREAT|O_TRUNC, S_IRUSR|S_IWUSR);
--
2.26.0.106.g9fadedd
[PATCH 1/1] dt-bindings: serial: Add label property for pl011
When there is more than one pl011 serial port present, the label property
allows a custom name to be used for briefly describe the usage or position
of each serial port.
Without this "label" property, many dtbs_check warnings similar to the
following are reported:
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dt.yaml: \
serial@ffd74000: Additional properties are not allowed ('label' was unexpected)
From schema: Documentation/devicetree/bindings/serial/pl011.yaml
Signed-off-by: Zhen Lei
---
Documentation/devicetree/bindings/serial/pl011.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml
b/Documentation/devicetree/bindings/serial/pl011.yaml
index 1f8e9f2644b6b80..303c7746423f503 100644
--- a/Documentation/devicetree/bindings/serial/pl011.yaml
+++ b/Documentation/devicetree/bindings/serial/pl011.yaml
@@ -34,6 +34,9 @@ properties:
reg:
maxItems: 1
+ label:
+maxItems: 1
+
interrupts:
maxItems: 1
--
2.26.0.106.g9fadedd
[PATCH v3 0/2] clean up dt_binding_check and dtbs_check warnings of renesas,rsnd.yaml
v2 --> v3: Modified based on Rob's review comments. For example, "ports" and "port" are not allowed at the same time. For the details, please refer: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg2539753.html v1 --> v2: The analysis was not clear in the previous version, "$ref: audio-graph.yaml#" is not required. It was then adjusted based on the following patch series: [1] https://lore.kernel.org/r/20210323163634.877511-1-r...@kernel.org/ v1: When I do dt_binding_check for all YAML files, below warning is reported: /root/mainline/Documentation/devicetree/bindings/sound/renesas,rsnd.example.dt.yaml: sound@ec50: 'dais' is a required property From schema: /root/mainline/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml make dt_binding_check -j24 2>err.txt Before: cat err.txt | wc -l 2 After: cat err.txt | wc -l 0 make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/renesas,rsnd.yaml -j24 2>err.txt Before: cat err.txt | wc -l 130 After: cat err.txt | wc -l 0 Zhen Lei (2): ASoC: dt-bindings: renesas, rsnd: Clear warning 'dais' is a required property ASoC: dt-bindings: renesas, rsnd: Clear warning 'ports' does not match any of the regexes .../devicetree/bindings/sound/renesas,rsnd.yaml | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) -- 2.26.0.106.g9fadedd
[PATCH v3 2/2] ASoC: dt-bindings: renesas, rsnd: Clear warning 'ports' does not match any of the regexes
Currently, if there are more than two ports, or if there is only one port but other properties(such as "#address-cells") is required, these ports are placed under the "ports" node. So add the schema of property "ports". Otherwise, warnings similar to the following will be reported: arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dt.yaml: \ sound@ec50: 'ports' does not match any of the regexes: \ '^rcar_sound,ctu$', '^rcar_sound,dai$', '^rcar_sound,dvc$', ... A given binding should just use 'ports' or 'port' depending on it's need. Both are not allowed at the same time. The check is done in "allOf". Signed-off-by: Zhen Lei --- .../devicetree/bindings/sound/renesas,rsnd.yaml | 12 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml index 384191ee497f534..32b10fc3789eeac 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml @@ -115,6 +115,12 @@ properties: $ref: audio-graph-port.yaml# unevaluatedProperties: false + ports: +$ref: /schemas/graph.yaml#/properties/ports +patternProperties: + '^port@[0-9]': +$ref: audio-graph-port.yaml# + # use patternProperties to avoid naming "xxx,yyy" issue patternProperties: "^rcar_sound,dvc$": @@ -258,6 +264,12 @@ required: - "#sound-dai-cells" allOf: + - if: + required: +- ports +then: + properties: +port: false - if: properties: compatible: -- 2.26.0.106.g9fadedd
[PATCH v3 1/2] ASoC: dt-bindings: renesas, rsnd: Clear warning 'dais' is a required property
When I do dt_binding_check, below warning is reported: Documentation/devicetree/bindings/sound/renesas,rsnd.example.dt.yaml: \ sound@ec50: 'dais' is a required property I looked at all the dts files in the "arch/arm64/boot/dts/renesas/" directory. However, the dts node of this driver does not reference any property in file audio-graph.yaml. This can be proved to be true, because after I deleted "$ref: audio-graph.yaml#", the old 'dais' warnings are cleared, and no new warning are generated. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/sound/renesas,rsnd.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml index 1e0e14e889133b8..384191ee497f534 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml @@ -258,7 +258,6 @@ required: - "#sound-dai-cells" allOf: - - $ref: audio-graph.yaml# - if: properties: compatible: -- 2.26.0.106.g9fadedd
[PATCH 1/1] lib/lzo: remove unused local variable 'level'
Fixes the following W=1 kernel build warning:
lib/decompress_unlzo.c: In function ‘parse_header’:
lib/decompress_unlzo.c:46:5: warning: variable ‘level’ set but not used
[-Wunused-but-set-variable]
Fixes: 7dd65feb6c60 ("lib: add support for LZO-compressed kernels")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
lib/decompress_unlzo.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/lib/decompress_unlzo.c b/lib/decompress_unlzo.c
index 1f439a622076c10..64c1358500ce4e9 100644
--- a/lib/decompress_unlzo.c
+++ b/lib/decompress_unlzo.c
@@ -43,7 +43,6 @@ STATIC inline long INIT parse_header(u8 *input, long *skip,
long in_len)
int l;
u8 *parse = input;
u8 *end = input + in_len;
- u8 level = 0;
u16 version;
/*
@@ -65,7 +64,7 @@ STATIC inline long INIT parse_header(u8 *input, long *skip,
long in_len)
version = get_unaligned_be16(parse);
parse += 7;
if (version >= 0x0940)
- level = *parse++;
+ parse++;
if (get_unaligned_be32(parse) & HEADER_HAS_FILTER)
parse += 8; /* flags + filter info */
else
--
2.26.0.106.g9fadedd
[PATCH 0/3] scsi: mptfusion: Clear the warnings indicating that the variable is not used
Fix below warnings: drivers/message/fusion/mptctl.c: In function ‘mptctl_do_taskmgmt’: drivers/message/fusion/mptctl.c:324:17: warning: variable ‘time_count’ set but not used [-Wunused-but-set-variable] 324 | unsigned long time_count; | ^~ drivers/message/fusion/mptctl.c: In function ‘mptctl_gettargetinfo’: drivers/message/fusion/mptctl.c:1372:7: warning: variable ‘port’ set but not used [-Wunused-but-set-variable] 1372 | u8 port; | ^~~~ drivers/message/fusion/mptctl.c: In function ‘mptctl_hp_hostinfo’: drivers/message/fusion/mptctl.c:2337:8: warning: variable ‘retval’ set but not used [-Wunused-but-set-variable] 2337 | int retval; |^~ Zhen Lei (3): scsi: mptfusion: Remove unused local variable 'time_count' scsi: mptfusion: Remove unused local variable 'port' scsi: mptfusion: Fix error return code of mptctl_hp_hostinfo() drivers/message/fusion/mptctl.c | 28 1 file changed, 12 insertions(+), 16 deletions(-) -- 2.21.1
[PATCH 1/3] scsi: mptfusion: Remove unused local variable 'time_count'
Fixes the following W=1 kernel build warning:
drivers/message/fusion/mptctl.c: In function ‘mptctl_do_taskmgmt:
drivers/message/fusion/mptctl.c:324:17: warning: variable ‘time_count’ set but
not used [-Wunused-but-set-variable]
Fixes: 7d757f185540 ("[SCSI] mptfusion: Updated SCSI IO IOCTL error handling.")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/message/fusion/mptctl.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/message/fusion/mptctl.c b/drivers/message/fusion/mptctl.c
index 24aebad60366..0a9321239e76 100644
--- a/drivers/message/fusion/mptctl.c
+++ b/drivers/message/fusion/mptctl.c
@@ -321,7 +321,6 @@ mptctl_do_taskmgmt(MPT_ADAPTER *ioc, u8 tm_type, u8 bus_id,
u8 target_id)
int ii;
int retval;
unsigned longtimeout;
- unsigned longtime_count;
u16 iocstatus;
@@ -383,7 +382,6 @@ mptctl_do_taskmgmt(MPT_ADAPTER *ioc, u8 tm_type, u8 bus_id,
u8 target_id)
ioc->name, tm_type, timeout));
INITIALIZE_MGMT_STATUS(ioc->taskmgmt_cmds.status)
- time_count = jiffies;
if ((ioc->facts.IOCCapabilities & MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q) &&
(ioc->facts.MsgVersion >= MPI_VERSION_01_05))
mpt_put_msg_frame_hi_pri(mptctl_taskmgmt_id, ioc, mf);
--
2.21.1
[PATCH 2/3] scsi: mptfusion: Remove unused local variable 'port'
Fixes the following W=1 kernel build warning:
drivers/message/fusion/mptctl.c: In function ‘mptctl_gettargetinfo
drivers/message/fusion/mptctl.c:1372:7: warning: variable ‘port’ set but not
used [-Wunused-but-set-variable]
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/message/fusion/mptctl.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/message/fusion/mptctl.c b/drivers/message/fusion/mptctl.c
index 0a9321239e76..72025996cd70 100644
--- a/drivers/message/fusion/mptctl.c
+++ b/drivers/message/fusion/mptctl.c
@@ -1367,7 +1367,6 @@ mptctl_gettargetinfo (MPT_ADAPTER *ioc, unsigned long arg)
int lun;
int maxWordsLeft;
int numBytes;
- u8 port;
struct scsi_device *sdev;
if (copy_from_user(, uarg, sizeof(struct mpt_ioctl_targetinfo))) {
@@ -1379,13 +1378,8 @@ mptctl_gettargetinfo (MPT_ADAPTER *ioc, unsigned long
arg)
dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mptctl_gettargetinfo
called.\n",
ioc->name));
- /* Get the port number and set the maximum number of bytes
-* in the returned structure.
-* Ignore the port setting.
-*/
numBytes = karg.hdr.maxDataSize - sizeof(mpt_ioctl_header);
maxWordsLeft = numBytes/sizeof(int);
- port = karg.hdr.port;
if (maxWordsLeft <= 0) {
printk(MYIOC_s_ERR_FMT "%s@%d::mptctl_gettargetinfo() - no
memory available!\n",
--
2.21.1
[PATCH 3/3] scsi: mptfusion: Fix error return code of mptctl_hp_hostinfo()
Ensure that all "goto out" error branches return correct error codes.
Currently, always returns 0.
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/message/fusion/mptctl.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/message/fusion/mptctl.c b/drivers/message/fusion/mptctl.c
index 72025996cd70..57bf511245b6 100644
--- a/drivers/message/fusion/mptctl.c
+++ b/drivers/message/fusion/mptctl.c
@@ -2326,7 +2326,7 @@ mptctl_hp_hostinfo(MPT_ADAPTER *ioc, unsigned long arg,
unsigned int data_size)
ToolboxIstwiReadWriteRequest_t *IstwiRWRequest;
MPT_FRAME_HDR *mf = NULL;
unsigned long timeleft;
- int retval;
+ int retval = 0;
u32 msgcontext;
/* Reset long to int. Should affect IA64 and SPARC only
@@ -2453,6 +2453,7 @@ mptctl_hp_hostinfo(MPT_ADAPTER *ioc, unsigned long arg,
unsigned int data_size)
if ((mf = mpt_get_msg_frame(mptctl_id, ioc)) == NULL) {
dfailprintk(ioc, printk(MYIOC_s_WARN_FMT
"%s, no msg frames!!\n", ioc->name, __func__));
+ retval = -EFAULT;
goto out;
}
@@ -2471,12 +2472,13 @@ mptctl_hp_hostinfo(MPT_ADAPTER *ioc, unsigned long arg,
unsigned int data_size)
IstwiRWRequest->DeviceAddr = 0xB0;
pbuf = pci_alloc_consistent(ioc->pcidev, 4, _dma);
- if (!pbuf)
+ if (!pbuf) {
+ retval = -ENOMEM;
goto out;
+ }
ioc->add_sge((char *)>SGL,
(MPT_SGE_FLAGS_SSIMPLE_READ|4), buf_dma);
- retval = 0;
SET_MGMT_MSG_CONTEXT(ioc->ioctl_cmds.msg_context,
IstwiRWRequest->MsgContext);
INITIALIZE_MGMT_STATUS(ioc->ioctl_cmds.status)
@@ -2486,10 +2488,10 @@ mptctl_hp_hostinfo(MPT_ADAPTER *ioc, unsigned long arg,
unsigned int data_size)
timeleft = wait_for_completion_timeout(>ioctl_cmds.done,
HZ*MPT_IOCTL_DEFAULT_TIMEOUT);
if (!(ioc->ioctl_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
- retval = -ETIME;
printk(MYIOC_s_WARN_FMT "%s: failed\n", ioc->name, __func__);
if (ioc->ioctl_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) {
mpt_free_msg_frame(ioc, mf);
+ retval = -ETIME;
goto out;
}
if (!timeleft) {
@@ -2497,9 +2499,11 @@ mptctl_hp_hostinfo(MPT_ADAPTER *ioc, unsigned long arg,
unsigned int data_size)
"HOST INFO command timeout, doorbell=0x%08x\n",
ioc->name, mpt_GetIocState(ioc, 0));
mptctl_timeout_expired(ioc, mf);
- } else
- goto retry_wait;
- goto out;
+ retval = -ETIME;
+ goto out;
+ }
+
+ goto retry_wait;
}
/*
@@ -2530,7 +2534,7 @@ mptctl_hp_hostinfo(MPT_ADAPTER *ioc, unsigned long arg,
unsigned int data_size)
return -EFAULT;
}
- return 0;
+ return retval;
}
--
2.21.1
[PATCH 1/1] agp: remove unused local variable 'current_size'
Fixes the following W=1 kernel build warning:
drivers/char/agp/via-agp.c: In function ‘via_configure_agp3’:
drivers/char/agp/via-agp.c:131:28: warning: variable ‘current_size’ set but not
used [-Wunused-but-set-variable]
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/char/agp/via-agp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c
index 87a92a044570e0b..dc594f4eca38aab 100644
--- a/drivers/char/agp/via-agp.c
+++ b/drivers/char/agp/via-agp.c
@@ -128,9 +128,6 @@ static int via_fetch_size_agp3(void)
static int via_configure_agp3(void)
{
u32 temp;
- struct aper_size_info_16 *current_size;
-
- current_size = A_SIZE_16(agp_bridge->current_size);
/* address to map to */
agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
--
1.8.3
[PATCH 1/1] ide: remove unused local variable 'sitre'
Fixes the following W=1 kernel build warning:
drivers/ide/piix.c: In function ‘piix_set_dma_mode’:
drivers/ide/piix.c:146:8: warning: variable ‘sitre’ set but not used
[-Wunused-but-set-variable]
Fixes: 2bfba3c444fe ("ide: remove useless subdirs from drivers/ide/")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/ide/piix.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/ide/piix.c b/drivers/ide/piix.c
index a671cead6ae72b7..b512d2dc9108cf6 100644
--- a/drivers/ide/piix.c
+++ b/drivers/ide/piix.c
@@ -143,13 +143,11 @@ static void piix_set_dma_mode(ide_hwif_t *hwif,
ide_drive_t *drive)
int v_flag = 0x01 << drive->dn;
int w_flag = 0x10 << drive->dn;
int u_speed = 0;
- int sitre;
u16 reg4042, reg4a;
u8 reg48, reg54, reg55;
const u8 speed = drive->dma_mode;
pci_read_config_word(dev, maslave, );
- sitre = (reg4042 & 0x4000) ? 1 : 0;
pci_read_config_byte(dev, 0x48, );
pci_read_config_word(dev, 0x4a, );
pci_read_config_byte(dev, 0x54, );
--
1.8.3
[PATCH 1/1] drm/nouveau/kms: remove unused local variable 'width'
Fixes the following W=1 kernel build warning:
drivers/gpu/drm/nouveau/nouveau_display.c: In function
‘nouveau_framebuffer_new’:
drivers/gpu/drm/nouveau/nouveau_display.c:309:15: warning: variable ‘width’ set
but not used [-Wunused-but-set-variable]
Fixes: 4f5746c863db ("drm/nouveau/kms: Check framebuffer size against bo")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/gpu/drm/nouveau/nouveau_display.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c
b/drivers/gpu/drm/nouveau/nouveau_display.c
index 17831ee897ea46d..7d3b1f8de300784 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -306,7 +306,7 @@
struct nouveau_bo *nvbo = nouveau_gem_object(gem);
struct drm_framebuffer *fb;
const struct drm_format_info *info;
- unsigned int width, height, i;
+ unsigned int height, i;
uint32_t tile_mode;
uint8_t kind;
int ret;
@@ -346,9 +346,6 @@
info = drm_get_format_info(dev, mode_cmd);
for (i = 0; i < info->num_planes; i++) {
- width = drm_format_info_plane_width(info,
- mode_cmd->width,
- i);
height = drm_format_info_plane_height(info,
mode_cmd->height,
i);
--
1.8.3
[PATCH 1/1] ide: remove unused static variable 'ide_media_proc_fops'
Fixes the following W=1 kernel build warning:
drivers/ide/ide-proc.c:457:37: warning: ‘ide_media_proc_fops’ defined but not
used [-Wunused-const-variable=]
The reference to the variable 'ide_media_proc_fops' is deleted by
commit ec7d9c9ce897 ("ide: replace ->proc_fops with ->proc_show").
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/ide/ide-proc.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/ide/ide-proc.c b/drivers/ide/ide-proc.c
index 15c17f3781ee917..34bed14f88c78b3 100644
--- a/drivers/ide/ide-proc.c
+++ b/drivers/ide/ide-proc.c
@@ -449,19 +449,6 @@ static int ide_media_proc_show(struct seq_file *m, void *v)
return 0;
}
-static int ide_media_proc_open(struct inode *inode, struct file *file)
-{
- return single_open(file, ide_media_proc_show, PDE_DATA(inode));
-}
-
-static const struct file_operations ide_media_proc_fops = {
- .owner = THIS_MODULE,
- .open = ide_media_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release= single_release,
-};
-
static ide_proc_entry_t generic_drive_entries[] = {
{ "driver", S_IFREG|S_IRUGO, ide_driver_proc_show },
{ "identify", S_IFREG|S_IRUSR, ide_identify_proc_show },
--
1.8.3
[PATCH 1/1] usb: typec: tcpm: remove unused static variable 'tcpm_altmode_ops'
Fixes the following W=1 kernel build warning:
drivers/usb/typec/tcpm/tcpm.c:2107:39: warning: ‘tcpm_altmode_ops’ defined but
not used [-Wunused-const-variable=]
The reference to the variable 'tcpm_altmode_ops' is deleted by the
commit a079973f462a ("usb: typec: tcpm: Remove tcpc_config configuration
mechanism").
By the way, the static functions referenced only by the variable
'tcpm_altmode_ops' are deleted accordingly.
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/usb/typec/tcpm/tcpm.c | 60 ---
1 file changed, 60 deletions(-)
diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
index ce7af398c7c1c1f..2f89bae29c0c297 100644
--- a/drivers/usb/typec/tcpm/tcpm.c
+++ b/drivers/usb/typec/tcpm/tcpm.c
@@ -1365,14 +1365,6 @@ static void tcpm_queue_vdm(struct tcpm_port *port, const
u32 header,
mod_vdm_delayed_work(port, 0);
}
-static void tcpm_queue_vdm_unlocked(struct tcpm_port *port, const u32 header,
- const u32 *data, int cnt)
-{
- mutex_lock(>lock);
- tcpm_queue_vdm(port, header, data, cnt);
- mutex_unlock(>lock);
-}
-
static void svdm_consume_identity(struct tcpm_port *port, const u32 *p, int
cnt)
{
u32 vdo = p[VDO_INDEX_IDH];
@@ -1705,8 +1697,6 @@ static void tcpm_handle_vdm_request(struct tcpm_port
*port,
*
* And we also have this ordering:
* 1. alt-mode driver takes the alt-mode's lock
-* 2. alt-mode driver calls tcpm_altmode_enter which takes the
-*tcpm port lock
*
* Dropping our lock here avoids this.
*/
@@ -2060,56 +2050,6 @@ static int tcpm_validate_caps(struct tcpm_port *port,
const u32 *pdo,
return 0;
}
-static int tcpm_altmode_enter(struct typec_altmode *altmode, u32 *vdo)
-{
- struct tcpm_port *port = typec_altmode_get_drvdata(altmode);
- int svdm_version;
- u32 header;
-
- svdm_version = typec_get_negotiated_svdm_version(port->typec_port);
- if (svdm_version < 0)
- return svdm_version;
-
- header = VDO(altmode->svid, vdo ? 2 : 1, svdm_version, CMD_ENTER_MODE);
- header |= VDO_OPOS(altmode->mode);
-
- tcpm_queue_vdm_unlocked(port, header, vdo, vdo ? 1 : 0);
- return 0;
-}
-
-static int tcpm_altmode_exit(struct typec_altmode *altmode)
-{
- struct tcpm_port *port = typec_altmode_get_drvdata(altmode);
- int svdm_version;
- u32 header;
-
- svdm_version = typec_get_negotiated_svdm_version(port->typec_port);
- if (svdm_version < 0)
- return svdm_version;
-
- header = VDO(altmode->svid, 1, svdm_version, CMD_EXIT_MODE);
- header |= VDO_OPOS(altmode->mode);
-
- tcpm_queue_vdm_unlocked(port, header, NULL, 0);
- return 0;
-}
-
-static int tcpm_altmode_vdm(struct typec_altmode *altmode,
- u32 header, const u32 *data, int count)
-{
- struct tcpm_port *port = typec_altmode_get_drvdata(altmode);
-
- tcpm_queue_vdm_unlocked(port, header, data, count - 1);
-
- return 0;
-}
-
-static const struct typec_altmode_ops tcpm_altmode_ops = {
- .enter = tcpm_altmode_enter,
- .exit = tcpm_altmode_exit,
- .vdm = tcpm_altmode_vdm,
-};
-
/*
* PD (data, control) command handling functions
*/
--
1.8.3
[PATCH 1/1] drm/msm/dpu: remove unused local variable 'cmd_enc'
Fixes the following W=1 kernel build warning:
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c: In function
‘dpu_encoder_phys_cmd_wait_for_commit_done’:
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c:688:31: warning: variable
‘cmd_enc’ set but not used [-Wunused-but-set-variable]
Fixes: fe286893ed34 ("drm/msm/dpu: Remove unused call in wait_for_commit_done")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index b2be39b9144e449..088900841bf8baa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -685,10 +685,6 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete(
static int dpu_encoder_phys_cmd_wait_for_commit_done(
struct dpu_encoder_phys *phys_enc)
{
- struct dpu_encoder_phys_cmd *cmd_enc;
-
- cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
-
/* only required for master controller */
if (!dpu_encoder_phys_cmd_is_master(phys_enc))
return 0;
--
1.8.3
[PATCH 1/1] drm/msm/dp: remove unused local variable 'hpd'
Fixes the following W=1 kernel build warning:
drivers/gpu/drm/msm/dp/dp_display.c: In function
‘dp_display_usbpd_attention_cb’:
drivers/gpu/drm/msm/dp/dp_display.c:496:19: warning: variable ‘hpd’ set but not
used [-Wunused-but-set-variable]
Fixes: c58eb1b54fee ("drm/msm/dp: fix connect/disconnect handled at irq_hpd")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/gpu/drm/msm/dp/dp_display.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 5a39da6e1eaf277..31bf2a40a9eb2c9 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -493,7 +493,6 @@ static int dp_display_usbpd_attention_cb(struct device *dev)
int rc = 0;
u32 sink_request;
struct dp_display_private *dp;
- struct dp_usbpd *hpd;
if (!dev) {
DRM_ERROR("invalid dev\n");
@@ -507,8 +506,6 @@ static int dp_display_usbpd_attention_cb(struct device *dev)
return -ENODEV;
}
- hpd = dp->usbpd;
-
/* check for any test request issued by sink */
rc = dp_link_process_request(dp->link);
if (!rc) {
--
1.8.3
[PATCH 1/1] agp/uninorth: remove unused local variable 'size'
Fixes the following W=1 kernel build warning:
drivers/char/agp/uninorth-agp.c: In function ‘uninorth_create_gatt_table:
drivers/char/agp/uninorth-agp.c:372:6: warning: variable ‘size’ set but not
used [-Wunused-but-set-variable]
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/char/agp/uninorth-agp.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c
index 62de7f4ba864368..e250a8452a4c4e5 100644
--- a/drivers/char/agp/uninorth-agp.c
+++ b/drivers/char/agp/uninorth-agp.c
@@ -369,7 +369,6 @@ static int uninorth_create_gatt_table(struct
agp_bridge_data *bridge)
{
char *table;
char *table_end;
- int size;
int page_order;
int num_entries;
int i;
@@ -383,10 +382,9 @@ static int uninorth_create_gatt_table(struct
agp_bridge_data *bridge)
table = NULL;
i = bridge->aperture_size_idx;
temp = bridge->current_size;
- size = page_order = num_entries = 0;
+ page_order = num_entries = 0;
do {
- size = A_SIZE_32(temp)->size;
page_order = A_SIZE_32(temp)->page_order;
num_entries = A_SIZE_32(temp)->num_entries;
--
1.8.3
[PATCH v2 0/1] thermal: ti-soc-thermal: Remove duplicated header file inclusion
v1 --> v2: Arrange all included header files in alphabetical order. Zhen Lei (1): thermal: ti-soc-thermal: Remove duplicated header file inclusion drivers/thermal/ti-soc-thermal/ti-bandgap.c | 35 ++--- 1 file changed, 17 insertions(+), 18 deletions(-) -- 1.8.3
[PATCH v2 1/1] thermal: ti-soc-thermal: Remove duplicated header file inclusion
Delete one of the header files that are included twice, all included header files are then rearranged alphabetically. Signed-off-by: Zhen Lei --- drivers/thermal/ti-soc-thermal/ti-bandgap.c | 35 ++--- 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/thermal/ti-soc-thermal/ti-bandgap.c b/drivers/thermal/ti-soc-thermal/ti-bandgap.c index 8a3646e26ddd208..5e7e80b4a8171c4 100644 --- a/drivers/thermal/ti-soc-thermal/ti-bandgap.c +++ b/drivers/thermal/ti-soc-thermal/ti-bandgap.c @@ -9,30 +9,29 @@ * Eduardo Valentin */ -#include +#include +#include +#include +#include #include +#include #include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include #include -#include -#include -#include -#include -#include +#include +#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include "ti-bandgap.h" -- 1.8.3
[PATCH v2 1/1] pinctrl: Remove duplicated header file inclusion
Delete one of the header files that are included twice, all included header files are then rearranged alphabetically. Signed-off-by: Zhen Lei --- drivers/pinctrl/pinctrl-k210.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index 8a733cf77ba0522..8670c8cd0e387c8 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -3,19 +3,18 @@ * Copyright (C) 2020 Sean Anderson * Copyright (c) 2020 Western Digital Corporation or its affiliates. */ -#include -#include +#include #include +#include #include +#include +#include +#include +#include +#include #include -#include #include #include -#include -#include -#include -#include -#include #include -- 1.8.3
[PATCH v2 0/1] pinctrl: Remove duplicated header file inclusion
v1 --> v2: Arrange all included header files in alphabetical order. Zhen Lei (1): pinctrl: Remove duplicated header file inclusion drivers/pinctrl/pinctrl-k210.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) -- 1.8.3
[PATCH v2 1/1] drm/nouveau/dmem: Remove duplicated header file inclusion
Delete one of the header files that are included twice, all included header files are then rearranged alphabetically. Signed-off-by: Zhen Lei --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 27 --- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 92987daa5e17d02..8e7a1b6598e0659 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -19,26 +19,23 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include "nouveau_dmem.h" -#include "nouveau_drv.h" -#include "nouveau_chan.h" -#include "nouveau_dma.h" -#include "nouveau_mem.h" -#include "nouveau_bo.h" -#include "nouveau_svm.h" - +#include +#include +#include #include -#include -#include #include #include #include -#include - -#include +#include +#include -#include -#include +#include "nouveau_bo.h" +#include "nouveau_chan.h" +#include "nouveau_dma.h" +#include "nouveau_dmem.h" +#include "nouveau_drv.h" +#include "nouveau_mem.h" +#include "nouveau_svm.h" /* * FIXME: this is ugly right now we are using TTM to allocate vram and we pin -- 1.8.3
[PATCH v2 0/1] drm/nouveau/dmem: Remove duplicated header file
v1 --> v2: Arrange all included header files in alphabetical order. Zhen Lei (1): drm/nouveau/dmem: Remove duplicated header file inclusion drivers/gpu/drm/nouveau/nouveau_dmem.c | 27 --- 1 file changed, 12 insertions(+), 15 deletions(-) -- 1.8.3
[PATCH v2 1/1] net/mlx5: Remove duplicated header file inclusion
Delete one of the header files "esw/indir_table.h" that are included twice, all included header files are then rearranged alphabetically. Signed-off-by: Zhen Lei --- drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 8694b83968b4c4f..e8307f5eae4cb6a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -33,21 +33,20 @@ #include #include #include +#include #include #include -#include -#include "mlx5_core.h" -#include "eswitch.h" -#include "esw/indir_table.h" +#include "en.h" +#include "en_tc.h" #include "esw/acl/ofld.h" #include "esw/indir_table.h" -#include "rdma.h" -#include "en.h" +#include "eswitch.h" #include "fs_core.h" #include "lib/devcom.h" #include "lib/eq.h" #include "lib/fs_chains.h" -#include "en_tc.h" +#include "mlx5_core.h" +#include "rdma.h" /* There are two match-all miss flows, one for unicast dst mac and * one for multicast. -- 1.8.3
[PATCH v2 0/1] net/mlx5: Remove duplicated header file inclusion
v1 --> v2: Arrange all included header files in alphabetical order. Zhen Lei (1): net/mlx5: Remove duplicated header file inclusion drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) -- 1.8.3
[PATCH v2 0/1] bus: bt1-apb: Remove duplicated header file inclusion
v1 --> v2: Arrange all included header files in alphabetical order. Zhen Lei (1): bus: bt1-apb: Remove duplicated header file inclusion drivers/bus/bt1-apb.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) -- 1.8.3
[PATCH v2 1/1] bus: bt1-apb: Remove duplicated header file inclusion
Delete one of the header files that are included twice, all included header files are then rearranged alphabetically. Signed-off-by: Zhen Lei --- drivers/bus/bt1-apb.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/bus/bt1-apb.c b/drivers/bus/bt1-apb.c index b25ff941e7c7f52..f7d3d2851a6cc48 100644 --- a/drivers/bus/bt1-apb.c +++ b/drivers/bus/bt1-apb.c @@ -8,22 +8,21 @@ * Baikal-T1 APB-bus driver */ -#include -#include -#include -#include #include -#include +#include +#include #include #include +#include +#include #include #include +#include #include -#include #include -#include -#include #include +#include +#include #define APB_EHB_ISR0x00 #define APB_EHB_ISR_PENDINGBIT(0) -- 1.8.3
[PATCH v2 0/2] clean up dt_binding_check and dtbs_check warnings of renesas,rsnd.yaml
It was then adjusted based on the following patch series: [1] https://lore.kernel.org/r/20210323163634.877511-1-r...@kernel.org/ v1: When I do dt_binding_check for all YAML files, below warning is reported: /root/mainline/Documentation/devicetree/bindings/sound/renesas,rsnd.example.dt.yaml: sound@ec50: 'dais' is a required property From schema: /root/mainline/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml make dt_binding_check -j24 2>err.txt Before: cat err.txt | wc -l 2 After: cat err.txt | wc -l 0 make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/renesas,rsnd.yaml -j24 2>err.txt Before: cat err.txt | wc -l 130 After: cat err.txt | wc -l 0 Zhen Lei (2): ASoC: dt-bindings: renesas, rsnd: Clear warning 'dais' is a required property ASoC: dt-bindings: renesas, rsnd: Clear warning 'ports' does not match any of the regexes Documentation/devicetree/bindings/sound/renesas,rsnd.yaml | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) -- 1.8.3
[PATCH v2 2/2] ASoC: dt-bindings: renesas, rsnd: Clear warning 'ports' does not match any of the regexes
Currently, if there are more than two ports, or if there is only one port but other properties(such as "#address-cells") is required, these ports are placed under the "ports" node. So add the schema of property "ports". Otherwise, warnings similar to the following will be reported: arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dt.yaml: \ sound@ec50: 'ports' does not match any of the regexes: \ '^rcar_sound,ctu$', '^rcar_sound,dai$', '^rcar_sound,dvc$', ... Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/sound/renesas,rsnd.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml index 384191ee497f534..a42992fa687d3f3 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml @@ -115,6 +115,11 @@ properties: $ref: audio-graph-port.yaml# unevaluatedProperties: false + ports: +patternProperties: + '^port@[0-9]': +$ref: "#/properties/port" + # use patternProperties to avoid naming "xxx,yyy" issue patternProperties: "^rcar_sound,dvc$": -- 1.8.3
[PATCH v2 1/2] ASoC: dt-bindings: renesas, rsnd: Clear warning 'dais' is a required property
When I do dt_binding_check, below warning is reported: Documentation/devicetree/bindings/sound/renesas,rsnd.example.dt.yaml: \ sound@ec50: 'dais' is a required property I looked at all the dts files in the "arch/arm64/boot/dts/renesas/" directory. However, the dts node of this driver does not reference any property in file audio-graph.yaml. This can be proved to be true, because after I deleted "$ref: audio-graph.yaml#", the old 'dais' warnings are cleared, and no new warning are generated. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/sound/renesas,rsnd.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml index 1e0e14e889133b8..384191ee497f534 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml @@ -258,7 +258,6 @@ required: - "#sound-dai-cells" allOf: - - $ref: audio-graph.yaml# - if: properties: compatible: -- 1.8.3
[PATCH 2/2] ASoC: dt-bindings: renesas, rsnd: Clear warning 'ports' does not match any of the regexes
Currently, the property "ports" is always present. So mark it as true, and let audio-graph-card.yaml to check it. Otherwise, warnings similar to the following will be reported: arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dt.yaml: \ sound@ec50: 'ports' does not match any of the regexes: \ '^rcar_sound,ctu$', '^rcar_sound,dai$', '^rcar_sound,dvc$', ... Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/sound/renesas,rsnd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml index 487aeabd1f0e65b..d3c2899843aee58 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml @@ -112,6 +112,7 @@ properties: - pattern: '^clk_(a|b|c|i)$' port: true + ports: true # use patternProperties to avoid naming "xxx,yyy" issue patternProperties: -- 1.8.3
[PATCH 0/2] clean up dt_binding_check and dtbs_check warnings of renesas,rsnd.yaml
When I do dt_binding_check for all YAML files, below warning is reported: /root/mainline/Documentation/devicetree/bindings/sound/renesas,rsnd.example.dt.yaml: sound@ec50: 'dais' is a required property From schema: /root/mainline/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml make dt_binding_check -j24 2>err.txt Before: cat err.txt | wc -l 2 After: cat err.txt | wc -l 0 make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/renesas,rsnd.yaml -j24 2>err.txt Before: cat err.txt | wc -l 130 After: cat err.txt | wc -l 0 Zhen Lei (2): ASoC: dt-bindings: renesas, rsnd: Clear warning 'dais' is a required property ASoC: dt-bindings: renesas, rsnd: Clear warning 'ports' does not match any of the regexes Documentation/devicetree/bindings/sound/renesas,rsnd.yaml | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) -- 1.8.3
[PATCH 1/2] ASoC: dt-bindings: renesas, rsnd: Clear warning 'dais' is a required property
When I do dt_binding_check, below warning is reported: Documentation/devicetree/bindings/sound/renesas,rsnd.example.dt.yaml: \ sound@ec50: 'dais' is a required property I looked at all the dts files in the "arch/arm64/boot/dts/renesas/" directory, I found that all nodes that contain the "dais" property have compatible string: "audio-graph-card". So I can be sure that the "$ref: audio-graph.yaml#" should be corrected to "$ref: audio-graph-card.yaml#". In addition, not all nodes have compatible string "audio-graph-card", so the "$ref: audio-graph-card.yaml#" should be described as "anyOf". To ensure the validation of "anyOf" always passes, group it with the "if" statement, because the result of the "if" statement is always not empty. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/sound/renesas,rsnd.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml index 2e1046513603ed0..487aeabd1f0e65b 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml @@ -256,8 +256,10 @@ required: - "#sound-dai-cells" allOf: - - $ref: audio-graph.yaml# - $ref: audio-graph-port.yaml# + +anyOf: + - $ref: audio-graph-card.yaml# - if: properties: compatible: -- 1.8.3
[PATCH 1/1] ASoC: intel, keembay-i2s: Fix a dt_binding_check warning
The property "dmas" contains two items: DMA "TX" and "RX" channel, Therefore, its value also needs to be written in two parts. Otherwise, below YAML check warning is reported: Documentation/devicetree/bindings/sound/intel,keembay-i2s.example.dt.yaml:\ i2s@2014: dmas: [[4294967295, 29, 4294967295, 33]] is too short Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/sound/intel,keembay-i2s.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/intel,keembay-i2s.yaml b/Documentation/devicetree/bindings/sound/intel,keembay-i2s.yaml index 6f71294909a5fb4..803627e984f6089 100644 --- a/Documentation/devicetree/bindings/sound/intel,keembay-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/intel,keembay-i2s.yaml @@ -81,6 +81,6 @@ examples: interrupts = ; clock-names = "osc", "apb_clk"; clocks = <_clk KEEM_BAY_PSS_AUX_I2S3>, <_clk KEEM_BAY_PSS_I2S3>; - dmas = <_dma0 29 _dma0 33>; + dmas = <_dma0 29>, <_dma0 33>; dma-names = "tx", "rx"; }; -- 1.8.3
[PATCH 2/2] arm64: dts: imx8mp: Use the correct name for child node "snps,dwc3"
After the node name of "snps,dwc3" has been corrected to start with "usb"
in fsl,imx8mp-dwc3.yaml. Its name in dts should be modified accordingly.
Signed-off-by: Zhen Lei
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c7523fd4eae9b53..4967d72f41f613f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -828,7 +828,7 @@
ranges;
status = "disabled";
- usb_dwc3_0: dwc3@3810 {
+ usb_dwc3_0: usb@3810 {
compatible = "snps,dwc3";
reg = <0x3810 0x1>;
clocks = < IMX8MP_CLK_HSIO_AXI>,
@@ -869,7 +869,7 @@
ranges;
status = "disabled";
- usb_dwc3_1: dwc3@3820 {
+ usb_dwc3_1: usb@3820 {
compatible = "snps,dwc3";
reg = <0x3820 0x1>;
clocks = < IMX8MP_CLK_HSIO_AXI>,
--
1.8.3
[PATCH 1/2] dt-bindings: usb: dwc3-imx8mp: Use the correct name for child node "snps,dwc3"
File snps,dwc3.yaml describes the schema of Synopsys DesignWare USB3
Controller, it directly or indirectly contains "$ref: usb.yaml". So the
node name of "snps,dwc3" must start with "usb". Otherwise, the following
warning will be displayed:
Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.example.dt.yaml: \
dwc3@3810: $nodename:0: 'dwc3@3810' does not match '^usb(@.*)?'
From schema: Documentation/devicetree/bindings/usb/snps,dwc3.yaml
In addition, replace "type: object" with "$ref: snps,dwc3.yaml#". Ensure
that all properties of the child node comply with snps,dwc3.yaml.
Signed-off-by: Zhen Lei
---
Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
index cb4c6f6d3a33a3f..974032b1fda04fb 100644
--- a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
@@ -52,11 +52,8 @@ properties:
# Required child node:
patternProperties:
- "^dwc3@[0-9a-f]+$":
-type: object
-description:
- A child node must exist to represent the core DWC3 IP block
- The content of the node is defined in dwc3.txt.
+ "^usb@[0-9a-f]+$":
+$ref: snps,dwc3.yaml#
required:
- compatible
@@ -87,7 +84,7 @@ examples:
dma-ranges = <0x4000 0x4000 0xc000>;
ranges;
- dwc3@3810 {
+ usb@3810 {
compatible = "snps,dwc3";
reg = <0x3810 0x1>;
clocks = < IMX8MP_CLK_HSIO_AXI>,
--
1.8.3
[PATCH 0/2] dt-bindings: usb: dwc3-imx8mp: Use the correct name for child node "snps,dwc3"
File snps,dwc3.yaml describes the schema of Synopsys DesignWare USB3 Controller, it directly or indirectly contains "$ref: usb.yaml". So the node name of "snps,dwc3" must start with "usb". Otherwise, the following warning will be displayed: Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.example.dt.yaml: \ dwc3@3810: $nodename:0: 'dwc3@3810' does not match '^usb(@.*)?' From schema: Documentation/devicetree/bindings/usb/snps,dwc3.yaml Zhen Lei (2): dt-bindings: usb: dwc3-imx8mp: Use the correct name for child node "snps,dwc3" arm64: dts: imx8mp: Use the correct name for child node "snps,dwc3" Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 9 +++-- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++-- 2 files changed, 5 insertions(+), 8 deletions(-) -- 1.8.3
[PATCH 1/1] drm/amd/display: Remove duplicated header file inclusion
The header file "dce110/dce110_resource.h" is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index 4a3df13c9e49add..c4fe21b3b23f65a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -61,7 +61,6 @@ #include "dcn21/dcn21_dccg.h" #include "dcn21_hubbub.h" #include "dcn10/dcn10_resource.h" -#include "dce110/dce110_resource.h" #include "dce/dce_panel_cntl.h" #include "dcn20/dcn20_dwb.h" -- 1.8.3
[PATCH 1/1] scsi: ufs: Remove duplicated header file inclusion
The header file is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/scsi/ufs/ufshcd.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index c86760788c72c9a..e8aa7de17d0accd 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -24,7 +24,6 @@ #include "ufs_bsg.h" #include "ufshcd-crypto.h" #include -#include #define CREATE_TRACE_POINTS #include -- 1.8.3
[PATCH 1/1] drm/nouveau/nvenc: Remove duplicated header file inclusion
The header file "priv.h" is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c index c39e797dc7c9425..cf5dcfda7b2538f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c @@ -21,7 +21,6 @@ */ #include "priv.h" -#include "priv.h" #include static void * -- 1.8.3
[PATCH 1/1] drm/nouveau/dmem: Remove duplicated header file inclusion
The header file is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 92987daa5e17d02..f5cc057b123b8b0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -33,7 +33,6 @@ #include #include #include -#include #include -- 1.8.3
[PATCH 1/1] drm/amd/display: Remove duplicated header file inclusion
The header file is included in the following common section and can be removed here. Signed-off-by: Zhen Lei --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 573cf17262da4e1..74989ed502016ee 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -44,7 +44,6 @@ #include "amdgpu_dm.h" #ifdef CONFIG_DRM_AMD_DC_HDCP #include "amdgpu_dm_hdcp.h" -#include #endif #include "amdgpu_pm.h" -- 1.8.3
[PATCH 1/1] thermal: ti-soc-thermal: Remove duplicated header file inclusion
The header file is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/thermal/ti-soc-thermal/ti-bandgap.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/thermal/ti-soc-thermal/ti-bandgap.c b/drivers/thermal/ti-soc-thermal/ti-bandgap.c index 8a3646e26ddd208..d81af89166d2360 100644 --- a/drivers/thermal/ti-soc-thermal/ti-bandgap.c +++ b/drivers/thermal/ti-soc-thermal/ti-bandgap.c @@ -32,7 +32,6 @@ #include #include #include -#include #include "ti-bandgap.h" -- 1.8.3
[PATCH 1/1] pinctrl: Remove duplicated header file inclusion
The header file is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/pinctrl/pinctrl-k210.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index 8a733cf77ba0522..f831526d06ff68f 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -15,7 +15,6 @@ #include #include #include -#include #include -- 1.8.3
[PATCH 1/1] soc: litex: Remove duplicated header file inclusion
The header file is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/soc/litex/litex_soc_ctrl.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/litex/litex_soc_ctrl.c b/drivers/soc/litex/litex_soc_ctrl.c index 6268bfa7f0d6088..c3e379a990f2cc9 100644 --- a/drivers/soc/litex/litex_soc_ctrl.c +++ b/drivers/soc/litex/litex_soc_ctrl.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include -- 1.8.3
[PATCH 1/1] watchdog: dw_wdt: Remove duplicated header file inclusion
The header file is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/watchdog/dw_wdt.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c index 32d0e1781e63c4e..b1642e2d9175584 100644 --- a/drivers/watchdog/dw_wdt.c +++ b/drivers/watchdog/dw_wdt.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include -- 1.8.3
[PATCH 1/1] bus: bt1-apb: Remove duplicated header file inclusion
The header file is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/bus/bt1-apb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/bus/bt1-apb.c b/drivers/bus/bt1-apb.c index b25ff941e7c7f52..74b1b712ef3a804 100644 --- a/drivers/bus/bt1-apb.c +++ b/drivers/bus/bt1-apb.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #define APB_EHB_ISR0x00 -- 1.8.3
[PATCH 1/1] media: vidtv: Remove duplicated header file inclusion
The header file is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/media/test-drivers/vidtv/vidtv_psi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/test-drivers/vidtv/vidtv_psi.c b/drivers/media/test-drivers/vidtv/vidtv_psi.c index 47ed7907db8df55..c11ac8dca73dffb 100644 --- a/drivers/media/test-drivers/vidtv/vidtv_psi.c +++ b/drivers/media/test-drivers/vidtv/vidtv_psi.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include -- 1.8.3
[PATCH 1/1] media: atomisp: Remove duplicated header file inclusion
The header file "ia_css_isys.h" is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/staging/media/atomisp/pci/sh_css.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/staging/media/atomisp/pci/sh_css.c b/drivers/staging/media/atomisp/pci/sh_css.c index ddee04c8248d043..afddc54094e9f8d 100644 --- a/drivers/staging/media/atomisp/pci/sh_css.c +++ b/drivers/staging/media/atomisp/pci/sh_css.c @@ -49,9 +49,6 @@ #include "ia_css_pipe_util.h" #include "ia_css_pipe_binarydesc.h" #include "ia_css_pipe_stagedesc.h" -#ifndef ISP2401 -#include "ia_css_isys.h" -#endif #include "tag.h" #include "assert_support.h" -- 1.8.3
[PATCH 1/1] net/mlx5: Remove duplicated header file inclusion
The header file "esw/indir_table.h" is already included above and can be removed here. Signed-off-by: Zhen Lei --- drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 8694b83968b4c4f..e598a5cda98853f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -40,7 +40,6 @@ #include "eswitch.h" #include "esw/indir_table.h" #include "esw/acl/ofld.h" -#include "esw/indir_table.h" #include "rdma.h" #include "en.h" #include "fs_core.h" -- 1.8.3
[PATCH 2/4] vfio/mdev: Fix spelling mistake "interal" -> "internal"
There is a spelling mistake in a comment, fix it. Signed-off-by: Zhen Lei --- drivers/vfio/mdev/mdev_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/mdev/mdev_private.h b/drivers/vfio/mdev/mdev_private.h index 7d922950caaf3c1..4d62b76c473409d 100644 --- a/drivers/vfio/mdev/mdev_private.h +++ b/drivers/vfio/mdev/mdev_private.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Mediated device interal definitions + * Mediated device internal definitions * * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * Author: Neo Jia -- 1.8.3
[PATCH 4/4] vfio/platform: Fix spelling mistake "registe" -> "register"
There is a spelling mistake in a comment, fix it. Signed-off-by: Zhen Lei --- drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c b/drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c index 09a9453b75c5592..63cc7f0b2e4a437 100644 --- a/drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c +++ b/drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c @@ -26,7 +26,7 @@ #define XGMAC_DMA_CONTROL 0x0f18 /* Ctrl (Operational Mode) */ #define XGMAC_DMA_INTR_ENA 0x0f1c /* Interrupt Enable */ -/* DMA Control registe defines */ +/* DMA Control register defines */ #define DMA_CONTROL_ST 0x2000 /* Start/Stop Transmission */ #define DMA_CONTROL_SR 0x0002 /* Start/Stop Receive */ -- 1.8.3
[PATCH 3/4] vfio/pci: fix a couple of spelling mistakes
There are several spelling mistakes, as follows:
permision ==> permission
thru ==> through
presense ==> presence
Signed-off-by: Zhen Lei
---
drivers/vfio/pci/vfio_pci.c | 2 +-
drivers/vfio/pci/vfio_pci_config.c | 2 +-
drivers/vfio/pci/vfio_pci_nvlink2.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c
index 65e7e6b44578c29..d2ab8b5bc8a86fe 100644
--- a/drivers/vfio/pci/vfio_pci.c
+++ b/drivers/vfio/pci/vfio_pci.c
@@ -2409,7 +2409,7 @@ static int __init vfio_pci_init(void)
{
int ret;
- /* Allocate shared config space permision data used by all devices */
+ /* Allocate shared config space permission data used by all devices */
ret = vfio_pci_init_perm_bits();
if (ret)
return ret;
diff --git a/drivers/vfio/pci/vfio_pci_config.c
b/drivers/vfio/pci/vfio_pci_config.c
index a402adee8a21558..d57f037f65b85d4 100644
--- a/drivers/vfio/pci/vfio_pci_config.c
+++ b/drivers/vfio/pci/vfio_pci_config.c
@@ -101,7 +101,7 @@
/*
* Read/Write Permission Bits - one bit for each bit in capability
* Any field can be read if it exists, but what is read depends on
- * whether the field is 'virtualized', or just pass thru to the
+ * whether the field is 'virtualized', or just pass through to the
* hardware. Any virtualized field is also virtualized for writes.
* Writes are only permitted if they have a 1 bit here.
*/
diff --git a/drivers/vfio/pci/vfio_pci_nvlink2.c
b/drivers/vfio/pci/vfio_pci_nvlink2.c
index 9adcf6a8f888575..f276624fec79f68 100644
--- a/drivers/vfio/pci/vfio_pci_nvlink2.c
+++ b/drivers/vfio/pci/vfio_pci_nvlink2.c
@@ -219,7 +219,7 @@ int vfio_pci_nvdia_v100_nvlink2_init(struct vfio_pci_device
*vdev)
unsigned long events = VFIO_GROUP_NOTIFY_SET_KVM;
/*
-* PCI config space does not tell us about NVLink presense but
+* PCI config space does not tell us about NVLink presence but
* platform does, use this.
*/
npu_dev = pnv_pci_get_npu_dev(vdev->pdev, 0);
@@ -402,7 +402,7 @@ int vfio_pci_ibm_npu2_init(struct vfio_pci_device *vdev)
u32 link_speed = 0xff;
/*
-* PCI config space does not tell us about NVLink presense but
+* PCI config space does not tell us about NVLink presence but
* platform does, use this.
*/
if (!pnv_pci_get_gpu_dev(vdev->pdev))
--
1.8.3
[PATCH 0/4] vfio: fix a couple of spelling mistakes detected by codespell tool
This detection and correction covers the entire driver/vfio directory. Zhen Lei (4): vfio/type1: fix a couple of spelling mistakes vfio/mdev: Fix spelling mistake "interal" -> "internal" vfio/pci: fix a couple of spelling mistakes vfio/platform: Fix spelling mistake "registe" -> "register" drivers/vfio/mdev/mdev_private.h | 2 +- drivers/vfio/pci/vfio_pci.c | 2 +- drivers/vfio/pci/vfio_pci_config.c | 2 +- drivers/vfio/pci/vfio_pci_nvlink2.c | 4 ++-- drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c | 2 +- drivers/vfio/vfio_iommu_type1.c | 6 +++--- 6 files changed, 9 insertions(+), 9 deletions(-) -- 1.8.3
[PATCH 1/4] vfio/type1: fix a couple of spelling mistakes
There are several spelling mistakes, as follows: userpsace ==> userspace Accouting ==> Accounting exlude ==> exclude Signed-off-by: Zhen Lei --- drivers/vfio/vfio_iommu_type1.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c index be07664af74..21cf1d123036c82 100644 --- a/drivers/vfio/vfio_iommu_type1.c +++ b/drivers/vfio/vfio_iommu_type1.c @@ -16,7 +16,7 @@ * IOMMU to support the IOMMU API and have few to no restrictions around * the IOVA range that can be mapped. The Type1 IOMMU is currently * optimized for relatively static mappings of a userspace process with - * userpsace pages pinned into memory. We also assume devices and IOMMU + * userspace pages pinned into memory. We also assume devices and IOMMU * domains are PCI based as the IOMMU API is still centered around a * device/bus interface rather than a group interface. */ @@ -871,7 +871,7 @@ static int vfio_iommu_type1_pin_pages(void *iommu_data, /* * If iommu capable domain exist in the container then all pages are -* already pinned and accounted. Accouting should be done if there is no +* already pinned and accounted. Accounting should be done if there is no * iommu capable domain in the container. */ do_accounting = !IS_IOMMU_CAP_DOMAIN_IN_CONTAINER(iommu); @@ -2171,7 +2171,7 @@ static int vfio_iommu_resv_exclude(struct list_head *iova, continue; /* * Insert a new node if current node overlaps with the -* reserve region to exlude that from valid iova range. +* reserve region to exclude that from valid iova range. * Note that, new node is inserted before the current * node and finally the current node is deleted keeping * the list updated and sorted. -- 1.8.3
[PATCH 8/8] iommu/vt-d: fix a couple of spelling mistakes
There are several spelling mistakes, as follows:
guarentees ==> guarantees
resgister ==> register
insufficent ==> insufficient
creats ==> creates
tabke ==> take
Signed-off-by: Zhen Lei
---
drivers/iommu/intel/dmar.c | 6 +++---
drivers/iommu/intel/iommu.c | 2 +-
drivers/iommu/intel/irq_remapping.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index d5c51b5c20aff4b..bb6f0880f6f4db0 100644
--- a/drivers/iommu/intel/dmar.c
+++ b/drivers/iommu/intel/dmar.c
@@ -45,7 +45,7 @@ struct dmar_res_callback {
/*
* Assumptions:
- * 1) The hotplug framework guarentees that DMAR unit will be hot-added
+ * 1) The hotplug framework guarantees that DMAR unit will be hot-added
*before IO devices managed by that unit.
* 2) The hotplug framework guarantees that DMAR unit will be hot-removed
*after IO devices managed by that unit.
@@ -960,10 +960,10 @@ static void unmap_iommu(struct intel_iommu *iommu)
/**
* map_iommu: map the iommu's registers
* @iommu: the iommu to map
- * @phys_addr: the physical address of the base resgister
+ * @phys_addr: the physical address of the base register
*
* Memory map the iommu's registers. Start w/ a single page, and
- * possibly expand if that turns out to be insufficent.
+ * possibly expand if that turns out to be insufficient.
*/
static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
{
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index ee0932307d646bb..f9a2277fba99f9f 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -288,7 +288,7 @@ static inline void context_clear_entry(struct context_entry
*context)
/*
* This domain is a statically identity mapping domain.
- * 1. This domain creats a static 1:1 mapping to all usable memory.
+ * 1. This domain creates a static 1:1 mapping to all usable memory.
* 2. It maps to each iommu if successful.
* 3. Each iommu mapps to this domain if successful.
*/
diff --git a/drivers/iommu/intel/irq_remapping.c
b/drivers/iommu/intel/irq_remapping.c
index 611ef5243cb63b9..12e9f2cf84e5101 100644
--- a/drivers/iommu/intel/irq_remapping.c
+++ b/drivers/iommu/intel/irq_remapping.c
@@ -74,7 +74,7 @@ struct intel_ir_data {
* ->iommu->register_lock
* Note:
* intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
- * in single-threaded environment with interrupt disabled, so no need to tabke
+ * in single-threaded environment with interrupt disabled, so no need to take
* the dmar_global_lock.
*/
DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
--
1.8.3
[PATCH 2/8] iommu/omap: Fix spelling mistake "alignement" -> "alignment"
There is a spelling mistake in a comment, fix it.
Signed-off-by: Zhen Lei
---
drivers/iommu/omap-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index 71f29c0927fc710..b2a6ab700ec43d1 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -1754,7 +1754,7 @@ static int __init omap_iommu_init(void)
{
struct kmem_cache *p;
const slab_flags_t flags = SLAB_HWCACHE_ALIGN;
- size_t align = 1 << 10; /* L2 pagetable alignement */
+ size_t align = 1 << 10; /* L2 pagetable alignment */
struct device_node *np;
int ret;
--
1.8.3
[PATCH 6/8] iommu/amd: fix a couple of spelling mistakes
There are several spelling mistakes, as follows:
alignement ==> alignment
programing ==> programming
implemtation ==> implementation
assignement ==> assignment
By the way, both "programing" and "programming" are acceptable, but the
latter seems more formal.
Signed-off-by: Zhen Lei
---
drivers/iommu/amd/amd_iommu_types.h | 2 +-
drivers/iommu/amd/init.c| 4 ++--
drivers/iommu/amd/iommu.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h
b/drivers/iommu/amd/amd_iommu_types.h
index 6937e3674a16e26..dc1814c355cff77 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -446,7 +446,7 @@ struct irq_remap_table {
/* Interrupt remapping feature used? */
extern bool amd_iommu_irq_remap;
-/* kmem_cache to get tables with 128 byte alignement */
+/* kmem_cache to get tables with 128 byte alignment */
extern struct kmem_cache *amd_iommu_irq_cache;
/*
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 321f5906e6ed3a5..48799002b3571d1 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -1734,7 +1734,7 @@ static void __init init_iommu_perf_ctr(struct amd_iommu
*iommu)
goto pc_false;
/*
-* Disable power gating by programing the performance counter
+* Disable power gating by programming the performance counter
* source to 20 (i.e. counts the reads and writes from/to IOMMU
* Reserved Register [MMIO Offset 1FF8h] that are ignored.),
* which never get incremented during this init phase.
@@ -2088,7 +2088,7 @@ static int intcapxt_irqdomain_activate(struct irq_domain
*domain,
xt.destid_24_31 = cfg->dest_apicid >> 24;
/**
-* Current IOMMU implemtation uses the same IRQ for all
+* Current IOMMU implementation uses the same IRQ for all
* 3 IOMMU interrupts.
*/
writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET);
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index a69a8b573e40d00..d14e4698f507b89 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1865,7 +1865,7 @@ int __init amd_iommu_init_dma_ops(void)
* The following functions belong to the exported interface of AMD IOMMU
*
* This interface allows access to lower level functions of the IOMMU
- * like protection domain handling and assignement of devices to domains
+ * like protection domain handling and assignment of devices to domains
* which is not possible with the dma_ops interface.
*
*/
--
1.8.3
[PATCH 3/8] iommu/mediatek: Fix spelling mistake "phyiscal" -> "physical"
There is a spelling mistake in a comment, fix it.
Signed-off-by: Zhen Lei
---
drivers/iommu/mtk_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 6ecc007f07cd52e..c8c9bf1d70b29dc 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -160,7 +160,7 @@ struct mtk_iommu_domain {
* The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
* bit32 of the CPU physical address always is needed to set, and for Region
* 'E', the CPU physical address keep as is.
- * Additionally, The iommu consumers always use the CPU phyiscal address.
+ * Additionally, The iommu consumers always use the CPU physical address.
*/
#define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x14000UL
--
1.8.3
[PATCH 5/8] iommu: fix a couple of spelling mistakes
There are several spelling mistakes, as follows: funcions ==> functions distiguish ==> distinguish detroyed ==> destroyed Signed-off-by: Zhen Lei --- drivers/iommu/iommu.c | 4 ++-- drivers/iommu/iova.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index d0b0a15dba8413c..0f4e9a6122ee58f 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1453,7 +1453,7 @@ struct iommu_group *pci_device_group(struct device *dev) /* * Look for existing groups on non-isolated functions on the same -* slot and aliases of those funcions, if any. No need to clear +* slot and aliases of those functions, if any. No need to clear * the search bitmap, the tested devfns are still valid. */ group = get_pci_function_alias_group(pdev, (unsigned long *)devfns); @@ -2267,7 +2267,7 @@ struct iommu_domain *iommu_get_dma_domain(struct device *dev) * iterating over the devices in a group. Ideally we'd have a single * device which represents the requestor ID of the group, but we also * allow IOMMU drivers to create policy defined minimum sets, where - * the physical hardware may be able to distiguish members, but we + * the physical hardware may be able to distinguish members, but we * wish to group them at a higher level (ex. untrusted multi-function * PCI devices). Thus we attach each device. */ diff --git a/drivers/iommu/iova.c b/drivers/iommu/iova.c index e6e2fa85271c3f8..bf710b0a3713e21 100644 --- a/drivers/iommu/iova.c +++ b/drivers/iommu/iova.c @@ -524,7 +524,7 @@ static void fq_destroy_all_entries(struct iova_domain *iovad) int cpu; /* -* This code runs when the iova_domain is being detroyed, so don't +* This code runs when the iova_domain is being destroyed, so don't * bother to free iovas, just call the entry_dtor on all remaining * entries. */ -- 1.8.3
[PATCH 7/8] iommu/arm-smmu: Fix spelling mistake "initally" -> "initially"
There is a spelling mistake in a comment, fix it. Signed-off-by: Zhen Lei --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index d8c6bfde6a61587..8e4e8fea106b612 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1358,7 +1358,7 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) ret = arm_smmu_register_legacy_master(dev, ); /* -* If dev->iommu_fwspec is initally NULL, arm_smmu_register_legacy_master() +* If dev->iommu_fwspec is initially NULL, arm_smmu_register_legacy_master() * will allocate/initialise a new one. Thus we need to update fwspec for * later use. */ -- 1.8.3
[PATCH 4/8] iommu/sun50i: Fix spelling mistake "consits" -> "consists"
There is a spelling mistake in a comment, fix it. Signed-off-by: Zhen Lei --- drivers/iommu/sun50i-iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index ea6db1341916524..7685b96b2d445a7 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -149,7 +149,7 @@ static void iommu_write(struct sun50i_iommu *iommu, u32 offset, u32 value) * 4096 4-bytes Directory Table Entries (DTE), each pointing to a Page * Table (PT). * - * Each PT consits of 256 4-bytes Page Table Entries (PTE), each + * Each PT consists of 256 4-bytes Page Table Entries (PTE), each * pointing to a 4kB page of physical memory. * * The IOMMU supports a single DT, pointed by the IOMMU_TTB_REG -- 1.8.3
[PATCH 0/8] iommu: fix a couple of spelling mistakes detected by codespell tool
This detection and correction covers the entire driver/iommu directory. Zhen Lei (8): iommu/pamu: fix a couple of spelling mistakes iommu/omap: Fix spelling mistake "alignement" -> "alignment" iommu/mediatek: Fix spelling mistake "phyiscal" -> "physical" iommu/sun50i: Fix spelling mistake "consits" -> "consists" iommu: fix a couple of spelling mistakes iommu/amd: fix a couple of spelling mistakes iommu/arm-smmu: Fix spelling mistake "initally" -> "initially" iommu/vt-d: fix a couple of spelling mistakes drivers/iommu/amd/amd_iommu_types.h | 2 +- drivers/iommu/amd/init.c | 4 ++-- drivers/iommu/amd/iommu.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu.c | 2 +- drivers/iommu/fsl_pamu.c | 2 +- drivers/iommu/fsl_pamu_domain.c | 2 +- drivers/iommu/fsl_pamu_domain.h | 2 +- drivers/iommu/intel/dmar.c| 6 +++--- drivers/iommu/intel/iommu.c | 2 +- drivers/iommu/intel/irq_remapping.c | 2 +- drivers/iommu/iommu.c | 4 ++-- drivers/iommu/iova.c | 2 +- drivers/iommu/mtk_iommu.c | 2 +- drivers/iommu/omap-iommu.c| 2 +- drivers/iommu/sun50i-iommu.c | 2 +- 15 files changed, 19 insertions(+), 19 deletions(-) -- 1.8.3
[PATCH 1/8] iommu/pamu: fix a couple of spelling mistakes
There are several spelling mistakes, as follows:
Returs ==> Returns
defaul ==> default
assocaited ==> associated
Signed-off-by: Zhen Lei
---
drivers/iommu/fsl_pamu.c| 2 +-
drivers/iommu/fsl_pamu_domain.c | 2 +-
drivers/iommu/fsl_pamu_domain.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c
index b9a974d9783113d..48ebbf0daa21cf9 100644
--- a/drivers/iommu/fsl_pamu.c
+++ b/drivers/iommu/fsl_pamu.c
@@ -503,7 +503,7 @@ void get_ome_index(u32 *omi_index, struct device *dev)
* @stash_dest_hint: L1, L2 or L3
* @vcpu: vpcu target for a particular cache type.
*
- * Returs stash on success or ~(u32)0 on failure.
+ * Returns stash on success or ~(u32)0 on failure.
*
*/
u32 get_stash_id(u32 stash_dest_hint, u32 vcpu)
diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c
index b2110767caf49c8..be664cd18c51970 100644
--- a/drivers/iommu/fsl_pamu_domain.c
+++ b/drivers/iommu/fsl_pamu_domain.c
@@ -418,7 +418,7 @@ static struct iommu_domain *fsl_pamu_domain_alloc(unsigned
type)
pr_debug("dma_domain allocation failed\n");
return NULL;
}
- /* defaul geometry 64 GB i.e. maximum system address */
+ /* default geometry 64 GB i.e. maximum system address */
dma_domain->iommu_domain. geometry.aperture_start = 0;
dma_domain->iommu_domain.geometry.aperture_end = (1ULL << 36) - 1;
dma_domain->iommu_domain.geometry.force_aperture = true;
diff --git a/drivers/iommu/fsl_pamu_domain.h b/drivers/iommu/fsl_pamu_domain.h
index 2865d42782e8021..4f508fa041080e3 100644
--- a/drivers/iommu/fsl_pamu_domain.h
+++ b/drivers/iommu/fsl_pamu_domain.h
@@ -24,7 +24,7 @@ struct fsl_dma_domain {
*/
dma_addr_t geom_size;
/*
-* Number of windows assocaited with this domain.
+* Number of windows associated with this domain.
* During domain initialization, it is set to the
* the maximum number of subwindows allowed for a LIODN.
* Minimum value for this is 1 indicating a single PAMU
--
1.8.3
[PATCH 1/1] iommu/arm-smmu-v3: add bit field SFM into GERROR_ERR_MASK
In arm_smmu_gerror_handler(), the value of the SMMU_GERROR register is
filtered by GERROR_ERR_MASK. However, the GERROR_ERR_MASK does not contain
the SFM bit. As a result, the subsequent error processing is not performed
when only the SFM error occurs.
Fixes: 48ec83bcbcf5 ("iommu/arm-smmu: Add initial driver support for ARM SMMUv3
devices")
Reported-by: Rui Zhu
Signed-off-by: Zhen Lei
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index f985817c967a257..230b6f6b39016cd 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -115,7 +115,7 @@
#define GERROR_PRIQ_ABT_ERR(1 << 3)
#define GERROR_EVTQ_ABT_ERR(1 << 2)
#define GERROR_CMDQ_ERR(1 << 0)
-#define GERROR_ERR_MASK0xfd
+#define GERROR_ERR_MASK0x1fd
#define ARM_SMMU_GERRORN 0x64
--
2.26.0.106.g9fadedd
[PATCH v7 4/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller
Add support for the Hisilicon Kunpeng L3 cache controller as used with
Kunpeng506 and Kunpeng509 SoCs.
These Hisilicon SoCs support LPAE, so the physical addresses is wider than
32-bits, but the actual bit width does not exceed 36 bits. When the cache
operation is performed based on the address range, the upper 30 bits of
the physical address are recorded in registers L3_MAINT_START and
L3_MAINT_END, and ignore the lower 6 bits cacheline offset.
Signed-off-by: Zhen Lei
Reviewed-by: Arnd Bergmann
---
arch/arm/mm/Kconfig| 10 ++
arch/arm/mm/Makefile | 1 +
arch/arm/mm/cache-kunpeng-l3.c | 178 +
3 files changed, 189 insertions(+)
create mode 100644 arch/arm/mm/cache-kunpeng-l3.c
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 02692fbe2db5c59..d2082503de053d2 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1070,6 +1070,16 @@ config CACHE_XSC3L2
help
This option enables the L2 cache on XScale3.
+config CACHE_KUNPENG_L3
+ bool "Enable the Hisilicon Kunpeng L3 cache controller"
+ depends on ARCH_KUNPENG50X && OF
+ default y
+ select OUTER_CACHE
+ help
+ This option enables the Kunpeng L3 cache controller on Hisilicon
+ Kunpeng506 and Kunpeng509 SoCs. It supports a maximum of 36-bit
+ physical addresses.
+
config ARM_L1_CACHE_SHIFT_6
bool
default y if CPU_V7
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 3510503bc5e688b..ececc5489e353eb 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -112,6 +112,7 @@ obj-$(CONFIG_CACHE_L2X0_PMU)+= cache-l2x0-pmu.o
obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
obj-$(CONFIG_CACHE_TAUROS2)+= cache-tauros2.o
obj-$(CONFIG_CACHE_UNIPHIER) += cache-uniphier.o
+obj-$(CONFIG_CACHE_KUNPENG_L3) += cache-kunpeng-l3.o
KASAN_SANITIZE_kasan_init.o:= n
obj-$(CONFIG_KASAN)+= kasan_init.o
diff --git a/arch/arm/mm/cache-kunpeng-l3.c b/arch/arm/mm/cache-kunpeng-l3.c
new file mode 100644
index 000..64f892de9d68058
--- /dev/null
+++ b/arch/arm/mm/cache-kunpeng-l3.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 Hisilicon Limited.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
+#define L3_CACHE_LINE_SHITF6
+
+#define L3_CTRL0x0
+#define L3_CTRL_ENABLE (1U << 0)
+#define L3_CTRL_DISABLE(0U << 0)
+
+#define L3_AUCTRL 0x4
+#define L3_AUCTRL_EVENT_EN BIT(23)
+#define L3_AUCTRL_ECC_EN BIT(8)
+
+#define L3_MAINT_CTRL 0x20
+#define L3_MAINT_RANGE_MASKGENMASK(3, 3)
+#define L3_MAINT_RANGE_ALL (0U << 3)
+#define L3_MAINT_RANGE_ADDR(1U << 3)
+#define L3_MAINT_TYPE_MASK GENMASK(2, 1)
+#define L3_MAINT_TYPE_CLEAN(1U << 1)
+#define L3_MAINT_TYPE_INV (2U << 1)
+#define L3_MAINT_TYPE_FLUSH(3U << 1)
+#define L3_MAINT_STATUS_MASK GENMASK(0, 0)
+#define L3_MAINT_STATUS_START (1U << 0)
+#define L3_MAINT_STATUS_END(0U << 0)
+
+#define L3_MAINT_START 0x24
+#define L3_MAINT_END 0x28
+
+static DEFINE_RAW_SPINLOCK(l3cache_lock);
+static void __iomem *l3_ctrl_base;
+
+/*
+ * All read and write operations on L3 cache registers are protected by the
+ * spinlock, except for l3cache_init(). Each time the L3 cache operation is
+ * performed, all related information is filled into its registers. Therefore,
+ * there is no memory order problem when only _relaxed() functions are used.
+ * This can help us achieve some performance improvement:
+ * 1) The readl_relaxed() is about 20ns faster than readl().
+ * 2) The writel_relaxed() is about 123ns faster than writel().
+ */
+static void l3cache_maint_common(u32 range, u32 op_type)
+{
+ u32 reg;
+
+ reg = readl_relaxed(l3_ctrl_base + L3_MAINT_CTRL);
+ reg &= ~(L3_MAINT_RANGE_MASK | L3_MAINT_TYPE_MASK);
+ reg |= range | op_type;
+ reg |= L3_MAINT_STATUS_START;
+ writel_relaxed(reg, l3_ctrl_base + L3_MAINT_CTRL);
+
+ /* Wait until the hardware maintenance operation is complete. */
+ do {
+ cpu_relax();
+ reg = readl_relaxed(l3_ctrl_base + L3_MAINT_CTRL);
+ } while ((reg & L3_MAINT_STATUS_MASK) != L3_MAINT_STATUS_END);
+}
+
+static void l3cache_maint_range(phys_addr_t start, phys_addr_t end, u32
op_type)
+{
+ start = start >> L3_CACHE_LINE_SHITF;
+ end = ((end - 1) >> L3_CACHE_LINE_SHITF) + 1;
+
+ writel_relaxed(start, l3_ctrl_base + L3_MAINT_START);
+ writel_relaxed(end, l3_ctrl_base + L3_MAINT_END);
+
+ l3cache_maint_common(L3_MAINT_RANGE_ADDR, op_type);
+}
+
+static i
[PATCH v7 3/4] dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller
Add devicetree binding for Hisilicon Kunpeng L3 cache controller.
Signed-off-by: Zhen Lei
Reviewed-by: Arnd Bergmann
---
.../arm/hisilicon/kunpeng-l3cache.yaml| 40 +++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
diff --git
a/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
new file mode 100644
index 000..5bf33c0e4d14b7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/kunpeng-l3cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Kunpeng L3 cache controller
+
+maintainers:
+ - Wei Xu
+
+description: |
+ The Hisilicon Kunpeng L3 outer cache controller supports a maximum of 36-bit
+ physical addresses. The data cached in the L3 outer cache can be operated
+ based on the physical address range or the entire cache.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - hisilicon,kunpeng506-l3cache
+ - hisilicon,kunpeng509-l3cache
+ - const: hisilicon,kunpeng-l3cache
+
+ reg:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+l3cache@f302b000 {
+compatible = "hisilicon,kunpeng509-l3cache",
"hisilicon,kunpeng-l3cache";
+reg = <0xf302b000 0x1000>;
+};
+...
--
2.26.0.106.g9fadedd
[PATCH v7 2/4] ARM: hisi: add support for Kunpeng50x SoC
Enable support for the Hisilicon Kunpeng506 and Kunpeng509 SoC. Signed-off-by: Zhen Lei Reviewed-by: Arnd Bergmann --- arch/arm/mach-hisi/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 2e980f834a6aa1b..a004eac24b243af 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -55,6 +55,12 @@ config ARCH_HIX5HD2 help Support for Hisilicon HIX5HD2 SoC family +config ARCH_KUNPENG50X + bool "Hisilicon Kunpeng50x family" + depends on ARCH_MULTI_V7 + help + Support for Hisilicon Kunpeng506 and Kunpeng509 SoC family + config ARCH_SD5203 bool "Hisilicon SD5203 family" depends on ARCH_MULTI_V5 -- 2.26.0.106.g9fadedd
[PATCH v7 1/4] ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks
The outercache of some Hisilicon SOCs support physical addresses wider
than 32-bits. The unsigned long datatype is not sufficient for mapping
physical addresses >= 4GB. The commit ad6b9c9d78b9 ("ARM: 6671/1: LPAE:
use phys_addr_t instead of unsigned long in outercache functions") has
already modified the outercache functions. But the parameters of the
outercache hooks are not changed. This patch use phys_addr_t instead of
unsigned long in outercache hooks: inv_range, clean_range, flush_range.
To ensure the outercache that does not support LPAE works properly, do
cast phys_addr_t to unsigned long by adding a group of temporary
variables. For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
Note that the outercache functions have been doing this cast before this
patch. So now, the cast is just moved into the outercache hook functions.
No functional change.
Signed-off-by: Zhen Lei
Reviewed-by: Arnd Bergmann
---
arch/arm/include/asm/outercache.h | 6 ++--
arch/arm/mm/cache-feroceon-l2.c | 15 --
arch/arm/mm/cache-l2x0.c | 50 ++-
arch/arm/mm/cache-tauros2.c | 15 --
arch/arm/mm/cache-uniphier.c | 6 ++--
arch/arm/mm/cache-xsc3l2.c| 12 ++--
6 files changed, 75 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index 3364637755e86aa..4cee1ea0c15449a 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -14,9 +14,9 @@
struct l2x0_regs;
struct outer_cache_fns {
- void (*inv_range)(unsigned long, unsigned long);
- void (*clean_range)(unsigned long, unsigned long);
- void (*flush_range)(unsigned long, unsigned long);
+ void (*inv_range)(phys_addr_t, phys_addr_t);
+ void (*clean_range)(phys_addr_t, phys_addr_t);
+ void (*flush_range)(phys_addr_t, phys_addr_t);
void (*flush_all)(void);
void (*disable)(void);
#ifdef CONFIG_OUTER_CACHE_SYNC
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 5c1b7a7b9af6300..10f909744d5e963 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -168,8 +168,11 @@ static unsigned long calc_range_end(unsigned long start,
unsigned long end)
return range_end;
}
-static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
+static void feroceon_l2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
+
/*
* Clean and invalidate partial first cache line.
*/
@@ -198,8 +201,11 @@ static void feroceon_l2_inv_range(unsigned long start,
unsigned long end)
dsb();
}
-static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
+static void feroceon_l2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
+
/*
* If L2 is forced to WT, the L2 will always be clean and we
* don't need to do anything here.
@@ -217,8 +223,11 @@ static void feroceon_l2_clean_range(unsigned long start,
unsigned long end)
dsb();
}
-static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
+static void feroceon_l2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
+
start &= ~(CACHE_LINE_SIZE - 1);
end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
while (start != end) {
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 43d91bfd2360086..cdaddd772b09ede 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -184,8 +184,10 @@ static void __l2c210_op_pa_range(void __iomem *reg,
unsigned long start,
}
}
-static void l2c210_inv_range(unsigned long start, unsigned long end)
+static void l2c210_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
void __iomem *base = l2x0_base;
if (start & (CACHE_LINE_SIZE - 1)) {
@@ -203,8 +205,10 @@ static void l2c210_inv_range(unsigned long start, unsigned
long end)
__l2c210_cache_sync(base);
}
-static void l2c210_clean_range(unsigned long start, unsigned long end)
+static void l2c210_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
void __iomem *base = l2x0_base;
start &= ~(CACHE_LINE_SIZE - 1);
@@ -212,8 +216,10 @@ static void l2c210_clean_range(unsigned long start,
unsigned long end)
__l2c210_cache_sync(base);
}
-s
[PATCH v7 0/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller
v6 --> v7:
1. Change all readl()/writel() to _relaxed(), add the corresponding description
to the code.
2. Delete the unnecessary spinlock protection in l3cache_init().
v5 --> v6:
1. Use raw_spin_lock_irqsave() instead of spin_lock_irqsave()
2. Move the macros defined in cache-kunpeng-l3.h into cache-kunpeng-l3.c, and
delete that header file.
3. In some places, replace readl()/writel() with
readl_relaxed()/writel_relaxed() to improve performance without affecting
functions.
4. Returns 0 instead of an error code when Kunpeng L3 Cache matching failed.
Thank you for Arnd's review comments and Russell's help.
v4 --> v5:
1. Add SoC macro ARCH_KUNPENG50X, and the Kunpeng L3 cache controller only
enabled
on that platform.
2. Require the compatible string of the Kunpeng L3 cache controller must have a
relevant name on a specific SoC. For example:
compatible = "hisilicon,kunpeng509-l3cache", "hisilicon,kunpeng-l3cache";
v3 --> v4:
Rename the compatible string from "hisilicon,l3cache" to
"hisilicon,kunpeng-l3cache".
Then adjust the file name, configuration option name, and description
accordingly.
v2 --> v3:
Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3.
v1 --> v2:
Discard the middle-tier functions and do silent narrowing cast in the outcache
hook functions. For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
v1:
Do cast phys_addr_t to unsigned long by adding a middle-tier function.
For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void __l2c220_inv_range(unsigned long start, unsigned long end)
{
...
}
+static void l2c220_inv_range(phys_addr_t start, phys_addr_t end)
+{
+ __l2c220_inv_range(start, end);
+}
Zhen Lei (4):
ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache
hooks
ARM: hisi: add support for Kunpeng50x SoC
dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache
controller
ARM: Add support for Hisilicon Kunpeng L3 cache controller
.../arm/hisilicon/kunpeng-l3cache.yaml| 40
arch/arm/include/asm/outercache.h | 6 +-
arch/arm/mach-hisi/Kconfig| 6 +
arch/arm/mm/Kconfig | 10 +
arch/arm/mm/Makefile | 1 +
arch/arm/mm/cache-feroceon-l2.c | 15 +-
arch/arm/mm/cache-kunpeng-l3.c| 178 ++
arch/arm/mm/cache-l2x0.c | 50 +++--
arch/arm/mm/cache-tauros2.c | 15 +-
arch/arm/mm/cache-uniphier.c | 6 +-
arch/arm/mm/cache-xsc3l2.c| 12 +-
11 files changed, 310 insertions(+), 29 deletions(-)
create mode 100644
Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
create mode 100644 arch/arm/mm/cache-kunpeng-l3.c
--
2.26.0.106.g9fadedd
[PATCH v5 1/1] perf/smmuv3: Don't reserve the PMCG register spaces
According to the SMMUv3 specification:
Each PMCG counter group is represented by one 4KB page (Page 0) with one
optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION
DEFINED base addresses.
This means that the PMCG register spaces may be within the 64KB pages of
the SMMUv3 register space. When both the SMMU and PMCG drivers reserve
their own resources, a resource conflict occurs.
To avoid this conflict, don't reserve the PMCG regions.
Suggested-by: Robin Murphy
Signed-off-by: Zhen Lei
Reviewed-by: Robin Murphy
---
drivers/perf/arm_smmuv3_pmu.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index 74474bb322c3f26..8f0b71b5d08a815 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -793,17 +793,30 @@ static int smmu_pmu_probe(struct platform_device *pdev)
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
- smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0,
_0);
- if (IS_ERR(smmu_pmu->reg_base))
- return PTR_ERR(smmu_pmu->reg_base);
+ /*
+* The register spaces of the PMCG may be in the register space of
+* other devices. For example, SMMU. Therefore, the PMCG resources are
+* not reserved to avoid resource conflicts with other drivers.
+*/
+ res_0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res_0)
+ return -EINVAL;
+ smmu_pmu->reg_base = devm_ioremap(dev, res_0->start,
resource_size(res_0));
+ if (!smmu_pmu->reg_base)
+ return -ENOMEM;
cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
/* Determine if page 1 is present */
if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
- smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(smmu_pmu->reloc_base))
- return PTR_ERR(smmu_pmu->reloc_base);
+ struct resource *res_1;
+
+ res_1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res_1)
+ return -EINVAL;
+ smmu_pmu->reloc_base = devm_ioremap(dev, res_1->start,
resource_size(res_1));
+ if (!smmu_pmu->reloc_base)
+ return -ENOMEM;
} else {
smmu_pmu->reloc_base = smmu_pmu->reg_base;
}
--
2.26.0.106.g9fadedd
[PATCH v5 0/1] perf/smmuv3: Don't reserve the PMCG register spaces
v4 --> v5:
1. Give up doing the mapping for the entire SMMU register space.
2. Fix some compile warnings. Sorry. So sorry.
v3 --> v4:
1. Delete the unnecessary encapsulation function
smmu_pmu_get_and_ioremap_resource().
2. Discard adding MODULE_SOFTDEP.
v2 --> v3:
Patch 3 is updated because https://lkml.org/lkml/2021/1/22/532 has been queued
in advance.
v1 --> v2:
According to Robin Murphy's suggestion: https://lkml.org/lkml/2021/1/20/470
Don't reserve the PMCG register spaces, and reserve the entire SMMU register
space.
v1:
Since the PMCG may implement its resigters space(4KB Page0 and 4KB Page1)
within the SMMUv3 64KB Page0. In this case, when the SMMUv3 driver reserves the
64KB Page0 resource in advance, the PMCG driver try to reserve its Page0 and
Page1 resources, a resource conflict occurs.
commit 52f3fab0067d6fa ("iommu/arm-smmu-v3: Don't reserve implementation
defined register space") reduce the resource reservation range of the SMMUv3
driver, it only reserves the first 0xe00 bytes in the 64KB Page0, to avoid
the above-mentioned resource conflicts.
But the SMMUv3.3 add support for ECMDQ, its registers space is also implemented
in the SMMUv3 64KB Page0. This means we need to build two separate mappings.
New features may be added in the future, and more independent mappings may be
required. The simple problem is complicated because the user expects to map the
entire SMMUv3 64KB Page0.
Therefore, the proper solution is: If the PMCG register resources are located in
the 64KB Page0 of the SMMU, the PMCG driver does not reserve the conflict
resources
when the SMMUv3 driver has reserved the conflict resources before. Instead, the
PMCG
driver only performs devm_ioremap() to ensure that it can work properly.
Zhen Lei (1):
perf/smmuv3: Don't reserve the PMCG register spaces
drivers/perf/arm_smmuv3_pmu.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
--
2.26.0.106.g9fadedd
[PATCH v6 1/4] ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks
The outercache of some Hisilicon SOCs support physical addresses wider
than 32-bits. The unsigned long datatype is not sufficient for mapping
physical addresses >= 4GB. The commit ad6b9c9d78b9 ("ARM: 6671/1: LPAE:
use phys_addr_t instead of unsigned long in outercache functions") has
already modified the outercache functions. But the parameters of the
outercache hooks are not changed. This patch use phys_addr_t instead of
unsigned long in outercache hooks: inv_range, clean_range, flush_range.
To ensure the outercache that does not support LPAE works properly, do
cast phys_addr_t to unsigned long by adding a group of temporary
variables. For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
Note that the outercache functions have been doing this cast before this
patch. So now, the cast is just moved into the outercache hook functions.
No functional change.
Signed-off-by: Zhen Lei
Reviewed-by: Arnd Bergmann
---
arch/arm/include/asm/outercache.h | 6 ++--
arch/arm/mm/cache-feroceon-l2.c | 15 --
arch/arm/mm/cache-l2x0.c | 50 ++-
arch/arm/mm/cache-tauros2.c | 15 --
arch/arm/mm/cache-uniphier.c | 6 ++--
arch/arm/mm/cache-xsc3l2.c| 12 ++--
6 files changed, 75 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index 3364637755e86aa..4cee1ea0c15449a 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -14,9 +14,9 @@
struct l2x0_regs;
struct outer_cache_fns {
- void (*inv_range)(unsigned long, unsigned long);
- void (*clean_range)(unsigned long, unsigned long);
- void (*flush_range)(unsigned long, unsigned long);
+ void (*inv_range)(phys_addr_t, phys_addr_t);
+ void (*clean_range)(phys_addr_t, phys_addr_t);
+ void (*flush_range)(phys_addr_t, phys_addr_t);
void (*flush_all)(void);
void (*disable)(void);
#ifdef CONFIG_OUTER_CACHE_SYNC
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 5c1b7a7b9af6300..10f909744d5e963 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -168,8 +168,11 @@ static unsigned long calc_range_end(unsigned long start,
unsigned long end)
return range_end;
}
-static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
+static void feroceon_l2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
+
/*
* Clean and invalidate partial first cache line.
*/
@@ -198,8 +201,11 @@ static void feroceon_l2_inv_range(unsigned long start,
unsigned long end)
dsb();
}
-static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
+static void feroceon_l2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
+
/*
* If L2 is forced to WT, the L2 will always be clean and we
* don't need to do anything here.
@@ -217,8 +223,11 @@ static void feroceon_l2_clean_range(unsigned long start,
unsigned long end)
dsb();
}
-static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
+static void feroceon_l2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
+
start &= ~(CACHE_LINE_SIZE - 1);
end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
while (start != end) {
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 43d91bfd2360086..cdaddd772b09ede 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -184,8 +184,10 @@ static void __l2c210_op_pa_range(void __iomem *reg,
unsigned long start,
}
}
-static void l2c210_inv_range(unsigned long start, unsigned long end)
+static void l2c210_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
void __iomem *base = l2x0_base;
if (start & (CACHE_LINE_SIZE - 1)) {
@@ -203,8 +205,10 @@ static void l2c210_inv_range(unsigned long start, unsigned
long end)
__l2c210_cache_sync(base);
}
-static void l2c210_clean_range(unsigned long start, unsigned long end)
+static void l2c210_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
void __iomem *base = l2x0_base;
start &= ~(CACHE_LINE_SIZE - 1);
@@ -212,8 +216,10 @@ static void l2c210_clean_range(unsigned long start,
unsigned long end)
__l2c210_cache_sync(base);
}
-s
[PATCH v6 4/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller
Add support for the Hisilicon Kunpeng L3 cache controller as used with
Kunpeng506 and Kunpeng509 SoCs.
These Hisilicon SoCs support LPAE, so the physical addresses is wider than
32-bits, but the actual bit width does not exceed 36 bits. When the cache
operation is performed based on the address range, the upper 30 bits of
the physical address are recorded in registers L3_MAINT_START and
L3_MAINT_END, and ignore the lower 6 bits cacheline offset.
Signed-off-by: Zhen Lei
---
arch/arm/mm/Kconfig| 10 ++
arch/arm/mm/Makefile | 1 +
arch/arm/mm/cache-kunpeng-l3.c | 176 +
3 files changed, 187 insertions(+)
create mode 100644 arch/arm/mm/cache-kunpeng-l3.c
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 02692fbe2db5c59..d2082503de053d2 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1070,6 +1070,16 @@ config CACHE_XSC3L2
help
This option enables the L2 cache on XScale3.
+config CACHE_KUNPENG_L3
+ bool "Enable the Hisilicon Kunpeng L3 cache controller"
+ depends on ARCH_KUNPENG50X && OF
+ default y
+ select OUTER_CACHE
+ help
+ This option enables the Kunpeng L3 cache controller on Hisilicon
+ Kunpeng506 and Kunpeng509 SoCs. It supports a maximum of 36-bit
+ physical addresses.
+
config ARM_L1_CACHE_SHIFT_6
bool
default y if CPU_V7
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 3510503bc5e688b..ececc5489e353eb 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -112,6 +112,7 @@ obj-$(CONFIG_CACHE_L2X0_PMU)+= cache-l2x0-pmu.o
obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
obj-$(CONFIG_CACHE_TAUROS2)+= cache-tauros2.o
obj-$(CONFIG_CACHE_UNIPHIER) += cache-uniphier.o
+obj-$(CONFIG_CACHE_KUNPENG_L3) += cache-kunpeng-l3.o
KASAN_SANITIZE_kasan_init.o:= n
obj-$(CONFIG_KASAN)+= kasan_init.o
diff --git a/arch/arm/mm/cache-kunpeng-l3.c b/arch/arm/mm/cache-kunpeng-l3.c
new file mode 100644
index 000..4a9e47150a446ed
--- /dev/null
+++ b/arch/arm/mm/cache-kunpeng-l3.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 Hisilicon Limited.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
+#define L3_CACHE_LINE_SHITF6
+
+#define L3_CTRL0x0
+#define L3_CTRL_ENABLE (1U << 0)
+#define L3_CTRL_DISABLE(0U << 0)
+
+#define L3_AUCTRL 0x4
+#define L3_AUCTRL_EVENT_EN BIT(23)
+#define L3_AUCTRL_ECC_EN BIT(8)
+
+#define L3_MAINT_CTRL 0x20
+#define L3_MAINT_RANGE_MASKGENMASK(3, 3)
+#define L3_MAINT_RANGE_ALL (0U << 3)
+#define L3_MAINT_RANGE_ADDR(1U << 3)
+#define L3_MAINT_TYPE_MASK GENMASK(2, 1)
+#define L3_MAINT_TYPE_CLEAN(1U << 1)
+#define L3_MAINT_TYPE_INV (2U << 1)
+#define L3_MAINT_TYPE_FLUSH(3U << 1)
+#define L3_MAINT_STATUS_MASK GENMASK(0, 0)
+#define L3_MAINT_STATUS_START (1U << 0)
+#define L3_MAINT_STATUS_END(0U << 0)
+
+#define L3_MAINT_START 0x24
+#define L3_MAINT_END 0x28
+
+static DEFINE_RAW_SPINLOCK(l3cache_lock);
+static void __iomem *l3_ctrl_base;
+
+
+static void l3cache_maint_common(u32 range, u32 op_type)
+{
+ u32 reg;
+
+ reg = readl_relaxed(l3_ctrl_base + L3_MAINT_CTRL);
+ reg &= ~(L3_MAINT_RANGE_MASK | L3_MAINT_TYPE_MASK);
+ reg |= range | op_type;
+ reg |= L3_MAINT_STATUS_START;
+ writel(reg, l3_ctrl_base + L3_MAINT_CTRL);
+
+ /* Wait until the hardware maintenance operation is complete. */
+ do {
+ cpu_relax();
+ reg = readl(l3_ctrl_base + L3_MAINT_CTRL);
+ } while ((reg & L3_MAINT_STATUS_MASK) != L3_MAINT_STATUS_END);
+}
+
+static void l3cache_maint_range(phys_addr_t start, phys_addr_t end, u32
op_type)
+{
+ start = start >> L3_CACHE_LINE_SHITF;
+ end = ((end - 1) >> L3_CACHE_LINE_SHITF) + 1;
+
+ writel_relaxed(start, l3_ctrl_base + L3_MAINT_START);
+ writel_relaxed(end, l3_ctrl_base + L3_MAINT_END);
+
+ l3cache_maint_common(L3_MAINT_RANGE_ADDR, op_type);
+}
+
+static inline void l3cache_flush_all_nolock(void)
+{
+ l3cache_maint_common(L3_MAINT_RANGE_ALL, L3_MAINT_TYPE_FLUSH);
+}
+
+static void l3cache_flush_all(void)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(_lock, flags);
+ l3cache_flush_all_nolock();
+ raw_spin_unlock_irqrestore(_lock, flags);
+}
+
+static void l3cache_inv_range(phys_addr_t start, phys_addr_t end)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(_lock, flags);
+ l3cache_maint_range(start, end, L3_MAINT_TYPE_INV);
+ raw_s
[PATCH v6 2/4] ARM: hisi: add support for Kunpeng50x SoC
Enable support for the Hisilicon Kunpeng506 and Kunpeng509 SoC. Signed-off-by: Zhen Lei --- arch/arm/mach-hisi/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 2e980f834a6aa1b..a004eac24b243af 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -55,6 +55,12 @@ config ARCH_HIX5HD2 help Support for Hisilicon HIX5HD2 SoC family +config ARCH_KUNPENG50X + bool "Hisilicon Kunpeng50x family" + depends on ARCH_MULTI_V7 + help + Support for Hisilicon Kunpeng506 and Kunpeng509 SoC family + config ARCH_SD5203 bool "Hisilicon SD5203 family" depends on ARCH_MULTI_V5 -- 2.26.0.106.g9fadedd
[PATCH v6 3/4] dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller
Add devicetree binding for Hisilicon Kunpeng L3 cache controller.
Signed-off-by: Zhen Lei
Reviewed-by: Arnd Bergmann
---
.../arm/hisilicon/kunpeng-l3cache.yaml| 40 +++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
diff --git
a/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
new file mode 100644
index 000..5bf33c0e4d14b7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/kunpeng-l3cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Kunpeng L3 cache controller
+
+maintainers:
+ - Wei Xu
+
+description: |
+ The Hisilicon Kunpeng L3 outer cache controller supports a maximum of 36-bit
+ physical addresses. The data cached in the L3 outer cache can be operated
+ based on the physical address range or the entire cache.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - hisilicon,kunpeng506-l3cache
+ - hisilicon,kunpeng509-l3cache
+ - const: hisilicon,kunpeng-l3cache
+
+ reg:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+l3cache@f302b000 {
+compatible = "hisilicon,kunpeng509-l3cache",
"hisilicon,kunpeng-l3cache";
+reg = <0xf302b000 0x1000>;
+};
+...
--
2.26.0.106.g9fadedd
[PATCH v6 0/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller
v5 --> v6:
1. Use raw_spin_lock_irqsave() instead of spin_lock_irqsave()
2. Move the macros defined in cache-kunpeng-l3.h into cache-kunpeng-l3.c, and
delete that header file.
3. In some places, replace readl()/writel() with
readl_relaxed()/writel_relaxed() to improve performance without affecting
functions.
4. Returns 0 instead of an error code when Kunpeng L3 Cache matching failed.
Thank you for Arnd's review comments and Russell's help.
v4 --> v5:
1. Add SoC macro ARCH_KUNPENG50X, and the Kunpeng L3 cache controller only
enabled
on that platform.
2. Require the compatible string of the Kunpeng L3 cache controller must have a
relevant name on a specific SoC. For example:
compatible = "hisilicon,kunpeng509-l3cache", "hisilicon,kunpeng-l3cache";
v3 --> v4:
Rename the compatible string from "hisilicon,l3cache" to
"hisilicon,kunpeng-l3cache".
Then adjust the file name, configuration option name, and description
accordingly.
v2 --> v3:
Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3.
v1 --> v2:
Discard the middle-tier functions and do silent narrowing cast in the outcache
hook functions. For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
v1:
Do cast phys_addr_t to unsigned long by adding a middle-tier function.
For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void __l2c220_inv_range(unsigned long start, unsigned long end)
{
...
}
+static void l2c220_inv_range(phys_addr_t start, phys_addr_t end)
+{
+ __l2c220_inv_range(start, end);
+}
Zhen Lei (4):
ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache
hooks
ARM: hisi: add support for Kunpeng50x SoC
dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache
controller
ARM: Add support for Hisilicon Kunpeng L3 cache controller
.../arm/hisilicon/kunpeng-l3cache.yaml| 40
arch/arm/include/asm/outercache.h | 6 +-
arch/arm/mach-hisi/Kconfig| 6 +
arch/arm/mm/Kconfig | 10 +
arch/arm/mm/Makefile | 1 +
arch/arm/mm/cache-feroceon-l2.c | 15 +-
arch/arm/mm/cache-kunpeng-l3.c| 176 ++
arch/arm/mm/cache-l2x0.c | 50 +++--
arch/arm/mm/cache-tauros2.c | 15 +-
arch/arm/mm/cache-uniphier.c | 6 +-
arch/arm/mm/cache-xsc3l2.c| 12 +-
11 files changed, 308 insertions(+), 29 deletions(-)
create mode 100644
Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
create mode 100644 arch/arm/mm/cache-kunpeng-l3.c
--
2.26.0.106.g9fadedd
[PATCH v4 2/2] iommu/arm-smmu-v3: Reserving the entire SMMU register space
commit 52f3fab0067d ("iommu/arm-smmu-v3: Don't reserve implementation
defined register space") only reserves the basic SMMU register space. So
the ECMDQ register space is not covered, it should be mapped again. Due
to the size of this ECMDQ resource is not fixed, depending on
SMMU_IDR6.CMDQ_CONTROL_PAGE_LOG2NUMQ. Processing its resource reservation
to avoid resource conflict with PMCG is a bit more complicated.
Therefore, the resources of the PMCG are not reserved, and the entire SMMU
resources are reserved.
Signed-off-by: Zhen Lei
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 --
2 files changed, 4 insertions(+), 22 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index f04c55a7503c790..fde24403b06a9e3 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -3476,14 +3476,6 @@ static int arm_smmu_set_bus_ops(struct iommu_ops *ops)
return err;
}
-static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t
start,
- resource_size_t size)
-{
- struct resource res = DEFINE_RES_MEM(start, size);
-
- return devm_ioremap_resource(dev, );
-}
-
static int arm_smmu_device_probe(struct platform_device *pdev)
{
int irq, ret;
@@ -3519,22 +3511,14 @@ static int arm_smmu_device_probe(struct platform_device
*pdev)
}
ioaddr = res->start;
- /*
-* Don't map the IMPLEMENTATION DEFINED regions, since they may contain
-* the PMCG registers which are reserved by the PMU driver.
-*/
- smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ);
+ smmu->base = devm_ioremap_resource(dev, res);
if (IS_ERR(smmu->base))
return PTR_ERR(smmu->base);
- if (arm_smmu_resource_size(smmu) > SZ_64K) {
- smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K,
- ARM_SMMU_REG_SZ);
- if (IS_ERR(smmu->page1))
- return PTR_ERR(smmu->page1);
- } else {
+ if (arm_smmu_resource_size(smmu) > SZ_64K)
+ smmu->page1 = smmu->base + SZ_64K;
+ else
smmu->page1 = smmu->base;
- }
/* Interrupt lines */
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index da525f46dab4fc1..63f2b476987d6ae 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -152,8 +152,6 @@
#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
-#define ARM_SMMU_REG_SZ0xe00
-
/* Common MSI config fields */
#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
#define MSI_CFG2_SHGENMASK(5, 4)
--
1.8.3
[PATCH v4 1/2] perf/smmuv3: Don't reserve the PMCG register spaces
According to the SMMUv3 specification:
Each PMCG counter group is represented by one 4KB page (Page 0) with one
optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION
DEFINED base addresses.
This means that the PMCG register spaces may be within the 64KB pages of
the SMMUv3 register space. When both the SMMU and PMCG drivers reserve
their own resources, a resource conflict occurs.
To avoid this conflict, don't reserve the PMCG regions.
Suggested-by: Robin Murphy
Signed-off-by: Zhen Lei
---
drivers/perf/arm_smmuv3_pmu.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index 74474bb322c3f26..5e894f957c7b935 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -793,17 +793,30 @@ static int smmu_pmu_probe(struct platform_device *pdev)
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
- smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0,
_0);
- if (IS_ERR(smmu_pmu->reg_base))
- return PTR_ERR(smmu_pmu->reg_base);
+ /*
+* The register spaces of the PMCG may be in the register space of
+* other devices. For example, SMMU. Therefore, the PMCG resources are
+* not reserved to avoid resource conflicts with other drivers.
+*/
+ res_0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res_0)
+ return ERR_PTR(-EINVAL);
+ smmu_pmu->reg_base = devm_ioremap(dev, res_0->start,
resource_size(res_0));
+ if (!smmu_pmu->reg_base)
+ return ERR_PTR(-ENOMEM);
cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
/* Determine if page 1 is present */
if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
- smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(smmu_pmu->reloc_base))
- return PTR_ERR(smmu_pmu->reloc_base);
+ struct resource *res_1;
+
+ res_1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res_1)
+ return ERR_PTR(-EINVAL);
+ smmu_pmu->reloc_base = devm_ioremap(dev, res_1->start,
resource_size(res_1));
+ if (!smmu_pmu->reloc_base)
+ return ERR_PTR(-ENOMEM);
} else {
smmu_pmu->reloc_base = smmu_pmu->reg_base;
}
--
1.8.3
[PATCH v4 0/2] perf/smmuv3: Don't reserve the PMCG register spaces
v3 --> v4:
1. Delete the unnecessary encapsulation function
smmu_pmu_get_and_ioremap_resource().
2. Discard adding MODULE_SOFTDEP.
v2 --> v3:
Patch 3 is updated because https://lkml.org/lkml/2021/1/22/532 has been queued
in advance.
v1 --> v2:
According to Robin Murphy's suggestion: https://lkml.org/lkml/2021/1/20/470
Don't reserve the PMCG register spaces, and reserve the entire SMMU register
space.
v1:
Since the PMCG may implement its resigters space(4KB Page0 and 4KB Page1)
within the SMMUv3 64KB Page0. In this case, when the SMMUv3 driver reserves the
64KB Page0 resource in advance, the PMCG driver try to reserve its Page0 and
Page1 resources, a resource conflict occurs.
commit 52f3fab0067d6fa ("iommu/arm-smmu-v3: Don't reserve implementation
defined register space") reduce the resource reservation range of the SMMUv3
driver, it only reserves the first 0xe00 bytes in the 64KB Page0, to avoid
the above-mentioned resource conflicts.
But the SMMUv3.3 add support for ECMDQ, its registers space is also implemented
in the SMMUv3 64KB Page0. This means we need to build two separate mappings.
New features may be added in the future, and more independent mappings may be
required. The simple problem is complicated because the user expects to map the
entire SMMUv3 64KB Page0.
Therefore, the proper solution is: If the PMCG register resources are located in
the 64KB Page0 of the SMMU, the PMCG driver does not reserve the conflict
resources
when the SMMUv3 driver has reserved the conflict resources before. Instead, the
PMCG
driver only performs devm_ioremap() to ensure that it can work properly.
Zhen Lei (2):
perf/smmuv3: Don't reserve the PMCG register spaces
iommu/arm-smmu-v3: Reserving the entire SMMU register space
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 --
drivers/perf/arm_smmuv3_pmu.c | 25 +++--
3 files changed, 23 insertions(+), 28 deletions(-)
--
1.8.3
[PATCH v3 0/3] perf/smmuv3: Don't reserve the PMCG register spaces
v2 --> v3:
Patch 3 is updated because https://lkml.org/lkml/2021/1/22/532 has been queued
in advance.
v1 --> v2:
According to Robin Murphy's suggestion: https://lkml.org/lkml/2021/1/20/470
Don't reserve the PMCG register spaces, and reserve the entire SMMU register
space.
v1:
Since the PMCG may implement its resigters space(4KB Page0 and 4KB Page1)
within the SMMUv3 64KB Page0. In this case, when the SMMUv3 driver reserves the
64KB Page0 resource in advance, the PMCG driver try to reserve its Page0 and
Page1 resources, a resource conflict occurs.
commit 52f3fab0067d6fa ("iommu/arm-smmu-v3: Don't reserve implementation
defined register space") reduce the resource reservation range of the SMMUv3
driver, it only reserves the first 0xe00 bytes in the 64KB Page0, to avoid
the above-mentioned resource conflicts.
But the SMMUv3.3 add support for ECMDQ, its registers space is also implemented
in the SMMUv3 64KB Page0. This means we need to build two separate mappings.
New features may be added in the future, and more independent mappings may be
required. The simple problem is complicated because the user expects to map the
entire SMMUv3 64KB Page0.
Therefore, the proper solution is: If the PMCG register resources are located in
the 64KB Page0 of the SMMU, the PMCG driver does not reserve the conflict
resources
when the SMMUv3 driver has reserved the conflict resources before. Instead, the
PMCG
driver only performs devm_ioremap() to ensure that it can work properly.
Zhen Lei (3):
perf/smmuv3: Don't reserve the PMCG register spaces
perf/smmuv3: Add a MODULE_SOFTDEP() to indicate dependency on SMMU
iommu/arm-smmu-v3: Reserving the entire SMMU register space
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 --
drivers/perf/arm_smmuv3_pmu.c | 28 ++--
3 files changed, 30 insertions(+), 24 deletions(-)
--
1.8.3
[PATCH v3 2/3] perf/smmuv3: Add a MODULE_SOFTDEP() to indicate dependency on SMMU
The MODULE_SOFTDEP() gives user space a hint of the loading sequence. And
when command "modprobe arm_smmuv3_pmu" is executed, the arm_smmu_v3.ko is
automatically loaded in advance.
Signed-off-by: Zhen Lei
---
drivers/perf/arm_smmuv3_pmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index e5e505a0804fe53..9a305ac51208cd2 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -950,6 +950,7 @@ static void __exit arm_smmu_pmu_exit(void)
module_exit(arm_smmu_pmu_exit);
MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
+MODULE_SOFTDEP("pre: arm_smmu_v3");
MODULE_AUTHOR("Neil Leeder ");
MODULE_AUTHOR("Shameer Kolothum ");
MODULE_LICENSE("GPL v2");
--
1.8.3
[PATCH v3 3/3] iommu/arm-smmu-v3: Reserving the entire SMMU register space
commit 52f3fab0067d ("iommu/arm-smmu-v3: Don't reserve implementation
defined register space") only reserves the basic SMMU register space. So
the ECMDQ register space is not covered, it should be mapped again. Due
to the size of this ECMDQ resource is not fixed, depending on
SMMU_IDR6.CMDQ_CONTROL_PAGE_LOG2NUMQ. Processing its resource reservation
to avoid resource conflict with PMCG is a bit more complicated.
Therefore, the resources of the PMCG are not reserved, and the entire SMMU
resources are reserved.
Suggested-by: Robin Murphy
Signed-off-by: Zhen Lei
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 --
2 files changed, 4 insertions(+), 22 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index f04c55a7503c790..fde24403b06a9e3 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -3476,14 +3476,6 @@ static int arm_smmu_set_bus_ops(struct iommu_ops *ops)
return err;
}
-static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t
start,
- resource_size_t size)
-{
- struct resource res = DEFINE_RES_MEM(start, size);
-
- return devm_ioremap_resource(dev, );
-}
-
static int arm_smmu_device_probe(struct platform_device *pdev)
{
int irq, ret;
@@ -3519,22 +3511,14 @@ static int arm_smmu_device_probe(struct platform_device
*pdev)
}
ioaddr = res->start;
- /*
-* Don't map the IMPLEMENTATION DEFINED regions, since they may contain
-* the PMCG registers which are reserved by the PMU driver.
-*/
- smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ);
+ smmu->base = devm_ioremap_resource(dev, res);
if (IS_ERR(smmu->base))
return PTR_ERR(smmu->base);
- if (arm_smmu_resource_size(smmu) > SZ_64K) {
- smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K,
- ARM_SMMU_REG_SZ);
- if (IS_ERR(smmu->page1))
- return PTR_ERR(smmu->page1);
- } else {
+ if (arm_smmu_resource_size(smmu) > SZ_64K)
+ smmu->page1 = smmu->base + SZ_64K;
+ else
smmu->page1 = smmu->base;
- }
/* Interrupt lines */
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index da525f46dab4fc1..63f2b476987d6ae 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -152,8 +152,6 @@
#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
-#define ARM_SMMU_REG_SZ0xe00
-
/* Common MSI config fields */
#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
#define MSI_CFG2_SHGENMASK(5, 4)
--
1.8.3
[PATCH v3 1/3] perf/smmuv3: Don't reserve the PMCG register spaces
According to the SMMUv3 specification:
Each PMCG counter group is represented by one 4KB page (Page 0) with one
optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION
DEFINED base addresses.
This means that the PMCG register spaces may be within the 64KB pages of
the SMMUv3 register space. When both the SMMU and PMCG drivers reserve
their own resources, a resource conflict occurs.
To avoid this conflict, don't reserve the PMCG regions.
Suggested-by: Robin Murphy
Signed-off-by: Zhen Lei
---
drivers/perf/arm_smmuv3_pmu.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index 74474bb322c3f26..e5e505a0804fe53 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -761,6 +761,29 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu
*smmu_pmu)
dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
}
+static void __iomem *
+smmu_pmu_get_and_ioremap_resource(struct platform_device *pdev,
+ unsigned int index,
+ struct resource **res)
+{
+ void __iomem *base;
+ struct resource *r;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, index);
+ if (!r) {
+ dev_err(>dev, "invalid resource\n");
+ return ERR_PTR(-EINVAL);
+ }
+ if (res)
+ *res = r;
+
+ base = devm_ioremap(>dev, r->start, resource_size(r));
+ if (!base)
+ return ERR_PTR(-ENOMEM);
+
+ return base;
+}
+
static int smmu_pmu_probe(struct platform_device *pdev)
{
struct smmu_pmu *smmu_pmu;
@@ -793,7 +816,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
- smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0,
_0);
+ smmu_pmu->reg_base = smmu_pmu_get_and_ioremap_resource(pdev, 0, _0);
if (IS_ERR(smmu_pmu->reg_base))
return PTR_ERR(smmu_pmu->reg_base);
@@ -801,7 +824,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
/* Determine if page 1 is present */
if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
- smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
+ smmu_pmu->reloc_base = smmu_pmu_get_and_ioremap_resource(pdev,
1, NULL);
if (IS_ERR(smmu_pmu->reloc_base))
return PTR_ERR(smmu_pmu->reloc_base);
} else {
--
1.8.3
[PATCH v2 0/3] perf/smmuv3: Don't reserve the PMCG register spaces
v1 --> v2:
According to Robin Murphy's suggestion: https://lkml.org/lkml/2021/1/20/470
Don't reserve the PMCG register spaces, and reserve the entire SMMU register
space.
v1:
Since the PMCG may implement its resigters space(4KB Page0 and 4KB Page1)
within the SMMUv3 64KB Page0. In this case, when the SMMUv3 driver reserves the
64KB Page0 resource in advance, the PMCG driver try to reserve its Page0 and
Page1 resources, a resource conflict occurs.
commit 52f3fab0067d6fa ("iommu/arm-smmu-v3: Don't reserve implementation
defined register space") reduce the resource reservation range of the SMMUv3
driver, it only reserves the first 0xe00 bytes in the 64KB Page0, to avoid
the above-mentioned resource conflicts.
But the SMMUv3.3 add support for ECMDQ, its registers space is also implemented
in the SMMUv3 64KB Page0. This means we need to build two separate mappings.
New features may be added in the future, and more independent mappings may be
required. The simple problem is complicated because the user expects to map the
entire SMMUv3 64KB Page0.
Therefore, the proper solution is: If the PMCG register resources are located in
the 64KB Page0 of the SMMU, the PMCG driver does not reserve the conflict
resources
when the SMMUv3 driver has reserved the conflict resources before. Instead, the
PMCG
driver only performs devm_ioremap() to ensure that it can work properly.
Zhen Lei (3):
perf/smmuv3: Don't reserve the PMCG register spaces
perf/smmuv3: Add a MODULE_SOFTDEP() to indicate dependency on SMMU
iommu/arm-smmu-v3: Reserving the entire SMMU register space
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 --
drivers/perf/arm_smmuv3_pmu.c | 28 ++--
3 files changed, 30 insertions(+), 28 deletions(-)
--
1.8.3
[PATCH v2 1/3] perf/smmuv3: Don't reserve the PMCG register spaces
According to the SMMUv3 specification:
Each PMCG counter group is represented by one 4KB page (Page 0) with one
optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION
DEFINED base addresses.
This means that the PMCG register spaces may be within the 64KB pages of
the SMMUv3 register space. When both the SMMU and PMCG drivers reserve
their own resources, a resource conflict occurs.
To avoid this conflict, don't reserve the PMCG regions.
Suggested-by: Robin Murphy
Signed-off-by: Zhen Lei
---
drivers/perf/arm_smmuv3_pmu.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index 74474bb322c3f26..e5e505a0804fe53 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -761,6 +761,29 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu
*smmu_pmu)
dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
}
+static void __iomem *
+smmu_pmu_get_and_ioremap_resource(struct platform_device *pdev,
+ unsigned int index,
+ struct resource **res)
+{
+ void __iomem *base;
+ struct resource *r;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, index);
+ if (!r) {
+ dev_err(>dev, "invalid resource\n");
+ return ERR_PTR(-EINVAL);
+ }
+ if (res)
+ *res = r;
+
+ base = devm_ioremap(>dev, r->start, resource_size(r));
+ if (!base)
+ return ERR_PTR(-ENOMEM);
+
+ return base;
+}
+
static int smmu_pmu_probe(struct platform_device *pdev)
{
struct smmu_pmu *smmu_pmu;
@@ -793,7 +816,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
- smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0,
_0);
+ smmu_pmu->reg_base = smmu_pmu_get_and_ioremap_resource(pdev, 0, _0);
if (IS_ERR(smmu_pmu->reg_base))
return PTR_ERR(smmu_pmu->reg_base);
@@ -801,7 +824,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
/* Determine if page 1 is present */
if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
- smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
+ smmu_pmu->reloc_base = smmu_pmu_get_and_ioremap_resource(pdev,
1, NULL);
if (IS_ERR(smmu_pmu->reloc_base))
return PTR_ERR(smmu_pmu->reloc_base);
} else {
--
1.8.3
[PATCH v2 3/3] iommu/arm-smmu-v3: Reserving the entire SMMU register space
commit 52f3fab0067d ("iommu/arm-smmu-v3: Don't reserve implementation
defined register space") only reserves the basic SMMU register space. So
the ECMDQ register space is not covered, it should be mapped again. Due
to the size of this ECMDQ resource is not fixed, depending on
SMMU_IDR6.CMDQ_CONTROL_PAGE_LOG2NUMQ. Processing its resource reservation
to avoid resource conflict with PMCG is a bit more complicated.
Therefore, the resources of the PMCG are not reserved, and the entire SMMU
resources are reserved.
Suggested-by: Robin Murphy
Signed-off-by: Zhen Lei
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 --
2 files changed, 4 insertions(+), 26 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index bca458c00e48a8b..fde24403b06a9e3 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -3476,18 +3476,6 @@ static int arm_smmu_set_bus_ops(struct iommu_ops *ops)
return err;
}
-static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t
start,
- resource_size_t size)
-{
- struct resource res = {
- .flags = IORESOURCE_MEM,
- .start = start,
- .end = start + size - 1,
- };
-
- return devm_ioremap_resource(dev, );
-}
-
static int arm_smmu_device_probe(struct platform_device *pdev)
{
int irq, ret;
@@ -3523,22 +3511,14 @@ static int arm_smmu_device_probe(struct platform_device
*pdev)
}
ioaddr = res->start;
- /*
-* Don't map the IMPLEMENTATION DEFINED regions, since they may contain
-* the PMCG registers which are reserved by the PMU driver.
-*/
- smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ);
+ smmu->base = devm_ioremap_resource(dev, res);
if (IS_ERR(smmu->base))
return PTR_ERR(smmu->base);
- if (arm_smmu_resource_size(smmu) > SZ_64K) {
- smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K,
- ARM_SMMU_REG_SZ);
- if (IS_ERR(smmu->page1))
- return PTR_ERR(smmu->page1);
- } else {
+ if (arm_smmu_resource_size(smmu) > SZ_64K)
+ smmu->page1 = smmu->base + SZ_64K;
+ else
smmu->page1 = smmu->base;
- }
/* Interrupt lines */
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index da525f46dab4fc1..63f2b476987d6ae 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -152,8 +152,6 @@
#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
-#define ARM_SMMU_REG_SZ0xe00
-
/* Common MSI config fields */
#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
#define MSI_CFG2_SHGENMASK(5, 4)
--
1.8.3
[PATCH v2 2/3] perf/smmuv3: Add a MODULE_SOFTDEP() to indicate dependency on SMMU
The MODULE_SOFTDEP() gives user space a hint of the loading sequence. And
when command "modprobe arm_smmuv3_pmu" is executed, the arm_smmu_v3.ko is
automatically loaded in advance.
Signed-off-by: Zhen Lei
---
drivers/perf/arm_smmuv3_pmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index e5e505a0804fe53..9a305ac51208cd2 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -950,6 +950,7 @@ static void __exit arm_smmu_pmu_exit(void)
module_exit(arm_smmu_pmu_exit);
MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
+MODULE_SOFTDEP("pre: arm_smmu_v3");
MODULE_AUTHOR("Neil Leeder ");
MODULE_AUTHOR("Shameer Kolothum ");
MODULE_LICENSE("GPL v2");
--
1.8.3
[PATCH 1/1] iommu/arm-smmu-v3: Use DEFINE_RES_MEM() to simplify code
No functional change.
Signed-off-by: Zhen Lei
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index bca458c00e48a8b..f04c55a7503c790 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -3479,11 +3479,7 @@ static int arm_smmu_set_bus_ops(struct iommu_ops *ops)
static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t
start,
resource_size_t size)
{
- struct resource res = {
- .flags = IORESOURCE_MEM,
- .start = start,
- .end = start + size - 1,
- };
+ struct resource res = DEFINE_RES_MEM(start, size);
return devm_ioremap_resource(dev, );
}
--
1.8.3
[PATCH 2/2] Revert "iommu/arm-smmu-v3: Don't reserve implementation defined register space"
This reverts commit 52f3fab0067d6fa9e99c1b7f63265dd48ca76046.
This problem has been fixed by another patch. The original method had side
effects, it was not mapped to the user-specified resource size. The code
will become more complex when ECMDQ is supported later.
Signed-off-by: Zhen Lei
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 32 -
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 ---
2 files changed, 4 insertions(+), 31 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 8ca7415d785d9bf..477f473842e5272 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -91,8 +91,9 @@ struct arm_smmu_option_prop {
static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset,
struct arm_smmu_device *smmu)
{
- if (offset > SZ_64K)
- return smmu->page1 + offset - SZ_64K;
+ if ((offset > SZ_64K) &&
+ (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY))
+ offset -= SZ_64K;
return smmu->base + offset;
}
@@ -3486,18 +3487,6 @@ static int arm_smmu_set_bus_ops(struct iommu_ops *ops)
return err;
}
-static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t
start,
- resource_size_t size)
-{
- struct resource res = {
- .flags = IORESOURCE_MEM,
- .start = start,
- .end = start + size - 1,
- };
-
- return devm_ioremap_resource(dev, );
-}
-
static int arm_smmu_device_probe(struct platform_device *pdev)
{
int irq, ret;
@@ -3533,23 +3522,10 @@ static int arm_smmu_device_probe(struct platform_device
*pdev)
}
ioaddr = res->start;
- /*
-* Don't map the IMPLEMENTATION DEFINED regions, since they may contain
-* the PMCG registers which are reserved by the PMU driver.
-*/
- smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ);
+ smmu->base = devm_ioremap_resource(dev, res);
if (IS_ERR(smmu->base))
return PTR_ERR(smmu->base);
- if (arm_smmu_resource_size(smmu) > SZ_64K) {
- smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K,
- ARM_SMMU_REG_SZ);
- if (IS_ERR(smmu->page1))
- return PTR_ERR(smmu->page1);
- } else {
- smmu->page1 = smmu->base;
- }
-
/* Interrupt lines */
irq = platform_get_irq_byname_optional(pdev, "combined");
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 96c2e9565e00282..0c3090c60840c22 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -152,8 +152,6 @@
#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
-#define ARM_SMMU_REG_SZ0xe00
-
/* Common MSI config fields */
#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
#define MSI_CFG2_SHGENMASK(5, 4)
@@ -584,7 +582,6 @@ struct arm_smmu_strtab_cfg {
struct arm_smmu_device {
struct device *dev;
void __iomem*base;
- void __iomem*page1;
#define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0)
#define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1)
--
1.8.3
[PATCH 1/2] perf/smmuv3: Don't reserve the register space that overlaps with the SMMUv3
Some SMMUv3 implementation embed the Perf Monitor Group Registers (PMCG)
inside the first 64kB region of the SMMU. Since SMMU and PMCG are managed
by two separate drivers, and this driver depends on ARM_SMMU_V3, so the
SMMU driver reserves the corresponding resource first, this driver should
not reserve the corresponding resource again. Otherwise, a resource
reservation conflict is reported during boot.
Signed-off-by: Zhen Lei
---
drivers/perf/arm_smmuv3_pmu.c | 42 --
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index 74474bb322c3f26..dcce085431c6ce8 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -761,6 +761,44 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu
*smmu_pmu)
dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
}
+static void __iomem *
+smmu_pmu_get_and_ioremap_resource(struct platform_device *pdev,
+ unsigned int index,
+ struct resource **out_res)
+{
+ int ret;
+ void __iomem *base;
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, index);
+ if (!res) {
+ dev_err(>dev, "invalid resource\n");
+ return IOMEM_ERR_PTR(-EINVAL);
+ }
+ if (out_res)
+ *out_res = res;
+
+ ret = region_intersects(res->start, resource_size(res),
+ IORESOURCE_MEM, IORES_DESC_NONE);
+ if (ret == REGION_INTERSECTS) {
+ /*
+* The resource has already been reserved by the SMMUv3 driver.
+* Don't reserve it again, just do devm_ioremap().
+*/
+ base = devm_ioremap(>dev, res->start, resource_size(res));
+ } else {
+ /*
+* The resource may have not been reserved by any driver, or
+* has been reserved but not type IORESOURCE_MEM. In the latter
+* case, devm_ioremap_resource() reports a conflict and returns
+* IOMEM_ERR_PTR(-EBUSY).
+*/
+ base = devm_ioremap_resource(>dev, res);
+ }
+
+ return base;
+}
+
static int smmu_pmu_probe(struct platform_device *pdev)
{
struct smmu_pmu *smmu_pmu;
@@ -793,7 +831,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
- smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0,
_0);
+ smmu_pmu->reg_base = smmu_pmu_get_and_ioremap_resource(pdev, 0, _0);
if (IS_ERR(smmu_pmu->reg_base))
return PTR_ERR(smmu_pmu->reg_base);
@@ -801,7 +839,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
/* Determine if page 1 is present */
if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
- smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
+ smmu_pmu->reloc_base = smmu_pmu_get_and_ioremap_resource(pdev,
1, NULL);
if (IS_ERR(smmu_pmu->reloc_base))
return PTR_ERR(smmu_pmu->reloc_base);
} else {
--
1.8.3
[PATCH 0/2] Use another method to avoid resource conflicts between the SMMU and PMCG drivers
Since the PMCG may implement its resigters space(4KB Page0 and 4KB Page1)
within the SMMUv3 64KB Page0. In this case, when the SMMUv3 driver reserves the
64KB Page0 resource in advance, the PMCG driver try to reserve its Page0 and
Page1 resources, a resource conflict occurs.
commit 52f3fab0067d6fa ("iommu/arm-smmu-v3: Don't reserve implementation
defined register space") reduce the resource reservation range of the SMMUv3
driver, it only reserves the first 0xe00 bytes in the 64KB Page0, to avoid
the above-mentioned resource conflicts.
But the SMMUv3.3 add support for ECMDQ, its registers space is also implemented
in the SMMUv3 64KB Page0. This means we need to build two separate mappings.
New features may be added in the future, and more independent mappings may be
required. The simple problem is complicated because the user expects to map the
entire SMMUv3 64KB Page0.
Therefore, the proper solution is: If the PMCG register resources are located in
the 64KB Page0 of the SMMU, the PMCG driver does not reserve the conflict
resources
when the SMMUv3 driver has reserved the conflict resources before. Instead, the
PMCG
driver only performs devm_ioremap() to ensure that it can work properly.
Zhen Lei (2):
perf/smmuv3: Don't reserve the register space that overlaps with the
SMMUv3
Revert "iommu/arm-smmu-v3: Don't reserve implementation defined
register space"
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 32 +++---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 ---
drivers/perf/arm_smmuv3_pmu.c | 42 +++--
3 files changed, 44 insertions(+), 33 deletions(-)
--
1.8.3
[PATCH v5 4/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller
Add support for the Hisilicon Kunpeng L3 cache controller as used with
Kunpeng506 and Kunpeng509 SoCs.
These Hisilicon SoCs support LPAE, so the physical addresses is wider than
32-bits, but the actual bit width does not exceed 36 bits. When the cache
operation is performed based on the address range, the upper 30 bits of
the physical address are recorded in registers L3_MAINT_START and
L3_MAINT_END, and ignore the lower 6 bits cacheline offset.
Signed-off-by: Zhen Lei
---
arch/arm/mm/Kconfig| 10 +++
arch/arm/mm/Makefile | 1 +
arch/arm/mm/cache-kunpeng-l3.c | 153 +
arch/arm/mm/cache-kunpeng-l3.h | 30 +++
4 files changed, 194 insertions(+)
create mode 100644 arch/arm/mm/cache-kunpeng-l3.c
create mode 100644 arch/arm/mm/cache-kunpeng-l3.h
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 02692fbe2db5c59..d2082503de053d2 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1070,6 +1070,16 @@ config CACHE_XSC3L2
help
This option enables the L2 cache on XScale3.
+config CACHE_KUNPENG_L3
+ bool "Enable the Hisilicon Kunpeng L3 cache controller"
+ depends on ARCH_KUNPENG50X && OF
+ default y
+ select OUTER_CACHE
+ help
+ This option enables the Kunpeng L3 cache controller on Hisilicon
+ Kunpeng506 and Kunpeng509 SoCs. It supports a maximum of 36-bit
+ physical addresses.
+
config ARM_L1_CACHE_SHIFT_6
bool
default y if CPU_V7
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 3510503bc5e688b..ececc5489e353eb 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -112,6 +112,7 @@ obj-$(CONFIG_CACHE_L2X0_PMU)+= cache-l2x0-pmu.o
obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
obj-$(CONFIG_CACHE_TAUROS2)+= cache-tauros2.o
obj-$(CONFIG_CACHE_UNIPHIER) += cache-uniphier.o
+obj-$(CONFIG_CACHE_KUNPENG_L3) += cache-kunpeng-l3.o
KASAN_SANITIZE_kasan_init.o:= n
obj-$(CONFIG_KASAN)+= kasan_init.o
diff --git a/arch/arm/mm/cache-kunpeng-l3.c b/arch/arm/mm/cache-kunpeng-l3.c
new file mode 100644
index 000..cb81f15d26a0cf2
--- /dev/null
+++ b/arch/arm/mm/cache-kunpeng-l3.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 Hisilicon Limited.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cache-kunpeng-l3.h"
+
+static DEFINE_SPINLOCK(l3cache_lock);
+static void __iomem *l3_ctrl_base;
+
+
+static void l3cache_maint_common(u32 range, u32 op_type)
+{
+ u32 reg;
+
+ reg = readl(l3_ctrl_base + L3_MAINT_CTRL);
+ reg &= ~(L3_MAINT_RANGE_MASK | L3_MAINT_TYPE_MASK);
+ reg |= range | op_type;
+ reg |= L3_MAINT_STATUS_START;
+ writel(reg, l3_ctrl_base + L3_MAINT_CTRL);
+
+ /* Wait until the hardware maintenance operation is complete. */
+ do {
+ cpu_relax();
+ reg = readl(l3_ctrl_base + L3_MAINT_CTRL);
+ } while ((reg & L3_MAINT_STATUS_MASK) != L3_MAINT_STATUS_END);
+}
+
+static void l3cache_maint_range(phys_addr_t start, phys_addr_t end, u32
op_type)
+{
+ start = start >> L3_CACHE_LINE_SHITF;
+ end = ((end - 1) >> L3_CACHE_LINE_SHITF) + 1;
+
+ writel(start, l3_ctrl_base + L3_MAINT_START);
+ writel(end, l3_ctrl_base + L3_MAINT_END);
+
+ l3cache_maint_common(L3_MAINT_RANGE_ADDR, op_type);
+}
+
+static inline void l3cache_flush_all_nolock(void)
+{
+ l3cache_maint_common(L3_MAINT_RANGE_ALL, L3_MAINT_TYPE_FLUSH);
+}
+
+static void l3cache_flush_all(void)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(_lock, flags);
+ l3cache_flush_all_nolock();
+ spin_unlock_irqrestore(_lock, flags);
+}
+
+static void l3cache_inv_range(phys_addr_t start, phys_addr_t end)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(_lock, flags);
+ l3cache_maint_range(start, end, L3_MAINT_TYPE_INV);
+ spin_unlock_irqrestore(_lock, flags);
+}
+
+static void l3cache_clean_range(phys_addr_t start, phys_addr_t end)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(_lock, flags);
+ l3cache_maint_range(start, end, L3_MAINT_TYPE_CLEAN);
+ spin_unlock_irqrestore(_lock, flags);
+}
+
+static void l3cache_flush_range(phys_addr_t start, phys_addr_t end)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(_lock, flags);
+ l3cache_maint_range(start, end, L3_MAINT_TYPE_FLUSH);
+ spin_unlock_irqrestore(_lock, flags);
+}
+
+static void l3cache_disable(void)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(_lock, flags);
+ l3cache_flush_all_nolock();
+ writel(L3_CTRL_DISABLE, l3_ctrl_base + L3_CTRL);
+ spin_unlock_irqrestore(_lock, flags);
+}
+
+static const struct of_device_id l3cache_ids[] __initconst = {
+ {.compatible = "hisilicon,kunpeng-l3cache", .data = NULL},
+ {}
[PATCH v5 1/4] ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks
The outercache of some Hisilicon SOCs support physical addresses wider
than 32-bits. The unsigned long datatype is not sufficient for mapping
physical addresses >= 4GB. The commit ad6b9c9d78b9 ("ARM: 6671/1: LPAE:
use phys_addr_t instead of unsigned long in outercache functions") has
already modified the outercache functions. But the parameters of the
outercache hooks are not changed. This patch use phys_addr_t instead of
unsigned long in outercache hooks: inv_range, clean_range, flush_range.
To ensure the outercache that does not support LPAE works properly, do
cast phys_addr_t to unsigned long by adding a group of temporary
variables. For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
Note that the outercache functions have been doing this cast before this
patch. So now, the cast is just moved into the outercache hook functions.
No functional change.
Signed-off-by: Zhen Lei
---
arch/arm/include/asm/outercache.h | 6 ++--
arch/arm/mm/cache-feroceon-l2.c | 15 --
arch/arm/mm/cache-l2x0.c | 50 ++-
arch/arm/mm/cache-tauros2.c | 15 --
arch/arm/mm/cache-uniphier.c | 6 ++--
arch/arm/mm/cache-xsc3l2.c| 12 ++--
6 files changed, 75 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index 3364637755e86aa..4cee1ea0c15449a 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -14,9 +14,9 @@
struct l2x0_regs;
struct outer_cache_fns {
- void (*inv_range)(unsigned long, unsigned long);
- void (*clean_range)(unsigned long, unsigned long);
- void (*flush_range)(unsigned long, unsigned long);
+ void (*inv_range)(phys_addr_t, phys_addr_t);
+ void (*clean_range)(phys_addr_t, phys_addr_t);
+ void (*flush_range)(phys_addr_t, phys_addr_t);
void (*flush_all)(void);
void (*disable)(void);
#ifdef CONFIG_OUTER_CACHE_SYNC
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 5c1b7a7b9af6300..10f909744d5e963 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -168,8 +168,11 @@ static unsigned long calc_range_end(unsigned long start,
unsigned long end)
return range_end;
}
-static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
+static void feroceon_l2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
+
/*
* Clean and invalidate partial first cache line.
*/
@@ -198,8 +201,11 @@ static void feroceon_l2_inv_range(unsigned long start,
unsigned long end)
dsb();
}
-static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
+static void feroceon_l2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
+
/*
* If L2 is forced to WT, the L2 will always be clean and we
* don't need to do anything here.
@@ -217,8 +223,11 @@ static void feroceon_l2_clean_range(unsigned long start,
unsigned long end)
dsb();
}
-static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
+static void feroceon_l2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
+
start &= ~(CACHE_LINE_SIZE - 1);
end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
while (start != end) {
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 43d91bfd2360086..cdaddd772b09ede 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -184,8 +184,10 @@ static void __l2c210_op_pa_range(void __iomem *reg,
unsigned long start,
}
}
-static void l2c210_inv_range(unsigned long start, unsigned long end)
+static void l2c210_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
void __iomem *base = l2x0_base;
if (start & (CACHE_LINE_SIZE - 1)) {
@@ -203,8 +205,10 @@ static void l2c210_inv_range(unsigned long start, unsigned
long end)
__l2c210_cache_sync(base);
}
-static void l2c210_clean_range(unsigned long start, unsigned long end)
+static void l2c210_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
void __iomem *base = l2x0_base;
start &= ~(CACHE_LINE_SIZE - 1);
@@ -212,8 +216,10 @@ static void l2c210_clean_range(unsigned long start,
unsigned long end)
__l2c210_cache_sync(base);
}
-static void l2c210_flush_range(
[PATCH v5 0/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller
v4 --> v5:
1. Add SoC macro ARCH_KUNPENG50X, and the Kunpeng L3 cache controller only
enabled
on that platform.
2. Require the compatible string of the Kunpeng L3 cache controller must have a
relevant name on a specific SoC. For example:
compatible = "hisilicon,kunpeng509-l3cache", "hisilicon,kunpeng-l3cache";
v3 --> v4:
Rename the compatible string from "hisilicon,l3cache" to
"hisilicon,kunpeng-l3cache".
Then adjust the file name, configuration option name, and description
accordingly.
v2 --> v3:
Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3.
v1 --> v2:
Discard the middle-tier functions and do silent narrowing cast in the outcache
hook functions. For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
v1:
Do cast phys_addr_t to unsigned long by adding a middle-tier function.
For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void __l2c220_inv_range(unsigned long start, unsigned long end)
{
...
}
+static void l2c220_inv_range(phys_addr_t start, phys_addr_t end)
+{
+ __l2c220_inv_range(start, end);
+}
Zhen Lei (4):
ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache
hooks
ARM: hisi: add support for Kunpeng50x SoC
dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache
controller
ARM: Add support for Hisilicon Kunpeng L3 cache controller
.../arm/hisilicon/kunpeng-l3cache.yaml| 40 +
arch/arm/include/asm/outercache.h | 6 +-
arch/arm/mach-hisi/Kconfig| 8 +
arch/arm/mm/Kconfig | 10 ++
arch/arm/mm/Makefile | 1 +
arch/arm/mm/cache-feroceon-l2.c | 15 +-
arch/arm/mm/cache-kunpeng-l3.c| 153 ++
arch/arm/mm/cache-kunpeng-l3.h| 30
arch/arm/mm/cache-l2x0.c | 50 --
arch/arm/mm/cache-tauros2.c | 15 +-
arch/arm/mm/cache-uniphier.c | 6 +-
arch/arm/mm/cache-xsc3l2.c| 12 +-
12 files changed, 317 insertions(+), 29 deletions(-)
create mode 100644
Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
create mode 100644 arch/arm/mm/cache-kunpeng-l3.c
create mode 100644 arch/arm/mm/cache-kunpeng-l3.h
--
2.26.0.106.g9fadedd
[PATCH v5 3/4] dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller
Add devicetree binding for Hisilicon Kunpeng L3 cache controller.
Signed-off-by: Zhen Lei
---
.../arm/hisilicon/kunpeng-l3cache.yaml| 40 +++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
diff --git
a/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
new file mode 100644
index 000..5bf33c0e4d14b7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/kunpeng-l3cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Kunpeng L3 cache controller
+
+maintainers:
+ - Wei Xu
+
+description: |
+ The Hisilicon Kunpeng L3 outer cache controller supports a maximum of 36-bit
+ physical addresses. The data cached in the L3 outer cache can be operated
+ based on the physical address range or the entire cache.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - hisilicon,kunpeng506-l3cache
+ - hisilicon,kunpeng509-l3cache
+ - const: hisilicon,kunpeng-l3cache
+
+ reg:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+l3cache@f302b000 {
+compatible = "hisilicon,kunpeng509-l3cache",
"hisilicon,kunpeng-l3cache";
+reg = <0xf302b000 0x1000>;
+};
+...
--
2.26.0.106.g9fadedd
[PATCH v5 2/4] ARM: hisi: add support for Kunpeng50x SoC
Enable support for the Hisilicon Kunpeng506 and Kunpeng509 SoC. Signed-off-by: Zhen Lei --- arch/arm/mach-hisi/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 2e980f834a6aa1b..c724acc5c642b97 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -55,6 +55,14 @@ config ARCH_HIX5HD2 help Support for Hisilicon HIX5HD2 SoC family +config ARCH_KUNPENG50X + bool "Hisilicon Kunpeng50x family" + depends on ARCH_MULTI_V7 + select ARCH_FLATMEM_ENABLE + select ARCH_HAS_HOLES_MEMORYMODEL if SPARSEMEM + help + Support for Hisilicon Kunpeng506 and Kunpeng509 SoC family + config ARCH_SD5203 bool "Hisilicon SD5203 family" depends on ARCH_MULTI_V5 -- 2.26.0.106.g9fadedd
