[PATCH 1/2] MIPS: generic: Add support for MIPSfpga

[Zubair Lutfullah Kakakhel]

Add support for the MIPSfpga platform to generic kernel.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
---
 arch/mips/boot/dts/xilfpga/Makefile|  2 +-
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts   |  8 
 arch/mips/configs/generic/board-xilfpga.config | 19 +++
 arch/mips/generic/Kconfig  |  6 ++
 arch/mips/generic/vmlinux.its.S| 25 +
 5 files changed, 59 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/configs/generic/board-xilfpga.config

diff --git a/arch/mips/boot/dts/xilfpga/Makefile 
b/arch/mips/boot/dts/xilfpga/Makefile
index 913a752..bbf8fb6 100644
--- a/arch/mips/boot/dts/xilfpga/Makefile
+++ b/arch/mips/boot/dts/xilfpga/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_XILFPGA_NEXYS4DDR)+= nexys4ddr.dtb
+dtb-$(CONFIG_FIT_IMAGE_FDT_XILFPGA)+= nexys4ddr.dtb
 
 obj-y  += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
 
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 09a62f2..8050e84 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -4,6 +4,14 @@
 
 / {
compatible = "digilent,nexys4ddr";
+
+   aliases {
+   serial0 = _uart16550;
+   };
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   stdout-path = "serial0:115200n8";
+   };
 
memory {
device_type = "memory";
diff --git a/arch/mips/configs/generic/board-xilfpga.config 
b/arch/mips/configs/generic/board-xilfpga.config
new file mode 100644
index 000..786d387
--- /dev/null
+++ b/arch/mips/configs/generic/board-xilfpga.config
@@ -0,0 +1,19 @@
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_XILINX=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_FIT_IMAGE_FDT_XILFPGA=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_XILINX=y
+CONFIG_SENSORS_ADT7410=y
+CONFIG_TMPFS=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_NETDEVICES=y
+CONFIG_XILINX_EMACLITE=y
+CONFIG_SMSC_PHY=y
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index a606b3f..26201e2 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -16,4 +16,10 @@ config LEGACY_BOARD_SEAD3
  Enable this to include support for booting on MIPS SEAD-3 FPGA-based
  development boards, which boot using a legacy boot protocol.
 
+config FIT_IMAGE_FDT_XILFPGA
+   bool "Include FDT for Xilfpga"
+   help
+ Enable this to include the FDT for the MIPSfpga platform
+ from Imagination Technologies in the FIT kernel image.
+
 endif
diff --git a/arch/mips/generic/vmlinux.its.S b/arch/mips/generic/vmlinux.its.S
index f67fbf1..b2daa7e 100644
--- a/arch/mips/generic/vmlinux.its.S
+++ b/arch/mips/generic/vmlinux.its.S
@@ -29,3 +29,28 @@
};
};
 };
+
+#ifdef CONFIG_FIT_IMAGE_FDT_XILFPGA
+/ {
+   images {
+   fdt@xilfpga {
+   description = "MIPSfpga (xilfpga) Device Tree";
+   data = /incbin/("boot/dts/xilfpga/nexys4ddr.dtb");
+   type = "flat_dt";
+   arch = "mips";
+   compression = "none";
+   hash@0 {
+   algo = "sha1";
+   };
+   };
+   };
+
+   configurations {
+   conf@xilfpga {
+   description = "MIPSfpga Linux kernel";
+   kernel = "kernel@0";
+   fdt = "fdt@xilfpga";
+   };
+   };
+};
+#endif /* CONFIG_FIT_IMAGE_FDT_XILFPGA */
-- 
2.10.2

[PATCH 1/2] MIPS: generic: Add support for MIPSfpga

[Zubair Lutfullah Kakakhel]

Add support for the MIPSfpga platform to generic kernel.

Signed-off-by: Zubair Lutfullah Kakakhel 
---
 arch/mips/boot/dts/xilfpga/Makefile|  2 +-
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts   |  8 
 arch/mips/configs/generic/board-xilfpga.config | 19 +++
 arch/mips/generic/Kconfig  |  6 ++
 arch/mips/generic/vmlinux.its.S| 25 +
 5 files changed, 59 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/configs/generic/board-xilfpga.config

diff --git a/arch/mips/boot/dts/xilfpga/Makefile 
b/arch/mips/boot/dts/xilfpga/Makefile
index 913a752..bbf8fb6 100644
--- a/arch/mips/boot/dts/xilfpga/Makefile
+++ b/arch/mips/boot/dts/xilfpga/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_XILFPGA_NEXYS4DDR)+= nexys4ddr.dtb
+dtb-$(CONFIG_FIT_IMAGE_FDT_XILFPGA)+= nexys4ddr.dtb
 
 obj-y  += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
 
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 09a62f2..8050e84 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -4,6 +4,14 @@
 
 / {
compatible = "digilent,nexys4ddr";
+
+   aliases {
+   serial0 = _uart16550;
+   };
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   stdout-path = "serial0:115200n8";
+   };
 
memory {
device_type = "memory";
diff --git a/arch/mips/configs/generic/board-xilfpga.config 
b/arch/mips/configs/generic/board-xilfpga.config
new file mode 100644
index 000..786d387
--- /dev/null
+++ b/arch/mips/configs/generic/board-xilfpga.config
@@ -0,0 +1,19 @@
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_XILINX=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_FIT_IMAGE_FDT_XILFPGA=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_XILINX=y
+CONFIG_SENSORS_ADT7410=y
+CONFIG_TMPFS=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_NETDEVICES=y
+CONFIG_XILINX_EMACLITE=y
+CONFIG_SMSC_PHY=y
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index a606b3f..26201e2 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -16,4 +16,10 @@ config LEGACY_BOARD_SEAD3
  Enable this to include support for booting on MIPS SEAD-3 FPGA-based
  development boards, which boot using a legacy boot protocol.
 
+config FIT_IMAGE_FDT_XILFPGA
+   bool "Include FDT for Xilfpga"
+   help
+ Enable this to include the FDT for the MIPSfpga platform
+ from Imagination Technologies in the FIT kernel image.
+
 endif
diff --git a/arch/mips/generic/vmlinux.its.S b/arch/mips/generic/vmlinux.its.S
index f67fbf1..b2daa7e 100644
--- a/arch/mips/generic/vmlinux.its.S
+++ b/arch/mips/generic/vmlinux.its.S
@@ -29,3 +29,28 @@
};
};
 };
+
+#ifdef CONFIG_FIT_IMAGE_FDT_XILFPGA
+/ {
+   images {
+   fdt@xilfpga {
+   description = "MIPSfpga (xilfpga) Device Tree";
+   data = /incbin/("boot/dts/xilfpga/nexys4ddr.dtb");
+   type = "flat_dt";
+   arch = "mips";
+   compression = "none";
+   hash@0 {
+   algo = "sha1";
+   };
+   };
+   };
+
+   configurations {
+   conf@xilfpga {
+   description = "MIPSfpga Linux kernel";
+   kernel = "kernel@0";
+   fdt = "fdt@xilfpga";
+   };
+   };
+};
+#endif /* CONFIG_FIT_IMAGE_FDT_XILFPGA */
-- 
2.10.2

[PATCH 0/2] MIPS: Xilfpga: Switch to generic kernel

[Zubair Lutfullah Kakakhel]

Hi,

Couple of patches that convert the MIPSfpga platform to using
the generic kernels

Based on v4.11-rc4.

Regards,
ZubairLK

Zubair Lutfullah Kakakhel (2):
  MIPS: generic: Add support for MIPSfpga
  MIPS: Xilfpga: Switch to using generic defconfigs

 arch/mips/Kbuild.platforms |  1 -
 arch/mips/Kconfig  | 24 -
 arch/mips/Makefile |  4 ++
 arch/mips/boot/dts/xilfpga/Makefile|  2 +-
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts   |  8 +++
 arch/mips/configs/generic/board-xilfpga.config | 19 +++
 arch/mips/configs/xilfpga_defconfig| 75 --
 arch/mips/generic/Kconfig  |  6 +++
 arch/mips/generic/vmlinux.its.S| 25 +
 arch/mips/xilfpga/Kconfig  |  9 
 arch/mips/xilfpga/Makefile |  7 ---
 arch/mips/xilfpga/Platform |  3 --
 arch/mips/xilfpga/init.c   | 44 ---
 arch/mips/xilfpga/intc.c   | 22 
 arch/mips/xilfpga/time.c   | 41 --
 15 files changed, 63 insertions(+), 227 deletions(-)
 create mode 100644 arch/mips/configs/generic/board-xilfpga.config
 delete mode 100644 arch/mips/configs/xilfpga_defconfig
 delete mode 100644 arch/mips/xilfpga/Kconfig
 delete mode 100644 arch/mips/xilfpga/Makefile
 delete mode 100644 arch/mips/xilfpga/Platform
 delete mode 100644 arch/mips/xilfpga/init.c
 delete mode 100644 arch/mips/xilfpga/intc.c
 delete mode 100644 arch/mips/xilfpga/time.c

-- 
2.10.2

[PATCH 2/2] MIPS: Xilfpga: Switch to using generic defconfigs

[Zubair Lutfullah Kakakhel]

Use the generic platform code and remove arch/mips/xilfpga

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
---
 arch/mips/Kbuild.platforms  |  1 -
 arch/mips/Kconfig   | 24 
 arch/mips/Makefile  |  4 ++
 arch/mips/configs/xilfpga_defconfig | 75 -
 arch/mips/xilfpga/Kconfig   |  9 -
 arch/mips/xilfpga/Makefile  |  7 
 arch/mips/xilfpga/Platform  |  3 --
 arch/mips/xilfpga/init.c| 44 --
 arch/mips/xilfpga/intc.c| 22 ---
 arch/mips/xilfpga/time.c| 41 
 10 files changed, 4 insertions(+), 226 deletions(-)
 delete mode 100644 arch/mips/configs/xilfpga_defconfig
 delete mode 100644 arch/mips/xilfpga/Kconfig
 delete mode 100644 arch/mips/xilfpga/Makefile
 delete mode 100644 arch/mips/xilfpga/Platform
 delete mode 100644 arch/mips/xilfpga/init.c
 delete mode 100644 arch/mips/xilfpga/intc.c
 delete mode 100644 arch/mips/xilfpga/time.c

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index f5f1bdb..ac7ad54 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -34,7 +34,6 @@ platforms += sibyte
 platforms += sni
 platforms += txx9
 platforms += vr41xx
-platforms += xilfpga
 
 # include the platform specific files
 include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a008a9f..d8f152e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -463,29 +463,6 @@ config MACH_PISTACHIO
help
  This enables support for the IMG Pistachio SoC platform.
 
-config MACH_XILFPGA
-   bool "MIPSfpga Xilinx based boards"
-   select BOOT_ELF32
-   select BOOT_RAW
-   select BUILTIN_DTB
-   select CEVT_R4K
-   select COMMON_CLK
-   select CSRC_R4K
-   select GPIOLIB
-   select IRQ_MIPS_CPU
-   select LIBFDT
-   select MIPS_CPU_SCACHE
-   select SYS_HAS_EARLY_PRINTK
-   select SYS_HAS_CPU_MIPS32_R2
-   select SYS_SUPPORTS_32BIT_KERNEL
-   select SYS_SUPPORTS_LITTLE_ENDIAN
-   select SYS_SUPPORTS_ZBOOT_UART16550
-   select USE_OF
-   select USE_GENERIC_EARLY_PRINTK_8250
-   select XILINX_INTC
-   help
- This enables support for the IMG University Program MIPSfpga platform.
-
 config MIPS_MALTA
bool "MIPS Malta board"
select ARCH_MAY_HAVE_PC_FDC
@@ -1029,7 +1006,6 @@ source "arch/mips/loongson32/Kconfig"
 source "arch/mips/loongson64/Kconfig"
 source "arch/mips/netlogic/Kconfig"
 source "arch/mips/paravirt/Kconfig"
-source "arch/mips/xilfpga/Kconfig"
 
 endmenu
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 8ef9c02..ce65dea 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -501,6 +501,10 @@ $(generic_config_dir)/%.config: ;
 # now that the boards have been converted to use the generic kernel they are
 # wrappers around the generic rules above.
 #
+.PHONY: xilfpga_defconfig
+xilfpga_defconfig:
+   $(Q)$(MAKE) 32r2el_defconfig BOARDS=xilfpga
+
 .PHONY: sead3_defconfig
 sead3_defconfig:
$(Q)$(MAKE) 32r2el_defconfig BOARDS=sead-3
diff --git a/arch/mips/configs/xilfpga_defconfig 
b/arch/mips/configs/xilfpga_defconfig
deleted file mode 100644
index 829c637..000
--- a/arch/mips/configs/xilfpga_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_MACH_XILFPGA=y
-# CONFIG_COMPACTION is not set
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-# CONFIG_BLOCK is not set
-# CONFIG_SUSPEND is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-# CONFIG_ALLOW_DEV_COREDUMP is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_CORE is not set
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_EZCHIP is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_NETRONOME is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_RENESAS is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_SYNOPSYS is not set
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_XILINX_EMACLITE=y
-CONFIG_SMSC_PHY=y
-# CONFIG_WLAN is not

[PATCH 0/2] MIPS: Xilfpga: Switch to generic kernel

[Zubair Lutfullah Kakakhel]

Hi,

Couple of patches that convert the MIPSfpga platform to using
the generic kernels

Based on v4.11-rc4.

Regards,
ZubairLK

Zubair Lutfullah Kakakhel (2):
  MIPS: generic: Add support for MIPSfpga
  MIPS: Xilfpga: Switch to using generic defconfigs

 arch/mips/Kbuild.platforms |  1 -
 arch/mips/Kconfig  | 24 -
 arch/mips/Makefile |  4 ++
 arch/mips/boot/dts/xilfpga/Makefile|  2 +-
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts   |  8 +++
 arch/mips/configs/generic/board-xilfpga.config | 19 +++
 arch/mips/configs/xilfpga_defconfig| 75 --
 arch/mips/generic/Kconfig  |  6 +++
 arch/mips/generic/vmlinux.its.S| 25 +
 arch/mips/xilfpga/Kconfig  |  9 
 arch/mips/xilfpga/Makefile |  7 ---
 arch/mips/xilfpga/Platform |  3 --
 arch/mips/xilfpga/init.c   | 44 ---
 arch/mips/xilfpga/intc.c   | 22 
 arch/mips/xilfpga/time.c   | 41 --
 15 files changed, 63 insertions(+), 227 deletions(-)
 create mode 100644 arch/mips/configs/generic/board-xilfpga.config
 delete mode 100644 arch/mips/configs/xilfpga_defconfig
 delete mode 100644 arch/mips/xilfpga/Kconfig
 delete mode 100644 arch/mips/xilfpga/Makefile
 delete mode 100644 arch/mips/xilfpga/Platform
 delete mode 100644 arch/mips/xilfpga/init.c
 delete mode 100644 arch/mips/xilfpga/intc.c
 delete mode 100644 arch/mips/xilfpga/time.c

-- 
2.10.2

[PATCH 2/2] MIPS: Xilfpga: Switch to using generic defconfigs

[Zubair Lutfullah Kakakhel]

Use the generic platform code and remove arch/mips/xilfpga

Signed-off-by: Zubair Lutfullah Kakakhel 
---
 arch/mips/Kbuild.platforms  |  1 -
 arch/mips/Kconfig   | 24 
 arch/mips/Makefile  |  4 ++
 arch/mips/configs/xilfpga_defconfig | 75 -
 arch/mips/xilfpga/Kconfig   |  9 -
 arch/mips/xilfpga/Makefile  |  7 
 arch/mips/xilfpga/Platform  |  3 --
 arch/mips/xilfpga/init.c| 44 --
 arch/mips/xilfpga/intc.c| 22 ---
 arch/mips/xilfpga/time.c| 41 
 10 files changed, 4 insertions(+), 226 deletions(-)
 delete mode 100644 arch/mips/configs/xilfpga_defconfig
 delete mode 100644 arch/mips/xilfpga/Kconfig
 delete mode 100644 arch/mips/xilfpga/Makefile
 delete mode 100644 arch/mips/xilfpga/Platform
 delete mode 100644 arch/mips/xilfpga/init.c
 delete mode 100644 arch/mips/xilfpga/intc.c
 delete mode 100644 arch/mips/xilfpga/time.c

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index f5f1bdb..ac7ad54 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -34,7 +34,6 @@ platforms += sibyte
 platforms += sni
 platforms += txx9
 platforms += vr41xx
-platforms += xilfpga
 
 # include the platform specific files
 include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a008a9f..d8f152e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -463,29 +463,6 @@ config MACH_PISTACHIO
help
  This enables support for the IMG Pistachio SoC platform.
 
-config MACH_XILFPGA
-   bool "MIPSfpga Xilinx based boards"
-   select BOOT_ELF32
-   select BOOT_RAW
-   select BUILTIN_DTB
-   select CEVT_R4K
-   select COMMON_CLK
-   select CSRC_R4K
-   select GPIOLIB
-   select IRQ_MIPS_CPU
-   select LIBFDT
-   select MIPS_CPU_SCACHE
-   select SYS_HAS_EARLY_PRINTK
-   select SYS_HAS_CPU_MIPS32_R2
-   select SYS_SUPPORTS_32BIT_KERNEL
-   select SYS_SUPPORTS_LITTLE_ENDIAN
-   select SYS_SUPPORTS_ZBOOT_UART16550
-   select USE_OF
-   select USE_GENERIC_EARLY_PRINTK_8250
-   select XILINX_INTC
-   help
- This enables support for the IMG University Program MIPSfpga platform.
-
 config MIPS_MALTA
bool "MIPS Malta board"
select ARCH_MAY_HAVE_PC_FDC
@@ -1029,7 +1006,6 @@ source "arch/mips/loongson32/Kconfig"
 source "arch/mips/loongson64/Kconfig"
 source "arch/mips/netlogic/Kconfig"
 source "arch/mips/paravirt/Kconfig"
-source "arch/mips/xilfpga/Kconfig"
 
 endmenu
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 8ef9c02..ce65dea 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -501,6 +501,10 @@ $(generic_config_dir)/%.config: ;
 # now that the boards have been converted to use the generic kernel they are
 # wrappers around the generic rules above.
 #
+.PHONY: xilfpga_defconfig
+xilfpga_defconfig:
+   $(Q)$(MAKE) 32r2el_defconfig BOARDS=xilfpga
+
 .PHONY: sead3_defconfig
 sead3_defconfig:
$(Q)$(MAKE) 32r2el_defconfig BOARDS=sead-3
diff --git a/arch/mips/configs/xilfpga_defconfig 
b/arch/mips/configs/xilfpga_defconfig
deleted file mode 100644
index 829c637..000
--- a/arch/mips/configs/xilfpga_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_MACH_XILFPGA=y
-# CONFIG_COMPACTION is not set
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-# CONFIG_BLOCK is not set
-# CONFIG_SUSPEND is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-# CONFIG_ALLOW_DEV_COREDUMP is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_CORE is not set
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_EZCHIP is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_NETRONOME is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_RENESAS is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_SYNOPSYS is not set
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_XILINX_EMACLITE=y
-CONFIG_SMSC_PHY=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not se

Re: [PATCH] MIPS: NI 169445 board support

[Zubair Lutfullah Kakakhel]

Hi,

On 12/02/2016 03:42 PM, Nathan Sullivan wrote:

Support the National Instruments 169445 board.


Interesting patch.

But do you happen to have a link to a description of the board?
I couldn't find anything with a quick search.
Perhaps the public name is something else?

Thanks,
ZubairLK



Signed-off-by: Nathan Sullivan 
---
"gpio: mmio: add support for NI 169445 NAND GPIO" and
"devicetree: add vendor prefix for National Instruments" are required for the
NAND on this board to work.

 Documentation/devicetree/bindings/mips/ni.txt |   7 ++
 arch/mips/Kbuild.platforms|   1 +
 arch/mips/Kconfig |  26 ++
 arch/mips/boot/dts/Makefile   |   1 +
 arch/mips/boot/dts/ni/169445.dts  |  99 +
 arch/mips/boot/dts/ni/Makefile|   9 ++
 arch/mips/configs/ni169445_defconfig  | 120 ++
 arch/mips/ni169445/169445-console.c   |  38 
 arch/mips/ni169445/169445-init.c  |  39 +
 arch/mips/ni169445/169445-int.c   |  34 
 arch/mips/ni169445/169445-setup.c |  58 +
 arch/mips/ni169445/169445-time.c  |  35 
 arch/mips/ni169445/Makefile   |   9 ++
 arch/mips/ni169445/Platform   |   6 ++
 14 files changed, 482 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/ni.txt
 create mode 100644 arch/mips/boot/dts/ni/169445.dts
 create mode 100644 arch/mips/boot/dts/ni/Makefile
 create mode 100644 arch/mips/configs/ni169445_defconfig
 create mode 100644 arch/mips/ni169445/169445-console.c
 create mode 100644 arch/mips/ni169445/169445-init.c
 create mode 100644 arch/mips/ni169445/169445-int.c
 create mode 100644 arch/mips/ni169445/169445-setup.c
 create mode 100644 arch/mips/ni169445/169445-time.c
 create mode 100644 arch/mips/ni169445/Makefile
 create mode 100644 arch/mips/ni169445/Platform

diff --git a/Documentation/devicetree/bindings/mips/ni.txt 
b/Documentation/devicetree/bindings/mips/ni.txt
new file mode 100644
index 000..722bf2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ni.txt
@@ -0,0 +1,7 @@
+National Instruments MIPS platforms
+
+required root node properties:
+   - compatible: must be "ni,169445"
+
+CPU Nodes
+   - compatible: must be "mti,mips14KEc"
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index f5f1bdb..f2d7b5c 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -20,6 +20,7 @@ platforms += loongson32
 platforms += loongson64
 platforms += mti-malta
 platforms += netlogic
+platforms += ni169445
 platforms += paravirt
 platforms += pic32
 platforms += pistachio
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3c5bde..d24d11f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -574,6 +574,32 @@ config NXP_STB225
help
 Support for NXP Semiconductors STB225 Development Board.

+config NI_169445
+   bool "NI 169445 board"
+   select ARCH_WANT_OPTIONAL_GPIOLIB
+   select BOOT_ELF32
+   select BOOT_RAW
+   select BUILTIN_DTB
+   select CEVT_R4K
+   select CSRC_R4K
+   select CPU_MIPSR2_IRQ_VI
+   select CPU_MIPSR2_IRQ_EI
+   select DMA_NONCOHERENT
+   select IRQ_MIPS_CPU
+   select LIBFDT
+   select MIPS_MSC
+   select SYS_HAS_CPU_MIPS32_R1
+   select SYS_HAS_CPU_MIPS32_R2
+   select SYS_HAS_EARLY_PRINTK
+   select SYS_SUPPORTS_32BIT_KERNEL
+   select SYS_SUPPORTS_LITTLE_ENDIAN
+   select USE_OF
+   select COMMON_CLK
+   help
+ This enables support for the National Instruments 169445A
+ board.
+
+
 config PMC_MSP
bool "PMC-Sierra MSP chipsets"
select CEVT_R4K
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index fc7a0a9..65a0ad8 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -3,6 +3,7 @@ dts-dirs+= cavium-octeon
 dts-dirs   += ingenic
 dts-dirs   += lantiq
 dts-dirs   += mti
+dts-dirs   += ni
 dts-dirs   += netlogic
 dts-dirs   += pic32
 dts-dirs   += qca
diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
new file mode 100644
index 000..a2b49f9
--- /dev/null
+++ b/arch/mips/boot/dts/ni/169445.dts
@@ -0,0 +1,99 @@
+/dts-v1/;
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "ni,169445";
+
+   cpus {
+   mips-hpt-frequency = <2500>;
+
+   cpu@0 {
+   compatible = "mti,mips14KEc";
+   };
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x0 0x0800>;
+   };
+
+   clocks {
+   baseclk: baseclock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+

Re: [PATCH] MIPS: NI 169445 board support

[Zubair Lutfullah Kakakhel]

Hi,

On 12/02/2016 03:42 PM, Nathan Sullivan wrote:

Support the National Instruments 169445 board.


Interesting patch.

But do you happen to have a link to a description of the board?
I couldn't find anything with a quick search.
Perhaps the public name is something else?

Thanks,
ZubairLK



Signed-off-by: Nathan Sullivan 
---
"gpio: mmio: add support for NI 169445 NAND GPIO" and
"devicetree: add vendor prefix for National Instruments" are required for the
NAND on this board to work.

 Documentation/devicetree/bindings/mips/ni.txt |   7 ++
 arch/mips/Kbuild.platforms|   1 +
 arch/mips/Kconfig |  26 ++
 arch/mips/boot/dts/Makefile   |   1 +
 arch/mips/boot/dts/ni/169445.dts  |  99 +
 arch/mips/boot/dts/ni/Makefile|   9 ++
 arch/mips/configs/ni169445_defconfig  | 120 ++
 arch/mips/ni169445/169445-console.c   |  38 
 arch/mips/ni169445/169445-init.c  |  39 +
 arch/mips/ni169445/169445-int.c   |  34 
 arch/mips/ni169445/169445-setup.c |  58 +
 arch/mips/ni169445/169445-time.c  |  35 
 arch/mips/ni169445/Makefile   |   9 ++
 arch/mips/ni169445/Platform   |   6 ++
 14 files changed, 482 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/ni.txt
 create mode 100644 arch/mips/boot/dts/ni/169445.dts
 create mode 100644 arch/mips/boot/dts/ni/Makefile
 create mode 100644 arch/mips/configs/ni169445_defconfig
 create mode 100644 arch/mips/ni169445/169445-console.c
 create mode 100644 arch/mips/ni169445/169445-init.c
 create mode 100644 arch/mips/ni169445/169445-int.c
 create mode 100644 arch/mips/ni169445/169445-setup.c
 create mode 100644 arch/mips/ni169445/169445-time.c
 create mode 100644 arch/mips/ni169445/Makefile
 create mode 100644 arch/mips/ni169445/Platform

diff --git a/Documentation/devicetree/bindings/mips/ni.txt 
b/Documentation/devicetree/bindings/mips/ni.txt
new file mode 100644
index 000..722bf2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ni.txt
@@ -0,0 +1,7 @@
+National Instruments MIPS platforms
+
+required root node properties:
+   - compatible: must be "ni,169445"
+
+CPU Nodes
+   - compatible: must be "mti,mips14KEc"
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index f5f1bdb..f2d7b5c 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -20,6 +20,7 @@ platforms += loongson32
 platforms += loongson64
 platforms += mti-malta
 platforms += netlogic
+platforms += ni169445
 platforms += paravirt
 platforms += pic32
 platforms += pistachio
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3c5bde..d24d11f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -574,6 +574,32 @@ config NXP_STB225
help
 Support for NXP Semiconductors STB225 Development Board.

+config NI_169445
+   bool "NI 169445 board"
+   select ARCH_WANT_OPTIONAL_GPIOLIB
+   select BOOT_ELF32
+   select BOOT_RAW
+   select BUILTIN_DTB
+   select CEVT_R4K
+   select CSRC_R4K
+   select CPU_MIPSR2_IRQ_VI
+   select CPU_MIPSR2_IRQ_EI
+   select DMA_NONCOHERENT
+   select IRQ_MIPS_CPU
+   select LIBFDT
+   select MIPS_MSC
+   select SYS_HAS_CPU_MIPS32_R1
+   select SYS_HAS_CPU_MIPS32_R2
+   select SYS_HAS_EARLY_PRINTK
+   select SYS_SUPPORTS_32BIT_KERNEL
+   select SYS_SUPPORTS_LITTLE_ENDIAN
+   select USE_OF
+   select COMMON_CLK
+   help
+ This enables support for the National Instruments 169445A
+ board.
+
+
 config PMC_MSP
bool "PMC-Sierra MSP chipsets"
select CEVT_R4K
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index fc7a0a9..65a0ad8 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -3,6 +3,7 @@ dts-dirs+= cavium-octeon
 dts-dirs   += ingenic
 dts-dirs   += lantiq
 dts-dirs   += mti
+dts-dirs   += ni
 dts-dirs   += netlogic
 dts-dirs   += pic32
 dts-dirs   += qca
diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
new file mode 100644
index 000..a2b49f9
--- /dev/null
+++ b/arch/mips/boot/dts/ni/169445.dts
@@ -0,0 +1,99 @@
+/dts-v1/;
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "ni,169445";
+
+   cpus {
+   mips-hpt-frequency = <2500>;
+
+   cpu@0 {
+   compatible = "mti,mips14KEc";
+   };
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x0 0x0800>;
+   };
+
+   clocks {
+   baseclk: baseclock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = 

[PATCH 5/6] MIPS: xilfpga: Add DT node for AXI emaclite

[Zubair Lutfullah Kakakhel]

The xilfpga platform has a Xilinx AXI emaclite block.

Add the DT node to use it.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index f5ebab8..09a62f2 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -42,6 +42,32 @@
xlnx,tri-default = <0x>;
} ;
 
+   axi_ethernetlite: ethernet@10e0 {
+   compatible = "xlnx,xps-ethernetlite-3.00.a";
+   device_type = "network";
+   interrupt-parent = <_intc>;
+   interrupts = <1>;
+   phy-handle = <>;
+   reg = <0x10e0 0x1>;
+   xlnx,duplex = <0x1>;
+   xlnx,include-global-buffers = <0x1>;
+   xlnx,include-internal-loopback = <0x0>;
+   xlnx,include-mdio = <0x1>;
+   xlnx,instance = "axi_ethernetlite_inst";
+   xlnx,rx-ping-pong = <0x1>;
+   xlnx,s-axi-id-width = <0x1>;
+   xlnx,tx-ping-pong = <0x1>;
+   xlnx,use-internal = <0x0>;
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   phy0: phy@1 {
+   device_type = "ethernet-phy";
+   reg = <1>;
+   };
+   };
+   };
+
axi_uart16550: serial@1040 {
compatible = "ns16550a";
reg = <0x1040 0x1>;
-- 
2.10.2

[PATCH 1/6] MIPS: xilfpga: Use irqchip instead of the legacy way

[Zubair Lutfullah Kakakhel]

This prepares the code to use the Xilinx Interrupt Controller
driver in drivers/irqchip/irq-xilinx-intc.c

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
---
 arch/mips/xilfpga/intc.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/mips/xilfpga/intc.c b/arch/mips/xilfpga/intc.c
index c4d1a71..a127cca 100644
--- a/arch/mips/xilfpga/intc.c
+++ b/arch/mips/xilfpga/intc.c
@@ -11,15 +11,12 @@
 
 #include 
 #include 
+#include 
 
 #include 
 
-static struct of_device_id of_irq_ids[] __initdata = {
-   { .compatible = "mti,cpu-interrupt-controller", .data = 
mips_cpu_irq_of_init },
-   {},
-};
 
 void __init arch_init_irq(void)
 {
-   of_irq_init(of_irq_ids);
+   irqchip_init();
 }
-- 
2.10.2

[PATCH 1/6] MIPS: xilfpga: Use irqchip instead of the legacy way

[Zubair Lutfullah Kakakhel]

This prepares the code to use the Xilinx Interrupt Controller
driver in drivers/irqchip/irq-xilinx-intc.c

Signed-off-by: Zubair Lutfullah Kakakhel 
---
 arch/mips/xilfpga/intc.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/mips/xilfpga/intc.c b/arch/mips/xilfpga/intc.c
index c4d1a71..a127cca 100644
--- a/arch/mips/xilfpga/intc.c
+++ b/arch/mips/xilfpga/intc.c
@@ -11,15 +11,12 @@
 
 #include 
 #include 
+#include 
 
 #include 
 
-static struct of_device_id of_irq_ids[] __initdata = {
-   { .compatible = "mti,cpu-interrupt-controller", .data = 
mips_cpu_irq_of_init },
-   {},
-};
 
 void __init arch_init_irq(void)
 {
-   of_irq_init(of_irq_ids);
+   irqchip_init();
 }
-- 
2.10.2

[PATCH 5/6] MIPS: xilfpga: Add DT node for AXI emaclite

[Zubair Lutfullah Kakakhel]

The xilfpga platform has a Xilinx AXI emaclite block.

Add the DT node to use it.

Signed-off-by: Zubair Lutfullah Kakakhel 
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index f5ebab8..09a62f2 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -42,6 +42,32 @@
xlnx,tri-default = <0x>;
} ;
 
+   axi_ethernetlite: ethernet@10e0 {
+   compatible = "xlnx,xps-ethernetlite-3.00.a";
+   device_type = "network";
+   interrupt-parent = <_intc>;
+   interrupts = <1>;
+   phy-handle = <>;
+   reg = <0x10e0 0x1>;
+   xlnx,duplex = <0x1>;
+   xlnx,include-global-buffers = <0x1>;
+   xlnx,include-internal-loopback = <0x0>;
+   xlnx,include-mdio = <0x1>;
+   xlnx,instance = "axi_ethernetlite_inst";
+   xlnx,rx-ping-pong = <0x1>;
+   xlnx,s-axi-id-width = <0x1>;
+   xlnx,tx-ping-pong = <0x1>;
+   xlnx,use-internal = <0x0>;
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   phy0: phy@1 {
+   device_type = "ethernet-phy";
+   reg = <1>;
+   };
+   };
+   };
+
axi_uart16550: serial@1040 {
compatible = "ns16550a";
reg = <0x1040 0x1>;
-- 
2.10.2

[PATCH 3/6] MIPS: xilfpga: Update DT node and specify uart irq

[Zubair Lutfullah Kakakhel]

Update the DT node with the UART irq

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 8db660b..d285c8d 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -50,6 +50,9 @@
reg-offset = <0x1000>;
 
clocks  = <>;
+
+   interrupt-parent = <_intc>;
+   interrupts = <0>;
};
 };
 
-- 
2.10.2

[PATCH 3/6] MIPS: xilfpga: Update DT node and specify uart irq

[Zubair Lutfullah Kakakhel]

Update the DT node with the UART irq

Signed-off-by: Zubair Lutfullah Kakakhel 
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 8db660b..d285c8d 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -50,6 +50,9 @@
reg-offset = <0x1000>;
 
clocks  = <>;
+
+   interrupt-parent = <_intc>;
+   interrupts = <0>;
};
 };
 
-- 
2.10.2

[PATCH 0/6] MIPS: xilfpga: Use irq-xilinx-intc

[Zubair Lutfullah Kakakhel]

Hi,

The interrupt controller driver was in arch/microblaze.
The patches to move the driver out from arch/microblaze
to drivers/irqchip/irq-xilinx-intc.c have now been accepted [1]

Hence, xilfpga can make use of the driver in v4.10.

These patches do the following:
- Use the irqchip driver
- Add Device Tree nodes for various peripherals that were blocked
- Enable those drivers in the defconfig

Based on v4.9-rc6

Regards,
ZubairLK

[1] https://lkml.org/lkml/2016/11/22/186

Zubair Lutfullah Kakakhel (6):
  MIPS: xilfpga: Use irqchip instead of the legacy way
  MIPS: xilfpga: Use Xilinx Interrupt Controller
  MIPS: xilfpga: Update DT node and specify uart irq
  MIPS: xilfpga: Add DT node for AXI I2C
  MIPS: xilfpga: Add DT node for AXI emaclite
  MIPS: xilfpga: Update defconfig

 arch/mips/Kconfig|  1 +
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 63 
 arch/mips/configs/xilfpga_defconfig  | 37 ++-
 arch/mips/xilfpga/intc.c |  7 +---
 4 files changed, 102 insertions(+), 6 deletions(-)

-- 
2.10.2

[PATCH 6/6] MIPS: xilfpga: Update defconfig

[Zubair Lutfullah Kakakhel]

Update defconfig to enable emaclite, i2c and temp sensor on the
xilfpga platform

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
---
 arch/mips/configs/xilfpga_defconfig | 37 -
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/mips/configs/xilfpga_defconfig 
b/arch/mips/configs/xilfpga_defconfig
index ed1dce3..829c637 100644
--- a/arch/mips/configs/xilfpga_defconfig
+++ b/arch/mips/configs/xilfpga_defconfig
@@ -7,6 +7,12 @@ CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 # CONFIG_BLOCK is not set
 # CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -14,6 +20,30 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
 # CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CORE is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_XILINX_EMACLITE=y
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
@@ -25,13 +55,18 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_XILINX=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_ADT7410=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MIPS_PLATFORM_DEVICES is not set
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_PANIC_ON_OOPS=y
 # CONFIG_SCHED_DEBUG is not set
-- 
2.10.2

[PATCH 0/6] MIPS: xilfpga: Use irq-xilinx-intc

[Zubair Lutfullah Kakakhel]

Hi,

The interrupt controller driver was in arch/microblaze.
The patches to move the driver out from arch/microblaze
to drivers/irqchip/irq-xilinx-intc.c have now been accepted [1]

Hence, xilfpga can make use of the driver in v4.10.

These patches do the following:
- Use the irqchip driver
- Add Device Tree nodes for various peripherals that were blocked
- Enable those drivers in the defconfig

Based on v4.9-rc6

Regards,
ZubairLK

[1] https://lkml.org/lkml/2016/11/22/186

Zubair Lutfullah Kakakhel (6):
  MIPS: xilfpga: Use irqchip instead of the legacy way
  MIPS: xilfpga: Use Xilinx Interrupt Controller
  MIPS: xilfpga: Update DT node and specify uart irq
  MIPS: xilfpga: Add DT node for AXI I2C
  MIPS: xilfpga: Add DT node for AXI emaclite
  MIPS: xilfpga: Update defconfig

 arch/mips/Kconfig|  1 +
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 63 
 arch/mips/configs/xilfpga_defconfig  | 37 ++-
 arch/mips/xilfpga/intc.c |  7 +---
 4 files changed, 102 insertions(+), 6 deletions(-)

-- 
2.10.2

[PATCH 6/6] MIPS: xilfpga: Update defconfig

[Zubair Lutfullah Kakakhel]

Update defconfig to enable emaclite, i2c and temp sensor on the
xilfpga platform

Signed-off-by: Zubair Lutfullah Kakakhel 
---
 arch/mips/configs/xilfpga_defconfig | 37 -
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/mips/configs/xilfpga_defconfig 
b/arch/mips/configs/xilfpga_defconfig
index ed1dce3..829c637 100644
--- a/arch/mips/configs/xilfpga_defconfig
+++ b/arch/mips/configs/xilfpga_defconfig
@@ -7,6 +7,12 @@ CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 # CONFIG_BLOCK is not set
 # CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -14,6 +20,30 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
 # CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CORE is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_XILINX_EMACLITE=y
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
@@ -25,13 +55,18 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_XILINX=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_ADT7410=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MIPS_PLATFORM_DEVICES is not set
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_PANIC_ON_OOPS=y
 # CONFIG_SCHED_DEBUG is not set
-- 
2.10.2

[PATCH 2/6] MIPS: xilfpga: Use Xilinx Interrupt Controller

[Zubair Lutfullah Kakakhel]

IRQs from peripherals such as i2c/uart/ethernet come via
the AXI Interrupt controller.

Select it in Kconfig for xilfpga and add the DT node

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
---
 arch/mips/Kconfig|  1 +
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 12 
 2 files changed, 13 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3c5bde..3d681c6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -478,6 +478,7 @@ config MACH_XILFPGA
select SYS_SUPPORTS_ZBOOT_UART16550
select USE_OF
select USE_GENERIC_EARLY_PRINTK_8250
+   select XILINX_INTC
help
  This enables support for the IMG University Program MIPSfpga platform.
 
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 48d2112..8db660b 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -17,6 +17,18 @@
compatible = "mti,cpu-interrupt-controller";
};
 
+   axi_intc: interrupt-controller@1020 {
+   #interrupt-cells = <1>;
+   compatible = "xlnx,xps-intc-1.00.a";
+   interrupt-controller;
+   reg = <0x1020 0x1>;
+   xlnx,kind-of-intr = <0x0>;
+   xlnx,num-intr-inputs = <0x6>;
+
+   interrupt-parent = <>;
+   interrupts = <6>;
+   };
+
axi_gpio: gpio@1060 {
#gpio-cells = <1>;
compatible = "xlnx,xps-gpio-1.00.a";
-- 
2.10.2

[PATCH 4/6] MIPS: xilfpga: Add DT node for AXI I2C

[Zubair Lutfullah Kakakhel]

The xilfpga platform has an AXI I2C Bus master with a temperature
sensor connected to it.

Add the device tree node to use them.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index d285c8d..f5ebab8 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -54,6 +54,28 @@
interrupt-parent = <_intc>;
interrupts = <0>;
};
+
+   axi_i2c: i2c@10A0 {
+   compatible = "xlnx,xps-iic-2.00.a";
+   interrupt-parent = <_intc>;
+   interrupts = <4>;
+   reg = < 0x10A0 0x1 >;
+   clocks = <>;
+   xlnx,clk-freq = <0x5f5e100>;
+   xlnx,family = "Artix7";
+   xlnx,gpo-width = <0x1>;
+   xlnx,iic-freq = <0x186a0>;
+   xlnx,scl-inertial-delay = <0x0>;
+   xlnx,sda-inertial-delay = <0x0>;
+   xlnx,ten-bit-adr = <0x0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ad7420@4B {
+   compatible = "adi,adt7420";
+   reg = <0x4B>;
+   };
+   } ;
 };
 
  {
-- 
2.10.2

[PATCH 2/6] MIPS: xilfpga: Use Xilinx Interrupt Controller

[Zubair Lutfullah Kakakhel]

IRQs from peripherals such as i2c/uart/ethernet come via
the AXI Interrupt controller.

Select it in Kconfig for xilfpga and add the DT node

Signed-off-by: Zubair Lutfullah Kakakhel 
---
 arch/mips/Kconfig|  1 +
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 12 
 2 files changed, 13 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3c5bde..3d681c6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -478,6 +478,7 @@ config MACH_XILFPGA
select SYS_SUPPORTS_ZBOOT_UART16550
select USE_OF
select USE_GENERIC_EARLY_PRINTK_8250
+   select XILINX_INTC
help
  This enables support for the IMG University Program MIPSfpga platform.
 
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 48d2112..8db660b 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -17,6 +17,18 @@
compatible = "mti,cpu-interrupt-controller";
};
 
+   axi_intc: interrupt-controller@1020 {
+   #interrupt-cells = <1>;
+   compatible = "xlnx,xps-intc-1.00.a";
+   interrupt-controller;
+   reg = <0x1020 0x1>;
+   xlnx,kind-of-intr = <0x0>;
+   xlnx,num-intr-inputs = <0x6>;
+
+   interrupt-parent = <>;
+   interrupts = <6>;
+   };
+
axi_gpio: gpio@1060 {
#gpio-cells = <1>;
compatible = "xlnx,xps-gpio-1.00.a";
-- 
2.10.2

[PATCH 4/6] MIPS: xilfpga: Add DT node for AXI I2C

[Zubair Lutfullah Kakakhel]

The xilfpga platform has an AXI I2C Bus master with a temperature
sensor connected to it.

Add the device tree node to use them.

Signed-off-by: Zubair Lutfullah Kakakhel 
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index d285c8d..f5ebab8 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -54,6 +54,28 @@
interrupt-parent = <_intc>;
interrupts = <0>;
};
+
+   axi_i2c: i2c@10A0 {
+   compatible = "xlnx,xps-iic-2.00.a";
+   interrupt-parent = <_intc>;
+   interrupts = <4>;
+   reg = < 0x10A0 0x1 >;
+   clocks = <>;
+   xlnx,clk-freq = <0x5f5e100>;
+   xlnx,family = "Artix7";
+   xlnx,gpo-width = <0x1>;
+   xlnx,iic-freq = <0x186a0>;
+   xlnx,scl-inertial-delay = <0x0>;
+   xlnx,sda-inertial-delay = <0x0>;
+   xlnx,ten-bit-adr = <0x0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ad7420@4B {
+   compatible = "adi,adt7420";
+   reg = <0x4B>;
+   };
+   } ;
 };
 
  {
-- 
2.10.2

Re: [Patch v7 0/7] microblaze/PowerPC: Move irq-xilinx to irqchip

[Zubair Lutfullah Kakakhel]

Hi,

On 11/22/2016 10:55 AM, Marc Zyngier wrote:

On 14/11/16 12:13, Zubair Lutfullah Kakakhel wrote:

Hi,

This patch series moves the Xilinx interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then removes another implementation of the driver in arch/powerpc.

This effort results in one common driver usable by mips,microblaze
and powerpc.

Compile tested on microblaze-el.
Tested using qemu-system-ppc using virtix440-ml507
Tested on MIPSfpga platform.

Based on v4.9-rc5


I've queued this for 4.10 with Michal's Acks and TBs.


Thank you very much! :)

ZubairLK



Thanks,

M.

Re: [Patch v7 0/7] microblaze/PowerPC: Move irq-xilinx to irqchip

[Zubair Lutfullah Kakakhel]

Hi,

On 11/22/2016 10:55 AM, Marc Zyngier wrote:

On 14/11/16 12:13, Zubair Lutfullah Kakakhel wrote:

Hi,

This patch series moves the Xilinx interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then removes another implementation of the driver in arch/powerpc.

This effort results in one common driver usable by mips,microblaze
and powerpc.

Compile tested on microblaze-el.
Tested using qemu-system-ppc using virtix440-ml507
Tested on MIPSfpga platform.

Based on v4.9-rc5


I've queued this for 4.10 with Michal's Acks and TBs.


Thank you very much! :)

ZubairLK



Thanks,

M.

Re: [Patch v7 6/7] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

Hi,

On 11/21/2016 02:17 PM, Marc Zyngier wrote:

On 21/11/16 14:05, Zubair Lutfullah Kakakhel wrote:

Hi,

On 11/18/2016 01:29 PM, Thomas Gleixner wrote:

On Mon, 14 Nov 2016, Zubair Lutfullah Kakakhel wrote:


The powerpc dts file does not have the xlnx,kind-of-intr property.
Instead of erroring out, give a warning instead. And attempt to
continue to probe the interrupt controller while assuming
kind-of-intr is 0x0 as a fall back.


This is broken, really. On multiplatform kernels this will try to probe the
chip no matter what.


I'm not sure I understand why this driver will probe on multi-platform kernels
if the compatible string isn't in the DT?



Powerpc already has:

static const struct of_device_id xilinx_intc_match[] __initconst = {
   { .compatible = "xlnx,opb-intc-1.00.c", },
   { .compatible = "xlnx,xps-intc-1.00.a", },
   {}
};

Unless I'm missing something important, then adding those compatible
strings to the driver will just keep stuff working as expected instead of
adding unsafe and broken heuristics.



The last two lines of the driver already specify the compatible strings.

"
IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);
"


Is PPC actually using this infrastructure? It predates the whole
IRQCHIP_DECLARE business by about a decade. You seem to have tested it
using QEMU, so I assume it "just works", but I'd feel more reassured it
you stated so...


I didn't realize that it could have been an issue.
I simply included  and called irqchip_init() in the platform 
code
instead of the previous initialization. Patch 7/7 in this series does that.

And yes I tested it on QEMU. And it does look like it 'just works'.
Without this patch, the UART driver would revert to polling and there would be 
various
error messages about no irq domain found. With this patch, the 'no irq domain 
found'
messages disappeared and the uart driver did get an irq.

Regards,
ZubairLK



Thanks,

M.

Re: [Patch v7 6/7] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

Hi,

On 11/21/2016 02:17 PM, Marc Zyngier wrote:

On 21/11/16 14:05, Zubair Lutfullah Kakakhel wrote:

Hi,

On 11/18/2016 01:29 PM, Thomas Gleixner wrote:

On Mon, 14 Nov 2016, Zubair Lutfullah Kakakhel wrote:


The powerpc dts file does not have the xlnx,kind-of-intr property.
Instead of erroring out, give a warning instead. And attempt to
continue to probe the interrupt controller while assuming
kind-of-intr is 0x0 as a fall back.


This is broken, really. On multiplatform kernels this will try to probe the
chip no matter what.


I'm not sure I understand why this driver will probe on multi-platform kernels
if the compatible string isn't in the DT?



Powerpc already has:

static const struct of_device_id xilinx_intc_match[] __initconst = {
   { .compatible = "xlnx,opb-intc-1.00.c", },
   { .compatible = "xlnx,xps-intc-1.00.a", },
   {}
};

Unless I'm missing something important, then adding those compatible
strings to the driver will just keep stuff working as expected instead of
adding unsafe and broken heuristics.



The last two lines of the driver already specify the compatible strings.

"
IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);
"


Is PPC actually using this infrastructure? It predates the whole
IRQCHIP_DECLARE business by about a decade. You seem to have tested it
using QEMU, so I assume it "just works", but I'd feel more reassured it
you stated so...


I didn't realize that it could have been an issue.
I simply included  and called irqchip_init() in the platform 
code
instead of the previous initialization. Patch 7/7 in this series does that.

And yes I tested it on QEMU. And it does look like it 'just works'.
Without this patch, the UART driver would revert to polling and there would be 
various
error messages about no irq domain found. With this patch, the 'no irq domain 
found'
messages disappeared and the uart driver did get an irq.

Regards,
ZubairLK



Thanks,

M.

Re: [Patch v7 6/7] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

Hi,

On 11/18/2016 01:29 PM, Thomas Gleixner wrote:

On Mon, 14 Nov 2016, Zubair Lutfullah Kakakhel wrote:


The powerpc dts file does not have the xlnx,kind-of-intr property.
Instead of erroring out, give a warning instead. And attempt to
continue to probe the interrupt controller while assuming
kind-of-intr is 0x0 as a fall back.


This is broken, really. On multiplatform kernels this will try to probe the
chip no matter what.


I'm not sure I understand why this driver will probe on multi-platform kernels
if the compatible string isn't in the DT?



Powerpc already has:

static const struct of_device_id xilinx_intc_match[] __initconst = {
   { .compatible = "xlnx,opb-intc-1.00.c", },
   { .compatible = "xlnx,xps-intc-1.00.a", },
   {}
};

Unless I'm missing something important, then adding those compatible
strings to the driver will just keep stuff working as expected instead of
adding unsafe and broken heuristics.



The last two lines of the driver already specify the compatible strings.

"
IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);
"

I'll elaborate on the commit message.

The DT node in arch/powerpc for this driver is

intc_0: interrupt-controller@8180 {
#interrupt-cells = <0x2>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = < 0x8180 0x1 >;
xlnx,num-intr-inputs = <0xc>;
} ;

The DT node in arch/microblaze for this driver is

intc_0: interrupt-controller@8180 {
#interrupt-cells = <0x2>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = < 0x8180 0x1 >;
xlnx,kind-of-intr = <0x100>;  //!
xlnx,num-intr-inputs = <0x9>;
} ;

The PPC driver assumes the kind-of-intr value be 0x0 and doesn't specify it in 
DT.
This patch makes that a fall back case. Instead of completely error-ing out.

Regards,
ZubairLK


Thanks,

tglx

Re: [Patch v7 6/7] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

Hi,

On 11/18/2016 01:29 PM, Thomas Gleixner wrote:

On Mon, 14 Nov 2016, Zubair Lutfullah Kakakhel wrote:


The powerpc dts file does not have the xlnx,kind-of-intr property.
Instead of erroring out, give a warning instead. And attempt to
continue to probe the interrupt controller while assuming
kind-of-intr is 0x0 as a fall back.


This is broken, really. On multiplatform kernels this will try to probe the
chip no matter what.


I'm not sure I understand why this driver will probe on multi-platform kernels
if the compatible string isn't in the DT?



Powerpc already has:

static const struct of_device_id xilinx_intc_match[] __initconst = {
   { .compatible = "xlnx,opb-intc-1.00.c", },
   { .compatible = "xlnx,xps-intc-1.00.a", },
   {}
};

Unless I'm missing something important, then adding those compatible
strings to the driver will just keep stuff working as expected instead of
adding unsafe and broken heuristics.



The last two lines of the driver already specify the compatible strings.

"
IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);
"

I'll elaborate on the commit message.

The DT node in arch/powerpc for this driver is

intc_0: interrupt-controller@8180 {
#interrupt-cells = <0x2>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = < 0x8180 0x1 >;
xlnx,num-intr-inputs = <0xc>;
} ;

The DT node in arch/microblaze for this driver is

intc_0: interrupt-controller@8180 {
#interrupt-cells = <0x2>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = < 0x8180 0x1 >;
xlnx,kind-of-intr = <0x100>;  //!
xlnx,num-intr-inputs = <0x9>;
} ;

The PPC driver assumes the kind-of-intr value be 0x0 and doesn't specify it in 
DT.
This patch makes that a fall back case. Instead of completely error-ing out.

Regards,
ZubairLK


Thanks,

tglx

Re: [Patch v7 3/7] irqchip: xilinx: restructure and use jump label api

[Zubair Lutfullah Kakakhel]

Hi,

On 11/15/2016 12:49 PM, Michal Simek wrote:

On 14.11.2016 13:13, Zubair Lutfullah Kakakhel wrote:

Add a global structure to house various variables.
And cleanup read/write handling by using jump label api.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>



...


@@ -138,59 +136,75 @@ static const struct irq_domain_ops xintc_irq_domain_ops = 
{
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
-   u32 nr_irq, intr_mask;
+   u32 nr_irq;
int ret;
+   struct xintc_irq_chip *irqc;

-   intc_baseaddr = of_iomap(intc, 0);
-   BUG_ON(!intc_baseaddr);
+   if (xintc_irqc) {
+   pr_err("irq-xilinx: Multiple instances aren't supported\n");
+   return -EINVAL;
+   }


I don't agree with this.
Pretty long time ago we were added support for multiple instances in
xilinx private tree.
You can look here.

https://github.com/Xilinx/linux-xlnx/blob/master/drivers/irqchip/irq-xilinx-intc.c

Not sure if this the latest way how to do it but as you can see
we were setting up
irq_set_handler_data(irq, intc);

and then when you need that structure we were calling
struct intc *local_intc = irq_data_get_irq_chip_data(d);

And that should be it to support multiple instance of this driver.

Based on 5/7 you are describing your interrupt subsystem like this.

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller
If mips_cpu_int has more than one input you can connect more xilinx intc
controllers.
If not you still have an option to connect
xilinx_intcontroller(up to 32 peripherals) -> xilinx_intcontroller(one
intc + up to 31 peripherals)  -> mips_cpu_int controller


That configuration in FPGA is technically possible. Although not done/needed in 
the
way we use the Xilinx Interrupt Controller IP block in MIPSfpga.

This series takes the drivers out of arch code and makes it accessible.
Any further development on the driver would be common to all architectures.
Support for multiple instances would be a 'new feature'.

I say this as this series keeps growing and mutating in terms of its scope
and work.

Would it be possible to ack this so that the restructure out of arch code
can move forward?

Regards,
ZubairLK



Thanks,
Michal

Re: [Patch v7 3/7] irqchip: xilinx: restructure and use jump label api

[Zubair Lutfullah Kakakhel]

Hi,

On 11/15/2016 12:49 PM, Michal Simek wrote:

On 14.11.2016 13:13, Zubair Lutfullah Kakakhel wrote:

Add a global structure to house various variables.
And cleanup read/write handling by using jump label api.

Signed-off-by: Zubair Lutfullah Kakakhel 



...


@@ -138,59 +136,75 @@ static const struct irq_domain_ops xintc_irq_domain_ops = 
{
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
-   u32 nr_irq, intr_mask;
+   u32 nr_irq;
int ret;
+   struct xintc_irq_chip *irqc;

-   intc_baseaddr = of_iomap(intc, 0);
-   BUG_ON(!intc_baseaddr);
+   if (xintc_irqc) {
+   pr_err("irq-xilinx: Multiple instances aren't supported\n");
+   return -EINVAL;
+   }


I don't agree with this.
Pretty long time ago we were added support for multiple instances in
xilinx private tree.
You can look here.

https://github.com/Xilinx/linux-xlnx/blob/master/drivers/irqchip/irq-xilinx-intc.c

Not sure if this the latest way how to do it but as you can see
we were setting up
irq_set_handler_data(irq, intc);

and then when you need that structure we were calling
struct intc *local_intc = irq_data_get_irq_chip_data(d);

And that should be it to support multiple instance of this driver.

Based on 5/7 you are describing your interrupt subsystem like this.

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller
If mips_cpu_int has more than one input you can connect more xilinx intc
controllers.
If not you still have an option to connect
xilinx_intcontroller(up to 32 peripherals) -> xilinx_intcontroller(one
intc + up to 31 peripherals)  -> mips_cpu_int controller


That configuration in FPGA is technically possible. Although not done/needed in 
the
way we use the Xilinx Interrupt Controller IP block in MIPSfpga.

This series takes the drivers out of arch code and makes it accessible.
Any further development on the driver would be common to all architectures.
Support for multiple instances would be a 'new feature'.

I say this as this series keeps growing and mutating in terms of its scope
and work.

Would it be possible to ack this so that the restructure out of arch code
can move forward?

Regards,
ZubairLK



Thanks,
Michal

[Patch v7 2/7] irqchip: xilinx: clean up print messages

[Zubair Lutfullah Kakakhel]

Remove __func__ and prefix irq-xilinx in various debug prints

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V6 -> V7
New patch
This diff was squashed into another patch. Split it up for cleanliness
---
 drivers/irqchip/irq-xilinx-intc.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 90bec7d..096c1ed 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -58,7 +58,7 @@ static void intc_enable_or_unmask(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
 
-   pr_debug("enable_or_unmask: %ld\n", d->hwirq);
+   pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
 
/* ack level irqs because they can't be acked during
 * ack function since the handle_level_irq function
@@ -72,13 +72,13 @@ static void intc_enable_or_unmask(struct irq_data *d)
 
 static void intc_disable_or_mask(struct irq_data *d)
 {
-   pr_debug("disable: %ld\n", d->hwirq);
+   pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
write_fn(1 << d->hwirq, intc_baseaddr + CIE);
 }
 
 static void intc_ack(struct irq_data *d)
 {
-   pr_debug("ack: %ld\n", d->hwirq);
+   pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
write_fn(1 << d->hwirq, intc_baseaddr + IAR);
 }
 
@@ -86,7 +86,7 @@ static void intc_mask_ack(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
 
-   pr_debug("disable_and_ack: %ld\n", d->hwirq);
+   pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
write_fn(mask, intc_baseaddr + CIE);
write_fn(mask, intc_baseaddr + IAR);
 }
@@ -109,7 +109,7 @@ unsigned int get_irq(void)
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
-   pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
+   pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
 
return irq;
 }
@@ -146,20 +146,20 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
 
ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", _irq);
if (ret < 0) {
-   pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__);
+   pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
return ret;
}
 
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", _mask);
if (ret < 0) {
-   pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__);
+   pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
return ret;
}
 
if (intr_mask >> nr_irq)
-   pr_warn("%s: mismatch in kind-of-intr param\n", __func__);
+   pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
 
-   pr_info("%s: num_irq=%d, edge=0x%x\n",
+   pr_info("irq-xilinx: %s: num_irq=%d, edge=0x%x\n",
intc->full_name, nr_irq, intr_mask);
 
write_fn = intc_write32;
-- 
2.10.2

[Patch v7 1/7] microblaze: irqchip: Move intc driver to irqchip

[Zubair Lutfullah Kakakhel]

The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform and a few PowerPC based platforms.

Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V6 -> V7
Rebase to v4.9-rc5

V5 -> V6
Rebase to v4.9-rc3

V4 -> V5
Rebase to v4.9-rc1
Renamed back to irq-xilinx-intc.c

V3 -> V4
No change

V2 -> V3
No change here. Cleanup patches follow after this patch.
Its debatable to cleanup before/after move. Decided to place cleanup
after move to put history in new place.

V1 -> V2

Renamed irq-xilinx to irq-axi-intc
Renamed CONFIG_XILINX_INTC to CONFIG_XILINX_AXI_INTC
Patch is now without rename flag so as to facilitate review
---
 arch/microblaze/Kconfig| 1 +
 arch/microblaze/kernel/Makefile| 2 +-
 drivers/irqchip/Kconfig| 4 
 drivers/irqchip/Makefile   | 1 +
 arch/microblaze/kernel/intc.c => drivers/irqchip/irq-xilinx-intc.c | 0
 5 files changed, 7 insertions(+), 1 deletion(-)
 rename arch/microblaze/kernel/intc.c => drivers/irqchip/irq-xilinx-intc.c 
(100%)

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 86f6572..85885a5 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -27,6 +27,7 @@ config MICROBLAZE
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_OPROFILE
select IRQ_DOMAIN
+   select XILINX_INTC
select MODULES_USE_ELF_RELA
select OF
select OF_EARLY_FLATTREE
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index f08baca..e098381 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -15,7 +15,7 @@ endif
 extra-y := head.o vmlinux.lds
 
 obj-y += dma.o exceptions.o \
-   hw_exception_handler.o intc.o irq.o \
+   hw_exception_handler.o irq.o \
platform.o process.o prom.o ptrace.o \
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
 
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index bc0af33..ae96731 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -211,6 +211,10 @@ config XTENSA_MX
bool
select IRQ_DOMAIN
 
+config XILINX_INTC
+   bool
+   select IRQ_DOMAIN
+
 config IRQ_CROSSBAR
bool
help
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e4dbfc8..0e55d94 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_TB10X_IRQC)  += irq-tb10x.o
 obj-$(CONFIG_TS4800_IRQ)   += irq-ts4800.o
 obj-$(CONFIG_XTENSA)   += irq-xtensa-pic.o
 obj-$(CONFIG_XTENSA_MX)+= irq-xtensa-mx.o
+obj-$(CONFIG_XILINX_INTC)  += irq-xilinx-intc.o
 obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
 obj-$(CONFIG_SOC_VF610)+= irq-vf610-mscm-ir.o
 obj-$(CONFIG_BCM6345_L1_IRQ)   += irq-bcm6345-l1.o
diff --git a/arch/microblaze/kernel/intc.c b/drivers/irqchip/irq-xilinx-intc.c
similarity index 100%
rename from arch/microblaze/kernel/intc.c
rename to drivers/irqchip/irq-xilinx-intc.c
-- 
2.10.2

[Patch v7 2/7] irqchip: xilinx: clean up print messages

[Zubair Lutfullah Kakakhel]

Remove __func__ and prefix irq-xilinx in various debug prints

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V6 -> V7
New patch
This diff was squashed into another patch. Split it up for cleanliness
---
 drivers/irqchip/irq-xilinx-intc.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 90bec7d..096c1ed 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -58,7 +58,7 @@ static void intc_enable_or_unmask(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
 
-   pr_debug("enable_or_unmask: %ld\n", d->hwirq);
+   pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
 
/* ack level irqs because they can't be acked during
 * ack function since the handle_level_irq function
@@ -72,13 +72,13 @@ static void intc_enable_or_unmask(struct irq_data *d)
 
 static void intc_disable_or_mask(struct irq_data *d)
 {
-   pr_debug("disable: %ld\n", d->hwirq);
+   pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
write_fn(1 << d->hwirq, intc_baseaddr + CIE);
 }
 
 static void intc_ack(struct irq_data *d)
 {
-   pr_debug("ack: %ld\n", d->hwirq);
+   pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
write_fn(1 << d->hwirq, intc_baseaddr + IAR);
 }
 
@@ -86,7 +86,7 @@ static void intc_mask_ack(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
 
-   pr_debug("disable_and_ack: %ld\n", d->hwirq);
+   pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
write_fn(mask, intc_baseaddr + CIE);
write_fn(mask, intc_baseaddr + IAR);
 }
@@ -109,7 +109,7 @@ unsigned int get_irq(void)
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
-   pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
+   pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
 
return irq;
 }
@@ -146,20 +146,20 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
 
ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", _irq);
if (ret < 0) {
-   pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__);
+   pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
return ret;
}
 
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", _mask);
if (ret < 0) {
-   pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__);
+   pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
return ret;
}
 
if (intr_mask >> nr_irq)
-   pr_warn("%s: mismatch in kind-of-intr param\n", __func__);
+   pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
 
-   pr_info("%s: num_irq=%d, edge=0x%x\n",
+   pr_info("irq-xilinx: %s: num_irq=%d, edge=0x%x\n",
intc->full_name, nr_irq, intr_mask);
 
write_fn = intc_write32;
-- 
2.10.2

[Patch v7 1/7] microblaze: irqchip: Move intc driver to irqchip

[Zubair Lutfullah Kakakhel]

The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform and a few PowerPC based platforms.

Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V6 -> V7
Rebase to v4.9-rc5

V5 -> V6
Rebase to v4.9-rc3

V4 -> V5
Rebase to v4.9-rc1
Renamed back to irq-xilinx-intc.c

V3 -> V4
No change

V2 -> V3
No change here. Cleanup patches follow after this patch.
Its debatable to cleanup before/after move. Decided to place cleanup
after move to put history in new place.

V1 -> V2

Renamed irq-xilinx to irq-axi-intc
Renamed CONFIG_XILINX_INTC to CONFIG_XILINX_AXI_INTC
Patch is now without rename flag so as to facilitate review
---
 arch/microblaze/Kconfig| 1 +
 arch/microblaze/kernel/Makefile| 2 +-
 drivers/irqchip/Kconfig| 4 
 drivers/irqchip/Makefile   | 1 +
 arch/microblaze/kernel/intc.c => drivers/irqchip/irq-xilinx-intc.c | 0
 5 files changed, 7 insertions(+), 1 deletion(-)
 rename arch/microblaze/kernel/intc.c => drivers/irqchip/irq-xilinx-intc.c 
(100%)

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 86f6572..85885a5 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -27,6 +27,7 @@ config MICROBLAZE
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_OPROFILE
select IRQ_DOMAIN
+   select XILINX_INTC
select MODULES_USE_ELF_RELA
select OF
select OF_EARLY_FLATTREE
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index f08baca..e098381 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -15,7 +15,7 @@ endif
 extra-y := head.o vmlinux.lds
 
 obj-y += dma.o exceptions.o \
-   hw_exception_handler.o intc.o irq.o \
+   hw_exception_handler.o irq.o \
platform.o process.o prom.o ptrace.o \
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
 
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index bc0af33..ae96731 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -211,6 +211,10 @@ config XTENSA_MX
bool
select IRQ_DOMAIN
 
+config XILINX_INTC
+   bool
+   select IRQ_DOMAIN
+
 config IRQ_CROSSBAR
bool
help
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e4dbfc8..0e55d94 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_TB10X_IRQC)  += irq-tb10x.o
 obj-$(CONFIG_TS4800_IRQ)   += irq-ts4800.o
 obj-$(CONFIG_XTENSA)   += irq-xtensa-pic.o
 obj-$(CONFIG_XTENSA_MX)+= irq-xtensa-mx.o
+obj-$(CONFIG_XILINX_INTC)  += irq-xilinx-intc.o
 obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
 obj-$(CONFIG_SOC_VF610)+= irq-vf610-mscm-ir.o
 obj-$(CONFIG_BCM6345_L1_IRQ)   += irq-bcm6345-l1.o
diff --git a/arch/microblaze/kernel/intc.c b/drivers/irqchip/irq-xilinx-intc.c
similarity index 100%
rename from arch/microblaze/kernel/intc.c
rename to drivers/irqchip/irq-xilinx-intc.c
-- 
2.10.2

[Patch v7 3/7] irqchip: xilinx: restructure and use jump label api

[Zubair Lutfullah Kakakhel]

Add a global structure to house various variables.
And cleanup read/write handling by using jump label api.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V6 -> V7
Restructure and use jump label api
Better commit log

V5 -> V6
Removed __func__ from printk
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Better error handling

V3 -> V4
Better error handling for kzalloc
Erroring out if the axi intc is probed twice as that isn't
supported

V2 -> V3
New patch. Cleans up driver structure
---
 drivers/irqchip/irq-xilinx-intc.c | 118 +-
 1 file changed, 66 insertions(+), 52 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 096c1ed..7331d8c 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -14,10 +14,9 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
-static void __iomem *intc_baseaddr;
-
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
 #define IPR 0x04   /* Interrupt Pending Register */
@@ -31,27 +30,30 @@ static void __iomem *intc_baseaddr;
 #define MER_ME (1<<0)
 #define MER_HIE (1<<1)
 
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
 
-static void intc_write32(u32 val, void __iomem *addr)
-{
-   iowrite32(val, addr);
-}
+struct xintc_irq_chip {
+   void__iomem *base;
+   struct  irq_domain *root_domain;
+   u32 intr_mask;
+};
 
-static unsigned int intc_read32(void __iomem *addr)
-{
-   return ioread32(addr);
-}
+static struct xintc_irq_chip *xintc_irqc;
 
-static void intc_write32_be(u32 val, void __iomem *addr)
+static void xintc_write(int reg, u32 data)
 {
-   iowrite32be(val, addr);
+   if (static_branch_unlikely(_is_be))
+   iowrite32be(data, xintc_irqc->base + reg);
+   else
+   iowrite32(data, xintc_irqc->base + reg);
 }
 
-static unsigned int intc_read32_be(void __iomem *addr)
+static unsigned int xintc_read(int reg)
 {
-   return ioread32be(addr);
+   if (static_branch_unlikely(_is_be))
+   return ioread32be(xintc_irqc->base + reg);
+   else
+   return ioread32(xintc_irqc->base + reg);
 }
 
 static void intc_enable_or_unmask(struct irq_data *d)
@@ -65,21 +67,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
 * acks the irq before calling the interrupt handler
 */
if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(IAR, mask);
 
-   write_fn(mask, intc_baseaddr + SIE);
+   xintc_write(SIE, mask);
 }
 
 static void intc_disable_or_mask(struct irq_data *d)
 {
pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
+   xintc_write(CIE, 1 << d->hwirq);
 }
 
 static void intc_ack(struct irq_data *d)
 {
pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
+   xintc_write(IAR, 1 << d->hwirq);
 }
 
 static void intc_mask_ack(struct irq_data *d)
@@ -87,8 +89,8 @@ static void intc_mask_ack(struct irq_data *d)
unsigned long mask = 1 << d->hwirq;
 
pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
-   write_fn(mask, intc_baseaddr + CIE);
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(CIE, mask);
+   xintc_write(IAR, mask);
 }
 
 static struct irq_chip intc_dev = {
@@ -99,15 +101,13 @@ static struct irq_chip intc_dev = {
.irq_mask_ack = intc_mask_ack,
 };
 
-static struct irq_domain *root_domain;
-
 unsigned int get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
-   hwirq = read_fn(intc_baseaddr + IVR);
+   hwirq = xintc_read(IVR);
if (hwirq != -1U)
-   irq = irq_find_mapping(root_domain, hwirq);
+   irq = irq_find_mapping(xintc_irqc->root_domain, hwirq);
 
pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
 
@@ -116,9 +116,7 @@ unsigned int get_irq(void)
 
 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t 
hw)
 {
-   u32 intr_mask = (u32)d->host_data;
-
-   if (intr_mask & (1 << hw)) {
+   if (xintc_irqc->intr_mask & (1 << hw)) {
irq_set_chip_and_handler_name(irq, _dev,
handle_edge_irq, "edge");
irq_clear_status_flags(irq, IRQ_LEVEL);
@@ -138,59 +136,75 @@ static const struct irq_domain_ops xintc_irq_domain_ops = 
{
 static int __init xilinx_intc_of_init(struct device_node *intc,
 

[Patch v7 3/7] irqchip: xilinx: restructure and use jump label api

[Zubair Lutfullah Kakakhel]

Add a global structure to house various variables.
And cleanup read/write handling by using jump label api.

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V6 -> V7
Restructure and use jump label api
Better commit log

V5 -> V6
Removed __func__ from printk
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Better error handling

V3 -> V4
Better error handling for kzalloc
Erroring out if the axi intc is probed twice as that isn't
supported

V2 -> V3
New patch. Cleans up driver structure
---
 drivers/irqchip/irq-xilinx-intc.c | 118 +-
 1 file changed, 66 insertions(+), 52 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 096c1ed..7331d8c 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -14,10 +14,9 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
-static void __iomem *intc_baseaddr;
-
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
 #define IPR 0x04   /* Interrupt Pending Register */
@@ -31,27 +30,30 @@ static void __iomem *intc_baseaddr;
 #define MER_ME (1<<0)
 #define MER_HIE (1<<1)
 
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
 
-static void intc_write32(u32 val, void __iomem *addr)
-{
-   iowrite32(val, addr);
-}
+struct xintc_irq_chip {
+   void__iomem *base;
+   struct  irq_domain *root_domain;
+   u32 intr_mask;
+};
 
-static unsigned int intc_read32(void __iomem *addr)
-{
-   return ioread32(addr);
-}
+static struct xintc_irq_chip *xintc_irqc;
 
-static void intc_write32_be(u32 val, void __iomem *addr)
+static void xintc_write(int reg, u32 data)
 {
-   iowrite32be(val, addr);
+   if (static_branch_unlikely(_is_be))
+   iowrite32be(data, xintc_irqc->base + reg);
+   else
+   iowrite32(data, xintc_irqc->base + reg);
 }
 
-static unsigned int intc_read32_be(void __iomem *addr)
+static unsigned int xintc_read(int reg)
 {
-   return ioread32be(addr);
+   if (static_branch_unlikely(_is_be))
+   return ioread32be(xintc_irqc->base + reg);
+   else
+   return ioread32(xintc_irqc->base + reg);
 }
 
 static void intc_enable_or_unmask(struct irq_data *d)
@@ -65,21 +67,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
 * acks the irq before calling the interrupt handler
 */
if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(IAR, mask);
 
-   write_fn(mask, intc_baseaddr + SIE);
+   xintc_write(SIE, mask);
 }
 
 static void intc_disable_or_mask(struct irq_data *d)
 {
pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
+   xintc_write(CIE, 1 << d->hwirq);
 }
 
 static void intc_ack(struct irq_data *d)
 {
pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
+   xintc_write(IAR, 1 << d->hwirq);
 }
 
 static void intc_mask_ack(struct irq_data *d)
@@ -87,8 +89,8 @@ static void intc_mask_ack(struct irq_data *d)
unsigned long mask = 1 << d->hwirq;
 
pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
-   write_fn(mask, intc_baseaddr + CIE);
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(CIE, mask);
+   xintc_write(IAR, mask);
 }
 
 static struct irq_chip intc_dev = {
@@ -99,15 +101,13 @@ static struct irq_chip intc_dev = {
.irq_mask_ack = intc_mask_ack,
 };
 
-static struct irq_domain *root_domain;
-
 unsigned int get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
-   hwirq = read_fn(intc_baseaddr + IVR);
+   hwirq = xintc_read(IVR);
if (hwirq != -1U)
-   irq = irq_find_mapping(root_domain, hwirq);
+   irq = irq_find_mapping(xintc_irqc->root_domain, hwirq);
 
pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
 
@@ -116,9 +116,7 @@ unsigned int get_irq(void)
 
 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t 
hw)
 {
-   u32 intr_mask = (u32)d->host_data;
-
-   if (intr_mask & (1 << hw)) {
+   if (xintc_irqc->intr_mask & (1 << hw)) {
irq_set_chip_and_handler_name(irq, _dev,
handle_edge_irq, "edge");
irq_clear_status_flags(irq, IRQ_LEVEL);
@@ -138,59 +136,75 @@ static const struct irq_domain_ops xintc_irq_domain_ops = 
{
 static int __init xilinx_intc_of_init(struct device_node *intc,
   

[Patch v7 5/7] irqchip: xilinx: Add support for parent intc

[Zubair Lutfullah Kakakhel]

The MIPS based xilfpga platform has the following IRQ structure

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller

Add support for the driver to chain the irq handler

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V6 -> V7
Rebase to v4.9-rc5

V5 -> V6
Use chained_irq_enter and chained_irq_exit
Add error check for irq_of_parse_and_map
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Missing curly braces

V3 -> V4
Clean up if/else when a parent is found
Pass irqchip structure to handler as data

V2 -> V3
Reused existing parent node instead of finding again.
Cleanup up handler based on review

V1 -> V2

No change
---
 drivers/irqchip/irq-xilinx-intc.c | 34 --
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 34ec609..971c141 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -12,10 +12,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
@@ -133,11 +135,26 @@ static const struct irq_domain_ops xintc_irq_domain_ops = 
{
.map = xintc_map,
 };
 
+static void xil_intc_irq_handler(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   u32 pending;
+
+   chained_irq_enter(chip, desc);
+   do {
+   pending = xintc_get_irq();
+   if (pending == -1U)
+   break;
+   generic_handle_irq(pending);
+   } while (true);
+   chained_irq_exit(chip, desc);
+}
+
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
u32 nr_irq;
-   int ret;
+   int ret, irq;
struct xintc_irq_chip *irqc;
 
if (xintc_irqc) {
@@ -196,7 +213,20 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
goto err_alloc;
}
 
-   irq_set_default_host(irqc->root_domain);
+   if (parent) {
+   irq = irq_of_parse_and_map(intc, 0);
+   if (irq) {
+   irq_set_chained_handler_and_data(irq,
+xil_intc_irq_handler,
+irqc);
+   } else {
+   pr_err("irq-xilinx: interrupts property not in DT\n");
+   ret = -EINVAL;
+   goto err_alloc;
+   }
+   } else {
+   irq_set_default_host(irqc->root_domain);
+   }
 
return 0;
 
-- 
2.10.2

[Patch v7 4/7] irqchip: xilinx: Rename get_irq to xintc_get_irq

[Zubair Lutfullah Kakakhel]

Now that the driver is generic and used by multiple archs,
get_irq is too generic.

Rename get_irq to xintc_get_irq to avoid any conflicts

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V6 -> V7
Rebase to v4.9-rc5

V5 -> V6
Removed __func__ in printk
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Use __func__ in pr_err

V3 -> V4
New patch.
---
 arch/microblaze/include/asm/irq.h | 2 +-
 arch/microblaze/kernel/irq.c  | 4 ++--
 drivers/irqchip/irq-xilinx-intc.c | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/microblaze/include/asm/irq.h 
b/arch/microblaze/include/asm/irq.h
index bab3b13..d785def 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -16,6 +16,6 @@ struct pt_regs;
 extern void do_IRQ(struct pt_regs *regs);
 
 /* should be defined in each interrupt controller driver */
-extern unsigned int get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* _ASM_MICROBLAZE_IRQ_H */
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 11e24de..903dad8 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -29,12 +29,12 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
trace_hardirqs_off();
 
irq_enter();
-   irq = get_irq();
+   irq = xintc_get_irq();
 next_irq:
BUG_ON(!irq);
generic_handle_irq(irq);
 
-   irq = get_irq();
+   irq = xintc_get_irq();
if (irq != -1U) {
pr_debug("next irq: %d\n", irq);
++concurrent_irq;
diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 7331d8c..34ec609 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -101,7 +101,7 @@ static struct irq_chip intc_dev = {
.irq_mask_ack = intc_mask_ack,
 };
 
-unsigned int get_irq(void)
+unsigned int xintc_get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
-- 
2.10.2

[Patch v7 5/7] irqchip: xilinx: Add support for parent intc

[Zubair Lutfullah Kakakhel]

The MIPS based xilfpga platform has the following IRQ structure

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller

Add support for the driver to chain the irq handler

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V6 -> V7
Rebase to v4.9-rc5

V5 -> V6
Use chained_irq_enter and chained_irq_exit
Add error check for irq_of_parse_and_map
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Missing curly braces

V3 -> V4
Clean up if/else when a parent is found
Pass irqchip structure to handler as data

V2 -> V3
Reused existing parent node instead of finding again.
Cleanup up handler based on review

V1 -> V2

No change
---
 drivers/irqchip/irq-xilinx-intc.c | 34 --
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 34ec609..971c141 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -12,10 +12,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
@@ -133,11 +135,26 @@ static const struct irq_domain_ops xintc_irq_domain_ops = 
{
.map = xintc_map,
 };
 
+static void xil_intc_irq_handler(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   u32 pending;
+
+   chained_irq_enter(chip, desc);
+   do {
+   pending = xintc_get_irq();
+   if (pending == -1U)
+   break;
+   generic_handle_irq(pending);
+   } while (true);
+   chained_irq_exit(chip, desc);
+}
+
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
u32 nr_irq;
-   int ret;
+   int ret, irq;
struct xintc_irq_chip *irqc;
 
if (xintc_irqc) {
@@ -196,7 +213,20 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
goto err_alloc;
}
 
-   irq_set_default_host(irqc->root_domain);
+   if (parent) {
+   irq = irq_of_parse_and_map(intc, 0);
+   if (irq) {
+   irq_set_chained_handler_and_data(irq,
+xil_intc_irq_handler,
+irqc);
+   } else {
+   pr_err("irq-xilinx: interrupts property not in DT\n");
+   ret = -EINVAL;
+   goto err_alloc;
+   }
+   } else {
+   irq_set_default_host(irqc->root_domain);
+   }
 
return 0;
 
-- 
2.10.2

[Patch v7 4/7] irqchip: xilinx: Rename get_irq to xintc_get_irq

[Zubair Lutfullah Kakakhel]

Now that the driver is generic and used by multiple archs,
get_irq is too generic.

Rename get_irq to xintc_get_irq to avoid any conflicts

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V6 -> V7
Rebase to v4.9-rc5

V5 -> V6
Removed __func__ in printk
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Use __func__ in pr_err

V3 -> V4
New patch.
---
 arch/microblaze/include/asm/irq.h | 2 +-
 arch/microblaze/kernel/irq.c  | 4 ++--
 drivers/irqchip/irq-xilinx-intc.c | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/microblaze/include/asm/irq.h 
b/arch/microblaze/include/asm/irq.h
index bab3b13..d785def 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -16,6 +16,6 @@ struct pt_regs;
 extern void do_IRQ(struct pt_regs *regs);
 
 /* should be defined in each interrupt controller driver */
-extern unsigned int get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* _ASM_MICROBLAZE_IRQ_H */
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 11e24de..903dad8 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -29,12 +29,12 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
trace_hardirqs_off();
 
irq_enter();
-   irq = get_irq();
+   irq = xintc_get_irq();
 next_irq:
BUG_ON(!irq);
generic_handle_irq(irq);
 
-   irq = get_irq();
+   irq = xintc_get_irq();
if (irq != -1U) {
pr_debug("next irq: %d\n", irq);
++concurrent_irq;
diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 7331d8c..34ec609 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -101,7 +101,7 @@ static struct irq_chip intc_dev = {
.irq_mask_ack = intc_mask_ack,
 };
 
-unsigned int get_irq(void)
+unsigned int xintc_get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
-- 
2.10.2

[Patch v7 6/7] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

The powerpc dts file does not have the xlnx,kind-of-intr property.
Instead of erroring out, give a warning instead. And attempt to
continue to probe the interrupt controller while assuming
kind-of-intr is 0x0 as a fall back.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V6 -> V7
Rebase to v4.9-rc5

V5 -> V6
Rebase to v4.9-rc3

V5 new patch
---
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 971c141..d330917 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -179,8 +179,8 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
 
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", >intr_mask);
if (ret < 0) {
-   pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
-   goto err_alloc;
+   pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
+   irqc->intr_mask = 0;
}
 
if (irqc->intr_mask >> nr_irq)
-- 
2.10.2

[Patch v7 6/7] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

The powerpc dts file does not have the xlnx,kind-of-intr property.
Instead of erroring out, give a warning instead. And attempt to
continue to probe the interrupt controller while assuming
kind-of-intr is 0x0 as a fall back.

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V6 -> V7
Rebase to v4.9-rc5

V5 -> V6
Rebase to v4.9-rc3

V5 new patch
---
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 971c141..d330917 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -179,8 +179,8 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
 
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", >intr_mask);
if (ret < 0) {
-   pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
-   goto err_alloc;
+   pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
+   irqc->intr_mask = 0;
}
 
if (irqc->intr_mask >> nr_irq)
-- 
2.10.2

[Patch v7 7/7] powerpc/virtex: Use generic xilinx irqchip driver

[Zubair Lutfullah Kakakhel]

The Xilinx interrupt controller driver is now available in drivers/irqchip.
Switch to using that driver.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
Acked-by: Michael Ellerman <m...@ellerman.id.au> (powerpc)

---
V6 - V7
Rebase to v4.9-rc5

V5 -> V6 Added Acked-by Micheal Ellerman

V5 New patch

Tested on virtex440-ml507 using qemu
---
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +
 drivers/irqchip/irq-xilinx-intc.c  |   3 +-
 7 files changed, 9 insertions(+), 213 deletions(-)

diff --git a/arch/powerpc/include/asm/xilinx_intc.h 
b/arch/powerpc/include/asm/xilinx_intc.h
index 343612f..3192d7f 100644
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ b/arch/powerpc/include/asm/xilinx_intc.h
@@ -14,7 +14,7 @@
 #ifdef __KERNEL__
 
 extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xilinx_intc_get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/platforms/40x/Kconfig 
b/arch/powerpc/platforms/40x/Kconfig
index e3257f2..1d7c1b1 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -64,6 +64,7 @@ config XILINX_VIRTEX_GENERIC_BOARD
default n
select XILINX_VIRTEX_II_PRO
select XILINX_VIRTEX_4_FX
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards.
 
diff --git a/arch/powerpc/platforms/40x/virtex.c 
b/arch/powerpc/platforms/40x/virtex.c
index 91a08ea..e3d5e09 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -48,7 +48,7 @@ define_machine(virtex) {
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.restart= ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/Kconfig 
b/arch/powerpc/platforms/44x/Kconfig
index 48fc180..25b8d64 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -241,6 +241,7 @@ config XILINX_VIRTEX440_GENERIC_BOARD
depends on 44x
default n
select XILINX_VIRTEX_5_FXT
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards
  that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
diff --git a/arch/powerpc/platforms/44x/virtex.c 
b/arch/powerpc/platforms/44x/virtex.c
index a7e0802..3eb13ed 100644
--- a/arch/powerpc/platforms/44x/virtex.c
+++ b/arch/powerpc/platforms/44x/virtex.c
@@ -54,7 +54,7 @@ define_machine(virtex) {
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.calibrate_decr = generic_calibrate_decr,
.restart= ppc4xx_reset_system,
 };
diff --git a/arch/powerpc/sysdev/xilinx_intc.c 
b/arch/powerpc/sysdev/xilinx_intc.c
index 0f52d79..4a86dcf 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -29,194 +29,7 @@
 #include 
 #include 
 #include 
-
-/*
- * INTC Registers
- */
-#define XINTC_ISR  0   /* Interrupt Status */
-#define XINTC_IPR  4   /* Interrupt Pending */
-#define XINTC_IER  8   /* Interrupt Enable */
-#define XINTC_IAR  12  /* Interrupt Acknowledge */
-#define XINTC_SIE  16  /* Set Interrupt Enable bits */
-#define XINTC_CIE  20  /* Clear Interrupt Enable bits */
-#define XINTC_IVR  24  /* Interrupt Vector */
-#define XINTC_MER  28  /* Master Enable */
-
-static struct irq_domain *master_irqhost;
-
-#define XILINX_INTC_MAXIRQS(32)
-
-/* The following table allows the interrupt type, edge or level,
- * to be cached after being read from the device tree until the interrupt
- * is mapped
- */
-static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
-
-/* Map the interrupt type from the device tree to the interrupt types
- * used by the interrupt subsystem
- */
-static unsigned char xilinx_intc_map_senses[] = {
-   IRQ_TYPE_EDGE_RISING,
-   IRQ_TYPE_EDGE_FALLING,
-   IRQ_TYPE_LEVEL_HIGH,
-   IRQ_TYPE_LEVEL_LOW,
-};
-
-/*
- * The interrupt controller is setup such that it doesn't work well with
- * the level interrupt handler in the kernel because the handler acks the
- * interrupt

[Patch v7 0/7] microblaze/PowerPC: Move irq-xilinx to irqchip

[Zubair Lutfullah Kakakhel]

Hi,

This patch series moves the Xilinx interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then removes another implementation of the driver in arch/powerpc.

This effort results in one common driver usable by mips,microblaze
and powerpc.

Compile tested on microblaze-el.
Tested using qemu-system-ppc using virtix440-ml507
Tested on MIPSfpga platform.

Based on v4.9-rc5

Thanks,
ZubairLK

V6 -> V7
Rebase to v4.5-rc5
Split print messages cleanup into a separate patch
Use jump label api to restructure read/write handling in driver.

V5 -> V6
Split patch series. Patches for arch/mips can go separately
Rebase to v4.9-rc3
Added chained_irq_enter/exit
Removed __func__ used in pr_err

V4 -> V5
Added a new patch that removes the PPC driver
Rebase to v4.9-rc1
Better error handling

V3 -> V4
Better error handling
Some minor fixups

V2 -> V3
Cleanup the interrupt controller driver a bit based on feedback
Rebase to v4.8-rc4

V1 -> V2
Resubmitting without truncating the diff output for file moves
Removed accidental local mac address entry
Individual logs have more detail


Zubair Lutfullah Kakakhel (7):
  microblaze: irqchip: Move intc driver to irqchip
  irqchip: xilinx: clean up print messages
  irqchip: xilinx: restructure and use jump label api
  irqchip: xilinx: Rename get_irq to xintc_get_irq
  irqchip: xilinx: Add support for parent intc
  irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided
  powerpc/virtex: Use generic xilinx irqchip driver

 arch/microblaze/Kconfig|   1 +
 arch/microblaze/include/asm/irq.h  |   2 +-
 arch/microblaze/kernel/Makefile|   2 +-
 arch/microblaze/kernel/intc.c  | 196 ---
 arch/microblaze/kernel/irq.c   |   4 +-
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +
 drivers/irqchip/Kconfig|   4 +
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-xilinx-intc.c  | 241 +
 14 files changed, 258 insertions(+), 412 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

-- 
2.10.2

[Patch v7 7/7] powerpc/virtex: Use generic xilinx irqchip driver

[Zubair Lutfullah Kakakhel]

The Xilinx interrupt controller driver is now available in drivers/irqchip.
Switch to using that driver.

Signed-off-by: Zubair Lutfullah Kakakhel 
Acked-by: Michael Ellerman  (powerpc)

---
V6 - V7
Rebase to v4.9-rc5

V5 -> V6 Added Acked-by Micheal Ellerman

V5 New patch

Tested on virtex440-ml507 using qemu
---
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +
 drivers/irqchip/irq-xilinx-intc.c  |   3 +-
 7 files changed, 9 insertions(+), 213 deletions(-)

diff --git a/arch/powerpc/include/asm/xilinx_intc.h 
b/arch/powerpc/include/asm/xilinx_intc.h
index 343612f..3192d7f 100644
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ b/arch/powerpc/include/asm/xilinx_intc.h
@@ -14,7 +14,7 @@
 #ifdef __KERNEL__
 
 extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xilinx_intc_get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/platforms/40x/Kconfig 
b/arch/powerpc/platforms/40x/Kconfig
index e3257f2..1d7c1b1 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -64,6 +64,7 @@ config XILINX_VIRTEX_GENERIC_BOARD
default n
select XILINX_VIRTEX_II_PRO
select XILINX_VIRTEX_4_FX
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards.
 
diff --git a/arch/powerpc/platforms/40x/virtex.c 
b/arch/powerpc/platforms/40x/virtex.c
index 91a08ea..e3d5e09 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -48,7 +48,7 @@ define_machine(virtex) {
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.restart= ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/Kconfig 
b/arch/powerpc/platforms/44x/Kconfig
index 48fc180..25b8d64 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -241,6 +241,7 @@ config XILINX_VIRTEX440_GENERIC_BOARD
depends on 44x
default n
select XILINX_VIRTEX_5_FXT
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards
  that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
diff --git a/arch/powerpc/platforms/44x/virtex.c 
b/arch/powerpc/platforms/44x/virtex.c
index a7e0802..3eb13ed 100644
--- a/arch/powerpc/platforms/44x/virtex.c
+++ b/arch/powerpc/platforms/44x/virtex.c
@@ -54,7 +54,7 @@ define_machine(virtex) {
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.calibrate_decr = generic_calibrate_decr,
.restart= ppc4xx_reset_system,
 };
diff --git a/arch/powerpc/sysdev/xilinx_intc.c 
b/arch/powerpc/sysdev/xilinx_intc.c
index 0f52d79..4a86dcf 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -29,194 +29,7 @@
 #include 
 #include 
 #include 
-
-/*
- * INTC Registers
- */
-#define XINTC_ISR  0   /* Interrupt Status */
-#define XINTC_IPR  4   /* Interrupt Pending */
-#define XINTC_IER  8   /* Interrupt Enable */
-#define XINTC_IAR  12  /* Interrupt Acknowledge */
-#define XINTC_SIE  16  /* Set Interrupt Enable bits */
-#define XINTC_CIE  20  /* Clear Interrupt Enable bits */
-#define XINTC_IVR  24  /* Interrupt Vector */
-#define XINTC_MER  28  /* Master Enable */
-
-static struct irq_domain *master_irqhost;
-
-#define XILINX_INTC_MAXIRQS(32)
-
-/* The following table allows the interrupt type, edge or level,
- * to be cached after being read from the device tree until the interrupt
- * is mapped
- */
-static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
-
-/* Map the interrupt type from the device tree to the interrupt types
- * used by the interrupt subsystem
- */
-static unsigned char xilinx_intc_map_senses[] = {
-   IRQ_TYPE_EDGE_RISING,
-   IRQ_TYPE_EDGE_FALLING,
-   IRQ_TYPE_LEVEL_HIGH,
-   IRQ_TYPE_LEVEL_LOW,
-};
-
-/*
- * The interrupt controller is setup such that it doesn't work well with
- * the level interrupt handler in the kernel because the handler acks the
- * interrupt before calling the application interrupt handler. To d

[Patch v7 0/7] microblaze/PowerPC: Move irq-xilinx to irqchip

[Zubair Lutfullah Kakakhel]

Hi,

This patch series moves the Xilinx interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then removes another implementation of the driver in arch/powerpc.

This effort results in one common driver usable by mips,microblaze
and powerpc.

Compile tested on microblaze-el.
Tested using qemu-system-ppc using virtix440-ml507
Tested on MIPSfpga platform.

Based on v4.9-rc5

Thanks,
ZubairLK

V6 -> V7
Rebase to v4.5-rc5
Split print messages cleanup into a separate patch
Use jump label api to restructure read/write handling in driver.

V5 -> V6
Split patch series. Patches for arch/mips can go separately
Rebase to v4.9-rc3
Added chained_irq_enter/exit
Removed __func__ used in pr_err

V4 -> V5
Added a new patch that removes the PPC driver
Rebase to v4.9-rc1
Better error handling

V3 -> V4
Better error handling
Some minor fixups

V2 -> V3
Cleanup the interrupt controller driver a bit based on feedback
Rebase to v4.8-rc4

V1 -> V2
Resubmitting without truncating the diff output for file moves
Removed accidental local mac address entry
Individual logs have more detail


Zubair Lutfullah Kakakhel (7):
  microblaze: irqchip: Move intc driver to irqchip
  irqchip: xilinx: clean up print messages
  irqchip: xilinx: restructure and use jump label api
  irqchip: xilinx: Rename get_irq to xintc_get_irq
  irqchip: xilinx: Add support for parent intc
  irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided
  powerpc/virtex: Use generic xilinx irqchip driver

 arch/microblaze/Kconfig|   1 +
 arch/microblaze/include/asm/irq.h  |   2 +-
 arch/microblaze/kernel/Makefile|   2 +-
 arch/microblaze/kernel/intc.c  | 196 ---
 arch/microblaze/kernel/irq.c   |   4 +-
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +
 drivers/irqchip/Kconfig|   4 +
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-xilinx-intc.c  | 241 +
 14 files changed, 258 insertions(+), 412 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

-- 
2.10.2

Re: [Patch V6 2/6] irqchip: xilinx: Clean up irqdomain argument and read/write

[Zubair Lutfullah Kakakhel]

Hi,

On 11/01/2016 11:05 AM, Zubair Lutfullah Kakakhel wrote:

Hi,

Thanks for the review.

On 10/31/2016 07:51 PM, Thomas Gleixner wrote:

On Mon, 31 Oct 2016, Zubair Lutfullah Kakakhel wrote:

The drivers read/write function handling is a bit quirky.


Can you please explain in more detail what's quirky and why it should be
done differently,


And the irqmask is passed directly to the handler.


I can't make any sense out of that sentence.  Which handler? If you talk
about the write function, then I don't see a change. So what are you
talking about?


Thanks. I'll add more detail in v7 if this patch survives.




Add a new irqchip struct to pass to the handler and
cleanup read/write handling.


I still don't see what it cleans up. You move the write function pointer
into a data structure, which is exposed by another pointer. So you create
two levels of indirection in the hotpath. The function prototype is still
the same. So all this does is making things slower unless I'm missing
something.


I wrote this patch/cleanup based on a review of driver by Marc when I moved the
driver from arch/microblaze to drivers/irqchip

"Marc Zyngier

...


 arch/microblaze/kernel/intc.c   | 196 
 drivers/irqchip/irq-axi-intc.c  | 196 


...


+/* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
+ * lazy and Michal can clean it up to something nicer when he tests
+ * and commits this patch.  ~~gcl */
+root_domain = irq_domain_add_linear(intc, nr_irq, _irq_domain_ops,
+(void *)intr_mask);


Since you're now reworking this driver, how about addressing this
ugliness? You could store the intr_mask together with intc_baseaddr,
and the read/write functions in a global structure, and pass a
pointer to it? That would make the code a bit nicer...
"

https://patchwork.kernel.org/patch/9287933/




-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+struct xintc_irq_chip {
+void __iomem *base;
+structirq_domain *domain;
+structirq_chip chip;


The tabs between struct and the structure name are bogus.


+u32intr_mask;
+unsigned int (*read)(void __iomem *iomem);
+void (*write)(u32 data, void __iomem *iomem);


Please structure that like a table:

void__iomem *base;
struct irq_domain*domain;
struct irq_chipchip;
u32intr_mask;
unsigned int(*read)(void __iomem *iomem);
void(*write)(u32 data, void __iomem *iomem);

Can you see how that makes parsing the struct simpler, because the data
types are clearly to identify?


That does make it look much better.




+static struct xintc_irq_chip *xintc_irqc;

 static void intc_write32(u32 val, void __iomem *addr)
 {
@@ -54,6 +60,18 @@ static unsigned int intc_read32_be(void __iomem *addr)
 return ioread32be(addr);
 }

+static inline unsigned int xintc_read(struct xintc_irq_chip *xintc_irqc,
+ int reg)
+{
+return xintc_irqc->read(xintc_irqc->base + reg);
+}
+
+static inline void xintc_write(struct xintc_irq_chip *xintc_irqc,
+ int reg, u32 data)
+{
+xintc_irqc->write(data, xintc_irqc->base + reg);
+}
+
 static void intc_enable_or_unmask(struct irq_data *d)
 {
 unsigned long mask = 1 << d->hwirq;
@@ -65,21 +83,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
  * acks the irq before calling the interrupt handler
  */
 if (irqd_is_level_type(d))
-write_fn(mask, intc_baseaddr + IAR);
+xintc_write(xintc_irqc, IAR, mask);


So this whole thing makes only sense, when you want to support multiple
instances of that chip and then you need to store the xintc_irqc pointer as
irqchip data and retrieve it from there. Unless you do that, this "cleanup"
is just churn for nothing with the effect of making things less efficient.



Indeed the driver doesn't support multiple instances of the Xilinx Interrupt 
controller.
I don't have a use-case or the hardware for that.

So what would be the recommended course of action?


I'd really appreciate a consensus here.
I'm hoping that these patches can go in v4.10.

Thanks
ZubairLK



Regards,
ZubairLK


Thanks,

tglx

Re: [Patch V6 2/6] irqchip: xilinx: Clean up irqdomain argument and read/write

[Zubair Lutfullah Kakakhel]

Hi,

On 11/01/2016 11:05 AM, Zubair Lutfullah Kakakhel wrote:

Hi,

Thanks for the review.

On 10/31/2016 07:51 PM, Thomas Gleixner wrote:

On Mon, 31 Oct 2016, Zubair Lutfullah Kakakhel wrote:

The drivers read/write function handling is a bit quirky.


Can you please explain in more detail what's quirky and why it should be
done differently,


And the irqmask is passed directly to the handler.


I can't make any sense out of that sentence.  Which handler? If you talk
about the write function, then I don't see a change. So what are you
talking about?


Thanks. I'll add more detail in v7 if this patch survives.




Add a new irqchip struct to pass to the handler and
cleanup read/write handling.


I still don't see what it cleans up. You move the write function pointer
into a data structure, which is exposed by another pointer. So you create
two levels of indirection in the hotpath. The function prototype is still
the same. So all this does is making things slower unless I'm missing
something.


I wrote this patch/cleanup based on a review of driver by Marc when I moved the
driver from arch/microblaze to drivers/irqchip

"Marc Zyngier

...


 arch/microblaze/kernel/intc.c   | 196 
 drivers/irqchip/irq-axi-intc.c  | 196 


...


+/* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
+ * lazy and Michal can clean it up to something nicer when he tests
+ * and commits this patch.  ~~gcl */
+root_domain = irq_domain_add_linear(intc, nr_irq, _irq_domain_ops,
+(void *)intr_mask);


Since you're now reworking this driver, how about addressing this
ugliness? You could store the intr_mask together with intc_baseaddr,
and the read/write functions in a global structure, and pass a
pointer to it? That would make the code a bit nicer...
"

https://patchwork.kernel.org/patch/9287933/




-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+struct xintc_irq_chip {
+void __iomem *base;
+structirq_domain *domain;
+structirq_chip chip;


The tabs between struct and the structure name are bogus.


+u32intr_mask;
+unsigned int (*read)(void __iomem *iomem);
+void (*write)(u32 data, void __iomem *iomem);


Please structure that like a table:

void__iomem *base;
struct irq_domain*domain;
struct irq_chipchip;
u32intr_mask;
unsigned int(*read)(void __iomem *iomem);
void(*write)(u32 data, void __iomem *iomem);

Can you see how that makes parsing the struct simpler, because the data
types are clearly to identify?


That does make it look much better.




+static struct xintc_irq_chip *xintc_irqc;

 static void intc_write32(u32 val, void __iomem *addr)
 {
@@ -54,6 +60,18 @@ static unsigned int intc_read32_be(void __iomem *addr)
 return ioread32be(addr);
 }

+static inline unsigned int xintc_read(struct xintc_irq_chip *xintc_irqc,
+ int reg)
+{
+return xintc_irqc->read(xintc_irqc->base + reg);
+}
+
+static inline void xintc_write(struct xintc_irq_chip *xintc_irqc,
+ int reg, u32 data)
+{
+xintc_irqc->write(data, xintc_irqc->base + reg);
+}
+
 static void intc_enable_or_unmask(struct irq_data *d)
 {
 unsigned long mask = 1 << d->hwirq;
@@ -65,21 +83,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
  * acks the irq before calling the interrupt handler
  */
 if (irqd_is_level_type(d))
-write_fn(mask, intc_baseaddr + IAR);
+xintc_write(xintc_irqc, IAR, mask);


So this whole thing makes only sense, when you want to support multiple
instances of that chip and then you need to store the xintc_irqc pointer as
irqchip data and retrieve it from there. Unless you do that, this "cleanup"
is just churn for nothing with the effect of making things less efficient.



Indeed the driver doesn't support multiple instances of the Xilinx Interrupt 
controller.
I don't have a use-case or the hardware for that.

So what would be the recommended course of action?


I'd really appreciate a consensus here.
I'm hoping that these patches can go in v4.10.

Thanks
ZubairLK



Regards,
ZubairLK


Thanks,

tglx

Re: [Patch V6 2/6] irqchip: xilinx: Clean up irqdomain argument and read/write

[Zubair Lutfullah Kakakhel]

Hi,

Thanks for the review.

On 10/31/2016 07:51 PM, Thomas Gleixner wrote:

On Mon, 31 Oct 2016, Zubair Lutfullah Kakakhel wrote:

The drivers read/write function handling is a bit quirky.


Can you please explain in more detail what's quirky and why it should be
done differently,


And the irqmask is passed directly to the handler.


I can't make any sense out of that sentence.  Which handler? If you talk
about the write function, then I don't see a change. So what are you
talking about?


Thanks. I'll add more detail in v7 if this patch survives.




Add a new irqchip struct to pass to the handler and
cleanup read/write handling.


I still don't see what it cleans up. You move the write function pointer
into a data structure, which is exposed by another pointer. So you create
two levels of indirection in the hotpath. The function prototype is still
the same. So all this does is making things slower unless I'm missing
something.


I wrote this patch/cleanup based on a review of driver by Marc when I moved the
driver from arch/microblaze to drivers/irqchip

"Marc Zyngier

...

>  arch/microblaze/kernel/intc.c   | 196 

>  drivers/irqchip/irq-axi-intc.c  | 196 


...

> +  /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
> +   * lazy and Michal can clean it up to something nicer when he tests
> +   * and commits this patch.  ~~gcl */
> +  root_domain = irq_domain_add_linear(intc, nr_irq, _irq_domain_ops,
> +  (void *)intr_mask);

Since you're now reworking this driver, how about addressing this
ugliness? You could store the intr_mask together with intc_baseaddr,
and the read/write functions in a global structure, and pass a
pointer to it? That would make the code a bit nicer...
"

https://patchwork.kernel.org/patch/9287933/




-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+struct xintc_irq_chip {
+   void __iomem *base;
+   struct  irq_domain *domain;
+   struct  irq_chip chip;


The tabs between struct and the structure name are bogus.


+   u32 intr_mask;
+   unsigned int (*read)(void __iomem *iomem);
+   void (*write)(u32 data, void __iomem *iomem);


Please structure that like a table:

void__iomem *base;
struct irq_domain   *domain;
struct irq_chip chip;
u32 intr_mask;
unsigned int(*read)(void __iomem *iomem);
void(*write)(u32 data, void __iomem *iomem);

Can you see how that makes parsing the struct simpler, because the data
types are clearly to identify?


That does make it look much better.




+static struct xintc_irq_chip *xintc_irqc;

 static void intc_write32(u32 val, void __iomem *addr)
 {
@@ -54,6 +60,18 @@ static unsigned int intc_read32_be(void __iomem *addr)
return ioread32be(addr);
 }

+static inline unsigned int xintc_read(struct xintc_irq_chip *xintc_irqc,
+int reg)
+{
+   return xintc_irqc->read(xintc_irqc->base + reg);
+}
+
+static inline void xintc_write(struct xintc_irq_chip *xintc_irqc,
+int reg, u32 data)
+{
+   xintc_irqc->write(data, xintc_irqc->base + reg);
+}
+
 static void intc_enable_or_unmask(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
@@ -65,21 +83,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
 * acks the irq before calling the interrupt handler
 */
if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, mask);


So this whole thing makes only sense, when you want to support multiple
instances of that chip and then you need to store the xintc_irqc pointer as
irqchip data and retrieve it from there. Unless you do that, this "cleanup"
is just churn for nothing with the effect of making things less efficient.



Indeed the driver doesn't support multiple instances of the Xilinx Interrupt 
controller.
I don't have a use-case or the hardware for that.

So what would be the recommended course of action?

Regards,
ZubairLK


Thanks,

tglx

Re: [Patch V6 2/6] irqchip: xilinx: Clean up irqdomain argument and read/write

[Zubair Lutfullah Kakakhel]

Hi,

Thanks for the review.

On 10/31/2016 07:51 PM, Thomas Gleixner wrote:

On Mon, 31 Oct 2016, Zubair Lutfullah Kakakhel wrote:

The drivers read/write function handling is a bit quirky.


Can you please explain in more detail what's quirky and why it should be
done differently,


And the irqmask is passed directly to the handler.


I can't make any sense out of that sentence.  Which handler? If you talk
about the write function, then I don't see a change. So what are you
talking about?


Thanks. I'll add more detail in v7 if this patch survives.




Add a new irqchip struct to pass to the handler and
cleanup read/write handling.


I still don't see what it cleans up. You move the write function pointer
into a data structure, which is exposed by another pointer. So you create
two levels of indirection in the hotpath. The function prototype is still
the same. So all this does is making things slower unless I'm missing
something.


I wrote this patch/cleanup based on a review of driver by Marc when I moved the
driver from arch/microblaze to drivers/irqchip

"Marc Zyngier

...

>  arch/microblaze/kernel/intc.c   | 196 

>  drivers/irqchip/irq-axi-intc.c  | 196 


...

> +  /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
> +   * lazy and Michal can clean it up to something nicer when he tests
> +   * and commits this patch.  ~~gcl */
> +  root_domain = irq_domain_add_linear(intc, nr_irq, _irq_domain_ops,
> +  (void *)intr_mask);

Since you're now reworking this driver, how about addressing this
ugliness? You could store the intr_mask together with intc_baseaddr,
and the read/write functions in a global structure, and pass a
pointer to it? That would make the code a bit nicer...
"

https://patchwork.kernel.org/patch/9287933/




-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+struct xintc_irq_chip {
+   void __iomem *base;
+   struct  irq_domain *domain;
+   struct  irq_chip chip;


The tabs between struct and the structure name are bogus.


+   u32 intr_mask;
+   unsigned int (*read)(void __iomem *iomem);
+   void (*write)(u32 data, void __iomem *iomem);


Please structure that like a table:

void__iomem *base;
struct irq_domain   *domain;
struct irq_chip chip;
u32 intr_mask;
unsigned int(*read)(void __iomem *iomem);
void(*write)(u32 data, void __iomem *iomem);

Can you see how that makes parsing the struct simpler, because the data
types are clearly to identify?


That does make it look much better.




+static struct xintc_irq_chip *xintc_irqc;

 static void intc_write32(u32 val, void __iomem *addr)
 {
@@ -54,6 +60,18 @@ static unsigned int intc_read32_be(void __iomem *addr)
return ioread32be(addr);
 }

+static inline unsigned int xintc_read(struct xintc_irq_chip *xintc_irqc,
+int reg)
+{
+   return xintc_irqc->read(xintc_irqc->base + reg);
+}
+
+static inline void xintc_write(struct xintc_irq_chip *xintc_irqc,
+int reg, u32 data)
+{
+   xintc_irqc->write(data, xintc_irqc->base + reg);
+}
+
 static void intc_enable_or_unmask(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
@@ -65,21 +83,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
 * acks the irq before calling the interrupt handler
 */
if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, mask);


So this whole thing makes only sense, when you want to support multiple
instances of that chip and then you need to store the xintc_irqc pointer as
irqchip data and retrieve it from there. Unless you do that, this "cleanup"
is just churn for nothing with the effect of making things less efficient.



Indeed the driver doesn't support multiple instances of the Xilinx Interrupt 
controller.
I don't have a use-case or the hardware for that.

So what would be the recommended course of action?

Regards,
ZubairLK


Thanks,

tglx

[Patch V6 5/6] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

The powerpc dts file upstream does not have the xlnx,kind-of-intr
property. Instead of erroring out, give a warning instead.
And attempt to continue to probe the interrupt controller while
assuming kind-of-intr is 0x0 as a fall back.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V5 -> V6
Rebase to v4.9-rc3

V5 new patch
---
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index ea15446..954e9b4 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -200,8 +200,8 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
 
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", >intr_mask);
if (ret < 0) {
-   pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
-   goto err_alloc;
+   pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
+   irqc->intr_mask = 0;
}
 
if (irqc->intr_mask >> nr_irq)
-- 
1.9.1

[Patch V6 5/6] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

The powerpc dts file upstream does not have the xlnx,kind-of-intr
property. Instead of erroring out, give a warning instead.
And attempt to continue to probe the interrupt controller while
assuming kind-of-intr is 0x0 as a fall back.

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V5 -> V6
Rebase to v4.9-rc3

V5 new patch
---
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index ea15446..954e9b4 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -200,8 +200,8 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
 
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", >intr_mask);
if (ret < 0) {
-   pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
-   goto err_alloc;
+   pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
+   irqc->intr_mask = 0;
}
 
if (irqc->intr_mask >> nr_irq)
-- 
1.9.1

[Patch V6 2/6] irqchip: xilinx: Clean up irqdomain argument and read/write

[Zubair Lutfullah Kakakhel]

The drivers read/write function handling is a bit quirky.
And the irqmask is passed directly to the handler.

Add a new irqchip struct to pass to the handler and
cleanup read/write handling.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V5 -> V6
Removed __func__ from printk
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Better error handling

V3 -> V4
Better error handling for kzalloc
Erroring out if the axi intc is probed twice as that isn't
supported

V2 -> V3
New patch. Cleans up driver structure
---
 drivers/irqchip/irq-xilinx-intc.c | 110 +-
 1 file changed, 74 insertions(+), 36 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 90bec7d..c2052fb 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -16,8 +16,6 @@
 #include 
 #include 
 
-static void __iomem *intc_baseaddr;
-
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
 #define IPR 0x04   /* Interrupt Pending Register */
@@ -31,8 +29,16 @@
 #define MER_ME (1<<0)
 #define MER_HIE (1<<1)
 
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+struct xintc_irq_chip {
+   void __iomem *base;
+   struct  irq_domain *domain;
+   struct  irq_chip chip;
+   u32 intr_mask;
+   unsigned int (*read)(void __iomem *iomem);
+   void (*write)(u32 data, void __iomem *iomem);
+};
+
+static struct xintc_irq_chip *xintc_irqc;
 
 static void intc_write32(u32 val, void __iomem *addr)
 {
@@ -54,6 +60,18 @@ static unsigned int intc_read32_be(void __iomem *addr)
return ioread32be(addr);
 }
 
+static inline unsigned int xintc_read(struct xintc_irq_chip *xintc_irqc,
+int reg)
+{
+   return xintc_irqc->read(xintc_irqc->base + reg);
+}
+
+static inline void xintc_write(struct xintc_irq_chip *xintc_irqc,
+int reg, u32 data)
+{
+   xintc_irqc->write(data, xintc_irqc->base + reg);
+}
+
 static void intc_enable_or_unmask(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
@@ -65,21 +83,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
 * acks the irq before calling the interrupt handler
 */
if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, mask);
 
-   write_fn(mask, intc_baseaddr + SIE);
+   xintc_write(xintc_irqc, SIE, mask);
 }
 
 static void intc_disable_or_mask(struct irq_data *d)
 {
pr_debug("disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
+   xintc_write(xintc_irqc, CIE, 1 << d->hwirq);
 }
 
 static void intc_ack(struct irq_data *d)
 {
pr_debug("ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, 1 << d->hwirq);
 }
 
 static void intc_mask_ack(struct irq_data *d)
@@ -87,8 +105,8 @@ static void intc_mask_ack(struct irq_data *d)
unsigned long mask = 1 << d->hwirq;
 
pr_debug("disable_and_ack: %ld\n", d->hwirq);
-   write_fn(mask, intc_baseaddr + CIE);
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, CIE, mask);
+   xintc_write(xintc_irqc, IAR, mask);
 }
 
 static struct irq_chip intc_dev = {
@@ -105,7 +123,7 @@ unsigned int get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
-   hwirq = read_fn(intc_baseaddr + IVR);
+   hwirq = xintc_read(xintc_irqc, IVR);
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
@@ -116,7 +134,8 @@ unsigned int get_irq(void)
 
 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t 
hw)
 {
-   u32 intr_mask = (u32)d->host_data;
+   struct xintc_irq_chip *irqc = d->host_data;
+   u32 intr_mask = irqc->intr_mask;
 
if (intr_mask & (1 << hw)) {
irq_set_chip_and_handler_name(irq, _dev,
@@ -138,59 +157,78 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
-   u32 nr_irq, intr_mask;
+   u32 nr_irq;
int ret;
+   struct xintc_irq_chip *irqc;
+
+   if (xintc_irqc) {
+   pr_err("irq-xilinx: Multiple instances aren't supported\n");
+   return -EINVAL;
+   }
+
+   irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
+   if (!irqc)
+   return -ENOMEM;
 
-   intc_baseaddr = of_iomap(intc, 0);
-   BUG_ON(!intc_baseaddr)

[Patch V6 4/6] irqchip: xilinx: Add support for parent intc

[Zubair Lutfullah Kakakhel]

The MIPS based xilfpga platform has the following IRQ structure

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller

Add support for the driver to chain the irq handler

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V5 -> V6
Use chained_irq_enter and chained_irq_exit
Add error check for irq_of_parse_and_map
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Missing curly braces

V3 -> V4
Clean up if/else when a parent is found
Pass irqchip structure to handler as data

V2 -> V3
Reused existing parent node instead of finding again.
Cleanup up handler based on review

V1 -> V2

No change
---
 drivers/irqchip/irq-xilinx-intc.c | 36 ++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 1f37089..ea15446 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -12,9 +12,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
@@ -154,11 +156,26 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
.map = xintc_map,
 };
 
+static void xil_intc_irq_handler(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   u32 pending;
+
+   chained_irq_enter(chip, desc);
+   do {
+   pending = xintc_get_irq();
+   if (pending == -1U)
+   break;
+   generic_handle_irq(pending);
+   } while (true);
+   chained_irq_exit(chip, desc);
+}
+
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
u32 nr_irq;
-   int ret;
+   int ret, irq;
struct xintc_irq_chip *irqc;
 
if (xintc_irqc) {
@@ -220,7 +237,22 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
goto err_alloc;
}
 
-   irq_set_default_host(root_domain);
+   if (parent) {
+   irq = irq_of_parse_and_map(intc, 0);
+   if (irq) {
+   irq_set_chained_handler_and_data(irq,
+xil_intc_irq_handler,
+irqc);
+   } else {
+   pr_err("irq-xilinx: interrupts property not in DT\n");
+   ret = -EINVAL;
+   goto err_alloc;
+   }
+
+
+   } else {
+   irq_set_default_host(root_domain);
+   }
 
return 0;
 
-- 
1.9.1

[Patch V6 3/6] irqchip: xilinx: Rename get_irq to xintc_get_irq

[Zubair Lutfullah Kakakhel]

Now that the driver is generic and used by multiple archs,
get_irq is too generic.

Rename get_irq to xintc_get_irq to avoid any conflicts

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V5 -> V6
Removed __func__ in printk
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Use __func__ in pr_err

V3 -> V4
New patch.
---
 arch/microblaze/include/asm/irq.h | 2 +-
 arch/microblaze/kernel/irq.c  | 4 ++--
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/microblaze/include/asm/irq.h 
b/arch/microblaze/include/asm/irq.h
index bab3b13..d785def 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -16,6 +16,6 @@
 extern void do_IRQ(struct pt_regs *regs);
 
 /* should be defined in each interrupt controller driver */
-extern unsigned int get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* _ASM_MICROBLAZE_IRQ_H */
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 11e24de..903dad8 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -29,12 +29,12 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
trace_hardirqs_off();
 
irq_enter();
-   irq = get_irq();
+   irq = xintc_get_irq();
 next_irq:
BUG_ON(!irq);
generic_handle_irq(irq);
 
-   irq = get_irq();
+   irq = xintc_get_irq();
if (irq != -1U) {
pr_debug("next irq: %d\n", irq);
++concurrent_irq;
diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index c2052fb..1f37089 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -119,7 +119,7 @@ static void intc_mask_ack(struct irq_data *d)
 
 static struct irq_domain *root_domain;
 
-unsigned int get_irq(void)
+unsigned int xintc_get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
@@ -127,7 +127,7 @@ unsigned int get_irq(void)
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
-   pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
+   pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
 
return irq;
 }
-- 
1.9.1

[Patch V6 1/6] microblaze: irqchip: Move intc driver to irqchip

[Zubair Lutfullah Kakakhel]

The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform and a few PowerPC based platforms.

Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V5 -> V6
Rebase to v4.9-rc3

V4 -> V5
Rebase to v4.9-rc1
Renamed back to irq-xilinx-intc.c

V3 -> V4
No change

V2 -> V3
No change here. Cleanup patches follow after this patch.
Its debatable to cleanup before/after move. Decided to place cleanup
after move to put history in new place.

V1 -> V2

Renamed irq-xilinx to irq-axi-intc
Renamed CONFIG_XILINX_INTC to CONFIG_XILINX_AXI_INTC
Patch is now without rename flag so as to facilitate review
---
 arch/microblaze/Kconfig   |   1 +
 arch/microblaze/kernel/Makefile   |   2 +-
 arch/microblaze/kernel/intc.c | 196 --
 drivers/irqchip/Kconfig   |   4 +
 drivers/irqchip/Makefile  |   1 +
 drivers/irqchip/irq-xilinx-intc.c | 196 ++
 6 files changed, 203 insertions(+), 197 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 86f6572..85885a5 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -27,6 +27,7 @@ config MICROBLAZE
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_OPROFILE
select IRQ_DOMAIN
+   select XILINX_INTC
select MODULES_USE_ELF_RELA
select OF
select OF_EARLY_FLATTREE
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index f08baca..e098381 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -15,7 +15,7 @@ endif
 extra-y := head.o vmlinux.lds
 
 obj-y += dma.o exceptions.o \
-   hw_exception_handler.o intc.o irq.o \
+   hw_exception_handler.o irq.o \
platform.o process.o prom.o ptrace.o \
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
 
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
deleted file mode 100644
index 90bec7d..000
--- a/arch/microblaze/kernel/intc.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (C) 2007-2013 Michal Simek <mon...@monstr.eu>
- * Copyright (C) 2012-2013 Xilinx, Inc.
- * Copyright (C) 2007-2009 PetaLogix
- * Copyright (C) 2006 Atmark Techno, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-static void __iomem *intc_baseaddr;
-
-/* No one else should require these constants, so define them locally here. */
-#define ISR 0x00   /* Interrupt Status Register */
-#define IPR 0x04   /* Interrupt Pending Register */
-#define IER 0x08   /* Interrupt Enable Register */
-#define IAR 0x0c   /* Interrupt Acknowledge Register */
-#define SIE 0x10   /* Set Interrupt Enable bits */
-#define CIE 0x14   /* Clear Interrupt Enable bits */
-#define IVR 0x18   /* Interrupt Vector Register */
-#define MER 0x1c   /* Master Enable Register */
-
-#define MER_ME (1<<0)
-#define MER_HIE (1<<1)
-
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
-
-static void intc_write32(u32 val, void __iomem *addr)
-{
-   iowrite32(val, addr);
-}
-
-static unsigned int intc_read32(void __iomem *addr)
-{
-   return ioread32(addr);
-}
-
-static void intc_write32_be(u32 val, void __iomem *addr)
-{
-   iowrite32be(val, addr);
-}
-
-static unsigned int intc_read32_be(void __iomem *addr)
-{
-   return ioread32be(addr);
-}
-
-static void intc_enable_or_unmask(struct irq_data *d)
-{
-   unsigned long mask = 1 << d->hwirq;
-
-   pr_debug("enable_or_unmask: %ld\n", d->hwirq);
-
-   /* ack level irqs because they can't be acked during
-* ack function since the handle_level_irq function
-* acks the irq before calling the interrupt handler
-*/
-   if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
-
-   write_fn(mask, intc_baseaddr + SIE);
-}
-
-static void intc_disable_or_mask(struct irq_data *d)
-{
-   pr_debug("disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
-}
-
-static void intc_ack(struct irq_data *d)
-{
-   pr_debug("ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
-}
-
-static void intc_mask_ack(struct irq_data *d)
-{
-   unsigned long mask = 1 << d->hwirq

[Patch V6 2/6] irqchip: xilinx: Clean up irqdomain argument and read/write

[Zubair Lutfullah Kakakhel]

The drivers read/write function handling is a bit quirky.
And the irqmask is passed directly to the handler.

Add a new irqchip struct to pass to the handler and
cleanup read/write handling.

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V5 -> V6
Removed __func__ from printk
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Better error handling

V3 -> V4
Better error handling for kzalloc
Erroring out if the axi intc is probed twice as that isn't
supported

V2 -> V3
New patch. Cleans up driver structure
---
 drivers/irqchip/irq-xilinx-intc.c | 110 +-
 1 file changed, 74 insertions(+), 36 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 90bec7d..c2052fb 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -16,8 +16,6 @@
 #include 
 #include 
 
-static void __iomem *intc_baseaddr;
-
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
 #define IPR 0x04   /* Interrupt Pending Register */
@@ -31,8 +29,16 @@
 #define MER_ME (1<<0)
 #define MER_HIE (1<<1)
 
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+struct xintc_irq_chip {
+   void __iomem *base;
+   struct  irq_domain *domain;
+   struct  irq_chip chip;
+   u32 intr_mask;
+   unsigned int (*read)(void __iomem *iomem);
+   void (*write)(u32 data, void __iomem *iomem);
+};
+
+static struct xintc_irq_chip *xintc_irqc;
 
 static void intc_write32(u32 val, void __iomem *addr)
 {
@@ -54,6 +60,18 @@ static unsigned int intc_read32_be(void __iomem *addr)
return ioread32be(addr);
 }
 
+static inline unsigned int xintc_read(struct xintc_irq_chip *xintc_irqc,
+int reg)
+{
+   return xintc_irqc->read(xintc_irqc->base + reg);
+}
+
+static inline void xintc_write(struct xintc_irq_chip *xintc_irqc,
+int reg, u32 data)
+{
+   xintc_irqc->write(data, xintc_irqc->base + reg);
+}
+
 static void intc_enable_or_unmask(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
@@ -65,21 +83,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
 * acks the irq before calling the interrupt handler
 */
if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, mask);
 
-   write_fn(mask, intc_baseaddr + SIE);
+   xintc_write(xintc_irqc, SIE, mask);
 }
 
 static void intc_disable_or_mask(struct irq_data *d)
 {
pr_debug("disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
+   xintc_write(xintc_irqc, CIE, 1 << d->hwirq);
 }
 
 static void intc_ack(struct irq_data *d)
 {
pr_debug("ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, 1 << d->hwirq);
 }
 
 static void intc_mask_ack(struct irq_data *d)
@@ -87,8 +105,8 @@ static void intc_mask_ack(struct irq_data *d)
unsigned long mask = 1 << d->hwirq;
 
pr_debug("disable_and_ack: %ld\n", d->hwirq);
-   write_fn(mask, intc_baseaddr + CIE);
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, CIE, mask);
+   xintc_write(xintc_irqc, IAR, mask);
 }
 
 static struct irq_chip intc_dev = {
@@ -105,7 +123,7 @@ unsigned int get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
-   hwirq = read_fn(intc_baseaddr + IVR);
+   hwirq = xintc_read(xintc_irqc, IVR);
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
@@ -116,7 +134,8 @@ unsigned int get_irq(void)
 
 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t 
hw)
 {
-   u32 intr_mask = (u32)d->host_data;
+   struct xintc_irq_chip *irqc = d->host_data;
+   u32 intr_mask = irqc->intr_mask;
 
if (intr_mask & (1 << hw)) {
irq_set_chip_and_handler_name(irq, _dev,
@@ -138,59 +157,78 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
-   u32 nr_irq, intr_mask;
+   u32 nr_irq;
int ret;
+   struct xintc_irq_chip *irqc;
+
+   if (xintc_irqc) {
+   pr_err("irq-xilinx: Multiple instances aren't supported\n");
+   return -EINVAL;
+   }
+
+   irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
+   if (!irqc)
+   return -ENOMEM;
 
-   intc_baseaddr = of_iomap(intc, 0);
-   BUG_ON(!intc_baseaddr);
+   xintc_irqc = irqc;
+

[Patch V6 4/6] irqchip: xilinx: Add support for parent intc

[Zubair Lutfullah Kakakhel]

The MIPS based xilfpga platform has the following IRQ structure

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller

Add support for the driver to chain the irq handler

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V5 -> V6
Use chained_irq_enter and chained_irq_exit
Add error check for irq_of_parse_and_map
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Missing curly braces

V3 -> V4
Clean up if/else when a parent is found
Pass irqchip structure to handler as data

V2 -> V3
Reused existing parent node instead of finding again.
Cleanup up handler based on review

V1 -> V2

No change
---
 drivers/irqchip/irq-xilinx-intc.c | 36 ++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 1f37089..ea15446 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -12,9 +12,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
@@ -154,11 +156,26 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
.map = xintc_map,
 };
 
+static void xil_intc_irq_handler(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   u32 pending;
+
+   chained_irq_enter(chip, desc);
+   do {
+   pending = xintc_get_irq();
+   if (pending == -1U)
+   break;
+   generic_handle_irq(pending);
+   } while (true);
+   chained_irq_exit(chip, desc);
+}
+
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
u32 nr_irq;
-   int ret;
+   int ret, irq;
struct xintc_irq_chip *irqc;
 
if (xintc_irqc) {
@@ -220,7 +237,22 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
goto err_alloc;
}
 
-   irq_set_default_host(root_domain);
+   if (parent) {
+   irq = irq_of_parse_and_map(intc, 0);
+   if (irq) {
+   irq_set_chained_handler_and_data(irq,
+xil_intc_irq_handler,
+irqc);
+   } else {
+   pr_err("irq-xilinx: interrupts property not in DT\n");
+   ret = -EINVAL;
+   goto err_alloc;
+   }
+
+
+   } else {
+   irq_set_default_host(root_domain);
+   }
 
return 0;
 
-- 
1.9.1

[Patch V6 3/6] irqchip: xilinx: Rename get_irq to xintc_get_irq

[Zubair Lutfullah Kakakhel]

Now that the driver is generic and used by multiple archs,
get_irq is too generic.

Rename get_irq to xintc_get_irq to avoid any conflicts

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V5 -> V6
Removed __func__ in printk
Rebase to v4.9-rc3

V4 -> V5
Rebased to v4.9-rc1
Use __func__ in pr_err

V3 -> V4
New patch.
---
 arch/microblaze/include/asm/irq.h | 2 +-
 arch/microblaze/kernel/irq.c  | 4 ++--
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/microblaze/include/asm/irq.h 
b/arch/microblaze/include/asm/irq.h
index bab3b13..d785def 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -16,6 +16,6 @@
 extern void do_IRQ(struct pt_regs *regs);
 
 /* should be defined in each interrupt controller driver */
-extern unsigned int get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* _ASM_MICROBLAZE_IRQ_H */
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 11e24de..903dad8 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -29,12 +29,12 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
trace_hardirqs_off();
 
irq_enter();
-   irq = get_irq();
+   irq = xintc_get_irq();
 next_irq:
BUG_ON(!irq);
generic_handle_irq(irq);
 
-   irq = get_irq();
+   irq = xintc_get_irq();
if (irq != -1U) {
pr_debug("next irq: %d\n", irq);
++concurrent_irq;
diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index c2052fb..1f37089 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -119,7 +119,7 @@ static void intc_mask_ack(struct irq_data *d)
 
 static struct irq_domain *root_domain;
 
-unsigned int get_irq(void)
+unsigned int xintc_get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
@@ -127,7 +127,7 @@ unsigned int get_irq(void)
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
-   pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
+   pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
 
return irq;
 }
-- 
1.9.1

[Patch V6 1/6] microblaze: irqchip: Move intc driver to irqchip

[Zubair Lutfullah Kakakhel]

The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform and a few PowerPC based platforms.

Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V5 -> V6
Rebase to v4.9-rc3

V4 -> V5
Rebase to v4.9-rc1
Renamed back to irq-xilinx-intc.c

V3 -> V4
No change

V2 -> V3
No change here. Cleanup patches follow after this patch.
Its debatable to cleanup before/after move. Decided to place cleanup
after move to put history in new place.

V1 -> V2

Renamed irq-xilinx to irq-axi-intc
Renamed CONFIG_XILINX_INTC to CONFIG_XILINX_AXI_INTC
Patch is now without rename flag so as to facilitate review
---
 arch/microblaze/Kconfig   |   1 +
 arch/microblaze/kernel/Makefile   |   2 +-
 arch/microblaze/kernel/intc.c | 196 --
 drivers/irqchip/Kconfig   |   4 +
 drivers/irqchip/Makefile  |   1 +
 drivers/irqchip/irq-xilinx-intc.c | 196 ++
 6 files changed, 203 insertions(+), 197 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 86f6572..85885a5 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -27,6 +27,7 @@ config MICROBLAZE
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_OPROFILE
select IRQ_DOMAIN
+   select XILINX_INTC
select MODULES_USE_ELF_RELA
select OF
select OF_EARLY_FLATTREE
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index f08baca..e098381 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -15,7 +15,7 @@ endif
 extra-y := head.o vmlinux.lds
 
 obj-y += dma.o exceptions.o \
-   hw_exception_handler.o intc.o irq.o \
+   hw_exception_handler.o irq.o \
platform.o process.o prom.o ptrace.o \
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
 
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
deleted file mode 100644
index 90bec7d..000
--- a/arch/microblaze/kernel/intc.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (C) 2007-2013 Michal Simek 
- * Copyright (C) 2012-2013 Xilinx, Inc.
- * Copyright (C) 2007-2009 PetaLogix
- * Copyright (C) 2006 Atmark Techno, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-static void __iomem *intc_baseaddr;
-
-/* No one else should require these constants, so define them locally here. */
-#define ISR 0x00   /* Interrupt Status Register */
-#define IPR 0x04   /* Interrupt Pending Register */
-#define IER 0x08   /* Interrupt Enable Register */
-#define IAR 0x0c   /* Interrupt Acknowledge Register */
-#define SIE 0x10   /* Set Interrupt Enable bits */
-#define CIE 0x14   /* Clear Interrupt Enable bits */
-#define IVR 0x18   /* Interrupt Vector Register */
-#define MER 0x1c   /* Master Enable Register */
-
-#define MER_ME (1<<0)
-#define MER_HIE (1<<1)
-
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
-
-static void intc_write32(u32 val, void __iomem *addr)
-{
-   iowrite32(val, addr);
-}
-
-static unsigned int intc_read32(void __iomem *addr)
-{
-   return ioread32(addr);
-}
-
-static void intc_write32_be(u32 val, void __iomem *addr)
-{
-   iowrite32be(val, addr);
-}
-
-static unsigned int intc_read32_be(void __iomem *addr)
-{
-   return ioread32be(addr);
-}
-
-static void intc_enable_or_unmask(struct irq_data *d)
-{
-   unsigned long mask = 1 << d->hwirq;
-
-   pr_debug("enable_or_unmask: %ld\n", d->hwirq);
-
-   /* ack level irqs because they can't be acked during
-* ack function since the handle_level_irq function
-* acks the irq before calling the interrupt handler
-*/
-   if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
-
-   write_fn(mask, intc_baseaddr + SIE);
-}
-
-static void intc_disable_or_mask(struct irq_data *d)
-{
-   pr_debug("disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
-}
-
-static void intc_ack(struct irq_data *d)
-{
-   pr_debug("ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
-}
-
-static void intc_mask_ack(struct irq_data *d)
-{
-   unsigned long mask = 1 << d->hwirq;
-
-   pr_debug("disable_and_ack: %ld\n", d->h

[Patch V6 6/6] powerpc/virtex: Use generic xilinx irqchip driver

[Zubair Lutfullah Kakakhel]

The Xilinx interrupt controller driver is now available in drivers/irqchip.
Switch to using that driver.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
Acked-by: Michael Ellerman <m...@ellerman.id.au> (powerpc)

---
V5 -> V6 Added Acked-by Micheal Ellerman

V5 New patch

Tested on virtex440-ml507 using qemu
---
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +
 drivers/irqchip/irq-xilinx-intc.c  |   3 +-
 7 files changed, 9 insertions(+), 213 deletions(-)

diff --git a/arch/powerpc/include/asm/xilinx_intc.h 
b/arch/powerpc/include/asm/xilinx_intc.h
index 343612f..3192d7f 100644
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ b/arch/powerpc/include/asm/xilinx_intc.h
@@ -14,7 +14,7 @@
 #ifdef __KERNEL__
 
 extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xilinx_intc_get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/platforms/40x/Kconfig 
b/arch/powerpc/platforms/40x/Kconfig
index e3257f2..1d7c1b1 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -64,6 +64,7 @@ config XILINX_VIRTEX_GENERIC_BOARD
default n
select XILINX_VIRTEX_II_PRO
select XILINX_VIRTEX_4_FX
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards.
 
diff --git a/arch/powerpc/platforms/40x/virtex.c 
b/arch/powerpc/platforms/40x/virtex.c
index 91a08ea..e3d5e09 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -48,7 +48,7 @@ static int __init virtex_probe(void)
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.restart= ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/Kconfig 
b/arch/powerpc/platforms/44x/Kconfig
index 48fc180..25b8d64 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -241,6 +241,7 @@ config XILINX_VIRTEX440_GENERIC_BOARD
depends on 44x
default n
select XILINX_VIRTEX_5_FXT
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards
  that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
diff --git a/arch/powerpc/platforms/44x/virtex.c 
b/arch/powerpc/platforms/44x/virtex.c
index a7e0802..3eb13ed 100644
--- a/arch/powerpc/platforms/44x/virtex.c
+++ b/arch/powerpc/platforms/44x/virtex.c
@@ -54,7 +54,7 @@ static int __init virtex_probe(void)
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.calibrate_decr = generic_calibrate_decr,
.restart= ppc4xx_reset_system,
 };
diff --git a/arch/powerpc/sysdev/xilinx_intc.c 
b/arch/powerpc/sysdev/xilinx_intc.c
index 0f52d79..4a86dcf 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -29,194 +29,7 @@
 #include 
 #include 
 #include 
-
-/*
- * INTC Registers
- */
-#define XINTC_ISR  0   /* Interrupt Status */
-#define XINTC_IPR  4   /* Interrupt Pending */
-#define XINTC_IER  8   /* Interrupt Enable */
-#define XINTC_IAR  12  /* Interrupt Acknowledge */
-#define XINTC_SIE  16  /* Set Interrupt Enable bits */
-#define XINTC_CIE  20  /* Clear Interrupt Enable bits */
-#define XINTC_IVR  24  /* Interrupt Vector */
-#define XINTC_MER  28  /* Master Enable */
-
-static struct irq_domain *master_irqhost;
-
-#define XILINX_INTC_MAXIRQS(32)
-
-/* The following table allows the interrupt type, edge or level,
- * to be cached after being read from the device tree until the interrupt
- * is mapped
- */
-static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
-
-/* Map the interrupt type from the device tree to the interrupt types
- * used by the interrupt subsystem
- */
-static unsigned char xilinx_intc_map_senses[] = {
-   IRQ_TYPE_EDGE_RISING,
-   IRQ_TYPE_EDGE_FALLING,
-   IRQ_TYPE_LEVEL_HIGH,
-   IRQ_TYPE_LEVEL_LOW,
-};
-
-/*
- * The interrupt controller is setup such that it doesn't work well with
- * the level interrupt handler in the kernel because the handler acks the
- * interrupt

[Patch V6 6/6] powerpc/virtex: Use generic xilinx irqchip driver

[Zubair Lutfullah Kakakhel]

The Xilinx interrupt controller driver is now available in drivers/irqchip.
Switch to using that driver.

Signed-off-by: Zubair Lutfullah Kakakhel 
Acked-by: Michael Ellerman  (powerpc)

---
V5 -> V6 Added Acked-by Micheal Ellerman

V5 New patch

Tested on virtex440-ml507 using qemu
---
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +
 drivers/irqchip/irq-xilinx-intc.c  |   3 +-
 7 files changed, 9 insertions(+), 213 deletions(-)

diff --git a/arch/powerpc/include/asm/xilinx_intc.h 
b/arch/powerpc/include/asm/xilinx_intc.h
index 343612f..3192d7f 100644
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ b/arch/powerpc/include/asm/xilinx_intc.h
@@ -14,7 +14,7 @@
 #ifdef __KERNEL__
 
 extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xilinx_intc_get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/platforms/40x/Kconfig 
b/arch/powerpc/platforms/40x/Kconfig
index e3257f2..1d7c1b1 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -64,6 +64,7 @@ config XILINX_VIRTEX_GENERIC_BOARD
default n
select XILINX_VIRTEX_II_PRO
select XILINX_VIRTEX_4_FX
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards.
 
diff --git a/arch/powerpc/platforms/40x/virtex.c 
b/arch/powerpc/platforms/40x/virtex.c
index 91a08ea..e3d5e09 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -48,7 +48,7 @@ static int __init virtex_probe(void)
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.restart= ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/Kconfig 
b/arch/powerpc/platforms/44x/Kconfig
index 48fc180..25b8d64 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -241,6 +241,7 @@ config XILINX_VIRTEX440_GENERIC_BOARD
depends on 44x
default n
select XILINX_VIRTEX_5_FXT
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards
  that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
diff --git a/arch/powerpc/platforms/44x/virtex.c 
b/arch/powerpc/platforms/44x/virtex.c
index a7e0802..3eb13ed 100644
--- a/arch/powerpc/platforms/44x/virtex.c
+++ b/arch/powerpc/platforms/44x/virtex.c
@@ -54,7 +54,7 @@ static int __init virtex_probe(void)
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.calibrate_decr = generic_calibrate_decr,
.restart= ppc4xx_reset_system,
 };
diff --git a/arch/powerpc/sysdev/xilinx_intc.c 
b/arch/powerpc/sysdev/xilinx_intc.c
index 0f52d79..4a86dcf 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -29,194 +29,7 @@
 #include 
 #include 
 #include 
-
-/*
- * INTC Registers
- */
-#define XINTC_ISR  0   /* Interrupt Status */
-#define XINTC_IPR  4   /* Interrupt Pending */
-#define XINTC_IER  8   /* Interrupt Enable */
-#define XINTC_IAR  12  /* Interrupt Acknowledge */
-#define XINTC_SIE  16  /* Set Interrupt Enable bits */
-#define XINTC_CIE  20  /* Clear Interrupt Enable bits */
-#define XINTC_IVR  24  /* Interrupt Vector */
-#define XINTC_MER  28  /* Master Enable */
-
-static struct irq_domain *master_irqhost;
-
-#define XILINX_INTC_MAXIRQS(32)
-
-/* The following table allows the interrupt type, edge or level,
- * to be cached after being read from the device tree until the interrupt
- * is mapped
- */
-static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
-
-/* Map the interrupt type from the device tree to the interrupt types
- * used by the interrupt subsystem
- */
-static unsigned char xilinx_intc_map_senses[] = {
-   IRQ_TYPE_EDGE_RISING,
-   IRQ_TYPE_EDGE_FALLING,
-   IRQ_TYPE_LEVEL_HIGH,
-   IRQ_TYPE_LEVEL_LOW,
-};
-
-/*
- * The interrupt controller is setup such that it doesn't work well with
- * the level interrupt handler in the kernel because the handler acks the
- * interrupt before calling the application interrupt handler. To d

[Patch V6 0/6] microblaze/PowerPC: Move irq-xilinx

[Zubair Lutfullah Kakakhel]

Hi,

The MIPS based Xilfpga platform uses the Xilinx interrupt controller
daisy chained to the MIPS microAptiv cpu interrupt controller.

This patch series moves the Xilinx interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then removes another implementation of the driver in arch/powerpc.

This effort results in one common driver usable by mips,microblaze
and powerpc.

Compile tested on microblaze-el.
Tested using qemu-system-ppc using virtix440-ml507
Tested on MIPSfpga platform.

Based on v4.9-rc3

Thanks,
ZubairLK

V5 -> V6
Split patch series. Patches for arch/mips can go separately
Rebase to v4.9-rc3
Added chained_irq_enter/exit
Removed __func__ used in pr_err

V4 -> V5
Added a new patch that removes the PPC driver
Rebase to v4.9-rc1
Better error handling

V3 -> V4
Better error handling
Some minor fixups

V2 -> V3
Cleanup the interrupt controller driver a bit based on feedback
Rebase to v4.8-rc4

V1 -> V2
Resubmitting without truncating the diff output for file moves
Removed accidental local mac address entry
Individual logs have more detail

Zubair Lutfullah Kakakhel (6):
  microblaze: irqchip: Move intc driver to irqchip
  irqchip: xilinx: Clean up irqdomain argument and read/write
  irqchip: xilinx: Rename get_irq to xintc_get_irq
  irqchip: xilinx: Add support for parent intc
  irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided
  powerpc/virtex: Use generic xilinx irqchip driver

 arch/microblaze/Kconfig|   1 +
 arch/microblaze/include/asm/irq.h  |   2 +-
 arch/microblaze/kernel/Makefile|   2 +-
 arch/microblaze/kernel/intc.c  | 196 
 arch/microblaze/kernel/irq.c   |   4 +-
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +-
 drivers/irqchip/Kconfig|   4 +
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-xilinx-intc.c  | 267 +
 14 files changed, 284 insertions(+), 412 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

-- 
1.9.1

[Patch V6 0/6] microblaze/PowerPC: Move irq-xilinx

[Zubair Lutfullah Kakakhel]

Hi,

The MIPS based Xilfpga platform uses the Xilinx interrupt controller
daisy chained to the MIPS microAptiv cpu interrupt controller.

This patch series moves the Xilinx interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then removes another implementation of the driver in arch/powerpc.

This effort results in one common driver usable by mips,microblaze
and powerpc.

Compile tested on microblaze-el.
Tested using qemu-system-ppc using virtix440-ml507
Tested on MIPSfpga platform.

Based on v4.9-rc3

Thanks,
ZubairLK

V5 -> V6
Split patch series. Patches for arch/mips can go separately
Rebase to v4.9-rc3
Added chained_irq_enter/exit
Removed __func__ used in pr_err

V4 -> V5
Added a new patch that removes the PPC driver
Rebase to v4.9-rc1
Better error handling

V3 -> V4
Better error handling
Some minor fixups

V2 -> V3
Cleanup the interrupt controller driver a bit based on feedback
Rebase to v4.8-rc4

V1 -> V2
Resubmitting without truncating the diff output for file moves
Removed accidental local mac address entry
Individual logs have more detail

Zubair Lutfullah Kakakhel (6):
  microblaze: irqchip: Move intc driver to irqchip
  irqchip: xilinx: Clean up irqdomain argument and read/write
  irqchip: xilinx: Rename get_irq to xintc_get_irq
  irqchip: xilinx: Add support for parent intc
  irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided
  powerpc/virtex: Use generic xilinx irqchip driver

 arch/microblaze/Kconfig|   1 +
 arch/microblaze/include/asm/irq.h  |   2 +-
 arch/microblaze/kernel/Makefile|   2 +-
 arch/microblaze/kernel/intc.c  | 196 
 arch/microblaze/kernel/irq.c   |   4 +-
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +-
 drivers/irqchip/Kconfig|   4 +
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-xilinx-intc.c  | 267 +
 14 files changed, 284 insertions(+), 412 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

-- 
1.9.1

Re: [Patch v5 04/12] irqchip: xilinx: Add support for parent intc

[Zubair Lutfullah Kakakhel]

Hi,

Thanks for the review.
Some comments in-line.

On 10/21/2016 10:48 AM, Marc Zyngier wrote:

On 17/10/16 17:52, Zubair Lutfullah Kakakhel wrote:

The MIPS based xilfpga platform has the following IRQ structure

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller

Add support for the driver to chain the irq handler

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V4 -> V5
Rebased to v4.9-rc1
Missing curly braces

V3 -> V4
Clean up if/else when a parent is found
Pass irqchip structure to handler as data

V2 -> V3
Reused existing parent node instead of finding again.
Cleanup up handler based on review

V1 -> V2

No change
---
 drivers/irqchip/irq-xilinx-intc.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 45e5154..dbf8b0c 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 

 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
@@ -154,11 +155,23 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
.map = xintc_map,
 };

+static void xil_intc_irq_handler(struct irq_desc *desc)
+{
+   u32 pending;
+
+   do {
+   pending = xintc_get_irq();
+   if (pending == -1U)
+   break;
+   generic_handle_irq(pending);
+   } while (true);


This is missing the chained_irq_enter()/exit() calls, which will lead to
races or lockups on the root irqchip.



I 'll fix it up in the next series.


+}
+
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
u32 nr_irq;
-   int ret;
+   int ret, irq;
struct xintc_irq_chip *irqc;

if (xintc_irqc) {
@@ -221,7 +234,16 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
goto err_alloc;
}

-   irq_set_default_host(root_domain);
+   if (parent) {
+   irq = irq_of_parse_and_map(intc, 0);
+   if (irq)
+   irq_set_chained_handler_and_data(irq,
+xil_intc_irq_handler,
+irqc);
+


Shouldn't you return an error if irq is zero?



I'll add the following for the error case

pr_err("%s: Parent exists but interrupts property not defined\n" , 
__func__);
goto err_alloc;

Thanks
ZubairLK


+   } else {
+   irq_set_default_host(root_domain);
+   }

return 0;




Thanks,

M.

Re: [Patch v5 04/12] irqchip: xilinx: Add support for parent intc

[Zubair Lutfullah Kakakhel]

Hi,

Thanks for the review.
Some comments in-line.

On 10/21/2016 10:48 AM, Marc Zyngier wrote:

On 17/10/16 17:52, Zubair Lutfullah Kakakhel wrote:

The MIPS based xilfpga platform has the following IRQ structure

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller

Add support for the driver to chain the irq handler

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V4 -> V5
Rebased to v4.9-rc1
Missing curly braces

V3 -> V4
Clean up if/else when a parent is found
Pass irqchip structure to handler as data

V2 -> V3
Reused existing parent node instead of finding again.
Cleanup up handler based on review

V1 -> V2

No change
---
 drivers/irqchip/irq-xilinx-intc.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 45e5154..dbf8b0c 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 

 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
@@ -154,11 +155,23 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
.map = xintc_map,
 };

+static void xil_intc_irq_handler(struct irq_desc *desc)
+{
+   u32 pending;
+
+   do {
+   pending = xintc_get_irq();
+   if (pending == -1U)
+   break;
+   generic_handle_irq(pending);
+   } while (true);


This is missing the chained_irq_enter()/exit() calls, which will lead to
races or lockups on the root irqchip.



I 'll fix it up in the next series.


+}
+
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
u32 nr_irq;
-   int ret;
+   int ret, irq;
struct xintc_irq_chip *irqc;

if (xintc_irqc) {
@@ -221,7 +234,16 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
goto err_alloc;
}

-   irq_set_default_host(root_domain);
+   if (parent) {
+   irq = irq_of_parse_and_map(intc, 0);
+   if (irq)
+   irq_set_chained_handler_and_data(irq,
+xil_intc_irq_handler,
+irqc);
+


Shouldn't you return an error if irq is zero?



I'll add the following for the error case

pr_err("%s: Parent exists but interrupts property not defined\n" , 
__func__);
goto err_alloc;

Thanks
ZubairLK


+   } else {
+   irq_set_default_host(root_domain);
+   }

return 0;




Thanks,

M.

[Patch v5 05/12] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

The powerpc dts file upstream does not have the xlnx,kind-of-intr
property. Instead of erroring out, give a warning instead.
And attempt to continue to probe the interrupt controller while
assuming kind-of-intr is 0x0 as a fall back.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V5 new patch
---
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index dbf8b0c..485fb11 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -197,8 +197,8 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
 
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", >intr_mask);
if (ret < 0) {
-   pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__);
-   goto err_alloc;
+   pr_warn("%s: unable to read xlnx,kind-of-intr\n", __func__);
+   irqc->intr_mask = 0;
}
 
if (irqc->intr_mask >> nr_irq)
-- 
1.9.1

[Patch v5 00/12] microblaze/MIPS/PowerPC: Xilinx intc

[Zubair Lutfullah Kakakhel]

Hi,

The MIPS based Xilfpga platform uses the axi interrupt controller
daisy chained to the MIPS microAptiv cpu interrupt controller.
This patch series moves the axi interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then remove another implementation of the driver in arch/powerpc.
This makes one common driver usable by mips,microblaze and powerpc.
The rest of the series basically enables drivers and adds dt nodes.

Would make sense for this to go via the MIPS tree.
Hence, ACKs from microblaze, powerpc and irqchip welcome.

Compile tested on microblaze-el.
Tested using qemu-system-ppc using virtix440-ml507

Based on v4.9-rc1

Regards,
ZubairLK

V4 -> V5
Added a new patch that removes the PPC driver
Rebase to v4.9-rc1
Better error handling

V3 -> V4
Better error handling
Some minor fixups

V2 -> V3
Cleanup the interrupt controller driver a bit based on feedback
Rebase to v4.8-rc4

V1 -> V2
Resubmitting without truncating the diff output for file moves
Removed accidental local mac address entry
Individual logs have more detail


Zubair Lutfullah Kakakhel (12):
  microblaze: irqchip: Move intc driver to irqchip
  irqchip: xilinx: Clean up irqdomain argument and read/write
  irqchip: xilinx: Rename get_irq to xintc_get_irq
  irqchip: xilinx: Add support for parent intc
  irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided
  powerpc/virtex: Use generic xilinx irqchip driver
  MIPS: xilfpga: Use irqchip instead of the legacy way
  MIPS: xilfpga: Use Xilinx Interrupt Controller
  MIPS: xilfpga: Update DT node and specify uart irq
  MIPS: xilfpga: Add DT node for AXI I2C
  MIPS: xilfpga: Add DT node for AXI emaclite
  MIPS: xilfpga: Update defconfig

 arch/microblaze/Kconfig  |   1 +
 arch/microblaze/include/asm/irq.h|   2 +-
 arch/microblaze/kernel/Makefile  |   2 +-
 arch/microblaze/kernel/intc.c| 196 ---
 arch/microblaze/kernel/irq.c |   4 +-
 arch/mips/Kconfig|   1 +
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts |  63 
 arch/mips/configs/xilfpga_defconfig  |  37 -
 arch/mips/xilfpga/intc.c |   7 +-
 arch/powerpc/include/asm/xilinx_intc.h   |   2 +-
 arch/powerpc/platforms/40x/Kconfig   |   1 +
 arch/powerpc/platforms/40x/virtex.c  |   2 +-
 arch/powerpc/platforms/44x/Kconfig   |   1 +
 arch/powerpc/platforms/44x/virtex.c  |   2 +-
 arch/powerpc/sysdev/xilinx_intc.c| 211 +
 drivers/irqchip/Kconfig  |   4 +
 drivers/irqchip/Makefile |   1 +
 drivers/irqchip/irq-xilinx-intc.c| 258 +++
 18 files changed, 377 insertions(+), 418 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

-- 
1.9.1

[Patch v5 04/12] irqchip: xilinx: Add support for parent intc

[Zubair Lutfullah Kakakhel]

The MIPS based xilfpga platform has the following IRQ structure

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller

Add support for the driver to chain the irq handler

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V4 -> V5
Rebased to v4.9-rc1
Missing curly braces

V3 -> V4
Clean up if/else when a parent is found
Pass irqchip structure to handler as data

V2 -> V3
Reused existing parent node instead of finding again.
Cleanup up handler based on review

V1 -> V2

No change
---
 drivers/irqchip/irq-xilinx-intc.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 45e5154..dbf8b0c 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
@@ -154,11 +155,23 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
.map = xintc_map,
 };
 
+static void xil_intc_irq_handler(struct irq_desc *desc)
+{
+   u32 pending;
+
+   do {
+   pending = xintc_get_irq();
+   if (pending == -1U)
+   break;
+   generic_handle_irq(pending);
+   } while (true);
+}
+
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
u32 nr_irq;
-   int ret;
+   int ret, irq;
struct xintc_irq_chip *irqc;
 
if (xintc_irqc) {
@@ -221,7 +234,16 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
goto err_alloc;
}
 
-   irq_set_default_host(root_domain);
+   if (parent) {
+   irq = irq_of_parse_and_map(intc, 0);
+   if (irq)
+   irq_set_chained_handler_and_data(irq,
+xil_intc_irq_handler,
+irqc);
+
+   } else {
+   irq_set_default_host(root_domain);
+   }
 
return 0;
 
-- 
1.9.1

[Patch v5 05/12] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided

[Zubair Lutfullah Kakakhel]

The powerpc dts file upstream does not have the xlnx,kind-of-intr
property. Instead of erroring out, give a warning instead.
And attempt to continue to probe the interrupt controller while
assuming kind-of-intr is 0x0 as a fall back.

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V5 new patch
---
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index dbf8b0c..485fb11 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -197,8 +197,8 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
 
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", >intr_mask);
if (ret < 0) {
-   pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__);
-   goto err_alloc;
+   pr_warn("%s: unable to read xlnx,kind-of-intr\n", __func__);
+   irqc->intr_mask = 0;
}
 
if (irqc->intr_mask >> nr_irq)
-- 
1.9.1

[Patch v5 00/12] microblaze/MIPS/PowerPC: Xilinx intc

[Zubair Lutfullah Kakakhel]

Hi,

The MIPS based Xilfpga platform uses the axi interrupt controller
daisy chained to the MIPS microAptiv cpu interrupt controller.
This patch series moves the axi interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then remove another implementation of the driver in arch/powerpc.
This makes one common driver usable by mips,microblaze and powerpc.
The rest of the series basically enables drivers and adds dt nodes.

Would make sense for this to go via the MIPS tree.
Hence, ACKs from microblaze, powerpc and irqchip welcome.

Compile tested on microblaze-el.
Tested using qemu-system-ppc using virtix440-ml507

Based on v4.9-rc1

Regards,
ZubairLK

V4 -> V5
Added a new patch that removes the PPC driver
Rebase to v4.9-rc1
Better error handling

V3 -> V4
Better error handling
Some minor fixups

V2 -> V3
Cleanup the interrupt controller driver a bit based on feedback
Rebase to v4.8-rc4

V1 -> V2
Resubmitting without truncating the diff output for file moves
Removed accidental local mac address entry
Individual logs have more detail


Zubair Lutfullah Kakakhel (12):
  microblaze: irqchip: Move intc driver to irqchip
  irqchip: xilinx: Clean up irqdomain argument and read/write
  irqchip: xilinx: Rename get_irq to xintc_get_irq
  irqchip: xilinx: Add support for parent intc
  irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided
  powerpc/virtex: Use generic xilinx irqchip driver
  MIPS: xilfpga: Use irqchip instead of the legacy way
  MIPS: xilfpga: Use Xilinx Interrupt Controller
  MIPS: xilfpga: Update DT node and specify uart irq
  MIPS: xilfpga: Add DT node for AXI I2C
  MIPS: xilfpga: Add DT node for AXI emaclite
  MIPS: xilfpga: Update defconfig

 arch/microblaze/Kconfig  |   1 +
 arch/microblaze/include/asm/irq.h|   2 +-
 arch/microblaze/kernel/Makefile  |   2 +-
 arch/microblaze/kernel/intc.c| 196 ---
 arch/microblaze/kernel/irq.c |   4 +-
 arch/mips/Kconfig|   1 +
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts |  63 
 arch/mips/configs/xilfpga_defconfig  |  37 -
 arch/mips/xilfpga/intc.c |   7 +-
 arch/powerpc/include/asm/xilinx_intc.h   |   2 +-
 arch/powerpc/platforms/40x/Kconfig   |   1 +
 arch/powerpc/platforms/40x/virtex.c  |   2 +-
 arch/powerpc/platforms/44x/Kconfig   |   1 +
 arch/powerpc/platforms/44x/virtex.c  |   2 +-
 arch/powerpc/sysdev/xilinx_intc.c| 211 +
 drivers/irqchip/Kconfig  |   4 +
 drivers/irqchip/Makefile |   1 +
 drivers/irqchip/irq-xilinx-intc.c| 258 +++
 18 files changed, 377 insertions(+), 418 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

-- 
1.9.1

[Patch v5 04/12] irqchip: xilinx: Add support for parent intc

[Zubair Lutfullah Kakakhel]

The MIPS based xilfpga platform has the following IRQ structure

Peripherals --> xilinx_intcontroller -> mips_cpu_int controller

Add support for the driver to chain the irq handler

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V4 -> V5
Rebased to v4.9-rc1
Missing curly braces

V3 -> V4
Clean up if/else when a parent is found
Pass irqchip structure to handler as data

V2 -> V3
Reused existing parent node instead of finding again.
Cleanup up handler based on review

V1 -> V2

No change
---
 drivers/irqchip/irq-xilinx-intc.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 45e5154..dbf8b0c 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
@@ -154,11 +155,23 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
.map = xintc_map,
 };
 
+static void xil_intc_irq_handler(struct irq_desc *desc)
+{
+   u32 pending;
+
+   do {
+   pending = xintc_get_irq();
+   if (pending == -1U)
+   break;
+   generic_handle_irq(pending);
+   } while (true);
+}
+
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
u32 nr_irq;
-   int ret;
+   int ret, irq;
struct xintc_irq_chip *irqc;
 
if (xintc_irqc) {
@@ -221,7 +234,16 @@ static int __init xilinx_intc_of_init(struct device_node 
*intc,
goto err_alloc;
}
 
-   irq_set_default_host(root_domain);
+   if (parent) {
+   irq = irq_of_parse_and_map(intc, 0);
+   if (irq)
+   irq_set_chained_handler_and_data(irq,
+xil_intc_irq_handler,
+irqc);
+
+   } else {
+   irq_set_default_host(root_domain);
+   }
 
return 0;
 
-- 
1.9.1

[Patch v5 11/12] MIPS: xilfpga: Add DT node for AXI emaclite

[Zubair Lutfullah Kakakhel]

The xilfpga platform has a Xilinx AXI emaclite block.

Add the DT node to use it.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V3 -> V4
No change

V2 -> V3
No change

V1 -> V2
Removed accidental local-mac-address entry
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index f5ebab8..09a62f2 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -42,6 +42,32 @@
xlnx,tri-default = <0x>;
} ;
 
+   axi_ethernetlite: ethernet@10e0 {
+   compatible = "xlnx,xps-ethernetlite-3.00.a";
+   device_type = "network";
+   interrupt-parent = <_intc>;
+   interrupts = <1>;
+   phy-handle = <>;
+   reg = <0x10e0 0x1>;
+   xlnx,duplex = <0x1>;
+   xlnx,include-global-buffers = <0x1>;
+   xlnx,include-internal-loopback = <0x0>;
+   xlnx,include-mdio = <0x1>;
+   xlnx,instance = "axi_ethernetlite_inst";
+   xlnx,rx-ping-pong = <0x1>;
+   xlnx,s-axi-id-width = <0x1>;
+   xlnx,tx-ping-pong = <0x1>;
+   xlnx,use-internal = <0x0>;
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   phy0: phy@1 {
+   device_type = "ethernet-phy";
+   reg = <1>;
+   };
+   };
+   };
+
axi_uart16550: serial@1040 {
compatible = "ns16550a";
reg = <0x1040 0x1>;
-- 
1.9.1

[Patch v5 07/12] MIPS: xilfpga: Use irqchip instead of the legacy way

[Zubair Lutfullah Kakakhel]

This prepares the code use the Xilinx Interrupt Controller
driver now available in drivers/irqchip

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
---
V4 -> V5
Better commit message

V3 -> V4
Corrected commit message. Was irq-xilinx.c. Now irq-axi-intc.c

V2 -> V3
No change

V1 -> V2
No change
---
 arch/mips/xilfpga/intc.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/mips/xilfpga/intc.c b/arch/mips/xilfpga/intc.c
index c4d1a71..a127cca 100644
--- a/arch/mips/xilfpga/intc.c
+++ b/arch/mips/xilfpga/intc.c
@@ -11,15 +11,12 @@
 
 #include 
 #include 
+#include 
 
 #include 
 
-static struct of_device_id of_irq_ids[] __initdata = {
-   { .compatible = "mti,cpu-interrupt-controller", .data = 
mips_cpu_irq_of_init },
-   {},
-};
 
 void __init arch_init_irq(void)
 {
-   of_irq_init(of_irq_ids);
+   irqchip_init();
 }
-- 
1.9.1

[Patch v5 12/12] MIPS: xilfpga: Update defconfig

[Zubair Lutfullah Kakakhel]

Update defconfig to enable emaclite, i2c, temp sensor found on the
xilfpga platform

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V3 -> V4
No change

V2 -> V3
No change

V1 -> V2
No change
---
 arch/mips/configs/xilfpga_defconfig | 37 -
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/mips/configs/xilfpga_defconfig 
b/arch/mips/configs/xilfpga_defconfig
index ed1dce3..829c637 100644
--- a/arch/mips/configs/xilfpga_defconfig
+++ b/arch/mips/configs/xilfpga_defconfig
@@ -7,6 +7,12 @@ CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 # CONFIG_BLOCK is not set
 # CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -14,6 +20,30 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
 # CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CORE is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_XILINX_EMACLITE=y
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
@@ -25,13 +55,18 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_XILINX=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_ADT7410=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MIPS_PLATFORM_DEVICES is not set
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_PANIC_ON_OOPS=y
 # CONFIG_SCHED_DEBUG is not set
-- 
1.9.1

[Patch v5 11/12] MIPS: xilfpga: Add DT node for AXI emaclite

[Zubair Lutfullah Kakakhel]

The xilfpga platform has a Xilinx AXI emaclite block.

Add the DT node to use it.

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V3 -> V4
No change

V2 -> V3
No change

V1 -> V2
Removed accidental local-mac-address entry
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index f5ebab8..09a62f2 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -42,6 +42,32 @@
xlnx,tri-default = <0x>;
} ;
 
+   axi_ethernetlite: ethernet@10e0 {
+   compatible = "xlnx,xps-ethernetlite-3.00.a";
+   device_type = "network";
+   interrupt-parent = <_intc>;
+   interrupts = <1>;
+   phy-handle = <>;
+   reg = <0x10e0 0x1>;
+   xlnx,duplex = <0x1>;
+   xlnx,include-global-buffers = <0x1>;
+   xlnx,include-internal-loopback = <0x0>;
+   xlnx,include-mdio = <0x1>;
+   xlnx,instance = "axi_ethernetlite_inst";
+   xlnx,rx-ping-pong = <0x1>;
+   xlnx,s-axi-id-width = <0x1>;
+   xlnx,tx-ping-pong = <0x1>;
+   xlnx,use-internal = <0x0>;
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   phy0: phy@1 {
+   device_type = "ethernet-phy";
+   reg = <1>;
+   };
+   };
+   };
+
axi_uart16550: serial@1040 {
compatible = "ns16550a";
reg = <0x1040 0x1>;
-- 
1.9.1

[Patch v5 07/12] MIPS: xilfpga: Use irqchip instead of the legacy way

[Zubair Lutfullah Kakakhel]

This prepares the code use the Xilinx Interrupt Controller
driver now available in drivers/irqchip

Signed-off-by: Zubair Lutfullah Kakakhel 
---
V4 -> V5
Better commit message

V3 -> V4
Corrected commit message. Was irq-xilinx.c. Now irq-axi-intc.c

V2 -> V3
No change

V1 -> V2
No change
---
 arch/mips/xilfpga/intc.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/mips/xilfpga/intc.c b/arch/mips/xilfpga/intc.c
index c4d1a71..a127cca 100644
--- a/arch/mips/xilfpga/intc.c
+++ b/arch/mips/xilfpga/intc.c
@@ -11,15 +11,12 @@
 
 #include 
 #include 
+#include 
 
 #include 
 
-static struct of_device_id of_irq_ids[] __initdata = {
-   { .compatible = "mti,cpu-interrupt-controller", .data = 
mips_cpu_irq_of_init },
-   {},
-};
 
 void __init arch_init_irq(void)
 {
-   of_irq_init(of_irq_ids);
+   irqchip_init();
 }
-- 
1.9.1

[Patch v5 12/12] MIPS: xilfpga: Update defconfig

[Zubair Lutfullah Kakakhel]

Update defconfig to enable emaclite, i2c, temp sensor found on the
xilfpga platform

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V3 -> V4
No change

V2 -> V3
No change

V1 -> V2
No change
---
 arch/mips/configs/xilfpga_defconfig | 37 -
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/mips/configs/xilfpga_defconfig 
b/arch/mips/configs/xilfpga_defconfig
index ed1dce3..829c637 100644
--- a/arch/mips/configs/xilfpga_defconfig
+++ b/arch/mips/configs/xilfpga_defconfig
@@ -7,6 +7,12 @@ CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 # CONFIG_BLOCK is not set
 # CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -14,6 +20,30 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
 # CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CORE is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_XILINX_EMACLITE=y
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
@@ -25,13 +55,18 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_XILINX=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_ADT7410=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MIPS_PLATFORM_DEVICES is not set
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_PANIC_ON_OOPS=y
 # CONFIG_SCHED_DEBUG is not set
-- 
1.9.1

[Patch v5 10/12] MIPS: xilfpga: Add DT node for AXI I2C

[Zubair Lutfullah Kakakhel]

The xilfpga platform has an AXI I2C Bus master with a temperature
sensor connected to it.

Add the device tree node to use them.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V3 -> V4
changed compatible string from "adt7420" to "adi,adt7420"

V2 -> V3
No change

V1 -> V2

No change
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index d285c8d..f5ebab8 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -54,6 +54,28 @@
interrupt-parent = <_intc>;
interrupts = <0>;
};
+
+   axi_i2c: i2c@10A0 {
+   compatible = "xlnx,xps-iic-2.00.a";
+   interrupt-parent = <_intc>;
+   interrupts = <4>;
+   reg = < 0x10A0 0x1 >;
+   clocks = <>;
+   xlnx,clk-freq = <0x5f5e100>;
+   xlnx,family = "Artix7";
+   xlnx,gpo-width = <0x1>;
+   xlnx,iic-freq = <0x186a0>;
+   xlnx,scl-inertial-delay = <0x0>;
+   xlnx,sda-inertial-delay = <0x0>;
+   xlnx,ten-bit-adr = <0x0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ad7420@4B {
+   compatible = "adi,adt7420";
+   reg = <0x4B>;
+   };
+   } ;
 };
 
  {
-- 
1.9.1

[Patch v5 10/12] MIPS: xilfpga: Add DT node for AXI I2C

[Zubair Lutfullah Kakakhel]

The xilfpga platform has an AXI I2C Bus master with a temperature
sensor connected to it.

Add the device tree node to use them.

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V3 -> V4
changed compatible string from "adt7420" to "adi,adt7420"

V2 -> V3
No change

V1 -> V2

No change
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index d285c8d..f5ebab8 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -54,6 +54,28 @@
interrupt-parent = <_intc>;
interrupts = <0>;
};
+
+   axi_i2c: i2c@10A0 {
+   compatible = "xlnx,xps-iic-2.00.a";
+   interrupt-parent = <_intc>;
+   interrupts = <4>;
+   reg = < 0x10A0 0x1 >;
+   clocks = <>;
+   xlnx,clk-freq = <0x5f5e100>;
+   xlnx,family = "Artix7";
+   xlnx,gpo-width = <0x1>;
+   xlnx,iic-freq = <0x186a0>;
+   xlnx,scl-inertial-delay = <0x0>;
+   xlnx,sda-inertial-delay = <0x0>;
+   xlnx,ten-bit-adr = <0x0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ad7420@4B {
+   compatible = "adi,adt7420";
+   reg = <0x4B>;
+   };
+   } ;
 };
 
  {
-- 
1.9.1

[Patch v5 09/12] MIPS: xilfpga: Update DT node and specify uart irq

[Zubair Lutfullah Kakakhel]

Update the DT node with the UART irq

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V3 -> V4
No change

V2 -> V3
No change

V1 -> V2

No change
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 8db660b..d285c8d 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -50,6 +50,9 @@
reg-offset = <0x1000>;
 
clocks  = <>;
+
+   interrupt-parent = <_intc>;
+   interrupts = <0>;
};
 };
 
-- 
1.9.1

[Patch v5 09/12] MIPS: xilfpga: Update DT node and specify uart irq

[Zubair Lutfullah Kakakhel]

Update the DT node with the UART irq

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V3 -> V4
No change

V2 -> V3
No change

V1 -> V2

No change
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 8db660b..d285c8d 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -50,6 +50,9 @@
reg-offset = <0x1000>;
 
clocks  = <>;
+
+   interrupt-parent = <_intc>;
+   interrupts = <0>;
};
 };
 
-- 
1.9.1

[Patch v5 01/12] microblaze: irqchip: Move intc driver to irqchip

[Zubair Lutfullah Kakakhel]

The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform and a few PowerPC based platforms.

Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V4 -> V5
Rebase to v4.9-rc1
Renamed back to irq-xilinx-intc.c

V3 -> V4
No change

V2 -> V3
No change here. Cleanup patches follow after this patch.
Its debatable to cleanup before/after move. Decided to place cleanup
after move to put history in new place.

V1 -> V2

Renamed irq-xilinx to irq-axi-intc
Renamed CONFIG_XILINX_INTC to CONFIG_XILINX_AXI_INTC
Patch is now without rename flag so as to facilitate review
---
 arch/microblaze/Kconfig   |   1 +
 arch/microblaze/kernel/Makefile   |   2 +-
 arch/microblaze/kernel/intc.c | 196 --
 drivers/irqchip/Kconfig   |   4 +
 drivers/irqchip/Makefile  |   1 +
 drivers/irqchip/irq-xilinx-intc.c | 196 ++
 6 files changed, 203 insertions(+), 197 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 86f6572..85885a5 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -27,6 +27,7 @@ config MICROBLAZE
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_OPROFILE
select IRQ_DOMAIN
+   select XILINX_INTC
select MODULES_USE_ELF_RELA
select OF
select OF_EARLY_FLATTREE
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index f08baca..e098381 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -15,7 +15,7 @@ endif
 extra-y := head.o vmlinux.lds
 
 obj-y += dma.o exceptions.o \
-   hw_exception_handler.o intc.o irq.o \
+   hw_exception_handler.o irq.o \
platform.o process.o prom.o ptrace.o \
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
 
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
deleted file mode 100644
index 90bec7d..000
--- a/arch/microblaze/kernel/intc.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (C) 2007-2013 Michal Simek <mon...@monstr.eu>
- * Copyright (C) 2012-2013 Xilinx, Inc.
- * Copyright (C) 2007-2009 PetaLogix
- * Copyright (C) 2006 Atmark Techno, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-static void __iomem *intc_baseaddr;
-
-/* No one else should require these constants, so define them locally here. */
-#define ISR 0x00   /* Interrupt Status Register */
-#define IPR 0x04   /* Interrupt Pending Register */
-#define IER 0x08   /* Interrupt Enable Register */
-#define IAR 0x0c   /* Interrupt Acknowledge Register */
-#define SIE 0x10   /* Set Interrupt Enable bits */
-#define CIE 0x14   /* Clear Interrupt Enable bits */
-#define IVR 0x18   /* Interrupt Vector Register */
-#define MER 0x1c   /* Master Enable Register */
-
-#define MER_ME (1<<0)
-#define MER_HIE (1<<1)
-
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
-
-static void intc_write32(u32 val, void __iomem *addr)
-{
-   iowrite32(val, addr);
-}
-
-static unsigned int intc_read32(void __iomem *addr)
-{
-   return ioread32(addr);
-}
-
-static void intc_write32_be(u32 val, void __iomem *addr)
-{
-   iowrite32be(val, addr);
-}
-
-static unsigned int intc_read32_be(void __iomem *addr)
-{
-   return ioread32be(addr);
-}
-
-static void intc_enable_or_unmask(struct irq_data *d)
-{
-   unsigned long mask = 1 << d->hwirq;
-
-   pr_debug("enable_or_unmask: %ld\n", d->hwirq);
-
-   /* ack level irqs because they can't be acked during
-* ack function since the handle_level_irq function
-* acks the irq before calling the interrupt handler
-*/
-   if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
-
-   write_fn(mask, intc_baseaddr + SIE);
-}
-
-static void intc_disable_or_mask(struct irq_data *d)
-{
-   pr_debug("disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
-}
-
-static void intc_ack(struct irq_data *d)
-{
-   pr_debug("ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
-}
-
-static void intc_mask_ack(struct irq_data *d)
-{
-   unsigned long mask = 1 << d->hwirq;
-
-   pr_debug(&qu

[Patch v5 01/12] microblaze: irqchip: Move intc driver to irqchip

[Zubair Lutfullah Kakakhel]

The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform and a few PowerPC based platforms.

Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V4 -> V5
Rebase to v4.9-rc1
Renamed back to irq-xilinx-intc.c

V3 -> V4
No change

V2 -> V3
No change here. Cleanup patches follow after this patch.
Its debatable to cleanup before/after move. Decided to place cleanup
after move to put history in new place.

V1 -> V2

Renamed irq-xilinx to irq-axi-intc
Renamed CONFIG_XILINX_INTC to CONFIG_XILINX_AXI_INTC
Patch is now without rename flag so as to facilitate review
---
 arch/microblaze/Kconfig   |   1 +
 arch/microblaze/kernel/Makefile   |   2 +-
 arch/microblaze/kernel/intc.c | 196 --
 drivers/irqchip/Kconfig   |   4 +
 drivers/irqchip/Makefile  |   1 +
 drivers/irqchip/irq-xilinx-intc.c | 196 ++
 6 files changed, 203 insertions(+), 197 deletions(-)
 delete mode 100644 arch/microblaze/kernel/intc.c
 create mode 100644 drivers/irqchip/irq-xilinx-intc.c

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 86f6572..85885a5 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -27,6 +27,7 @@ config MICROBLAZE
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_OPROFILE
select IRQ_DOMAIN
+   select XILINX_INTC
select MODULES_USE_ELF_RELA
select OF
select OF_EARLY_FLATTREE
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index f08baca..e098381 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -15,7 +15,7 @@ endif
 extra-y := head.o vmlinux.lds
 
 obj-y += dma.o exceptions.o \
-   hw_exception_handler.o intc.o irq.o \
+   hw_exception_handler.o irq.o \
platform.o process.o prom.o ptrace.o \
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
 
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
deleted file mode 100644
index 90bec7d..000
--- a/arch/microblaze/kernel/intc.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (C) 2007-2013 Michal Simek 
- * Copyright (C) 2012-2013 Xilinx, Inc.
- * Copyright (C) 2007-2009 PetaLogix
- * Copyright (C) 2006 Atmark Techno, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-static void __iomem *intc_baseaddr;
-
-/* No one else should require these constants, so define them locally here. */
-#define ISR 0x00   /* Interrupt Status Register */
-#define IPR 0x04   /* Interrupt Pending Register */
-#define IER 0x08   /* Interrupt Enable Register */
-#define IAR 0x0c   /* Interrupt Acknowledge Register */
-#define SIE 0x10   /* Set Interrupt Enable bits */
-#define CIE 0x14   /* Clear Interrupt Enable bits */
-#define IVR 0x18   /* Interrupt Vector Register */
-#define MER 0x1c   /* Master Enable Register */
-
-#define MER_ME (1<<0)
-#define MER_HIE (1<<1)
-
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
-
-static void intc_write32(u32 val, void __iomem *addr)
-{
-   iowrite32(val, addr);
-}
-
-static unsigned int intc_read32(void __iomem *addr)
-{
-   return ioread32(addr);
-}
-
-static void intc_write32_be(u32 val, void __iomem *addr)
-{
-   iowrite32be(val, addr);
-}
-
-static unsigned int intc_read32_be(void __iomem *addr)
-{
-   return ioread32be(addr);
-}
-
-static void intc_enable_or_unmask(struct irq_data *d)
-{
-   unsigned long mask = 1 << d->hwirq;
-
-   pr_debug("enable_or_unmask: %ld\n", d->hwirq);
-
-   /* ack level irqs because they can't be acked during
-* ack function since the handle_level_irq function
-* acks the irq before calling the interrupt handler
-*/
-   if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
-
-   write_fn(mask, intc_baseaddr + SIE);
-}
-
-static void intc_disable_or_mask(struct irq_data *d)
-{
-   pr_debug("disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
-}
-
-static void intc_ack(struct irq_data *d)
-{
-   pr_debug("ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
-}
-
-static void intc_mask_ack(struct irq_data *d)
-{
-   unsigned long mask = 1 << d->hwirq;
-
-   pr_debug("disable_and_ack: %ld\n", d->hwirq);
-   write_fn(mask, 

[Patch v5 08/12] MIPS: xilfpga: Use Xilinx Interrupt Controller

[Zubair Lutfullah Kakakhel]

IRQs from peripherals such as i2c/uart/ethernet come via
the AXI Interrupt controller.

Select it in Kconfig for xilfpga and add the DT node

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V4 -> V5
Rebase to v4.9-rc1
Renamed XILINX_AXI_INTC to XILINX_INTC

V3 -> V4
No change

V2 -> V3
No change

V1 -> V2
Renamed select XILINX_INTC to select XILINX_AXI_INTC
---
 arch/mips/Kconfig|  1 +
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 12 
 2 files changed, 13 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3c5bde..3d681c6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -478,6 +478,7 @@ config MACH_XILFPGA
select SYS_SUPPORTS_ZBOOT_UART16550
select USE_OF
select USE_GENERIC_EARLY_PRINTK_8250
+   select XILINX_INTC
help
  This enables support for the IMG University Program MIPSfpga platform.
 
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 48d2112..8db660b 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -17,6 +17,18 @@
compatible = "mti,cpu-interrupt-controller";
};
 
+   axi_intc: interrupt-controller@1020 {
+   #interrupt-cells = <1>;
+   compatible = "xlnx,xps-intc-1.00.a";
+   interrupt-controller;
+   reg = <0x1020 0x1>;
+   xlnx,kind-of-intr = <0x0>;
+   xlnx,num-intr-inputs = <0x6>;
+
+   interrupt-parent = <>;
+   interrupts = <6>;
+   };
+
axi_gpio: gpio@1060 {
#gpio-cells = <1>;
compatible = "xlnx,xps-gpio-1.00.a";
-- 
1.9.1

[Patch v5 06/12] powerpc/virtex: Use generic xilinx irqchip driver

[Zubair Lutfullah Kakakhel]

The Xilinx interrupt controller driver is now available in drivers/irqchip.
Switch to using that driver.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V5 New patch

Tested on virtex440-ml507 using qemu
---
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +
 drivers/irqchip/irq-xilinx-intc.c  |   3 +-
 7 files changed, 9 insertions(+), 213 deletions(-)

diff --git a/arch/powerpc/include/asm/xilinx_intc.h 
b/arch/powerpc/include/asm/xilinx_intc.h
index 343612f..3192d7f 100644
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ b/arch/powerpc/include/asm/xilinx_intc.h
@@ -14,7 +14,7 @@
 #ifdef __KERNEL__
 
 extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xilinx_intc_get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/platforms/40x/Kconfig 
b/arch/powerpc/platforms/40x/Kconfig
index e3257f2..1d7c1b1 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -64,6 +64,7 @@ config XILINX_VIRTEX_GENERIC_BOARD
default n
select XILINX_VIRTEX_II_PRO
select XILINX_VIRTEX_4_FX
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards.
 
diff --git a/arch/powerpc/platforms/40x/virtex.c 
b/arch/powerpc/platforms/40x/virtex.c
index 91a08ea..e3d5e09 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -48,7 +48,7 @@ static int __init virtex_probe(void)
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.restart= ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/Kconfig 
b/arch/powerpc/platforms/44x/Kconfig
index 48fc180..25b8d64 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -241,6 +241,7 @@ config XILINX_VIRTEX440_GENERIC_BOARD
depends on 44x
default n
select XILINX_VIRTEX_5_FXT
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards
  that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
diff --git a/arch/powerpc/platforms/44x/virtex.c 
b/arch/powerpc/platforms/44x/virtex.c
index a7e0802..3eb13ed 100644
--- a/arch/powerpc/platforms/44x/virtex.c
+++ b/arch/powerpc/platforms/44x/virtex.c
@@ -54,7 +54,7 @@ static int __init virtex_probe(void)
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.calibrate_decr = generic_calibrate_decr,
.restart= ppc4xx_reset_system,
 };
diff --git a/arch/powerpc/sysdev/xilinx_intc.c 
b/arch/powerpc/sysdev/xilinx_intc.c
index 0f52d79..4a86dcf 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -29,194 +29,7 @@
 #include 
 #include 
 #include 
-
-/*
- * INTC Registers
- */
-#define XINTC_ISR  0   /* Interrupt Status */
-#define XINTC_IPR  4   /* Interrupt Pending */
-#define XINTC_IER  8   /* Interrupt Enable */
-#define XINTC_IAR  12  /* Interrupt Acknowledge */
-#define XINTC_SIE  16  /* Set Interrupt Enable bits */
-#define XINTC_CIE  20  /* Clear Interrupt Enable bits */
-#define XINTC_IVR  24  /* Interrupt Vector */
-#define XINTC_MER  28  /* Master Enable */
-
-static struct irq_domain *master_irqhost;
-
-#define XILINX_INTC_MAXIRQS(32)
-
-/* The following table allows the interrupt type, edge or level,
- * to be cached after being read from the device tree until the interrupt
- * is mapped
- */
-static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
-
-/* Map the interrupt type from the device tree to the interrupt types
- * used by the interrupt subsystem
- */
-static unsigned char xilinx_intc_map_senses[] = {
-   IRQ_TYPE_EDGE_RISING,
-   IRQ_TYPE_EDGE_FALLING,
-   IRQ_TYPE_LEVEL_HIGH,
-   IRQ_TYPE_LEVEL_LOW,
-};
-
-/*
- * The interrupt controller is setup such that it doesn't work well with
- * the level interrupt handler in the kernel because the handler acks the
- * interrupt before calling the application interrupt handler. To deal with
- * that, we use 2 different irq chips so that dif

[Patch v5 08/12] MIPS: xilfpga: Use Xilinx Interrupt Controller

[Zubair Lutfullah Kakakhel]

IRQs from peripherals such as i2c/uart/ethernet come via
the AXI Interrupt controller.

Select it in Kconfig for xilfpga and add the DT node

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V4 -> V5
Rebase to v4.9-rc1
Renamed XILINX_AXI_INTC to XILINX_INTC

V3 -> V4
No change

V2 -> V3
No change

V1 -> V2
Renamed select XILINX_INTC to select XILINX_AXI_INTC
---
 arch/mips/Kconfig|  1 +
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 12 
 2 files changed, 13 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3c5bde..3d681c6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -478,6 +478,7 @@ config MACH_XILFPGA
select SYS_SUPPORTS_ZBOOT_UART16550
select USE_OF
select USE_GENERIC_EARLY_PRINTK_8250
+   select XILINX_INTC
help
  This enables support for the IMG University Program MIPSfpga platform.
 
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts 
b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 48d2112..8db660b 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -17,6 +17,18 @@
compatible = "mti,cpu-interrupt-controller";
};
 
+   axi_intc: interrupt-controller@1020 {
+   #interrupt-cells = <1>;
+   compatible = "xlnx,xps-intc-1.00.a";
+   interrupt-controller;
+   reg = <0x1020 0x1>;
+   xlnx,kind-of-intr = <0x0>;
+   xlnx,num-intr-inputs = <0x6>;
+
+   interrupt-parent = <>;
+   interrupts = <6>;
+   };
+
axi_gpio: gpio@1060 {
#gpio-cells = <1>;
compatible = "xlnx,xps-gpio-1.00.a";
-- 
1.9.1

[Patch v5 06/12] powerpc/virtex: Use generic xilinx irqchip driver

[Zubair Lutfullah Kakakhel]

The Xilinx interrupt controller driver is now available in drivers/irqchip.
Switch to using that driver.

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V5 New patch

Tested on virtex440-ml507 using qemu
---
 arch/powerpc/include/asm/xilinx_intc.h |   2 +-
 arch/powerpc/platforms/40x/Kconfig |   1 +
 arch/powerpc/platforms/40x/virtex.c|   2 +-
 arch/powerpc/platforms/44x/Kconfig |   1 +
 arch/powerpc/platforms/44x/virtex.c|   2 +-
 arch/powerpc/sysdev/xilinx_intc.c  | 211 +
 drivers/irqchip/irq-xilinx-intc.c  |   3 +-
 7 files changed, 9 insertions(+), 213 deletions(-)

diff --git a/arch/powerpc/include/asm/xilinx_intc.h 
b/arch/powerpc/include/asm/xilinx_intc.h
index 343612f..3192d7f 100644
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ b/arch/powerpc/include/asm/xilinx_intc.h
@@ -14,7 +14,7 @@
 #ifdef __KERNEL__
 
 extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xilinx_intc_get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/platforms/40x/Kconfig 
b/arch/powerpc/platforms/40x/Kconfig
index e3257f2..1d7c1b1 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -64,6 +64,7 @@ config XILINX_VIRTEX_GENERIC_BOARD
default n
select XILINX_VIRTEX_II_PRO
select XILINX_VIRTEX_4_FX
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards.
 
diff --git a/arch/powerpc/platforms/40x/virtex.c 
b/arch/powerpc/platforms/40x/virtex.c
index 91a08ea..e3d5e09 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -48,7 +48,7 @@ static int __init virtex_probe(void)
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.restart= ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/Kconfig 
b/arch/powerpc/platforms/44x/Kconfig
index 48fc180..25b8d64 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -241,6 +241,7 @@ config XILINX_VIRTEX440_GENERIC_BOARD
depends on 44x
default n
select XILINX_VIRTEX_5_FXT
+   select XILINX_INTC
help
  This option enables generic support for Xilinx Virtex based boards
  that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
diff --git a/arch/powerpc/platforms/44x/virtex.c 
b/arch/powerpc/platforms/44x/virtex.c
index a7e0802..3eb13ed 100644
--- a/arch/powerpc/platforms/44x/virtex.c
+++ b/arch/powerpc/platforms/44x/virtex.c
@@ -54,7 +54,7 @@ static int __init virtex_probe(void)
.probe  = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ   = xilinx_intc_init_tree,
-   .get_irq= xilinx_intc_get_irq,
+   .get_irq= xintc_get_irq,
.calibrate_decr = generic_calibrate_decr,
.restart= ppc4xx_reset_system,
 };
diff --git a/arch/powerpc/sysdev/xilinx_intc.c 
b/arch/powerpc/sysdev/xilinx_intc.c
index 0f52d79..4a86dcf 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -29,194 +29,7 @@
 #include 
 #include 
 #include 
-
-/*
- * INTC Registers
- */
-#define XINTC_ISR  0   /* Interrupt Status */
-#define XINTC_IPR  4   /* Interrupt Pending */
-#define XINTC_IER  8   /* Interrupt Enable */
-#define XINTC_IAR  12  /* Interrupt Acknowledge */
-#define XINTC_SIE  16  /* Set Interrupt Enable bits */
-#define XINTC_CIE  20  /* Clear Interrupt Enable bits */
-#define XINTC_IVR  24  /* Interrupt Vector */
-#define XINTC_MER  28  /* Master Enable */
-
-static struct irq_domain *master_irqhost;
-
-#define XILINX_INTC_MAXIRQS(32)
-
-/* The following table allows the interrupt type, edge or level,
- * to be cached after being read from the device tree until the interrupt
- * is mapped
- */
-static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
-
-/* Map the interrupt type from the device tree to the interrupt types
- * used by the interrupt subsystem
- */
-static unsigned char xilinx_intc_map_senses[] = {
-   IRQ_TYPE_EDGE_RISING,
-   IRQ_TYPE_EDGE_FALLING,
-   IRQ_TYPE_LEVEL_HIGH,
-   IRQ_TYPE_LEVEL_LOW,
-};
-
-/*
- * The interrupt controller is setup such that it doesn't work well with
- * the level interrupt handler in the kernel because the handler acks the
- * interrupt before calling the application interrupt handler. To deal with
- * that, we use 2 different irq chips so that different functions can be
- * used

[Patch v5 03/12] irqchip: xilinx: Rename get_irq to xintc_get_irq

[Zubair Lutfullah Kakakhel]

Now that the driver is generic and used by multiple archs,
get_irq is too generic.

Rename get_irq to xintc_get_irq to avoid any conflicts

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V4 -> V5
Rebased to v4.9-rc1
Use __func__ in pr_err

V3 -> V4
New patch.
---
 arch/microblaze/include/asm/irq.h | 2 +-
 arch/microblaze/kernel/irq.c  | 4 ++--
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/microblaze/include/asm/irq.h 
b/arch/microblaze/include/asm/irq.h
index bab3b13..d785def 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -16,6 +16,6 @@
 extern void do_IRQ(struct pt_regs *regs);
 
 /* should be defined in each interrupt controller driver */
-extern unsigned int get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* _ASM_MICROBLAZE_IRQ_H */
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 11e24de..903dad8 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -29,12 +29,12 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
trace_hardirqs_off();
 
irq_enter();
-   irq = get_irq();
+   irq = xintc_get_irq();
 next_irq:
BUG_ON(!irq);
generic_handle_irq(irq);
 
-   irq = get_irq();
+   irq = xintc_get_irq();
if (irq != -1U) {
pr_debug("next irq: %d\n", irq);
++concurrent_irq;
diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index fe533e1..45e5154 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -119,7 +119,7 @@ static void intc_mask_ack(struct irq_data *d)
 
 static struct irq_domain *root_domain;
 
-unsigned int get_irq(void)
+unsigned int xintc_get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
@@ -127,7 +127,7 @@ unsigned int get_irq(void)
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
-   pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
+   pr_debug("%s: hwirq=%d, irq=%d\n", __func__, hwirq, irq);
 
return irq;
 }
-- 
1.9.1

[Patch v5 03/12] irqchip: xilinx: Rename get_irq to xintc_get_irq

[Zubair Lutfullah Kakakhel]

Now that the driver is generic and used by multiple archs,
get_irq is too generic.

Rename get_irq to xintc_get_irq to avoid any conflicts

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V4 -> V5
Rebased to v4.9-rc1
Use __func__ in pr_err

V3 -> V4
New patch.
---
 arch/microblaze/include/asm/irq.h | 2 +-
 arch/microblaze/kernel/irq.c  | 4 ++--
 drivers/irqchip/irq-xilinx-intc.c | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/microblaze/include/asm/irq.h 
b/arch/microblaze/include/asm/irq.h
index bab3b13..d785def 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -16,6 +16,6 @@
 extern void do_IRQ(struct pt_regs *regs);
 
 /* should be defined in each interrupt controller driver */
-extern unsigned int get_irq(void);
+extern unsigned int xintc_get_irq(void);
 
 #endif /* _ASM_MICROBLAZE_IRQ_H */
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 11e24de..903dad8 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -29,12 +29,12 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
trace_hardirqs_off();
 
irq_enter();
-   irq = get_irq();
+   irq = xintc_get_irq();
 next_irq:
BUG_ON(!irq);
generic_handle_irq(irq);
 
-   irq = get_irq();
+   irq = xintc_get_irq();
if (irq != -1U) {
pr_debug("next irq: %d\n", irq);
++concurrent_irq;
diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index fe533e1..45e5154 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -119,7 +119,7 @@ static void intc_mask_ack(struct irq_data *d)
 
 static struct irq_domain *root_domain;
 
-unsigned int get_irq(void)
+unsigned int xintc_get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
@@ -127,7 +127,7 @@ unsigned int get_irq(void)
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
-   pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
+   pr_debug("%s: hwirq=%d, irq=%d\n", __func__, hwirq, irq);
 
return irq;
 }
-- 
1.9.1

[Patch v5 02/12] irqchip: xilinx: Clean up irqdomain argument and read/write

[Zubair Lutfullah Kakakhel]

The drivers read/write function handling is a bit quirky.
And the irqmask is passed directly to the handler.

Add a new irqchip struct to pass to the handler and
cleanup read/write handling.

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V4 -> V5
Rebased to v4.9-rc1
Better error handling

V3 -> V4
Better error handling for kzalloc
Erroring out if the axi intc is probed twice as that isn't
supported

V2 -> V3
New patch. Cleans up driver structure
---
 drivers/irqchip/irq-xilinx-intc.c | 105 ++
 1 file changed, 72 insertions(+), 33 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 90bec7d..fe533e1 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -16,8 +16,6 @@
 #include 
 #include 
 
-static void __iomem *intc_baseaddr;
-
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
 #define IPR 0x04   /* Interrupt Pending Register */
@@ -31,8 +29,16 @@
 #define MER_ME (1<<0)
 #define MER_HIE (1<<1)
 
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+struct xintc_irq_chip {
+   void __iomem *base;
+   struct  irq_domain *domain;
+   struct  irq_chip chip;
+   u32 intr_mask;
+   unsigned int (*read)(void __iomem *iomem);
+   void (*write)(u32 data, void __iomem *iomem);
+};
+
+static struct xintc_irq_chip *xintc_irqc;
 
 static void intc_write32(u32 val, void __iomem *addr)
 {
@@ -54,6 +60,18 @@ static unsigned int intc_read32_be(void __iomem *addr)
return ioread32be(addr);
 }
 
+static inline unsigned int xintc_read(struct xintc_irq_chip *xintc_irqc,
+int reg)
+{
+   return xintc_irqc->read(xintc_irqc->base + reg);
+}
+
+static inline void xintc_write(struct xintc_irq_chip *xintc_irqc,
+int reg, u32 data)
+{
+   xintc_irqc->write(data, xintc_irqc->base + reg);
+}
+
 static void intc_enable_or_unmask(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
@@ -65,21 +83,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
 * acks the irq before calling the interrupt handler
 */
if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, mask);
 
-   write_fn(mask, intc_baseaddr + SIE);
+   xintc_write(xintc_irqc, SIE, mask);
 }
 
 static void intc_disable_or_mask(struct irq_data *d)
 {
pr_debug("disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
+   xintc_write(xintc_irqc, CIE, 1 << d->hwirq);
 }
 
 static void intc_ack(struct irq_data *d)
 {
pr_debug("ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, 1 << d->hwirq);
 }
 
 static void intc_mask_ack(struct irq_data *d)
@@ -87,8 +105,8 @@ static void intc_mask_ack(struct irq_data *d)
unsigned long mask = 1 << d->hwirq;
 
pr_debug("disable_and_ack: %ld\n", d->hwirq);
-   write_fn(mask, intc_baseaddr + CIE);
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, CIE, mask);
+   xintc_write(xintc_irqc, IAR, mask);
 }
 
 static struct irq_chip intc_dev = {
@@ -105,7 +123,7 @@ unsigned int get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
-   hwirq = read_fn(intc_baseaddr + IVR);
+   hwirq = xintc_read(xintc_irqc, IVR);
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
@@ -116,7 +134,8 @@ unsigned int get_irq(void)
 
 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t 
hw)
 {
-   u32 intr_mask = (u32)d->host_data;
+   struct xintc_irq_chip *irqc = d->host_data;
+   u32 intr_mask = irqc->intr_mask;
 
if (intr_mask & (1 << hw)) {
irq_set_chip_and_handler_name(irq, _dev,
@@ -138,59 +157,79 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
-   u32 nr_irq, intr_mask;
+   u32 nr_irq;
int ret;
+   struct xintc_irq_chip *irqc;
+
+   if (xintc_irqc) {
+   pr_err("%s: Multiple instances of xilinx_intc aren't 
supported\n",
+  __func__);
+   return -EINVAL;
+   }
+
+   irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
+   if (!irqc)
+   return -ENOMEM;
 
-   intc_baseaddr = of_iomap(intc, 0);
-   BUG_ON(!intc_baseaddr);
+   

[Patch v5 02/12] irqchip: xilinx: Clean up irqdomain argument and read/write

[Zubair Lutfullah Kakakhel]

The drivers read/write function handling is a bit quirky.
And the irqmask is passed directly to the handler.

Add a new irqchip struct to pass to the handler and
cleanup read/write handling.

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V4 -> V5
Rebased to v4.9-rc1
Better error handling

V3 -> V4
Better error handling for kzalloc
Erroring out if the axi intc is probed twice as that isn't
supported

V2 -> V3
New patch. Cleans up driver structure
---
 drivers/irqchip/irq-xilinx-intc.c | 105 ++
 1 file changed, 72 insertions(+), 33 deletions(-)

diff --git a/drivers/irqchip/irq-xilinx-intc.c 
b/drivers/irqchip/irq-xilinx-intc.c
index 90bec7d..fe533e1 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -16,8 +16,6 @@
 #include 
 #include 
 
-static void __iomem *intc_baseaddr;
-
 /* No one else should require these constants, so define them locally here. */
 #define ISR 0x00   /* Interrupt Status Register */
 #define IPR 0x04   /* Interrupt Pending Register */
@@ -31,8 +29,16 @@
 #define MER_ME (1<<0)
 #define MER_HIE (1<<1)
 
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+struct xintc_irq_chip {
+   void __iomem *base;
+   struct  irq_domain *domain;
+   struct  irq_chip chip;
+   u32 intr_mask;
+   unsigned int (*read)(void __iomem *iomem);
+   void (*write)(u32 data, void __iomem *iomem);
+};
+
+static struct xintc_irq_chip *xintc_irqc;
 
 static void intc_write32(u32 val, void __iomem *addr)
 {
@@ -54,6 +60,18 @@ static unsigned int intc_read32_be(void __iomem *addr)
return ioread32be(addr);
 }
 
+static inline unsigned int xintc_read(struct xintc_irq_chip *xintc_irqc,
+int reg)
+{
+   return xintc_irqc->read(xintc_irqc->base + reg);
+}
+
+static inline void xintc_write(struct xintc_irq_chip *xintc_irqc,
+int reg, u32 data)
+{
+   xintc_irqc->write(data, xintc_irqc->base + reg);
+}
+
 static void intc_enable_or_unmask(struct irq_data *d)
 {
unsigned long mask = 1 << d->hwirq;
@@ -65,21 +83,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
 * acks the irq before calling the interrupt handler
 */
if (irqd_is_level_type(d))
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, mask);
 
-   write_fn(mask, intc_baseaddr + SIE);
+   xintc_write(xintc_irqc, SIE, mask);
 }
 
 static void intc_disable_or_mask(struct irq_data *d)
 {
pr_debug("disable: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + CIE);
+   xintc_write(xintc_irqc, CIE, 1 << d->hwirq);
 }
 
 static void intc_ack(struct irq_data *d)
 {
pr_debug("ack: %ld\n", d->hwirq);
-   write_fn(1 << d->hwirq, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, IAR, 1 << d->hwirq);
 }
 
 static void intc_mask_ack(struct irq_data *d)
@@ -87,8 +105,8 @@ static void intc_mask_ack(struct irq_data *d)
unsigned long mask = 1 << d->hwirq;
 
pr_debug("disable_and_ack: %ld\n", d->hwirq);
-   write_fn(mask, intc_baseaddr + CIE);
-   write_fn(mask, intc_baseaddr + IAR);
+   xintc_write(xintc_irqc, CIE, mask);
+   xintc_write(xintc_irqc, IAR, mask);
 }
 
 static struct irq_chip intc_dev = {
@@ -105,7 +123,7 @@ unsigned int get_irq(void)
 {
unsigned int hwirq, irq = -1;
 
-   hwirq = read_fn(intc_baseaddr + IVR);
+   hwirq = xintc_read(xintc_irqc, IVR);
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
 
@@ -116,7 +134,8 @@ unsigned int get_irq(void)
 
 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t 
hw)
 {
-   u32 intr_mask = (u32)d->host_data;
+   struct xintc_irq_chip *irqc = d->host_data;
+   u32 intr_mask = irqc->intr_mask;
 
if (intr_mask & (1 << hw)) {
irq_set_chip_and_handler_name(irq, _dev,
@@ -138,59 +157,79 @@ static int xintc_map(struct irq_domain *d, unsigned int 
irq, irq_hw_number_t hw)
 static int __init xilinx_intc_of_init(struct device_node *intc,
 struct device_node *parent)
 {
-   u32 nr_irq, intr_mask;
+   u32 nr_irq;
int ret;
+   struct xintc_irq_chip *irqc;
+
+   if (xintc_irqc) {
+   pr_err("%s: Multiple instances of xilinx_intc aren't 
supported\n",
+  __func__);
+   return -EINVAL;
+   }
+
+   irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
+   if (!irqc)
+   return -ENOMEM;
 
-   intc_baseaddr = of_iomap(intc, 0);
-   BUG_ON(!intc_baseaddr);
+   xintc_irqc = irqc;
+
+  

Re: [Patch v6] net: ethernet: xilinx: Enable emaclite for MIPS

[Zubair Lutfullah Kakakhel]

Hi,

On 09/08/2016 12:07 AM, David Miller wrote:

From: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
Date: Mon, 5 Sep 2016 13:07:54 +0100


The MIPS based xilfpga platform uses this driver.
Enable it for MIPS

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V1 -> V6 are from a series that has gotten too big.
So I have split this patch and am sending it separately.


What tree to you expect this patch to be applied to?



net-next

Apologies for not mentioning.
When I sent it, I had rebased it on the top commit at the time.

https://git.kernel.org/cgit/linux/kernel/git/davem/net-next.git/commit/?id=2f5281ba2a8feaf6f0aee93356f350855bb530fc

Kind Regards,
ZubairLK

Re: [Patch v6] net: ethernet: xilinx: Enable emaclite for MIPS

[Zubair Lutfullah Kakakhel]

Hi,

On 09/08/2016 12:07 AM, David Miller wrote:

From: Zubair Lutfullah Kakakhel 
Date: Mon, 5 Sep 2016 13:07:54 +0100


The MIPS based xilfpga platform uses this driver.
Enable it for MIPS

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V1 -> V6 are from a series that has gotten too big.
So I have split this patch and am sending it separately.


What tree to you expect this patch to be applied to?



net-next

Apologies for not mentioning.
When I sent it, I had rebased it on the top commit at the time.

https://git.kernel.org/cgit/linux/kernel/git/davem/net-next.git/commit/?id=2f5281ba2a8feaf6f0aee93356f350855bb530fc

Kind Regards,
ZubairLK

[Patch v6] net: ethernet: xilinx: Enable emaclite for MIPS

[Zubair Lutfullah Kakakhel]

The MIPS based xilfpga platform uses this driver.
Enable it for MIPS

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V1 -> V6 are from a series that has gotten too big.
So I have split this patch and am sending it separately.
---
 drivers/net/ethernet/xilinx/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/Kconfig 
b/drivers/net/ethernet/xilinx/Kconfig
index 4f5c024..6d68c8a 100644
--- a/drivers/net/ethernet/xilinx/Kconfig
+++ b/drivers/net/ethernet/xilinx/Kconfig
@@ -5,7 +5,7 @@
 config NET_VENDOR_XILINX
bool "Xilinx devices"
default y
-   depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ
+   depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS
---help---
  If you have a network (Ethernet) card belonging to this class, say Y.
 
@@ -18,7 +18,7 @@ if NET_VENDOR_XILINX
 
 config XILINX_EMACLITE
tristate "Xilinx 10/100 Ethernet Lite support"
-   depends on (PPC32 || MICROBLAZE || ARCH_ZYNQ)
+   depends on PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS
select PHYLIB
---help---
  This driver supports the 10/100 Ethernet Lite from Xilinx.
-- 
1.9.1

[Patch v6] net: ethernet: xilinx: Enable emaclite for MIPS

[Zubair Lutfullah Kakakhel]

The MIPS based xilfpga platform uses this driver.
Enable it for MIPS

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V1 -> V6 are from a series that has gotten too big.
So I have split this patch and am sending it separately.
---
 drivers/net/ethernet/xilinx/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/Kconfig 
b/drivers/net/ethernet/xilinx/Kconfig
index 4f5c024..6d68c8a 100644
--- a/drivers/net/ethernet/xilinx/Kconfig
+++ b/drivers/net/ethernet/xilinx/Kconfig
@@ -5,7 +5,7 @@
 config NET_VENDOR_XILINX
bool "Xilinx devices"
default y
-   depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ
+   depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS
---help---
  If you have a network (Ethernet) card belonging to this class, say Y.
 
@@ -18,7 +18,7 @@ if NET_VENDOR_XILINX
 
 config XILINX_EMACLITE
tristate "Xilinx 10/100 Ethernet Lite support"
-   depends on (PPC32 || MICROBLAZE || ARCH_ZYNQ)
+   depends on PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS
select PHYLIB
---help---
  This driver supports the 10/100 Ethernet Lite from Xilinx.
-- 
1.9.1

Re: [Patch v5 0/2] net: ethernet: xilinx: mac addr and mips

[Zubair Lutfullah Kakakhel]

On 09/04/2016 07:45 PM, David Miller wrote:

From: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>
Date: Fri, 2 Sep 2016 12:39:24 +0100


A couple of simple patches to generate the random mac address
if none is found. And enabling the driver for mips.

Based on v4.8-rc4.

These were part of a larger series but that series is growing
wildly. Splitting and submitting the net subsystem patches separately.
Hence the v5.


This doesn't apply cleanly to any of my trees.



:)

Looks like there is an identical patch by someone else already in net-next.

https://git.kernel.org/cgit/linux/kernel/git/davem/net.git/commit/drivers/net/ethernet/xilinx/xilinx_emaclite.c?id=5575cf133cf7f564da991595c6bc9344afa7d89a

Regards,
ZubairLK

Re: [Patch v5 0/2] net: ethernet: xilinx: mac addr and mips

[Zubair Lutfullah Kakakhel]

On 09/04/2016 07:45 PM, David Miller wrote:

From: Zubair Lutfullah Kakakhel 
Date: Fri, 2 Sep 2016 12:39:24 +0100


A couple of simple patches to generate the random mac address
if none is found. And enabling the driver for mips.

Based on v4.8-rc4.

These were part of a larger series but that series is growing
wildly. Splitting and submitting the net subsystem patches separately.
Hence the v5.


This doesn't apply cleanly to any of my trees.



:)

Looks like there is an identical patch by someone else already in net-next.

https://git.kernel.org/cgit/linux/kernel/git/davem/net.git/commit/drivers/net/ethernet/xilinx/xilinx_emaclite.c?id=5575cf133cf7f564da991595c6bc9344afa7d89a

Regards,
ZubairLK

Re: [Patch v4 01/12] microblaze: irqchip: Move intc driver to irqchip

[Zubair Lutfullah Kakakhel]

Hi,

Thanks for the valuable feedback.
Comments inline


On 09/02/2016 11:27 AM, Michal Simek wrote:

On 2.9.2016 12:06, Zubair Lutfullah Kakakhel wrote:

Hi,

On 09/02/2016 07:25 AM, Michal Simek wrote:

On 1.9.2016 18:50, Zubair Lutfullah Kakakhel wrote:

The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform.

Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone

Signed-off-by: Zubair Lutfullah Kakakhel <zubair.kakak...@imgtec.com>

---
V3 -> V4
No change

V2 -> V3
No change here. Cleanup patches follow after this patch.
Its debatable to cleanup before/after move. Decided to place cleanup
after move to put history in new place.

V1 -> V2

Renamed irq-xilinx to irq-axi-intc
Renamed CONFIG_XILINX_INTC to CONFIG_XILINX_AXI_INTC



I see that this was suggested by Jason Cooper but using axi name here is
not correct.
There is xps-intc name which is the name used on old OPB hardware
designs. It means this driver can be still used only on system which
uses it.


Wouldn't axi-intc be more suitable moving forwards?
The IP block is now known as axi intc for 5 years as far as I can tell.

Searching "axi intc" online results in the right docs for current and
future platforms.


yes but we still should support older platform and it is more then this.
This is soft-IP core and in future when there is new bus then IP will
just change bus interface, etc.


That makes sense. I'll rename the driver to irq-xps-intc.c
and CONFIG_XILINX_XPS_INTC

Please shout now if anybody has issues with this.

Regards,
ZubairLK

Re: [Patch v4 01/12] microblaze: irqchip: Move intc driver to irqchip

[Zubair Lutfullah Kakakhel]

Hi,

Thanks for the valuable feedback.
Comments inline


On 09/02/2016 11:27 AM, Michal Simek wrote:

On 2.9.2016 12:06, Zubair Lutfullah Kakakhel wrote:

Hi,

On 09/02/2016 07:25 AM, Michal Simek wrote:

On 1.9.2016 18:50, Zubair Lutfullah Kakakhel wrote:

The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform.

Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone

Signed-off-by: Zubair Lutfullah Kakakhel 

---
V3 -> V4
No change

V2 -> V3
No change here. Cleanup patches follow after this patch.
Its debatable to cleanup before/after move. Decided to place cleanup
after move to put history in new place.

V1 -> V2

Renamed irq-xilinx to irq-axi-intc
Renamed CONFIG_XILINX_INTC to CONFIG_XILINX_AXI_INTC



I see that this was suggested by Jason Cooper but using axi name here is
not correct.
There is xps-intc name which is the name used on old OPB hardware
designs. It means this driver can be still used only on system which
uses it.


Wouldn't axi-intc be more suitable moving forwards?
The IP block is now known as axi intc for 5 years as far as I can tell.

Searching "axi intc" online results in the right docs for current and
future platforms.


yes but we still should support older platform and it is more then this.
This is soft-IP core and in future when there is new bus then IP will
just change bus interface, etc.


That makes sense. I'll rename the driver to irq-xps-intc.c
and CONFIG_XILINX_XPS_INTC

Please shout now if anybody has issues with this.

Regards,
ZubairLK