Re: [PATCH v3 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[sricharan]

On 2018-03-20 13:04, Stephen Boyd wrote:

Quoting Sricharan R (2018-03-19 20:58:49)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

new file mode 100644
index 000..871ac3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+
+   soc {
+   qpic_bam: dma@7984000 {


Why the labels?



  ok, will remove here and few other places to make it uniform.

Regards,
 Sricharan


___
linux-arm-kernel mailing list
linux-arm-ker...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[sricharan]

Hi Stephen,

On 2018-03-20 13:03, Stephen Boyd wrote:

Quoting Sricharan R (2018-03-19 20:58:47)

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>


That is an odd place for a reviewed-by tag.



  oops, by mistake. will fix.


Adds missing memory, reserved-memory nodes.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 
+++

 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

index e413b21e..ad0fbc9 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,34 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";

+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {


Lowercase hex please.


 ok.

Regards,
 Sricharan

Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[sricharan]

Hi Stephen,

On 2018-03-20 13:03, Stephen Boyd wrote:

Quoting Sricharan R (2018-03-19 20:58:47)

Reviewed-by: Abhishek Sahu 


That is an odd place for a reviewed-by tag.



  oops, by mistake. will fix.


Adds missing memory, reserved-memory nodes.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 
+++

 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

index e413b21e..ad0fbc9 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,34 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";

+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {


Lowercase hex please.


 ok.

Regards,
 Sricharan

[PATCH v3 07/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/Makefile  | 1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8 
 2 files changed, 9 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4f209fb..b71487a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -748,6 +748,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 000..0843523
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 07/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  | 1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8 
 2 files changed, 9 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4f209fb..b71487a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -748,6 +748,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 000..0843523
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[Sricharan R]

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Adds missing memory, reserved-memory nodes.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ad0fbc9 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,34 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
 
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
soc {
rng@22000 {
status = "ok";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Adds missing memory, reserved-memory nodes.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ad0fbc9 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,34 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
 
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
soc {
rng@22000 {
status = "ok";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Add the common parts for the dk04 boards.

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++
 1 file changed, 129 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 000..96ce081
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+   compatible = "qcom,ipq4019";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+
+   nand_pins: nand_pins {
+   mux {
+   pins = "gpio53", "gpio55", "gpio56",
+   "gpio57", "gpio58", "gpio59",
+   "gpio60", "gpio62", "gpio63",
+   "gpio64", "gpio65", "gpio66",
+   "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   blsp_dma: dma@7884000 {
+   status = "ok";
+  

[PATCH v3 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Add the common parts for the dk04 boards.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++
 1 file changed, 129 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 000..96ce081
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+   compatible = "qcom,ipq4019";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+
+   nand_pins: nand_pins {
+   mux {
+   pins = "gpio53", "gpio55", "gpio56",
+   "gpio57", "gpio58", "gpio59",
+   "gpio60", "gpio62", "gpio63",
+   "gpio64", "gpio65", "gpio66",
+   "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   blsp_dma: dma@7884000 {
+   status = "ok";
+   };
+
+   

[PATCH v3 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b71487a..8c93fd0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+   qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 000..e4fddc1
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+
+   soc {
+   pcie0: pci@4000 {
+   status = "ok";
+   perst-gpio = < 38 0x1>;
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   status = "ok";
+   };
+
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = < 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b71487a..8c93fd0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+   qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 000..e4fddc1
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+
+   soc {
+   pcie0: pci@4000 {
+   status = "ok";
+   perst-gpio = < 38 0x1>;
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   status = "ok";
+   };
+
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = < 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 10/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +
 2 files changed, 27 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8c93fd0..0844087 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -750,6 +750,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+   qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 000..c1e909c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+
+   soc {
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 10/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +
 2 files changed, 27 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8c93fd0..0844087 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -750,6 +750,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+   qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 000..c1e909c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+
+   soc {
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++
 1 file changed, 103 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..8efc8f9e 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
 
aliases {
serial0 = _uart5;
+   serial1 = _blsp2;
};
 
chosen {
@@ -41,6 +42,47 @@
bias-disable;
};
};
+
+i2c_0_pins: i2c_0_pinmux {
+ mux {
+  pins = "gpio42", "gpio43";
+  function = "blsp1_i2c";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+spi_0_pins: spi_0_pins {
+ mux {
+  pins = "gpio38", "gpio39", "gpio40", 
"gpio41";
+  function = "blsp0_spi";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+hsuart_pins: hsuart_pins {
+ mux {
+  pins = "gpio46", "gpio47", "gpio48", 
"gpio49";
+  function = "blsp2_uart";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+qpic_pins: qpic_pins {
+   mux {
+  pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+  function = "qpic";
+  drive-strength = <8>;
+  bias-disable;
+ };
+   };
+
};
 
serial@78b3000 {
@@ -48,5 +90,66 @@
pinctrl-names = "default";
status = "ok";
};
+
+   spi@78b5000 {
+pinctrl-0 = <_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+
+m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+};
+   };
+
+   serial@78b1000 {
+pinctrl-0 = <_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   i2c_0@78b6000 {
+pinctrl-0 = <_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   dma@7984000 {
+status = "ok";
+   };
+
+   nand@79b {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+
+   nand@0 {
+   reg = <0>;
+   nand-ecc-strength = <4>;
+   nand-ecc-step-size = <512>;
+   nand-bus-width = <8>;
+   };
+   };
+
+   phy@86000 {
+ 

[PATCH v3 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++
 1 file changed, 103 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..8efc8f9e 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
 
aliases {
serial0 = _uart5;
+   serial1 = _blsp2;
};
 
chosen {
@@ -41,6 +42,47 @@
bias-disable;
};
};
+
+i2c_0_pins: i2c_0_pinmux {
+ mux {
+  pins = "gpio42", "gpio43";
+  function = "blsp1_i2c";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+spi_0_pins: spi_0_pins {
+ mux {
+  pins = "gpio38", "gpio39", "gpio40", 
"gpio41";
+  function = "blsp0_spi";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+hsuart_pins: hsuart_pins {
+ mux {
+  pins = "gpio46", "gpio47", "gpio48", 
"gpio49";
+  function = "blsp2_uart";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+qpic_pins: qpic_pins {
+   mux {
+  pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+  function = "qpic";
+  drive-strength = <8>;
+  bias-disable;
+ };
+   };
+
};
 
serial@78b3000 {
@@ -48,5 +90,66 @@
pinctrl-names = "default";
status = "ok";
};
+
+   spi@78b5000 {
+pinctrl-0 = <_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+
+m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+};
+   };
+
+   serial@78b1000 {
+pinctrl-0 = <_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   i2c_0@78b6000 {
+pinctrl-0 = <_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   dma@7984000 {
+status = "ok";
+   };
+
+   nand@79b {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+
+   nand@0 {
+   reg = <0>;
+   nand-ecc-strength = <4>;
+   nand-ecc-step-size = <512>;
+   nand-bus-width = <8>;
+   };
+   };
+
+   phy@86000 {
+   status = "ok";
+   };
+
+   phy@8e000 {
+   status = "ok";
+   };
+
+   pci@2000 {
+   status = "ok";
+   perst-gpio = < 58 0x1>;
+   };
+
+   pci@1000 {
+   status = "ok";
+   perst-gpio = < 61 0x1>;
+   };
};
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 12/13] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
 1 file changed, 156 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index a8dbbf0..caf3485 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
 
-   pinctrl@100 {
+   tlmm: pinctrl@100 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x100 0x30>;
interrupts = ;
@@ -229,6 +229,161 @@
dma-names = "tx", "rx", "cmd";
status = "disabled";
};
+
+   pcie_phy0: phy@86000 {
+   compatible = "qcom,ipq8074-qmp-pcie-phy";
+   reg = <0x86000 0x1000>;
+   #phy-cells = <0>;
+   clocks = < GCC_PCIE0_PIPE_CLK>;
+   clock-names = "pipe_clk";
+   clock-output-names = "pcie20_phy0_pipe_clk";
+
+   resets = < GCC_PCIE0_PHY_BCR>,
+   < GCC_PCIE0PHY_PHY_BCR>;
+   reset-names = "phy",
+ "common";
+   status = "disabled";
+   };
+
+   pcie0: pci@2000 {
+   compatible = "qcom,pcie-ipq8074";
+   reg =  <0x2000 0xf1d
+   0x2f20 0xa8
+   0x8 0x2000
+   0x2010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   phys = <_phy0>;
+   phy-names = "pciephy";
+
+   ranges = <0x8100 0 0x2020 0x2020
+ 0 0x10   /* downstream I/O */
+ 0x8200 0 0x2030 0x2030
+ 0 0xd0>; /* non-prefetchable memory */
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 75
+IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 78
+IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3  0 79
+IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4  0 83
+IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+   clocks = < GCC_SYS_NOC_PCIE0_AXI_CLK>,
+< GCC_PCIE0_AXI_M_CLK>,
+< GCC_PCIE0_AXI_S_CLK>,
+< GCC_PCIE0_AHB_CLK>,
+< GCC_PCIE0_AUX_CLK>;
+
+   clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+   resets = < GCC_PCIE0_PIPE_ARES>,
+< GCC_PCIE0_SLEEP_ARES>,
+< GCC_PCIE0_CORE_STICKY_ARES>,
+< GCC_PCIE0_AXI_MASTER_ARES>,
+< GCC_PCIE0_AXI_SLAVE_ARES>,
+< GCC_PCIE0_AHB_ARES>,
+< GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+   reset-names = "pipe",
+ "sleep",
+ "sticky",
+

[PATCH v3 12/13] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
 1 file changed, 156 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index a8dbbf0..caf3485 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
 
-   pinctrl@100 {
+   tlmm: pinctrl@100 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x100 0x30>;
interrupts = ;
@@ -229,6 +229,161 @@
dma-names = "tx", "rx", "cmd";
status = "disabled";
};
+
+   pcie_phy0: phy@86000 {
+   compatible = "qcom,ipq8074-qmp-pcie-phy";
+   reg = <0x86000 0x1000>;
+   #phy-cells = <0>;
+   clocks = < GCC_PCIE0_PIPE_CLK>;
+   clock-names = "pipe_clk";
+   clock-output-names = "pcie20_phy0_pipe_clk";
+
+   resets = < GCC_PCIE0_PHY_BCR>,
+   < GCC_PCIE0PHY_PHY_BCR>;
+   reset-names = "phy",
+ "common";
+   status = "disabled";
+   };
+
+   pcie0: pci@2000 {
+   compatible = "qcom,pcie-ipq8074";
+   reg =  <0x2000 0xf1d
+   0x2f20 0xa8
+   0x8 0x2000
+   0x2010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   phys = <_phy0>;
+   phy-names = "pciephy";
+
+   ranges = <0x8100 0 0x2020 0x2020
+ 0 0x10   /* downstream I/O */
+ 0x8200 0 0x2030 0x2030
+ 0 0xd0>; /* non-prefetchable memory */
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 75
+IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 78
+IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3  0 79
+IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4  0 83
+IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+   clocks = < GCC_SYS_NOC_PCIE0_AXI_CLK>,
+< GCC_PCIE0_AXI_M_CLK>,
+< GCC_PCIE0_AXI_S_CLK>,
+< GCC_PCIE0_AHB_CLK>,
+< GCC_PCIE0_AUX_CLK>;
+
+   clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+   resets = < GCC_PCIE0_PIPE_ARES>,
+< GCC_PCIE0_SLEEP_ARES>,
+< GCC_PCIE0_CORE_STICKY_ARES>,
+< GCC_PCIE0_AXI_MASTER_ARES>,
+< GCC_PCIE0_AXI_SLAVE_ARES>,
+< GCC_PCIE0_AHB_ARES>,
+< GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+   reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ 

[PATCH v3 08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Add the common data for all dk07 based boards.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++
 1 file changed, 83 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 000..37a2ea8
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+   compatible = "qcom,ipq4019";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x2000>; /* 512MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   blsp_dma: dma@7884000 {
+   status = "ok";
+   };
+
+   i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   qpic_bam: dma@7984000 {
+   status = "ok";
+   };
+
+   nand: qpic-nand@79b {
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Add the common data for all dk07 based boards.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++
 1 file changed, 83 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 000..37a2ea8
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+   compatible = "qcom,ipq4019";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x2000>; /* 512MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   blsp_dma: dma@7884000 {
+   status = "ok";
+   };
+
+   i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   qpic_bam: dma@7984000 {
+   status = "ok";
+   };
+
+   nand: qpic-nand@79b {
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 11/13] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

Add serial, i2c, bam, spi, qpic peripheral nodes.

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..a8dbbf0 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -124,6 +124,111 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7884000 0x2b000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   };
+
+   serial_blsp0: serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+< GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   status = "disabled";
+   };
+
+   serial_blsp2: serial@78b1000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b1000 0x200>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART3_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <_dma 4>,
+   <_dma 5>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   spi_0: spi@78b5000 {
+   compatible = "qcom,spi-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b5000 0x600>;
+   interrupts = ;
+   spi-max-frequency = <5000>;
+   clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <_dma 12>, <_dma 13>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   i2c_0: i2c@78b6000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+   < GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency = <40>;
+   dmas = <_dma 15>, <_dma 14>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   i2c_1: i2c@78b7000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b7000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+   < GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency = <10>;
+   dmas = <_dma 17>, <_dma 16>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   qpic_bam: dma@7984000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7984000 0x1a000>;
+   interrupts = ;
+   clocks = < GCC_QPIC_AHB_CLK>;
+   clock-names = "bam_clk";
+  

[PATCH v3 11/13] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

Add serial, i2c, bam, spi, qpic peripheral nodes.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..a8dbbf0 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -124,6 +124,111 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7884000 0x2b000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   };
+
+   serial_blsp0: serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+< GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   status = "disabled";
+   };
+
+   serial_blsp2: serial@78b1000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b1000 0x200>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART3_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <_dma 4>,
+   <_dma 5>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   spi_0: spi@78b5000 {
+   compatible = "qcom,spi-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b5000 0x600>;
+   interrupts = ;
+   spi-max-frequency = <5000>;
+   clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <_dma 12>, <_dma 13>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   i2c_0: i2c@78b6000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+   < GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency = <40>;
+   dmas = <_dma 15>, <_dma 14>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   i2c_1: i2c@78b7000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b7000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+   < GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency = <10>;
+   dmas = <_dma 17>, <_dma 16>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   qpic_bam: dma@7984000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7984000 0x1a000>;
+   interrupts = ;
+   clocks = < GCC_QPIC_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+

[PATCH v3 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20 
 2 files changed, 21 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b59e99b..4f209fb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -747,6 +747,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 000..871ac3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+
+   soc {
+   qpic_bam: dma@7984000 {
+   status = "ok";
+   };
+
+   nand: qpic-nand@79b {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20 
 2 files changed, 21 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b59e99b..4f209fb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -747,6 +747,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 000..871ac3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+
+   soc {
+   qpic_bam: dma@7984000 {
+   status = "ok";
+   };
+
+   nand: qpic-nand@79b {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 01/13] firmware: qcom: scm: Add ipq4019 soc compatible

[Sricharan R]

Add the compatible for ipq4019.
This does not need clocks to do scm calls.

Reviewed-by: Rob Herring <r...@kernel.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
 drivers/firmware/qcom_scm.c | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt 
b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 7b40054..fcf6979 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -11,9 +11,10 @@ Required properties:
  * "qcom,scm-msm8660" for MSM8660 platforms
  * "qcom,scm-msm8690" for MSM8690 platforms
  * "qcom,scm-msm8996" for MSM8996 platforms
+ * "qcom,scm-ipq4019" for IPQ4019 platforms
  * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
 - clocks: One to three clocks may be required based on compatible.
- * No clock required for "qcom,scm-msm8996"
+ * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
  * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and 
"qcom,scm-msm8960"
  * Core, iface, and bus clocks required for "qcom,scm"
 - clock-names: Must contain "core" for the core clock, "iface" for the 
interface
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 5a7d6930..e778af7 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -603,6 +603,9 @@ static void qcom_scm_shutdown(struct platform_device *pdev)
{ .compatible = "qcom,scm-msm8996",
  .data = NULL, /* no clocks */
},
+   { .compatible = "qcom,scm-ipq4019",
+ .data = NULL, /* no clocks */
+   },
{ .compatible = "qcom,scm",
  .data = (void *)(SCM_HAS_CORE_CLK
   | SCM_HAS_IFACE_CLK
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 01/13] firmware: qcom: scm: Add ipq4019 soc compatible

[Sricharan R]

Add the compatible for ipq4019.
This does not need clocks to do scm calls.

Reviewed-by: Rob Herring 
Signed-off-by: Sricharan R 
---
 Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
 drivers/firmware/qcom_scm.c | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt 
b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 7b40054..fcf6979 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -11,9 +11,10 @@ Required properties:
  * "qcom,scm-msm8660" for MSM8660 platforms
  * "qcom,scm-msm8690" for MSM8690 platforms
  * "qcom,scm-msm8996" for MSM8996 platforms
+ * "qcom,scm-ipq4019" for IPQ4019 platforms
  * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
 - clocks: One to three clocks may be required based on compatible.
- * No clock required for "qcom,scm-msm8996"
+ * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
  * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and 
"qcom,scm-msm8960"
  * Core, iface, and bus clocks required for "qcom,scm"
 - clock-names: Must contain "core" for the core clock, "iface" for the 
interface
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 5a7d6930..e778af7 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -603,6 +603,9 @@ static void qcom_scm_shutdown(struct platform_device *pdev)
{ .compatible = "qcom,scm-msm8996",
  .data = NULL, /* no clocks */
},
+   { .compatible = "qcom,scm-ipq4019",
+ .data = NULL, /* no clocks */
+   },
{ .compatible = "qcom,scm",
  .data = (void *)(SCM_HAS_CORE_CLK
   | SCM_HAS_IFACE_CLK
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals

[Sricharan R]

[v3]
* Fixed minor comments from v2,
  https://www.spinics.net/lists/arm-kernel/msg641480.html

* Added Abhishek's review tags

[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
  as support for spinand is not complete
* Based all patches on top of Andy's for-next branch

[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html

Sricharan R (13):
  firmware: qcom: scm: Add ipq4019 soc compatible
  ARM: dts: ipq4019: Add a few peripheral nodes
  ARM: dts: ipq4019: Change the max opp frequency
  ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
  ARM: dts: ipq8074: Add peripheral nodes
  ARM: dts: ipq8074: Add pcie nodes
  ARM: dts: ipq8074: Enable few peripherals for hk01 board

 .../devicetree/bindings/firmware/qcom,scm.txt  |   3 +-
 arch/arm/boot/dts/Makefile |   4 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi  |  32 ++-
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts|  20 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts|   8 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi  | 135 +++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts|  65 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts|  26 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi  |  83 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi| 136 ++-
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts  | 103 
 arch/arm64/boot/dts/qcom/ipq8074.dtsi  | 262 -
 drivers/firmware/qcom_scm.c|   3 +
 13 files changed, 875 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 02/13] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 
 1 file changed, 134 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..3a7127c 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,7 +25,9 @@
 
aliases {
spi0 = _0;
+   spi1 = _1;
i2c0 = _0;
+   i2c1 = _1;
};
 
cpus {
@@ -104,6 +106,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -172,6 +180,22 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 5>, <_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 7>, <_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
@@ -184,9 +208,24 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 9>, <_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+< GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 11>, <_dma 10>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
 
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
 
+   pcie0: pci@4000 {
+   compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+   reg =  <0x4000 0xf1d
+   0x4f20 0xa8
+   0x8 0x2000
+   0x4010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   ranges = <0x8100 0 0x4020 0x4020 0 
0x0010
+ 0x8200 0 0x4800 0x4800 0 
0x1000>;
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 142 
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 143 
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0

[PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals

[Sricharan R]

[v3]
* Fixed minor comments from v2,
  https://www.spinics.net/lists/arm-kernel/msg641480.html

* Added Abhishek's review tags

[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
  as support for spinand is not complete
* Based all patches on top of Andy's for-next branch

[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html

Sricharan R (13):
  firmware: qcom: scm: Add ipq4019 soc compatible
  ARM: dts: ipq4019: Add a few peripheral nodes
  ARM: dts: ipq4019: Change the max opp frequency
  ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
  ARM: dts: ipq8074: Add peripheral nodes
  ARM: dts: ipq8074: Add pcie nodes
  ARM: dts: ipq8074: Enable few peripherals for hk01 board

 .../devicetree/bindings/firmware/qcom,scm.txt  |   3 +-
 arch/arm/boot/dts/Makefile |   4 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi  |  32 ++-
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts|  20 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts|   8 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi  | 135 +++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts|  65 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts|  26 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi  |  83 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi| 136 ++-
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts  | 103 
 arch/arm64/boot/dts/qcom/ipq8074.dtsi  | 262 -
 drivers/firmware/qcom_scm.c|   3 +
 13 files changed, 875 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 02/13] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 
 1 file changed, 134 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..3a7127c 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,7 +25,9 @@
 
aliases {
spi0 = _0;
+   spi1 = _1;
i2c0 = _0;
+   i2c1 = _1;
};
 
cpus {
@@ -104,6 +106,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -172,6 +180,22 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 5>, <_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 7>, <_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
@@ -184,9 +208,24 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 9>, <_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+< GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 11>, <_dma 10>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
 
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
 
+   pcie0: pci@4000 {
+   compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+   reg =  <0x4000 0xf1d
+   0x4f20 0xa8
+   0x8 0x2000
+   0x4010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   ranges = <0x8100 0 0x4020 0x4020 0 
0x0010
+ 0x8200 0 0x4800 0x4800 0 
0x1000>;
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 142 
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 143 
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3  0 144 
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   

[PATCH v3 03/13] ARM: dts: ipq4019: Change the max opp frequency

[Sricharan R]

The max opp frequency is 716MHZ. So update that.

Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 3a7127c..e87e825 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000   110
20  110
50  110
-   666000  110
+   716000  110
>;
clock-latency = <256000>;
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 03/13] ARM: dts: ipq4019: Change the max opp frequency

[Sricharan R]

The max opp frequency is 716MHZ. So update that.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 3a7127c..e87e825 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000   110
20  110
50  110
-   666000  110
+   716000  110
>;
clock-latency = <256000>;
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

On 3/16/2018 3:55 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> ---
>>  arch/arm/boot/dts/Makefile  |  1 +
>>  arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 
>> +
>>  2 files changed, 66 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index b71487a..8c93fd0 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
>>  qcom-ipq4019-ap.dk01.1-c1.dtb \
>>  qcom-ipq4019-ap.dk04.1-c1.dtb \
>>  qcom-ipq4019-ap.dk04.1-c3.dtb \
>> +    qcom-ipq4019-ap.dk07.1-c1.dtb \
>>  qcom-ipq8064-ap148.dtb \
>>  qcom-msm8660-surf.dtb \
>>  qcom-msm8960-cdp.dtb \
>> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>> new file mode 100644
>> index 000..4562f7f
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>> @@ -0,0 +1,65 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> +
>> +#include "qcom-ipq4019-ap.dk07.1.dtsi"
>> +
>> +/ {
>> +    model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK07.1-C1";
> 
>  s/IPQ40xx/IPQ4019
> 
>  with that.
> 
>  Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
  Thanks, will update

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

On 3/16/2018 3:55 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R 
>> ---
>>  arch/arm/boot/dts/Makefile  |  1 +
>>  arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 
>> +
>>  2 files changed, 66 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index b71487a..8c93fd0 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
>>  qcom-ipq4019-ap.dk01.1-c1.dtb \
>>  qcom-ipq4019-ap.dk04.1-c1.dtb \
>>  qcom-ipq4019-ap.dk04.1-c3.dtb \
>> +    qcom-ipq4019-ap.dk07.1-c1.dtb \
>>  qcom-ipq8064-ap148.dtb \
>>  qcom-msm8660-surf.dtb \
>>  qcom-msm8960-cdp.dtb \
>> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>> new file mode 100644
>> index 000..4562f7f
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>> @@ -0,0 +1,65 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> +
>> +#include "qcom-ipq4019-ap.dk07.1.dtsi"
>> +
>> +/ {
>> +    model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK07.1-C1";
> 
>  s/IPQ40xx/IPQ4019
> 
>  with that.
> 
>  Reviewed-by: Abhishek Sahu 
  Thanks, will update

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 11/13] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

On 3/16/2018 4:17 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Add serial, i2c, bam, spi, qpic peripheral nodes.
>>
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 
>> ++
>>  1 file changed, 105 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 2bc5dec..806fc56 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -124,6 +124,111 @@
>>  clock-names = "core", "iface";
>>  status = "disabled";
>>  };
>> +
>> +    blsp_dma: dma@7884000 {
>> +    compatible = "qcom,bam-v1.7.0";
>> +    reg = <0x07884000 0x2b000>;
> 
>  we can remove leading zero. s/0x07884000/0x7884000
> 
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_AHB_CLK>;
>> +    clock-names = "bam_clk";
>> +    #dma-cells = <1>;
>> +    qcom,ee = <0>;
>> +    };
>> +
>> +    serial_blsp0: serial@78af000 {
>> +    compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +    reg = <0x78af000 0x200>;
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_UART1_APPS_CLK>,
>> + < GCC_BLSP1_AHB_CLK>;
>> +    clock-names = "core", "iface";
>> +    status = "disabled";
>> +    };
>> +
>> +    serial_blsp2: serial@78B1000 {
> 
>  For maintaining uniformity, we can have all address in lower case
>  s/78B1000/78b1000
> 
>> +    compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +    reg = <0x78B1000 0x200>;
> 
>  same thing, here also
> 
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_UART3_APPS_CLK>,
>> +    < GCC_BLSP1_AHB_CLK>;
>> +    clock-names = "core", "iface";
>> +    dmas = <_dma 4>,
>> +    <_dma 5>;
>> +    dma-names = "tx", "rx";
>> +    status = "disabled";
>> +    };
>> +
>> +    spi_0: spi@78b5000 {
>> +    compatible = "qcom,spi-qup-v2.2.1";
>> +    #address-cells = <1>;
>> +    #size-cells = <0>;
>> +    reg = <0x78b5000 0x600>;
>> +    interrupts = ;
>> +    spi-max-frequency = <5000>;
>> +    clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>,
>> +    < GCC_BLSP1_AHB_CLK>;
>> +    clock-names = "core", "iface";
>> +    dmas = <_dma 12>, <_dma 13>;
>> +    dma-names = "tx", "rx";
>> +    status = "disabled";
>> +    };
>> +
>> +    i2c_0: i2c@78b6000 {
>> +    compatible = "qcom,i2c-qup-v2.2.1";
>> +    #address-cells = <1>;
>> +    #size-cells = <0>;
>> +    reg = <0x78b6000 0x600>;
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_AHB_CLK>,
>> +    < GCC_BLSP1_QUP2_I2C_APPS_CLK>;
>> +    clock-names = "iface", "core";
>> +    clock-frequency  = <40>;
> 
>  remove one extra space. clock-frequency = <40>;
> 
>> +    dmas = <_dma 15>, <_dma 14>;
>> +    dma-names = "rx", "tx";
>> +    status = "disabled";
>> +    };
>> +
>> +    i2c_1: i2c@78b7000 {
>> +    compatible = "qcom,i2c-qup-v2.2.1";
>> +    #address-cells = <1>;
>> +    #size-cells = <0>;
>> +    reg = <0x78b7000 0x600>;
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_AHB_CLK>,
>> +    < GCC_BLSP1_QUP3_I2C_APPS_CLK>;
>> +    clock-names = "iface", "core";
>> +    clock-frequency  = <10>;
> 
>  remove one extra space. clock-frequency = <10>;
> 
>  with above changes.
> 
>  Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
> 

 Sure, will take care of all the above. Thanks

Regards,
 Sricharan
-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 11/13] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

On 3/16/2018 4:17 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Add serial, i2c, bam, spi, qpic peripheral nodes.
>>
>> Signed-off-by: Sricharan R 
>> ---
>>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 
>> ++
>>  1 file changed, 105 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 2bc5dec..806fc56 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -124,6 +124,111 @@
>>  clock-names = "core", "iface";
>>  status = "disabled";
>>  };
>> +
>> +    blsp_dma: dma@7884000 {
>> +    compatible = "qcom,bam-v1.7.0";
>> +    reg = <0x07884000 0x2b000>;
> 
>  we can remove leading zero. s/0x07884000/0x7884000
> 
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_AHB_CLK>;
>> +    clock-names = "bam_clk";
>> +    #dma-cells = <1>;
>> +    qcom,ee = <0>;
>> +    };
>> +
>> +    serial_blsp0: serial@78af000 {
>> +    compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +    reg = <0x78af000 0x200>;
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_UART1_APPS_CLK>,
>> + < GCC_BLSP1_AHB_CLK>;
>> +    clock-names = "core", "iface";
>> +    status = "disabled";
>> +    };
>> +
>> +    serial_blsp2: serial@78B1000 {
> 
>  For maintaining uniformity, we can have all address in lower case
>  s/78B1000/78b1000
> 
>> +    compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +    reg = <0x78B1000 0x200>;
> 
>  same thing, here also
> 
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_UART3_APPS_CLK>,
>> +    < GCC_BLSP1_AHB_CLK>;
>> +    clock-names = "core", "iface";
>> +    dmas = <_dma 4>,
>> +    <_dma 5>;
>> +    dma-names = "tx", "rx";
>> +    status = "disabled";
>> +    };
>> +
>> +    spi_0: spi@78b5000 {
>> +    compatible = "qcom,spi-qup-v2.2.1";
>> +    #address-cells = <1>;
>> +    #size-cells = <0>;
>> +    reg = <0x78b5000 0x600>;
>> +    interrupts = ;
>> +    spi-max-frequency = <5000>;
>> +    clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>,
>> +    < GCC_BLSP1_AHB_CLK>;
>> +    clock-names = "core", "iface";
>> +    dmas = <_dma 12>, <_dma 13>;
>> +    dma-names = "tx", "rx";
>> +    status = "disabled";
>> +    };
>> +
>> +    i2c_0: i2c@78b6000 {
>> +    compatible = "qcom,i2c-qup-v2.2.1";
>> +    #address-cells = <1>;
>> +    #size-cells = <0>;
>> +    reg = <0x78b6000 0x600>;
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_AHB_CLK>,
>> +    < GCC_BLSP1_QUP2_I2C_APPS_CLK>;
>> +    clock-names = "iface", "core";
>> +    clock-frequency  = <40>;
> 
>  remove one extra space. clock-frequency = <40>;
> 
>> +    dmas = <_dma 15>, <_dma 14>;
>> +    dma-names = "rx", "tx";
>> +    status = "disabled";
>> +    };
>> +
>> +    i2c_1: i2c@78b7000 {
>> +    compatible = "qcom,i2c-qup-v2.2.1";
>> +    #address-cells = <1>;
>> +    #size-cells = <0>;
>> +    reg = <0x78b7000 0x600>;
>> +    interrupts = ;
>> +    clocks = < GCC_BLSP1_AHB_CLK>,
>> +    < GCC_BLSP1_QUP3_I2C_APPS_CLK>;
>> +    clock-names = "iface", "core";
>> +    clock-frequency  = <10>;
> 
>  remove one extra space. clock-frequency = <10>;
> 
>  with above changes.
> 
>  Reviewed-by: Abhishek Sahu 
> 

 Sure, will take care of all the above. Thanks

Regards,
 Sricharan
-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Hi Abhishek,

On 3/16/2018 4:27 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 
>> ++
>>  1 file changed, 103 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> index 6a838b5..81dff867 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> @@ -21,6 +21,7 @@
>>
>>  aliases {
>>  serial0 = _uart5;
>> +    serial1 = _blsp2;
>>  };
>>
>>  chosen {
>> @@ -41,6 +42,47 @@
>>  bias-disable;
>>  };
>>  };
>> +
>> + i2c_0_pins: i2c_0_pinmux {
>> +  mux {
>> +   pins = "gpio42", "gpio43";
>> +   function = "blsp1_i2c";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> + };
>> +
>> + spi_0_pins: spi_0_pins {
>> +  mux {
>> +   pins = "gpio38", "gpio39", "gpio40", "gpio41";
>> +   function = "blsp0_spi";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> + };
>> +
>> + hsuart_pins: hsuart_pins {
>> +  mux {
>> +   pins = "gpio46", "gpio47", "gpio48", "gpio49";
>> +   function = "blsp2_uart";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> + };
>> +
>> + qpic_pins: qpic_pins {
>> +    mux {
>> +   pins = "gpio1", "gpio3", "gpio4",
>> +  "gpio5", "gpio6", "gpio7",
>> +  "gpio8", "gpio10", "gpio11",
>> +  "gpio12", "gpio13", "gpio14",
>> +  "gpio15", "gpio16", "gpio17";
>> +   function = "qpic";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> +    };
>> +
>>  };
>>
>>  serial@78b3000 {
>> @@ -48,5 +90,66 @@
>>  pinctrl-names = "default";
>>  status = "ok";
>>  };
>> +
>> +    spi@78b5000 {
>> + pinctrl-0 = <_0_pins>;
>> + pinctrl-names = "default";
>> + status = "ok";
>> +
>> + m25p80@0 {
>> +  #address-cells = <1>;
>> +  #size-cells = <1>;
>> +  compatible = "n25q128a11", "jedec,spi-nor";
>> +  reg = <0>;
>> +  spi-max-frequency = <5000>;
>> + };
>> +    };
>> +
>> +    serial@78B1000 {
> 
>  s/78B1000/78b1000
> 
>  With that,
>  Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>
> 

 ok, Thanks.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Hi Abhishek,

On 3/16/2018 4:27 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R 
>> ---
>>  arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 
>> ++
>>  1 file changed, 103 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> index 6a838b5..81dff867 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> @@ -21,6 +21,7 @@
>>
>>  aliases {
>>  serial0 = _uart5;
>> +    serial1 = _blsp2;
>>  };
>>
>>  chosen {
>> @@ -41,6 +42,47 @@
>>  bias-disable;
>>  };
>>  };
>> +
>> + i2c_0_pins: i2c_0_pinmux {
>> +  mux {
>> +   pins = "gpio42", "gpio43";
>> +   function = "blsp1_i2c";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> + };
>> +
>> + spi_0_pins: spi_0_pins {
>> +  mux {
>> +   pins = "gpio38", "gpio39", "gpio40", "gpio41";
>> +   function = "blsp0_spi";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> + };
>> +
>> + hsuart_pins: hsuart_pins {
>> +  mux {
>> +   pins = "gpio46", "gpio47", "gpio48", "gpio49";
>> +   function = "blsp2_uart";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> + };
>> +
>> + qpic_pins: qpic_pins {
>> +    mux {
>> +   pins = "gpio1", "gpio3", "gpio4",
>> +  "gpio5", "gpio6", "gpio7",
>> +  "gpio8", "gpio10", "gpio11",
>> +  "gpio12", "gpio13", "gpio14",
>> +  "gpio15", "gpio16", "gpio17";
>> +   function = "qpic";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> +    };
>> +
>>  };
>>
>>      serial@78b3000 {
>> @@ -48,5 +90,66 @@
>>  pinctrl-names = "default";
>>  status = "ok";
>>  };
>> +
>> +    spi@78b5000 {
>> + pinctrl-0 = <_0_pins>;
>> + pinctrl-names = "default";
>> + status = "ok";
>> +
>> + m25p80@0 {
>> +  #address-cells = <1>;
>> +  #size-cells = <1>;
>> +  compatible = "n25q128a11", "jedec,spi-nor";
>> +  reg = <0>;
>> +  spi-max-frequency = <5000>;
>> + };
>> +    };
>> +
>> +    serial@78B1000 {
> 
>  s/78B1000/78b1000
> 
>  With that,
>  Reviewed-by: Abhishek Sahu 
> 

 ok, Thanks.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 12/13] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

Hi Abhishek,

On 3/16/2018 4:50 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> The driver/phy support for ipq8074 is available now.
>> So enabling the nodes in DT.
>>
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 
>> +-
>>  1 file changed, 156 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 806fc56..7562650 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -24,7 +24,7 @@
>>  ranges = <0 0 0 0x>;
>>  compatible = "simple-bus";
>>
>> -    pinctrl@100 {
>> +    tlmm: pinctrl@100 {
>>  compatible = "qcom,ipq8074-pinctrl";
>>  reg = <0x100 0x30>;
>>  interrupts = ;
>> @@ -229,6 +229,161 @@
>>  dma-names = "tx", "rx", "cmd";
>>  status = "disabled";
>>  };
>> +
>> +    pcie_phy0: phy@86000 {
>> +    compatible = "qcom,ipq8074-qmp-pcie-phy";
>> +    reg = <0x86000 0x1000>;
>> +    #phy-cells = <0>;
>> +    clocks = < GCC_PCIE0_PIPE_CLK>;
>> +    clock-names = "pipe_clk";
>> +    clock-output-names = "pcie20_phy0_pipe_clk";
>> +
>> +    resets = < GCC_PCIE0_PHY_BCR>,
>> +    < GCC_PCIE0PHY_PHY_BCR>;
>> +    reset-names = "phy",
>> +  "common";
>> +    status = "disabled";
>> +    };
>> +
>> +    pcie0: pci@2000 {
>> +    compatible = "qcom,pcie-ipq8074";
>> +    reg =  <0x2000 0xf1d
>> +    0x2F20 0xa8
> 
>  s/0x2F20/0x2f20

ok

> 
>> +    0x8 0x2000
>> +    0x2010 0x1000>;
>> +    reg-names = "dbi", "elbi", "parf", "config";
>> +    device_type = "pci";
>> +    linux,pci-domain = <0>;
>> +    bus-range = <0x00 0xff>;
>> +    num-lanes = <1>;
>> +    #address-cells = <3>;
>> +    #size-cells = <2>;
>> +
>> +    phys = <_phy0>;
>> +    phy-names = "pciephy";
>> +
>> +    ranges = <0x8100 0 0x2020 0x2020
>> +  0 0x0010   /* downstream I/O */
> 
>  we can remove trailing zeros from address.
>  s/0x0010/0x10
> 
>> +  0x8200 0 0x2030 0x2030
>> +  0 0x00d0>; /* non-prefetchable memory */
> 
>  s/0x00d0/0xd0
> 
>  Same changes are for PCIE1 also.

 ok

> 
>  With that.
> 
>  Reviewed-by: Abhishek Sahu <abs...@codeaurora.org>

 Thanks.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 12/13] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

Hi Abhishek,

On 3/16/2018 4:50 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> The driver/phy support for ipq8074 is available now.
>> So enabling the nodes in DT.
>>
>> Signed-off-by: Sricharan R 
>> ---
>>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 
>> +-
>>  1 file changed, 156 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 806fc56..7562650 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -24,7 +24,7 @@
>>  ranges = <0 0 0 0x>;
>>  compatible = "simple-bus";
>>
>> -    pinctrl@100 {
>> +    tlmm: pinctrl@100 {
>>  compatible = "qcom,ipq8074-pinctrl";
>>  reg = <0x100 0x30>;
>>  interrupts = ;
>> @@ -229,6 +229,161 @@
>>  dma-names = "tx", "rx", "cmd";
>>  status = "disabled";
>>  };
>> +
>> +    pcie_phy0: phy@86000 {
>> +    compatible = "qcom,ipq8074-qmp-pcie-phy";
>> +    reg = <0x86000 0x1000>;
>> +    #phy-cells = <0>;
>> +    clocks = < GCC_PCIE0_PIPE_CLK>;
>> +    clock-names = "pipe_clk";
>> +    clock-output-names = "pcie20_phy0_pipe_clk";
>> +
>> +    resets = < GCC_PCIE0_PHY_BCR>,
>> +    < GCC_PCIE0PHY_PHY_BCR>;
>> +    reset-names = "phy",
>> +  "common";
>> +    status = "disabled";
>> +    };
>> +
>> +    pcie0: pci@2000 {
>> +    compatible = "qcom,pcie-ipq8074";
>> +    reg =  <0x2000 0xf1d
>> +    0x2F20 0xa8
> 
>  s/0x2F20/0x2f20

ok

> 
>> +    0x8 0x2000
>> +    0x2010 0x1000>;
>> +    reg-names = "dbi", "elbi", "parf", "config";
>> +    device_type = "pci";
>> +    linux,pci-domain = <0>;
>> +    bus-range = <0x00 0xff>;
>> +    num-lanes = <1>;
>> +    #address-cells = <3>;
>> +    #size-cells = <2>;
>> +
>> +    phys = <_phy0>;
>> +    phy-names = "pciephy";
>> +
>> +    ranges = <0x8100 0 0x2020 0x2020
>> +  0 0x0010   /* downstream I/O */
> 
>  we can remove trailing zeros from address.
>  s/0x0010/0x10
> 
>> +  0x8200 0 0x2030 0x2030
>> +  0 0x00d0>; /* non-prefetchable memory */
> 
>  s/0x00d0/0xd0
> 
>  Same changes are for PCIE1 also.

 ok

> 
>  With that.
> 
>  Reviewed-by: Abhishek Sahu 

 Thanks.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 02/13] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Hi Marc,

On 3/16/2018 5:47 PM, Marc Zyngier wrote:
> On 16/03/18 09:38, Sricharan R wrote:
>> Now with the driver updates for some peripherals being there,
>> add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
>> peripheral support.
>>
>> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
>> ---
>>  arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 
>> 
>>  1 file changed, 134 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
>> b/arch/arm/boot/dts/qcom-ipq4019.dtsi
>> index 10d112a..e38fffa 100644
>> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
>> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
>> @@ -25,7 +25,9 @@
> 
> [...]
> 
>> +pcie0: pci@4000 {
>> +compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
>> +reg =  <0x4000 0xf1d
>> +0x4f20 0xa8
>> +0x8 0x2000
>> +0x4010 0x1000>;
>> +reg-names = "dbi", "elbi", "parf", "config";
>> +device_type = "pci";
>> +linux,pci-domain = <0>;
>> +bus-range = <0x00 0xff>;
>> +num-lanes = <1>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +
>> +ranges = <0x8100 0 0x40200000 0x4020 0 
>> 0x0010
>> +  0x8200 0 0x4800 0x4800 0 
>> 0x1000>;
>> +
>> +interrupts = ;
> 
> There is no such thing as IRQ_TYPE_NONE. Please replace this with the
> actual trigger information.

 ok, will update this.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 02/13] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Hi Marc,

On 3/16/2018 5:47 PM, Marc Zyngier wrote:
> On 16/03/18 09:38, Sricharan R wrote:
>> Now with the driver updates for some peripherals being there,
>> add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
>> peripheral support.
>>
>> Signed-off-by: Sricharan R 
>> ---
>>  arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 
>> 
>>  1 file changed, 134 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
>> b/arch/arm/boot/dts/qcom-ipq4019.dtsi
>> index 10d112a..e38fffa 100644
>> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
>> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
>> @@ -25,7 +25,9 @@
> 
> [...]
> 
>> +pcie0: pci@4000 {
>> +compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
>> +reg =  <0x4000 0xf1d
>> +0x4f20 0xa8
>> +0x8 0x2000
>> +0x4010 0x1000>;
>> +reg-names = "dbi", "elbi", "parf", "config";
>> +device_type = "pci";
>> +linux,pci-domain = <0>;
>> +bus-range = <0x00 0xff>;
>> +num-lanes = <1>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +
>> +ranges = <0x8100 0 0x4020 0x4020 0 
>> 0x0010
>> +  0x8200 0 0x4800 0x4800 0 
>> 0x1000>;
>> +
>> +interrupts = ;
> 
> There is no such thing as IRQ_TYPE_NONE. Please replace this with the
> actual trigger information.

 ok, will update this.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 03/13] ARM: dts: ipq4019: Change the max opp frequency

[Sricharan R]

The max opp frequency is 716MHZ. So update that.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index e38fffa..2ee71c2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000   110
20  110
50  110
-   666000  110
+   716000  110
>;
clock-latency = <256000>;
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 03/13] ARM: dts: ipq4019: Change the max opp frequency

[Sricharan R]

The max opp frequency is 716MHZ. So update that.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index e38fffa..2ee71c2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000   110
20  110
50  110
-   666000  110
+   716000  110
>;
clock-latency = <256000>;
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Add the common parts for the dk04 boards.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++
 1 file changed, 129 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 000..96ce081
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+   compatible = "qcom,ipq4019";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+
+   nand_pins: nand_pins {
+   mux {
+   pins = "gpio53", "gpio55", "gpio56",
+   "gpio57", "gpio58", "gpio59",
+   "gpio60", "gpio62", "gpio63",
+   "gpio64", "gpio65", "gpio66",
+   "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   blsp_dma: dma@7884000 {
+   status = "ok";
+   };
+
+   spi_0: spi@78b5000 { /* 

[PATCH v2 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Add the common parts for the dk04 boards.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++
 1 file changed, 129 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 000..96ce081
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+   compatible = "qcom,ipq4019";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+
+   nand_pins: nand_pins {
+   mux {
+   pins = "gpio53", "gpio55", "gpio56",
+   "gpio57", "gpio58", "gpio59",
+   "gpio60", "gpio62", "gpio63",
+   "gpio64", "gpio65", "gpio66",
+   "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   blsp_dma: dma@7884000 {
+   status = "ok";
+   };
+
+   spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+ 

[PATCH v2 08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

Add the common data for all dk07 based boards.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++
 1 file changed, 83 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 000..37a2ea8
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+   compatible = "qcom,ipq4019";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x2000>; /* 512MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   blsp_dma: dma@7884000 {
+   status = "ok";
+   };
+
+   i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   qpic_bam: dma@7984000 {
+   status = "ok";
+   };
+
+   nand: qpic-nand@79b {
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

Add the common data for all dk07 based boards.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++
 1 file changed, 83 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 000..37a2ea8
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+   compatible = "qcom,ipq4019";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x2000>; /* 512MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   blsp_dma: dma@7884000 {
+   status = "ok";
+   };
+
+   i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   qpic_bam: dma@7984000 {
+   status = "ok";
+   };
+
+   nand: qpic-nand@79b {
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 10/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

[Sricharan R]

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +
 2 files changed, 27 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8c93fd0..0844087 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -750,6 +750,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+   qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 000..c1e909c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+
+   soc {
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 10/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

[Sricharan R]

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +
 2 files changed, 27 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8c93fd0..0844087 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -750,6 +750,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+   qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 000..c1e909c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+
+   soc {
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++
 1 file changed, 103 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..81dff867 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
 
aliases {
serial0 = _uart5;
+   serial1 = _blsp2;
};
 
chosen {
@@ -41,6 +42,47 @@
bias-disable;
};
};
+
+i2c_0_pins: i2c_0_pinmux {
+ mux {
+  pins = "gpio42", "gpio43";
+  function = "blsp1_i2c";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+spi_0_pins: spi_0_pins {
+ mux {
+  pins = "gpio38", "gpio39", "gpio40", 
"gpio41";
+  function = "blsp0_spi";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+hsuart_pins: hsuart_pins {
+ mux {
+  pins = "gpio46", "gpio47", "gpio48", 
"gpio49";
+  function = "blsp2_uart";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+qpic_pins: qpic_pins {
+   mux {
+  pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+  function = "qpic";
+  drive-strength = <8>;
+  bias-disable;
+ };
+   };
+
};
 
serial@78b3000 {
@@ -48,5 +90,66 @@
pinctrl-names = "default";
status = "ok";
};
+
+   spi@78b5000 {
+pinctrl-0 = <_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+
+m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+};
+   };
+
+   serial@78B1000 {
+pinctrl-0 = <_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   i2c_0@78b6000 {
+pinctrl-0 = <_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   dma@7984000 {
+status = "ok";
+   };
+
+   nand@79b {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+
+   nand@0 {
+   reg = <0>;
+   nand-ecc-strength = <4>;
+   nand-ecc-step-size = <512>;
+   nand-bus-width = <8>;
+   };
+   };
+
+   phy@86000 {
+   status = "ok";
+   };
+
+   phy@8e000 {
+   status = "ok";
+   };
+
+   pci@2000 {
+   status = "ok";
+   perst-gpio = < 58 0x1>;
+   };
+
+   pci@1000 {
+   status = "ok";
+   perst-gpio = < 61 0x1>;
+   };
};
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++
 1 file changed, 103 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..81dff867 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
 
aliases {
serial0 = _uart5;
+   serial1 = _blsp2;
};
 
chosen {
@@ -41,6 +42,47 @@
bias-disable;
};
};
+
+i2c_0_pins: i2c_0_pinmux {
+ mux {
+  pins = "gpio42", "gpio43";
+  function = "blsp1_i2c";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+spi_0_pins: spi_0_pins {
+ mux {
+  pins = "gpio38", "gpio39", "gpio40", 
"gpio41";
+  function = "blsp0_spi";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+hsuart_pins: hsuart_pins {
+ mux {
+  pins = "gpio46", "gpio47", "gpio48", 
"gpio49";
+  function = "blsp2_uart";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+qpic_pins: qpic_pins {
+   mux {
+  pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+  function = "qpic";
+  drive-strength = <8>;
+  bias-disable;
+ };
+   };
+
};
 
serial@78b3000 {
@@ -48,5 +90,66 @@
pinctrl-names = "default";
status = "ok";
};
+
+   spi@78b5000 {
+pinctrl-0 = <_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+
+m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+};
+   };
+
+   serial@78B1000 {
+pinctrl-0 = <_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   i2c_0@78b6000 {
+pinctrl-0 = <_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   dma@7984000 {
+status = "ok";
+   };
+
+   nand@79b {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+
+   nand@0 {
+   reg = <0>;
+   nand-ecc-strength = <4>;
+   nand-ecc-step-size = <512>;
+   nand-bus-width = <8>;
+   };
+   };
+
+   phy@86000 {
+   status = "ok";
+   };
+
+   phy@8e000 {
+   status = "ok";
+   };
+
+   pci@2000 {
+   status = "ok";
+   perst-gpio = < 58 0x1>;
+   };
+
+   pci@1000 {
+   status = "ok";
+   perst-gpio = < 61 0x1>;
+   };
};
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 12/13] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
 1 file changed, 156 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 806fc56..7562650 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
 
-   pinctrl@100 {
+   tlmm: pinctrl@100 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x100 0x30>;
interrupts = ;
@@ -229,6 +229,161 @@
dma-names = "tx", "rx", "cmd";
status = "disabled";
};
+
+   pcie_phy0: phy@86000 {
+   compatible = "qcom,ipq8074-qmp-pcie-phy";
+   reg = <0x86000 0x1000>;
+   #phy-cells = <0>;
+   clocks = < GCC_PCIE0_PIPE_CLK>;
+   clock-names = "pipe_clk";
+   clock-output-names = "pcie20_phy0_pipe_clk";
+
+   resets = < GCC_PCIE0_PHY_BCR>,
+   < GCC_PCIE0PHY_PHY_BCR>;
+   reset-names = "phy",
+ "common";
+   status = "disabled";
+   };
+
+   pcie0: pci@2000 {
+   compatible = "qcom,pcie-ipq8074";
+   reg =  <0x2000 0xf1d
+   0x2F20 0xa8
+   0x8 0x2000
+   0x2010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   phys = <_phy0>;
+   phy-names = "pciephy";
+
+   ranges = <0x8100 0 0x2020 0x2020
+ 0 0x0010   /* downstream I/O */
+ 0x8200 0 0x2030 0x2030
+ 0 0x00d0>; /* non-prefetchable memory */
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 75
+IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 78
+IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3  0 79
+IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4  0 83
+IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+   clocks = < GCC_SYS_NOC_PCIE0_AXI_CLK>,
+< GCC_PCIE0_AXI_M_CLK>,
+< GCC_PCIE0_AXI_S_CLK>,
+< GCC_PCIE0_AHB_CLK>,
+< GCC_PCIE0_AUX_CLK>;
+
+   clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+   resets = < GCC_PCIE0_PIPE_ARES>,
+< GCC_PCIE0_SLEEP_ARES>,
+< GCC_PCIE0_CORE_STICKY_ARES>,
+< GCC_PCIE0_AXI_MASTER_ARES>,
+< GCC_PCIE0_AXI_SLAVE_ARES>,
+< GCC_PCIE0_AHB_ARES>,
+< GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+   reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+   

[PATCH v2 12/13] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.

Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
 1 file changed, 156 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 806fc56..7562650 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
 
-   pinctrl@100 {
+   tlmm: pinctrl@100 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x100 0x30>;
interrupts = ;
@@ -229,6 +229,161 @@
dma-names = "tx", "rx", "cmd";
status = "disabled";
};
+
+   pcie_phy0: phy@86000 {
+   compatible = "qcom,ipq8074-qmp-pcie-phy";
+   reg = <0x86000 0x1000>;
+   #phy-cells = <0>;
+   clocks = < GCC_PCIE0_PIPE_CLK>;
+   clock-names = "pipe_clk";
+   clock-output-names = "pcie20_phy0_pipe_clk";
+
+   resets = < GCC_PCIE0_PHY_BCR>,
+   < GCC_PCIE0PHY_PHY_BCR>;
+   reset-names = "phy",
+ "common";
+   status = "disabled";
+   };
+
+   pcie0: pci@2000 {
+   compatible = "qcom,pcie-ipq8074";
+   reg =  <0x2000 0xf1d
+   0x2F20 0xa8
+   0x8 0x2000
+   0x2010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   phys = <_phy0>;
+   phy-names = "pciephy";
+
+   ranges = <0x8100 0 0x2020 0x2020
+ 0 0x0010   /* downstream I/O */
+ 0x8200 0 0x2030 0x2030
+ 0 0x00d0>; /* non-prefetchable memory */
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 75
+IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 78
+IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3  0 79
+IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4  0 83
+IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+   clocks = < GCC_SYS_NOC_PCIE0_AXI_CLK>,
+< GCC_PCIE0_AXI_M_CLK>,
+< GCC_PCIE0_AXI_S_CLK>,
+< GCC_PCIE0_AHB_CLK>,
+< GCC_PCIE0_AUX_CLK>;
+
+   clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+   resets = < GCC_PCIE0_PIPE_ARES>,
+< GCC_PCIE0_SLEEP_ARES>,
+< GCC_PCIE0_CORE_STICKY_ARES>,
+< GCC_PCIE0_AXI_MASTER_ARES>,
+< GCC_PCIE0_AXI_SLAVE_ARES>,
+< GCC_PCIE0_AHB_ARES>,
+< GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+   reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ 

[PATCH v2 11/13] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

Add serial, i2c, bam, spi, qpic peripheral nodes.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..806fc56 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -124,6 +124,111 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x07884000 0x2b000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   };
+
+   serial_blsp0: serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+< GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   status = "disabled";
+   };
+
+   serial_blsp2: serial@78B1000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78B1000 0x200>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART3_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <_dma 4>,
+   <_dma 5>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   spi_0: spi@78b5000 {
+   compatible = "qcom,spi-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b5000 0x600>;
+   interrupts = ;
+   spi-max-frequency = <5000>;
+   clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <_dma 12>, <_dma 13>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   i2c_0: i2c@78b6000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+   < GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency  = <40>;
+   dmas = <_dma 15>, <_dma 14>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   i2c_1: i2c@78b7000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b7000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+   < GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency  = <10>;
+   dmas = <_dma 17>, <_dma 16>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   qpic_bam: dma@7984000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7984000 0x1a000>;
+   interrupts = ;
+   clocks = < GCC_QPIC_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+ 

[PATCH v2 11/13] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

Add serial, i2c, bam, spi, qpic peripheral nodes.

Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..806fc56 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -124,6 +124,111 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x07884000 0x2b000>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   };
+
+   serial_blsp0: serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+< GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   status = "disabled";
+   };
+
+   serial_blsp2: serial@78B1000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78B1000 0x200>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_UART3_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <_dma 4>,
+   <_dma 5>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   spi_0: spi@78b5000 {
+   compatible = "qcom,spi-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b5000 0x600>;
+   interrupts = ;
+   spi-max-frequency = <5000>;
+   clocks = < GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <_dma 12>, <_dma 13>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   i2c_0: i2c@78b6000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+   < GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency  = <40>;
+   dmas = <_dma 15>, <_dma 14>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   i2c_1: i2c@78b7000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b7000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+   < GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency  = <10>;
+   dmas = <_dma 17>, <_dma 16>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   qpic_bam: dma@7984000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7984000 0x1a000>;
+   interrupts = ;
+   clocks = < GCC_QPIC_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   status

[PATCH v2 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b71487a..8c93fd0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+   qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 000..4562f7f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK07.1-C1";
+
+   soc {
+   pcie0: pci@4000 {
+   status = "ok";
+   perst-gpio = < 38 0x1>;
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   status = "ok";
+   };
+
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = < 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b71487a..8c93fd0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+   qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 000..4562f7f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK07.1-C1";
+
+   soc {
+   pcie0: pci@4000 {
+   status = "ok";
+   perst-gpio = < 38 0x1>;
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   status = "ok";
+   };
+
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+   pinctrl-0 = <_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = < 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[Sricharan R]

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20 
 2 files changed, 21 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b59e99b..4f209fb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -747,6 +747,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 000..871ac3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+
+   soc {
+   qpic_bam: dma@7984000 {
+   status = "ok";
+   };
+
+   nand: qpic-nand@79b {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 07/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

[Sricharan R]

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/Makefile  | 1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8 
 2 files changed, 9 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4f209fb..b71487a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -748,6 +748,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 000..0843523
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[Sricharan R]

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20 
 2 files changed, 21 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b59e99b..4f209fb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -747,6 +747,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 000..871ac3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+
+   soc {
+   qpic_bam: dma@7984000 {
+   status = "ok";
+   };
+
+   nand: qpic-nand@79b {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 07/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

[Sricharan R]

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  | 1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8 
 2 files changed, 9 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4f209fb..b71487a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -748,6 +748,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 000..0843523
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 02/13] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 
 1 file changed, 134 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..e38fffa 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,7 +25,9 @@
 
aliases {
spi0 = _0;
+   spi1 = _1;
i2c0 = _0;
+   i2c1 = _1;
};
 
cpus {
@@ -104,6 +106,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -172,6 +180,22 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 5>, <_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 7>, <_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
@@ -184,9 +208,24 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 9>, <_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+< GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 11>, <_dma 10>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
 
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
 
+   pcie0: pci@4000 {
+   compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+   reg =  <0x4000 0xf1d
+   0x4f20 0xa8
+   0x8 0x2000
+   0x4010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   ranges = <0x8100 0 0x4020 0x4020 0 
0x0010
+ 0x8200 0 0x4800 0x4800 0 
0x1000>;
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 142 
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 143 
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3  0 144 
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ 

[PATCH v2 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[Sricharan R]

Adds missing memory, reserved-memory nodes.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ad0fbc9 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,34 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
 
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
soc {
rng@22000 {
status = "ok";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 02/13] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 
 1 file changed, 134 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..e38fffa 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,7 +25,9 @@
 
aliases {
spi0 = _0;
+   spi1 = _1;
i2c0 = _0;
+   i2c1 = _1;
};
 
cpus {
@@ -104,6 +106,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -172,6 +180,22 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 5>, <_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 7>, <_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
@@ -184,9 +208,24 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 9>, <_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+< GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 11>, <_dma 10>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
 
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
 
+   pcie0: pci@4000 {
+   compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+   reg =  <0x4000 0xf1d
+   0x4f20 0xa8
+   0x8 0x2000
+   0x4010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   ranges = <0x8100 0 0x4020 0x4020 0 
0x0010
+ 0x8200 0 0x4800 0x4800 0 
0x1000>;
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 142 
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 143 
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3  0 144 
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4  0 145 
IRQ_TYPE_LEVEL_H

[PATCH v2 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[Sricharan R]

Adds missing memory, reserved-memory nodes.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ad0fbc9 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,34 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
 
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   rsvd1@8700 {
+   /* Reserved for other subsystem */
+   reg = <0x8700 0x50>;
+   no-map;
+   };
+
+   wifi_dump@8750 {
+   reg = <0x8750 0x60>;
+   no-map;
+   };
+
+   rsvd2@87B0 {
+   /* Reserved for other subsystem */
+   reg = <0x87B0 0x50>;
+   no-map;
+   };
+   };
+
soc {
rng@22000 {
status = "ok";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 00/13] ARM: dts: ipq: updates to enable a few peripherals

[Sricharan R]

[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
  as support for spinand is not complete
* Based all patches on top of Andy's for-next branch

[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html

Sricharan R (13):
  firmware: qcom: scm: Add ipq4019 soc compatible
  ARM: dts: ipq4019: Add a few peripheral nodes
  ARM: dts: ipq4019: Change the max opp frequency
  ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
  ARM: dts: ipq8074: Add peripheral nodes
  ARM: dts: ipq8074: Add pcie nodes
  ARM: dts: ipq8074: Enable few peripherals for hk01 board

 .../devicetree/bindings/firmware/qcom,scm.txt  |   3 +-
 arch/arm/boot/dts/Makefile |   4 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi  |  32 ++-
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts|  20 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts|   8 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi  | 135 +++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts|  65 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts|  26 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi  |  83 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi| 136 ++-
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts  | 103 
 arch/arm64/boot/dts/qcom/ipq8074.dtsi  | 262 -
 drivers/firmware/qcom_scm.c|   3 +
 13 files changed, 875 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 01/13] firmware: qcom: scm: Add ipq4019 soc compatible

[Sricharan R]

Add the compatible for ipq4019.
This does not need clocks to do scm calls.

Reviewed-by: Rob Herring <r...@kernel.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
 drivers/firmware/qcom_scm.c | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt 
b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 7b40054..fcf6979 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -11,9 +11,10 @@ Required properties:
  * "qcom,scm-msm8660" for MSM8660 platforms
  * "qcom,scm-msm8690" for MSM8690 platforms
  * "qcom,scm-msm8996" for MSM8996 platforms
+ * "qcom,scm-ipq4019" for IPQ4019 platforms
  * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
 - clocks: One to three clocks may be required based on compatible.
- * No clock required for "qcom,scm-msm8996"
+ * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
  * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and 
"qcom,scm-msm8960"
  * Core, iface, and bus clocks required for "qcom,scm"
 - clock-names: Must contain "core" for the core clock, "iface" for the 
interface
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 5a7d6930..e778af7 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -603,6 +603,9 @@ static void qcom_scm_shutdown(struct platform_device *pdev)
{ .compatible = "qcom,scm-msm8996",
  .data = NULL, /* no clocks */
},
+   { .compatible = "qcom,scm-ipq4019",
+ .data = NULL, /* no clocks */
+   },
{ .compatible = "qcom,scm",
  .data = (void *)(SCM_HAS_CORE_CLK
   | SCM_HAS_IFACE_CLK
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 00/13] ARM: dts: ipq: updates to enable a few peripherals

[Sricharan R]

[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
  as support for spinand is not complete
* Based all patches on top of Andy's for-next branch

[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html

Sricharan R (13):
  firmware: qcom: scm: Add ipq4019 soc compatible
  ARM: dts: ipq4019: Add a few peripheral nodes
  ARM: dts: ipq4019: Change the max opp frequency
  ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
  ARM: dts: ipq8074: Add peripheral nodes
  ARM: dts: ipq8074: Add pcie nodes
  ARM: dts: ipq8074: Enable few peripherals for hk01 board

 .../devicetree/bindings/firmware/qcom,scm.txt  |   3 +-
 arch/arm/boot/dts/Makefile |   4 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi  |  32 ++-
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts|  20 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts|   8 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi  | 135 +++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts|  65 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts|  26 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi  |  83 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi| 136 ++-
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts  | 103 
 arch/arm64/boot/dts/qcom/ipq8074.dtsi  | 262 -
 drivers/firmware/qcom_scm.c|   3 +
 13 files changed, 875 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v2 01/13] firmware: qcom: scm: Add ipq4019 soc compatible

[Sricharan R]

Add the compatible for ipq4019.
This does not need clocks to do scm calls.

Reviewed-by: Rob Herring 
Signed-off-by: Sricharan R 
---
 Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
 drivers/firmware/qcom_scm.c | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt 
b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 7b40054..fcf6979 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -11,9 +11,10 @@ Required properties:
  * "qcom,scm-msm8660" for MSM8660 platforms
  * "qcom,scm-msm8690" for MSM8690 platforms
  * "qcom,scm-msm8996" for MSM8996 platforms
+ * "qcom,scm-ipq4019" for IPQ4019 platforms
  * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
 - clocks: One to three clocks may be required based on compatible.
- * No clock required for "qcom,scm-msm8996"
+ * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
  * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and 
"qcom,scm-msm8960"
  * Core, iface, and bus clocks required for "qcom,scm"
 - clock-names: Must contain "core" for the core clock, "iface" for the 
interface
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 5a7d6930..e778af7 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -603,6 +603,9 @@ static void qcom_scm_shutdown(struct platform_device *pdev)
{ .compatible = "qcom,scm-msm8996",
  .data = NULL, /* no clocks */
},
+   { .compatible = "qcom,scm-ipq4019",
+ .data = NULL, /* no clocks */
+   },
{ .compatible = "qcom,scm",
  .data = (void *)(SCM_HAS_CORE_CLK
   | SCM_HAS_IFACE_CLK
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v2 05/13] i2c: qup: schedule EOT and FLUSH tags at the end of transfer

[Sricharan R]

On 3/12/2018 6:44 PM, Abhishek Sahu wrote:
> The role of FLUSH and EOT tag is to flush already scheduled
> descriptors in BAM HW in case of error. EOT is required only
> when descriptors are scheduled in RX FIFO. If all the messages
> are WRITE, then only FLUSH tag will be used.
> 
> A single BAM transfer can have multiple read and write messages.
> The EOT and FLUSH tags should be scheduled at the end of BAM HW
> descriptors. Since the READ and WRITE can be present in any order
> so for some of the cases, these tags are not being written
> correctly.
> 
> Following is one of the example
> 
>READ, READ, READ, READ
> 
> Currently EOT and FLUSH tags are being written after each READ.
> If QUP gets NACK for first READ itself, then flush will be
> triggered. It will look for first FLUSH tag in TX FIFO and will
> stop there so only descriptors for first READ descriptors be
> flushed. All the scheduled descriptors should be cleared to
> generate BAM DMA completion.
> 
> Now this patch is scheduling FLUSH and EOT only once after all the
> descriptors. So, flush will clear all the scheduled descriptors and
> BAM will generate the completion interrupt.
> 
> Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
> ---
> 

Reviewed-by: Sricharan R <sricha...@codeaurora.org>

Regards,
 Sricharan





> * Changes from v1:
> 
> 1. Modified commit message with more details
> 
>  drivers/i2c/busses/i2c-qup.c | 39 ---
>  1 file changed, 24 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
> index d970458..b2e8f57 100644
> --- a/drivers/i2c/busses/i2c-qup.c
> +++ b/drivers/i2c/busses/i2c-qup.c
> @@ -551,7 +551,7 @@ static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, 
> struct qup_i2c_dev *qup,
>  }
>  
>  static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
> - struct i2c_msg *msg,  int is_dma)
> + struct i2c_msg *msg)
>  {
>   u16 addr = i2c_8bit_addr_from_msg(msg);
>   int len = 0;
> @@ -592,11 +592,6 @@ static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev 
> *qup,
>   else
>   tags[len++] = data_len;
>  
> - if ((msg->flags & I2C_M_RD) && last && is_dma) {
> - tags[len++] = QUP_BAM_INPUT_EOT;
> - tags[len++] = QUP_BAM_FLUSH_STOP;
> - }
> -
>   return len;
>  }
>  
> @@ -605,7 +600,7 @@ static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, 
> struct i2c_msg *msg)
>   int data_len = 0, tag_len, index;
>   int ret;
>  
> - tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0);
> + tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg);
>   index = msg->len - qup->blk.data_len;
>  
>   /* only tags are written for read */
> @@ -701,7 +696,7 @@ static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, 
> struct i2c_msg *msg,
>   while (qup->blk.pos < blocks) {
>   tlen = (i == (blocks - 1)) ? rem : limit;
>   tags = >start_tag.start[off + len];
> - len += qup_i2c_set_tags(tags, qup, msg, 1);
> + len += qup_i2c_set_tags(tags, qup, msg);
>   qup->blk.data_len -= tlen;
>  
>   /* scratch buf to read the start and len tags */
> @@ -729,17 +724,11 @@ static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, 
> struct i2c_msg *msg,
>   return ret;
>  
>   off += len;
> - /* scratch buf to read the BAM EOT and FLUSH tags */
> - ret = qup_sg_set_buf(>brx.sg[rx_cnt++],
> -  >brx.tag.start[0],
> -  2, qup, DMA_FROM_DEVICE);
> - if (ret)
> - return ret;
>   } else {
>   while (qup->blk.pos < blocks) {
>   tlen = (i == (blocks - 1)) ? rem : limit;
>   tags = >start_tag.start[off + tx_len];
> - len = qup_i2c_set_tags(tags, qup, msg, 1);
> + len = qup_i2c_set_tags(tags, qup, msg);
>   qup->blk.data_len -= tlen;
>  
>   ret = qup_sg_set_buf(>btx.sg[tx_cnt++],
> @@ -779,6 +768,26 @@ static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, 
> struct i2c_msg *msg,
>   msg++;
>   }
>  
> + /

Re: [PATCH v2 05/13] i2c: qup: schedule EOT and FLUSH tags at the end of transfer

[Sricharan R]

On 3/12/2018 6:44 PM, Abhishek Sahu wrote:
> The role of FLUSH and EOT tag is to flush already scheduled
> descriptors in BAM HW in case of error. EOT is required only
> when descriptors are scheduled in RX FIFO. If all the messages
> are WRITE, then only FLUSH tag will be used.
> 
> A single BAM transfer can have multiple read and write messages.
> The EOT and FLUSH tags should be scheduled at the end of BAM HW
> descriptors. Since the READ and WRITE can be present in any order
> so for some of the cases, these tags are not being written
> correctly.
> 
> Following is one of the example
> 
>READ, READ, READ, READ
> 
> Currently EOT and FLUSH tags are being written after each READ.
> If QUP gets NACK for first READ itself, then flush will be
> triggered. It will look for first FLUSH tag in TX FIFO and will
> stop there so only descriptors for first READ descriptors be
> flushed. All the scheduled descriptors should be cleared to
> generate BAM DMA completion.
> 
> Now this patch is scheduling FLUSH and EOT only once after all the
> descriptors. So, flush will clear all the scheduled descriptors and
> BAM will generate the completion interrupt.
> 
> Signed-off-by: Abhishek Sahu 
> ---
> 

Reviewed-by: Sricharan R 

Regards,
 Sricharan





> * Changes from v1:
> 
> 1. Modified commit message with more details
> 
>  drivers/i2c/busses/i2c-qup.c | 39 ---
>  1 file changed, 24 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
> index d970458..b2e8f57 100644
> --- a/drivers/i2c/busses/i2c-qup.c
> +++ b/drivers/i2c/busses/i2c-qup.c
> @@ -551,7 +551,7 @@ static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, 
> struct qup_i2c_dev *qup,
>  }
>  
>  static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
> - struct i2c_msg *msg,  int is_dma)
> + struct i2c_msg *msg)
>  {
>   u16 addr = i2c_8bit_addr_from_msg(msg);
>   int len = 0;
> @@ -592,11 +592,6 @@ static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev 
> *qup,
>   else
>   tags[len++] = data_len;
>  
> - if ((msg->flags & I2C_M_RD) && last && is_dma) {
> - tags[len++] = QUP_BAM_INPUT_EOT;
> - tags[len++] = QUP_BAM_FLUSH_STOP;
> - }
> -
>   return len;
>  }
>  
> @@ -605,7 +600,7 @@ static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, 
> struct i2c_msg *msg)
>   int data_len = 0, tag_len, index;
>   int ret;
>  
> - tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0);
> + tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg);
>   index = msg->len - qup->blk.data_len;
>  
>   /* only tags are written for read */
> @@ -701,7 +696,7 @@ static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, 
> struct i2c_msg *msg,
>   while (qup->blk.pos < blocks) {
>   tlen = (i == (blocks - 1)) ? rem : limit;
>   tags = >start_tag.start[off + len];
> - len += qup_i2c_set_tags(tags, qup, msg, 1);
> + len += qup_i2c_set_tags(tags, qup, msg);
>   qup->blk.data_len -= tlen;
>  
>   /* scratch buf to read the start and len tags */
> @@ -729,17 +724,11 @@ static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, 
> struct i2c_msg *msg,
>   return ret;
>  
>   off += len;
> - /* scratch buf to read the BAM EOT and FLUSH tags */
> - ret = qup_sg_set_buf(>brx.sg[rx_cnt++],
> -  >brx.tag.start[0],
> -  2, qup, DMA_FROM_DEVICE);
> - if (ret)
> - return ret;
>   } else {
>   while (qup->blk.pos < blocks) {
>   tlen = (i == (blocks - 1)) ? rem : limit;
>   tags = >start_tag.start[off + tx_len];
> - len = qup_i2c_set_tags(tags, qup, msg, 1);
> + len = qup_i2c_set_tags(tags, qup, msg);
>   qup->blk.data_len -= tlen;
>  
>   ret = qup_sg_set_buf(>btx.sg[tx_cnt++],
> @@ -779,6 +768,26 @@ static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, 
> struct i2c_msg *msg,
>   msg++;
>   }
>  
> + /* schedule the EOT and FLUSH I2C tags 

Re: [PATCH v2 13/13] i2c: qup: reorganization of driver code to remove polling for qup v2

[Sricharan R]

Hi Abhishek,

On 3/12/2018 6:45 PM, Abhishek Sahu wrote:
> Following are the major issues in current driver code
> 
> 1. The current driver simply assumes the transfer completion
>whenever its gets any non-error interrupts and then simply do the
>polling of available/free bytes in FIFO.
> 2. The block mode is not working properly since no handling in
>being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_READ.
> 3. An i2c transfer can contain multiple message and QUP v2
>supports reconfiguration during run in which the mode should be same
>for all the sub transfer. Currently the mode is being programmed
>before every sub transfer which is functionally wrong. If one message
>is less than FIFO length and other message is greater than FIFO
>length, then transfers will fail.
> 
> Because of above, i2c v2 transfers of size greater than 64 are failing
> with following error message
> 
>   i2c_qup 78b6000.i2c: timeout for fifo out full
> 
> To make block mode working properly and move to use the interrupts
> instead of polling, major code reorganization is required. Following
> are the major changes done in this patch
> 
> 1. Remove the polling of TX FIFO free space and RX FIFO available
>bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE,
>QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ
>interrupts to handle FIFO’s properly so check all these interrupts.
> 2. Determine the mode for transfer before starting by checking
>all the tx/rx data length in each message. The complete message can be
>transferred either in DMA mode or Programmed IO by FIFO/Block mode.
>in DMA mode, both tx and rx uses same mode but in PIO mode, the TX and
>RX can be in different mode.
> 3. During write, For FIFO mode, TX FIFO can be directly written
>without checking for FIFO space. For block mode, the QUP will generate
>OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available
>space.
> 4. During read, both TX and RX FIFO will be used. TX will be used
>for writing tags and RX will be used for receiving the data. In QUP,
>TX and RX can operate in separate mode so configure modes accordingly.
> 5. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which
>will be generated after all the bytes have been copied in RX FIFO. For
>read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts
>whenever it has block size of available data.
> 6. Split the transfer in chunk of one QUP block size(256 bytes)
>and schedule each block separately. QUP v2 supports reconfiguration
>during run in which QUP can transfer multiple blocks without issuing a
>stop events.
> 7. Port the SMBus block read support for new code changes.
> 
> Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
> ---
> 

Reviewed-by: Sricharan R <sricha...@codeaurora.org>

Regards,
  Sricharan



> * Changes from v1:
> 
> 1. Removed event-based completion and changed transfer completion
>detection logic in interrupt handler
> 2. Fixed function comments as suggested in v1 review comments
> 3. Removed blk_mode_threshold from global structure
> 4. Improved determine mode logic for QUP v2 transfers
> 
>  drivers/i2c/busses/i2c-qup.c | 900 
> +--
>  1 file changed, 515 insertions(+), 385 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
> index 3bf3c34..904dfec 100644
> --- a/drivers/i2c/busses/i2c-qup.c
> +++ b/drivers/i2c/busses/i2c-qup.c
> @@ -141,17 +141,40 @@
>  #define DEFAULT_SRC_CLK 2000
>  
>  /*
> + * Max tags length (start, stop and maximum 2 bytes address) for each QUP
> + * data transfer
> + */
> +#define QUP_MAX_TAGS_LEN 4
> +/* Max data length for each DATARD tags */
> +#define RECV_MAX_DATA_LEN254
> +/* TAG length for DATA READ in RX FIFO  */
> +#define READ_RX_TAGS_LEN 2
> +
> +/*
>   * count: no of blocks
>   * pos: current block number
>   * tx_tag_len: tx tag length for current block
>   * rx_tag_len: rx tag length for current block
>   * data_len: remaining data length for current message
> + * cur_blk_len: data length for current block
>   * total_tx_len: total tx length including tag bytes for current QUP transfer
>   * total_rx_len: total rx length including tag bytes for current QUP transfer
> + * tx_fifo_data_pos: current byte number in TX FIFO word
>   * tx_fifo_free: number of free bytes in current QUP block write.
> + * rx_fifo_data_pos: current byte number in RX FIFO word
>   * fifo_available: number of available bytes in RX FIFO for current
>   *  QUP block re

Re: [PATCH v2 13/13] i2c: qup: reorganization of driver code to remove polling for qup v2

[Sricharan R]

Hi Abhishek,

On 3/12/2018 6:45 PM, Abhishek Sahu wrote:
> Following are the major issues in current driver code
> 
> 1. The current driver simply assumes the transfer completion
>whenever its gets any non-error interrupts and then simply do the
>polling of available/free bytes in FIFO.
> 2. The block mode is not working properly since no handling in
>being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_READ.
> 3. An i2c transfer can contain multiple message and QUP v2
>supports reconfiguration during run in which the mode should be same
>for all the sub transfer. Currently the mode is being programmed
>before every sub transfer which is functionally wrong. If one message
>is less than FIFO length and other message is greater than FIFO
>length, then transfers will fail.
> 
> Because of above, i2c v2 transfers of size greater than 64 are failing
> with following error message
> 
>   i2c_qup 78b6000.i2c: timeout for fifo out full
> 
> To make block mode working properly and move to use the interrupts
> instead of polling, major code reorganization is required. Following
> are the major changes done in this patch
> 
> 1. Remove the polling of TX FIFO free space and RX FIFO available
>bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE,
>QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ
>interrupts to handle FIFO’s properly so check all these interrupts.
> 2. Determine the mode for transfer before starting by checking
>all the tx/rx data length in each message. The complete message can be
>transferred either in DMA mode or Programmed IO by FIFO/Block mode.
>in DMA mode, both tx and rx uses same mode but in PIO mode, the TX and
>RX can be in different mode.
> 3. During write, For FIFO mode, TX FIFO can be directly written
>without checking for FIFO space. For block mode, the QUP will generate
>OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available
>space.
> 4. During read, both TX and RX FIFO will be used. TX will be used
>for writing tags and RX will be used for receiving the data. In QUP,
>TX and RX can operate in separate mode so configure modes accordingly.
> 5. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which
>will be generated after all the bytes have been copied in RX FIFO. For
>read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts
>whenever it has block size of available data.
> 6. Split the transfer in chunk of one QUP block size(256 bytes)
>and schedule each block separately. QUP v2 supports reconfiguration
>during run in which QUP can transfer multiple blocks without issuing a
>stop events.
> 7. Port the SMBus block read support for new code changes.
> 
> Signed-off-by: Abhishek Sahu 
> ---
> 

Reviewed-by: Sricharan R 

Regards,
  Sricharan



> * Changes from v1:
> 
> 1. Removed event-based completion and changed transfer completion
>detection logic in interrupt handler
> 2. Fixed function comments as suggested in v1 review comments
> 3. Removed blk_mode_threshold from global structure
> 4. Improved determine mode logic for QUP v2 transfers
> 
>  drivers/i2c/busses/i2c-qup.c | 900 
> +--
>  1 file changed, 515 insertions(+), 385 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
> index 3bf3c34..904dfec 100644
> --- a/drivers/i2c/busses/i2c-qup.c
> +++ b/drivers/i2c/busses/i2c-qup.c
> @@ -141,17 +141,40 @@
>  #define DEFAULT_SRC_CLK 2000
>  
>  /*
> + * Max tags length (start, stop and maximum 2 bytes address) for each QUP
> + * data transfer
> + */
> +#define QUP_MAX_TAGS_LEN 4
> +/* Max data length for each DATARD tags */
> +#define RECV_MAX_DATA_LEN254
> +/* TAG length for DATA READ in RX FIFO  */
> +#define READ_RX_TAGS_LEN 2
> +
> +/*
>   * count: no of blocks
>   * pos: current block number
>   * tx_tag_len: tx tag length for current block
>   * rx_tag_len: rx tag length for current block
>   * data_len: remaining data length for current message
> + * cur_blk_len: data length for current block
>   * total_tx_len: total tx length including tag bytes for current QUP transfer
>   * total_rx_len: total rx length including tag bytes for current QUP transfer
> + * tx_fifo_data_pos: current byte number in TX FIFO word
>   * tx_fifo_free: number of free bytes in current QUP block write.
> + * rx_fifo_data_pos: current byte number in RX FIFO word
>   * fifo_available: number of available bytes in RX FIFO for current
>   *  QUP block read
> + * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes)

Re: [PATCH v2 12/13] i2c: qup: reorganization of driver code to remove polling for qup v1

[Sricharan R]

Hi Abhishek,

On 3/12/2018 6:45 PM, Abhishek Sahu wrote:
> Following are the major issues in current driver code
> 
> 1. The current driver simply assumes the transfer completion
>whenever its gets any non-error interrupts and then simply do the
>polling of available/free bytes in FIFO.
> 2. The block mode is not working properly since no handling in
>being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ.
> 
> Because of above, i2c v1 transfers of size greater than 32 are failing
> with following error message
> 
>   i2c_qup 78b6000.i2c: timeout for fifo out full
> 
> To make block mode working properly and move to use the interrupts
> instead of polling, major code reorganization is required. Following
> are the major changes done in this patch
> 
> 1. Remove the polling of TX FIFO free space and RX FIFO available
>bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE,
>QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ
>interrupts to handle FIFO’s properly so check all these interrupts.
> 2. During write, For FIFO mode, TX FIFO can be directly written
>without checking for FIFO space. For block mode, the QUP will generate
>OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available
>space.
> 3. During read, both TX and RX FIFO will be used. TX will be used
>for writing tags and RX will be used for receiving the data. In QUP,
>TX and RX can operate in separate mode so configure modes accordingly.
> 4. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which
>will be generated after all the bytes have been copied in RX FIFO. For
>read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts
>whenever it has block size of available data.
> 
> Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
> ---
> 

Reviewed-by: Sricharan R <sricha...@codeaurora.org>

Regards,
 Sricharan



> * Changes from v1:
> 
> 1. Fixed auto build test WARNING ‘idx' may be used uninitialized
>in this function
> 2. Removed event-based completion and changed transfer completion
>detection logic in interrupt handler
> 
>  drivers/i2c/busses/i2c-qup.c | 368 
> ++-
>  1 file changed, 224 insertions(+), 144 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
> index 4ebd922..3bf3c34 100644
> --- a/drivers/i2c/busses/i2c-qup.c
> +++ b/drivers/i2c/busses/i2c-qup.c
> @@ -64,8 +64,11 @@
>  #define QUP_IN_SVC_FLAG  BIT(9)
>  #define QUP_MX_OUTPUT_DONE   BIT(10)
>  #define QUP_MX_INPUT_DONEBIT(11)
> +#define OUT_BLOCK_WRITE_REQ  BIT(12)
> +#define IN_BLOCK_READ_REQBIT(13)
>  
>  /* I2C mini core related values */
> +#define QUP_NO_INPUT BIT(7)
>  #define QUP_CLOCK_AUTO_GATE  BIT(13)
>  #define I2C_MINI_CORE(2 << 8)
>  #define I2C_N_VAL15
> @@ -137,13 +140,36 @@
>  #define DEFAULT_CLK_FREQ 10
>  #define DEFAULT_SRC_CLK 2000
>  
> +/*
> + * count: no of blocks
> + * pos: current block number
> + * tx_tag_len: tx tag length for current block
> + * rx_tag_len: rx tag length for current block
> + * data_len: remaining data length for current message
> + * total_tx_len: total tx length including tag bytes for current QUP transfer
> + * total_rx_len: total rx length including tag bytes for current QUP transfer
> + * tx_fifo_free: number of free bytes in current QUP block write.
> + * fifo_available: number of available bytes in RX FIFO for current
> + *  QUP block read
> + * rx_bytes_read: if all the bytes have been read from rx FIFO.
> + * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM 
> xfer.
> + * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM 
> xfer.
> + * tags: contains tx tag bytes for current QUP transfer
> + */
>  struct qup_i2c_block {
> - int count;
> - int pos;
> - int tx_tag_len;
> - int rx_tag_len;
> - int data_len;
> - u8  tags[6];
> + int count;
> + int pos;
> + int tx_tag_len;
> + int rx_tag_len;
> + int data_len;
> + int total_tx_len;
> + int total_rx_len;
> + int tx_fifo_free;
> + int fifo_available;
> + boolrx_bytes_read;
> + boolis_tx_blk_mode;
> + boolis_rx_blk_mode;
> + u8  tags[6];
>  };
>  
>  struct qup_i2c_tag {
> @@ -186,6 +212,7 @@ struct qup_i2c_dev {
>  
>   /* To check if this is the last msg */
>   bo

Re: [PATCH v2 12/13] i2c: qup: reorganization of driver code to remove polling for qup v1

[Sricharan R]

Hi Abhishek,

On 3/12/2018 6:45 PM, Abhishek Sahu wrote:
> Following are the major issues in current driver code
> 
> 1. The current driver simply assumes the transfer completion
>whenever its gets any non-error interrupts and then simply do the
>polling of available/free bytes in FIFO.
> 2. The block mode is not working properly since no handling in
>being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ.
> 
> Because of above, i2c v1 transfers of size greater than 32 are failing
> with following error message
> 
>   i2c_qup 78b6000.i2c: timeout for fifo out full
> 
> To make block mode working properly and move to use the interrupts
> instead of polling, major code reorganization is required. Following
> are the major changes done in this patch
> 
> 1. Remove the polling of TX FIFO free space and RX FIFO available
>bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE,
>QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ
>interrupts to handle FIFO’s properly so check all these interrupts.
> 2. During write, For FIFO mode, TX FIFO can be directly written
>without checking for FIFO space. For block mode, the QUP will generate
>OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available
>space.
> 3. During read, both TX and RX FIFO will be used. TX will be used
>for writing tags and RX will be used for receiving the data. In QUP,
>TX and RX can operate in separate mode so configure modes accordingly.
> 4. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which
>will be generated after all the bytes have been copied in RX FIFO. For
>read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts
>whenever it has block size of available data.
> 
> Signed-off-by: Abhishek Sahu 
> ---
> 

Reviewed-by: Sricharan R 

Regards,
 Sricharan



> * Changes from v1:
> 
> 1. Fixed auto build test WARNING ‘idx' may be used uninitialized
>in this function
> 2. Removed event-based completion and changed transfer completion
>detection logic in interrupt handler
> 
>  drivers/i2c/busses/i2c-qup.c | 368 
> ++-
>  1 file changed, 224 insertions(+), 144 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
> index 4ebd922..3bf3c34 100644
> --- a/drivers/i2c/busses/i2c-qup.c
> +++ b/drivers/i2c/busses/i2c-qup.c
> @@ -64,8 +64,11 @@
>  #define QUP_IN_SVC_FLAG  BIT(9)
>  #define QUP_MX_OUTPUT_DONE   BIT(10)
>  #define QUP_MX_INPUT_DONEBIT(11)
> +#define OUT_BLOCK_WRITE_REQ  BIT(12)
> +#define IN_BLOCK_READ_REQBIT(13)
>  
>  /* I2C mini core related values */
> +#define QUP_NO_INPUT BIT(7)
>  #define QUP_CLOCK_AUTO_GATE  BIT(13)
>  #define I2C_MINI_CORE(2 << 8)
>  #define I2C_N_VAL15
> @@ -137,13 +140,36 @@
>  #define DEFAULT_CLK_FREQ 10
>  #define DEFAULT_SRC_CLK 2000
>  
> +/*
> + * count: no of blocks
> + * pos: current block number
> + * tx_tag_len: tx tag length for current block
> + * rx_tag_len: rx tag length for current block
> + * data_len: remaining data length for current message
> + * total_tx_len: total tx length including tag bytes for current QUP transfer
> + * total_rx_len: total rx length including tag bytes for current QUP transfer
> + * tx_fifo_free: number of free bytes in current QUP block write.
> + * fifo_available: number of available bytes in RX FIFO for current
> + *  QUP block read
> + * rx_bytes_read: if all the bytes have been read from rx FIFO.
> + * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM 
> xfer.
> + * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM 
> xfer.
> + * tags: contains tx tag bytes for current QUP transfer
> + */
>  struct qup_i2c_block {
> - int count;
> - int pos;
> - int tx_tag_len;
> - int rx_tag_len;
> - int data_len;
> - u8  tags[6];
> + int count;
> + int pos;
> + int tx_tag_len;
> + int rx_tag_len;
> + int data_len;
> + int total_tx_len;
> + int total_rx_len;
> + int tx_fifo_free;
> + int fifo_available;
> + boolrx_bytes_read;
> + boolis_tx_blk_mode;
> + boolis_rx_blk_mode;
> + u8  tags[6];
>  };
>  
>  struct qup_i2c_tag {
> @@ -186,6 +212,7 @@ struct qup_i2c_dev {
>  
>   /* To check if this is the last msg */
>   boolis_last;
> + bool  

[PATCH v9 02/15] clk: mux: Split out register accessors for reuse

[Sricharan R]

From: Stephen Boyd <sb...@codeaurora.org>

We want to reuse the logic in clk-mux.c for other clock drivers
that don't use readl as register accessors. Fortunately, there
really isn't much to the mux code besides the table indirection
and quirk flags if you assume any bit shifting and masking has
been done already. Pull that logic out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.

[Sricharan: Rebased for mainline]
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
---
 drivers/clk/clk-mux.c | 74 +++
 drivers/clk/nxp/clk-lpc32xx.c | 21 +++-
 include/linux/clk-provider.h  |  6 
 3 files changed, 57 insertions(+), 44 deletions(-)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 39cabe1..28223fa 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -26,35 +26,25 @@
  * parent - parent is adjustable through clk_set_parent
  */
 
-static u8 clk_mux_get_parent(struct clk_hw *hw)
+unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
+   unsigned int *table,
+   unsigned long flags)
 {
-   struct clk_mux *mux = to_clk_mux(hw);
int num_parents = clk_hw_get_num_parents(hw);
-   u32 val;
-
-   /*
-* FIXME need a mux-specific flag to determine if val is bitwise or 
numeric
-* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
-* to 0x7 (index starts at one)
-* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
-* val = 0x4 really means "bit 2, index starts at bit 0"
-*/
-   val = clk_readl(mux->reg) >> mux->shift;
-   val &= mux->mask;
 
-   if (mux->table) {
+   if (table) {
int i;
 
for (i = 0; i < num_parents; i++)
-   if (mux->table[i] == val)
+   if (table[i] == val)
return i;
return -EINVAL;
}
 
-   if (val && (mux->flags & CLK_MUX_INDEX_BIT))
+   if (val && (flags & CLK_MUX_INDEX_BIT))
val = ffs(val) - 1;
 
-   if (val && (mux->flags & CLK_MUX_INDEX_ONE))
+   if (val && (flags & CLK_MUX_INDEX_ONE))
val--;
 
if (val >= num_parents)
@@ -62,23 +52,53 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
 
return val;
 }
+EXPORT_SYMBOL_GPL(clk_mux_get_parent);
 
-static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
+static u8 _clk_mux_get_parent(struct clk_hw *hw)
 {
struct clk_mux *mux = to_clk_mux(hw);
u32 val;
-   unsigned long flags = 0;
 
-   if (mux->table) {
-   index = mux->table[index];
+   /*
+* FIXME need a mux-specific flag to determine if val is bitwise or
+* numeric e.g. sys_clkin_ck's clksel field is 3 bits wide,
+* but ranges from 0x1 to 0x7 (index starts at one)
+* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
+* val = 0x4 really means "bit 2, index starts at bit 0"
+*/
+   val = clk_readl(mux->reg) >> mux->shift;
+   val &= mux->mask;
+
+   return clk_mux_get_parent(hw, val, mux->table, mux->flags);
+}
+
+unsigned int clk_mux_reindex(u8 index, unsigned int *table,
+unsigned long flags)
+{
+   unsigned int val = index;
+
+   if (table) {
+   val = table[val];
} else {
-   if (mux->flags & CLK_MUX_INDEX_BIT)
-   index = 1 << index;
+   if (flags & CLK_MUX_INDEX_BIT)
+   val = 1 << index;
 
-   if (mux->flags & CLK_MUX_INDEX_ONE)
-   index++;
+   if (flags & CLK_MUX_INDEX_ONE)
+   val++;
}
 
+   return val;
+}
+EXPORT_SYMBOL_GPL(clk_mux_reindex);
+
+static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_mux *mux = to_clk_mux(hw);
+   u32 val;
+   unsigned long flags = 0;
+
+   index = clk_mux_reindex(index, mux->table, mux->flags);
+
if (mux->lock)
spin_lock_irqsave(mux->lock, flags);
else
@@ -102,14 +122,14 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 }
 
 const struct clk_ops clk_mux_ops = {
-   .get_parent = clk_mux_get_parent,
+   .get_parent = _clk_mux_get_parent,
.set_parent = clk_mux_set_parent,
.determine_rate = __clk_mux_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
 const struct clk_ops clk_mux_ro_ops = {
-   .get_parent = clk_mux_get_parent,
+   .get_parent = _clk_mux_

[PATCH v9 02/15] clk: mux: Split out register accessors for reuse

[Sricharan R]

From: Stephen Boyd 

We want to reuse the logic in clk-mux.c for other clock drivers
that don't use readl as register accessors. Fortunately, there
really isn't much to the mux code besides the table indirection
and quirk flags if you assume any bit shifting and masking has
been done already. Pull that logic out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.

[Sricharan: Rebased for mainline]
Signed-off-by: Sricharan R 
Signed-off-by: Stephen Boyd 
---
 drivers/clk/clk-mux.c | 74 +++
 drivers/clk/nxp/clk-lpc32xx.c | 21 +++-
 include/linux/clk-provider.h  |  6 
 3 files changed, 57 insertions(+), 44 deletions(-)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 39cabe1..28223fa 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -26,35 +26,25 @@
  * parent - parent is adjustable through clk_set_parent
  */
 
-static u8 clk_mux_get_parent(struct clk_hw *hw)
+unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
+   unsigned int *table,
+   unsigned long flags)
 {
-   struct clk_mux *mux = to_clk_mux(hw);
int num_parents = clk_hw_get_num_parents(hw);
-   u32 val;
-
-   /*
-* FIXME need a mux-specific flag to determine if val is bitwise or 
numeric
-* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
-* to 0x7 (index starts at one)
-* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
-* val = 0x4 really means "bit 2, index starts at bit 0"
-*/
-   val = clk_readl(mux->reg) >> mux->shift;
-   val &= mux->mask;
 
-   if (mux->table) {
+   if (table) {
int i;
 
for (i = 0; i < num_parents; i++)
-   if (mux->table[i] == val)
+   if (table[i] == val)
return i;
return -EINVAL;
}
 
-   if (val && (mux->flags & CLK_MUX_INDEX_BIT))
+   if (val && (flags & CLK_MUX_INDEX_BIT))
val = ffs(val) - 1;
 
-   if (val && (mux->flags & CLK_MUX_INDEX_ONE))
+   if (val && (flags & CLK_MUX_INDEX_ONE))
val--;
 
if (val >= num_parents)
@@ -62,23 +52,53 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
 
return val;
 }
+EXPORT_SYMBOL_GPL(clk_mux_get_parent);
 
-static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
+static u8 _clk_mux_get_parent(struct clk_hw *hw)
 {
struct clk_mux *mux = to_clk_mux(hw);
u32 val;
-   unsigned long flags = 0;
 
-   if (mux->table) {
-   index = mux->table[index];
+   /*
+* FIXME need a mux-specific flag to determine if val is bitwise or
+* numeric e.g. sys_clkin_ck's clksel field is 3 bits wide,
+* but ranges from 0x1 to 0x7 (index starts at one)
+* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
+* val = 0x4 really means "bit 2, index starts at bit 0"
+*/
+   val = clk_readl(mux->reg) >> mux->shift;
+   val &= mux->mask;
+
+   return clk_mux_get_parent(hw, val, mux->table, mux->flags);
+}
+
+unsigned int clk_mux_reindex(u8 index, unsigned int *table,
+unsigned long flags)
+{
+   unsigned int val = index;
+
+   if (table) {
+   val = table[val];
} else {
-   if (mux->flags & CLK_MUX_INDEX_BIT)
-   index = 1 << index;
+   if (flags & CLK_MUX_INDEX_BIT)
+   val = 1 << index;
 
-   if (mux->flags & CLK_MUX_INDEX_ONE)
-   index++;
+   if (flags & CLK_MUX_INDEX_ONE)
+   val++;
}
 
+   return val;
+}
+EXPORT_SYMBOL_GPL(clk_mux_reindex);
+
+static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_mux *mux = to_clk_mux(hw);
+   u32 val;
+   unsigned long flags = 0;
+
+   index = clk_mux_reindex(index, mux->table, mux->flags);
+
if (mux->lock)
spin_lock_irqsave(mux->lock, flags);
else
@@ -102,14 +122,14 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 }
 
 const struct clk_ops clk_mux_ops = {
-   .get_parent = clk_mux_get_parent,
+   .get_parent = _clk_mux_get_parent,
.set_parent = clk_mux_set_parent,
.determine_rate = __clk_mux_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
 const struct clk_ops clk_mux_ro_ops = {
-   .get_parent = clk_mux_get_parent,
+   .get_parent = _clk_mux_get_parent,
 };
 EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
 
diff --git a/drivers/clk/nx

[PATCH v9 05/15] dt-bindings: clock: Document qcom,hfpll

[Sricharan R]

From: Stephen Boyd 

Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.

Reviewed-by: Rob Herring 
Signed-off-by: Stephen Boyd 
---
 .../devicetree/bindings/clock/qcom,hfpll.txt   | 46 ++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt

diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt 
b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
new file mode 100644
index 000..771cb0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
@@ -0,0 +1,46 @@
+High-Frequency PLL (HFPLL)
+
+PROPERTIES
+
+- compatible:
+   Usage: required
+   Value type: :
+   shall contain only one of the following. The generic
+   compatible "qcom,hfpll" should be also included.
+
+"qcom,hfpll-ipq8064", "qcom,hfpll"
+"qcom,hfpll-apq8064", "qcom,hfpll"
+"qcom,hfpll-msm8974", "qcom,hfpll"
+"qcom,hfpll-msm8960", "qcom,hfpll"
+
+- reg:
+   Usage: required
+   Value type: 
+   Definition: address and size of HPLL registers. An optional second
+   element specifies the address and size of the alias
+   register region.
+
+- clock-output-names:
+   Usage: required
+   Value type: 
+   Definition: Name of the PLL. Typically hfpllX where X is a CPU number
+   starting at 0. Otherwise hfpll_Y where Y is more specific
+   such as "l2".
+
+Example:
+
+1) An HFPLL for the L2 cache.
+
+   clock-controller@f9016000 {
+   compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+   reg = <0xf9016000 0x30>;
+   clock-output-names = "hfpll_l2";
+   };
+
+2) An HFPLL for CPU0. This HFPLL has the alias register region.
+
+   clock-controller@f908a000 {
+   compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+   reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
+   clock-output-names = "hfpll0";
+   };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 05/15] dt-bindings: clock: Document qcom,hfpll

[Sricharan R]

From: Stephen Boyd 

Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.

Reviewed-by: Rob Herring 
Signed-off-by: Stephen Boyd 
---
 .../devicetree/bindings/clock/qcom,hfpll.txt   | 46 ++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt

diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt 
b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
new file mode 100644
index 000..771cb0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
@@ -0,0 +1,46 @@
+High-Frequency PLL (HFPLL)
+
+PROPERTIES
+
+- compatible:
+   Usage: required
+   Value type: :
+   shall contain only one of the following. The generic
+   compatible "qcom,hfpll" should be also included.
+
+"qcom,hfpll-ipq8064", "qcom,hfpll"
+"qcom,hfpll-apq8064", "qcom,hfpll"
+"qcom,hfpll-msm8974", "qcom,hfpll"
+"qcom,hfpll-msm8960", "qcom,hfpll"
+
+- reg:
+   Usage: required
+   Value type: 
+   Definition: address and size of HPLL registers. An optional second
+   element specifies the address and size of the alias
+   register region.
+
+- clock-output-names:
+   Usage: required
+   Value type: 
+   Definition: Name of the PLL. Typically hfpllX where X is a CPU number
+   starting at 0. Otherwise hfpll_Y where Y is more specific
+   such as "l2".
+
+Example:
+
+1) An HFPLL for the L2 cache.
+
+   clock-controller@f9016000 {
+   compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+   reg = <0xf9016000 0x30>;
+   clock-output-names = "hfpll_l2";
+   };
+
+2) An HFPLL for CPU0. This HFPLL has the alias register region.
+
+   clock-controller@f908a000 {
+   compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+   reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
+   clock-output-names = "hfpll0";
+   };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 09/15] clk: qcom: Add KPSS ACC/GCC driver

[Sricharan R]

From: Stephen Boyd 

The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.

Cc: 
Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/Kconfig|  8 +
 drivers/clk/qcom/Makefile   |  1 +
 drivers/clk/qcom/kpss-xcc.c | 87 +
 3 files changed, 96 insertions(+)
 create mode 100644 drivers/clk/qcom/kpss-xcc.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index bf14f56..8fca65d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -235,6 +235,14 @@ config QCOM_HFPLL
  Say Y if you want to support CPU frequency scaling on devices
  such as MSM8974, APQ8084, etc.
 
+config KPSS_XCC
+   tristate "KPSS Clock Controller"
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the Krait ACC and GCC clock controllers. Say Y
+ if you want to support CPU frequency scaling on devices such
+ as MSM8960, APQ8064, etc.
+
 config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index e1e96f6..24e598a 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -40,4 +40,5 @@ obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
 obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c
new file mode 100644
index 000..8590b5e
--- /dev/null
+++ b/drivers/clk/qcom/kpss-xcc.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const char *aux_parents[] = {
+   "pll8_vote",
+   "pxo",
+};
+
+static unsigned int aux_parent_map[] = {
+   3,
+   0,
+};
+
+static const struct of_device_id kpss_xcc_match_table[] = {
+   { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
+   { .compatible = "qcom,kpss-gcc" },
+   {}
+};
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
+
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
+{
+   const struct of_device_id *id;
+   struct clk *clk;
+   struct resource *res;
+   void __iomem *base;
+   const char *name;
+
+   id = of_match_device(kpss_xcc_match_table, >dev);
+   if (!id)
+   return -ENODEV;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   base = devm_ioremap_resource(>dev, res);
+   if (IS_ERR(base))
+   return PTR_ERR(base);
+
+   if (id->data) {
+   if (of_property_read_string_index(pdev->dev.of_node,
+ "clock-output-names",
+ 0, ))
+   return -ENODEV;
+   base += 0x14;
+   } else {
+   name = "acpu_l2_aux";
+   base += 0x28;
+   }
+
+   clk = clk_register_mux_table(>dev, name, aux_parents,
+ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+0, aux_parent_map, NULL);
+
+   platform_set_drvdata(pdev, clk);
+
+   return PTR_ERR_OR_ZERO(clk);
+}
+
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
+{
+   clk_unregister_mux(platform_get_drvdata(pdev));
+   return 0;
+}
+
+static struct platform_driver kpss_xcc_driver = {
+   .probe = kpss_xcc_driver_probe,
+   .remove = kpss_xcc_driver_remove,
+   .driver = {
+   .name = "kpss-xcc",
+   .of_match_table = kpss_xcc_match_table,
+   },
+};
+module_platform_driver(kpss_xcc_driver);
+
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:kpss-xcc");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 06/15] clk: qcom: Add MSM8960/APQ8064's HFPLLs

[Sricharan R]

From: Stephen Boyd 

Describe the HFPLLs present on MSM8960 and APQ8064 devices.

Acked-by: Rob Herring  (bindings)
Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/gcc-msm8960.c   | 172 +++
 include/dt-bindings/clock/qcom,gcc-msm8960.h |   2 +
 2 files changed, 174 insertions(+)

diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index eb551c7..809f16a 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -30,6 +30,7 @@
 #include "clk-pll.h"
 #include "clk-rcg.h"
 #include "clk-branch.h"
+#include "clk-hfpll.h"
 #include "reset.h"
 
 static struct clk_pll pll3 = {
@@ -86,6 +87,164 @@
},
 };
 
+static struct hfpll_data hfpll0_data = {
+   .mode_reg = 0x3200,
+   .l_reg = 0x3208,
+   .m_reg = 0x320c,
+   .n_reg = 0x3210,
+   .config_reg = 0x3204,
+   .status_reg = 0x321c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3214,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll0",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_8064_data = {
+   .mode_reg = 0x3240,
+   .l_reg = 0x3248,
+   .m_reg = 0x324c,
+   .n_reg = 0x3250,
+   .config_reg = 0x3244,
+   .status_reg = 0x325c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3254,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll1_data = {
+   .mode_reg = 0x3300,
+   .l_reg = 0x3308,
+   .m_reg = 0x330c,
+   .n_reg = 0x3310,
+   .config_reg = 0x3304,
+   .status_reg = 0x331c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3314,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll1",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll2_data = {
+   .mode_reg = 0x3280,
+   .l_reg = 0x3288,
+   .m_reg = 0x328c,
+   .n_reg = 0x3290,
+   .config_reg = 0x3284,
+   .status_reg = 0x329c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3294,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll2 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll2",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
+};
+
+static struct hfpll_data hfpll3_data = {
+   .mode_reg = 0x32c0,
+   .l_reg = 0x32c8,
+   .m_reg = 0x32cc,
+   .n_reg = 0x32d0,
+   .config_reg = 0x32c4,
+   .status_reg = 0x32dc,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x32d4,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll3 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll3",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
+};
+
+static struct hfpll_data hfpll_l2_8064_data = {
+   .mode_reg = 0x3300,
+   .l_reg = 0x3308,
+   .m_reg = 0x330c,
+   .n_reg = 0x3310,
+   .config_reg = 0x3304,
+   .status_reg = 0x331c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3314,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll_l2_data = {
+   .mode_reg = 0x3400,
+   .l_reg = 0x3408,
+   .m_reg = 0x340c,
+   .n_reg = 0x3410,
+   .config_reg = 0x3404,
+   .status_reg = 0x341c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3414,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+   .d = _l2_data,
+   .clkr.hw.init = 

[PATCH v9 09/15] clk: qcom: Add KPSS ACC/GCC driver

[Sricharan R]

From: Stephen Boyd 

The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.

Cc: 
Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/Kconfig|  8 +
 drivers/clk/qcom/Makefile   |  1 +
 drivers/clk/qcom/kpss-xcc.c | 87 +
 3 files changed, 96 insertions(+)
 create mode 100644 drivers/clk/qcom/kpss-xcc.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index bf14f56..8fca65d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -235,6 +235,14 @@ config QCOM_HFPLL
  Say Y if you want to support CPU frequency scaling on devices
  such as MSM8974, APQ8084, etc.
 
+config KPSS_XCC
+   tristate "KPSS Clock Controller"
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the Krait ACC and GCC clock controllers. Say Y
+ if you want to support CPU frequency scaling on devices such
+ as MSM8960, APQ8064, etc.
+
 config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index e1e96f6..24e598a 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -40,4 +40,5 @@ obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
 obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c
new file mode 100644
index 000..8590b5e
--- /dev/null
+++ b/drivers/clk/qcom/kpss-xcc.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const char *aux_parents[] = {
+   "pll8_vote",
+   "pxo",
+};
+
+static unsigned int aux_parent_map[] = {
+   3,
+   0,
+};
+
+static const struct of_device_id kpss_xcc_match_table[] = {
+   { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
+   { .compatible = "qcom,kpss-gcc" },
+   {}
+};
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
+
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
+{
+   const struct of_device_id *id;
+   struct clk *clk;
+   struct resource *res;
+   void __iomem *base;
+   const char *name;
+
+   id = of_match_device(kpss_xcc_match_table, >dev);
+   if (!id)
+   return -ENODEV;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   base = devm_ioremap_resource(>dev, res);
+   if (IS_ERR(base))
+   return PTR_ERR(base);
+
+   if (id->data) {
+   if (of_property_read_string_index(pdev->dev.of_node,
+ "clock-output-names",
+ 0, ))
+   return -ENODEV;
+   base += 0x14;
+   } else {
+   name = "acpu_l2_aux";
+   base += 0x28;
+   }
+
+   clk = clk_register_mux_table(>dev, name, aux_parents,
+ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+0, aux_parent_map, NULL);
+
+   platform_set_drvdata(pdev, clk);
+
+   return PTR_ERR_OR_ZERO(clk);
+}
+
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
+{
+   clk_unregister_mux(platform_get_drvdata(pdev));
+   return 0;
+}
+
+static struct platform_driver kpss_xcc_driver = {
+   .probe = kpss_xcc_driver_probe,
+   .remove = kpss_xcc_driver_remove,
+   .driver = {
+   .name = "kpss-xcc",
+   .of_match_table = kpss_xcc_match_table,
+   },
+};
+module_platform_driver(kpss_xcc_driver);
+
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:kpss-xcc");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 06/15] clk: qcom: Add MSM8960/APQ8064's HFPLLs

[Sricharan R]

From: Stephen Boyd 

Describe the HFPLLs present on MSM8960 and APQ8064 devices.

Acked-by: Rob Herring  (bindings)
Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/gcc-msm8960.c   | 172 +++
 include/dt-bindings/clock/qcom,gcc-msm8960.h |   2 +
 2 files changed, 174 insertions(+)

diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index eb551c7..809f16a 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -30,6 +30,7 @@
 #include "clk-pll.h"
 #include "clk-rcg.h"
 #include "clk-branch.h"
+#include "clk-hfpll.h"
 #include "reset.h"
 
 static struct clk_pll pll3 = {
@@ -86,6 +87,164 @@
},
 };
 
+static struct hfpll_data hfpll0_data = {
+   .mode_reg = 0x3200,
+   .l_reg = 0x3208,
+   .m_reg = 0x320c,
+   .n_reg = 0x3210,
+   .config_reg = 0x3204,
+   .status_reg = 0x321c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3214,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll0",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_8064_data = {
+   .mode_reg = 0x3240,
+   .l_reg = 0x3248,
+   .m_reg = 0x324c,
+   .n_reg = 0x3250,
+   .config_reg = 0x3244,
+   .status_reg = 0x325c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3254,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll1_data = {
+   .mode_reg = 0x3300,
+   .l_reg = 0x3308,
+   .m_reg = 0x330c,
+   .n_reg = 0x3310,
+   .config_reg = 0x3304,
+   .status_reg = 0x331c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3314,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll1",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll2_data = {
+   .mode_reg = 0x3280,
+   .l_reg = 0x3288,
+   .m_reg = 0x328c,
+   .n_reg = 0x3290,
+   .config_reg = 0x3284,
+   .status_reg = 0x329c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3294,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll2 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll2",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
+};
+
+static struct hfpll_data hfpll3_data = {
+   .mode_reg = 0x32c0,
+   .l_reg = 0x32c8,
+   .m_reg = 0x32cc,
+   .n_reg = 0x32d0,
+   .config_reg = 0x32c4,
+   .status_reg = 0x32dc,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x32d4,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll3 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll3",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
+};
+
+static struct hfpll_data hfpll_l2_8064_data = {
+   .mode_reg = 0x3300,
+   .l_reg = 0x3308,
+   .m_reg = 0x330c,
+   .n_reg = 0x3310,
+   .config_reg = 0x3304,
+   .status_reg = 0x331c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3314,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct hfpll_data hfpll_l2_data = {
+   .mode_reg = 0x3400,
+   .l_reg = 0x3408,
+   .m_reg = 0x340c,
+   .n_reg = 0x3410,
+   .config_reg = 0x3404,
+   .status_reg = 0x341c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3414,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+   .d = _l2_data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = 

[PATCH v9 14/15] cpufreq: Add module to register cpufreq on Krait CPUs

[Sricharan R]

From: Stephen Boyd <sb...@codeaurora.org>

Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.

Acked-by: Viresh Kumar <viresh.ku...@linaro.org>
[Sricharan: updated to use dev_pm_opp_set_prop_name and
nvmem apis]
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
---
 drivers/cpufreq/Kconfig.arm  |  10 ++
 drivers/cpufreq/Makefile |   1 +
 drivers/cpufreq/cpufreq-dt-platdev.c |   5 +
 drivers/cpufreq/qcom-cpufreq.c   | 183 +++
 4 files changed, 199 insertions(+)
 create mode 100644 drivers/cpufreq/qcom-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 3a88e33..826f9e7 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -133,6 +133,16 @@ config ARM_OMAP2PLUS_CPUFREQ
depends on ARCH_OMAP2PLUS
default ARCH_OMAP2PLUS
 
+config ARM_QCOM_CPUFREQ
+   bool "CPUfreq driver for the QCOM SoCs with KRAIT processors"
+   depends on ARCH_QCOM
+   select PM_OPP
+   help
+ This enables the CPUFreq driver for Qualcomm SoCs with
+ KRAIT processors.
+
+ If in doubt, say N.
+
 config ARM_S3C_CPUFREQ
bool
help
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index c60c1e1..1ca3390 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7)   += mvebu-cpufreq.o
 obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)+= omap-cpufreq.o
 obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)   += pxa2xx-cpufreq.o
 obj-$(CONFIG_PXA3xx)   += pxa3xx-cpufreq.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ) += qcom-cpufreq.o
 obj-$(CONFIG_ARM_S3C2410_CPUFREQ)  += s3c2410-cpufreq.o
 obj-$(CONFIG_ARM_S3C2412_CPUFREQ)  += s3c2412-cpufreq.o
 obj-$(CONFIG_ARM_S3C2416_CPUFREQ)  += s3c2416-cpufreq.o
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 3b585e4..e2e9a99 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -127,6 +127,11 @@
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
 
+   { .compatible = "qcom,ipq8064", },
+   { .compatible = "qcom,apq8064", },
+   { .compatible = "qcom,msm8974", },
+   { .compatible = "qcom,msm8960", },
+
{ }
 };
 
diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
new file mode 100644
index 000..6d71a3c
--- /dev/null
+++ b/drivers/cpufreq/qcom-cpufreq.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+   u32 pte_efuse;
+
+   pte_efuse = *((u32 *)buf);
+
+   *speed = pte_efuse & 0xf;
+   if (*speed == 0xf)
+   *speed = (pte_efuse >> 4) & 0xf;
+
+   if (*speed == 0xf) {
+   *speed = 0;
+   pr_warn("Speed bin: Defaulting to %d\n", *speed);
+   } else {
+   pr_info("Speed bin: %d\n", *speed);
+   }
+
+   *pvs = (pte_efuse >> 10) & 0x7;
+   if (*pvs == 0x7)
+   *pvs = (pte_efuse >> 13) & 0x7;
+
+   if (*pvs == 0x7) {
+   *pvs = 0;
+   pr_warn("PVS bin: Defaulting to %d\n", *pvs);
+   } else {
+   pr_info("PVS bin: %d\n", *pvs);
+   }
+
+   kfree(buf);
+}
+
+static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+   u32 pte_efuse, redundant_sel;
+
+   pte_efuse = *((u32 *)buf);
+   redundant_sel = (pte_efuse >> 24) & 0x7;
+   *speed = pte_efuse & 0x7;
+
+   /* 4 bits of PVS are in efuse register bits 31, 8-6. */
+   *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+   *pvs_ver = (pte_efuse >> 4) & 0x3;
+
+   switch (redundant_sel) {
+   case 1:
+   *speed = (pte_efuse >> 27) & 0xf;
+   break;
+   case 2:
+   *pvs = (pte_efuse >> 27) & 0xf;
+   break;
+   }
+
+   /* Check SPEED_BIN_BLOW_STATUS */
+   if (pte_efuse & BIT(3)) {
+   pr_info("Speed bin: %d\n", *speed);
+   } else {
+   pr_warn("Speed bin not set. Defaulting to 0!\n");
+   *speed = 0;
+   }
+
+   /* Check PVS_BLOW_STATUS */
+

[PATCH v9 14/15] cpufreq: Add module to register cpufreq on Krait CPUs

[Sricharan R]

From: Stephen Boyd 

Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.

Acked-by: Viresh Kumar 
[Sricharan: updated to use dev_pm_opp_set_prop_name and
nvmem apis]
Signed-off-by: Sricharan R 
Signed-off-by: Stephen Boyd 
---
 drivers/cpufreq/Kconfig.arm  |  10 ++
 drivers/cpufreq/Makefile |   1 +
 drivers/cpufreq/cpufreq-dt-platdev.c |   5 +
 drivers/cpufreq/qcom-cpufreq.c   | 183 +++
 4 files changed, 199 insertions(+)
 create mode 100644 drivers/cpufreq/qcom-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 3a88e33..826f9e7 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -133,6 +133,16 @@ config ARM_OMAP2PLUS_CPUFREQ
depends on ARCH_OMAP2PLUS
default ARCH_OMAP2PLUS
 
+config ARM_QCOM_CPUFREQ
+   bool "CPUfreq driver for the QCOM SoCs with KRAIT processors"
+   depends on ARCH_QCOM
+   select PM_OPP
+   help
+ This enables the CPUFreq driver for Qualcomm SoCs with
+ KRAIT processors.
+
+ If in doubt, say N.
+
 config ARM_S3C_CPUFREQ
bool
help
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index c60c1e1..1ca3390 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7)   += mvebu-cpufreq.o
 obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)+= omap-cpufreq.o
 obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)   += pxa2xx-cpufreq.o
 obj-$(CONFIG_PXA3xx)   += pxa3xx-cpufreq.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ) += qcom-cpufreq.o
 obj-$(CONFIG_ARM_S3C2410_CPUFREQ)  += s3c2410-cpufreq.o
 obj-$(CONFIG_ARM_S3C2412_CPUFREQ)  += s3c2412-cpufreq.o
 obj-$(CONFIG_ARM_S3C2416_CPUFREQ)  += s3c2416-cpufreq.o
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 3b585e4..e2e9a99 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -127,6 +127,11 @@
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
 
+   { .compatible = "qcom,ipq8064", },
+   { .compatible = "qcom,apq8064", },
+   { .compatible = "qcom,msm8974", },
+   { .compatible = "qcom,msm8960", },
+
{ }
 };
 
diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
new file mode 100644
index 000..6d71a3c
--- /dev/null
+++ b/drivers/cpufreq/qcom-cpufreq.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+   u32 pte_efuse;
+
+   pte_efuse = *((u32 *)buf);
+
+   *speed = pte_efuse & 0xf;
+   if (*speed == 0xf)
+   *speed = (pte_efuse >> 4) & 0xf;
+
+   if (*speed == 0xf) {
+   *speed = 0;
+   pr_warn("Speed bin: Defaulting to %d\n", *speed);
+   } else {
+   pr_info("Speed bin: %d\n", *speed);
+   }
+
+   *pvs = (pte_efuse >> 10) & 0x7;
+   if (*pvs == 0x7)
+   *pvs = (pte_efuse >> 13) & 0x7;
+
+   if (*pvs == 0x7) {
+   *pvs = 0;
+   pr_warn("PVS bin: Defaulting to %d\n", *pvs);
+   } else {
+   pr_info("PVS bin: %d\n", *pvs);
+   }
+
+   kfree(buf);
+}
+
+static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+   u32 pte_efuse, redundant_sel;
+
+   pte_efuse = *((u32 *)buf);
+   redundant_sel = (pte_efuse >> 24) & 0x7;
+   *speed = pte_efuse & 0x7;
+
+   /* 4 bits of PVS are in efuse register bits 31, 8-6. */
+   *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+   *pvs_ver = (pte_efuse >> 4) & 0x3;
+
+   switch (redundant_sel) {
+   case 1:
+   *speed = (pte_efuse >> 27) & 0xf;
+   break;
+   case 2:
+   *pvs = (pte_efuse >> 27) & 0xf;
+   break;
+   }
+
+   /* Check SPEED_BIN_BLOW_STATUS */
+   if (pte_efuse & BIT(3)) {
+   pr_info("Speed bin: %d\n", *speed);
+   } else {
+   pr_warn("Speed bin not set. Defaulting to 0!\n");
+   *speed = 0;
+   }
+
+   /* Check PVS_BLOW_STATUS */
+   pte_efuse = *(((u32 *)buf) + 4);
+   if (pte_efuse) {
+   pr_info("PVS bin: %d\n", *pvs);
+  

[PATCH v9 15/15] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu

[Sricharan R]

In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
operating-points-v2-krait-cpu specifies the phandle to nvmem efuse cells
and the operating-points-v2 table for each opp. The qcom-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.

Reviewed-by: Rob Herring <r...@kernel.org>
Acked-by: Viresh Kumar <viresh.ku...@linaro.org>
Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 .../devicetree/bindings/cpufreq/krait-cpufreq.txt  | 363 +
 1 file changed, 363 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt

diff --git a/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt 
b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
new file mode 100644
index 000..7b083c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
@@ -0,0 +1,363 @@
+QCOM KRAIT CPUFreq and OPP bindings
+===
+
+In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
+that has KRAIT processors the voltage value of each OPP varies
+based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
+defines the voltage and current value based on the speed/pvs/version
+combination blown in the efuse. The qcom-cpufreq driver reads the efuse
+value from the SoC to provide the OPP framework with required information.
+This is used to determine the voltage and current value for each OPP of
+operating-points-v2 table when it is parsed by the OPP framework.
+
+Required properties:
+
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+   - 'operating-points-v2-krait-cpu' for ipq8064, apq8064, msm8960,
+ msm8974.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+   efuse registers that has information about the
+   speedbin/pvs/version that is used to select the right
+   voltage/current value pair. Note that the length field of the
+   nvmem-cell is used to differentiate between format 'A' or 'B'
+   efuse settings. len of '4' bytes is for format 'A' and '8'
+   bytes for format 'B'. Please refer the for nvmem-cells
+   bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+   and also examples below for both the cases.
+Example 1:
+-
+
+/* For arch/arm/boot/dts/apq8064.dtsi --> format 'A' */
+cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   CPU0: cpu@0 {
+   compatible = "qcom,krait";
+   enable-method = "qcom,kpss-acc-v1";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   qcom,acc = <>;
+   qcom,saw = <>;
+   cpu-idle-states = <_SPC>;
+   operating-points-v2 = <_opp_table>;
+   };
+};
+
+qfprom: qfprom@70 {
+   compatible  = "qcom,qfprom";
+   reg   = <0x0070 0x1000>;
+   #address-cells  = <1>;
+   #size-cells = <1>;
+   ranges;
+   pvs_efuse: pvs {
+   reg = <0xc0 0x4>;
+   };
+};
+
+cpu_opp_table: opp-table {
+   compatible = "operating-points-v2-krait-cpu";
+   nvmem-cells = <_efuse>;
+
+   /*
+* Missing opp-shared property means CPUs switch DVFS states
+* independently.
+*/
+
+   opp-91800 {
+   opp-hz = /bits/ 64 <91800>;
+   opp-microvolt-speed0-pvs0-v0 = <110>;
+   opp-microvolt-speed0-pvs1-v0 = <105>;
+   opp-microvolt-speed0-pvs3-v0 = <100>;
+   opp-microvolt-speed0-pvs4-v0 = <975000>;
+   opp-microvolt-speed1-pvs0-v0 = <1025000>;
+   opp-microvolt-speed1-pvs1-v0 = <100>;
+   opp-microvolt-speed1-pvs2-v0 = <95>;
+   opp-microvolt-speed1-pvs3-v0 = <925000>;
+   opp-microvolt-speed1-pvs4-v0 = <90>;
+   opp-microvolt-speed1-pvs5-v0 = <90>;
+   opp-microvolt-speed1-pvs6-v0 = <90>;
+   opp-microvolt-speed2-pvs0-v0 = <975000>;
+   opp-microvolt-speed2-pvs1-v0 = <9

[PATCH v9 15/15] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu

[Sricharan R]

In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
operating-points-v2-krait-cpu specifies the phandle to nvmem efuse cells
and the operating-points-v2 table for each opp. The qcom-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.

Reviewed-by: Rob Herring 
Acked-by: Viresh Kumar 
Signed-off-by: Sricharan R 
---
 .../devicetree/bindings/cpufreq/krait-cpufreq.txt  | 363 +
 1 file changed, 363 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt

diff --git a/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt 
b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
new file mode 100644
index 000..7b083c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
@@ -0,0 +1,363 @@
+QCOM KRAIT CPUFreq and OPP bindings
+===
+
+In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
+that has KRAIT processors the voltage value of each OPP varies
+based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
+defines the voltage and current value based on the speed/pvs/version
+combination blown in the efuse. The qcom-cpufreq driver reads the efuse
+value from the SoC to provide the OPP framework with required information.
+This is used to determine the voltage and current value for each OPP of
+operating-points-v2 table when it is parsed by the OPP framework.
+
+Required properties:
+
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+   - 'operating-points-v2-krait-cpu' for ipq8064, apq8064, msm8960,
+ msm8974.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+   efuse registers that has information about the
+   speedbin/pvs/version that is used to select the right
+   voltage/current value pair. Note that the length field of the
+   nvmem-cell is used to differentiate between format 'A' or 'B'
+   efuse settings. len of '4' bytes is for format 'A' and '8'
+   bytes for format 'B'. Please refer the for nvmem-cells
+   bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+   and also examples below for both the cases.
+Example 1:
+-
+
+/* For arch/arm/boot/dts/apq8064.dtsi --> format 'A' */
+cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   CPU0: cpu@0 {
+   compatible = "qcom,krait";
+   enable-method = "qcom,kpss-acc-v1";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   qcom,acc = <>;
+   qcom,saw = <>;
+   cpu-idle-states = <_SPC>;
+   operating-points-v2 = <_opp_table>;
+   };
+};
+
+qfprom: qfprom@70 {
+   compatible  = "qcom,qfprom";
+   reg   = <0x0070 0x1000>;
+   #address-cells  = <1>;
+   #size-cells = <1>;
+   ranges;
+   pvs_efuse: pvs {
+   reg = <0xc0 0x4>;
+   };
+};
+
+cpu_opp_table: opp-table {
+   compatible = "operating-points-v2-krait-cpu";
+   nvmem-cells = <_efuse>;
+
+   /*
+* Missing opp-shared property means CPUs switch DVFS states
+* independently.
+*/
+
+   opp-91800 {
+   opp-hz = /bits/ 64 <91800>;
+   opp-microvolt-speed0-pvs0-v0 = <110>;
+   opp-microvolt-speed0-pvs1-v0 = <105>;
+   opp-microvolt-speed0-pvs3-v0 = <100>;
+   opp-microvolt-speed0-pvs4-v0 = <975000>;
+   opp-microvolt-speed1-pvs0-v0 = <1025000>;
+   opp-microvolt-speed1-pvs1-v0 = <100>;
+   opp-microvolt-speed1-pvs2-v0 = <95>;
+   opp-microvolt-speed1-pvs3-v0 = <925000>;
+   opp-microvolt-speed1-pvs4-v0 = <90>;
+   opp-microvolt-speed1-pvs5-v0 = <90>;
+   opp-microvolt-speed1-pvs6-v0 = <90>;
+   opp-microvolt-speed2-pvs0-v0 = <975000>;
+   opp-microvolt-speed2-pvs1-v0 = <95>;
+   opp-microvolt-speed2-pvs2-v0 = <925000>;
+  

[PATCH v9 13/15] clk: qcom: Add safe switch hook for krait mux clocks

[Sricharan R]

When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.

Signed-off-by: Sricharan R <sricha...@codeaurora.org>
---
 drivers/clk/qcom/clk-krait.c |  2 ++
 drivers/clk/qcom/clk-krait.h |  3 +++
 drivers/clk/qcom/krait-cc.c  | 56 
 3 files changed, 61 insertions(+)

diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 2e41767..ac2e020 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
if (__clk_is_enabled(hw->clk))
__krait_mux_set_sel(mux, sel);
 
+   mux->reparent = true;
+
return 0;
 }
 
diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h
index 71890bc..986f356 100644
--- a/drivers/clk/qcom/clk-krait.h
+++ b/drivers/clk/qcom/clk-krait.h
@@ -13,6 +13,9 @@ struct krait_mux_clk {
u32 shift;
u32 en_mask;
boollpl;
+   u8  safe_sel;
+   u8  old_index;
+   boolreparent;
 
struct clk_hw   hw;
struct notifier_block   clk_nb;
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 7c9dfb0..4d4b657 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -26,6 +26,49 @@
0,
 };
 
+/*
+ * Notifier function for switching the muxes to safe parent
+ * while the hfpll is getting reprogrammed.
+ */
+static int krait_notifier_cb(struct notifier_block *nb,
+unsigned long event,
+void *data)
+{
+   int ret = 0;
+   struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
+clk_nb);
+   /* Switch to safe parent */
+   if (event == PRE_RATE_CHANGE) {
+   mux->old_index = krait_mux_clk_ops.get_parent(>hw);
+   ret = krait_mux_clk_ops.set_parent(>hw, mux->safe_sel);
+   mux->reparent = false;
+   /*
+* By the time POST_RATE_CHANGE notifier is called,
+* clk framework itself would have changed the parent for the new rate.
+* Only otherwise, put back to the old parent.
+*/
+   } else if (event == POST_RATE_CHANGE) {
+   if (!mux->reparent)
+   ret = krait_mux_clk_ops.set_parent(>hw,
+  mux->old_index);
+   }
+
+   return notifier_from_errno(ret);
+}
+
+static int krait_notifier_register(struct device *dev, struct clk *clk,
+  struct krait_mux_clk *mux)
+{
+   int ret = 0;
+
+   mux->clk_nb.notifier_call = krait_notifier_cb;
+   ret = clk_notifier_register(clk, >clk_nb);
+   if (ret)
+   dev_err(dev, "failed to register clock notifier: %d\n", ret);
+
+   return ret;
+}
+
 static int
 krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
 {
@@ -70,6 +113,7 @@
 krait_add_sec_mux(struct device *dev, int id, const char *s,
  unsigned int offset, bool unique_aux)
 {
+   int ret;
struct krait_mux_clk *mux;
static const char *sec_mux_list[] = {
"acpu_aux",
@@ -93,6 +137,7 @@
mux->shift = 2;
mux->parent_map = sec_mux_map;
mux->hw.init = 
+   mux->safe_sel = 0;
 
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!init.name)
@@ -108,6 +153,11 @@
 
clk = devm_clk_register(dev, >hw);
 
+   ret = krait_notifier_register(dev, clk, mux);
+   if (ret)
+   goto unique_aux;
+
+unique_aux:
if (unique_aux)
kfree(sec_mux_list[0]);
 err_aux:
@@ -119,6 +169,7 @@
 krait_add_pri_mux(struct device *dev, int id, const char *s,
  unsigned int offset)
 {
+   int ret;
struct krait_mux_clk *mux;
const char *p_names[3];
struct clk_init_data init = {
@@ -139,6 +190,7 @@
mux->lpl = id >= 0;
mux->parent_map = pri_mux_map;
mux->hw.init = 
+   mux->safe_sel = 2;
 
init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
if (!init.name)
@@ -164,6 +216,10 @@
 
clk = devm_clk_register(dev, >hw);
 
+   ret = krait_notifier_register(dev, clk, mux);
+   if (ret)
+   goto err_p3;
+err_p3:
kfree(p_names[2]);
 err_p2:
kfree(p_names[1]);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 13/15] clk: qcom: Add safe switch hook for krait mux clocks

[Sricharan R]

When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.

Signed-off-by: Sricharan R 
---
 drivers/clk/qcom/clk-krait.c |  2 ++
 drivers/clk/qcom/clk-krait.h |  3 +++
 drivers/clk/qcom/krait-cc.c  | 56 
 3 files changed, 61 insertions(+)

diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 2e41767..ac2e020 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
if (__clk_is_enabled(hw->clk))
__krait_mux_set_sel(mux, sel);
 
+   mux->reparent = true;
+
return 0;
 }
 
diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h
index 71890bc..986f356 100644
--- a/drivers/clk/qcom/clk-krait.h
+++ b/drivers/clk/qcom/clk-krait.h
@@ -13,6 +13,9 @@ struct krait_mux_clk {
u32 shift;
u32 en_mask;
boollpl;
+   u8  safe_sel;
+   u8  old_index;
+   boolreparent;
 
struct clk_hw   hw;
struct notifier_block   clk_nb;
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 7c9dfb0..4d4b657 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -26,6 +26,49 @@
0,
 };
 
+/*
+ * Notifier function for switching the muxes to safe parent
+ * while the hfpll is getting reprogrammed.
+ */
+static int krait_notifier_cb(struct notifier_block *nb,
+unsigned long event,
+void *data)
+{
+   int ret = 0;
+   struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
+clk_nb);
+   /* Switch to safe parent */
+   if (event == PRE_RATE_CHANGE) {
+   mux->old_index = krait_mux_clk_ops.get_parent(>hw);
+   ret = krait_mux_clk_ops.set_parent(>hw, mux->safe_sel);
+   mux->reparent = false;
+   /*
+* By the time POST_RATE_CHANGE notifier is called,
+* clk framework itself would have changed the parent for the new rate.
+* Only otherwise, put back to the old parent.
+*/
+   } else if (event == POST_RATE_CHANGE) {
+   if (!mux->reparent)
+   ret = krait_mux_clk_ops.set_parent(>hw,
+  mux->old_index);
+   }
+
+   return notifier_from_errno(ret);
+}
+
+static int krait_notifier_register(struct device *dev, struct clk *clk,
+  struct krait_mux_clk *mux)
+{
+   int ret = 0;
+
+   mux->clk_nb.notifier_call = krait_notifier_cb;
+   ret = clk_notifier_register(clk, >clk_nb);
+   if (ret)
+   dev_err(dev, "failed to register clock notifier: %d\n", ret);
+
+   return ret;
+}
+
 static int
 krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
 {
@@ -70,6 +113,7 @@
 krait_add_sec_mux(struct device *dev, int id, const char *s,
  unsigned int offset, bool unique_aux)
 {
+   int ret;
struct krait_mux_clk *mux;
static const char *sec_mux_list[] = {
"acpu_aux",
@@ -93,6 +137,7 @@
mux->shift = 2;
mux->parent_map = sec_mux_map;
mux->hw.init = 
+   mux->safe_sel = 0;
 
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!init.name)
@@ -108,6 +153,11 @@
 
clk = devm_clk_register(dev, >hw);
 
+   ret = krait_notifier_register(dev, clk, mux);
+   if (ret)
+   goto unique_aux;
+
+unique_aux:
if (unique_aux)
kfree(sec_mux_list[0]);
 err_aux:
@@ -119,6 +169,7 @@
 krait_add_pri_mux(struct device *dev, int id, const char *s,
  unsigned int offset)
 {
+   int ret;
struct krait_mux_clk *mux;
const char *p_names[3];
struct clk_init_data init = {
@@ -139,6 +190,7 @@
mux->lpl = id >= 0;
mux->parent_map = pri_mux_map;
mux->hw.init = 
+   mux->safe_sel = 2;
 
init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
if (!init.name)
@@ -164,6 +216,10 @@
 
clk = devm_clk_register(dev, >hw);
 
+   ret = krait_notifier_register(dev, clk, mux);
+   if (ret)
+   goto err_p3;
+err_p3:
kfree(p_names[2]);
 err_p2:
kfree(p_names[1]);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 12/15] dt-bindings: clock: Document qcom,krait-cc

[Sricharan R]

From: Stephen Boyd 

The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.

Reviewed-by: Rob Herring 
Signed-off-by: Stephen Boyd 
---
 .../devicetree/bindings/clock/qcom,krait-cc.txt| 22 ++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt

diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt 
b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
new file mode 100644
index 000..874138f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
@@ -0,0 +1,22 @@
+Krait Clock Controller
+
+PROPERTIES
+
+- compatible:
+   Usage: required
+   Value type: 
+   Definition: must be one of:
+   "qcom,krait-cc-v1"
+   "qcom,krait-cc-v2"
+
+- #clock-cells:
+   Usage: required
+   Value type: 
+   Definition: must be 1
+
+Example:
+
+   kraitcc: clock-controller {
+   compatible = "qcom,krait-cc-v1";
+   #clock-cells = <1>;
+   };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 12/15] dt-bindings: clock: Document qcom,krait-cc

[Sricharan R]

From: Stephen Boyd 

The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.

Reviewed-by: Rob Herring 
Signed-off-by: Stephen Boyd 
---
 .../devicetree/bindings/clock/qcom,krait-cc.txt| 22 ++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt

diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt 
b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
new file mode 100644
index 000..874138f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
@@ -0,0 +1,22 @@
+Krait Clock Controller
+
+PROPERTIES
+
+- compatible:
+   Usage: required
+   Value type: 
+   Definition: must be one of:
+   "qcom,krait-cc-v1"
+   "qcom,krait-cc-v2"
+
+- #clock-cells:
+   Usage: required
+   Value type: 
+   Definition: must be 1
+
+Example:
+
+   kraitcc: clock-controller {
+   compatible = "qcom,krait-cc-v1";
+   #clock-cells = <1>;
+   };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 11/15] clk: qcom: Add Krait clock controller driver

[Sricharan R]

From: Stephen Boyd 

The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.

Cc: 
Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/Kconfig|   8 ++
 drivers/clk/qcom/Makefile   |   1 +
 drivers/clk/qcom/krait-cc.c | 341 
 3 files changed, 350 insertions(+)
 create mode 100644 drivers/clk/qcom/krait-cc.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8fca65d..73cb840 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,14 @@ config KPSS_XCC
  if you want to support CPU frequency scaling on devices such
  as MSM8960, APQ8064, etc.
 
+config KRAITCC
+   tristate "Krait Clock Controller"
+   depends on COMMON_CLK_QCOM && ARM
+   select KRAIT_CLOCKS
+   help
+ Support for the Krait CPU clocks on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling.
+
 config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 24e598a..cd99c7b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
+obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
new file mode 100644
index 000..7c9dfb0
--- /dev/null
+++ b/drivers/clk/qcom/krait-cc.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk-krait.h"
+
+static unsigned int sec_mux_map[] = {
+   2,
+   0,
+};
+
+static unsigned int pri_mux_map[] = {
+   1,
+   2,
+   0,
+};
+
+static int
+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+{
+   struct krait_div2_clk *div;
+   struct clk_init_data init = {
+   .num_parents = 1,
+   .ops = _div2_clk_ops,
+   .flags = CLK_SET_RATE_PARENT,
+   };
+   const char *p_names[1];
+   struct clk *clk;
+
+   div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+   if (!div)
+   return -ENOMEM;
+
+   div->width = 2;
+   div->shift = 6;
+   div->lpl = id >= 0;
+   div->offset = offset;
+   div->hw.init = 
+
+   init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+   if (!init.name)
+   return -ENOMEM;
+
+   init.parent_names = p_names;
+   p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+   if (!p_names[0]) {
+   kfree(init.name);
+   return -ENOMEM;
+   }
+
+   clk = devm_clk_register(dev, >hw);
+   kfree(p_names[0]);
+   kfree(init.name);
+
+   return PTR_ERR_OR_ZERO(clk);
+}
+
+static int
+krait_add_sec_mux(struct device *dev, int id, const char *s,
+ unsigned int offset, bool unique_aux)
+{
+   struct krait_mux_clk *mux;
+   static const char *sec_mux_list[] = {
+   "acpu_aux",
+   "qsb",
+   };
+   struct clk_init_data init = {
+   .parent_names = sec_mux_list,
+   .num_parents = ARRAY_SIZE(sec_mux_list),
+   .ops = _mux_clk_ops,
+   .flags = CLK_SET_RATE_PARENT,
+   };
+   struct clk *clk;
+
+   mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+   if (!mux)
+   return -ENOMEM;
+
+   mux->offset = offset;
+   mux->lpl = id >= 0;
+   mux->mask = 0x3;
+   mux->shift = 2;
+   mux->parent_map = sec_mux_map;
+   mux->hw.init = 
+
+   init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
+   if (!init.name)
+   return -ENOMEM;
+
+   if (unique_aux) {
+   sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
+   if (!sec_mux_list[0]) {
+   clk = ERR_PTR(-ENOMEM);
+   goto err_aux;
+   }
+   }
+
+   clk = devm_clk_register(dev, >hw);
+
+   if (unique_aux)
+   kfree(sec_mux_list[0]);
+err_aux:
+   kfree(init.name);
+   return PTR_ERR_OR_ZERO(clk);
+}
+
+static struct clk *
+krait_add_pri_mux(struct device *dev, int id, const char *s,
+ unsigned int offset)
+{
+   struct krait_mux_clk *mux;
+   const char *p_names[3];
+   struct clk_init_data init = {
+   .parent_names = p_names,
+   .num_parents = 

[PATCH v9 11/15] clk: qcom: Add Krait clock controller driver

[Sricharan R]

From: Stephen Boyd 

The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.

Cc: 
Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/Kconfig|   8 ++
 drivers/clk/qcom/Makefile   |   1 +
 drivers/clk/qcom/krait-cc.c | 341 
 3 files changed, 350 insertions(+)
 create mode 100644 drivers/clk/qcom/krait-cc.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8fca65d..73cb840 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,14 @@ config KPSS_XCC
  if you want to support CPU frequency scaling on devices such
  as MSM8960, APQ8064, etc.
 
+config KRAITCC
+   tristate "Krait Clock Controller"
+   depends on COMMON_CLK_QCOM && ARM
+   select KRAIT_CLOCKS
+   help
+ Support for the Krait CPU clocks on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling.
+
 config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 24e598a..cd99c7b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
+obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
new file mode 100644
index 000..7c9dfb0
--- /dev/null
+++ b/drivers/clk/qcom/krait-cc.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk-krait.h"
+
+static unsigned int sec_mux_map[] = {
+   2,
+   0,
+};
+
+static unsigned int pri_mux_map[] = {
+   1,
+   2,
+   0,
+};
+
+static int
+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+{
+   struct krait_div2_clk *div;
+   struct clk_init_data init = {
+   .num_parents = 1,
+   .ops = _div2_clk_ops,
+   .flags = CLK_SET_RATE_PARENT,
+   };
+   const char *p_names[1];
+   struct clk *clk;
+
+   div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+   if (!div)
+   return -ENOMEM;
+
+   div->width = 2;
+   div->shift = 6;
+   div->lpl = id >= 0;
+   div->offset = offset;
+   div->hw.init = 
+
+   init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+   if (!init.name)
+   return -ENOMEM;
+
+   init.parent_names = p_names;
+   p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+   if (!p_names[0]) {
+   kfree(init.name);
+   return -ENOMEM;
+   }
+
+   clk = devm_clk_register(dev, >hw);
+   kfree(p_names[0]);
+   kfree(init.name);
+
+   return PTR_ERR_OR_ZERO(clk);
+}
+
+static int
+krait_add_sec_mux(struct device *dev, int id, const char *s,
+ unsigned int offset, bool unique_aux)
+{
+   struct krait_mux_clk *mux;
+   static const char *sec_mux_list[] = {
+   "acpu_aux",
+   "qsb",
+   };
+   struct clk_init_data init = {
+   .parent_names = sec_mux_list,
+   .num_parents = ARRAY_SIZE(sec_mux_list),
+   .ops = _mux_clk_ops,
+   .flags = CLK_SET_RATE_PARENT,
+   };
+   struct clk *clk;
+
+   mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+   if (!mux)
+   return -ENOMEM;
+
+   mux->offset = offset;
+   mux->lpl = id >= 0;
+   mux->mask = 0x3;
+   mux->shift = 2;
+   mux->parent_map = sec_mux_map;
+   mux->hw.init = 
+
+   init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
+   if (!init.name)
+   return -ENOMEM;
+
+   if (unique_aux) {
+   sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
+   if (!sec_mux_list[0]) {
+   clk = ERR_PTR(-ENOMEM);
+   goto err_aux;
+   }
+   }
+
+   clk = devm_clk_register(dev, >hw);
+
+   if (unique_aux)
+   kfree(sec_mux_list[0]);
+err_aux:
+   kfree(init.name);
+   return PTR_ERR_OR_ZERO(clk);
+}
+
+static struct clk *
+krait_add_pri_mux(struct device *dev, int id, const char *s,
+ unsigned int offset)
+{
+   struct krait_mux_clk *mux;
+   const char *p_names[3];
+   struct clk_init_data init = {
+   .parent_names = p_names,
+   .num_parents = ARRAY_SIZE(p_names),
+   .ops = _mux_clk_ops,
+   

[PATCH v9 10/15] dt-bindings: arm: Document qcom,kpss-gcc

[Sricharan R]

From: Stephen Boyd 

The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.

Reviewed-by: Rob Herring 
Signed-off-by: Stephen Boyd 
---
 .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  7 +
 .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  | 32 ++
 2 files changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt 
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..382a574 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,17 @@ PROPERTIES
the register region. An optional second element specifies
the base address and size of the alias register region.
 
+- clock-output-names:
+   Usage: optional
+   Value type: 
+   Definition: Name of the output clock. Typically acpuX_aux where X is a
+   CPU number starting at 0.
+
 Example:
 
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
  <0x02008000 0x1000>;
+   clock-output-names = "acpu0_aux";
};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt 
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 000..37fc0a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,32 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+   Usage: required
+   Value type: 
+   Definition: should be one of the following. The generic compatible
+   "qcom,kpss-gcc" should also be included.
+   "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+   "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+   "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+   "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+   Usage: required
+   Value type: 
+   Definition: base address and size of the register region
+
+- clock-output-names:
+   Usage: required
+   Value type: 
+   Definition: Name of the output clock. Typically acpu_l2_aux indicating
+   an L2 cache auxiliary clock.
+
+Example:
+
+   l2cc: clock-controller@2011000 {
+   compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+   reg = <0x2011000 0x1000>;
+   clock-output-names = "acpu_l2_aux";
+   };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 10/15] dt-bindings: arm: Document qcom,kpss-gcc

[Sricharan R]

From: Stephen Boyd 

The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.

Reviewed-by: Rob Herring 
Signed-off-by: Stephen Boyd 
---
 .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  7 +
 .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  | 32 ++
 2 files changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt 
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..382a574 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,17 @@ PROPERTIES
the register region. An optional second element specifies
the base address and size of the alias register region.
 
+- clock-output-names:
+   Usage: optional
+   Value type: 
+   Definition: Name of the output clock. Typically acpuX_aux where X is a
+   CPU number starting at 0.
+
 Example:
 
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
  <0x02008000 0x1000>;
+   clock-output-names = "acpu0_aux";
};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt 
b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 000..37fc0a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,32 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+   Usage: required
+   Value type: 
+   Definition: should be one of the following. The generic compatible
+   "qcom,kpss-gcc" should also be included.
+   "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+   "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+   "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+   "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+   Usage: required
+   Value type: 
+   Definition: base address and size of the register region
+
+- clock-output-names:
+   Usage: required
+   Value type: 
+   Definition: Name of the output clock. Typically acpu_l2_aux indicating
+   an L2 cache auxiliary clock.
+
+Example:
+
+   l2cc: clock-controller@2011000 {
+   compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+   reg = <0x2011000 0x1000>;
+   clock-output-names = "acpu_l2_aux";
+   };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 08/15] clk: qcom: Add support for Krait clocks

[Sricharan R]

From: Stephen Boyd 

The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.

Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/Kconfig |   4 ++
 drivers/clk/qcom/Makefile|   1 +
 drivers/clk/qcom/clk-krait.c | 124 +++
 drivers/clk/qcom/clk-krait.h |  38 +
 4 files changed, 167 insertions(+)
 create mode 100644 drivers/clk/qcom/clk-krait.c
 create mode 100644 drivers/clk/qcom/clk-krait.h

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index d9ae51e..bf14f56 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -234,3 +234,7 @@ config QCOM_HFPLL
  Support for the high-frequency PLLs present on Qualcomm devices.
  Say Y if you want to support CPU frequency scaling on devices
  such as MSM8974, APQ8084, etc.
+
+config KRAIT_CLOCKS
+   bool
+   select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index c57b808..e1e96f6 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
 clk-qcom-y += clk-regmap-divider.o
 clk-qcom-y += clk-regmap-mux.o
 clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
 clk-qcom-y += clk-hfpll.o
 clk-qcom-y += reset.o
 clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
new file mode 100644
index 000..2e41767
--- /dev/null
+++ b/drivers/clk/qcom/clk-krait.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "clk-krait.h"
+
+/* Secondary and primary muxes share the same cp15 register */
+static DEFINE_SPINLOCK(krait_clock_reg_lock);
+
+#define LPL_SHIFT  8
+static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
+{
+   unsigned long flags;
+   u32 regval;
+
+   spin_lock_irqsave(_clock_reg_lock, flags);
+   regval = krait_get_l2_indirect_reg(mux->offset);
+   regval &= ~(mux->mask << mux->shift);
+   regval |= (sel & mux->mask) << mux->shift;
+   if (mux->lpl) {
+   regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
+   regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
+   }
+   krait_set_l2_indirect_reg(mux->offset, regval);
+   spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+   /* Wait for switch to complete. */
+   mb();
+   udelay(1);
+}
+
+static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+   u32 sel;
+
+   sel = clk_mux_reindex(index, mux->parent_map, 0);
+   mux->en_mask = sel;
+   /* Don't touch mux if CPU is off as it won't work */
+   if (__clk_is_enabled(hw->clk))
+   __krait_mux_set_sel(mux, sel);
+
+   return 0;
+}
+
+static u8 krait_mux_get_parent(struct clk_hw *hw)
+{
+   struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+   u32 sel;
+
+   sel = krait_get_l2_indirect_reg(mux->offset);
+   sel >>= mux->shift;
+   sel &= mux->mask;
+   mux->en_mask = sel;
+
+   return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+}
+
+const struct clk_ops krait_mux_clk_ops = {
+   .set_parent = krait_mux_set_parent,
+   .get_parent = krait_mux_get_parent,
+   .determine_rate = __clk_mux_determine_rate_closest,
+};
+EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+
+/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
+static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+   *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+   return DIV_ROUND_UP(*parent_rate, 2);
+}
+
+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct krait_div2_clk *d = to_krait_div2_clk(hw);
+   unsigned long flags;
+   u32 val;
+   u32 mask = BIT(d->width) - 1;
+
+   if (d->lpl)
+   mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
+
+   spin_lock_irqsave(_clock_reg_lock, flags);
+   val = krait_get_l2_indirect_reg(d->offset);
+   val &= ~mask;
+   krait_set_l2_indirect_reg(d->offset, val);
+   spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+   return 0;
+}
+
+static unsigned long
+krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+   struct krait_div2_clk *d = to_krait_div2_clk(hw);
+   u32 mask = 

[PATCH v9 08/15] clk: qcom: Add support for Krait clocks

[Sricharan R]

From: Stephen Boyd 

The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.

Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/Kconfig |   4 ++
 drivers/clk/qcom/Makefile|   1 +
 drivers/clk/qcom/clk-krait.c | 124 +++
 drivers/clk/qcom/clk-krait.h |  38 +
 4 files changed, 167 insertions(+)
 create mode 100644 drivers/clk/qcom/clk-krait.c
 create mode 100644 drivers/clk/qcom/clk-krait.h

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index d9ae51e..bf14f56 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -234,3 +234,7 @@ config QCOM_HFPLL
  Support for the high-frequency PLLs present on Qualcomm devices.
  Say Y if you want to support CPU frequency scaling on devices
  such as MSM8974, APQ8084, etc.
+
+config KRAIT_CLOCKS
+   bool
+   select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index c57b808..e1e96f6 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
 clk-qcom-y += clk-regmap-divider.o
 clk-qcom-y += clk-regmap-mux.o
 clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
 clk-qcom-y += clk-hfpll.o
 clk-qcom-y += reset.o
 clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
new file mode 100644
index 000..2e41767
--- /dev/null
+++ b/drivers/clk/qcom/clk-krait.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "clk-krait.h"
+
+/* Secondary and primary muxes share the same cp15 register */
+static DEFINE_SPINLOCK(krait_clock_reg_lock);
+
+#define LPL_SHIFT  8
+static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
+{
+   unsigned long flags;
+   u32 regval;
+
+   spin_lock_irqsave(_clock_reg_lock, flags);
+   regval = krait_get_l2_indirect_reg(mux->offset);
+   regval &= ~(mux->mask << mux->shift);
+   regval |= (sel & mux->mask) << mux->shift;
+   if (mux->lpl) {
+   regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
+   regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
+   }
+   krait_set_l2_indirect_reg(mux->offset, regval);
+   spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+   /* Wait for switch to complete. */
+   mb();
+   udelay(1);
+}
+
+static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+   u32 sel;
+
+   sel = clk_mux_reindex(index, mux->parent_map, 0);
+   mux->en_mask = sel;
+   /* Don't touch mux if CPU is off as it won't work */
+   if (__clk_is_enabled(hw->clk))
+   __krait_mux_set_sel(mux, sel);
+
+   return 0;
+}
+
+static u8 krait_mux_get_parent(struct clk_hw *hw)
+{
+   struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+   u32 sel;
+
+   sel = krait_get_l2_indirect_reg(mux->offset);
+   sel >>= mux->shift;
+   sel &= mux->mask;
+   mux->en_mask = sel;
+
+   return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+}
+
+const struct clk_ops krait_mux_clk_ops = {
+   .set_parent = krait_mux_set_parent,
+   .get_parent = krait_mux_get_parent,
+   .determine_rate = __clk_mux_determine_rate_closest,
+};
+EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+
+/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
+static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+   *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+   return DIV_ROUND_UP(*parent_rate, 2);
+}
+
+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct krait_div2_clk *d = to_krait_div2_clk(hw);
+   unsigned long flags;
+   u32 val;
+   u32 mask = BIT(d->width) - 1;
+
+   if (d->lpl)
+   mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
+
+   spin_lock_irqsave(_clock_reg_lock, flags);
+   val = krait_get_l2_indirect_reg(d->offset);
+   val &= ~mask;
+   krait_set_l2_indirect_reg(d->offset, val);
+   spin_unlock_irqrestore(_clock_reg_lock, flags);
+
+   return 0;
+}
+
+static unsigned long
+krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+   struct krait_div2_clk *d = to_krait_div2_clk(hw);
+   u32 mask = BIT(d->width) - 1;
+   u32 div;
+
+  

[PATCH v9 07/15] clk: qcom: Add IPQ806X's HFPLLs

[Sricharan R]

From: Stephen Boyd 

Describe the HFPLLs present on IPQ806X devices.

Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/gcc-ipq806x.c | 82 ++
 1 file changed, 82 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 28eb200..d571cf8 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -30,6 +30,7 @@
 #include "clk-pll.h"
 #include "clk-rcg.h"
 #include "clk-branch.h"
+#include "clk-hfpll.h"
 #include "reset.h"
 
 static struct clk_pll pll0 = {
@@ -113,6 +114,84 @@
},
 };
 
+static struct hfpll_data hfpll0_data = {
+   .mode_reg = 0x3200,
+   .l_reg = 0x3208,
+   .m_reg = 0x320c,
+   .n_reg = 0x3210,
+   .config_reg = 0x3204,
+   .status_reg = 0x321c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3214,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll0",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_data = {
+   .mode_reg = 0x3240,
+   .l_reg = 0x3248,
+   .m_reg = 0x324c,
+   .n_reg = 0x3250,
+   .config_reg = 0x3244,
+   .status_reg = 0x325c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3314,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll1",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll_l2_data = {
+   .mode_reg = 0x3300,
+   .l_reg = 0x3308,
+   .m_reg = 0x330c,
+   .n_reg = 0x3310,
+   .config_reg = 0x3304,
+   .status_reg = 0x331c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3314,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+   .d = _l2_data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll_l2",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
+};
+
 static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
@@ -2800,6 +2879,9 @@ enum {
[UBI32_CORE2_CLK_SRC] = _core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = _tcm_src.clkr,
[NSSTCM_CLK] = _tcm_clk.clkr,
+   [PLL9] = ,
+   [PLL10] = ,
+   [PLL12] = _l2.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 07/15] clk: qcom: Add IPQ806X's HFPLLs

[Sricharan R]

From: Stephen Boyd 

Describe the HFPLLs present on IPQ806X devices.

Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/gcc-ipq806x.c | 82 ++
 1 file changed, 82 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 28eb200..d571cf8 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -30,6 +30,7 @@
 #include "clk-pll.h"
 #include "clk-rcg.h"
 #include "clk-branch.h"
+#include "clk-hfpll.h"
 #include "reset.h"
 
 static struct clk_pll pll0 = {
@@ -113,6 +114,84 @@
},
 };
 
+static struct hfpll_data hfpll0_data = {
+   .mode_reg = 0x3200,
+   .l_reg = 0x3208,
+   .m_reg = 0x320c,
+   .n_reg = 0x3210,
+   .config_reg = 0x3204,
+   .status_reg = 0x321c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3214,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll0",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_data = {
+   .mode_reg = 0x3240,
+   .l_reg = 0x3248,
+   .m_reg = 0x324c,
+   .n_reg = 0x3250,
+   .config_reg = 0x3244,
+   .status_reg = 0x325c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3314,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+   .d = _data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll1",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll_l2_data = {
+   .mode_reg = 0x3300,
+   .l_reg = 0x3308,
+   .m_reg = 0x330c,
+   .n_reg = 0x3310,
+   .config_reg = 0x3304,
+   .status_reg = 0x331c,
+   .config_val = 0x7845c665,
+   .droop_reg = 0x3314,
+   .droop_val = 0x0108c000,
+   .min_rate = 6UL,
+   .max_rate = 18UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+   .d = _l2_data,
+   .clkr.hw.init = &(struct clk_init_data){
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .name = "hfpll_l2",
+   .ops = _ops_hfpll,
+   .flags = CLK_IGNORE_UNUSED,
+   },
+   .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
+};
+
 static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
@@ -2800,6 +2879,9 @@ enum {
[UBI32_CORE2_CLK_SRC] = _core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = _tcm_src.clkr,
[NSSTCM_CLK] = _tcm_clk.clkr,
+   [PLL9] = ,
+   [PLL10] = ,
+   [PLL12] = _l2.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v9 04/15] clk: qcom: Add HFPLL driver

[Sricharan R]

From: Stephen Boyd 

On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.

Cc: 
Signed-off-by: Stephen Boyd 
---
 drivers/clk/qcom/Kconfig  |  8 
 drivers/clk/qcom/Makefile |  1 +
 drivers/clk/qcom/hfpll.c  | 96 +++
 3 files changed, 105 insertions(+)
 create mode 100644 drivers/clk/qcom/hfpll.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index fbf4532..d9ae51e 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -226,3 +226,11 @@ config SPMI_PMIC_CLKDIV
  Technologies, Inc. SPMI PMIC. It configures the frequency of
  clkdiv outputs of the PMIC. These clocks are typically wired
  through alternate functions on GPIO pins.
+
+config QCOM_HFPLL
+   tristate "High-Frequency PLL (HFPLL) Clock Controller"
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the high-frequency PLLs present on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling on devices
+ such as MSM8974, APQ8084, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index a2b7888..c57b808 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
 obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
new file mode 100644
index 000..a6de7101
--- /dev/null
+++ b/drivers/clk/qcom/hfpll.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk-regmap.h"
+#include "clk-hfpll.h"
+
+static const struct hfpll_data hdata = {
+   .mode_reg = 0x00,
+   .l_reg = 0x04,
+   .m_reg = 0x08,
+   .n_reg = 0x0c,
+   .user_reg = 0x10,
+   .config_reg = 0x14,
+   .config_val = 0x430405d,
+   .status_reg = 0x1c,
+   .lock_bit = 16,
+
+   .user_val = 0x8,
+   .user_vco_mask = 0x10,
+   .low_vco_max_rate = 124800,
+   .min_rate = 53760UL,
+   .max_rate = 29UL,
+};
+
+static const struct of_device_id qcom_hfpll_match_table[] = {
+   { .compatible = "qcom,hfpll" },
+   { }
+};
+MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
+
+static const struct regmap_config hfpll_regmap_config = {
+   .reg_bits   = 32,
+   .reg_stride = 4,
+   .val_bits   = 32,
+   .max_register   = 0x30,
+   .fast_io= true,
+};
+
+static int qcom_hfpll_probe(struct platform_device *pdev)
+{
+   struct resource *res;
+   struct device *dev = >dev;
+   void __iomem *base;
+   struct regmap *regmap;
+   struct clk_hfpll *h;
+   struct clk_init_data init = {
+   .parent_names = (const char *[]){ "xo" },
+   .num_parents = 1,
+   .ops = _ops_hfpll,
+   };
+
+   h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
+   if (!h)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   base = devm_ioremap_resource(dev, res);
+   if (IS_ERR(base))
+   return PTR_ERR(base);
+
+   regmap = devm_regmap_init_mmio(>dev, base, _regmap_config);
+   if (IS_ERR(regmap))
+   return PTR_ERR(regmap);
+
+   if (of_property_read_string_index(dev->of_node, "clock-output-names",
+ 0, ))
+   return -ENODEV;
+
+   h->d = 
+   h->clkr.hw.init = 
+   spin_lock_init(>lock);
+
+   return devm_clk_register_regmap(>dev, >clkr);
+}
+
+static struct platform_driver qcom_hfpll_driver = {
+   .probe  = qcom_hfpll_probe,
+   .driver = {
+   .name   = "qcom-hfpll",
+   .of_match_table = qcom_hfpll_match_table,
+   },
+};
+module_platform_driver(qcom_hfpll_driver);
+
+MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-hfpll");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation