[tip:x86/cpu] x86/power: Optimize C3 entry on Centaur CPUs

2019-04-19 Thread tip-bot for David Wang 
Commit-ID:  987ddbe4870b53623d76ac64044c55a13e368113
Gitweb: https://git.kernel.org/tip/987ddbe4870b53623d76ac64044c55a13e368113
Author: David Wang 
AuthorDate: Thu, 27 Dec 2018 16:41:50 +0800
Committer:  Ingo Molnar 
CommitDate: Fri, 19 Apr 2019 19:28:06 +0200

x86/power: Optimize C3 entry on Centaur CPUs

For new Centaur CPUs the ucode will take care of the preservation of cache 
coherence
between CPU cores in C-states regardless of how deep the C-states are. So, it 
is not
necessary to flush the caches in software befor entering C3. This useless 
operation
will cause performance drop for the cores which share some caches with the 
idling core.

Signed-off-by: David Wang 
Reviewed-by: Thomas Gleixner 
Acked-by: Pavel Machek 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: brucech...@via-alliance.com
Cc: cooper...@zhaoxin.com
Cc: len.br...@intel.com
Cc: linux...@kernel.org
Cc: qiyuanw...@zhaoxin.com
Cc: r...@rjwysocki.net
Cc: tim...@zhaoxin.com
Link: 
http://lkml.kernel.org/r/1545900110-2757-1-git-send-email-davidw...@zhaoxin.com
[ Tidy up the comment. ]
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/acpi/cstate.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 158ad1483c43..cb6e076a6d39 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct 
acpi_processor_flags *flags,
if (c->x86_vendor == X86_VENDOR_INTEL &&
(c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
flags->bm_control = 0;
+   /*
+* For all recent Centaur CPUs, the ucode will make sure that each
+* core can keep cache coherence with each other while entering C3
+* type state. So, set bm_check to 1 to indicate that the kernel
+* doesn't need to execute a cache flush operation (WBINVD) when
+* entering C3 type state.
+*/
+   if (c->x86_vendor == X86_VENDOR_CENTAUR) {
+   if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f &&
+   c->x86_stepping >= 0x0e))
+   flags->bm_check = 1;
+   }
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);

[tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  807e9bc8e2fe6b4907f9f77fd073f7ef5073af29
Gitweb: https://git.kernel.org/tip/807e9bc8e2fe6b4907f9f77fd073f7ef5073af29
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:45 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 16:14:24 +0200

x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()

There is no point in having the conditional cpu_detect_cache_sizes() call
at the callsite of init_intel_cacheinfo().

Move it into init_intel_cacheinfo() and make init_intel_cacheinfo() void.

[ tglx: Made the init_intel_cacheinfo() void as the return value was
pointless. Adjust changelog accordingly ]

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-3-git-send-email-davidw...@zhaoxin.com


---
 arch/x86/kernel/cpu/cacheinfo.c |  5 +++--
 arch/x86/kernel/cpu/cpu.h   |  2 +-
 arch/x86/kernel/cpu/intel.c | 14 --
 3 files changed, 8 insertions(+), 13 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 58d472c84ba2..38354c66df81 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -691,7 +691,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c)
}
 }
 
-unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
+void init_intel_cacheinfo(struct cpuinfo_x86 *c)
 {
/* Cache sizes */
unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
@@ -843,7 +843,8 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
 
c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
 
-   return l2;
+   if (!l2)
+   cpu_detect_cache_sizes(c);
 }
 
 static int __cache_amd_cpumap_setup(unsigned int cpu, int index,
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index efd6ef8ad14e..49bf8a080105 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -51,7 +51,7 @@ extern void init_scattered_cpuid_features(struct cpuinfo_x86 
*c);
 extern u32 get_scattered_cpuid_leaf(unsigned int level,
unsigned int sub_leaf,
enum cpuid_regs_idx reg);
-extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
+extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 
 extern int detect_num_cpu_cores(struct cpuinfo_x86 *c);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b54535be254a..ca141d159be1 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -635,8 +635,6 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c)
 
 static void init_intel(struct cpuinfo_x86 *c)
 {
-   unsigned int l2 = 0;
-
early_init_intel(c);
 
intel_workarounds(c);
@@ -659,13 +657,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 #endif
}
 
-   l2 = init_intel_cacheinfo(c);
-
-   /* Detect legacy cache sizes if init_intel_cacheinfo did not */
-   if (l2 == 0) {
-   cpu_detect_cache_sizes(c);
-   l2 = c->x86_cache_size;
-   }
+   init_intel_cacheinfo(c);
 
if (c->cpuid_level > 9) {
unsigned eax = cpuid_eax(10);
@@ -678,7 +670,8 @@ static void init_intel(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 
if (boot_cpu_has(X86_FEATURE_DS)) {
-   unsigned int l1;
+   unsigned int l1, l2;
+
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
if (!(l1 & (1<<11)))
set_cpu_cap(c, X86_FEATURE_BTS);
@@ -706,6 +699,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 * Dixon is NOT a Celeron.
 */
if (c->x86 == 6) {
+   unsigned int l2 = c->x86_cache_size;
char *p = NULL;
 
switch (c->x86_model) {

[tip:x86/cpu] x86/Centaur: Report correct CPU/cache topology

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  a2aa578fec8c29436bce5e6c15e1e31729d539a3
Gitweb: https://git.kernel.org/tip/a2aa578fec8c29436bce5e6c15e1e31729d539a3
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:46 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 16:14:24 +0200

x86/Centaur: Report correct CPU/cache topology

Centaur CPUs enumerate the cache topology in the same way as Intel CPUs,
but the function is unused so for. The Centaur init code also misses to
initialize x86_info::max_cores, so the CPU topology can't be described
correctly.

Initialize x86_info::max_cores and invoke init_cacheinfo() to make
CPU and cache topology information available and correct.

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-4-git-send-email-davidw...@zhaoxin.com


---
 arch/x86/kernel/cpu/centaur.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 80d5110481ec..c265494234e6 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c)
clear_cpu_cap(c, 0*32+31);
 #endif
early_init_centaur(c);
+   init_intel_cacheinfo(c);
+   c->x86_max_cores = detect_num_cpu_cores(c);
+#ifdef CONFIG_X86_32
+   detect_ht(c);
+#endif
 
if (c->cpuid_level > 9) {
unsigned int eax = cpuid_eax(10);

[tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  807e9bc8e2fe6b4907f9f77fd073f7ef5073af29
Gitweb: https://git.kernel.org/tip/807e9bc8e2fe6b4907f9f77fd073f7ef5073af29
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:45 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 16:14:24 +0200

x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()

There is no point in having the conditional cpu_detect_cache_sizes() call
at the callsite of init_intel_cacheinfo().

Move it into init_intel_cacheinfo() and make init_intel_cacheinfo() void.

[ tglx: Made the init_intel_cacheinfo() void as the return value was
pointless. Adjust changelog accordingly ]

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-3-git-send-email-davidw...@zhaoxin.com


---
 arch/x86/kernel/cpu/cacheinfo.c |  5 +++--
 arch/x86/kernel/cpu/cpu.h   |  2 +-
 arch/x86/kernel/cpu/intel.c | 14 --
 3 files changed, 8 insertions(+), 13 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 58d472c84ba2..38354c66df81 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -691,7 +691,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c)
}
 }
 
-unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
+void init_intel_cacheinfo(struct cpuinfo_x86 *c)
 {
/* Cache sizes */
unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
@@ -843,7 +843,8 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
 
c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
 
-   return l2;
+   if (!l2)
+   cpu_detect_cache_sizes(c);
 }
 
 static int __cache_amd_cpumap_setup(unsigned int cpu, int index,
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index efd6ef8ad14e..49bf8a080105 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -51,7 +51,7 @@ extern void init_scattered_cpuid_features(struct cpuinfo_x86 
*c);
 extern u32 get_scattered_cpuid_leaf(unsigned int level,
unsigned int sub_leaf,
enum cpuid_regs_idx reg);
-extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
+extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 
 extern int detect_num_cpu_cores(struct cpuinfo_x86 *c);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b54535be254a..ca141d159be1 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -635,8 +635,6 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c)
 
 static void init_intel(struct cpuinfo_x86 *c)
 {
-   unsigned int l2 = 0;
-
early_init_intel(c);
 
intel_workarounds(c);
@@ -659,13 +657,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 #endif
}
 
-   l2 = init_intel_cacheinfo(c);
-
-   /* Detect legacy cache sizes if init_intel_cacheinfo did not */
-   if (l2 == 0) {
-   cpu_detect_cache_sizes(c);
-   l2 = c->x86_cache_size;
-   }
+   init_intel_cacheinfo(c);
 
if (c->cpuid_level > 9) {
unsigned eax = cpuid_eax(10);
@@ -678,7 +670,8 @@ static void init_intel(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 
if (boot_cpu_has(X86_FEATURE_DS)) {
-   unsigned int l1;
+   unsigned int l1, l2;
+
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
if (!(l1 & (1<<11)))
set_cpu_cap(c, X86_FEATURE_BTS);
@@ -706,6 +699,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 * Dixon is NOT a Celeron.
 */
if (c->x86 == 6) {
+   unsigned int l2 = c->x86_cache_size;
char *p = NULL;
 
switch (c->x86_model) {

[tip:x86/cpu] x86/Centaur: Report correct CPU/cache topology

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  a2aa578fec8c29436bce5e6c15e1e31729d539a3
Gitweb: https://git.kernel.org/tip/a2aa578fec8c29436bce5e6c15e1e31729d539a3
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:46 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 16:14:24 +0200

x86/Centaur: Report correct CPU/cache topology

Centaur CPUs enumerate the cache topology in the same way as Intel CPUs,
but the function is unused so for. The Centaur init code also misses to
initialize x86_info::max_cores, so the CPU topology can't be described
correctly.

Initialize x86_info::max_cores and invoke init_cacheinfo() to make
CPU and cache topology information available and correct.

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-4-git-send-email-davidw...@zhaoxin.com


---
 arch/x86/kernel/cpu/centaur.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 80d5110481ec..c265494234e6 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c)
clear_cpu_cap(c, 0*32+31);
 #endif
early_init_centaur(c);
+   init_intel_cacheinfo(c);
+   c->x86_max_cores = detect_num_cpu_cores(c);
+#ifdef CONFIG_X86_32
+   detect_ht(c);
+#endif
 
if (c->cpuid_level > 9) {
unsigned int eax = cpuid_eax(10);

[tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  606e20959ef49f22cddb611f2cefef8e6501e3dd
Gitweb: https://git.kernel.org/tip/606e20959ef49f22cddb611f2cefef8e6501e3dd
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:45 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 12:06:12 +0200

x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()

There is no point in having the conditional cpu_detect_cache_sizes() call
at the callsite of init_intel_cacheinfo().

Move it into init_intel_cacheinfo() and make init_intel_cacheinfo() void.

[ tglx: Made the init_intel_cacheinfo() void as the return value was
pointless. Adjust changelog accordingly ]

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-3-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/cacheinfo.c |  5 +++--
 arch/x86/kernel/cpu/cpu.h   |  2 +-
 arch/x86/kernel/cpu/intel.c | 13 +++--
 3 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 58d472c84ba2..38354c66df81 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -691,7 +691,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c)
}
 }
 
-unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
+void init_intel_cacheinfo(struct cpuinfo_x86 *c)
 {
/* Cache sizes */
unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
@@ -843,7 +843,8 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
 
c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
 
-   return l2;
+   if (!l2)
+   cpu_detect_cache_sizes(c);
 }
 
 static int __cache_amd_cpumap_setup(unsigned int cpu, int index,
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index efd6ef8ad14e..49bf8a080105 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -51,7 +51,7 @@ extern void init_scattered_cpuid_features(struct cpuinfo_x86 
*c);
 extern u32 get_scattered_cpuid_leaf(unsigned int level,
unsigned int sub_leaf,
enum cpuid_regs_idx reg);
-extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
+extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 
 extern int detect_num_cpu_cores(struct cpuinfo_x86 *c);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b54535be254a..615870420be2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -635,8 +635,6 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c)
 
 static void init_intel(struct cpuinfo_x86 *c)
 {
-   unsigned int l2 = 0;
-
early_init_intel(c);
 
intel_workarounds(c);
@@ -659,13 +657,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 #endif
}
 
-   l2 = init_intel_cacheinfo(c);
-
-   /* Detect legacy cache sizes if init_intel_cacheinfo did not */
-   if (l2 == 0) {
-   cpu_detect_cache_sizes(c);
-   l2 = c->x86_cache_size;
-   }
+   init_intel_cacheinfo(c);
 
if (c->cpuid_level > 9) {
unsigned eax = cpuid_eax(10);
@@ -678,7 +670,8 @@ static void init_intel(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 
if (boot_cpu_has(X86_FEATURE_DS)) {
-   unsigned int l1;
+   unsigned int l1, l2;
+
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
if (!(l1 & (1<<11)))
set_cpu_cap(c, X86_FEATURE_BTS);

[tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  606e20959ef49f22cddb611f2cefef8e6501e3dd
Gitweb: https://git.kernel.org/tip/606e20959ef49f22cddb611f2cefef8e6501e3dd
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:45 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 12:06:12 +0200

x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()

There is no point in having the conditional cpu_detect_cache_sizes() call
at the callsite of init_intel_cacheinfo().

Move it into init_intel_cacheinfo() and make init_intel_cacheinfo() void.

[ tglx: Made the init_intel_cacheinfo() void as the return value was
pointless. Adjust changelog accordingly ]

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-3-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/cacheinfo.c |  5 +++--
 arch/x86/kernel/cpu/cpu.h   |  2 +-
 arch/x86/kernel/cpu/intel.c | 13 +++--
 3 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 58d472c84ba2..38354c66df81 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -691,7 +691,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c)
}
 }
 
-unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
+void init_intel_cacheinfo(struct cpuinfo_x86 *c)
 {
/* Cache sizes */
unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
@@ -843,7 +843,8 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
 
c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
 
-   return l2;
+   if (!l2)
+   cpu_detect_cache_sizes(c);
 }
 
 static int __cache_amd_cpumap_setup(unsigned int cpu, int index,
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index efd6ef8ad14e..49bf8a080105 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -51,7 +51,7 @@ extern void init_scattered_cpuid_features(struct cpuinfo_x86 
*c);
 extern u32 get_scattered_cpuid_leaf(unsigned int level,
unsigned int sub_leaf,
enum cpuid_regs_idx reg);
-extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
+extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 
 extern int detect_num_cpu_cores(struct cpuinfo_x86 *c);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b54535be254a..615870420be2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -635,8 +635,6 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c)
 
 static void init_intel(struct cpuinfo_x86 *c)
 {
-   unsigned int l2 = 0;
-
early_init_intel(c);
 
intel_workarounds(c);
@@ -659,13 +657,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 #endif
}
 
-   l2 = init_intel_cacheinfo(c);
-
-   /* Detect legacy cache sizes if init_intel_cacheinfo did not */
-   if (l2 == 0) {
-   cpu_detect_cache_sizes(c);
-   l2 = c->x86_cache_size;
-   }
+   init_intel_cacheinfo(c);
 
if (c->cpuid_level > 9) {
unsigned eax = cpuid_eax(10);
@@ -678,7 +670,8 @@ static void init_intel(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 
if (boot_cpu_has(X86_FEATURE_DS)) {
-   unsigned int l1;
+   unsigned int l1, l2;
+
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
if (!(l1 & (1<<11)))
set_cpu_cap(c, X86_FEATURE_BTS);

[tip:x86/cpu] x86/Centaur: Report correct CPU/cache topology

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  5a19009043fcffd1591b04a588d53336a66855d5
Gitweb: https://git.kernel.org/tip/5a19009043fcffd1591b04a588d53336a66855d5
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:46 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 12:06:13 +0200

x86/Centaur: Report correct CPU/cache topology

Centaur CPUs enumerate the cache topology in the same way as Intel CPUs,
but the function is unused so for. The Centaur init code also misses to
initialize x86_info::max_cores, so the CPU topology can't be described
correctly.

Initialize x86_info::max_cores and invoke init_cacheinfo() to make
CPU and cache topology information available and correct.

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-4-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/centaur.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 80d5110481ec..c265494234e6 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c)
clear_cpu_cap(c, 0*32+31);
 #endif
early_init_centaur(c);
+   init_intel_cacheinfo(c);
+   c->x86_max_cores = detect_num_cpu_cores(c);
+#ifdef CONFIG_X86_32
+   detect_ht(c);
+#endif
 
if (c->cpuid_level > 9) {
unsigned int eax = cpuid_eax(10);

[tip:x86/cpu] x86/Centaur: Report correct CPU/cache topology

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  5a19009043fcffd1591b04a588d53336a66855d5
Gitweb: https://git.kernel.org/tip/5a19009043fcffd1591b04a588d53336a66855d5
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:46 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 12:06:13 +0200

x86/Centaur: Report correct CPU/cache topology

Centaur CPUs enumerate the cache topology in the same way as Intel CPUs,
but the function is unused so for. The Centaur init code also misses to
initialize x86_info::max_cores, so the CPU topology can't be described
correctly.

Initialize x86_info::max_cores and invoke init_cacheinfo() to make
CPU and cache topology information available and correct.

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-4-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/centaur.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 80d5110481ec..c265494234e6 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c)
clear_cpu_cap(c, 0*32+31);
 #endif
early_init_centaur(c);
+   init_intel_cacheinfo(c);
+   c->x86_max_cores = detect_num_cpu_cores(c);
+#ifdef CONFIG_X86_32
+   detect_ht(c);
+#endif
 
if (c->cpuid_level > 9) {
unsigned int eax = cpuid_eax(10);

[tip:x86/cpu] x86/CPU: Make intel_num_cpu_cores() generic

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  2cc61be60e37b1856a97ccbdcca3e86e593bf06a
Gitweb: https://git.kernel.org/tip/2cc61be60e37b1856a97ccbdcca3e86e593bf06a
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:44 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 12:06:12 +0200

x86/CPU: Make intel_num_cpu_cores() generic

intel_num_cpu_cores() is a static function in intel.c which can't be used
by other files. Define another function called detect_num_cpu_cores() in
common.c to replace this function so it can be reused.

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-2-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/common.c | 14 ++
 arch/x86/kernel/cpu/cpu.h|  1 +
 arch/x86/kernel/cpu/intel.c  | 20 +---
 3 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 37c7c8334a00..6993842e788c 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -584,6 +584,20 @@ static void get_model_name(struct cpuinfo_x86 *c)
*(s + 1) = '\0';
 }
 
+int detect_num_cpu_cores(struct cpuinfo_x86 *c)
+{
+   unsigned int eax, ebx, ecx, edx;
+
+   if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
+   return 1;
+
+   cpuid_count(4, 0, , , , );
+   if (eax & 0x1f)
+   return (eax >> 26) + 1;
+   else
+   return 1;
+}
+
 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
 {
unsigned int n, dummy, ebx, ecx, edx, l2size;
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index c415f99e9599..efd6ef8ad14e 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -54,6 +54,7 @@ extern u32 get_scattered_cpuid_leaf(unsigned int level,
 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 
+extern int detect_num_cpu_cores(struct cpuinfo_x86 *c);
 extern int detect_extended_topology(struct cpuinfo_x86 *c);
 extern void detect_ht(struct cpuinfo_x86 *c);
 
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b9693b80fc21..b54535be254a 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -453,24 +453,6 @@ static void srat_detect_node(struct cpuinfo_x86 *c)
 #endif
 }
 
-/*
- * find out the number of processor cores on the die
- */
-static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
-{
-   unsigned int eax, ebx, ecx, edx;
-
-   if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
-   return 1;
-
-   /* Intel has a non-standard dependency on %ecx for this CPUID level. */
-   cpuid_count(4, 0, , , , );
-   if (eax & 0x1f)
-   return (eax >> 26) + 1;
-   else
-   return 1;
-}
-
 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
 {
/* Intel VMX MSR indicated features */
@@ -671,7 +653,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 * detection.
 */
-   c->x86_max_cores = intel_num_cpu_cores(c);
+   c->x86_max_cores = detect_num_cpu_cores(c);
 #ifdef CONFIG_X86_32
detect_ht(c);
 #endif

[tip:x86/cpu] x86/CPU: Make intel_num_cpu_cores() generic

2018-05-13 Thread tip-bot for David Wang 
Commit-ID:  2cc61be60e37b1856a97ccbdcca3e86e593bf06a
Gitweb: https://git.kernel.org/tip/2cc61be60e37b1856a97ccbdcca3e86e593bf06a
Author: David Wang 
AuthorDate: Thu, 3 May 2018 10:32:44 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 13 May 2018 12:06:12 +0200

x86/CPU: Make intel_num_cpu_cores() generic

intel_num_cpu_cores() is a static function in intel.c which can't be used
by other files. Define another function called detect_num_cpu_cores() in
common.c to replace this function so it can be reused.

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1525314766-18910-2-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/common.c | 14 ++
 arch/x86/kernel/cpu/cpu.h|  1 +
 arch/x86/kernel/cpu/intel.c  | 20 +---
 3 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 37c7c8334a00..6993842e788c 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -584,6 +584,20 @@ static void get_model_name(struct cpuinfo_x86 *c)
*(s + 1) = '\0';
 }
 
+int detect_num_cpu_cores(struct cpuinfo_x86 *c)
+{
+   unsigned int eax, ebx, ecx, edx;
+
+   if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
+   return 1;
+
+   cpuid_count(4, 0, , , , );
+   if (eax & 0x1f)
+   return (eax >> 26) + 1;
+   else
+   return 1;
+}
+
 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
 {
unsigned int n, dummy, ebx, ecx, edx, l2size;
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index c415f99e9599..efd6ef8ad14e 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -54,6 +54,7 @@ extern u32 get_scattered_cpuid_leaf(unsigned int level,
 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 
+extern int detect_num_cpu_cores(struct cpuinfo_x86 *c);
 extern int detect_extended_topology(struct cpuinfo_x86 *c);
 extern void detect_ht(struct cpuinfo_x86 *c);
 
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b9693b80fc21..b54535be254a 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -453,24 +453,6 @@ static void srat_detect_node(struct cpuinfo_x86 *c)
 #endif
 }
 
-/*
- * find out the number of processor cores on the die
- */
-static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
-{
-   unsigned int eax, ebx, ecx, edx;
-
-   if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
-   return 1;
-
-   /* Intel has a non-standard dependency on %ecx for this CPUID level. */
-   cpuid_count(4, 0, , , , );
-   if (eax & 0x1f)
-   return (eax >> 26) + 1;
-   else
-   return 1;
-}
-
 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
 {
/* Intel VMX MSR indicated features */
@@ -671,7 +653,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 * detection.
 */
-   c->x86_max_cores = intel_num_cpu_cores(c);
+   c->x86_max_cores = detect_num_cpu_cores(c);
 #ifdef CONFIG_X86_32
detect_ht(c);
 #endif

[tip:ras/core] x86/MCE: Enable MCE broadcasting on new Centaur CPUs

2018-05-06 Thread tip-bot for David Wang 
Commit-ID:  13e8582245267b872dc6eb4ab695fffc797d99f5
Gitweb: https://git.kernel.org/tip/13e8582245267b872dc6eb4ab695fffc797d99f5
Author: David Wang 
AuthorDate: Wed, 25 Apr 2018 18:33:39 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 6 May 2018 12:46:25 +0200

x86/MCE: Enable MCE broadcasting on new Centaur CPUs

Newer Centaur multi-core CPUs also support MCE broadcasting to all
cores. Add a Centaur-specific init function setting that up.

 [ bp:
   - make mce_centaur_feature_init() static
   - flip check to do the f/m/s first for better readability
   - touch up text
  ]

Signed-off-by: David Wang 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: Greg KH 
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: Tony Luck 
Cc: benjamin...@viatech.com
Cc: linux-edac 
Link: 
http://lkml.kernel.org/r/1524652420-17330-2-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/mcheck/mce.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 42cf2880d0ed..cd76380af79f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1727,6 +1727,21 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 
*c)
}
 }
 
+static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
+{
+   struct mca_config *cfg = _cfg;
+
+/*
+ * All newer Centaur CPUs support MCE broadcasting. Enable
+ * synchronization with a one second timeout.
+ */
+   if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
+c->x86 > 6) {
+   if (cfg->monarch_timeout < 0)
+   cfg->monarch_timeout = USEC_PER_SEC;
+   }
+}
+
 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
 {
switch (c->x86_vendor) {
@@ -1739,6 +1754,9 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 
*c)
mce_amd_feature_init(c);
break;
}
+   case X86_VENDOR_CENTAUR:
+   mce_centaur_feature_init(c);
+   break;
 
default:
break;

[tip:ras/core] x86/MCE: Enable MCE broadcasting on new Centaur CPUs

2018-05-06 Thread tip-bot for David Wang 
Commit-ID:  13e8582245267b872dc6eb4ab695fffc797d99f5
Gitweb: https://git.kernel.org/tip/13e8582245267b872dc6eb4ab695fffc797d99f5
Author: David Wang 
AuthorDate: Wed, 25 Apr 2018 18:33:39 +0800
Committer:  Thomas Gleixner 
CommitDate: Sun, 6 May 2018 12:46:25 +0200

x86/MCE: Enable MCE broadcasting on new Centaur CPUs

Newer Centaur multi-core CPUs also support MCE broadcasting to all
cores. Add a Centaur-specific init function setting that up.

 [ bp:
   - make mce_centaur_feature_init() static
   - flip check to do the f/m/s first for better readability
   - touch up text
  ]

Signed-off-by: David Wang 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: Greg KH 
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: Tony Luck 
Cc: benjamin...@viatech.com
Cc: linux-edac 
Link: 
http://lkml.kernel.org/r/1524652420-17330-2-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/mcheck/mce.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 42cf2880d0ed..cd76380af79f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1727,6 +1727,21 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 
*c)
}
 }
 
+static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
+{
+   struct mca_config *cfg = _cfg;
+
+/*
+ * All newer Centaur CPUs support MCE broadcasting. Enable
+ * synchronization with a one second timeout.
+ */
+   if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
+c->x86 > 6) {
+   if (cfg->monarch_timeout < 0)
+   cfg->monarch_timeout = USEC_PER_SEC;
+   }
+}
+
 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
 {
switch (c->x86_vendor) {
@@ -1739,6 +1754,9 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 
*c)
mce_amd_feature_init(c);
break;
}
+   case X86_VENDOR_CENTAUR:
+   mce_centaur_feature_init(c);
+   break;
 
default:
break;

[tip:x86/cpu] x86/Centaur: Initialize supported CPU features properly

2018-04-20 Thread tip-bot for David Wang 
Commit-ID:  60882cc159e1416fb1d17210de60d4a3ba04e613
Gitweb: https://git.kernel.org/tip/60882cc159e1416fb1d17210de60d4a3ba04e613
Author: David Wang 
AuthorDate: Fri, 20 Apr 2018 16:29:28 +0800
Committer:  Thomas Gleixner 
CommitDate: Fri, 20 Apr 2018 12:08:17 +0200

x86/Centaur: Initialize supported CPU features properly

Centaur CPUs have some Intel compatible capabilities,including Permformance
Monitoring Counters and CPU virtualization capabilities. Initialize them in
the Centaur specific init code.

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1524212968-28998-1-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/centaur.c | 48 +++
 1 file changed, 48 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index e5ec0f11c0de..80d5110481ec 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -18,6 +18,13 @@
 #define RNG_ENABLED(1 << 3)
 #define RNG_ENABLE (1 << 6)/* MSR_VIA_RNG */
 
+#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW   0x0020
+#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x0040
+#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x8000
+#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC   0x0001
+#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x0002
+#define X86_VMX_FEATURE_PROC_CTLS2_VPID0x0020
+
 static void init_c3(struct cpuinfo_x86 *c)
 {
u32  lo, hi;
@@ -112,6 +119,31 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
}
 }
 
+static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
+{
+   u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
+
+   rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
+   msr_ctl = vmx_msr_high | vmx_msr_low;
+
+   if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
+   set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
+   if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
+   set_cpu_cap(c, X86_FEATURE_VNMI);
+   if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
+   rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
+ vmx_msr_low, vmx_msr_high);
+   msr_ctl2 = vmx_msr_high | vmx_msr_low;
+   if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
+   (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
+   set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
+   if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
+   set_cpu_cap(c, X86_FEATURE_EPT);
+   if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
+   set_cpu_cap(c, X86_FEATURE_VPID);
+   }
+}
+
 static void init_centaur(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_X86_32
@@ -128,6 +160,19 @@ static void init_centaur(struct cpuinfo_x86 *c)
clear_cpu_cap(c, 0*32+31);
 #endif
early_init_centaur(c);
+
+   if (c->cpuid_level > 9) {
+   unsigned int eax = cpuid_eax(10);
+
+   /*
+* Check for version and the number of counters
+* Version(eax[7:0]) can't be 0;
+* Counters(eax[15:8]) should be greater than 1;
+*/
+   if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
+   set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
+   }
+
switch (c->x86) {
 #ifdef CONFIG_X86_32
case 5:
@@ -199,6 +244,9 @@ static void init_centaur(struct cpuinfo_x86 *c)
 #ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 #endif
+
+   if (cpu_has(c, X86_FEATURE_VMX))
+   centaur_detect_vmx_virtcap(c);
 }
 
 #ifdef CONFIG_X86_32

[tip:x86/cpu] x86/Centaur: Initialize supported CPU features properly

2018-04-20 Thread tip-bot for David Wang 
Commit-ID:  60882cc159e1416fb1d17210de60d4a3ba04e613
Gitweb: https://git.kernel.org/tip/60882cc159e1416fb1d17210de60d4a3ba04e613
Author: David Wang 
AuthorDate: Fri, 20 Apr 2018 16:29:28 +0800
Committer:  Thomas Gleixner 
CommitDate: Fri, 20 Apr 2018 12:08:17 +0200

x86/Centaur: Initialize supported CPU features properly

Centaur CPUs have some Intel compatible capabilities,including Permformance
Monitoring Counters and CPU virtualization capabilities. Initialize them in
the Centaur specific init code.

Signed-off-by: David Wang 
Signed-off-by: Thomas Gleixner 
Cc: luke...@viacpu.com
Cc: qiyuanw...@zhaoxin.com
Cc: gre...@linuxfoundation.org
Cc: brucech...@via-alliance.com
Cc: tim...@zhaoxin.com
Cc: cooper...@zhaoxin.com
Cc: h...@zytor.com
Cc: benjamin...@viatech.com
Link: 
https://lkml.kernel.org/r/1524212968-28998-1-git-send-email-davidw...@zhaoxin.com

---
 arch/x86/kernel/cpu/centaur.c | 48 +++
 1 file changed, 48 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index e5ec0f11c0de..80d5110481ec 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -18,6 +18,13 @@
 #define RNG_ENABLED(1 << 3)
 #define RNG_ENABLE (1 << 6)/* MSR_VIA_RNG */
 
+#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW   0x0020
+#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x0040
+#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x8000
+#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC   0x0001
+#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x0002
+#define X86_VMX_FEATURE_PROC_CTLS2_VPID0x0020
+
 static void init_c3(struct cpuinfo_x86 *c)
 {
u32  lo, hi;
@@ -112,6 +119,31 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
}
 }
 
+static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
+{
+   u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
+
+   rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
+   msr_ctl = vmx_msr_high | vmx_msr_low;
+
+   if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
+   set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
+   if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
+   set_cpu_cap(c, X86_FEATURE_VNMI);
+   if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
+   rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
+ vmx_msr_low, vmx_msr_high);
+   msr_ctl2 = vmx_msr_high | vmx_msr_low;
+   if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
+   (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
+   set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
+   if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
+   set_cpu_cap(c, X86_FEATURE_EPT);
+   if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
+   set_cpu_cap(c, X86_FEATURE_VPID);
+   }
+}
+
 static void init_centaur(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_X86_32
@@ -128,6 +160,19 @@ static void init_centaur(struct cpuinfo_x86 *c)
clear_cpu_cap(c, 0*32+31);
 #endif
early_init_centaur(c);
+
+   if (c->cpuid_level > 9) {
+   unsigned int eax = cpuid_eax(10);
+
+   /*
+* Check for version and the number of counters
+* Version(eax[7:0]) can't be 0;
+* Counters(eax[15:8]) should be greater than 1;
+*/
+   if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
+   set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
+   }
+
switch (c->x86) {
 #ifdef CONFIG_X86_32
case 5:
@@ -199,6 +244,9 @@ static void init_centaur(struct cpuinfo_x86 *c)
 #ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 #endif
+
+   if (cpu_has(c, X86_FEATURE_VMX))
+   centaur_detect_vmx_virtcap(c);
 }
 
 #ifdef CONFIG_X86_32