[tip: timers/core] clocksource/drivers/timer-ti-dm: Add missing set_state_oneshot_stopped
The following commit has been merged into the timers/core branch of tip:
Commit-ID: ac4daf737674b4d29e19b7c300caff3bcf7160d8
Gitweb:
https://git.kernel.org/tip/ac4daf737674b4d29e19b7c300caff3bcf7160d8
Author:Tony Lindgren
AuthorDate:Thu, 04 Mar 2021 09:21:35 +02:00
Committer: Daniel Lezcano
CommitterDate: Thu, 08 Apr 2021 13:23:47 +02:00
clocksource/drivers/timer-ti-dm: Add missing set_state_oneshot_stopped
To avoid spurious timer interrupts when KTIME_MAX is used, we need to
configure set_state_oneshot_stopped(). Although implementing this is
optional, it still affects things like power management for the extra
timer interrupt.
For more information, please see commit 8fff52fd5093 ("clockevents:
Introduce CLOCK_EVT_STATE_ONESHOT_STOPPED state") and commit cf8c5009ee37
("clockevents/drivers/arm_arch_timer: Implement
->set_state_oneshot_stopped()").
Fixes: 52762fbd1c47 ("clocksource/drivers/timer-ti-dm: Add clockevent and
clocksource support")
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20210304072135.52712-4-t...@atomide.com
---
drivers/clocksource/timer-ti-dm-systimer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
index 3a65434..186a599 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -554,6 +554,7 @@ static int __init dmtimer_clockevent_init(struct
device_node *np)
dev->set_state_shutdown = dmtimer_clockevent_shutdown;
dev->set_state_periodic = dmtimer_set_periodic;
dev->set_state_oneshot = dmtimer_clockevent_shutdown;
+ dev->set_state_oneshot_stopped = dmtimer_clockevent_shutdown;
dev->tick_resume = dmtimer_clockevent_shutdown;
dev->cpumask = cpu_possible_mask;
[tip: timers/core] clocksource/drivers/timer-ti-dm: Fix posted mode status check order
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 212709926c5493a566ca4086ad4f4b0d4e66b553
Gitweb:
https://git.kernel.org/tip/212709926c5493a566ca4086ad4f4b0d4e66b553
Author:Tony Lindgren
AuthorDate:Thu, 04 Mar 2021 09:21:33 +02:00
Committer: Daniel Lezcano
CommitterDate: Thu, 08 Apr 2021 13:23:41 +02:00
clocksource/drivers/timer-ti-dm: Fix posted mode status check order
When the timer is configured in posted mode, we need to check the write-
posted status register (TWPS) before writing to the register.
We now check TWPS after the write starting with commit 52762fbd1c47
("clocksource/drivers/timer-ti-dm: Add clockevent and clocksource
support").
For example, in the TRM for am571x the following is documented in chapter
"22.2.4.13.1.1 Write Posting Synchronization Mode":
"For each register, a status bit is provided in the timer write-posted
status (TWPS) register. In this mode, it is mandatory that software check
this status bit before any write access. If a write is attempted to a
register with a previous access pending, the previous access is discarded
without notice."
The regression happened when I updated the code to use standard read/write
accessors for the driver instead of using __omap_dm_timer_load_start().
We have__omap_dm_timer_load_start() check the TWPS status correctly using
__omap_dm_timer_write().
Fixes: 52762fbd1c47 ("clocksource/drivers/timer-ti-dm: Add clockevent and
clocksource support")
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20210304072135.52712-2-t...@atomide.com
---
drivers/clocksource/timer-ti-dm-systimer.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
index 614c838..3a65434 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -449,13 +449,13 @@ static int dmtimer_set_next_event(unsigned long cycles,
struct dmtimer_systimer *t = >t;
void __iomem *pend = t->base + t->pend;
- writel_relaxed(0x - cycles, t->base + t->counter);
while (readl_relaxed(pend) & WP_TCRR)
cpu_relax();
+ writel_relaxed(0x - cycles, t->base + t->counter);
- writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
while (readl_relaxed(pend) & WP_TCLR)
cpu_relax();
+ writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
return 0;
}
@@ -490,18 +490,18 @@ static int dmtimer_set_periodic(struct clock_event_device
*evt)
dmtimer_clockevent_shutdown(evt);
/* Looks like we need to first set the load value separately */
- writel_relaxed(clkevt->period, t->base + t->load);
while (readl_relaxed(pend) & WP_TLDR)
cpu_relax();
+ writel_relaxed(clkevt->period, t->base + t->load);
- writel_relaxed(clkevt->period, t->base + t->counter);
while (readl_relaxed(pend) & WP_TCRR)
cpu_relax();
+ writel_relaxed(clkevt->period, t->base + t->counter);
- writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
- t->base + t->ctrl);
while (readl_relaxed(pend) & WP_TCLR)
cpu_relax();
+ writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
+ t->base + t->ctrl);
return 0;
}
[tip: timers/core] clocksource/drivers/timer-ti-dm: Prepare to handle dra7 timer wrap issue
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 3efe7a878a11c13b5297057bfc1e5639ce1241ce
Gitweb:
https://git.kernel.org/tip/3efe7a878a11c13b5297057bfc1e5639ce1241ce
Author:Tony Lindgren
AuthorDate:Tue, 23 Mar 2021 09:43:25 +02:00
Committer: Daniel Lezcano
CommitterDate: Thu, 08 Apr 2021 16:15:54 +02:00
clocksource/drivers/timer-ti-dm: Prepare to handle dra7 timer wrap issue
There is a timer wrap issue on dra7 for the ARM architected timer.
In a typical clock configuration the timer fails to wrap after 388 days.
To work around the issue, we need to use timer-ti-dm timers instead.
Let's prepare for adding support for percpu timers by adding a common
dmtimer_clkevt_init_common() and call it from dmtimer_clockevent_init().
This patch makes no intentional functional changes.
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20210323074326.28302-2-t...@atomide.com
---
drivers/clocksource/timer-ti-dm-systimer.c | 66 +
1 file changed, 43 insertions(+), 23 deletions(-)
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
index 186a599..3308031 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -530,17 +530,17 @@ static void omap_clockevent_unidle(struct
clock_event_device *evt)
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
}
-static int __init dmtimer_clockevent_init(struct device_node *np)
+static int __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt,
+struct device_node *np,
+unsigned int features,
+const struct cpumask *cpumask,
+const char *name,
+int rating)
{
- struct dmtimer_clockevent *clkevt;
struct clock_event_device *dev;
struct dmtimer_systimer *t;
int error;
- clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL);
- if (!clkevt)
- return -ENOMEM;
-
t = >t;
dev = >dev;
@@ -548,25 +548,23 @@ static int __init dmtimer_clockevent_init(struct
device_node *np)
* We mostly use cpuidle_coupled with ARM local timers for runtime,
* so there's probably no use for CLOCK_EVT_FEAT_DYNIRQ here.
*/
- dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- dev->rating = 300;
+ dev->features = features;
+ dev->rating = rating;
dev->set_next_event = dmtimer_set_next_event;
dev->set_state_shutdown = dmtimer_clockevent_shutdown;
dev->set_state_periodic = dmtimer_set_periodic;
dev->set_state_oneshot = dmtimer_clockevent_shutdown;
dev->set_state_oneshot_stopped = dmtimer_clockevent_shutdown;
dev->tick_resume = dmtimer_clockevent_shutdown;
- dev->cpumask = cpu_possible_mask;
+ dev->cpumask = cpumask;
dev->irq = irq_of_parse_and_map(np, 0);
- if (!dev->irq) {
- error = -ENXIO;
- goto err_out_free;
- }
+ if (!dev->irq)
+ return -ENXIO;
error = dmtimer_systimer_setup(np, >t);
if (error)
- goto err_out_free;
+ return error;
clkevt->period = 0x - DIV_ROUND_CLOSEST(t->rate, HZ);
@@ -578,32 +576,54 @@ static int __init dmtimer_clockevent_init(struct
device_node *np)
writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl);
error = request_irq(dev->irq, dmtimer_clockevent_interrupt,
- IRQF_TIMER, "clockevent", clkevt);
+ IRQF_TIMER, name, clkevt);
if (error)
goto err_out_unmap;
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
- pr_info("TI gptimer clockevent: %s%lu Hz at %pOF\n",
- of_find_property(np, "ti,timer-alwon", NULL) ?
+ pr_info("TI gptimer %s: %s%lu Hz at %pOF\n",
+ name, of_find_property(np, "ti,timer-alwon", NULL) ?
"always-on " : "", t->rate, np->parent);
- clockevents_config_and_register(dev, t->rate,
+ return 0;
+
+err_out_unmap:
+ iounmap(t->base);
+
+ return error;
+}
+
+static int __init dmtimer_clockevent_init(struct device_node *np)
+{
+ struct dmtimer_clockevent *clkevt;
+ int error;
+
+ clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL);
+ if (!clkevt)
+ return -ENOMEM;
+
+ error = dmtimer_clkevt_init_common(clkevt, np,
+ CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT,
+
[tip: timers/core] clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 25de4ce5ed02994aea8bc111d133308f6fd62566
Gitweb:
https://git.kernel.org/tip/25de4ce5ed02994aea8bc111d133308f6fd62566
Author:Tony Lindgren
AuthorDate:Tue, 23 Mar 2021 09:43:26 +02:00
Committer: Daniel Lezcano
CommitterDate: Thu, 08 Apr 2021 16:41:18 +02:00
clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940
There is a timer wrap issue on dra7 for the ARM architected timer.
In a typical clock configuration the timer fails to wrap after 388 days.
To work around the issue, we need to use timer-ti-dm percpu timers instead.
Let's configure dmtimer3 and 4 as percpu timers by default, and warn about
the issue if the dtb is not configured properly.
Let's do this as a single patch so it can be backported to v5.8 and later
kernels easily. Note that this patch depends on earlier timer-ti-dm
systimer posted mode fixes, and a preparatory clockevent patch
"clocksource/drivers/timer-ti-dm: Prepare to handle dra7 timer wrap issue".
For more information, please see the errata for "AM572x Sitara Processors
Silicon Revisions 1.1, 2.0":
https://www.ti.com/lit/er/sprz429m/sprz429m.pdf
The concept is based on earlier reference patches done by Tero Kristo and
Keerthy.
Cc: Keerthy
Cc: Tero Kristo
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20210323074326.28302-3-t...@atomide.com
---
arch/arm/boot/dts/dra7-l4.dtsi | 4 +-
arch/arm/boot/dts/dra7.dtsi| 20 ++-
drivers/clocksource/timer-ti-dm-systimer.c | 76 +-
include/linux/cpuhotplug.h | 1 +-
4 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 3bf90d9..a294a02 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -1168,7 +1168,7 @@
};
};
- target-module@34000 { /* 0x48034000, ap 7
46.0 */
+ timer3_target: target-module@34000 {/* 0x48034000, ap 7
46.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x34000 0x4>,
<0x34010 0x4>;
@@ -1195,7 +1195,7 @@
};
};
- target-module@36000 { /* 0x48036000, ap 9
4e.0 */
+ timer4_target: target-module@36000 {/* 0x48036000, ap 9
4e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x36000 0x4>,
<0x36010 0x4>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ce11947..53d6878 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -46,6 +46,7 @@
timer {
compatible = "arm,armv7-timer";
+ status = "disabled";/* See ARM architected timer wrap
erratum i940 */
interrupts = ,
,
,
@@ -1241,3 +1242,22 @@
assigned-clock-parents = <_32k_ck>;
};
};
+
+/* Local timers, see ARM architected timer wrap erratum i940 */
+_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
+ assigned-clock-parents = <_sys_clk_div>;
+ };
+};
+
+_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
+ assigned-clock-parents = <_sys_clk_div>;
+ };
+};
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
index 3308031..b6f9796 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -2,6 +2,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -630,6 +631,78 @@ err_out_free:
return error;
}
+/* Dmtimer as percpu timer. See dra7 ARM architected timer wrap erratum i940 */
+static DEFINE_PER_CPU(struct dmtimer_clockevent, dmtimer_percpu_timer);
+
+static int __init dmtimer_percpu_timer_init(struct device_node *np, int cpu)
+{
+ struct dmtimer_clockevent *clkevt;
+ int error;
+
+ if (!cpu_possible(cpu))
+ return -EINVAL;
+
+ if (!of_property_read_bool(np->parent, "ti,no-reset-on-init") ||
+ !of_property_read_bool(np->parent, "ti,no-idle"))
+ pr_warn("Incomplete dtb for percpu dmtimer %pOF\n", np->parent);
+
+ clkevt = per_cpu_ptr(_percpu_timer, cpu);
+
+ error = dmtimer_clkevt_init_common(clkevt, np, CLOCK_EVT_FEAT_ONESHOT,
+ cpumask_of(cpu), "percpu-dmtimer",
+
[tip: timers/urgent] clocksource/drivers/timer-ti-dm: Do reset before enable
The following commit has been merged into the timers/urgent branch of tip:
Commit-ID: 164805157f3c6834670afbaff563353c773131f1
Gitweb:
https://git.kernel.org/tip/164805157f3c6834670afbaff563353c773131f1
Author:Tony Lindgren
AuthorDate:Mon, 17 Aug 2020 12:24:28 +03:00
Committer: Daniel Lezcano
CommitterDate: Mon, 24 Aug 2020 13:01:39 +02:00
clocksource/drivers/timer-ti-dm: Do reset before enable
Commit 6cfcd5563b4f ("clocksource/drivers/timer-ti-dm: Fix suspend and
resume for am3 and am4") exposed a new issue for type2 dual mode timers
on at least omap5 where the clockevent will stop when the SoC starts
entering idle states during the boot.
Turns out we are wrongly first enabling the system timer and then
resetting it, while we must also re-enable it after reset. The current
sequence leaves the timer module in a partially initialized state. This
issue went unnoticed earlier with ti-sysc driver reconfiguring the timer
module until we fixed the issue of ti-sysc reconfiguring system timers.
Let's fix the issue by calling dmtimer_systimer_enable() from reset for
both type1 and type2 timers, and switch the order of reset and enable in
dmtimer_systimer_setup(). Let's also move dmtimer_systimer_enable() and
dmtimer_systimer_disable() to do this without adding forward declarations.
Fixes: 6cfcd5563b4f ("clocksource/drivers/timer-ti-dm: Fix suspend and resume
for am3 and am4")
Reported-by: H. Nikolaus Schaller"
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20200817092428.6176-1-t...@atomide.com
---
drivers/clocksource/timer-ti-dm-systimer.c | 44 ++---
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
index f6fd1c1..33b3e8a 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -69,12 +69,33 @@ static bool dmtimer_systimer_revision1(struct
dmtimer_systimer *t)
return !(tidr >> 16);
}
+static void dmtimer_systimer_enable(struct dmtimer_systimer *t)
+{
+ u32 val;
+
+ if (dmtimer_systimer_revision1(t))
+ val = DMTIMER_TYPE1_ENABLE;
+ else
+ val = DMTIMER_TYPE2_ENABLE;
+
+ writel_relaxed(val, t->base + t->sysc);
+}
+
+static void dmtimer_systimer_disable(struct dmtimer_systimer *t)
+{
+ if (!dmtimer_systimer_revision1(t))
+ return;
+
+ writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);
+}
+
static int __init dmtimer_systimer_type1_reset(struct dmtimer_systimer *t)
{
void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;
int ret;
u32 l;
+ dmtimer_systimer_enable(t);
writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
ret = readl_poll_timeout_atomic(syss, l, l & BIT(0), 100,
DMTIMER_RESET_WAIT);
@@ -88,6 +109,7 @@ static int __init dmtimer_systimer_type2_reset(struct
dmtimer_systimer *t)
void __iomem *sysc = t->base + t->sysc;
u32 l;
+ dmtimer_systimer_enable(t);
l = readl_relaxed(sysc);
l |= BIT(0);
writel_relaxed(l, sysc);
@@ -336,26 +358,6 @@ static int __init dmtimer_systimer_init_clock(struct
dmtimer_systimer *t,
return 0;
}
-static void dmtimer_systimer_enable(struct dmtimer_systimer *t)
-{
- u32 val;
-
- if (dmtimer_systimer_revision1(t))
- val = DMTIMER_TYPE1_ENABLE;
- else
- val = DMTIMER_TYPE2_ENABLE;
-
- writel_relaxed(val, t->base + t->sysc);
-}
-
-static void dmtimer_systimer_disable(struct dmtimer_systimer *t)
-{
- if (!dmtimer_systimer_revision1(t))
- return;
-
- writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);
-}
-
static int __init dmtimer_systimer_setup(struct device_node *np,
struct dmtimer_systimer *t)
{
@@ -409,8 +411,8 @@ static int __init dmtimer_systimer_setup(struct device_node
*np,
t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET;
t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET;
- dmtimer_systimer_enable(t);
dmtimer_systimer_reset(t);
+ dmtimer_systimer_enable(t);
pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base),
readl_relaxed(t->base + t->sysc));
[tip: timers/urgent] clocksource/drivers/timer-ti-dm: Fix suspend and resume for am3 and am4
The following commit has been merged into the timers/urgent branch of tip:
Commit-ID: 6cfcd5563b4fadbf49ba8fa481978e5e86d30322
Gitweb:
https://git.kernel.org/tip/6cfcd5563b4fadbf49ba8fa481978e5e86d30322
Author:Tony Lindgren
AuthorDate:Mon, 13 Jul 2020 09:26:01 -07:00
Committer: Daniel Lezcano
CommitterDate: Tue, 21 Jul 2020 15:48:33 +02:00
clocksource/drivers/timer-ti-dm: Fix suspend and resume for am3 and am4
Carlos Hernandez reported that we now have a suspend and
resume regresssion on am3 and am4 compared to the earlier kernels. While
suspend and resume works with v5.8-rc3, we now get errors with rtcwake:
pm33xx pm33xx: PM: Could not transition all powerdomains to target state
...
rtcwake: write error
This is because we now fail to idle the system timer clocks that the
idle code checks and the error gets propagated to the rtcwake.
Turns out there are several issues that need to be fixed:
1. Ignore no-idle and no-reset configured timers for the ti-sysc
interconnect target driver as otherwise it will keep the system timer
clocks enabled
2. Toggle the system timer functional clock for suspend for am3 and am4
(but not for clocksource on am3)
3. Only reconfigure type1 timers in dmtimer_systimer_disable()
4. Use of_machine_is_compatible() instead of of_device_is_compatible()
for checking the SoC type
Fixes: 52762fbd1c47 ("clocksource/drivers/timer-ti-dm: Add clockevent and
clocksource support")
Reported-by: Carlos Hernandez
Signed-off-by: Tony Lindgren
Tested-by: Carlos Hernandez
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20200713162601.6829-1-t...@atomide.com
---
drivers/bus/ti-sysc.c | 22 ++-
drivers/clocksource/timer-ti-dm-systimer.c | 46 -
2 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
index bb54fb5..c6427d0 100644
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -2864,6 +2864,24 @@ static int sysc_check_disabled_devices(struct sysc
*ddata)
return error;
}
+/*
+ * Ignore timers tagged with no-reset and no-idle. These are likely in use,
+ * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
+ * are needed, we could also look at the timer register configuration.
+ */
+static int sysc_check_active_timer(struct sysc *ddata)
+{
+ if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
+ ddata->cap->type != TI_SYSC_OMAP4_TIMER)
+ return 0;
+
+ if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
+ (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
+ return -EBUSY;
+
+ return 0;
+}
+
static const struct of_device_id sysc_match_table[] = {
{ .compatible = "simple-bus", },
{ /* sentinel */ },
@@ -2920,6 +2938,10 @@ static int sysc_probe(struct platform_device *pdev)
if (error)
return error;
+ error = sysc_check_active_timer(ddata);
+ if (error)
+ return error;
+
error = sysc_get_clocks(ddata);
if (error)
return error;
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
index 6fd1f21..f6fd1c1 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -19,7 +19,7 @@
/* For type1, set SYSC_OMAP2_CLOCKACTIVITY for fck off on idle, l4 clock on */
#define DMTIMER_TYPE1_ENABLE ((1 << 9) | (SYSC_IDLE_SMART << 3) | \
SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_AUTOIDLE)
-
+#define DMTIMER_TYPE1_DISABLE (SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)
#define DMTIMER_TYPE2_ENABLE (SYSC_IDLE_SMART_WKUP << 2)
#define DMTIMER_RESET_WAIT 10
@@ -44,6 +44,8 @@ struct dmtimer_systimer {
u8 ctrl;
u8 wakeup;
u8 ifctrl;
+ struct clk *fck;
+ struct clk *ick;
unsigned long rate;
};
@@ -298,16 +300,20 @@ static void __init dmtimer_systimer_select_best(void)
}
/* Interface clocks are only available on some SoCs variants */
-static int __init dmtimer_systimer_init_clock(struct device_node *np,
+static int __init dmtimer_systimer_init_clock(struct dmtimer_systimer *t,
+ struct device_node *np,
const char *name,
unsigned long *rate)
{
struct clk *clock;
unsigned long r;
+ bool is_ick = false;
int error;
+ is_ick = !strncmp(name, "ick", 3);
+
clock = of_clk_get_by_name(np, name);
- if ((PTR_ERR(clock) == -EINVAL) && !strncmp(name, "ick", 3))
+ if ((PTR_ERR(clock) == -EINVAL) && is_ick)
return 0;
else if (IS_ERR(clock))
return PTR_ERR(clock);
@@ -320,6 +326,11 @@ static int __init dmtimer_systimer_init_clock(struct
device_node *np,
[tip: timers/core] clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 52762fbd1c4778ac9b173624ca0faacd22ef4724
Gitweb:
https://git.kernel.org/tip/52762fbd1c4778ac9b173624ca0faacd22ef4724
Author:Tony Lindgren
AuthorDate:Thu, 07 May 2020 10:23:18 -07:00
Committer: Daniel Lezcano
CommitterDate: Sat, 23 May 2020 00:01:04 +02:00
clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support
We can move the TI dmtimer clockevent and clocksource to live under
drivers/clocksource if we rely only on the clock framework, and handle
the module configuration directly in the clocksource driver based on the
device tree data.
This removes the early dependency with system timers to the interconnect
related code, and we can probe pretty much everything else later on at
the module_init level.
Let's first add a new driver for timer-ti-dm-systimer based on existing
arch/arm/mach-omap2/timer.c. Then let's start moving SoCs to probe with
device tree data while still keeping the old timer.c. And eventually we
can just drop the old timer.c.
Let's take the opportunity to switch to use readl/writel as pointed out
by Daniel Lezcano . This allows further
clean-up of the timer-ti-dm code the a lot of the shared helpers can
just become static to the non-syster related code.
Note the boards can optionally configure different timer source clocks
if needed with assigned-clocks and assigned-clock-parents.
Cc: linux-kernel@vger.kernel.org
Cc: linux-o...@vger.kernel.org
Cc: Daniel Lezcano
Cc: Grygorii Strashko
Cc: Keerthy
Cc: Lokesh Vutla
Cc: Rob Herring
Cc: Tero Kristo
Cc: Thomas Gleixner
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20200507172330.18679-3-t...@atomide.com
---
drivers/clocksource/Makefile | 1 +-
drivers/clocksource/timer-ti-dm-systimer.c | 731 -
2 files changed, 732 insertions(+)
create mode 100644 drivers/clocksource/timer-ti-dm-systimer.c
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 641ba53..bdda1a2 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
obj-$(CONFIG_DAVINCI_TIMER)+= timer-davinci.o
obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
obj-$(CONFIG_OMAP_DM_TIMER)+= timer-ti-dm.o
+obj-$(CONFIG_OMAP_DM_TIMER)+= timer-ti-dm-systimer.o
obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
new file mode 100644
index 000..1495618
--- /dev/null
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -0,0 +1,731 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+
+/* For type1, set SYSC_OMAP2_CLOCKACTIVITY for fck off on idle, l4 clock on */
+#define DMTIMER_TYPE1_ENABLE ((1 << 9) | (SYSC_IDLE_SMART << 3) | \
+SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_AUTOIDLE)
+
+#define DMTIMER_TYPE2_ENABLE (SYSC_IDLE_SMART_WKUP << 2)
+#define DMTIMER_RESET_WAIT 10
+
+#define DMTIMER_INST_DONT_CARE ~0U
+
+static int counter_32k;
+static u32 clocksource;
+static u32 clockevent;
+
+/*
+ * Subset of the timer registers we use. Note that the register offsets
+ * depend on the timer revision detected.
+ */
+struct dmtimer_systimer {
+ void __iomem *base;
+ u8 sysc;
+ u8 irq_stat;
+ u8 irq_ena;
+ u8 pend;
+ u8 load;
+ u8 counter;
+ u8 ctrl;
+ u8 wakeup;
+ u8 ifctrl;
+ unsigned long rate;
+};
+
+struct dmtimer_clockevent {
+ struct clock_event_device dev;
+ struct dmtimer_systimer t;
+ u32 period;
+};
+
+struct dmtimer_clocksource {
+ struct clocksource dev;
+ struct dmtimer_systimer t;
+ unsigned int loadval;
+};
+
+/* Assumes v1 ip if bits [31:16] are zero */
+static bool dmtimer_systimer_revision1(struct dmtimer_systimer *t)
+{
+ u32 tidr = readl_relaxed(t->base);
+
+ return !(tidr >> 16);
+}
+
+static int __init dmtimer_systimer_type1_reset(struct dmtimer_systimer *t)
+{
+ void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;
+ int ret;
+ u32 l;
+
+ writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
+ ret = readl_poll_timeout_atomic(syss, l, l & BIT(0), 100,
+ DMTIMER_RESET_WAIT);
+
+ return ret;
+}
+
+/* Note we must use io_base instead of func_base for type2 OCP regs */
+static int __init dmtimer_systimer_type2_reset(struct dmtimer_systimer *t)
+{
+ void __iomem *sysc = t->base + t->sysc;
+ u32 l;
+
+ l = readl_relaxed(sysc);
+ l |= BIT(0);
+
[tip: timers/core] clocksource/drivers/timer-ti-32k: Add support for initializing directly
The following commit has been merged into the timers/core branch of tip:
Commit-ID: d15483bb49bae0f9cbb67c54becec252545752d3
Gitweb:
https://git.kernel.org/tip/d15483bb49bae0f9cbb67c54becec252545752d3
Author:Tony Lindgren
AuthorDate:Thu, 07 May 2020 10:23:17 -07:00
Committer: Daniel Lezcano
CommitterDate: Mon, 18 May 2020 18:56:35 +02:00
clocksource/drivers/timer-ti-32k: Add support for initializing directly
Let's allow probing the 32k counter directly based on devicetree data to
prepare for dropping the related legacy platform code. Let's only do this
if the parent node is compatible with ti-sysc to make sure we have the
related devicetree data available.
Let's also show the 32k counter information before registering the
clocksource, now we see it after the clocksource information which is a
bit confusing.
Cc: linux-kernel@vger.kernel.org
Cc: linux-o...@vger.kernel.org
Cc: Daniel Lezcano
Cc: Grygorii Strashko
Cc: Keerthy
Cc: Lokesh Vutla
Cc: Rob Herring
Cc: Tero Kristo
Cc: Thomas Gleixner
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20200507172330.18679-2-t...@atomide.com
---
drivers/clocksource/timer-ti-32k.c | 48 -
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-ti-32k.c
b/drivers/clocksource/timer-ti-32k.c
index abd5f15..ae12bbf 100644
--- a/drivers/clocksource/timer-ti-32k.c
+++ b/drivers/clocksource/timer-ti-32k.c
@@ -24,6 +24,7 @@
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
*/
+#include
#include
#include
#include
@@ -76,6 +77,49 @@ static u64 notrace omap_32k_read_sched_clock(void)
return ti_32k_read_cycles(_32k_timer.cs);
}
+static void __init ti_32k_timer_enable_clock(struct device_node *np,
+const char *name)
+{
+ struct clk *clock;
+ int error;
+
+ clock = of_clk_get_by_name(np->parent, name);
+ if (IS_ERR(clock)) {
+ /* Only some SoCs have a separate interface clock */
+ if (PTR_ERR(clock) == -EINVAL && !strncmp("ick", name, 3))
+ return;
+
+ pr_warn("%s: could not get clock %s %li\n",
+ __func__, name, PTR_ERR(clock));
+ return;
+ }
+
+ error = clk_prepare_enable(clock);
+ if (error) {
+ pr_warn("%s: could not enable %s: %i\n",
+ __func__, name, error);
+ return;
+ }
+}
+
+static void __init ti_32k_timer_module_init(struct device_node *np,
+ void __iomem *base)
+{
+ void __iomem *sysc = base + 4;
+
+ if (!of_device_is_compatible(np->parent, "ti,sysc"))
+ return;
+
+ ti_32k_timer_enable_clock(np, "fck");
+ ti_32k_timer_enable_clock(np, "ick");
+
+ /*
+* Force idle module as wkup domain is active with MPU.
+* No need to tag the module disabled for ti-sysc probe.
+*/
+ writel_relaxed(0, sysc);
+}
+
static int __init ti_32k_timer_init(struct device_node *np)
{
int ret;
@@ -90,6 +134,7 @@ static int __init ti_32k_timer_init(struct device_node *np)
ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
ti_32k_timer.counter = ti_32k_timer.base;
+ ti_32k_timer_module_init(np, ti_32k_timer.base);
/*
* 32k sync Counter IP register offsets vary between the highlander
@@ -104,6 +149,8 @@ static int __init ti_32k_timer_init(struct device_node *np)
else
ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
+ pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
+
ret = clocksource_register_hz(_32k_timer.cs, 32768);
if (ret) {
pr_err("32k_counter: can't register clocksource\n");
@@ -111,7 +158,6 @@ static int __init ti_32k_timer_init(struct device_node *np)
}
sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
- pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
return 0;
}
[tip: timers/core] clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support
The following commit has been merged into the timers/core branch of tip:
Commit-ID: aba1ad05da088944a62eb87fb0cd8391152e8985
Gitweb:
https://git.kernel.org/tip/aba1ad05da088944a62eb87fb0cd8391152e8985
Author:Tony Lindgren
AuthorDate:Thu, 07 May 2020 10:23:18 -07:00
Committer: Daniel Lezcano
CommitterDate: Mon, 18 May 2020 18:56:35 +02:00
clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support
We can move the TI dmtimer clockevent and clocksource to live under
drivers/clocksource if we rely only on the clock framework, and handle
the module configuration directly in the clocksource driver based on the
device tree data.
This removes the early dependency with system timers to the interconnect
related code, and we can probe pretty much everything else later on at
the module_init level.
Let's first add a new driver for timer-ti-dm-systimer based on existing
arch/arm/mach-omap2/timer.c. Then let's start moving SoCs to probe with
device tree data while still keeping the old timer.c. And eventually we
can just drop the old timer.c.
Let's take the opportunity to switch to use readl/writel as pointed out
by Daniel Lezcano . This allows further
clean-up of the timer-ti-dm code the a lot of the shared helpers can
just become static to the non-syster related code.
Note the boards can optionally configure different timer source clocks
if needed with assigned-clocks and assigned-clock-parents.
Cc: linux-kernel@vger.kernel.org
Cc: linux-o...@vger.kernel.org
Cc: Daniel Lezcano
Cc: Grygorii Strashko
Cc: Keerthy
Cc: Lokesh Vutla
Cc: Rob Herring
Cc: Tero Kristo
Cc: Thomas Gleixner
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20200507172330.18679-3-t...@atomide.com
---
drivers/clocksource/Makefile | 1 +-
drivers/clocksource/timer-ti-dm-systimer.c | 731 -
2 files changed, 732 insertions(+)
create mode 100644 drivers/clocksource/timer-ti-dm-systimer.c
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 641ba53..bdda1a2 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
obj-$(CONFIG_DAVINCI_TIMER)+= timer-davinci.o
obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
obj-$(CONFIG_OMAP_DM_TIMER)+= timer-ti-dm.o
+obj-$(CONFIG_OMAP_DM_TIMER)+= timer-ti-dm-systimer.o
obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
new file mode 100644
index 000..1495618
--- /dev/null
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -0,0 +1,731 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+
+/* For type1, set SYSC_OMAP2_CLOCKACTIVITY for fck off on idle, l4 clock on */
+#define DMTIMER_TYPE1_ENABLE ((1 << 9) | (SYSC_IDLE_SMART << 3) | \
+SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_AUTOIDLE)
+
+#define DMTIMER_TYPE2_ENABLE (SYSC_IDLE_SMART_WKUP << 2)
+#define DMTIMER_RESET_WAIT 10
+
+#define DMTIMER_INST_DONT_CARE ~0U
+
+static int counter_32k;
+static u32 clocksource;
+static u32 clockevent;
+
+/*
+ * Subset of the timer registers we use. Note that the register offsets
+ * depend on the timer revision detected.
+ */
+struct dmtimer_systimer {
+ void __iomem *base;
+ u8 sysc;
+ u8 irq_stat;
+ u8 irq_ena;
+ u8 pend;
+ u8 load;
+ u8 counter;
+ u8 ctrl;
+ u8 wakeup;
+ u8 ifctrl;
+ unsigned long rate;
+};
+
+struct dmtimer_clockevent {
+ struct clock_event_device dev;
+ struct dmtimer_systimer t;
+ u32 period;
+};
+
+struct dmtimer_clocksource {
+ struct clocksource dev;
+ struct dmtimer_systimer t;
+ unsigned int loadval;
+};
+
+/* Assumes v1 ip if bits [31:16] are zero */
+static bool dmtimer_systimer_revision1(struct dmtimer_systimer *t)
+{
+ u32 tidr = readl_relaxed(t->base);
+
+ return !(tidr >> 16);
+}
+
+static int __init dmtimer_systimer_type1_reset(struct dmtimer_systimer *t)
+{
+ void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;
+ int ret;
+ u32 l;
+
+ writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
+ ret = readl_poll_timeout_atomic(syss, l, l & BIT(0), 100,
+ DMTIMER_RESET_WAIT);
+
+ return ret;
+}
+
+/* Note we must use io_base instead of func_base for type2 OCP regs */
+static int __init dmtimer_systimer_type2_reset(struct dmtimer_systimer *t)
+{
+ void __iomem *sysc = t->base + t->sysc;
+ u32 l;
+
+ l = readl_relaxed(sysc);
+ l |= BIT(0);
+
[tip: timers/core] clocksource/drivers/timer-ti-32k: Add support for initializing directly
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 46b30515f97ece3da661b251e4a0ad9ac7a338d3
Gitweb:
https://git.kernel.org/tip/46b30515f97ece3da661b251e4a0ad9ac7a338d3
Author:Tony Lindgren
AuthorDate:Thu, 07 May 2020 10:23:17 -07:00
Committer: Daniel Lezcano
CommitterDate: Sat, 23 May 2020 00:01:04 +02:00
clocksource/drivers/timer-ti-32k: Add support for initializing directly
Let's allow probing the 32k counter directly based on devicetree data to
prepare for dropping the related legacy platform code. Let's only do this
if the parent node is compatible with ti-sysc to make sure we have the
related devicetree data available.
Let's also show the 32k counter information before registering the
clocksource, now we see it after the clocksource information which is a
bit confusing.
Cc: linux-kernel@vger.kernel.org
Cc: linux-o...@vger.kernel.org
Cc: Daniel Lezcano
Cc: Grygorii Strashko
Cc: Keerthy
Cc: Lokesh Vutla
Cc: Rob Herring
Cc: Tero Kristo
Cc: Thomas Gleixner
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20200507172330.18679-2-t...@atomide.com
---
drivers/clocksource/timer-ti-32k.c | 48 -
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-ti-32k.c
b/drivers/clocksource/timer-ti-32k.c
index abd5f15..ae12bbf 100644
--- a/drivers/clocksource/timer-ti-32k.c
+++ b/drivers/clocksource/timer-ti-32k.c
@@ -24,6 +24,7 @@
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
*/
+#include
#include
#include
#include
@@ -76,6 +77,49 @@ static u64 notrace omap_32k_read_sched_clock(void)
return ti_32k_read_cycles(_32k_timer.cs);
}
+static void __init ti_32k_timer_enable_clock(struct device_node *np,
+const char *name)
+{
+ struct clk *clock;
+ int error;
+
+ clock = of_clk_get_by_name(np->parent, name);
+ if (IS_ERR(clock)) {
+ /* Only some SoCs have a separate interface clock */
+ if (PTR_ERR(clock) == -EINVAL && !strncmp("ick", name, 3))
+ return;
+
+ pr_warn("%s: could not get clock %s %li\n",
+ __func__, name, PTR_ERR(clock));
+ return;
+ }
+
+ error = clk_prepare_enable(clock);
+ if (error) {
+ pr_warn("%s: could not enable %s: %i\n",
+ __func__, name, error);
+ return;
+ }
+}
+
+static void __init ti_32k_timer_module_init(struct device_node *np,
+ void __iomem *base)
+{
+ void __iomem *sysc = base + 4;
+
+ if (!of_device_is_compatible(np->parent, "ti,sysc"))
+ return;
+
+ ti_32k_timer_enable_clock(np, "fck");
+ ti_32k_timer_enable_clock(np, "ick");
+
+ /*
+* Force idle module as wkup domain is active with MPU.
+* No need to tag the module disabled for ti-sysc probe.
+*/
+ writel_relaxed(0, sysc);
+}
+
static int __init ti_32k_timer_init(struct device_node *np)
{
int ret;
@@ -90,6 +134,7 @@ static int __init ti_32k_timer_init(struct device_node *np)
ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
ti_32k_timer.counter = ti_32k_timer.base;
+ ti_32k_timer_module_init(np, ti_32k_timer.base);
/*
* 32k sync Counter IP register offsets vary between the highlander
@@ -104,6 +149,8 @@ static int __init ti_32k_timer_init(struct device_node *np)
else
ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
+ pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
+
ret = clocksource_register_hz(_32k_timer.cs, 32768);
if (ret) {
pr_err("32k_counter: can't register clocksource\n");
@@ -111,7 +158,6 @@ static int __init ti_32k_timer_init(struct device_node *np)
}
sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
- pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
return 0;
}
[tip: timers/core] clocksource/drivers/timer-ti-dm: Fix warning for set but not used
The following commit has been merged into the timers/core branch of tip:
Commit-ID: c177e2975430cec296aa52a0d413e447417d6cf9
Gitweb:
https://git.kernel.org/tip/c177e2975430cec296aa52a0d413e447417d6cf9
Author:Tony Lindgren
AuthorDate:Tue, 19 May 2020 08:51:57 -07:00
Committer: Daniel Lezcano
CommitterDate: Sat, 23 May 2020 00:01:05 +02:00
clocksource/drivers/timer-ti-dm: Fix warning for set but not used
We can get a warning for dmtimer_clocksource_init() with 'pa' set but
not used. This was used in the earlier revisions of the code but no
longer needed, so let's remove the unused pa and of_translate_address().
Let's also do it for dmtimer_clockevent_init() that has a similar issue.
Reported-by: kbuild test robot
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20200519155157.12804-1-t...@atomide.com
---
drivers/clocksource/timer-ti-dm-systimer.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
index 1495618..7da998d 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -514,7 +514,6 @@ static int __init dmtimer_clockevent_init(struct
device_node *np)
struct clock_event_device *dev;
struct dmtimer_systimer *t;
int error;
- u32 pa;
clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL);
if (!clkevt)
@@ -563,7 +562,6 @@ static int __init dmtimer_clockevent_init(struct
device_node *np)
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
- pa = of_translate_address(np, of_get_address(np, 0, NULL, NULL));
pr_info("TI gptimer clockevent: %s%lu Hz at %pOF\n",
of_find_property(np, "ti,timer-alwon", NULL) ?
"always-on " : "", t->rate, np->parent);
@@ -637,7 +635,6 @@ static int __init dmtimer_clocksource_init(struct
device_node *np)
struct dmtimer_systimer *t;
struct clocksource *dev;
int error;
- u32 pa;
clksrc = kzalloc(sizeof(*clksrc), GFP_KERNEL);
if (!clksrc)
@@ -666,7 +663,6 @@ static int __init dmtimer_clocksource_init(struct
device_node *np)
writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
t->base + t->ctrl);
- pa = of_translate_address(np, of_get_address(np, 0, NULL, NULL));
pr_info("TI gptimer clocksource: %s%pOF\n",
of_find_property(np, "ti,timer-alwon", NULL) ?
"always-on " : "", np->parent);
[tip: timers/core] clocksource/drivers/timer-ti-dm: Fix warning for set but not used
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 6d15120b282e49811a47f2f6d6b749d178be7e99
Gitweb:
https://git.kernel.org/tip/6d15120b282e49811a47f2f6d6b749d178be7e99
Author:Tony Lindgren
AuthorDate:Tue, 19 May 2020 08:51:57 -07:00
Committer: Daniel Lezcano
CommitterDate: Tue, 19 May 2020 18:23:50 +02:00
clocksource/drivers/timer-ti-dm: Fix warning for set but not used
We can get a warning for dmtimer_clocksource_init() with 'pa' set but
not used. This was used in the earlier revisions of the code but no
longer needed, so let's remove the unused pa and of_translate_address().
Let's also do it for dmtimer_clockevent_init() that has a similar issue.
Reported-by: kbuild test robot
Signed-off-by: Tony Lindgren
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20200519155157.12804-1-t...@atomide.com
---
drivers/clocksource/timer-ti-dm-systimer.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/clocksource/timer-ti-dm-systimer.c
b/drivers/clocksource/timer-ti-dm-systimer.c
index 1495618..7da998d 100644
--- a/drivers/clocksource/timer-ti-dm-systimer.c
+++ b/drivers/clocksource/timer-ti-dm-systimer.c
@@ -514,7 +514,6 @@ static int __init dmtimer_clockevent_init(struct
device_node *np)
struct clock_event_device *dev;
struct dmtimer_systimer *t;
int error;
- u32 pa;
clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL);
if (!clkevt)
@@ -563,7 +562,6 @@ static int __init dmtimer_clockevent_init(struct
device_node *np)
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
- pa = of_translate_address(np, of_get_address(np, 0, NULL, NULL));
pr_info("TI gptimer clockevent: %s%lu Hz at %pOF\n",
of_find_property(np, "ti,timer-alwon", NULL) ?
"always-on " : "", t->rate, np->parent);
@@ -637,7 +635,6 @@ static int __init dmtimer_clocksource_init(struct
device_node *np)
struct dmtimer_systimer *t;
struct clocksource *dev;
int error;
- u32 pa;
clksrc = kzalloc(sizeof(*clksrc), GFP_KERNEL);
if (!clksrc)
@@ -666,7 +663,6 @@ static int __init dmtimer_clocksource_init(struct
device_node *np)
writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
t->base + t->ctrl);
- pa = of_translate_address(np, of_get_address(np, 0, NULL, NULL));
pr_info("TI gptimer clocksource: %s%pOF\n",
of_find_property(np, "ti,timer-alwon", NULL) ?
"always-on " : "", np->parent);
