Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-09-06 22:02, Sai Prakash Ranjan wrote:
On 9/7/2018 4:01 AM, vnkgu...@codeaurora.org wrote:
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this
compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
It does not require a separate binding, what I meant was to add this
compatible in the llcc binding itself, maybe as a subnode if it is
correct.
Hi,
We aren't really using this of_device_id structure, as this driver is
being registered from LLCC through
platform_register_device_data(...). This structure initialization is
just dead code as this driver won't be probed based on the DT entries.
Hence removing this compatible property and the corresponding struct in
the next patchset.
So, this doesn't need an extra binding/documentation.
Re: [PATCH v4 4/4] dt-bindings: msm: Update documentation of qcom,llcc
On 2018-09-06 06:16, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.
Signed-off-by: Venkata Narendra Kumar Gutta
Reviewed-by: Rob Herring
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 19
+--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..2e007dc 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -16,11 +16,26 @@ Properties:
- reg:
Usage: required
Value Type:
- Definition: Start address and the the size of the register region.
+ Definition: The first element specifies the llcc base start address
and
+ the size of the register region. The second element
specifies
+ the llcc broadcast base address and size of the register
region.
+
+- reg-names:
+Usage: required
+Value Type:
+Definition: Register region names. Must be "llcc_base",
"llcc_bcast_base".
+
+- interrupts:
+ Usage: required
+ Definition: The interrupt is associated with the llcc edac device.
+ It's used for llcc cache single and double bit error
detection
+ and reporting.
Example:
cache-controller@110 {
compatible = "qcom,sdm845-llcc";
- reg = <0x110 0x25>;
+ reg = <0x110 0x20>, <0x130 0x5> ;
+ reg-names = "llcc_base", "llcc_bcast_base";
+ interrupts = ;
};
Also, llcc_bcast_base should be llcc_broadcast_base as given in Patch
1 or you can change to llcc_bcast_base in Patch 1 of series.
My bad, I'll correct that in the next series.
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
Regards,
Sai
Re: [PATCH v3 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-08-30 05:11, Borislav Petkov wrote:
On Tue, Aug 28, 2018 at 05:42:26PM -0700, Venkata Narendra Kumar Gutta
wrote:
From: Channagoud Kadabi
Add error reporting driver for Single Bit Errors (SBEs) and Double Bit
Errors (DBEs). As of now, this driver supports error reporting for
Last Level Cache Controller (LLCC) of Tag RAM and Data RAM. Interrupts
are triggered when the errors happen in the cache, the driver handles
those interrupts and dumps the syndrome registers.
Signed-off-by: Channagoud Kadabi
Signed-off-by: Venkata Narendra Kumar Gutta
Co-developed-by: Venkata Narendra Kumar Gutta
---
MAINTAINERS| 8 +
drivers/edac/Kconfig | 22 ++
drivers/edac/Makefile | 1 +
drivers/edac/qcom_edac.c | 421
+
include/linux/soc/qcom/llcc-qcom.h | 24 +++
5 files changed, 476 insertions(+)
create mode 100644 drivers/edac/qcom_edac.c
We'd also need an agreement who picks up the whole pile?
Andy should take care of it.
(Andy Gross (maintainer:ARM/QUALCOMM SUPPORT))
Those guys:
Andy Gross (maintainer:ARM/QUALCOMM SUPPORT)
David Brown (maintainer:ARM/QUALCOMM SUPPORT)
and I ACK the EDAC driver or I do and they ACK the soc pieces.
I have a hunch the prior would be easier...
You can ACK the EDAC driver, rest should be taken care by
Andy or Bjorn Andersson
diff --git a/MAINTAINERS b/MAINTAINERS
index 0a23427..0bff713 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5227,6 +5227,14 @@ L: linux-e...@vger.kernel.org
S: Maintained
F: drivers/edac/ti_edac.c
+EDAC-QUALCOMM
+M: Channagoud Kadabi
+M: Venkata Narendra Kumar Gutta
+L: linux-arm-...@vger.kernel.org
+L: linux-e...@vger.kernel.org
+S: Maintained
+F: drivers/edac/qcom_edac.c
+
EDIROL UA-101/UA-1000 DRIVER
M: Clemens Ladisch
L: alsa-de...@alsa-project.org (moderated for non-subscribers)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 57304b2..df58957 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -460,4 +460,26 @@ config EDAC_TI
Support for error detection and correction on the
TI SoCs.
+config EDAC_QCOM
+ tristate "QCOM EDAC Controller"
+ depends on EDAC
+ help
+ Support for error detection and correction on the
+ QCOM SoCs.
+
+ This driver reports Single Bit Errors (SBEs) and Double Bit Errors
(DBEs).
+ As of now, it supports error reporting for Last Level Cache
Controller (LLCC)
+ of Tag RAM and Data RAM.
+
+config EDAC_QCOM_LLCC
+ tristate "QCOM EDAC Controller for LLCC Cache"
+ depends on EDAC_QCOM && QCOM_LLCC
This is just silly: two EDAC config options for a single driver and
this
second one only does:
#ifdef EDAC_QCOM_LLCC
{ .compatible = "qcom,llcc-edac" },
#endif
What for?!
You do this:
config EDAC_QCOM
depends on && QCOM_LLCC
and that's it.
Done, I'll update it the next patch set.
...
+/* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
+static int
+dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int
err_type)
+{
+ struct llcc_edac_reg_data reg_data = edac_reg_data[err_type];
+ int err_cnt, err_ways, ret, i;
+ u32 synd_reg, synd_val;
+
+ for (i = 0; i < reg_data.reg_cnt; i++) {
+ synd_reg = reg_data.synd_reg + (i * 4);
+ ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+ &synd_val);
+ if (ret)
+ goto clear;
<- newline here.
OK
+ edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 0x%8x\n",
+ reg_data.name, i, synd_val);
+ }
+
+ ret = regmap_read(drv->regmap,
+ drv->offsets[bank] + reg_data.count_status_reg,
+ &err_cnt);
+ if (ret)
+ goto clear;
+
+ err_cnt &= reg_data.count_mask;
+ err_cnt >>= reg_data.count_shift;
+ edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error count: 0x%4x\n",
+ reg_data.name, err_cnt);
+
+ ret = regmap_read(drv->regmap,
+ drv->offsets[bank] + reg_data.ways_status_reg,
+ &err_ways);
+ if (ret)
+ goto clear;
+
+ err_ways &= reg_data.ways_mask;
+ err_ways >>= reg_data.ways_shift;
+
+ edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error ways: 0x%4x\n",
+ reg_data.name, err_ways);
+
+clear:
+ return qcom_llcc_clear_error_status(err_type, drv);
+}
+
+static int
+dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32
bank)
+{
+ struct llcc_drv_data *drv = edev_ctl->pvt_info;
+ int ret;
+
+ ret = dump_syn_reg_values(drv, bank, err_type);
+ if (ret)
+ return ret;
+
+ switch (err_type) {
+ case LLCC_DRAM_CE:
+
Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-08-24 13:18, Evan Green wrote: On Fri, Aug 24, 2018 at 11:32 AM wrote: On 2018-08-23 16:04, Evan Green wrote: > On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta > wrote: >> >> From: Channagoud Kadabi >> >> Add error reporting driver for Single Bit Errors (SBEs) and Double Bit >> Errors (DBEs). As of now, this driver supports erp for Last Level >> Cache >> Controller (LLCC). This driver takes care of dumping registers and >> adding >> config options to enable and disable panic when the errors happen in >> cache. >> >> Signed-off-by: Channagoud Kadabi >> Signed-off-by: Venkata Narendra Kumar Gutta >> Co-developed-by: Venkata Narendra Kumar Gutta >> >> --- >> MAINTAINERS| 8 + >> drivers/edac/Kconfig | 28 +++ >> drivers/edac/Makefile | 1 + >> drivers/edac/qcom_edac.c | 446 >> + >> include/linux/soc/qcom/llcc-qcom.h | 25 +++ >> 5 files changed, 508 insertions(+) >> create mode 100644 drivers/edac/qcom_edac.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 0a23427..0bff713 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -5227,6 +5227,14 @@ L: linux-e...@vger.kernel.org >> S: Maintained >> F: drivers/edac/ti_edac.c >> >> +EDAC-QUALCOMM >> +M: Channagoud Kadabi >> +M: Venkata Narendra Kumar Gutta >> +L: linux-arm-...@vger.kernel.org >> +L: linux-e...@vger.kernel.org >> +S: Maintained >> +F: drivers/edac/qcom_edac.c >> + >> EDIROL UA-101/UA-1000 DRIVER >> M: Clemens Ladisch >> L: alsa-de...@alsa-project.org (moderated for non-subscribers) >> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig >> index 57304b2..da8f150 100644 >> --- a/drivers/edac/Kconfig >> +++ b/drivers/edac/Kconfig >> @@ -460,4 +460,32 @@ config EDAC_TI >> Support for error detection and correction on the >>TI SoCs. >> >> +config EDAC_QCOM >> + tristate "QCOM EDAC Controller" >> + depends on EDAC >> + help >> + Support for error detection and correction on the >> + QCOM SoCs. >> + >> +config EDAC_QCOM_LLCC >> + tristate "QCOM EDAC Controller for LLCC Cache" >> + depends on EDAC_QCOM && QCOM_LLCC >> + help >> + Support for error detection and correction on the >> + QCOM LLCC cache. Report errors caught by LLCC ECC >> + mechanism. >> + >> + For debugging issues having to do with stability and overall >> system >> + health, you should probably say 'Y' here. >> + >> +config EDAC_QCOM_LLCC_PANIC_ON_UE >> + bool "Panic on uncorrectable errors - qcom llcc" >> + depends on EDAC_QCOM_LLCC >> + help >> + Forcibly cause a kernel panic if an uncorrectable error (UE) >> is >> + detected. This can reduce debugging times on hardware which >> may be >> + operating at voltages or frequencies outside normal >> specification. >> + >> + For production builds, you should probably say 'N' here. >> + >> endif # EDAC >> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile >> index 02b43a7..716096d 100644 >> --- a/drivers/edac/Makefile >> +++ b/drivers/edac/Makefile >> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += >> altera_edac.o >> obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o >> obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o >> obj-$(CONFIG_EDAC_TI) += ti_edac.o >> +obj-$(CONFIG_EDAC_QCOM)+= qcom_edac.o >> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c >> new file mode 100644 >> index 000..9a8c670 >> --- /dev/null >> +++ b/drivers/edac/qcom_edac.c >> @@ -0,0 +1,446 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2018, The Linux Foundation. All rights reserved. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "edac_mc.h" >> +#include "edac_device.h" >> + >> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE >> +#define LLCC_ERP_PANIC_ON_UE1 >> +#else >> +#define LLCC_ERP_PANIC_ON_UE0 >> +#endif >> + >> +#define EDAC_LLCC "qcom_llcc" >> + >> +#define TRP_SYN_REG_CNT 6 >> + >> +#define DRP_SYN_REG_CNT 8 >> + >> +#define LLCC_COMMON_STATUS0 0x0003000C >> +#define LLCC_LB_CNT_MASKGENMASK(31, 28) >> +#define LLCC_LB_CNT_SHIFT 28 >> + >> +/* single & Double Bit syndrome register offsets */ > > Strange capitalization going on here. I'll fix this. > >> +#define TRP_ECC_SB_ERR_SYN0 0x0002304C >> +#define TRP_ECC_DB_ERR_SYN0 0x00020370 >> +#define DRP_ECC_SB_ERR_SYN0 0x0004204C >> +#define DRP_ECC_DB_ERR_SYN0 0x00042070 > > I think the convention is to use lowercase hex everywhere. I didn't get you. Do you mean, the Macros should be
Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-08-24 09:11, Stephen Boyd wrote: Quoting Venkata Narendra Kumar Gutta (2018-08-17 17:08:34) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 57304b2..da8f150 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,4 +460,32 @@ config EDAC_TI Support for error detection and correction on the TI SoCs. +config EDAC_QCOM + tristate "QCOM EDAC Controller" + depends on EDAC + help + Support for error detection and correction on the + QCOM SoCs. + +config EDAC_QCOM_LLCC + tristate "QCOM EDAC Controller for LLCC Cache" + depends on EDAC_QCOM && QCOM_LLCC + help + Support for error detection and correction on the + QCOM LLCC cache. Report errors caught by LLCC ECC + mechanism. + + For debugging issues having to do with stability and overall system + health, you should probably say 'Y' here. + +config EDAC_QCOM_LLCC_PANIC_ON_UE + bool "Panic on uncorrectable errors - qcom llcc" Why isn't this a generic option for all EDAC? I'm not sure, I'll get back to you on this. + depends on EDAC_QCOM_LLCC + help + Forcibly cause a kernel panic if an uncorrectable error (UE) is + detected. This can reduce debugging times on hardware which may be + operating at voltages or frequencies outside normal specification. + + For production builds, you should probably say 'N' here. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02b43a7..716096d 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o +obj-$(CONFIG_EDAC_QCOM)+= qcom_edac.o Maybe put this in sort of alphabetical order so conflicts don't happen. None of them are in alphabetical order, so I'm not sure where to start! what do you suggest? diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c new file mode 100644 index 000..9a8c670 --- /dev/null +++ b/drivers/edac/qcom_edac.c @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include Used? Maybe it should just be linux/of.h Ok, I'll check and update. +#include +#include +#include Why? I'll check if this is being used, otherwise, I'll remove it. +#include + +#include "edac_mc.h" +#include "edac_device.h" + +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE +#define LLCC_ERP_PANIC_ON_UE1 +#else +#define LLCC_ERP_PANIC_ON_UE0 +#endif + +#define EDAC_LLCC "qcom_llcc" + +#define TRP_SYN_REG_CNT 6 + +#define DRP_SYN_REG_CNT 8 + +#define LLCC_COMMON_STATUS0 0x0003000C +#define LLCC_LB_CNT_MASKGENMASK(31, 28) +#define LLCC_LB_CNT_SHIFT 28 + +/* single & Double Bit syndrome register offsets */ +#define TRP_ECC_SB_ERR_SYN0 0x0002304C +#define TRP_ECC_DB_ERR_SYN0 0x00020370 +#define DRP_ECC_SB_ERR_SYN0 0x0004204C +#define DRP_ECC_DB_ERR_SYN0 0x00042070 + +/* Error register offsets */ +#define TRP_ECC_ERROR_STATUS1 0x00020348 +#define TRP_ECC_ERROR_STATUS0 0x00020344 +#define DRP_ECC_ERROR_STATUS1 0x00042048 +#define DRP_ECC_ERROR_STATUS0 0x00042044 + +/* TRP, DRP interrupt register offsets */ +#define DRP_INTERRUPT_STATUS0x00041000 +#define TRP_INTERRUPT_0_STATUS 0x00020480 +#define DRP_INTERRUPT_CLEAR 0x00041008 +#define DRP_ECC_ERROR_CNTR_CLEAR0x00040004 +#define TRP_INTERRUPT_0_CLEAR 0x00020484 +#define TRP_ECC_ERROR_CNTR_CLEAR0x00020440 + +/* Mask and shift macros */ +#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) +#define ECC_DB_ERR_WAYS_MASKGENMASK(31, 16) +#define ECC_DB_ERR_WAYS_SHIFT BIT(4) + +#define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16) +#define ECC_SB_ERR_COUNT_SHIFT BIT(4) +#define ECC_SB_ERR_WAYS_MASKGENMASK(15, 0) + +#define SB_ECC_ERRORBIT(0) +#define DB_ECC_ERRORBIT(1) + +#define DRP_TRP_INT_CLEAR GENMASK(1, 0) +#define DRP_TRP_CNT_CLEAR GENMASK(1, 0) + +/* Config registers offsets*/ +#define DRP_ECC_ERROR_CFG 0x0004 + +/* TRP, DRP interrupt register offsets */ +#define CMN_INTERRUPT_0_ENABLE 0x0003001C +#define CMN_INTERRUPT_2_ENABLE 0x0003003C +#define TRP_INTERRUPT_0_ENABLE 0x00020488 +#define DRP_INTERRUPT_ENABLE0x0004100C + +#define SB_ERROR_THRESHOLD 0x1 +#define SB_ERROR_THRESHOLD_SHIFT2
Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-08-23 16:07, Evan Green wrote:
On Thu, Aug 23, 2018 at 4:04 PM Evan Green
wrote:
On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
wrote:
>
> From: Channagoud Kadabi
Also checkpatch.pl complains a bit about this patch:
WARNING: Non-standard signature: Co-developed-by:
#14:
Co-developed-by: Venkata Narendra Kumar Gutta
This needs to be there as the original author is Channagoud Kadabi
and I'm the one who is modifying and upstreaming this driver.
It was suggested to have this kind of signature from the earlier
patchset comments.
Can we do anything about this?
WARNING: please write a paragraph that describes the
config symbol fully
#63: FILE: drivers/edac/Kconfig:460:
+config EDAC_QCOM
This is also, I will check if I can get rid of this by writing more in
the description.
I don't really understand why do we need a paragraph here.
WARNING: DT compatible string "qcom,llcc-edac" appears
un-documented -- check ./Documentation/devicetree/bindings/
#536: FILE: drivers/edac/qcom_edac.c:430:
+ { .compatible = "qcom,llcc-edac" },
This file is not added in the dt-bindings as there are no properties
(like reg-names or interrupts) for this driver
and anyway initialized from llcc driver.
Do we still need to have the Documentation in place?
total: 0 errors, 3 warnings, 533 lines checked
-Evan
Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-08-23 16:04, Evan Green wrote: On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta wrote: From: Channagoud Kadabi Add error reporting driver for Single Bit Errors (SBEs) and Double Bit Errors (DBEs). As of now, this driver supports erp for Last Level Cache Controller (LLCC). This driver takes care of dumping registers and adding config options to enable and disable panic when the errors happen in cache. Signed-off-by: Channagoud Kadabi Signed-off-by: Venkata Narendra Kumar Gutta Co-developed-by: Venkata Narendra Kumar Gutta --- MAINTAINERS| 8 + drivers/edac/Kconfig | 28 +++ drivers/edac/Makefile | 1 + drivers/edac/qcom_edac.c | 446 + include/linux/soc/qcom/llcc-qcom.h | 25 +++ 5 files changed, 508 insertions(+) create mode 100644 drivers/edac/qcom_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index 0a23427..0bff713 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5227,6 +5227,14 @@ L: linux-e...@vger.kernel.org S: Maintained F: drivers/edac/ti_edac.c +EDAC-QUALCOMM +M: Channagoud Kadabi +M: Venkata Narendra Kumar Gutta +L: linux-arm-...@vger.kernel.org +L: linux-e...@vger.kernel.org +S: Maintained +F: drivers/edac/qcom_edac.c + EDIROL UA-101/UA-1000 DRIVER M: Clemens Ladisch L: alsa-de...@alsa-project.org (moderated for non-subscribers) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 57304b2..da8f150 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,4 +460,32 @@ config EDAC_TI Support for error detection and correction on the TI SoCs. +config EDAC_QCOM + tristate "QCOM EDAC Controller" + depends on EDAC + help + Support for error detection and correction on the + QCOM SoCs. + +config EDAC_QCOM_LLCC + tristate "QCOM EDAC Controller for LLCC Cache" + depends on EDAC_QCOM && QCOM_LLCC + help + Support for error detection and correction on the + QCOM LLCC cache. Report errors caught by LLCC ECC + mechanism. + + For debugging issues having to do with stability and overall system + health, you should probably say 'Y' here. + +config EDAC_QCOM_LLCC_PANIC_ON_UE + bool "Panic on uncorrectable errors - qcom llcc" + depends on EDAC_QCOM_LLCC + help + Forcibly cause a kernel panic if an uncorrectable error (UE) is + detected. This can reduce debugging times on hardware which may be + operating at voltages or frequencies outside normal specification. + + For production builds, you should probably say 'N' here. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02b43a7..716096d 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o +obj-$(CONFIG_EDAC_QCOM)+= qcom_edac.o diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c new file mode 100644 index 000..9a8c670 --- /dev/null +++ b/drivers/edac/qcom_edac.c @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "edac_mc.h" +#include "edac_device.h" + +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE +#define LLCC_ERP_PANIC_ON_UE1 +#else +#define LLCC_ERP_PANIC_ON_UE0 +#endif + +#define EDAC_LLCC "qcom_llcc" + +#define TRP_SYN_REG_CNT 6 + +#define DRP_SYN_REG_CNT 8 + +#define LLCC_COMMON_STATUS0 0x0003000C +#define LLCC_LB_CNT_MASKGENMASK(31, 28) +#define LLCC_LB_CNT_SHIFT 28 + +/* single & Double Bit syndrome register offsets */ Strange capitalization going on here. I'll fix this. +#define TRP_ECC_SB_ERR_SYN0 0x0002304C +#define TRP_ECC_DB_ERR_SYN0 0x00020370 +#define DRP_ECC_SB_ERR_SYN0 0x0004204C +#define DRP_ECC_DB_ERR_SYN0 0x00042070 I think the convention is to use lowercase hex everywhere. I didn't get you. Do you mean, the Macros should be in lower case or the comments? + +/* Error register offsets */ +#define TRP_ECC_ERROR_STATUS1 0x00020348 +#define TRP_ECC_ERROR_STATUS0 0x00020344 +#define DRP_ECC_ERROR_STATUS1 0x00042048 +#define DRP_ECC_ERROR_STATUS0 0x00042044 + +/* TRP, DRP interrupt register offsets */ +#define DRP_INTERRUPT_STATUS0x00041000 +#define TRP_INTERRUPT_0_STATUS 0x00020480 +#define DRP_INTERRUPT_CLEAR 0x00041008 +#
Re: [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC)
On 2018-08-23 16:01, Evan Green wrote: On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta wrote: Currently, boradcast base is set to end of the LLCC banks, which may s/boradcast/broadcast/ I'll correct this typo in the next version. not be correct always. As the number of banks may vary for each chipset and the broadcast base could be at a different address as well. This info depends on the chipset, so get the broadcast base info from the device tree (DT). Add broadcast base in LLCC driver and use this for broadcast writes. Signed-off-by: Venkata Narendra Kumar Gutta --- drivers/soc/qcom/llcc-slice.c | 55 +++--- include/linux/soc/qcom/llcc-qcom.h | 4 +-- 2 files changed, 35 insertions(+), 24 deletions(-) Reviewed-by: Evan Green
Re: [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver
On 2018-08-23 16:01, Evan Green wrote: On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta wrote: Cache error reporting controller is to detect and report single Should be "Cache error reporting controller detects and reports single"... Ok. I'll update this in next patchset. Other than that: Reviewed-by: Evan Green Thanks
Re: [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc
On 2018-08-20 12:53, Rob Herring wrote:
On Fri, Aug 17, 2018 at 05:08:35PM -0700, Venkata Narendra Kumar Gutta
wrote:
Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.
Typo in the subject.
This binding just landed recently and it's already being updated? Sigh.
Bindings should be complete from the start. Technically, you can't add
new required properties.
Sure, I'll correct the typo.
llcc broadcast base was being computed from the number of banks which
was incorrect,
so we have to add this property.
And the interrupt is needed for EDAC functionality.
Signed-off-by: Venkata Narendra Kumar Gutta
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15
++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..b4b1c86 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -18,9 +18,22 @@ Properties:
Value Type:
Definition: Start address and the the size of the register region.
+- reg-names:
+Usage: required
+Value Type:
+Definition: Register region names. Must be "llcc_base",
"llcc_bcast_base".
reg needs to be updated that there are 2 entries.
Ok, I'll update this in the next version.
+
+- interrupts:
+ Usage: required
+ Definition: The interrupt is associated with the llcc edac device.
+ It's used for llcc cache single and double bit error
detection
+ and reporting.
+
Example:
cache-controller@110 {
compatible = "qcom,sdm845-llcc";
- reg = <0x110 0x25>;
+ reg = <0x110 0x20>, <0x130 0x5> ;
+ reg-names = "llcc_base", "llcc_bcast_base";
+ interrupts = ;
};
--
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Forum,
a Linux Foundation Collaborative Project
Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-08-10 10:23, Evan Green wrote:
On Wed, Aug 1, 2018 at 1:34 PM Venkata Narendra Kumar Gutta
wrote:
From: Channagoud Kadabi
Add error reporting driver for SBEs and DBEs. As of now, this driver
supports erp for Last Level Cache Controller (LLCC). This driver takes
care of dumping registers and adding config options to enable and
disable panic when the errors happen in cache.
Co-developed-by: Venkata Narendra Kumar Gutta
Signed-off-by: Venkata Narendra Kumar Gutta
Signed-off-by: Channagoud Kadabi
---
MAINTAINERS | 7 +
drivers/edac/Kconfig | 28 +++
drivers/edac/Makefile| 1 +
drivers/edac/qcom_edac.c | 507
+++
4 files changed, 543 insertions(+)
create mode 100644 drivers/edac/qcom_edac.c
...
diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
new file mode 100644
index 000..cf3e2b0
--- /dev/null
+++ b/drivers/edac/qcom_edac.c
@@ -0,0 +1,507 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
Please alphabetize these includes, and remove any unneeded ones.
Ok, I'll update it in the next version. I didn't know that it's
mandatory to have in alphabetic order.
Is it recommended or a strict rule that we have includes in alphabetize
order?
+#include "edac_mc.h"
+#include "edac_device.h"
+
+#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
+#define LLCC_ERP_PANIC_ON_UE1
+#else
+#define LLCC_ERP_PANIC_ON_UE0
+#endif
+
+#define EDAC_LLCC "qcom_llcc"
+
+#define TRP_SYN_REG_CNT 6
+
+#define DRP_SYN_REG_CNT 8
+
+#define LLCC_COMMON_STATUS0 0x0003000C
+#define LLCC_LB_CNT_MASKGENMASK(31, 28)
+#define LLCC_LB_CNT_SHIFT 28
+
+/* single & Double Bit syndrome register offsets */
+#define TRP_ECC_SB_ERR_SYN0 0x0002304C
+#define TRP_ECC_DB_ERR_SYN0 0x00020370
+#define DRP_ECC_SB_ERR_SYN0 0x0004204C
+#define DRP_ECC_DB_ERR_SYN0 0x00042070
+
+/* Error register offsets */
+#define TRP_ECC_ERROR_STATUS1 0x00020348
+#define TRP_ECC_ERROR_STATUS0 0x00020344
+#define DRP_ECC_ERROR_STATUS1 0x00042048
+#define DRP_ECC_ERROR_STATUS0 0x00042044
+
+/* TRP, DRP interrupt register offsets */
+#define DRP_INTERRUPT_STATUS0x00041000
+#define TRP_INTERRUPT_0_STATUS 0x00020480
+#define DRP_INTERRUPT_CLEAR 0x00041008
+#define DRP_ECC_ERROR_CNTR_CLEAR0x00040004
+#define TRP_INTERRUPT_0_CLEAR 0x00020484
+#define TRP_ECC_ERROR_CNTR_CLEAR0x00020440
+
+/* Mask and shift macros */
+#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0)
+#define ECC_DB_ERR_WAYS_MASKGENMASK(31, 16)
+#define ECC_DB_ERR_WAYS_SHIFT BIT(4)
+
+#define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16)
+#define ECC_SB_ERR_COUNT_SHIFT BIT(4)
+#define ECC_SB_ERR_WAYS_MASKGENMASK(15, 0)
+
+#define SB_ECC_ERRORBIT(0)
+#define DB_ECC_ERRORBIT(1)
+
+#define DRP_TRP_INT_CLEAR GENMASK(1, 0)
+#define DRP_TRP_CNT_CLEAR GENMASK(1, 0)
+
+/* Config registers offsets*/
+#define DRP_ECC_ERROR_CFG 0x0004
+
+/* TRP, DRP interrupt register offsets */
+#define CMN_INTERRUPT_0_ENABLE 0x0003001C
+#define CMN_INTERRUPT_2_ENABLE 0x0003003C
+#define TRP_INTERRUPT_0_ENABLE 0x00020488
+#define DRP_INTERRUPT_ENABLE0x0004100C
+
+#define SB_ERROR_THRESHOLD 0x1
+#define SB_ERROR_THRESHOLD_SHIFT24
+#define SB_DB_TRP_INTERRUPT_ENABLE 0x3
+#define TRP0_INTERRUPT_ENABLE 0x1
+#define DRP0_INTERRUPT_ENABLE BIT(6)
+#define SB_DB_DRP_INTERRUPT_ENABLE 0x3
+
+
+enum {
+ LLCC_DRAM_CE = 0,
+ LLCC_DRAM_UE,
+ LLCC_TRAM_CE,
+ LLCC_TRAM_UE,
+};
+
+struct errors_edac {
+ const char *msg;
+ void (*func)(struct edac_device_ctl_info *edev_ctl,
+ int inst_nr, int block_nr, const char
*msg);
+};
+
+static const struct errors_edac errors[] = {
+ {"LLCC Data RAM correctable Error", edac_device_handle_ce},
+ {"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
+ {"LLCC Tag RAM correctable Error", edac_device_handle_ce},
+ {"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
+};
+
+static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
+{
+ u32 sb_err_threshold;
+ int ret;
+
+ /* Enable TRP in instance 2 of common interrupt enable
register */
+ ret = regmap_update_bits(llcc_bcast_regmap,
CMN_INTERRUPT_2_ENABLE,
+TRP0_INTERRUPT_ENABLE,
+TRP0_INTERRUPT_ENABLE);
+ if (ret)
+
Re: [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver
On 2018-08-10 10:21, Evan Green wrote:
On Wed, Aug 1, 2018 at 1:33 PM Venkata Narendra Kumar Gutta
wrote:
Cache error reporting controller is to detect and report single
and double bit errors on Last Level Cache Controller (LLCC) cache.
Add required support to register LLCC EDAC driver as platform driver,
from LLCC driver.
Signed-off-by: Venkata Narendra Kumar Gutta
---
drivers/soc/qcom/llcc-slice.c | 18 --
include/linux/soc/qcom/llcc-qcom.h | 2 ++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/llcc-slice.c
b/drivers/soc/qcom/llcc-slice.c
index a63640d..09c8bb0 100644
--- a/drivers/soc/qcom/llcc-slice.c
+++ b/drivers/soc/qcom/llcc-slice.c
@@ -224,7 +224,7 @@ static int qcom_llcc_cfg_program(struct
platform_device *pdev)
u32 attr0_val;
u32 max_cap_cacheline;
u32 sz;
- int ret;
+ int ret = 0;
const struct llcc_slice_config *llcc_table;
struct llcc_slice_desc desc;
@@ -282,6 +282,7 @@ int qcom_llcc_probe(struct platform_device *pdev,
struct resource *llcc_banks_res, *llcc_bcast_res;
void __iomem *llcc_banks_base, *llcc_bcast_base;
int ret, i;
+ struct platform_device *llcc_edac;
drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
if (!drv_data)
@@ -341,6 +342,19 @@ int qcom_llcc_probe(struct platform_device *pdev,
mutex_init(&drv_data->lock);
platform_set_drvdata(pdev, drv_data);
- return qcom_llcc_cfg_program(pdev);
+ ret = qcom_llcc_cfg_program(pdev);
+ if (ret)
+ return ret;
+
+ drv_data->ecc_irq = platform_get_irq(pdev, 0);
+ if (drv_data->ecc_irq >= 0) {
This condition will always be true for u32. See below...
That's true. I missed that.
+ llcc_edac = platform_device_register_data(&pdev->dev,
+ "qcom_llcc_edac", -1,
drv_data,
+ sizeof(*drv_data));
+ if (IS_ERR(llcc_edac))
+ dev_err(dev, "Failed to register llcc edac
driver\n");
+ }
+
+ return ret;
}
EXPORT_SYMBOL_GPL(qcom_llcc_probe);
diff --git a/include/linux/soc/qcom/llcc-qcom.h
b/include/linux/soc/qcom/llcc-qcom.h
index c681e79..1a3bc25 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -78,6 +78,7 @@ struct llcc_slice_config {
* @num_banks: Number of llcc banks
* @bitmap: Bit map to track the active slice ids
* @offsets: Pointer to the bank offsets array
+ * @ecc_irq: interrupt for llcc cache error detection and reporting
*/
struct llcc_drv_data {
struct regmap *regmap;
@@ -89,6 +90,7 @@ struct llcc_drv_data {
u32 num_banks;
unsigned long *bitmap;
u32 *offsets;
+ u32 ecc_irq;
The return type for platform_get_irq is int, so this should probably
be int, or "unsigned", but then you'd need to fix your logic above.
I think we should keep that as int. I'll check on which one I'm supposed
to use here and update in the next version.
};
#if IS_ENABLED(CONFIG_QCOM_LLCC)
--
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a Linux Foundation Collaborative Project
Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-08-09 20:59, Borislav Petkov wrote: On Wed, Aug 01, 2018 at 01:33:34PM -0700, Venkata Narendra Kumar Gutta wrote: From: Channagoud Kadabi Add error reporting driver for SBEs and DBEs. As of now, this driver Please write out those abbreviations. Done, I just followed the other commits which has the same and thought they are understood in the community, I'll update it in the next patch set. supports erp for Last Level Cache Controller (LLCC). This driver takes care of dumping registers and adding config options to enable and disable panic when the errors happen in cache. Co-developed-by: Venkata Narendra Kumar Gutta Signed-off-by: Venkata Narendra Kumar Gutta Signed-off-by: Channagoud Kadabi The proper order is: SOB: Author SOB: Sender/handler/... So: Signed-off-by: Channagoud Kadabi Signed-off-by: Venkata Narendra Kumar Gutta Ok, I'll update accordingly. --- MAINTAINERS | 7 + drivers/edac/Kconfig | 28 +++ drivers/edac/Makefile| 1 + drivers/edac/qcom_edac.c | 507 +++ 4 files changed, 543 insertions(+) create mode 100644 drivers/edac/qcom_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index f6a9b08..68b3484 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5227,6 +5227,13 @@ L: linux-e...@vger.kernel.org S: Maintained F: drivers/edac/ti_edac.c +EDAC-QUALCOMM +M: Channagoud Kadabi +M: Venkata Narendra Kumar Gutta Space between name and email address. +L: linux-arm-...@vger.kernel.org Also L: linux-e...@vger.kernel.org so that the EDAC ML gets CCed too. Ok, Done +S: Maintained +F: drivers/edac/qcom_edac.c + EDIROL UA-101/UA-1000 DRIVER M: Clemens Ladisch L: alsa-de...@alsa-project.org (moderated for non-subscribers) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 57304b2..c654b0e 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,4 +460,32 @@ config EDAC_TI Support for error detection and correction on the TI SoCs. +config EDAC_QCOM + depends on EDAC=y Why on EDAC=y? Did you blindly copy it or is there a reason why edac_core should be only built-in or can it be a module too? I took it from EDAC_ALTERA example. I want to put it like EDAC_QCOM should be dependent on EDAC. Doesn't it make any sense or we don't need this at all? or do you think it's redundant? + tristate "QCOM EDAC Controller" + help + Support for error detection and correction on the + QCOM SoCs. + +config EDAC_QCOM_LLCC + depends on EDAC_QCOM=y && QCOM_LLCC + tristate "QCOM EDAC Controller for LLCC Cache" + help + Support for error detection and correction on the + QCOM LLCC cache. Report errors caught by LLCC ECC + mechanism. + + For debugging issues having to do with stability and overall system + health, you should probably say 'Y' here. + +config EDAC_QCOM_LLCC_PANIC_ON_UE + depends on EDAC_QCOM_LLCC + bool "Panic on uncorrectable errors - qcom llcc" + help + Forcibly cause a kernel panic if an uncorrectable error (UE) is + detected. This can reduce debugging times on hardware which may be + operating at voltages or frequencies outside normal specification. + + For production builds, you should probably say 'N' here. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02b43a7..716096d 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o +obj-$(CONFIG_EDAC_QCOM)+= qcom_edac.o diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c new file mode 100644 index 000..cf3e2b0 --- /dev/null +++ b/drivers/edac/qcom_edac.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "edac_mc.h" +#include "edac_device.h" + +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE +#define LLCC_ERP_PANIC_ON_UE1 +#else +#define LLCC_ERP_PANIC_ON_UE0 +#endif + +#define EDAC_LLCC "qcom_llcc" + +#define TRP_SYN_REG_CNT 6 + +#define DRP_SYN_REG_CNT 8 + +#define LLCC_COMMON_STATUS0 0x0003000C +#define LLCC_LB_CNT_MASKGENMASK(31, 28) +#define LLCC_LB_CNT_SHIFT 28 + +/* single & Double Bit syndrome register offsets */ +#define TRP_ECC_SB_ERR_SYN0 0x0002304C +#define TRP_ECC_DB_ERR_SYN0 0x00020370 +#define DRP_ECC
Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
Reminder. Would someone review this EDAC patch series? Thanks, Narendra On 2018-08-01 13:33, Venkata Narendra Kumar Gutta wrote: From: Channagoud Kadabi Add error reporting driver for SBEs and DBEs. As of now, this driver supports erp for Last Level Cache Controller (LLCC). This driver takes care of dumping registers and adding config options to enable and disable panic when the errors happen in cache. Co-developed-by: Venkata Narendra Kumar Gutta Signed-off-by: Venkata Narendra Kumar Gutta Signed-off-by: Channagoud Kadabi --- MAINTAINERS | 7 + drivers/edac/Kconfig | 28 +++ drivers/edac/Makefile| 1 + drivers/edac/qcom_edac.c | 507 +++ 4 files changed, 543 insertions(+) create mode 100644 drivers/edac/qcom_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index f6a9b08..68b3484 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5227,6 +5227,13 @@ L: linux-e...@vger.kernel.org S: Maintained F: drivers/edac/ti_edac.c +EDAC-QUALCOMM +M: Channagoud Kadabi +M: Venkata Narendra Kumar Gutta +L: linux-arm-...@vger.kernel.org +S: Maintained +F: drivers/edac/qcom_edac.c + EDIROL UA-101/UA-1000 DRIVER M: Clemens Ladisch L: alsa-de...@alsa-project.org (moderated for non-subscribers) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 57304b2..c654b0e 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,4 +460,32 @@ config EDAC_TI Support for error detection and correction on the TI SoCs. +config EDAC_QCOM + depends on EDAC=y + tristate "QCOM EDAC Controller" + help + Support for error detection and correction on the + QCOM SoCs. + +config EDAC_QCOM_LLCC + depends on EDAC_QCOM=y && QCOM_LLCC + tristate "QCOM EDAC Controller for LLCC Cache" + help + Support for error detection and correction on the + QCOM LLCC cache. Report errors caught by LLCC ECC + mechanism. + + For debugging issues having to do with stability and overall system + health, you should probably say 'Y' here. + +config EDAC_QCOM_LLCC_PANIC_ON_UE + depends on EDAC_QCOM_LLCC + bool "Panic on uncorrectable errors - qcom llcc" + help + Forcibly cause a kernel panic if an uncorrectable error (UE) is + detected. This can reduce debugging times on hardware which may be + operating at voltages or frequencies outside normal specification. + + For production builds, you should probably say 'N' here. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02b43a7..716096d 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o +obj-$(CONFIG_EDAC_QCOM)+= qcom_edac.o diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c new file mode 100644 index 000..cf3e2b0 --- /dev/null +++ b/drivers/edac/qcom_edac.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "edac_mc.h" +#include "edac_device.h" + +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE +#define LLCC_ERP_PANIC_ON_UE1 +#else +#define LLCC_ERP_PANIC_ON_UE0 +#endif + +#define EDAC_LLCC "qcom_llcc" + +#define TRP_SYN_REG_CNT 6 + +#define DRP_SYN_REG_CNT 8 + +#define LLCC_COMMON_STATUS0 0x0003000C +#define LLCC_LB_CNT_MASKGENMASK(31, 28) +#define LLCC_LB_CNT_SHIFT 28 + +/* single & Double Bit syndrome register offsets */ +#define TRP_ECC_SB_ERR_SYN0 0x0002304C +#define TRP_ECC_DB_ERR_SYN0 0x00020370 +#define DRP_ECC_SB_ERR_SYN0 0x0004204C +#define DRP_ECC_DB_ERR_SYN0 0x00042070 + +/* Error register offsets */ +#define TRP_ECC_ERROR_STATUS1 0x00020348 +#define TRP_ECC_ERROR_STATUS0 0x00020344 +#define DRP_ECC_ERROR_STATUS1 0x00042048 +#define DRP_ECC_ERROR_STATUS0 0x00042044 + +/* TRP, DRP interrupt register offsets */ +#define DRP_INTERRUPT_STATUS0x00041000 +#define TRP_INTERRUPT_0_STATUS 0x00020480 +#define DRP_INTERRUPT_CLEAR 0x00041008 +#define DRP_ECC_ERROR_CNTR_CLEAR0x00040004 +#define TRP_INTERRUPT_0_CLEAR 0x00020484 +#define TRP_ECC_ERROR_CNTR_CLEAR0x00020440 + +/* Mask and shift macros */ +#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) +#define ECC_DB_ERR_WAYS_MASKGENMA
Re: [PATCH v0 3/4] drivers: edac: Add cache erp driver for Last Level Cache Controller (LLCC)
On 2018-07-28 20:49, Borislav Petkov wrote: On Wed, Jul 25, 2018 at 10:44:56AM -0700, Venkata Narendra Kumar Gutta wrote: Add cache error reporting driver for single and double bit errors on Last Level Cache Controller (LLCC) cache. This driver takes care of dumping registers and add config options to enable and disable panic when these errors happen. Signed-off-by: Channagoud Kadabi Signed-off-by: Venkata Narendra Kumar Gutta This SOB chain doesn't make any sense - see Documentation/process/submitting-patches.rst Do you mean the Signed-off-by lines above? That's because Channagoud is the one who is the original author of this driver, and I'm the one who did the incremental changes (changes in llcc) and uploading it upstream. That's why the Signed-off is like that. Which way do you think it should be? --- drivers/edac/Kconfig | 21 ++ drivers/edac/Makefile | 1 + drivers/edac/qcom_llcc_edac.c | 520 ++ 3 files changed, 542 insertions(+) create mode 100644 drivers/edac/qcom_llcc_edac.c Needs MAINTAINERS entry so that you get all the bug reports. I'll update it. diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 57304b2..68518ad 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,4 +460,25 @@ config EDAC_TI Support for error detection and correction on the TI SoCs. +config EDAC_QCOM_LLCC +depends on QCOM_LLCC +tristate "QCOM EDAC Controller for LLCC Cache" No edac driver per functional unit pls - see how altera_edac.c does it, for example. IOW, this driver - if it cannot share/reuse any of the existing edac drivers, it should be called qcom_edac and contain all the Qualcomm-specific RAS features there. Ok, I'll refactor it. +help + Support for error detection and correction on the + QCOM LLCC cache. Report errors caught by LLCC ECC + mechanism. + + For debugging issues having to do with stability and overall system + health, you should probably say 'Y' here. + +config EDAC_QCOM_LLCC_PANIC_ON_UE +depends on EDAC_QCOM_LLCC +bool "Panic on uncorrectable errors - qcom llcc" +help + Forcibly cause a kernel panic if an uncorrectable error (UE) is + detected. This can reduce debugging times on hardware which may be + operating at voltages or frequencies outside normal specification. + + For production builds, you should probably say 'N' here. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02b43a7..28aff28 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o +obj-$(CONFIG_EDAC_QCOM_LLCC) += qcom_llcc_edac.o diff --git a/drivers/edac/qcom_llcc_edac.c b/drivers/edac/qcom_llcc_edac.c new file mode 100644 index 000..7a678b5 --- /dev/null +++ b/drivers/edac/qcom_llcc_edac.c @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "edac_mc.h" +#include "edac_device.h" + +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE +#define LLCC_ERP_PANIC_ON_UE 1 +#else +#define LLCC_ERP_PANIC_ON_UE 0 +#endif + +#define EDAC_LLCC "qcom_llcc" + +#define TRP_SYN_REG_CNT6 + +#define DRP_SYN_REG_CNT8 + +#define LLCC_COMMON_STATUS00x0003000C +#define LLCC_LB_CNT_MASK GENMASK(31, 28) +#define LLCC_LB_CNT_SHIFT 28 + +/* single & Double Bit syndrome register offsets */ +#define TRP_ECC_SB_ERR_SYN00x0002304C +#define TRP_ECC_DB_ERR_SYN00x00020370 +#define DRP_ECC_SB_ERR_SYN00x0004204C +#define DRP_ECC_DB_ERR_SYN00x00042070 + +/* Error register offsets */ +#define TRP_ECC_ERROR_STATUS1 0x00020348 +#define TRP_ECC_ERROR_STATUS0 0x00020344 +#define DRP_ECC_ERROR_STATUS1 0x00042048 +#define DRP_ECC_ERROR_STATUS0 0x00042044 + +/* TRP, DRP interrupt register offsets */ +#define DRP_INTERRUPT_STATUS 0x00041000 +#define TRP_INTERRUPT_0_STATUS 0x00020480 +#define DRP_INTERRUPT_CLEAR0x00041008 +#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004 +#define TRP_INTERRUPT_0_CLEAR 0x00020484 +#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440 + +/* Mask and shift macros */ +#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) Align all those to the same vertical column. Sure, I'll update it in the next patch set. +#define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16) +#define ECC_DB_ERR_WAYS_SHIFT BIT(4) + +#define ECC_SB_ERR_COUNT_MASK GENMASK
