Re: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu

2019-10-12 Thread Daniel Baluta 
On Sat, Oct 12, 2019 at 4:12 AM Richard Zhu  wrote:
>
> Hi Daniel:
> New version patch-set had been sent out on Oct9.
> https://patchwork.kernel.org/cover/11180683/

Thanks Richard. Jassi, care to have a look?

Daniel

RE: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu

2019-10-11 Thread Richard Zhu 
Hi Daniel:
New version patch-set had been sent out on Oct9.
https://patchwork.kernel.org/cover/11180683/


Best Regards
Richard Zhu

> -Original Message-
> From: Richard Zhu
> Sent: 2019年10月9日 9:48
> To: Daniel Baluta 
> Cc: jassisinghb...@gmail.com; Oleksij Rempel ;
> Daniel Baluta ; Aisheng Dong
> ; dl-linux-imx ; Linux Kernel
> Mailing List ; linux-arm-kernel
> 
> Subject: RE: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for
> imx v1 mu
> 
> Hi Daniel:
> 
> 
> > -Original Message-
> > From: Daniel Baluta 
> > Sent: 2019年10月8日 15:26
> > To: Richard Zhu 
> > Cc: jassisinghb...@gmail.com; Oleksij Rempel
> > ; Daniel Baluta ;
> > Aisheng Dong ; dl-linux-imx
> ;
> > Linux Kernel Mailing List ;
> > linux-arm-kernel 
> > Subject: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for
> > imx v1 mu
> >
> >
> > Hi Richard,
> >
> > Can you please rebase and resend this patch series?
> >
> [Richard Zhu] No problem, I would resend this patch-set later.
> 
> 
> Best Regards
> Richard Zhu
> 
> > On Mon, Aug 5, 2019 at 10:21 PM Daniel Baluta
> > 
> > wrote:
> > >
> > > On Mon, Aug 5, 2019 at 8:16 AM Richard Zhu 
> > wrote:
> > > >
> > > > There is a version 1.0 MU on i.MX7ULP platform.
> > > > One new version ID register is added, and it's offset is 0.
> > > > TRn registers are defined at the offset 0x20 ~ 0x2C.
> > > > RRn registers are defined at the offset 0x40 ~ 0x4C.
> > > > SR/CR registers are defined at 0x60/0x64.
> > > > Extend this driver to support it.
> > > >
> > > > Signed-off-by: Richard Zhu 
> > > > Suggested-by: Oleksij Rempel 
> > > > Reviewed-by: Dong Aisheng 
> > > > Reviewed-by: Oleksij Rempel 
> > >
> > > Very clean solution. Thanks Richard!
> > >
> > > Reviewed-by: Daniel Baluta 
> > >
> > > > ---
> > > >  drivers/mailbox/imx-mailbox.c | 55
> > > > ++-
> > > >  1 file changed, 38 insertions(+), 17 deletions(-)
> > > >
> > > > diff --git a/drivers/mailbox/imx-mailbox.c
> > > > b/drivers/mailbox/imx-mailbox.c index afe625e..2cdcdc5 100644
> > > > --- a/drivers/mailbox/imx-mailbox.c
> > > > +++ b/drivers/mailbox/imx-mailbox.c
> > > > @@ -12,19 +12,11 @@
> > > >  #include 
> > > >  #include 
> > > >
> > > > -/* Transmit Register */
> > > > -#define IMX_MU_xTRn(x) (0x00 + 4 * (x))
> > > > -/* Receive Register */
> > > > -#define IMX_MU_xRRn(x) (0x10 + 4 * (x))
> > > > -/* Status Register */
> > > > -#define IMX_MU_xSR 0x20
> > > >  #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
> > > >  #define IMX_MU_xSR_RFn(x)  BIT(24 + (3 - (x)))
> > > >  #define IMX_MU_xSR_TEn(x)  BIT(20 + (3 - (x)))
> > > >  #define IMX_MU_xSR_BRDIP   BIT(9)
> > > >
> > > > -/* Control Register */
> > > > -#define IMX_MU_xCR 0x24
> > > >  /* General Purpose Interrupt Enable */
> > > >  #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
> > > >  /* Receive Interrupt Enable */
> > > > @@ -44,6 +36,13 @@ enum imx_mu_chan_type {
> > > > IMX_MU_TYPE_RXDB,   /* Rx doorbell */
> > > >  };
> > > >
> > > > +struct imx_mu_dcfg {
> > > > +   u32 xTR[4]; /* Transmit Registers */
> > > > +   u32 xRR[4]; /* Receive Registers */
> > > > +   u32 xSR;/* Status Register */
> > > > +   u32 xCR;/* Control Register */
> > > > +};
> > > > +
> > > >  struct imx_mu_con_priv {
> > > > unsigned intidx;
> > > > char
> > irq_desc[IMX_MU_CHAN_NAME_SIZE];
> > > > @@ -61,12 +60,27 @@ struct imx_mu_priv {
> > > > struct mbox_chanmbox_chans[IMX_MU_CHANS];
> > > >
> > > > struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
> > > > +   const struct imx_mu_dcfg*dcfg;
> > > > struct clk  *clk;
> > > > int irq;
> > > >
> > > > boolside_b;
> > > >  };
> > > >
> > > > +stati

RE: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu

2019-10-08 Thread Richard Zhu 
Hi Daniel:


> -Original Message-
> From: Daniel Baluta 
> Sent: 2019年10月8日 15:26
> To: Richard Zhu 
> Cc: jassisinghb...@gmail.com; Oleksij Rempel ;
> Daniel Baluta ; Aisheng Dong
> ; dl-linux-imx ; Linux Kernel
> Mailing List ; linux-arm-kernel
> 
> Subject: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1
> mu
> 
> 
> Hi Richard,
> 
> Can you please rebase and resend this patch series?
> 
[Richard Zhu] No problem, I would resend this patch-set later.


Best Regards
Richard Zhu

> On Mon, Aug 5, 2019 at 10:21 PM Daniel Baluta 
> wrote:
> >
> > On Mon, Aug 5, 2019 at 8:16 AM Richard Zhu 
> wrote:
> > >
> > > There is a version 1.0 MU on i.MX7ULP platform.
> > > One new version ID register is added, and it's offset is 0.
> > > TRn registers are defined at the offset 0x20 ~ 0x2C.
> > > RRn registers are defined at the offset 0x40 ~ 0x4C.
> > > SR/CR registers are defined at 0x60/0x64.
> > > Extend this driver to support it.
> > >
> > > Signed-off-by: Richard Zhu 
> > > Suggested-by: Oleksij Rempel 
> > > Reviewed-by: Dong Aisheng 
> > > Reviewed-by: Oleksij Rempel 
> >
> > Very clean solution. Thanks Richard!
> >
> > Reviewed-by: Daniel Baluta 
> >
> > > ---
> > >  drivers/mailbox/imx-mailbox.c | 55
> > > ++-
> > >  1 file changed, 38 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/mailbox/imx-mailbox.c
> > > b/drivers/mailbox/imx-mailbox.c index afe625e..2cdcdc5 100644
> > > --- a/drivers/mailbox/imx-mailbox.c
> > > +++ b/drivers/mailbox/imx-mailbox.c
> > > @@ -12,19 +12,11 @@
> > >  #include 
> > >  #include 
> > >
> > > -/* Transmit Register */
> > > -#define IMX_MU_xTRn(x) (0x00 + 4 * (x))
> > > -/* Receive Register */
> > > -#define IMX_MU_xRRn(x) (0x10 + 4 * (x))
> > > -/* Status Register */
> > > -#define IMX_MU_xSR 0x20
> > >  #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
> > >  #define IMX_MU_xSR_RFn(x)  BIT(24 + (3 - (x)))
> > >  #define IMX_MU_xSR_TEn(x)  BIT(20 + (3 - (x)))
> > >  #define IMX_MU_xSR_BRDIP   BIT(9)
> > >
> > > -/* Control Register */
> > > -#define IMX_MU_xCR 0x24
> > >  /* General Purpose Interrupt Enable */
> > >  #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
> > >  /* Receive Interrupt Enable */
> > > @@ -44,6 +36,13 @@ enum imx_mu_chan_type {
> > > IMX_MU_TYPE_RXDB,   /* Rx doorbell */
> > >  };
> > >
> > > +struct imx_mu_dcfg {
> > > +   u32 xTR[4]; /* Transmit Registers */
> > > +   u32 xRR[4]; /* Receive Registers */
> > > +   u32 xSR;/* Status Register */
> > > +   u32 xCR;/* Control Register */
> > > +};
> > > +
> > >  struct imx_mu_con_priv {
> > > unsigned intidx;
> > > char
> irq_desc[IMX_MU_CHAN_NAME_SIZE];
> > > @@ -61,12 +60,27 @@ struct imx_mu_priv {
> > > struct mbox_chanmbox_chans[IMX_MU_CHANS];
> > >
> > > struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
> > > +   const struct imx_mu_dcfg*dcfg;
> > > struct clk  *clk;
> > > int irq;
> > >
> > > boolside_b;
> > >  };
> > >
> > > +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
> > > +   .xTR= {0x0, 0x4, 0x8, 0xc},
> > > +   .xRR= {0x10, 0x14, 0x18, 0x1c},
> > > +   .xSR= 0x20,
> > > +   .xCR= 0x24,
> > > +};
> > > +
> > > +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
> > > +   .xTR= {0x20, 0x24, 0x28, 0x2c},
> > > +   .xRR= {0x40, 0x44, 0x48, 0x4c},
> > > +   .xSR= 0x60,
> > > +   .xCR= 0x64,
> > > +};
> > > +
> > >  static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller
> > > *mbox)  {
> > > return container_of(mbox, struct imx_mu_priv, mbox); @@
> > > -88,10 +102,10 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv,
> u32 set, u32 clr)
> > > u32 val;
> > >
> > > spin_lock_irqsave(>xcr_lock, flags);
> > > -   val = imx_mu_read(priv