[PATCH][SERIAL] mpsc updates
Hi again, Andrew.
This patch:
- replaces several macros with the actual code
- change the type of pointer variables from u32 to void *
- removes unecessary casts
- puts the contents of mpsc_defs.h into mpsc.h and removes the mpsc_defs.h
- reflects the new names of some structs
- cleans up some whitespace
Signed-off-by: Mark A. Greer <[EMAIL PROTECTED]>
--
diff -Nru a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c
--- a/drivers/serial/mpsc.c 2005-01-25 17:28:43 -07:00
+++ b/drivers/serial/mpsc.c 2005-01-25 17:28:43 -07:00
@@ -36,16 +36,14 @@
*
* 1) Some chips have an erratum where several regs cannot be
* read. To work around that, we keep a local copy of those regs in
- * 'mpsc_port_info' and use the *_M or *_S macros when accessing those regs.
+ * 'mpsc_port_info'.
*
* 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
- * accesses system mem in a cache coherent region. This *should* be a
- * show-stopper when coherency is turned on but it seems to work okay as
- * long as there are no snoop hits. Therefore, the ring buffer entries and
- * the buffers themselves are allocated via 'dma_alloc_noncoherent()' and
- * 'dma_cache_sync()' is used. Also, since most PPC platforms are coherent
- * which makes 'dma_cache_sync()' a no-op, explicit cache management macros
- * have been added ensuring there are no snoop hits when coherency is on.
+ * accesses system mem with coherency enabled. For that reason, the driver
+ * assumes that coherency for that ctlr has been disabled. This means
+ * that when in a cache coherent system, the driver has to manually manage
+ * the data cache on the areas that it touches because the dma_* macro are
+ * basically no-ops.
*
* 3) There is an erratum (on PPC) where you can't use the instruction to do
* a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
@@ -54,7 +52,6 @@
* 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
*/
-#include
#include "mpsc.h"
/*
@@ -81,25 +78,48 @@
static void
mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
{
+ u32 v;
+
+ v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
+ v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
+
if (pi->brg_can_tune)
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 25, 0);
+ v &= ~(1 << 25);
+
+ if (pi->mirror_regs)
+ pi->BRG_BCR_m = v;
+ writel(v, pi->brg_base + BRG_BCR);
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 4, 18, clk_src);
- MPSC_MOD_FIELD(pi, brg, BRG_BTR, 16, 0, 0);
+ writel(readl(pi->brg_base + BRG_BTR) & 0x,
+ pi->brg_base + BRG_BTR);
return;
}
static void
mpsc_brg_enable(struct mpsc_port_info *pi)
{
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 16, 1);
+ u32 v;
+
+ v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
+ v |= (1 << 16);
+
+ if (pi->mirror_regs)
+ pi->BRG_BCR_m = v;
+ writel(v, pi->brg_base + BRG_BCR);
return;
}
static void
mpsc_brg_disable(struct mpsc_port_info *pi)
{
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 16, 0);
+ u32 v;
+
+ v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
+ v &= ~(1 << 16);
+
+ if (pi->mirror_regs)
+ pi->BRG_BCR_m = v;
+ writel(v, pi->brg_base + BRG_BCR);
return;
}
@@ -115,10 +135,16 @@
* that accounts for the way the mpsc is set up is:
* CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
*/
- u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
+ u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
+ u32 v;
mpsc_brg_disable(pi);
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 16, 0, cdv);
+ v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
+ v = (v & 0x) | (cdv & 0x);
+
+ if (pi->mirror_regs)
+ pi->BRG_BCR_m = v;
+ writel(v, pi->brg_base + BRG_BCR);
mpsc_brg_enable(pi);
return;
@@ -135,7 +161,7 @@
static void
mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
{
- u32 v;
+ u32 v;
pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
pi->port.line, burst_size);
@@ -151,7 +177,8 @@
else
v = 0x3;/* 8 64-bit words */
- MPSC_MOD_FIELD(pi, sdma, SDMA_SDC, 2, 12, v);
+ writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
+ pi->sdma_base + SDMA_SDC);
return;
}
@@ -161,7 +188,8 @@
pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
burst_size);
- MPSC_MOD_FIELD(pi, sdma, SDMA_SDC, 10, 0, 0x03f);
+ writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
+ pi->sdma_base + SDMA_SDC);
mpsc_sdma_burstsize(pi,
[PATCH][SERIAL] mpsc updates
Hi again, Andrew.
This patch:
- replaces several macros with the actual code
- change the type of pointer variables from u32 to void *
- removes unecessary casts
- puts the contents of mpsc_defs.h into mpsc.h and removes the mpsc_defs.h
- reflects the new names of some structs
- cleans up some whitespace
Signed-off-by: Mark A. Greer [EMAIL PROTECTED]
--
diff -Nru a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c
--- a/drivers/serial/mpsc.c 2005-01-25 17:28:43 -07:00
+++ b/drivers/serial/mpsc.c 2005-01-25 17:28:43 -07:00
@@ -36,16 +36,14 @@
*
* 1) Some chips have an erratum where several regs cannot be
* read. To work around that, we keep a local copy of those regs in
- * 'mpsc_port_info' and use the *_M or *_S macros when accessing those regs.
+ * 'mpsc_port_info'.
*
* 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
- * accesses system mem in a cache coherent region. This *should* be a
- * show-stopper when coherency is turned on but it seems to work okay as
- * long as there are no snoop hits. Therefore, the ring buffer entries and
- * the buffers themselves are allocated via 'dma_alloc_noncoherent()' and
- * 'dma_cache_sync()' is used. Also, since most PPC platforms are coherent
- * which makes 'dma_cache_sync()' a no-op, explicit cache management macros
- * have been added ensuring there are no snoop hits when coherency is on.
+ * accesses system mem with coherency enabled. For that reason, the driver
+ * assumes that coherency for that ctlr has been disabled. This means
+ * that when in a cache coherent system, the driver has to manually manage
+ * the data cache on the areas that it touches because the dma_* macro are
+ * basically no-ops.
*
* 3) There is an erratum (on PPC) where you can't use the instruction to do
* a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
@@ -54,7 +52,6 @@
* 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
*/
-#include linux/mv643xx.h
#include mpsc.h
/*
@@ -81,25 +78,48 @@
static void
mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
{
+ u32 v;
+
+ v = (pi-mirror_regs) ? pi-BRG_BCR_m : readl(pi-brg_base + BRG_BCR);
+ v = (v ~(0xf 18)) | ((clk_src 0xf) 18);
+
if (pi-brg_can_tune)
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 25, 0);
+ v = ~(1 25);
+
+ if (pi-mirror_regs)
+ pi-BRG_BCR_m = v;
+ writel(v, pi-brg_base + BRG_BCR);
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 4, 18, clk_src);
- MPSC_MOD_FIELD(pi, brg, BRG_BTR, 16, 0, 0);
+ writel(readl(pi-brg_base + BRG_BTR) 0x,
+ pi-brg_base + BRG_BTR);
return;
}
static void
mpsc_brg_enable(struct mpsc_port_info *pi)
{
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 16, 1);
+ u32 v;
+
+ v = (pi-mirror_regs) ? pi-BRG_BCR_m : readl(pi-brg_base + BRG_BCR);
+ v |= (1 16);
+
+ if (pi-mirror_regs)
+ pi-BRG_BCR_m = v;
+ writel(v, pi-brg_base + BRG_BCR);
return;
}
static void
mpsc_brg_disable(struct mpsc_port_info *pi)
{
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 16, 0);
+ u32 v;
+
+ v = (pi-mirror_regs) ? pi-BRG_BCR_m : readl(pi-brg_base + BRG_BCR);
+ v = ~(1 16);
+
+ if (pi-mirror_regs)
+ pi-BRG_BCR_m = v;
+ writel(v, pi-brg_base + BRG_BCR);
return;
}
@@ -115,10 +135,16 @@
* that accounts for the way the mpsc is set up is:
* CDV = (clk / (baud*2*16)) - 1 == CDV = (clk / (baud 5)) - 1.
*/
- u32 cdv = (pi-port.uartclk / (baud 5)) - 1;
+ u32 cdv = (pi-port.uartclk / (baud 5)) - 1;
+ u32 v;
mpsc_brg_disable(pi);
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 16, 0, cdv);
+ v = (pi-mirror_regs) ? pi-BRG_BCR_m : readl(pi-brg_base + BRG_BCR);
+ v = (v 0x) | (cdv 0x);
+
+ if (pi-mirror_regs)
+ pi-BRG_BCR_m = v;
+ writel(v, pi-brg_base + BRG_BCR);
mpsc_brg_enable(pi);
return;
@@ -135,7 +161,7 @@
static void
mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
{
- u32 v;
+ u32 v;
pr_debug(mpsc_sdma_burstsize[%d]: burst_size: %d\n,
pi-port.line, burst_size);
@@ -151,7 +177,8 @@
else
v = 0x3;/* 8 64-bit words */
- MPSC_MOD_FIELD(pi, sdma, SDMA_SDC, 2, 12, v);
+ writel((readl(pi-sdma_base + SDMA_SDC) (0x3 12)) | (v 12),
+ pi-sdma_base + SDMA_SDC);
return;
}
@@ -161,7 +188,8 @@
pr_debug(mpsc_sdma_init[%d]: burst_size: %d\n, pi-port.line,
burst_size);
- MPSC_MOD_FIELD(pi, sdma, SDMA_SDC, 10, 0, 0x03f);
+ writel((readl(pi-sdma_base + SDMA_SDC) 0x3ff) | 0x03f,
+ pi-sdma_base + SDMA_SDC);
mpsc_sdma_burstsize(pi, burst_size);
return;
}
@@ -169,16 +197,21 @@
