Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On 05/20/2013 07:39 PM, Jongsung Kim wrote: > Jongsung Kim : >> Stephen Warren : All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011 TRM: r1p4-r1p5 Contains the following differences in functionality: * The receive and transmit FIFOs are increased to a depth of > 32. * The Revision field in the UARTPeriphID2 Register on page > 3-24 bits [7:4] now reads back as 0x3. >>> >>> Well, that certainly isn't true in practice. I think we should revert >>> this commit until we can determine what the problem is. >> >> I asked to the ARM support about this. Waiting for reply.. > > ARM support said they doesn't have information about BCM2835 UART. Does > anyone have a communication channel to Broadcom? It takes time for me to > get contact point to Broadcom.. (I'm trying) > > However, ARM support also said: > > "If the Broadcom part definitely has 16-deep FIFOs, it cannot be based > on a PL011 r1p5, so I might guess that Broadcom have just referenced > the latest version of the documentation on our website, but have actually > implemented an earlier version." This all seems rather academic. Irrespective of what the cause of the problem is, the commit actively breaks a previously working configuration. I still believe we should revert it first, then find out exactly what's going on later. Should I sent the revert commit? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Jongsung Kim : > Stephen Warren : >>> All r1p5 have 32-byte FIFO depth and it's not configurable. From the >>> PL011 >>> TRM: >>> >>> r1p4-r1p5 Contains the following differences in functionality: >>> * The receive and transmit FIFOs are increased to a depth of 32. >>> * The Revision field in the UARTPeriphID2 Register on page 3-24 >>> bits [7:4] now reads back as 0x3. >> >> Well, that certainly isn't true in practice. I think we should revert >> this commit until we can determine what the problem is. > > I asked to the ARM support about this. Waiting for reply.. ARM support said they doesn't have information about BCM2835 UART. Does anyone have a communication channel to Broadcom? It takes time for me to get contact point to Broadcom.. (I'm trying) However, ARM support also said: "If the Broadcom part definitely has 16-deep FIFOs, it cannot be based on a PL011 r1p5, so I might guess that Broadcom have just referenced the latest version of the documentation on our website, but have actually implemented an earlier version." -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Jongsung Kim neidhard@lge.com : Stephen Warren swar...@wwwdotorg.org : All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011 TRM: r1p4-r1p5 Contains the following differences in functionality: * The receive and transmit FIFOs are increased to a depth of 32. * The Revision field in the UARTPeriphID2 Register on page 3-24 bits [7:4] now reads back as 0x3. Well, that certainly isn't true in practice. I think we should revert this commit until we can determine what the problem is. I asked to the ARM support about this. Waiting for reply.. ARM support said they doesn't have information about BCM2835 UART. Does anyone have a communication channel to Broadcom? It takes time for me to get contact point to Broadcom.. (I'm trying) However, ARM support also said: If the Broadcom part definitely has 16-deep FIFOs, it cannot be based on a PL011 r1p5, so I might guess that Broadcom have just referenced the latest version of the documentation on our website, but have actually implemented an earlier version. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On 05/20/2013 07:39 PM, Jongsung Kim wrote: Jongsung Kim neidhard@lge.com : Stephen Warren swar...@wwwdotorg.org : All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011 TRM: r1p4-r1p5 Contains the following differences in functionality: * The receive and transmit FIFOs are increased to a depth of 32. * The Revision field in the UARTPeriphID2 Register on page 3-24 bits [7:4] now reads back as 0x3. Well, that certainly isn't true in practice. I think we should revert this commit until we can determine what the problem is. I asked to the ARM support about this. Waiting for reply.. ARM support said they doesn't have information about BCM2835 UART. Does anyone have a communication channel to Broadcom? It takes time for me to get contact point to Broadcom.. (I'm trying) However, ARM support also said: If the Broadcom part definitely has 16-deep FIFOs, it cannot be based on a PL011 r1p5, so I might guess that Broadcom have just referenced the latest version of the documentation on our website, but have actually implemented an earlier version. This all seems rather academic. Irrespective of what the cause of the problem is, the commit actively breaks a previously working configuration. I still believe we should revert it first, then find out exactly what's going on later. Should I sent the revert commit? -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Stephen Warren : >> All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011 >> TRM: >> >> r1p4-r1p5Contains the following differences in functionality: >> * The receive and transmit FIFOs are increased to a depth of 32. >> * The Revision field in the UARTPeriphID2 Register on page 3-24 >>bits [7:4] now reads back as 0x3. > > Well, that certainly isn't true in practice. I think we should revert > this commit until we can determine what the problem is. I asked to the ARM support about this. Waiting for reply.. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Stephen Warren swar...@wwwdotorg.org : All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011 TRM: r1p4-r1p5Contains the following differences in functionality: * The receive and transmit FIFOs are increased to a depth of 32. * The Revision field in the UARTPeriphID2 Register on page 3-24 bits [7:4] now reads back as 0x3. Well, that certainly isn't true in practice. I think we should revert this commit until we can determine what the problem is. I asked to the ARM support about this. Waiting for reply.. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Tue, May 14, 2013 at 10:59:58PM -0600, Stephen Warren wrote: > Well, that certainly isn't true in practice. I think we should revert > this commit until we can determine what the problem is. > > I validated that the periphid register in HW contains the r1p5 revision > (3), and the pcellid register does indeed contain the expected > 0xb105f00d value. However, if I run the following hacky code in U-Boot > to determine the FIFO depth, it comes out as 16, which explains the > symptoms I'm seeing: We could do that, just like we do in 8250.c to check the FIFO depth. There's not much harm in doing that at boot time, it just needs to be done carefully so that it doesn't disrupt any existing use of the UART. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Tue, May 14, 2013 at 10:59:58PM -0600, Stephen Warren wrote: Well, that certainly isn't true in practice. I think we should revert this commit until we can determine what the problem is. I validated that the periphid register in HW contains the r1p5 revision (3), and the pcellid register does indeed contain the expected 0xb105f00d value. However, if I run the following hacky code in U-Boot to determine the FIFO depth, it comes out as 16, which explains the symptoms I'm seeing: We could do that, just like we do in 8250.c to check the FIFO depth. There's not much harm in doing that at boot time, it just needs to be done carefully so that it doesn't disrupt any existing use of the UART. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On 05/14/2013 07:00 PM, Jongsung Kim wrote:
> Stephen Warren :
>> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for
>> the BCM2835 chip), I see:
>>
>> =
>> The UART provides:
>> * Separate 16x8 transmit and 16x12 receive FIFO memory.
>> ...
>> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
>> (PL011) Revision: r1p5 Technical Reference Manual.
>> =
>>
>> That seems to imply that not all r1p5 PL011s actually have a depth-32 FIFO.
>> Perhaps this is a configurable property of the IP block, not something that
>> all r1p5 have?
>
> All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011
> TRM:
>
> r1p4-r1p5 Contains the following differences in functionality:
> * The receive and transmit FIFOs are increased to a depth of 32.
> * The Revision field in the UARTPeriphID2 Register on page 3-24
> bits [7:4] now reads back as 0x3.
Well, that certainly isn't true in practice. I think we should revert
this commit until we can determine what the problem is.
I validated that the periphid register in HW contains the r1p5 revision
(3), and the pcellid register does indeed contain the expected
0xb105f00d value. However, if I run the following hacky code in U-Boot
to determine the FIFO depth, it comes out as 16, which explains the
symptoms I'm seeing:
void find_fifo_depth(void)
{
volatile u8 *uart = 0x20201000;
int depth = 0;
/* Wait for TX FIFO empty */
while (!(uart[0x18] & 0x80))
;
/* Disable UART */
uart[0x30] &= ~1;
/* Push chars into TX FIFO until full */
for (;;) {
uart[0] = 'A' + depth;
depth++;
/* Done if FIFO full */
if (uart[0x18] & 0x20)
break;
if (depth > 64) {
depth = -1;
break;
}
}
/* Re-enable UART */
uart[0x30] |= 1;
printf("FIFO depth: %d\n", depth);
}
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Stephen Warren : > Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for > the BCM2835 chip), I see: > > = > The UART provides: > * Separate 16x8 transmit and 16x12 receive FIFO memory. > ... > For the in-depth UART overview, please, refer to the ARM PrimeCell UART > (PL011) Revision: r1p5 Technical Reference Manual. > = > > That seems to imply that not all r1p5 PL011s actually have a depth-32 FIFO. > Perhaps this is a configurable property of the IP block, not something that > all r1p5 have? All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011 TRM: r1p4-r1p5 Contains the following differences in functionality: * The receive and transmit FIFOs are increased to a depth of 32. * The Revision field in the UARTPeriphID2 Register on page 3-24 bits [7:4] now reads back as 0x3. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Tue, May 14, 2013 at 03:03:14PM -0600, Stephen Warren wrote:
> On 05/14/2013 01:15 AM, Jongsung Kim wrote:
> > Stephen Warren :
> >> For reference, the AMBA periphid of the UART device there is 0x00341011.
> >> The nibble "3" is the revision being tested in:
> >
> > The UART device has periphid 0x00341011, and is compatible with the
> > original PL011 prior to r1p5. Not with r1p5. It could be a possible
> > way to specify the compatible periphid (such as 0x00241011) instead
> > of just 0x0 when initializing the amba_device for the UART.
> >
> >>> +static unsigned int get_fifosize_arm(unsigned int periphid)
> >>> +{
> >>> + unsigned int rev = (periphid >> 20) & 0xf;
> >>> + return rev < 3 ? 16 : 32;
> >>> +}
> ...
> > Doesn't the BCM2835 UART have anything different from the ARM PL011?
> > What about the UARTPCellID registers? They are set to 0xb105f00d with
> > the ARM PL011.
>
> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation
> for the BCM2835 chip), I see:
>
> =
> The UART provides:
> * Separate 16x8 transmit and 16x12 receive FIFO memory.
> ...
> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
> (PL011) Revision: r1p5 Technical Reference Manual.
> =
>
> That seems to imply that not all r1p5 PL011s actually have a depth-32
> FIFO. Perhaps this is a configurable property of the IP block, not
> something that all r1p5 have?
>
> I can't check the UARTPCellID registers right now.
The PCellID value is a marker for primecells, and is common to all primecells
which implement the ID scheme. It's the other ID registers you want. :)
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On 05/14/2013 01:15 AM, Jongsung Kim wrote:
> Stephen Warren :
>> For reference, the AMBA periphid of the UART device there is 0x00341011.
>> The nibble "3" is the revision being tested in:
>
> The UART device has periphid 0x00341011, and is compatible with the
> original PL011 prior to r1p5. Not with r1p5. It could be a possible
> way to specify the compatible periphid (such as 0x00241011) instead
> of just 0x0 when initializing the amba_device for the UART.
>
>>> +static unsigned int get_fifosize_arm(unsigned int periphid)
>>> +{
>>> + unsigned int rev = (periphid >> 20) & 0xf;
>>> + return rev < 3 ? 16 : 32;
>>> +}
...
> Doesn't the BCM2835 UART have anything different from the ARM PL011?
> What about the UARTPCellID registers? They are set to 0xb105f00d with
> the ARM PL011.
Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation
for the BCM2835 chip), I see:
=
The UART provides:
* Separate 16x8 transmit and 16x12 receive FIFO memory.
...
For the in-depth UART overview, please, refer to the ARM PrimeCell UART
(PL011) Revision: r1p5 Technical Reference Manual.
=
That seems to imply that not all r1p5 PL011s actually have a depth-32
FIFO. Perhaps this is a configurable property of the IP block, not
something that all r1p5 have?
I can't check the UARTPCellID registers right now.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Stephen Warren :
> For reference, the AMBA periphid of the UART device there is 0x00341011.
> The nibble "3" is the revision being tested in:
The UART device has periphid 0x00341011, and is compatible with the
original PL011 prior to r1p5. Not with r1p5. It could be a possible
way to specify the compatible periphid (such as 0x00241011) instead
of just 0x0 when initializing the amba_device for the UART.
> > +static unsigned int get_fifosize_arm(unsigned int periphid)
> > +{
> > + unsigned int rev = (periphid >> 20) & 0xf;
> > + return rev < 3 ? 16 : 32;
> > +}
>
> Should that be <= not <, or is there just something more wrong in the
> patch or bcm2835 HW? I wonder how r1p5 maps to 3 in the test above.
>From the PL011-r1p5 TRM, bits[7:4] of the UARTPeriphID2 register are
read as:
r1p0 - 0x0
r1p1 - 0x1
r1p3 - 0x2
r1p4 - 0x2
r1p5 - 0x3.
Doesn't the BCM2835 UART have anything different from the ARM PL011?
What about the UARTPCellID registers? They are set to 0xb105f00d with
the ARM PL011.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Stephen Warren swar...@wwwdotorg.org :
For reference, the AMBA periphid of the UART device there is 0x00341011.
The nibble 3 is the revision being tested in:
The UART device has periphid 0x00341011, and is compatible with the
original PL011 prior to r1p5. Not with r1p5. It could be a possible
way to specify the compatible periphid (such as 0x00241011) instead
of just 0x0 when initializing the amba_device for the UART.
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid 20) 0xf;
+ return rev 3 ? 16 : 32;
+}
Should that be = not , or is there just something more wrong in the
patch or bcm2835 HW? I wonder how r1p5 maps to 3 in the test above.
From the PL011-r1p5 TRM, bits[7:4] of the UARTPeriphID2 register are
read as:
r1p0 - 0x0
r1p1 - 0x1
r1p3 - 0x2
r1p4 - 0x2
r1p5 - 0x3.
Doesn't the BCM2835 UART have anything different from the ARM PL011?
What about the UARTPCellID registers? They are set to 0xb105f00d with
the ARM PL011.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On 05/14/2013 01:15 AM, Jongsung Kim wrote:
Stephen Warren swar...@wwwdotorg.org :
For reference, the AMBA periphid of the UART device there is 0x00341011.
The nibble 3 is the revision being tested in:
The UART device has periphid 0x00341011, and is compatible with the
original PL011 prior to r1p5. Not with r1p5. It could be a possible
way to specify the compatible periphid (such as 0x00241011) instead
of just 0x0 when initializing the amba_device for the UART.
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid 20) 0xf;
+ return rev 3 ? 16 : 32;
+}
...
Doesn't the BCM2835 UART have anything different from the ARM PL011?
What about the UARTPCellID registers? They are set to 0xb105f00d with
the ARM PL011.
Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation
for the BCM2835 chip), I see:
=
The UART provides:
* Separate 16x8 transmit and 16x12 receive FIFO memory.
...
For the in-depth UART overview, please, refer to the ARM PrimeCell UART
(PL011) Revision: r1p5 Technical Reference Manual.
=
That seems to imply that not all r1p5 PL011s actually have a depth-32
FIFO. Perhaps this is a configurable property of the IP block, not
something that all r1p5 have?
I can't check the UARTPCellID registers right now.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Tue, May 14, 2013 at 03:03:14PM -0600, Stephen Warren wrote:
On 05/14/2013 01:15 AM, Jongsung Kim wrote:
Stephen Warren swar...@wwwdotorg.org :
For reference, the AMBA periphid of the UART device there is 0x00341011.
The nibble 3 is the revision being tested in:
The UART device has periphid 0x00341011, and is compatible with the
original PL011 prior to r1p5. Not with r1p5. It could be a possible
way to specify the compatible periphid (such as 0x00241011) instead
of just 0x0 when initializing the amba_device for the UART.
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid 20) 0xf;
+ return rev 3 ? 16 : 32;
+}
...
Doesn't the BCM2835 UART have anything different from the ARM PL011?
What about the UARTPCellID registers? They are set to 0xb105f00d with
the ARM PL011.
Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation
for the BCM2835 chip), I see:
=
The UART provides:
* Separate 16x8 transmit and 16x12 receive FIFO memory.
...
For the in-depth UART overview, please, refer to the ARM PrimeCell UART
(PL011) Revision: r1p5 Technical Reference Manual.
=
That seems to imply that not all r1p5 PL011s actually have a depth-32
FIFO. Perhaps this is a configurable property of the IP block, not
something that all r1p5 have?
I can't check the UARTPCellID registers right now.
The PCellID value is a marker for primecells, and is common to all primecells
which implement the ID scheme. It's the other ID registers you want. :)
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Stephen Warren swar...@wwwdotorg.org : Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for the BCM2835 chip), I see: = The UART provides: * Separate 16x8 transmit and 16x12 receive FIFO memory. ... For the in-depth UART overview, please, refer to the ARM PrimeCell UART (PL011) Revision: r1p5 Technical Reference Manual. = That seems to imply that not all r1p5 PL011s actually have a depth-32 FIFO. Perhaps this is a configurable property of the IP block, not something that all r1p5 have? All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011 TRM: r1p4-r1p5 Contains the following differences in functionality: * The receive and transmit FIFOs are increased to a depth of 32. * The Revision field in the UARTPeriphID2 Register on page 3-24 bits [7:4] now reads back as 0x3. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On 05/14/2013 07:00 PM, Jongsung Kim wrote:
Stephen Warren swar...@wwwdotorg.org :
Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for
the BCM2835 chip), I see:
=
The UART provides:
* Separate 16x8 transmit and 16x12 receive FIFO memory.
...
For the in-depth UART overview, please, refer to the ARM PrimeCell UART
(PL011) Revision: r1p5 Technical Reference Manual.
=
That seems to imply that not all r1p5 PL011s actually have a depth-32 FIFO.
Perhaps this is a configurable property of the IP block, not something that
all r1p5 have?
All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011
TRM:
r1p4-r1p5 Contains the following differences in functionality:
* The receive and transmit FIFOs are increased to a depth of 32.
* The Revision field in the UARTPeriphID2 Register on page 3-24
bits [7:4] now reads back as 0x3.
Well, that certainly isn't true in practice. I think we should revert
this commit until we can determine what the problem is.
I validated that the periphid register in HW contains the r1p5 revision
(3), and the pcellid register does indeed contain the expected
0xb105f00d value. However, if I run the following hacky code in U-Boot
to determine the FIFO depth, it comes out as 16, which explains the
symptoms I'm seeing:
void find_fifo_depth(void)
{
volatile u8 *uart = 0x20201000;
int depth = 0;
/* Wait for TX FIFO empty */
while (!(uart[0x18] 0x80))
;
/* Disable UART */
uart[0x30] = ~1;
/* Push chars into TX FIFO until full */
for (;;) {
uart[0] = 'A' + depth;
depth++;
/* Done if FIFO full */
if (uart[0x18] 0x20)
break;
if (depth 64) {
depth = -1;
break;
}
}
/* Re-enable UART */
uart[0x30] |= 1;
printf(FIFO depth: %d\n, depth);
}
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On 04/12/2013 03:18 AM, Jongsung Kim wrote:
> The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs, while all
> earlier ones have 16-byte FIFOs. This patch suggests a way to set the
> FIFO-size correctly & flexibly by using a
> function(vendor_data::get_fifosize) rather than using the
> vendor_data::fifosize variable. The function takes the UARTPeriphID, and
> returns the correct size.
This change (now part of 3.10-rc1) breaks the serial port on the BCM2835
ARM SoC (part of the Raspberry Pi). Sorry for not noticing this earlier;
a combination of my vacation and laziness I guess.
For reference, the AMBA periphid of the UART device there is 0x00341011.
The nibble "3" is the revision being tested in:
> +static unsigned int get_fifosize_arm(unsigned int periphid)
> +{
> + unsigned int rev = (periphid >> 20) & 0xf;
> + return rev < 3 ? 16 : 32;
> +}
Should that be <= not <, or is there just something more wrong in the
patch or bcm2835 HW? I wonder how r1p5 maps to 3 in the test above.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On 04/12/2013 03:18 AM, Jongsung Kim wrote:
The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs, while all
earlier ones have 16-byte FIFOs. This patch suggests a way to set the
FIFO-size correctly flexibly by using a
function(vendor_data::get_fifosize) rather than using the
vendor_data::fifosize variable. The function takes the UARTPeriphID, and
returns the correct size.
This change (now part of 3.10-rc1) breaks the serial port on the BCM2835
ARM SoC (part of the Raspberry Pi). Sorry for not noticing this earlier;
a combination of my vacation and laziness I guess.
For reference, the AMBA periphid of the UART device there is 0x00341011.
The nibble 3 is the revision being tested in:
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid 20) 0xf;
+ return rev 3 ? 16 : 32;
+}
Should that be = not , or is there just something more wrong in the
patch or bcm2835 HW? I wonder how r1p5 maps to 3 in the test above.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Mon, Apr 22, 2013 at 11:24:18AM +0900, Jongsung Kim wrote: > Thank you for your comments, Russell. I'll happily apply your recommendation > just after it come up to the merge window. Or, do you want me to send it by > now? Sorry, don't understand what you're asking, could you rephrase please? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Mon, Apr 22, 2013 at 11:24:18AM +0900, Jongsung Kim wrote: Thank you for your comments, Russell. I'll happily apply your recommendation just after it come up to the merge window. Or, do you want me to send it by now? Sorry, don't understand what you're asking, could you rephrase please? -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
RE: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Thank you for your comments, Russell. I'll happily apply your recommendation just after it come up to the merge window. Or, do you want me to send it by now? -Original Message- From: Russell King - ARM Linux [mailto:li...@arm.linux.org.uk] Sent: Friday, April 19, 2013 11:18 PM To: Jongsung Kim Cc: gre...@linuxfoundation.org; jsl...@suse.cz; linux-ser...@vger.kernel.org; linux-kernel@vger.kernel.org Subject: Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5 On Mon, Apr 15, 2013 at 02:45:25PM +0900, Jongsung Kim wrote: > The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs, > while all earlier ones have 16-byte FIFOs. This patch suggests > a way to set the FIFO-size correctly & flexibly by using a member > function named get_fifosize, rather than using the fifosize member > variable. The function takes the UARTPeriphID, and returns the > correct FIFO size. Same comments as previous version. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Sat, Apr 20, 2013 at 03:31:39PM +0200, Linus Walleij wrote:
> static struct amba_id pl011_ids[] = {
> {
> .id = 0x00341011,
> .mask = 0x00ff,
> .data = _arm_deepfifo,
> },
> (...)
> };
>
> As you can see in amba_lookup() in
> drivers/amba/bus.c the table is traversed from the top,
> so for the new "3" variant this entry will match, while the
> next entry will match all older versions.
This isn't equivalent - this will only match variant 3, not any later
ones. The original patch uses the deep fifo for variant 3 or larger.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Sat, Apr 20, 2013 at 03:31:39PM +0200, Linus Walleij wrote:
static struct amba_id pl011_ids[] = {
{
.id = 0x00341011,
.mask = 0x00ff,
.data = vendor_arm_deepfifo,
},
(...)
};
As you can see in amba_lookup() in
drivers/amba/bus.c the table is traversed from the top,
so for the new 3 variant this entry will match, while the
next entry will match all older versions.
This isn't equivalent - this will only match variant 3, not any later
ones. The original patch uses the deep fifo for variant 3 or larger.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
RE: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Thank you for your comments, Russell. I'll happily apply your recommendation just after it come up to the merge window. Or, do you want me to send it by now? -Original Message- From: Russell King - ARM Linux [mailto:li...@arm.linux.org.uk] Sent: Friday, April 19, 2013 11:18 PM To: Jongsung Kim Cc: gre...@linuxfoundation.org; jsl...@suse.cz; linux-ser...@vger.kernel.org; linux-kernel@vger.kernel.org Subject: Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5 On Mon, Apr 15, 2013 at 02:45:25PM +0900, Jongsung Kim wrote: The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs, while all earlier ones have 16-byte FIFOs. This patch suggests a way to set the FIFO-size correctly flexibly by using a member function named get_fifosize, rather than using the fifosize member variable. The function takes the UARTPeriphID, and returns the correct FIFO size. Same comments as previous version. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Mon, Apr 15, 2013 at 7:45 AM, Jongsung Kim wrote:
At the risk to re-stating what Russell has already said...
> +
> + unsigned int (*get_fifosize)(unsigned int periphid);
> };
>
> +static unsigned int get_fifosize_arm(unsigned int periphid)
> +{
> + unsigned int rev = (periphid >> 20) & 0xf;
> + return rev < 3 ? 16 : 32;
> +}
This is a very complicated way to to something very simple.
Keep the .fifosize as part of struct vendor_data, define a
new vendor data cunk for your variant, use .id and .mask
to select your variant.
static struct vendor_data vendor_arm_deepfifo = {
.fifosize = 32,
(... the rest is the same)
}
(...)
static struct amba_id pl011_ids[] = {
{
.id = 0x00341011,
.mask = 0x00ff,
.data = _arm_deepfifo,
},
(...)
};
As you can see in amba_lookup() in
drivers/amba/bus.c the table is traversed from the top,
so for the new "3" variant this entry will match, while the
next entry will match all older versions.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Mon, Apr 15, 2013 at 7:45 AM, Jongsung Kim neidhard@lge.com wrote:
At the risk to re-stating what Russell has already said...
+
+ unsigned int (*get_fifosize)(unsigned int periphid);
};
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid 20) 0xf;
+ return rev 3 ? 16 : 32;
+}
This is a very complicated way to to something very simple.
Keep the .fifosize as part of struct vendor_data, define a
new vendor data cunk for your variant, use .id and .mask
to select your variant.
static struct vendor_data vendor_arm_deepfifo = {
.fifosize = 32,
(... the rest is the same)
}
(...)
static struct amba_id pl011_ids[] = {
{
.id = 0x00341011,
.mask = 0x00ff,
.data = vendor_arm_deepfifo,
},
(...)
};
As you can see in amba_lookup() in
drivers/amba/bus.c the table is traversed from the top,
so for the new 3 variant this entry will match, while the
next entry will match all older versions.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Mon, Apr 15, 2013 at 02:45:25PM +0900, Jongsung Kim wrote: > The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs, > while all earlier ones have 16-byte FIFOs. This patch suggests > a way to set the FIFO-size correctly & flexibly by using a member > function named get_fifosize, rather than using the fifosize member > variable. The function takes the UARTPeriphID, and returns the > correct FIFO size. Same comments as previous version. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Fri, Apr 12, 2013 at 06:18:47PM +0900, Jongsung Kim wrote:
> +static unsigned int get_fifosize_arm(unsigned int periphid)
> +{
> + unsigned int rev = (periphid >> 20) & 0xf;
> + return rev < 3 ? 16 : 32;
Don't we have a macro to get the revision given the amba device?
amba_rev().
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Fri, Apr 12, 2013 at 06:18:47PM +0900, Jongsung Kim wrote:
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid 20) 0xf;
+ return rev 3 ? 16 : 32;
Don't we have a macro to get the revision given the amba device?
amba_rev().
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
On Mon, Apr 15, 2013 at 02:45:25PM +0900, Jongsung Kim wrote: The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs, while all earlier ones have 16-byte FIFOs. This patch suggests a way to set the FIFO-size correctly flexibly by using a member function named get_fifosize, rather than using the fifosize member variable. The function takes the UARTPeriphID, and returns the correct FIFO size. Same comments as previous version. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs,
while all earlier ones have 16-byte FIFOs. This patch suggests
a way to set the FIFO-size correctly & flexibly by using a member
function named get_fifosize, rather than using the fifosize member
variable. The function takes the UARTPeriphID, and returns the
correct FIFO size.
Signed-off-by: Jongsung Kim
---
drivers/tty/serial/amba-pl011.c | 20
1 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 3ea5408..22af0c8 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -72,32 +72,44 @@
/* There is by now at least one vendor with differing details, so handle it */
struct vendor_data {
unsigned intifls;
- unsigned intfifosize;
unsigned intlcrh_tx;
unsigned intlcrh_rx;
booloversampling;
booldma_threshold;
boolcts_event_workaround;
+
+ unsigned int (*get_fifosize)(unsigned int periphid);
};
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid >> 20) & 0xf;
+ return rev < 3 ? 16 : 32;
+}
+
static struct vendor_data vendor_arm = {
.ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
- .fifosize = 16,
.lcrh_tx= UART011_LCRH,
.lcrh_rx= UART011_LCRH,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
+ .get_fifosize = get_fifosize_arm,
};
+static unsigned int get_fifosize_st(unsigned int periphid)
+{
+ return 64;
+}
+
static struct vendor_data vendor_st = {
.ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
- .fifosize = 64,
.lcrh_tx= ST_UART011_LCRH_TX,
.lcrh_rx= ST_UART011_LCRH_RX,
.oversampling = true,
.dma_threshold = true,
.cts_event_workaround = true,
+ .get_fifosize = get_fifosize_st,
};
static struct uart_amba_port *amba_ports[UART_NR];
@@ -2010,7 +2022,7 @@ static int pl011_probe(struct amba_device *dev, const
struct amba_id *id)
uap->lcrh_rx = vendor->lcrh_rx;
uap->lcrh_tx = vendor->lcrh_tx;
uap->old_cr = 0;
- uap->fifosize = vendor->fifosize;
+ uap->fifosize = vendor->get_fifosize(dev->periphid);
uap->port.dev = >dev;
uap->port.mapbase = dev->res.start;
uap->port.membase = base;
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[RESEND][PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs,
while all earlier ones have 16-byte FIFOs. This patch suggests
a way to set the FIFO-size correctly flexibly by using a member
function named get_fifosize, rather than using the fifosize member
variable. The function takes the UARTPeriphID, and returns the
correct FIFO size.
Signed-off-by: Jongsung Kim neidhard@lge.com
---
drivers/tty/serial/amba-pl011.c | 20
1 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 3ea5408..22af0c8 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -72,32 +72,44 @@
/* There is by now at least one vendor with differing details, so handle it */
struct vendor_data {
unsigned intifls;
- unsigned intfifosize;
unsigned intlcrh_tx;
unsigned intlcrh_rx;
booloversampling;
booldma_threshold;
boolcts_event_workaround;
+
+ unsigned int (*get_fifosize)(unsigned int periphid);
};
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid 20) 0xf;
+ return rev 3 ? 16 : 32;
+}
+
static struct vendor_data vendor_arm = {
.ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
- .fifosize = 16,
.lcrh_tx= UART011_LCRH,
.lcrh_rx= UART011_LCRH,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
+ .get_fifosize = get_fifosize_arm,
};
+static unsigned int get_fifosize_st(unsigned int periphid)
+{
+ return 64;
+}
+
static struct vendor_data vendor_st = {
.ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
- .fifosize = 64,
.lcrh_tx= ST_UART011_LCRH_TX,
.lcrh_rx= ST_UART011_LCRH_RX,
.oversampling = true,
.dma_threshold = true,
.cts_event_workaround = true,
+ .get_fifosize = get_fifosize_st,
};
static struct uart_amba_port *amba_ports[UART_NR];
@@ -2010,7 +2022,7 @@ static int pl011_probe(struct amba_device *dev, const
struct amba_id *id)
uap-lcrh_rx = vendor-lcrh_rx;
uap-lcrh_tx = vendor-lcrh_tx;
uap-old_cr = 0;
- uap-fifosize = vendor-fifosize;
+ uap-fifosize = vendor-get_fifosize(dev-periphid);
uap-port.dev = dev-dev;
uap-port.mapbase = dev-res.start;
uap-port.membase = base;
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs, while all
earlier ones have 16-byte FIFOs. This patch suggests a way to set the
FIFO-size correctly & flexibly by using a
function(vendor_data::get_fifosize) rather than using the
vendor_data::fifosize variable. The function takes the UARTPeriphID, and
returns the correct size.
Signed-off-by: Jongsung Kim
drivers/tty/serial/amba-pl011.c | 20
1 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/amba-pl011.c
b/drivers/tty/serial/amba-pl011.c
index 3ea5408..22af0c8 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -72,32 +72,44 @@
/* There is by now at least one vendor with differing details, so handle it
*/
struct vendor_data {
unsigned intifls;
- unsigned intfifosize;
unsigned intlcrh_tx;
unsigned intlcrh_rx;
booloversampling;
booldma_threshold;
boolcts_event_workaround;
+
+ unsigned int (*get_fifosize)(unsigned int periphid);
};
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid >> 20) & 0xf;
+ return rev < 3 ? 16 : 32;
+}
+
static struct vendor_data vendor_arm = {
.ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
- .fifosize = 16,
.lcrh_tx= UART011_LCRH,
.lcrh_rx= UART011_LCRH,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
+ .get_fifosize = get_fifosize_arm,
};
+static unsigned int get_fifosize_st(unsigned int periphid)
+{
+ return 64;
+}
+
static struct vendor_data vendor_st = {
.ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
- .fifosize = 64,
.lcrh_tx= ST_UART011_LCRH_TX,
.lcrh_rx= ST_UART011_LCRH_RX,
.oversampling = true,
.dma_threshold = true,
.cts_event_workaround = true,
+ .get_fifosize = get_fifosize_st,
};
static struct uart_amba_port *amba_ports[UART_NR];
@@ -2010,7 +2022,7 @@ static int pl011_probe(struct amba_device *dev, const
struct amba_id *id)
uap->lcrh_rx = vendor->lcrh_rx;
uap->lcrh_tx = vendor->lcrh_tx;
uap->old_cr = 0;
- uap->fifosize = vendor->fifosize;
+ uap->fifosize = vendor->get_fifosize(dev->periphid);
uap->port.dev = >dev;
uap->port.mapbase = dev->res.start;
uap->port.membase = base;
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
The latest r1p5-revision of the ARM PL011 UART has 32-byte FIFOs, while all
earlier ones have 16-byte FIFOs. This patch suggests a way to set the
FIFO-size correctly flexibly by using a
function(vendor_data::get_fifosize) rather than using the
vendor_data::fifosize variable. The function takes the UARTPeriphID, and
returns the correct size.
Signed-off-by: Jongsung Kim neidhard@lge.com
drivers/tty/serial/amba-pl011.c | 20
1 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/amba-pl011.c
b/drivers/tty/serial/amba-pl011.c
index 3ea5408..22af0c8 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -72,32 +72,44 @@
/* There is by now at least one vendor with differing details, so handle it
*/
struct vendor_data {
unsigned intifls;
- unsigned intfifosize;
unsigned intlcrh_tx;
unsigned intlcrh_rx;
booloversampling;
booldma_threshold;
boolcts_event_workaround;
+
+ unsigned int (*get_fifosize)(unsigned int periphid);
};
+static unsigned int get_fifosize_arm(unsigned int periphid)
+{
+ unsigned int rev = (periphid 20) 0xf;
+ return rev 3 ? 16 : 32;
+}
+
static struct vendor_data vendor_arm = {
.ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
- .fifosize = 16,
.lcrh_tx= UART011_LCRH,
.lcrh_rx= UART011_LCRH,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
+ .get_fifosize = get_fifosize_arm,
};
+static unsigned int get_fifosize_st(unsigned int periphid)
+{
+ return 64;
+}
+
static struct vendor_data vendor_st = {
.ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
- .fifosize = 64,
.lcrh_tx= ST_UART011_LCRH_TX,
.lcrh_rx= ST_UART011_LCRH_RX,
.oversampling = true,
.dma_threshold = true,
.cts_event_workaround = true,
+ .get_fifosize = get_fifosize_st,
};
static struct uart_amba_port *amba_ports[UART_NR];
@@ -2010,7 +2022,7 @@ static int pl011_probe(struct amba_device *dev, const
struct amba_id *id)
uap-lcrh_rx = vendor-lcrh_rx;
uap-lcrh_tx = vendor-lcrh_tx;
uap-old_cr = 0;
- uap-fifosize = vendor-fifosize;
+ uap-fifosize = vendor-get_fifosize(dev-periphid);
uap-port.dev = dev-dev;
uap-port.mapbase = dev-res.start;
uap-port.membase = base;
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
