Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Lorenzo Pieralisi]

On Wed, Jan 03, 2018 at 02:26:29PM +0900, Jaehoon Chung wrote:
> On 01/03/2018 01:34 AM, Lorenzo Pieralisi wrote:
> > On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
> >> pci-exynos had updated to use the PHY framework.
> >> (drivers/phy/samsung/phy-exynos-pcie.c)
> >> Removed the depreccated codes relevant to phy in pci-exynos.c.
> >> Instead, use the phy-exynos-pcie.c file.
> >>
> >> Modified the binding documentation.
> >>
> >> Signed-off-by: Jaehoon Chung 
> >> ---
> >>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
> >>  drivers/pci/dwc/pci-exynos.c   | 219 
> >> ++---
> >>  2 files changed, 22 insertions(+), 255 deletions(-)
> > 
> > I have updated the commit log to the patch below, please
> > check before I push it out.
> 
> Looks good to me. At next time, i will write the commit-msg more carefully.

No problem, applied to pci/dwc for v4.16, thanks.

Lorenzo

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Lorenzo Pieralisi]

On Wed, Jan 03, 2018 at 02:26:29PM +0900, Jaehoon Chung wrote:
> On 01/03/2018 01:34 AM, Lorenzo Pieralisi wrote:
> > On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
> >> pci-exynos had updated to use the PHY framework.
> >> (drivers/phy/samsung/phy-exynos-pcie.c)
> >> Removed the depreccated codes relevant to phy in pci-exynos.c.
> >> Instead, use the phy-exynos-pcie.c file.
> >>
> >> Modified the binding documentation.
> >>
> >> Signed-off-by: Jaehoon Chung 
> >> ---
> >>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
> >>  drivers/pci/dwc/pci-exynos.c   | 219 
> >> ++---
> >>  2 files changed, 22 insertions(+), 255 deletions(-)
> > 
> > I have updated the commit log to the patch below, please
> > check before I push it out.
> 
> Looks good to me. At next time, i will write the commit-msg more carefully.

No problem, applied to pci/dwc for v4.16, thanks.

Lorenzo

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Jaehoon Chung]

On 01/03/2018 01:34 AM, Lorenzo Pieralisi wrote:
> On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
>> pci-exynos had updated to use the PHY framework.
>> (drivers/phy/samsung/phy-exynos-pcie.c)
>> Removed the depreccated codes relevant to phy in pci-exynos.c.
>> Instead, use the phy-exynos-pcie.c file.
>>
>> Modified the binding documentation.
>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>>  drivers/pci/dwc/pci-exynos.c   | 219 
>> ++---
>>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> I have updated the commit log to the patch below, please
> check before I push it out.

Looks good to me. At next time, i will write the commit-msg more carefully.

> 
> Lorenzo
> 
> -- >8 --
> Subject: [PATCH] PCI: exynos: Remove deprecated PHY initialization code
> 
> Exynos platforms have a PCI PHY driver in the PHY framework that can be
> used by the PCI host bridge drivers to initialize and manage the PHY.
> 
> Remove the deprecated PHY initialization code in the Exynos PCI host
> bridge driver by updating the driver to use the PHY framework API;
> modify the DT binding documentation accordingly.
> 
> Signed-off-by: Jaehoon Chung 
> [lorenzo.pieral...@arm.com: updated commit log]
> Signed-off-by: Lorenzo Pieralisi 
> Acked-by: Jingoo Han 
> Reviewed-by: Rob Herring 
> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219 
> ++---
>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> diff --git 
> a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt 
> b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> index 34a11bfbfb60..651d957d1051 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> @@ -6,9 +6,6 @@ and thus inherits all the common properties defined in 
> designware-pcie.txt.
>  Required properties:
>  - compatible: "samsung,exynos5440-pcie"
>  - reg: base addresses and lengths of the PCIe controller,
> - the PHY controller, additional register for the PHY controller.
> - (Registers for the PHY controller are DEPRECATED.
> -  Use the PHY framework.)
>  - reg-names : First name should be set to "elbi".
>   And use the "config" instead of getting the configuration address space
>   from "ranges".
> @@ -23,49 +20,8 @@ For other common properties, refer to
>  
>  Example:
>  
> -SoC-specific DT Entry:
> +SoC-specific DT Entry (with using PHY framework):
>  
> - pcie@29 {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x29 0x1000
> - 0x27 0x1000
> - 0x271000 0x40>;
> - interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
> - clocks = < 28>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x4000 0x4000 0 0x1000   /* 
> configuration space */
> -   0x8100 0 0  0x40001000 0 0x0001   /* 
> downstream I/O */
> -   0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /* 
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> - pcie@2a {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x2a 0x1000
> - 0x272000 0x1000
> - 0x271040 0x40>;
> - interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
> - clocks = < 29>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x6000 0x6000 0 0x1000   /* 
> configuration space */
> -   0x8100 0 0  0x60001000 0 0x0001   /* 
> downstream I/O */
> -   0x8200 0 0x60011000 0x60011000 0 0x1ffef000>; /* 
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> -With using PHY framework:
>   pcie_phy0: pcie-phy@27 {
>   ...
>   reg = <0x27 0x1000>, <0x271000 0x40>;
> @@ -74,13 +30,21 @@ With using PHY framework:
>   };
>  
>   

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Jaehoon Chung]

On 01/03/2018 01:34 AM, Lorenzo Pieralisi wrote:
> On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
>> pci-exynos had updated to use the PHY framework.
>> (drivers/phy/samsung/phy-exynos-pcie.c)
>> Removed the depreccated codes relevant to phy in pci-exynos.c.
>> Instead, use the phy-exynos-pcie.c file.
>>
>> Modified the binding documentation.
>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>>  drivers/pci/dwc/pci-exynos.c   | 219 
>> ++---
>>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> I have updated the commit log to the patch below, please
> check before I push it out.

Looks good to me. At next time, i will write the commit-msg more carefully.

> 
> Lorenzo
> 
> -- >8 --
> Subject: [PATCH] PCI: exynos: Remove deprecated PHY initialization code
> 
> Exynos platforms have a PCI PHY driver in the PHY framework that can be
> used by the PCI host bridge drivers to initialize and manage the PHY.
> 
> Remove the deprecated PHY initialization code in the Exynos PCI host
> bridge driver by updating the driver to use the PHY framework API;
> modify the DT binding documentation accordingly.
> 
> Signed-off-by: Jaehoon Chung 
> [lorenzo.pieral...@arm.com: updated commit log]
> Signed-off-by: Lorenzo Pieralisi 
> Acked-by: Jingoo Han 
> Reviewed-by: Rob Herring 
> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219 
> ++---
>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> diff --git 
> a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt 
> b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> index 34a11bfbfb60..651d957d1051 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> @@ -6,9 +6,6 @@ and thus inherits all the common properties defined in 
> designware-pcie.txt.
>  Required properties:
>  - compatible: "samsung,exynos5440-pcie"
>  - reg: base addresses and lengths of the PCIe controller,
> - the PHY controller, additional register for the PHY controller.
> - (Registers for the PHY controller are DEPRECATED.
> -  Use the PHY framework.)
>  - reg-names : First name should be set to "elbi".
>   And use the "config" instead of getting the configuration address space
>   from "ranges".
> @@ -23,49 +20,8 @@ For other common properties, refer to
>  
>  Example:
>  
> -SoC-specific DT Entry:
> +SoC-specific DT Entry (with using PHY framework):
>  
> - pcie@29 {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x29 0x1000
> - 0x27 0x1000
> - 0x271000 0x40>;
> - interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
> - clocks = < 28>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x4000 0x4000 0 0x1000   /* 
> configuration space */
> -   0x8100 0 0  0x40001000 0 0x0001   /* 
> downstream I/O */
> -   0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /* 
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> - pcie@2a {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x2a 0x1000
> - 0x272000 0x1000
> - 0x271040 0x40>;
> - interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
> - clocks = < 29>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x6000 0x6000 0 0x1000   /* 
> configuration space */
> -   0x8100 0 0  0x60001000 0 0x0001   /* 
> downstream I/O */
> -   0x8200 0 0x60011000 0x60011000 0 0x1ffef000>; /* 
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> -With using PHY framework:
>   pcie_phy0: pcie-phy@27 {
>   ...
>   reg = <0x27 0x1000>, <0x271000 0x40>;
> @@ -74,13 +30,21 @@ With using PHY framework:
>   };
>  
>   pcie@29 {
> - ...
> + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
>   

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Jingoo Han]

On Tuesday, January 2, 2018 11:34 AM, Lorenzo Pieralisi wrote:
> On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
> > pci-exynos had updated to use the PHY framework.
> > (drivers/phy/samsung/phy-exynos-pcie.c)
> > Removed the depreccated codes relevant to phy in pci-exynos.c.
> > Instead, use the phy-exynos-pcie.c file.
> >
> > Modified the binding documentation.
> >
> > Signed-off-by: Jaehoon Chung 
> > ---
> >  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
> >  drivers/pci/dwc/pci-exynos.c   | 219
++-
> --
> >  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> I have updated the commit log to the patch below, please
> check before I push it out.

I think that the commit message looks good.
Thank you.

Best regards,
Jingoo Han

> 
> Lorenzo
> 
> -- >8 --
> Subject: [PATCH] PCI: exynos: Remove deprecated PHY initialization code
> 
> Exynos platforms have a PCI PHY driver in the PHY framework that can be
> used by the PCI host bridge drivers to initialize and manage the PHY.
> 
> Remove the deprecated PHY initialization code in the Exynos PCI host
> bridge driver by updating the driver to use the PHY framework API;
> modify the DT binding documentation accordingly.
> 
> Signed-off-by: Jaehoon Chung 
> [lorenzo.pieral...@arm.com: updated commit log]
> Signed-off-by: Lorenzo Pieralisi 
> Acked-by: Jingoo Han 
> Reviewed-by: Rob Herring 
> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219
++--
> -
>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt
> index 34a11bfbfb60..651d957d1051 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> @@ -6,9 +6,6 @@ and thus inherits all the common properties defined in
> designware-pcie.txt.
>  Required properties:
>  - compatible: "samsung,exynos5440-pcie"
>  - reg: base addresses and lengths of the PCIe controller,
> - the PHY controller, additional register for the PHY controller.
> - (Registers for the PHY controller are DEPRECATED.
> -  Use the PHY framework.)
>  - reg-names : First name should be set to "elbi".
>   And use the "config" instead of getting the configuration address
> space
>   from "ranges".
> @@ -23,49 +20,8 @@ For other common properties, refer to
> 
>  Example:
> 
> -SoC-specific DT Entry:
> +SoC-specific DT Entry (with using PHY framework):
> 
> - pcie@29 {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x29 0x1000
> - 0x27 0x1000
> - 0x271000 0x40>;
> - interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
> - clocks = < 28>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x4000 0x4000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x40001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x40011000 0x40011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> - pcie@2a {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x2a 0x1000
> - 0x272000 0x1000
> - 0x271040 0x40>;
> - interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
> - clocks = < 29>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x6000 0x6000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x60001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> -With using PHY framework:
>   pcie_phy0: pcie-phy@27 {
>   ...
>   reg = <0x27 0x1000>, <0x271000 0x40>;
> @@ -74,13 +30,21 @@ With using PHY framework:
>   };
> 

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Jingoo Han]

On Tuesday, January 2, 2018 11:34 AM, Lorenzo Pieralisi wrote:
> On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
> > pci-exynos had updated to use the PHY framework.
> > (drivers/phy/samsung/phy-exynos-pcie.c)
> > Removed the depreccated codes relevant to phy in pci-exynos.c.
> > Instead, use the phy-exynos-pcie.c file.
> >
> > Modified the binding documentation.
> >
> > Signed-off-by: Jaehoon Chung 
> > ---
> >  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
> >  drivers/pci/dwc/pci-exynos.c   | 219
++-
> --
> >  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> I have updated the commit log to the patch below, please
> check before I push it out.

I think that the commit message looks good.
Thank you.

Best regards,
Jingoo Han

> 
> Lorenzo
> 
> -- >8 --
> Subject: [PATCH] PCI: exynos: Remove deprecated PHY initialization code
> 
> Exynos platforms have a PCI PHY driver in the PHY framework that can be
> used by the PCI host bridge drivers to initialize and manage the PHY.
> 
> Remove the deprecated PHY initialization code in the Exynos PCI host
> bridge driver by updating the driver to use the PHY framework API;
> modify the DT binding documentation accordingly.
> 
> Signed-off-by: Jaehoon Chung 
> [lorenzo.pieral...@arm.com: updated commit log]
> Signed-off-by: Lorenzo Pieralisi 
> Acked-by: Jingoo Han 
> Reviewed-by: Rob Herring 
> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219
++--
> -
>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt
> index 34a11bfbfb60..651d957d1051 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> @@ -6,9 +6,6 @@ and thus inherits all the common properties defined in
> designware-pcie.txt.
>  Required properties:
>  - compatible: "samsung,exynos5440-pcie"
>  - reg: base addresses and lengths of the PCIe controller,
> - the PHY controller, additional register for the PHY controller.
> - (Registers for the PHY controller are DEPRECATED.
> -  Use the PHY framework.)
>  - reg-names : First name should be set to "elbi".
>   And use the "config" instead of getting the configuration address
> space
>   from "ranges".
> @@ -23,49 +20,8 @@ For other common properties, refer to
> 
>  Example:
> 
> -SoC-specific DT Entry:
> +SoC-specific DT Entry (with using PHY framework):
> 
> - pcie@29 {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x29 0x1000
> - 0x27 0x1000
> - 0x271000 0x40>;
> - interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
> - clocks = < 28>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x4000 0x4000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x40001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x40011000 0x40011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> - pcie@2a {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x2a 0x1000
> - 0x272000 0x1000
> - 0x271040 0x40>;
> - interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
> - clocks = < 29>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x6000 0x6000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x60001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> -With using PHY framework:
>   pcie_phy0: pcie-phy@27 {
>   ...
>   reg = <0x27 0x1000>, <0x271000 0x40>;
> @@ -74,13 +30,21 @@ With using PHY framework:
>   };
> 
>   pcie@29 {
> - ...
> + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Lorenzo Pieralisi]

On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
> pci-exynos had updated to use the PHY framework.
> (drivers/phy/samsung/phy-exynos-pcie.c)
> Removed the depreccated codes relevant to phy in pci-exynos.c.
> Instead, use the phy-exynos-pcie.c file.
> 
> Modified the binding documentation.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219 
> ++---
>  2 files changed, 22 insertions(+), 255 deletions(-)

I have updated the commit log to the patch below, please
check before I push it out.

Lorenzo

-- >8 --
Subject: [PATCH] PCI: exynos: Remove deprecated PHY initialization code

Exynos platforms have a PCI PHY driver in the PHY framework that can be
used by the PCI host bridge drivers to initialize and manage the PHY.

Remove the deprecated PHY initialization code in the Exynos PCI host
bridge driver by updating the driver to use the PHY framework API;
modify the DT binding documentation accordingly.

Signed-off-by: Jaehoon Chung 
[lorenzo.pieral...@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Jingoo Han 
Reviewed-by: Rob Herring 
---
 .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
 drivers/pci/dwc/pci-exynos.c   | 219 ++---
 2 files changed, 22 insertions(+), 255 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt 
b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 34a11bfbfb60..651d957d1051 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -6,9 +6,6 @@ and thus inherits all the common properties defined in 
designware-pcie.txt.
 Required properties:
 - compatible: "samsung,exynos5440-pcie"
 - reg: base addresses and lengths of the PCIe controller,
-   the PHY controller, additional register for the PHY controller.
-   (Registers for the PHY controller are DEPRECATED.
-Use the PHY framework.)
 - reg-names : First name should be set to "elbi".
And use the "config" instead of getting the configuration address space
from "ranges".
@@ -23,49 +20,8 @@ For other common properties, refer to
 
 Example:
 
-SoC-specific DT Entry:
+SoC-specific DT Entry (with using PHY framework):
 
-   pcie@29 {
-   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x29 0x1000
-   0x27 0x1000
-   0x271000 0x40>;
-   interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
-   clocks = < 28>, < 27>;
-   clock-names = "pcie", "pcie_bus";
-   #address-cells = <3>;
-   #size-cells = <2>;
-   device_type = "pci";
-   ranges = <0x0800 0 0x4000 0x4000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x40001000 0 0x0001   /* 
downstream I/O */
- 0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /* 
non-prefetchable memory */
-   #interrupt-cells = <1>;
-   interrupt-map-mask = <0 0 0 0>;
-   interrupt-map = <0 0 0 0  GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-   num-lanes = <4>;
-   };
-
-   pcie@2a {
-   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x2a 0x1000
-   0x272000 0x1000
-   0x271040 0x40>;
-   interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
-   clocks = < 29>, < 27>;
-   clock-names = "pcie", "pcie_bus";
-   #address-cells = <3>;
-   #size-cells = <2>;
-   device_type = "pci";
-   ranges = <0x0800 0 0x6000 0x6000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x60001000 0 0x0001   /* 
downstream I/O */
- 0x8200 0 0x60011000 0x60011000 0 0x1ffef000>; /* 
non-prefetchable memory */
-   #interrupt-cells = <1>;
-   interrupt-map-mask = <0 0 0 0>;
-   interrupt-map = <0 0 0 0  GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-   num-lanes = <4>;
-   };
-
-With using PHY framework:
pcie_phy0: pcie-phy@27 {
...
reg = <0x27 0x1000>, <0x271000 0x40>;
@@ -74,13 +30,21 @@ With using PHY framework:
};
 
pcie@29 {
-   ...
+   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
reg = <0x29 0x1000>, <0x4000 0x1000>;
reg-names = "elbi", "config";
+   clocks = < 28>, < 27>;
+   

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Lorenzo Pieralisi]

On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
> pci-exynos had updated to use the PHY framework.
> (drivers/phy/samsung/phy-exynos-pcie.c)
> Removed the depreccated codes relevant to phy in pci-exynos.c.
> Instead, use the phy-exynos-pcie.c file.
> 
> Modified the binding documentation.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219 
> ++---
>  2 files changed, 22 insertions(+), 255 deletions(-)

I have updated the commit log to the patch below, please
check before I push it out.

Lorenzo

-- >8 --
Subject: [PATCH] PCI: exynos: Remove deprecated PHY initialization code

Exynos platforms have a PCI PHY driver in the PHY framework that can be
used by the PCI host bridge drivers to initialize and manage the PHY.

Remove the deprecated PHY initialization code in the Exynos PCI host
bridge driver by updating the driver to use the PHY framework API;
modify the DT binding documentation accordingly.

Signed-off-by: Jaehoon Chung 
[lorenzo.pieral...@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Jingoo Han 
Reviewed-by: Rob Herring 
---
 .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
 drivers/pci/dwc/pci-exynos.c   | 219 ++---
 2 files changed, 22 insertions(+), 255 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt 
b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 34a11bfbfb60..651d957d1051 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -6,9 +6,6 @@ and thus inherits all the common properties defined in 
designware-pcie.txt.
 Required properties:
 - compatible: "samsung,exynos5440-pcie"
 - reg: base addresses and lengths of the PCIe controller,
-   the PHY controller, additional register for the PHY controller.
-   (Registers for the PHY controller are DEPRECATED.
-Use the PHY framework.)
 - reg-names : First name should be set to "elbi".
And use the "config" instead of getting the configuration address space
from "ranges".
@@ -23,49 +20,8 @@ For other common properties, refer to
 
 Example:
 
-SoC-specific DT Entry:
+SoC-specific DT Entry (with using PHY framework):
 
-   pcie@29 {
-   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x29 0x1000
-   0x27 0x1000
-   0x271000 0x40>;
-   interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
-   clocks = < 28>, < 27>;
-   clock-names = "pcie", "pcie_bus";
-   #address-cells = <3>;
-   #size-cells = <2>;
-   device_type = "pci";
-   ranges = <0x0800 0 0x4000 0x4000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x40001000 0 0x0001   /* 
downstream I/O */
- 0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /* 
non-prefetchable memory */
-   #interrupt-cells = <1>;
-   interrupt-map-mask = <0 0 0 0>;
-   interrupt-map = <0 0 0 0  GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-   num-lanes = <4>;
-   };
-
-   pcie@2a {
-   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x2a 0x1000
-   0x272000 0x1000
-   0x271040 0x40>;
-   interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
-   clocks = < 29>, < 27>;
-   clock-names = "pcie", "pcie_bus";
-   #address-cells = <3>;
-   #size-cells = <2>;
-   device_type = "pci";
-   ranges = <0x0800 0 0x6000 0x6000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x60001000 0 0x0001   /* 
downstream I/O */
- 0x8200 0 0x60011000 0x60011000 0 0x1ffef000>; /* 
non-prefetchable memory */
-   #interrupt-cells = <1>;
-   interrupt-map-mask = <0 0 0 0>;
-   interrupt-map = <0 0 0 0  GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-   num-lanes = <4>;
-   };
-
-With using PHY framework:
pcie_phy0: pcie-phy@27 {
...
reg = <0x27 0x1000>, <0x271000 0x40>;
@@ -74,13 +30,21 @@ With using PHY framework:
};
 
pcie@29 {
-   ...
+   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
reg = <0x29 0x1000>, <0x4000 0x1000>;
reg-names = "elbi", "config";
+   clocks = < 28>, < 27>;
+   clock-names = "pcie", "pcie_bus";
+   #address-cells = <3>;
+   #size-cells = <2>;
+  

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Rob Herring]

On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
> pci-exynos had updated to use the PHY framework.
> (drivers/phy/samsung/phy-exynos-pcie.c)
> Removed the depreccated codes relevant to phy in pci-exynos.c.
> Instead, use the phy-exynos-pcie.c file.
> 
> Modified the binding documentation.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219 
> ++---
>  2 files changed, 22 insertions(+), 255 deletions(-)

Reviewed-by: Rob Herring 

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Rob Herring]

On Wed, Dec 27, 2017 at 06:43:27PM +0900, Jaehoon Chung wrote:
> pci-exynos had updated to use the PHY framework.
> (drivers/phy/samsung/phy-exynos-pcie.c)
> Removed the depreccated codes relevant to phy in pci-exynos.c.
> Instead, use the phy-exynos-pcie.c file.
> 
> Modified the binding documentation.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219 
> ++---
>  2 files changed, 22 insertions(+), 255 deletions(-)

Reviewed-by: Rob Herring 

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Jingoo Han]

On Wednesday, December 27, 2017 1:43 AM, Jaehoon Chung wrote:
> 
> pci-exynos had updated to use the PHY framework.
> (drivers/phy/samsung/phy-exynos-pcie.c)
> Removed the depreccated codes relevant to phy in pci-exynos.c.
> Instead, use the phy-exynos-pcie.c file.
> 
> Modified the binding documentation.
> 
> Signed-off-by: Jaehoon Chung 

(I resend my email, because Bjorn's address was wrong in the previous
email.)

Thank you for your patch.
It looks good.

Acked-by: Jingoo Han 

Best regards,
Jingoo Han

> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219
++---
>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt
> index 34a11bfbfb60..651d957d1051 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> @@ -6,9 +6,6 @@ and thus inherits all the common properties defined in
> designware-pcie.txt.
>  Required properties:
>  - compatible: "samsung,exynos5440-pcie"
>  - reg: base addresses and lengths of the PCIe controller,
> - the PHY controller, additional register for the PHY controller.
> - (Registers for the PHY controller are DEPRECATED.
> -  Use the PHY framework.)
>  - reg-names : First name should be set to "elbi".
>   And use the "config" instead of getting the configuration address
> space
>   from "ranges".
> @@ -23,49 +20,8 @@ For other common properties, refer to
> 
>  Example:
> 
> -SoC-specific DT Entry:
> +SoC-specific DT Entry (with using PHY framework):
> 
> - pcie@29 {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x29 0x1000
> - 0x27 0x1000
> - 0x271000 0x40>;
> - interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
> - clocks = < 28>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x4000 0x4000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x40001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x40011000 0x40011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> - pcie@2a {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x2a 0x1000
> - 0x272000 0x1000
> - 0x271040 0x40>;
> - interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
> - clocks = < 29>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x6000 0x6000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x60001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> -With using PHY framework:
>   pcie_phy0: pcie-phy@27 {
>   ...
>   reg = <0x27 0x1000>, <0x271000 0x40>;
> @@ -74,13 +30,21 @@ With using PHY framework:
>   };
> 
>   pcie@29 {
> - ...
> + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
>   reg = <0x29 0x1000>, <0x4000 0x1000>;
>   reg-names = "elbi", "config";
> + clocks = < 28>, < 27>;
> + clock-names = "pcie", "pcie_bus";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
>   phys = <_phy0>;
>   ranges = <0x8100 0 0  0x60001000 0 0x0001
> 0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
> - ...
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> + num-lanes = <4>;
>   };
> 
>  Board-specific DT Entry:
> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
> index 5596fdedbb94..56f32aeebd0a 100644
> --- 

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Jingoo Han]

On Wednesday, December 27, 2017 1:43 AM, Jaehoon Chung wrote:
> 
> pci-exynos had updated to use the PHY framework.
> (drivers/phy/samsung/phy-exynos-pcie.c)
> Removed the depreccated codes relevant to phy in pci-exynos.c.
> Instead, use the phy-exynos-pcie.c file.
> 
> Modified the binding documentation.
> 
> Signed-off-by: Jaehoon Chung 

(I resend my email, because Bjorn's address was wrong in the previous
email.)

Thank you for your patch.
It looks good.

Acked-by: Jingoo Han 

Best regards,
Jingoo Han

> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219
++---
>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt
> index 34a11bfbfb60..651d957d1051 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> @@ -6,9 +6,6 @@ and thus inherits all the common properties defined in
> designware-pcie.txt.
>  Required properties:
>  - compatible: "samsung,exynos5440-pcie"
>  - reg: base addresses and lengths of the PCIe controller,
> - the PHY controller, additional register for the PHY controller.
> - (Registers for the PHY controller are DEPRECATED.
> -  Use the PHY framework.)
>  - reg-names : First name should be set to "elbi".
>   And use the "config" instead of getting the configuration address
> space
>   from "ranges".
> @@ -23,49 +20,8 @@ For other common properties, refer to
> 
>  Example:
> 
> -SoC-specific DT Entry:
> +SoC-specific DT Entry (with using PHY framework):
> 
> - pcie@29 {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x29 0x1000
> - 0x27 0x1000
> - 0x271000 0x40>;
> - interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
> - clocks = < 28>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x4000 0x4000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x40001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x40011000 0x40011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> - pcie@2a {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x2a 0x1000
> - 0x272000 0x1000
> - 0x271040 0x40>;
> - interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
> - clocks = < 29>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x6000 0x6000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x60001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> -With using PHY framework:
>   pcie_phy0: pcie-phy@27 {
>   ...
>   reg = <0x27 0x1000>, <0x271000 0x40>;
> @@ -74,13 +30,21 @@ With using PHY framework:
>   };
> 
>   pcie@29 {
> - ...
> + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
>   reg = <0x29 0x1000>, <0x4000 0x1000>;
>   reg-names = "elbi", "config";
> + clocks = < 28>, < 27>;
> + clock-names = "pcie", "pcie_bus";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
>   phys = <_phy0>;
>   ranges = <0x8100 0 0  0x60001000 0 0x0001
> 0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
> - ...
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> + num-lanes = <4>;
>   };
> 
>  Board-specific DT Entry:
> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
> index 5596fdedbb94..56f32aeebd0a 100644
> --- a/drivers/pci/dwc/pci-exynos.c
> +++ 

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Jingoo Han]

On Wednesday, December 27, 2017 1:43 AM, Jaehoon Chung wrote:
> 
> pci-exynos had updated to use the PHY framework.
> (drivers/phy/samsung/phy-exynos-pcie.c)
> Removed the depreccated codes relevant to phy in pci-exynos.c.
> Instead, use the phy-exynos-pcie.c file.
> 
> Modified the binding documentation.
> 
> Signed-off-by: Jaehoon Chung 

Thank you for your patch.
It looks good.

Acked-by: Jingoo Han 

Best regards,
Jingoo Han

> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219
++---
>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt
> index 34a11bfbfb60..651d957d1051 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> @@ -6,9 +6,6 @@ and thus inherits all the common properties defined in
> designware-pcie.txt.
>  Required properties:
>  - compatible: "samsung,exynos5440-pcie"
>  - reg: base addresses and lengths of the PCIe controller,
> - the PHY controller, additional register for the PHY controller.
> - (Registers for the PHY controller are DEPRECATED.
> -  Use the PHY framework.)
>  - reg-names : First name should be set to "elbi".
>   And use the "config" instead of getting the configuration address
> space
>   from "ranges".
> @@ -23,49 +20,8 @@ For other common properties, refer to
> 
>  Example:
> 
> -SoC-specific DT Entry:
> +SoC-specific DT Entry (with using PHY framework):
> 
> - pcie@29 {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x29 0x1000
> - 0x27 0x1000
> - 0x271000 0x40>;
> - interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
> - clocks = < 28>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x4000 0x4000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x40001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x40011000 0x40011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> - pcie@2a {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x2a 0x1000
> - 0x272000 0x1000
> - 0x271040 0x40>;
> - interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
> - clocks = < 29>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x6000 0x6000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x60001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> -With using PHY framework:
>   pcie_phy0: pcie-phy@27 {
>   ...
>   reg = <0x27 0x1000>, <0x271000 0x40>;
> @@ -74,13 +30,21 @@ With using PHY framework:
>   };
> 
>   pcie@29 {
> - ...
> + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
>   reg = <0x29 0x1000>, <0x4000 0x1000>;
>   reg-names = "elbi", "config";
> + clocks = < 28>, < 27>;
> + clock-names = "pcie", "pcie_bus";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
>   phys = <_phy0>;
>   ranges = <0x8100 0 0  0x60001000 0 0x0001
> 0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
> - ...
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> + num-lanes = <4>;
>   };
> 
>  Board-specific DT Entry:
> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
> index 5596fdedbb94..56f32aeebd0a 100644
> --- a/drivers/pci/dwc/pci-exynos.c
> +++ b/drivers/pci/dwc/pci-exynos.c
> @@ -55,49 

Re: [PATCH] PCI: exynos: remove the deprecated phy codes

[Jingoo Han]

On Wednesday, December 27, 2017 1:43 AM, Jaehoon Chung wrote:
> 
> pci-exynos had updated to use the PHY framework.
> (drivers/phy/samsung/phy-exynos-pcie.c)
> Removed the depreccated codes relevant to phy in pci-exynos.c.
> Instead, use the phy-exynos-pcie.c file.
> 
> Modified the binding documentation.
> 
> Signed-off-by: Jaehoon Chung 

Thank you for your patch.
It looks good.

Acked-by: Jingoo Han 

Best regards,
Jingoo Han

> ---
>  .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
>  drivers/pci/dwc/pci-exynos.c   | 219
++---
>  2 files changed, 22 insertions(+), 255 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-
> pcie.txt
> index 34a11bfbfb60..651d957d1051 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> @@ -6,9 +6,6 @@ and thus inherits all the common properties defined in
> designware-pcie.txt.
>  Required properties:
>  - compatible: "samsung,exynos5440-pcie"
>  - reg: base addresses and lengths of the PCIe controller,
> - the PHY controller, additional register for the PHY controller.
> - (Registers for the PHY controller are DEPRECATED.
> -  Use the PHY framework.)
>  - reg-names : First name should be set to "elbi".
>   And use the "config" instead of getting the configuration address
> space
>   from "ranges".
> @@ -23,49 +20,8 @@ For other common properties, refer to
> 
>  Example:
> 
> -SoC-specific DT Entry:
> +SoC-specific DT Entry (with using PHY framework):
> 
> - pcie@29 {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x29 0x1000
> - 0x27 0x1000
> - 0x271000 0x40>;
> - interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
> - clocks = < 28>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x4000 0x4000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x40001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x40011000 0x40011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> - pcie@2a {
> - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
> - reg = <0x2a 0x1000
> - 0x272000 0x1000
> - 0x271040 0x40>;
> - interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
> - clocks = < 29>, < 27>;
> - clock-names = "pcie", "pcie_bus";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - ranges = <0x0800 0 0x6000 0x6000 0 0x1000
> /* configuration space */
> -   0x8100 0 0  0x60001000 0 0x0001
/*
> downstream I/O */
> -   0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
/*
> non-prefetchable memory */
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0  GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> - num-lanes = <4>;
> - };
> -
> -With using PHY framework:
>   pcie_phy0: pcie-phy@27 {
>   ...
>   reg = <0x27 0x1000>, <0x271000 0x40>;
> @@ -74,13 +30,21 @@ With using PHY framework:
>   };
> 
>   pcie@29 {
> - ...
> + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
>   reg = <0x29 0x1000>, <0x4000 0x1000>;
>   reg-names = "elbi", "config";
> + clocks = < 28>, < 27>;
> + clock-names = "pcie", "pcie_bus";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
>   phys = <_phy0>;
>   ranges = <0x8100 0 0  0x60001000 0 0x0001
> 0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
> - ...
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 21
> IRQ_TYPE_LEVEL_HIGH>;
> + num-lanes = <4>;
>   };
> 
>  Board-specific DT Entry:
> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
> index 5596fdedbb94..56f32aeebd0a 100644
> --- a/drivers/pci/dwc/pci-exynos.c
> +++ b/drivers/pci/dwc/pci-exynos.c
> @@ -55,49 +55,8 @@
>  #define PCIE_ELBI_SLV_ARMISC 

[PATCH] PCI: exynos: remove the deprecated phy codes

[Jaehoon Chung]

pci-exynos had updated to use the PHY framework.
(drivers/phy/samsung/phy-exynos-pcie.c)
Removed the depreccated codes relevant to phy in pci-exynos.c.
Instead, use the phy-exynos-pcie.c file.

Modified the binding documentation.

Signed-off-by: Jaehoon Chung 
---
 .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
 drivers/pci/dwc/pci-exynos.c   | 219 ++---
 2 files changed, 22 insertions(+), 255 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt 
b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 34a11bfbfb60..651d957d1051 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -6,9 +6,6 @@ and thus inherits all the common properties defined in 
designware-pcie.txt.
 Required properties:
 - compatible: "samsung,exynos5440-pcie"
 - reg: base addresses and lengths of the PCIe controller,
-   the PHY controller, additional register for the PHY controller.
-   (Registers for the PHY controller are DEPRECATED.
-Use the PHY framework.)
 - reg-names : First name should be set to "elbi".
And use the "config" instead of getting the configuration address space
from "ranges".
@@ -23,49 +20,8 @@ For other common properties, refer to
 
 Example:
 
-SoC-specific DT Entry:
+SoC-specific DT Entry (with using PHY framework):
 
-   pcie@29 {
-   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x29 0x1000
-   0x27 0x1000
-   0x271000 0x40>;
-   interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
-   clocks = < 28>, < 27>;
-   clock-names = "pcie", "pcie_bus";
-   #address-cells = <3>;
-   #size-cells = <2>;
-   device_type = "pci";
-   ranges = <0x0800 0 0x4000 0x4000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x40001000 0 0x0001   /* 
downstream I/O */
- 0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /* 
non-prefetchable memory */
-   #interrupt-cells = <1>;
-   interrupt-map-mask = <0 0 0 0>;
-   interrupt-map = <0 0 0 0  GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-   num-lanes = <4>;
-   };
-
-   pcie@2a {
-   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x2a 0x1000
-   0x272000 0x1000
-   0x271040 0x40>;
-   interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
-   clocks = < 29>, < 27>;
-   clock-names = "pcie", "pcie_bus";
-   #address-cells = <3>;
-   #size-cells = <2>;
-   device_type = "pci";
-   ranges = <0x0800 0 0x6000 0x6000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x60001000 0 0x0001   /* 
downstream I/O */
- 0x8200 0 0x60011000 0x60011000 0 0x1ffef000>; /* 
non-prefetchable memory */
-   #interrupt-cells = <1>;
-   interrupt-map-mask = <0 0 0 0>;
-   interrupt-map = <0 0 0 0  GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-   num-lanes = <4>;
-   };
-
-With using PHY framework:
pcie_phy0: pcie-phy@27 {
...
reg = <0x27 0x1000>, <0x271000 0x40>;
@@ -74,13 +30,21 @@ With using PHY framework:
};
 
pcie@29 {
-   ...
+   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
reg = <0x29 0x1000>, <0x4000 0x1000>;
reg-names = "elbi", "config";
+   clocks = < 28>, < 27>;
+   clock-names = "pcie", "pcie_bus";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
phys = <_phy0>;
ranges = <0x8100 0 0  0x60001000 0 0x0001
  0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
-   ...
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+   num-lanes = <4>;
};
 
 Board-specific DT Entry:
diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index 5596fdedbb94..56f32aeebd0a 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -55,49 +55,8 @@
 #define PCIE_ELBI_SLV_ARMISC   0x120
 #define PCIE_ELBI_SLV_DBI_ENABLE   BIT(21)
 
-/* PCIe Purple registers */
-#define PCIE_PHY_GLOBAL_RESET  0x000
-#define PCIE_PHY_COMMON_RESET  0x004
-#define PCIE_PHY_CMN_REG   

[PATCH] PCI: exynos: remove the deprecated phy codes

[Jaehoon Chung]

pci-exynos had updated to use the PHY framework.
(drivers/phy/samsung/phy-exynos-pcie.c)
Removed the depreccated codes relevant to phy in pci-exynos.c.
Instead, use the phy-exynos-pcie.c file.

Modified the binding documentation.

Signed-off-by: Jaehoon Chung 
---
 .../bindings/pci/samsung,exynos5440-pcie.txt   |  58 ++
 drivers/pci/dwc/pci-exynos.c   | 219 ++---
 2 files changed, 22 insertions(+), 255 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt 
b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 34a11bfbfb60..651d957d1051 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -6,9 +6,6 @@ and thus inherits all the common properties defined in 
designware-pcie.txt.
 Required properties:
 - compatible: "samsung,exynos5440-pcie"
 - reg: base addresses and lengths of the PCIe controller,
-   the PHY controller, additional register for the PHY controller.
-   (Registers for the PHY controller are DEPRECATED.
-Use the PHY framework.)
 - reg-names : First name should be set to "elbi".
And use the "config" instead of getting the configuration address space
from "ranges".
@@ -23,49 +20,8 @@ For other common properties, refer to
 
 Example:
 
-SoC-specific DT Entry:
+SoC-specific DT Entry (with using PHY framework):
 
-   pcie@29 {
-   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x29 0x1000
-   0x27 0x1000
-   0x271000 0x40>;
-   interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
-   clocks = < 28>, < 27>;
-   clock-names = "pcie", "pcie_bus";
-   #address-cells = <3>;
-   #size-cells = <2>;
-   device_type = "pci";
-   ranges = <0x0800 0 0x4000 0x4000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x40001000 0 0x0001   /* 
downstream I/O */
- 0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /* 
non-prefetchable memory */
-   #interrupt-cells = <1>;
-   interrupt-map-mask = <0 0 0 0>;
-   interrupt-map = <0 0 0 0  GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-   num-lanes = <4>;
-   };
-
-   pcie@2a {
-   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x2a 0x1000
-   0x272000 0x1000
-   0x271040 0x40>;
-   interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
-   clocks = < 29>, < 27>;
-   clock-names = "pcie", "pcie_bus";
-   #address-cells = <3>;
-   #size-cells = <2>;
-   device_type = "pci";
-   ranges = <0x0800 0 0x6000 0x6000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x60001000 0 0x0001   /* 
downstream I/O */
- 0x8200 0 0x60011000 0x60011000 0 0x1ffef000>; /* 
non-prefetchable memory */
-   #interrupt-cells = <1>;
-   interrupt-map-mask = <0 0 0 0>;
-   interrupt-map = <0 0 0 0  GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-   num-lanes = <4>;
-   };
-
-With using PHY framework:
pcie_phy0: pcie-phy@27 {
...
reg = <0x27 0x1000>, <0x271000 0x40>;
@@ -74,13 +30,21 @@ With using PHY framework:
};
 
pcie@29 {
-   ...
+   compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
reg = <0x29 0x1000>, <0x4000 0x1000>;
reg-names = "elbi", "config";
+   clocks = < 28>, < 27>;
+   clock-names = "pcie", "pcie_bus";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
phys = <_phy0>;
ranges = <0x8100 0 0  0x60001000 0 0x0001
  0x8200 0 0x60011000 0x60011000 0 0x1ffef000>;
-   ...
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+   num-lanes = <4>;
};
 
 Board-specific DT Entry:
diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index 5596fdedbb94..56f32aeebd0a 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -55,49 +55,8 @@
 #define PCIE_ELBI_SLV_ARMISC   0x120
 #define PCIE_ELBI_SLV_DBI_ENABLE   BIT(21)
 
-/* PCIe Purple registers */
-#define PCIE_PHY_GLOBAL_RESET  0x000
-#define PCIE_PHY_COMMON_RESET  0x004
-#define PCIE_PHY_CMN_REG   0x008
-#define