Re: [PATCH] SPI: SSP SPI Controller driver v3
On Mon, Jan 07, 2013 at 11:21:04AM +0100, Linus Walleij wrote: > On Mon, Jan 7, 2013 at 9:05 AM, channing wrote: > > > Frankly I'm currently not sure whether they share same IP.. per your > > reminds, I tried to find but get > > limited info about PXA SSP's IP, from the code, looks like they have part > > of registers the same. > > > > As far as I know, spi-pxa2xx.c is specific for SSP controller of > > PXA2XX/PXA3XX core, right? > > As pointed out by Mika it may very well be the same IP anyway. People > copy/paste > share and fork VHDL/Verilog/SystemC code just as much as they do with > kernel code. Yes, at least on Intel Lynxpoint it is the same IP with few additional features. I'm about to send patches to spi-pxa2xx which enable the Lynxpoint support shortly. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] SPI: SSP SPI Controller driver v3
On Mon, Jan 7, 2013 at 9:05 AM, channing wrote: > Frankly I'm currently not sure whether they share same IP.. per your reminds, > I tried to find but get > limited info about PXA SSP's IP, from the code, looks like they have part of > registers the same. > > As far as I know, spi-pxa2xx.c is specific for SSP controller of > PXA2XX/PXA3XX core, right? As pointed out by Mika it may very well be the same IP anyway. People copy/paste share and fork VHDL/Verilog/SystemC code just as much as they do with kernel code. > While Medfield > platform is embedded with ATOM core, the SSP driver we upload is validated on > SSP controller of ATOM. In my > view, they're specific for different AP & Platforms, if compare the 2 files, > there are still many difference > in how they works, if to choose a driver for Intel Medfild/Moorestown > platform, I believe spi-intel-mid-ssp.c > driver could be a more mature solution. >From the kernel community point of view the driver that is being maintained in-tree is the more mature solution. For your productization maybe the other driver is more mature. These are two different definitions of maturity. In the kernel we worry that we do not needlessly need to fix bugs in two places or leave a bug in one place while fixing it in another place, which is potentially the problem we run into here. There may be an initial time/testing cost for you to adopt to the PXA driver, but on the other hand the PXA developers will review your code and fix bugs for you also, so it's what we call a win-win situation if you can share the driver. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] SPI: SSP SPI Controller driver v3
On Mon, Jan 7, 2013 at 9:05 AM, channing chao...@intel.com wrote: Frankly I'm currently not sure whether they share same IP.. per your reminds, I tried to find but get limited info about PXA SSP's IP, from the code, looks like they have part of registers the same. As far as I know, spi-pxa2xx.c is specific for SSP controller of PXA2XX/PXA3XX core, right? As pointed out by Mika it may very well be the same IP anyway. People copy/paste share and fork VHDL/Verilog/SystemC code just as much as they do with kernel code. While Medfield platform is embedded with ATOM core, the SSP driver we upload is validated on SSP controller of ATOM. In my view, they're specific for different AP Platforms, if compare the 2 files, there are still many difference in how they works, if to choose a driver for Intel Medfild/Moorestown platform, I believe spi-intel-mid-ssp.c driver could be a more mature solution. From the kernel community point of view the driver that is being maintained in-tree is the more mature solution. For your productization maybe the other driver is more mature. These are two different definitions of maturity. In the kernel we worry that we do not needlessly need to fix bugs in two places or leave a bug in one place while fixing it in another place, which is potentially the problem we run into here. There may be an initial time/testing cost for you to adopt to the PXA driver, but on the other hand the PXA developers will review your code and fix bugs for you also, so it's what we call a win-win situation if you can share the driver. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] SPI: SSP SPI Controller driver v3
On Mon, Jan 07, 2013 at 11:21:04AM +0100, Linus Walleij wrote: On Mon, Jan 7, 2013 at 9:05 AM, channing chao...@intel.com wrote: Frankly I'm currently not sure whether they share same IP.. per your reminds, I tried to find but get limited info about PXA SSP's IP, from the code, looks like they have part of registers the same. As far as I know, spi-pxa2xx.c is specific for SSP controller of PXA2XX/PXA3XX core, right? As pointed out by Mika it may very well be the same IP anyway. People copy/paste share and fork VHDL/Verilog/SystemC code just as much as they do with kernel code. Yes, at least on Intel Lynxpoint it is the same IP with few additional features. I'm about to send patches to spi-pxa2xx which enable the Lynxpoint support shortly. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] SPI: SSP SPI Controller driver v3
On Mon, 2013-01-07 at 00:36 +0100, Linus Walleij wrote: > On Wed, Dec 19, 2012 at 10:56 AM, Mika Westerberg > wrote: > > On Tue, Dec 18, 2012 at 04:11:36PM +0800, chao bi wrote: > >> > >> This patch is to implement SSP SPI controller driver, which has been > >> applied and > >> validated on intel Moorestown & Medfield platform. The patch are > >> originated by > >> Ken Mills and Sylvain Centelles > >> , > >> migrating to lateset Linux mainline SPI framework by Channing > >> > >> and Chen Jun according to their integration & > >> validation > >> on Medfield platform. > > > > This is the same IP block as used in PXA, right? With few modifications > > here and there. Is there a reason not to use spi-pxa2xx.c? > > This needs to be investigated. Two drivers for the same or closely related > hardware block is never a good sign... > > Yours, > Linus Walleij Dear Linus ,Mika and Grant, Thanks for your remind. Frankly I'm currently not sure whether they share same IP.. per your reminds, I tried to find but get limited info about PXA SSP's IP, from the code, looks like they have part of registers the same. As far as I know, spi-pxa2xx.c is specific for SSP controller of PXA2XX/PXA3XX core, right? While Medfield platform is embedded with ATOM core, the SSP driver we upload is validated on SSP controller of ATOM. In my view, they're specific for different AP & Platforms, if compare the 2 files, there are still many difference in how they works, if to choose a driver for Intel Medfild/Moorestown platform, I believe spi-intel-mid-ssp.c driver could be a more mature solution. What do you think? please correct me if I'm mistaken. -chao -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] SPI: SSP SPI Controller driver v3
On Wed, Dec 19, 2012 at 10:56 AM, Mika Westerberg wrote: > On Tue, Dec 18, 2012 at 04:11:36PM +0800, chao bi wrote: >> >> This patch is to implement SSP SPI controller driver, which has been applied >> and >> validated on intel Moorestown & Medfield platform. The patch are originated >> by >> Ken Mills and Sylvain Centelles >> , >> migrating to lateset Linux mainline SPI framework by Channing >> >> and Chen Jun according to their integration & >> validation >> on Medfield platform. > > This is the same IP block as used in PXA, right? With few modifications > here and there. Is there a reason not to use spi-pxa2xx.c? This needs to be investigated. Two drivers for the same or closely related hardware block is never a good sign... Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] SPI: SSP SPI Controller driver v3
On Wed, Dec 19, 2012 at 10:56 AM, Mika Westerberg mika.westerb...@linux.intel.com wrote: On Tue, Dec 18, 2012 at 04:11:36PM +0800, chao bi wrote: This patch is to implement SSP SPI controller driver, which has been applied and validated on intel Moorestown Medfield platform. The patch are originated by Ken Mills ken.k.mi...@intel.com and Sylvain Centelles sylvain.centel...@intel.com, migrating to lateset Linux mainline SPI framework by Channing chao...@intel.com and Chen Jun jun.d.c...@intel.com according to their integration validation on Medfield platform. This is the same IP block as used in PXA, right? With few modifications here and there. Is there a reason not to use spi-pxa2xx.c? This needs to be investigated. Two drivers for the same or closely related hardware block is never a good sign... Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] SPI: SSP SPI Controller driver v3
On Mon, 2013-01-07 at 00:36 +0100, Linus Walleij wrote: On Wed, Dec 19, 2012 at 10:56 AM, Mika Westerberg mika.westerb...@linux.intel.com wrote: On Tue, Dec 18, 2012 at 04:11:36PM +0800, chao bi wrote: This patch is to implement SSP SPI controller driver, which has been applied and validated on intel Moorestown Medfield platform. The patch are originated by Ken Mills ken.k.mi...@intel.com and Sylvain Centelles sylvain.centel...@intel.com, migrating to lateset Linux mainline SPI framework by Channing chao...@intel.com and Chen Jun jun.d.c...@intel.com according to their integration validation on Medfield platform. This is the same IP block as used in PXA, right? With few modifications here and there. Is there a reason not to use spi-pxa2xx.c? This needs to be investigated. Two drivers for the same or closely related hardware block is never a good sign... Yours, Linus Walleij Dear Linus ,Mika and Grant, Thanks for your remind. Frankly I'm currently not sure whether they share same IP.. per your reminds, I tried to find but get limited info about PXA SSP's IP, from the code, looks like they have part of registers the same. As far as I know, spi-pxa2xx.c is specific for SSP controller of PXA2XX/PXA3XX core, right? While Medfield platform is embedded with ATOM core, the SSP driver we upload is validated on SSP controller of ATOM. In my view, they're specific for different AP Platforms, if compare the 2 files, there are still many difference in how they works, if to choose a driver for Intel Medfild/Moorestown platform, I believe spi-intel-mid-ssp.c driver could be a more mature solution. What do you think? please correct me if I'm mistaken. -chao -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] SPI: SSP SPI Controller driver v3
On Tue, Dec 18, 2012 at 04:11:36PM +0800, chao bi wrote: > > This patch is to implement SSP SPI controller driver, which has been applied > and > validated on intel Moorestown & Medfield platform. The patch are originated by > Ken Mills and Sylvain Centelles > , > migrating to lateset Linux mainline SPI framework by Channing > > and Chen Jun according to their integration & > validation > on Medfield platform. This is the same IP block as used in PXA, right? With few modifications here and there. Is there a reason not to use spi-pxa2xx.c? I have a set of patches for spi-pxa2xx.c that adds support for Lynxpoint LPSS, DMA engine and ACPI enumeration. I'm hoping to send those soon (once -rc1 is released) to the list. Maybe we can co-operate to get the Medfield support there as well? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] SPI: SSP SPI Controller driver v3
On Tue, Dec 18, 2012 at 04:11:36PM +0800, chao bi wrote: This patch is to implement SSP SPI controller driver, which has been applied and validated on intel Moorestown Medfield platform. The patch are originated by Ken Mills ken.k.mi...@intel.com and Sylvain Centelles sylvain.centel...@intel.com, migrating to lateset Linux mainline SPI framework by Channing chao...@intel.com and Chen Jun jun.d.c...@intel.com according to their integration validation on Medfield platform. This is the same IP block as used in PXA, right? With few modifications here and there. Is there a reason not to use spi-pxa2xx.c? I have a set of patches for spi-pxa2xx.c that adds support for Lynxpoint LPSS, DMA engine and ACPI enumeration. I'm hoping to send those soon (once -rc1 is released) to the list. Maybe we can co-operate to get the Medfield support there as well? -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] SPI: SSP SPI Controller driver v3
This patch is to implement SSP SPI controller driver, which has been applied and validated on intel Moorestown & Medfield platform. The patch are originated by Ken Mills and Sylvain Centelles , migrating to lateset Linux mainline SPI framework by Channing and Chen Jun according to their integration & validation on Medfield platform. Signed-off-by: Ken Mills Signed-off-by: Sylvain Centelles Signed-off-by: channing Signed-off-by: Chen Jun --- drivers/spi/Kconfig |9 + drivers/spi/Makefile |1 + drivers/spi/spi-intel-mid-ssp.c | 1614 + include/linux/spi/spi-intel-mid-ssp.h | 103 +++ 4 files changed, 1727 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/spi-intel-mid-ssp.c create mode 100644 include/linux/spi/spi-intel-mid-ssp.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2e188e1..6285f17 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -186,6 +186,15 @@ config SPI_IMX This enables using the Freescale i.MX SPI controllers in master mode. +config SPI_INTEL_MID_SSP + tristate "SSP SPI controller driver for Intel MID platforms" + depends on SPI_MASTER && INTEL_MID_DMAC + help + This is the unified SSP SPI master controller driver for + the Intel MID platforms, handling Moorestown & Medfield, + master clock mode. + It supports Bulverde SSP core. + config SPI_LM70_LLP tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)" depends on PARPORT && EXPERIMENTAL diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 64e970b..1738966 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_SPI_FSL_ESPI)+= spi-fsl-espi.o obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o obj-$(CONFIG_SPI_GPIO) += spi-gpio.o obj-$(CONFIG_SPI_IMX) += spi-imx.o +obj-$(CONFIG_SPI_INTEL_MID_SSP)+= spi-intel-mid-ssp.o obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o diff --git a/drivers/spi/spi-intel-mid-ssp.c b/drivers/spi/spi-intel-mid-ssp.c new file mode 100644 index 000..440c4a2 --- /dev/null +++ b/drivers/spi/spi-intel-mid-ssp.c @@ -0,0 +1,1614 @@ +/* + * spi-intel-mid-ssp.c + * This driver supports Bulverde SSP core used on Intel MID platforms + * It supports SSP of Moorestown & Medfield platforms and handles clock + * slave & master modes. + * + * Copyright (c) 2010, Intel Corporation. + * Ken Mills + * Sylvain Centelles + * Jun Chen + * Chao Bi + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +/* + * Note: + * + * Supports DMA and non-interrupt polled transfers. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_MRST_DMAC1_ID 0x0814 +#define PCI_MDFL_DMAC1_ID 0x0827 + +#define SSP_NOT_SYNC BIT(22) +#define MAX_SPI_TRANSFER_SIZE 8192 +#define MAX_BITBANGING_LOOP 1 +#define SPI_FIFO_SIZE 16 + +/* PM QoS define(usec) */ +#define MIN_EXIT_LATENCY 20 + +/* SPI DMA max transfer time */ +#define SSP_SPI_DMA_TIMEOUT 100 + +/* SSP assignement configuration from PCI config */ +#define SSP_CFG_GET_MODE(ssp_cfg) ((ssp_cfg) & 0x07) +#define SSP_CFG_GET_SPI_BUS_NB(ssp_cfg)(((ssp_cfg) >> 3) & 0x07) +#define SSP_CFG_IS_SPI_SLAVE(ssp_cfg) ((ssp_cfg) & BIT(6)) +#define SSP_CFG_SPI_MODE_ID1 +/* adid field offset is 6 inside the vendor specific capability */ +#define VNDR_CAPABILITY_ADID_OFFSET6 + +/* Driver's quirk flags + * This workarround bufferizes data in the audio fabric SDRAM from + * where the DMA transfers will operate. Should be enabled only for + * SPI slave mode. */ +#define QUIRKS_SRAM_ADDITIONAL_CPY 1 +/* If set the trailing bytes won't be handled by the DMA. + * Trailing byte feature not fully available. */ +#define QUIRKS_DMA_USE_NO_TRAIL2 +/* If set, the driver will use PM_QOS to reduce the latency + * introduced by the deeper C-states which may produce over/under + * run issues. Must be used in slave mode. In master mode, the + * latency is not critical, but setting
[PATCH] SPI: SSP SPI Controller driver v3
This patch is to implement SSP SPI controller driver, which has been applied and validated on intel Moorestown Medfield platform. The patch are originated by Ken Mills ken.k.mi...@intel.com and Sylvain Centelles sylvain.centel...@intel.com, migrating to lateset Linux mainline SPI framework by Channing chao...@intel.com and Chen Jun jun.d.c...@intel.com according to their integration validation on Medfield platform. Signed-off-by: Ken Mills ken.k.mi...@intel.com Signed-off-by: Sylvain Centelles sylvain.centel...@intel.com Signed-off-by: channing chao...@intel.com Signed-off-by: Chen Jun jun.d.c...@intel.com --- drivers/spi/Kconfig |9 + drivers/spi/Makefile |1 + drivers/spi/spi-intel-mid-ssp.c | 1614 + include/linux/spi/spi-intel-mid-ssp.h | 103 +++ 4 files changed, 1727 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/spi-intel-mid-ssp.c create mode 100644 include/linux/spi/spi-intel-mid-ssp.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2e188e1..6285f17 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -186,6 +186,15 @@ config SPI_IMX This enables using the Freescale i.MX SPI controllers in master mode. +config SPI_INTEL_MID_SSP + tristate SSP SPI controller driver for Intel MID platforms + depends on SPI_MASTER INTEL_MID_DMAC + help + This is the unified SSP SPI master controller driver for + the Intel MID platforms, handling Moorestown Medfield, + master clock mode. + It supports Bulverde SSP core. + config SPI_LM70_LLP tristate Parallel port adapter for LM70 eval board (DEVELOPMENT) depends on PARPORT EXPERIMENTAL diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 64e970b..1738966 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_SPI_FSL_ESPI)+= spi-fsl-espi.o obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o obj-$(CONFIG_SPI_GPIO) += spi-gpio.o obj-$(CONFIG_SPI_IMX) += spi-imx.o +obj-$(CONFIG_SPI_INTEL_MID_SSP)+= spi-intel-mid-ssp.o obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o diff --git a/drivers/spi/spi-intel-mid-ssp.c b/drivers/spi/spi-intel-mid-ssp.c new file mode 100644 index 000..440c4a2 --- /dev/null +++ b/drivers/spi/spi-intel-mid-ssp.c @@ -0,0 +1,1614 @@ +/* + * spi-intel-mid-ssp.c + * This driver supports Bulverde SSP core used on Intel MID platforms + * It supports SSP of Moorestown Medfield platforms and handles clock + * slave master modes. + * + * Copyright (c) 2010, Intel Corporation. + * Ken Mills ken.k.mi...@intel.com + * Sylvain Centelles sylvain.centel...@intel.com + * Jun Chen jun.d.c...@intel.com + * Chao Bi chao...@intel.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +/* + * Note: + * + * Supports DMA and non-interrupt polled transfers. + * + */ + +#include linux/delay.h +#include linux/interrupt.h +#include linux/highmem.h +#include linux/init.h +#include linux/interrupt.h +#include linux/dma-mapping.h +#include linux/intel_mid_dma.h +#include linux/pm_qos.h +#include linux/module.h +#include linux/spi/spi-intel-mid-ssp.h +#include linux/bitops.h + +#define PCI_MRST_DMAC1_ID 0x0814 +#define PCI_MDFL_DMAC1_ID 0x0827 + +#define SSP_NOT_SYNC BIT(22) +#define MAX_SPI_TRANSFER_SIZE 8192 +#define MAX_BITBANGING_LOOP 1 +#define SPI_FIFO_SIZE 16 + +/* PM QoS define(usec) */ +#define MIN_EXIT_LATENCY 20 + +/* SPI DMA max transfer time */ +#define SSP_SPI_DMA_TIMEOUT 100 + +/* SSP assignement configuration from PCI config */ +#define SSP_CFG_GET_MODE(ssp_cfg) ((ssp_cfg) 0x07) +#define SSP_CFG_GET_SPI_BUS_NB(ssp_cfg)(((ssp_cfg) 3) 0x07) +#define SSP_CFG_IS_SPI_SLAVE(ssp_cfg) ((ssp_cfg) BIT(6)) +#define SSP_CFG_SPI_MODE_ID1 +/* adid field offset is 6 inside the vendor specific capability */ +#define VNDR_CAPABILITY_ADID_OFFSET6 + +/* Driver's quirk flags + * This workarround bufferizes data in the audio fabric SDRAM from + * where the DMA transfers will operate. Should be enabled only for + * SPI slave mode. */ +#define
