Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-31 Thread Nishanth Menon 
On 15:56-20180828, Kishon Vijay Abraham I wrote:
[...]
>   cbass_mcu: interconnect@2838 {
>   compatible = "simple-bus";
>   #address-cells = <1>;
>   #size-cells = <1>;
> - ranges = <0x2838 0x2838 0x0388>, /* MCU 
> NAVSS*/
> -  <0x4020 0x4020 0x00900100>, /* First 
> peripheral window */
> -  <0x4204 0x4204 0x03ac2400>, /* WKUP */
> -  <0x4510 0x4510 0x00c24000>, /* MMRs, 
> remaining NAVSS */
> -  <0x4600 0x4600 0x0020>, /* CPSW */
> -  <0x4700 0x4700 0x00068400>; /* OSPI 
> space 1 */
> + ranges = <0x2838 0x00 0x2838 0x0388>, /* 
> MCU NAVSS*/
> +  <0x4020 0x00 0x4020 0x00900100>, /* 
> First peripheral window */
> +  <0x4204 0x00 0x4204 0x03ac2400>, /* 
> WKUP */
> +  <0x4510 0x00 0x4510 0x00c24000>, /* 
> MMRs, remaining NAVSS */
> +  <0x4600 0x00 0x4600 0x0020>, /* 
> CPSW */
> +  <0x4700 0x00 0x4700 0x00068400>; /* 
> OSPI space 1 */
>  


You might need #address-cells and #size-cells as 2 in MCU as
well.. Could you refer to response from Vignesh?
https://marc.info/?l=linux-arm-kernel&m=153572924921895&w=2

-- 
Regards,
Nishanth Menon

Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-31 Thread Vignesh R 
Kishon,

On 28-Aug-18 9:55 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I  [180828 10:31]:
>> AM65 has two PCIe controllers and each PCIe controller has '2' address
>> spaces one within the 4GB address space of the SoC and the other above
>> the 4GB address space of the SoC in addition to the register space. The
>> size of the address space above the 4GB SoC address space is 4GB. These
>> address ranges will be used by CPU/DMA to access the PCIe address space.
>> In order to represent the address space above the 4GB SoC address space
>> and to represent the size of this address space as 4GB, change
>> address-cells and size-cells of interconnect to 2.
> ...
>>  cbass_mcu: interconnect@2838 {
>>  compatible = "simple-bus";
>>  #address-cells = <1>;
>>  #size-cells = <1>;
> 

Looking at Table 2-2. MCU Domain Memory Map in TRM, OSPI has similar
need. There are two address ranges to access OSPI flash in memory mapped
mode:
MCU_FSS0_DAT_REG1 0x005000 0x005800 128 MB(32bit space)
MCU_FSS0_DAT_REG0 0x04 0x05 4 GB(64bit space with ECC)
MCU_FSS0_DAT_REG3 0x05 0x06 4 GB(64bit space w/o ECC)

Since, there are already OSPI flashes with size > 128MB, we would need
to use 4GB address space in kernel (which is above 32 bit space)

Therefore, could you also change cbass_mcu also to have
#address-cells = <2>?

Regards
Vignesh

Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-28 Thread Tony Lindgren 
* Kishon Vijay Abraham I  [180828 10:31]:
> AM65 has two PCIe controllers and each PCIe controller has '2' address
> spaces one within the 4GB address space of the SoC and the other above
> the 4GB address space of the SoC in addition to the register space. The
> size of the address space above the 4GB SoC address space is 4GB. These
> address ranges will be used by CPU/DMA to access the PCIe address space.
> In order to represent the address space above the 4GB SoC address space
> and to represent the size of this address space as 4GB, change
> address-cells and size-cells of interconnect to 2.
...
>   cbass_mcu: interconnect@2838 {
>   compatible = "simple-bus";
>   #address-cells = <1>;
>   #size-cells = <1>;

Yup great, the interconnect instances that don't need above 4GB
address space should stay this way.

Acked-by: Tony Lindgren

[PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-28 Thread Kishon Vijay Abraham I 
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC in addition to the register space. The
size of the address space above the 4GB SoC address space is 4GB. These
address ranges will be used by CPU/DMA to access the PCIe address space.
In order to represent the address space above the 4GB SoC address space
and to represent the size of this address space as 4GB, change
address-cells and size-cells of interconnect to 2.

Signed-off-by: Kishon Vijay Abraham I 
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 10 +++
 arch/arm64/boot/dts/ti/k3-am65.dtsi  | 38 
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi 
b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 569618b411f0..fbd6fab8dd5e 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -8,13 +8,13 @@
 &cbass_main {
gic500: interrupt-controller@180 {
compatible = "arm,gic-v3";
-   #address-cells = <1>;
-   #size-cells = <1>;
+   #address-cells = <2>;
+   #size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
-   reg = <0x0180 0x1>, /* GICD */
- <0x0188 0x9>; /* GICR */
+   reg = <0x00 0x0180 0x00 0x1>,   /* GICD */
+ <0x00 0x0188 0x00 0x9>;   /* GICR */
/*
 * vcpumntirq:
 * virtual CPU interface maintenance interrupt
@@ -23,7 +23,7 @@
 
gic_its: gic-its@1820 {
compatible = "arm,gic-v3-its";
-   reg = <0x0182 0x1>;
+   reg = <0x00 0x0182 0x00 0x1>;
msi-controller;
#msi-cells = <1>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi 
b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index 17a053552852..5d1eb877e128 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -54,31 +54,31 @@
 
cbass_main: interconnect@10 {
compatible = "simple-bus";
-   #address-cells = <1>;
-   #size-cells = <1>;
-   ranges = <0x0010 0x00 0x0010 0x0002>, /* ctrl mmr */
-<0x0060 0x00 0x0060 0x1100>, /* GPIO */
-<0x0090 0x00 0x0090 0x00012000>, /* serdes */
-<0x0100 0x00 0x0100 0x0af02400>, /* Most 
peripherals */
-<0x3080 0x00 0x3080 0x0bc0>, /* MAIN NAVSS 
*/
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges = <0x00 0x0010 0x00 0x0010 0x00 0x0002>, /* 
ctrl mmr */
+<0x00 0x0060 0x00 0x0060 0x00 0x1100>, /* 
GPIO */
+<0x00 0x0090 0x00 0x0090 0x00 0x00012000>, /* 
serdes */
+<0x00 0x0100 0x00 0x0100 0x00 0x0af02400>, /* 
Most peripherals */
+<0x00 0x3080 0x00 0x3080 0x00 0x0bc0>, /* 
MAIN NAVSS */
 /* MCUSS Range */
-<0x2838 0x00 0x2838 0x0388>,
-<0x4020 0x00 0x4020 0x00900100>,
-<0x4204 0x00 0x4204 0x03ac2400>,
-<0x4510 0x00 0x4510 0x00c24000>,
-<0x4600 0x00 0x4600 0x0020>,
-<0x4700 0x00 0x4700 0x00068400>;
+<0x00 0x2838 0x00 0x2838 0x00 0x0388>,
+<0x00 0x4020 0x00 0x4020 0x00 0x00900100>,
+<0x00 0x4204 0x00 0x4204 0x00 0x03ac2400>,
+<0x00 0x4510 0x00 0x4510 0x00 0x00c24000>,
+<0x00 0x4600 0x00 0x4600 0x00 0x0020>,
+<0x00 0x4700 0x00 0x4700 0x00 0x00068400>;
 
cbass_mcu: interconnect@2838 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
-   ranges = <0x2838 0x2838 0x0388>, /* MCU 
NAVSS*/
-<0x4020 0x4020 0x00900100>, /* First 
peripheral window */
-<0x4204 0x4204 0x03ac2400>, /* WKUP */
-<0x4510 0x4510 0x00c24000>, /* MMRs, 
remaining NAVSS */
-<0x4600 0x4600 0x0020>, /* CPSW */
-<0x4700 0x4700 0