From: Roman Kiryanov
A driver for the Goldfish Android emulator that occupies
address space to use it with the memory sharing device
on the QEMU side. The memory sharding device allocates
subranges and populate them with actual RAM.
This allows sharing host's memory with the guest.
Signed-off-by: Roman Kiryanov
---
drivers/misc/Kconfig | 9 +
drivers/misc/Makefile | 1 +
drivers/misc/goldfish_address_space.c | 742 ++
.../linux/goldfish/goldfish_address_space.h | 27 +
4 files changed, 779 insertions(+)
create mode 100644 drivers/misc/goldfish_address_space.c
create mode 100644 include/uapi/linux/goldfish/goldfish_address_space.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f417b06e11c5..66518bbe4217 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -521,6 +521,15 @@ config PVPANIC
a paravirtualized device provided by QEMU; it lets a virtual machine
(guest) communicate panic events to the host.
+config GOLDFISH_ADDRESS_SPACE
+ tristate "A Goldfish driver that talks to the memory sharing device in
QEMU"
+ depends on PCI
+ depends on GOLDFISH
+ help
+ A Goldfish driver that allocates address space ranges in the guest to
+ populate them later in the host. This allows sharing host's memory
+ with the guest.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e39ccbbc1b3a..11c9f9d7d3a1 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -59,3 +59,4 @@ obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
obj-$(CONFIG_OCXL) += ocxl/
obj-y += cardreader/
obj-$(CONFIG_PVPANIC) += pvpanic.o
+obj-$(CONFIG_GOLDFISH_ADDRESS_SPACE) += goldfish_address_space.o
diff --git a/drivers/misc/goldfish_address_space.c
b/drivers/misc/goldfish_address_space.c
new file mode 100644
index ..3605adcdaf2e
--- /dev/null
+++ b/drivers/misc/goldfish_address_space.c
@@ -0,0 +1,742 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+
+MODULE_DESCRIPTION("A driver for the Goldfish Android emulator that occupies "
+ "address space to use it with the memory sharing device "
+ "on the QEMU side. The memory sharding device allocates "
+ "subranges and populate them with actual RAM. "
+ "This allows sharing host's memory with the guest.");
+MODULE_AUTHOR("Roman Kiryanov ");
+MODULE_LICENSE("GPL v2");
+
+enum as_register_id {
+ AS_REGISTER_COMMAND = 0,
+ AS_REGISTER_STATUS = 4,
+ AS_REGISTER_GUEST_PAGE_SIZE = 8,
+ AS_REGISTER_BLOCK_SIZE_LOW = 12,
+ AS_REGISTER_BLOCK_SIZE_HIGH = 16,
+ AS_REGISTER_BLOCK_OFFSET_LOW = 20,
+ AS_REGISTER_BLOCK_OFFSET_HIGH = 24,
+};
+
+enum as_command_id {
+ AS_COMMAND_ALLOCATE_BLOCK = 1,
+ AS_COMMAND_DEALLOCATE_BLOCK = 2,
+};
+
+#define AS_PCI_VENDOR_ID 0x607D
+#define AS_PCI_DEVICE_ID 0xF153
+#define AS_MAGIC_U32 (AS_PCI_VENDOR_ID << 16 | AS_PCI_DEVICE_ID)
+#define AS_ALLOCATED_BLOCKS_INITIAL_CAPACITY 32
+
+enum as_pci_bar_id {
+ AS_PCI_CONTROL_BAR_ID = 0,
+ AS_PCI_AREA_BAR_ID = 1,
+};
+
+struct as_driver_state;
+
+struct as_device_state {
+ u32 magic;
+
+ struct miscdevice miscdevice;
+ struct pci_dev *dev;
+ struct as_driver_state *driver_state;
+
+ void __iomem*io_registers;
+
+ void*address_area; /* to claim the address space */
+
+ /* physical address to allocate from */
+ unsigned long address_area_phys_address;
+
+ struct mutexregisters_lock; /* protects registers */
+
+ wait_queue_head_t wake_queue; /* to wait for the hardware */
+
+ int hw_done;/* to say hw is done */
+};
+
+struct as_driver_state {
+ struct as_device_state *device_state;
+ struct pci_driver pci;
+};
+
+struct as_block {
+ u64 offset;
+ u64 size;
+};
+
+struct as_allocated_blocks {
+ struct as_device_state *state;
+
+ struct as_block *blocks; /* a dynamic array of allocated blocks */
+ int blocks_size;
+ int blocks_capacity;
+ struct mutex blocks_lock; /* protects operations with blocks */
+};
+
+static void __iomem *as_register_address(void __iomem *base,
+int offset)
+{
+ return ((char __iomem *)base) + offset;
+}
+
+static void as_write_register(void __iomem *registers,
+ int offset,
+ u32 value)
+{
+ writel(value,
