RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider

[Meng Yi]

> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
> 
> Since using clk_register_divider to setup the pixel clock, regmap is no longer
> used. Regmap did take care of DCU using different endianness. Check
> endianness using the device-tree property "big-endian" to determine the
> location of DIV_RATIO.
> 
> Cc: sta...@vger.kernel.org
> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
> clock divider")
> Reported-by: Meng Yi <meng...@nxp.com>
> Signed-off-by: Stefan Agner <ste...@agner.ch>
> ---
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-
> dcu/fsl_dcu_drm_drv.c
> index 7882387..8dd042e 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> @@ -330,6 +330,7 @@ static int fsl_dcu_drm_probe(struct platform_device
> *pdev)
>   const char *pix_clk_in_name;
>   const struct of_device_id *id;
>   int ret;
> + u8 div_ratio_shift = 0;
> 
>   fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
>   if (!fsl_dev)
> @@ -382,11 +383,15 @@ static int fsl_dcu_drm_probe(struct platform_device
> *pdev)
>   pix_clk_in = fsl_dev->clk;
>   }
> 
> + if (of_property_read_bool(dev->of_node, "big-endian"))
> + div_ratio_shift = 24;
> +
> +
>   pix_clk_in_name = __clk_get_name(pix_clk_in);
>   snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix",
> pix_clk_in_name);
>   fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
>   pix_clk_in_name, 0, base + DCU_DIV_RATIO,
> - 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
> + div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST,
> NULL);
>   if (IS_ERR(fsl_dev->pix_clk)) {
>   dev_err(dev, "failed to register pix clk\n");
>   ret = PTR_ERR(fsl_dev->pix_clk);
> --
> 2.9.0

Tested-by: Meng Yi <meng...@nxp.com>
On LS1021A-TWR board.

Meng

RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider

[Meng Yi]

> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
> 
> Since using clk_register_divider to setup the pixel clock, regmap is no longer
> used. Regmap did take care of DCU using different endianness. Check
> endianness using the device-tree property "big-endian" to determine the
> location of DIV_RATIO.
> 
> Cc: sta...@vger.kernel.org
> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
> clock divider")
> Reported-by: Meng Yi 
> Signed-off-by: Stefan Agner 
> ---
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-
> dcu/fsl_dcu_drm_drv.c
> index 7882387..8dd042e 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> @@ -330,6 +330,7 @@ static int fsl_dcu_drm_probe(struct platform_device
> *pdev)
>   const char *pix_clk_in_name;
>   const struct of_device_id *id;
>   int ret;
> + u8 div_ratio_shift = 0;
> 
>   fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
>   if (!fsl_dev)
> @@ -382,11 +383,15 @@ static int fsl_dcu_drm_probe(struct platform_device
> *pdev)
>   pix_clk_in = fsl_dev->clk;
>   }
> 
> + if (of_property_read_bool(dev->of_node, "big-endian"))
> + div_ratio_shift = 24;
> +
> +
>   pix_clk_in_name = __clk_get_name(pix_clk_in);
>   snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix",
> pix_clk_in_name);
>   fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
>   pix_clk_in_name, 0, base + DCU_DIV_RATIO,
> - 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
> + div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST,
> NULL);
>   if (IS_ERR(fsl_dev->pix_clk)) {
>   dev_err(dev, "failed to register pix clk\n");
>   ret = PTR_ERR(fsl_dev->pix_clk);
> --
> 2.9.0

Tested-by: Meng Yi 
On LS1021A-TWR board.

Meng

RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider

[Stefan Agner]

On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using 
>> clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no 
>> longer
>> used. Regmap did take care of DCU using different endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: sta...@vger.kernel.org
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divider")
>> Reported-by: Meng Yi <meng...@nxp.com>
>> Signed-off-by: Stefan Agner <ste...@agner.ch>



> 
> Tested-by: Meng Yi <meng...@nxp.com>
> On LS1021A-TWR board.

Thanks, applied!

--
Stefan

RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider

[Stefan Agner]

On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using 
>> clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no 
>> longer
>> used. Regmap did take care of DCU using different endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: sta...@vger.kernel.org
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divider")
>> Reported-by: Meng Yi 
>> Signed-off-by: Stefan Agner 



> 
> Tested-by: Meng Yi 
> On LS1021A-TWR board.

Thanks, applied!

--
Stefan

[PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider

[Stefan Agner]

Since using clk_register_divider to setup the pixel clock, regmap
is no longer used. Regmap did take care of DCU using different
endianness. Check endianness using the device-tree property
"big-endian" to determine the location of DIV_RATIO.

Cc: sta...@vger.kernel.org
Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel clock 
divider")
Reported-by: Meng Yi 
Signed-off-by: Stefan Agner 
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 7882387..8dd042e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -330,6 +330,7 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
const char *pix_clk_in_name;
const struct of_device_id *id;
int ret;
+   u8 div_ratio_shift = 0;
 
fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
if (!fsl_dev)
@@ -382,11 +383,15 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
pix_clk_in = fsl_dev->clk;
}
 
+   if (of_property_read_bool(dev->of_node, "big-endian"))
+   div_ratio_shift = 24;
+
+
pix_clk_in_name = __clk_get_name(pix_clk_in);
snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
pix_clk_in_name, 0, base + DCU_DIV_RATIO,
-   0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
+   div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
if (IS_ERR(fsl_dev->pix_clk)) {
dev_err(dev, "failed to register pix clk\n");
ret = PTR_ERR(fsl_dev->pix_clk);
-- 
2.9.0

[PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider

[Stefan Agner]

Since using clk_register_divider to setup the pixel clock, regmap
is no longer used. Regmap did take care of DCU using different
endianness. Check endianness using the device-tree property
"big-endian" to determine the location of DIV_RATIO.

Cc: sta...@vger.kernel.org
Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel clock 
divider")
Reported-by: Meng Yi 
Signed-off-by: Stefan Agner 
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 7882387..8dd042e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -330,6 +330,7 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
const char *pix_clk_in_name;
const struct of_device_id *id;
int ret;
+   u8 div_ratio_shift = 0;
 
fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
if (!fsl_dev)
@@ -382,11 +383,15 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
pix_clk_in = fsl_dev->clk;
}
 
+   if (of_property_read_bool(dev->of_node, "big-endian"))
+   div_ratio_shift = 24;
+
+
pix_clk_in_name = __clk_get_name(pix_clk_in);
snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
pix_clk_in_name, 0, base + DCU_DIV_RATIO,
-   0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
+   div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
if (IS_ERR(fsl_dev->pix_clk)) {
dev_err(dev, "failed to register pix clk\n");
ret = PTR_ERR(fsl_dev->pix_clk);
-- 
2.9.0