[PATCH] mmc:sdhci-pci: Add Support of O2Mirco/BayHubTech SD Host
>From b7e8322ea04a221c268d74fb405da24d865795ff Mon Sep 17 00:00:00 2001
From: "Peter.Guo"
Date: Thu, 10 Oct 2013 13:42:22 +0800
Subject: [PATCH] mmc:sdhci-pci: Add Support of O2Mirco/BayHubTech SD Host
Add O2Micro/BayHubTech SD Host DeviceId 8520 support and specified Init.
Apply SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 for SD Host Controller.
Apply SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC for SD Host Controller.
Signed-off-by: Peter.Guo
---
drivers/mmc/host/sdhci-pci.c | 220 ++
1 file changed, 220 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index d7d6bc8..6e56001 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -364,11 +364,167 @@ static const struct sdhci_pci_fixes sdhci_intel_byt_sd =
{
#define O2_SD_ADMA10xE2
#define O2_SD_ADMA20xE7
#define O2_SD_INF_MOD 0xF1
+#defineO2_SD_PLL_SETTING 0x304
+#defineO2_SD_CLK_SETTING 0x328
+#defineO2_SD_UHS1_CAP_SETTING 0x33C
+#defineO2_SD_VENDOR_SETTING 0x110
+#define PCI_DEVICE_ID_FUJIN2 0x8520
+
+static void o2_host_pci_init(struct sdhci_pci_chip *chip)
+{
+ u32 scratch_32;
+ int ret;
+ /* Improve write performance for SD3.0 */
+ ret = pci_read_config_dword(chip->pdev, 0x88, _32);
+ if (ret)
+ return;
+ scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
+ pci_write_config_dword(chip->pdev, 0x88, scratch_32);
+
+
+ /* Enable Link abnormal reset generating Reset */
+ ret = pci_read_config_dword(chip->pdev, 0x64, _32);
+ if (ret)
+ return;
+ scratch_32 &= ~((1 << 19) | (1 << 11));
+ scratch_32 |= (1 << 10);
+ pci_write_config_dword(chip->pdev, 0x64, scratch_32);
+
+ /* set card power over current protection */
+ ret = pci_read_config_dword(chip->pdev, 0xd4, _32);
+ if (ret)
+ return;
+ scratch_32 |= (1 << 4);
+ pci_write_config_dword(chip->pdev, 0xd4, scratch_32);
+
+ /* Set timeout CLK */
+ ret = pci_read_config_dword(chip->pdev,
+ O2_SD_CLK_SETTING, _32);
+ if (ret)
+ return;
+ scratch_32 &= ~(0xFF00);
+ scratch_32 |= 0x07E0C800;
+ pci_write_config_dword(chip->pdev,
+ O2_SD_CLK_SETTING, scratch_32);
+
+ /* adjust the output delay for SD mode */
+ pci_write_config_dword(chip->pdev, 0x350, 0x2492);
+
+ /* Set the output voltage setting of Aux 1.2v LDO */
+ ret = pci_read_config_dword(chip->pdev,
+ 0x68, _32);
+ if (ret)
+ return;
+ scratch_32 &= ~(3 << 12);
+ pci_write_config_dword(chip->pdev,
+ 0x68, scratch_32);
+
+ /* Set Max power supply capability of SD host */
+ ret = pci_read_config_dword(chip->pdev,
+ 0x334, _32);
+ if (ret)
+ return;
+ scratch_32 &= ~(0x01FE);
+ scratch_32 |= 0x00CC;
+ pci_write_config_dword(chip->pdev,
+ 0x334, scratch_32);
+ /* Set DLL Tuning Window */
+ ret = pci_read_config_dword(chip->pdev,
+ 0x300, _32);
+ if (ret)
+ return;
+ scratch_32 &= ~(0x00FF);
+ scratch_32 |= 0x0066;
+ pci_write_config_dword(chip->pdev,
+ 0x300, scratch_32);
+
+ /* Set UHS2 T_EIDLE */
+ ret = pci_read_config_dword(chip->pdev,
+ 0x35C, _32);
+ if (ret)
+ return;
+ scratch_32 &= ~(0x00FC);
+ scratch_32 |= 0x0084;
+ pci_write_config_dword(chip->pdev,
+ 0x35C, scratch_32);
+
+ /* Set UHS2 Termination */
+ ret = pci_read_config_dword(chip->pdev,
+ 0x3E0, _32);
+ if (ret)
+ return;
+ scratch_32 &= ~((1 << 21) | (1 << 30));
+ pci_write_config_dword(chip->pdev,
+ 0x3E0, scratch_32);
+ /* Set RTD3 function */
+ ret = pci_read_config_dword(chip->pdev,
+ 0xD8, _32);
+ if (ret)
+ return;
+ scratch_32 |= (1 << 9);
+ pci_write_config_dword(chip->pdev,
+ 0xD8, scratch_32);
+
+ ret = pci_read_config_dword(chip->pdev,
+ 0x3F0, _32);
+ if (ret)
+ return;
+ scratch_32 |= (1 << 31);
+ pci_write_config_dword(chip->pdev,
+ 0x3F0, scratch_32);
+
+ /* Set L1 Entra
[PATCH] mmc:sdhci-pci: Add Support of O2Mirco/BayHubTech SD Host
From b7e8322ea04a221c268d74fb405da24d865795ff Mon Sep 17 00:00:00 2001
From: Peter.Guo peter@bayhubtech.com
Date: Thu, 10 Oct 2013 13:42:22 +0800
Subject: [PATCH] mmc:sdhci-pci: Add Support of O2Mirco/BayHubTech SD Host
Add O2Micro/BayHubTech SD Host DeviceId 8520 support and specified Init.
Apply SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 for SD Host Controller.
Apply SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC for SD Host Controller.
Signed-off-by: Peter.Guo peter@bayhubtech.com
---
drivers/mmc/host/sdhci-pci.c | 220 ++
1 file changed, 220 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index d7d6bc8..6e56001 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -364,11 +364,167 @@ static const struct sdhci_pci_fixes sdhci_intel_byt_sd =
{
#define O2_SD_ADMA10xE2
#define O2_SD_ADMA20xE7
#define O2_SD_INF_MOD 0xF1
+#defineO2_SD_PLL_SETTING 0x304
+#defineO2_SD_CLK_SETTING 0x328
+#defineO2_SD_UHS1_CAP_SETTING 0x33C
+#defineO2_SD_VENDOR_SETTING 0x110
+#define PCI_DEVICE_ID_FUJIN2 0x8520
+
+static void o2_host_pci_init(struct sdhci_pci_chip *chip)
+{
+ u32 scratch_32;
+ int ret;
+ /* Improve write performance for SD3.0 */
+ ret = pci_read_config_dword(chip-pdev, 0x88, scratch_32);
+ if (ret)
+ return;
+ scratch_32 = ~((1 12) | (1 13) | (1 14));
+ pci_write_config_dword(chip-pdev, 0x88, scratch_32);
+
+
+ /* Enable Link abnormal reset generating Reset */
+ ret = pci_read_config_dword(chip-pdev, 0x64, scratch_32);
+ if (ret)
+ return;
+ scratch_32 = ~((1 19) | (1 11));
+ scratch_32 |= (1 10);
+ pci_write_config_dword(chip-pdev, 0x64, scratch_32);
+
+ /* set card power over current protection */
+ ret = pci_read_config_dword(chip-pdev, 0xd4, scratch_32);
+ if (ret)
+ return;
+ scratch_32 |= (1 4);
+ pci_write_config_dword(chip-pdev, 0xd4, scratch_32);
+
+ /* Set timeout CLK */
+ ret = pci_read_config_dword(chip-pdev,
+ O2_SD_CLK_SETTING, scratch_32);
+ if (ret)
+ return;
+ scratch_32 = ~(0xFF00);
+ scratch_32 |= 0x07E0C800;
+ pci_write_config_dword(chip-pdev,
+ O2_SD_CLK_SETTING, scratch_32);
+
+ /* adjust the output delay for SD mode */
+ pci_write_config_dword(chip-pdev, 0x350, 0x2492);
+
+ /* Set the output voltage setting of Aux 1.2v LDO */
+ ret = pci_read_config_dword(chip-pdev,
+ 0x68, scratch_32);
+ if (ret)
+ return;
+ scratch_32 = ~(3 12);
+ pci_write_config_dword(chip-pdev,
+ 0x68, scratch_32);
+
+ /* Set Max power supply capability of SD host */
+ ret = pci_read_config_dword(chip-pdev,
+ 0x334, scratch_32);
+ if (ret)
+ return;
+ scratch_32 = ~(0x01FE);
+ scratch_32 |= 0x00CC;
+ pci_write_config_dword(chip-pdev,
+ 0x334, scratch_32);
+ /* Set DLL Tuning Window */
+ ret = pci_read_config_dword(chip-pdev,
+ 0x300, scratch_32);
+ if (ret)
+ return;
+ scratch_32 = ~(0x00FF);
+ scratch_32 |= 0x0066;
+ pci_write_config_dword(chip-pdev,
+ 0x300, scratch_32);
+
+ /* Set UHS2 T_EIDLE */
+ ret = pci_read_config_dword(chip-pdev,
+ 0x35C, scratch_32);
+ if (ret)
+ return;
+ scratch_32 = ~(0x00FC);
+ scratch_32 |= 0x0084;
+ pci_write_config_dword(chip-pdev,
+ 0x35C, scratch_32);
+
+ /* Set UHS2 Termination */
+ ret = pci_read_config_dword(chip-pdev,
+ 0x3E0, scratch_32);
+ if (ret)
+ return;
+ scratch_32 = ~((1 21) | (1 30));
+ pci_write_config_dword(chip-pdev,
+ 0x3E0, scratch_32);
+ /* Set RTD3 function */
+ ret = pci_read_config_dword(chip-pdev,
+ 0xD8, scratch_32);
+ if (ret)
+ return;
+ scratch_32 |= (1 9);
+ pci_write_config_dword(chip-pdev,
+ 0xD8, scratch_32);
+
+ ret = pci_read_config_dword(chip-pdev,
+ 0x3F0, scratch_32);
+ if (ret)
+ return;
+ scratch_32 |= (1 31);
+ pci_write_config_dword(chip-pdev,
+ 0x3F0, scratch_32);
+
+ /* Set L1 Entrance Timer */
+ ret = pci_read_config_dword(chip-pdev,
+ O2_SD_CAPS, scratch_32);
+ if (ret
