Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Peter Zijlstra]

On Thu, Dec 08, 2016 at 04:14:17PM -0800, Andi Kleen wrote:
> From: Andi Kleen 
> 
> An earlier patch allowed enabling PT and LBR at the same
> time on Goldmont. However it also allowed enabling BTS and LBR
> at the same time, which is still not supported. Fix this by
> bypassing the check only for PT.
> 
> Marking for stable because this allows crashing kernels. Also
> should be merged for 4.9.
> 
> Fixes: ccbebba4c6bf ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the 
> core supports it")
> Cc: alexander.shish...@intel.com
> Cc: kan.li...@intel.com
> Cc: 
> v2: Paint bike shed differently.

Now, if only you'd also clarified the point I asked about. By
documenting these cases we not only get easier to read code, but can
also verify if the code does what is intended.

> Signed-off-by: Andi Kleen 
> ---

Changed that to the below, which is more explicit on the what is and is
not allowed. And fixed the definition of lbr_pt_coexist.

--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -365,7 +365,11 @@ int x86_add_exclusive(unsigned int what)
 {
int i;
 
-   if (x86_pmu.lbr_pt_coexist)
+   /*
+* When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
+* LBR and BTS are still mutually exclusive.
+*/
+   if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return 0;
 
if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {
@@ -388,7 +392,7 @@ int x86_add_exclusive(unsigned int what)
 
 void x86_del_exclusive(unsigned int what)
 {
-   if (x86_pmu.lbr_pt_coexist)
+   if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return;
 
atomic_dec(_pmu.lbr_exclusive[what]);
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -604,7 +604,7 @@ struct x86_pmu {
u64 lbr_sel_mask;  /* LBR_SELECT valid bits */
const int   *lbr_sel_map;  /* lbr_select mappings */
boollbr_double_abort;  /* duplicated lbr aborts */
-   boollbr_pt_coexist;/* LBR may coexist with PT */
+   boollbr_pt_coexist;/* (LBR|BTS) may coexist 
with PT */
 
/*
 * Intel PT/LBR/BTS are exclusive

Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Peter Zijlstra]

On Thu, Dec 08, 2016 at 04:14:17PM -0800, Andi Kleen wrote:
> From: Andi Kleen 
> 
> An earlier patch allowed enabling PT and LBR at the same
> time on Goldmont. However it also allowed enabling BTS and LBR
> at the same time, which is still not supported. Fix this by
> bypassing the check only for PT.
> 
> Marking for stable because this allows crashing kernels. Also
> should be merged for 4.9.
> 
> Fixes: ccbebba4c6bf ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the 
> core supports it")
> Cc: alexander.shish...@intel.com
> Cc: kan.li...@intel.com
> Cc: 
> v2: Paint bike shed differently.

Now, if only you'd also clarified the point I asked about. By
documenting these cases we not only get easier to read code, but can
also verify if the code does what is intended.

> Signed-off-by: Andi Kleen 
> ---

Changed that to the below, which is more explicit on the what is and is
not allowed. And fixed the definition of lbr_pt_coexist.

--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -365,7 +365,11 @@ int x86_add_exclusive(unsigned int what)
 {
int i;
 
-   if (x86_pmu.lbr_pt_coexist)
+   /*
+* When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
+* LBR and BTS are still mutually exclusive.
+*/
+   if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return 0;
 
if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {
@@ -388,7 +392,7 @@ int x86_add_exclusive(unsigned int what)
 
 void x86_del_exclusive(unsigned int what)
 {
-   if (x86_pmu.lbr_pt_coexist)
+   if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return;
 
atomic_dec(_pmu.lbr_exclusive[what]);
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -604,7 +604,7 @@ struct x86_pmu {
u64 lbr_sel_mask;  /* LBR_SELECT valid bits */
const int   *lbr_sel_map;  /* lbr_select mappings */
boollbr_double_abort;  /* duplicated lbr aborts */
-   boollbr_pt_coexist;/* LBR may coexist with PT */
+   boollbr_pt_coexist;/* (LBR|BTS) may coexist 
with PT */
 
/*
 * Intel PT/LBR/BTS are exclusive

[PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Andi Kleen]

From: Andi Kleen 

An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Marking for stable because this allows crashing kernels. Also
should be merged for 4.9.

Fixes: ccbebba4c6bf ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the 
core supports it")
Cc: alexander.shish...@intel.com
Cc: kan.li...@intel.com
Cc: 
v2: Paint bike shed differently.
Signed-off-by: Andi Kleen 
---
 arch/x86/events/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d0efb5cb1b00..baa1eed55e88 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
 {
int i;
 
-   if (x86_pmu.lbr_pt_coexist)
+   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return 0;
 
if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {
@@ -387,7 +387,7 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
-   if (x86_pmu.lbr_pt_coexist)
+   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return;
 
atomic_dec(_pmu.lbr_exclusive[what]);
-- 
2.9.3

[PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Andi Kleen]

From: Andi Kleen 

An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Marking for stable because this allows crashing kernels. Also
should be merged for 4.9.

Fixes: ccbebba4c6bf ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the 
core supports it")
Cc: alexander.shish...@intel.com
Cc: kan.li...@intel.com
Cc: 
v2: Paint bike shed differently.
Signed-off-by: Andi Kleen 
---
 arch/x86/events/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d0efb5cb1b00..baa1eed55e88 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
 {
int i;
 
-   if (x86_pmu.lbr_pt_coexist)
+   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return 0;
 
if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {
@@ -387,7 +387,7 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
-   if (x86_pmu.lbr_pt_coexist)
+   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return;
 
atomic_dec(_pmu.lbr_exclusive[what]);
-- 
2.9.3

Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Andi Kleen]

> > -   if (x86_pmu.lbr_pt_coexist)
> > +   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
> > return 0;
> 
> This would also allow PT & BTS at the same time, is that a supported
> configuration?

Yes it is on Goldmont.

-Andi

Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Andi Kleen]

> > -   if (x86_pmu.lbr_pt_coexist)
> > +   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
> > return 0;
> 
> This would also allow PT & BTS at the same time, is that a supported
> configuration?

Yes it is on Goldmont.

-Andi

Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Peter Zijlstra]

For some reason this patch never hit my inbox, it could be because
you're wrecked the Cc line and either infradead or my mta dropped the
email because of that.

On Fri, Dec 02, 2016 at 03:17:32PM -0800, Andi Kleen wrote:
> From: Andi Kleen 
> 
> The earlier patch ccbebba4 allowed enabling PT and LBR at the same

SHAs should be 12 chars.

> time on Goldmont. However it also allowed enabling BTS and LBR
> at the same time, which is still not supported. Fix this by
> bypassing the check only for PT.
> 
> Marking for stable because this allows crashing kernels. Also
> should be merged for 4.9.
> 
> Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core 
> supports it")

same

> Cc: alexander.shish...@intel.com
> Cc: kan.li...@intel.com
> Cc: sta...@vger.kernel.org # 4.6+
> Signed-off-by: Andi Kleen 
> ---
>  arch/x86/events/core.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index d0efb5cb1b00..baa1eed55e88 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
>  {
>   int i;
>  
> - if (x86_pmu.lbr_pt_coexist)
> + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
>   return 0;

This would also allow PT & BTS at the same time, is that a supported
configuration?

>  
>   if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {

Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Peter Zijlstra]

For some reason this patch never hit my inbox, it could be because
you're wrecked the Cc line and either infradead or my mta dropped the
email because of that.

On Fri, Dec 02, 2016 at 03:17:32PM -0800, Andi Kleen wrote:
> From: Andi Kleen 
> 
> The earlier patch ccbebba4 allowed enabling PT and LBR at the same

SHAs should be 12 chars.

> time on Goldmont. However it also allowed enabling BTS and LBR
> at the same time, which is still not supported. Fix this by
> bypassing the check only for PT.
> 
> Marking for stable because this allows crashing kernels. Also
> should be merged for 4.9.
> 
> Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core 
> supports it")

same

> Cc: alexander.shish...@intel.com
> Cc: kan.li...@intel.com
> Cc: sta...@vger.kernel.org # 4.6+
> Signed-off-by: Andi Kleen 
> ---
>  arch/x86/events/core.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index d0efb5cb1b00..baa1eed55e88 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
>  {
>   int i;
>  
> - if (x86_pmu.lbr_pt_coexist)
> + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
>   return 0;

This would also allow PT & BTS at the same time, is that a supported
configuration?

>  
>   if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {

[PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Andi Kleen]

From: Andi Kleen 

The earlier patch ccbebba4 allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Marking for stable because this allows crashing kernels. Also
should be merged for 4.9.

Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core 
supports it")
Cc: alexander.shish...@intel.com
Cc: kan.li...@intel.com
Cc: sta...@vger.kernel.org # 4.6+
Signed-off-by: Andi Kleen 
---
 arch/x86/events/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d0efb5cb1b00..baa1eed55e88 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
 {
int i;
 
-   if (x86_pmu.lbr_pt_coexist)
+   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return 0;
 
if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {
@@ -387,7 +387,7 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
-   if (x86_pmu.lbr_pt_coexist)
+   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return;
 
atomic_dec(_pmu.lbr_exclusive[what]);
-- 
2.9.3

[PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Andi Kleen]

From: Andi Kleen 

The earlier patch ccbebba4 allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Marking for stable because this allows crashing kernels. Also
should be merged for 4.9.

Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core 
supports it")
Cc: alexander.shish...@intel.com
Cc: kan.li...@intel.com
Cc: sta...@vger.kernel.org # 4.6+
Signed-off-by: Andi Kleen 
---
 arch/x86/events/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d0efb5cb1b00..baa1eed55e88 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
 {
int i;
 
-   if (x86_pmu.lbr_pt_coexist)
+   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return 0;
 
if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {
@@ -387,7 +387,7 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
-   if (x86_pmu.lbr_pt_coexist)
+   if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return;
 
atomic_dec(_pmu.lbr_exclusive[what]);
-- 
2.9.3