Re: [PATCH] powerpc/perf: Power8 PMU support
On Mon, Apr 15, 2013 at 09:31:26AM +0200, Benjamin Herrenschmidt wrote: > On Mon, 2013-04-15 at 14:17 +1000, Michael Ellerman wrote: > > This patch adds preliminary support for the power8 PMU to perf. > > Might be worthwhile to have a small blurb explaining roughly what you > mean by "preliminary" :-) True. There's no alternative handling, and no cache events. I need to work with the HW folks on both of those. Also missing is EBB support. I will hopefully post that in the next few days. cheers -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] powerpc/perf: Power8 PMU support
On Mon, 2013-04-15 at 14:17 +1000, Michael Ellerman wrote: > This patch adds preliminary support for the power8 PMU to perf. Might be worthwhile to have a small blurb explaining roughly what you mean by "preliminary" :-) Cheers, Ben. > Signed-off-by: Michael Ellerman > --- > arch/powerpc/perf/Makefile |3 +- > arch/powerpc/perf/power8-pmu.c | 454 > > 2 files changed, 456 insertions(+), 1 deletion(-) > create mode 100644 arch/powerpc/perf/power8-pmu.c > > diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile > index af3fac2..472db18 100644 > --- a/arch/powerpc/perf/Makefile > +++ b/arch/powerpc/perf/Makefile > @@ -4,7 +4,8 @@ obj-$(CONFIG_PERF_EVENTS) += callchain.o > > obj-$(CONFIG_PPC_PERF_CTRS) += core-book3s.o > obj64-$(CONFIG_PPC_PERF_CTRS)+= power4-pmu.o ppc970-pmu.o > power5-pmu.o \ > -power5+-pmu.o power6-pmu.o power7-pmu.o > +power5+-pmu.o power6-pmu.o power7-pmu.o \ > +power8-pmu.o > obj32-$(CONFIG_PPC_PERF_CTRS)+= mpc7450-pmu.o > > obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o > diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c > new file mode 100644 > index 000..106ae0b > --- /dev/null > +++ b/arch/powerpc/perf/power8-pmu.c > @@ -0,0 +1,454 @@ > +/* > + * Performance counter support for POWER8 processors. > + * > + * Copyright 2009 Paul Mackerras, IBM Corporation. > + * Copyright 2013 Michael Ellerman, IBM Corporation. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version > + * 2 of the License, or (at your option) any later version. > + */ > + > +#include > +#include > +#include > + > + > +/* > + * Some power8 event codes. > + */ > +#define PM_CYC 0x0001e > +#define PM_GCT_NOSLOT_CYC0x100f8 > +#define PM_CMPLU_STALL 0x4000a /* or 0x1e054 */ > +#define PM_INST_CMPL 0x2 > +#define PM_BRU_FIN 0x10068 > +#define PM_BR_MPRED_CMPL 0x400f6 > + > + > +/* > + * Raw event encoding for POWER8: > + * > + *60565248444036 >32 > + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - > - - - | > + * [ thresh_cmp ] [ > thresh_ctl ] > + * | > + * thresh start/stop OR FAB match -* > + * > + *2824201612 8 4 > 0 > + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - > - - - | > + * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ > pmcxsel] > + * || | | | > + * || | | *- mark > + * || *- L1/L2/L3 cache_sel | > + * || | > + * |*- sampling mode for marked events *- combine > + * | > + * *- thresh_sel > + * > + * Below uses IBM bit numbering. > + * > + * MMCR1[x:y] = unit(PMCxUNIT) > + * MMCR1[x] = combine (PMCxCOMB) > + * > + * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 > + * # PM_MRK_FAB_RSP_MATCH > + * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) > + * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 > + * # PM_MRK_FAB_RSP_MATCH_CYC > + * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) > + * else > + * MMCRA[48:55] = thresh_ctl (THRESH START/END) > + * > + * if thresh_sel: > + * MMCRA[45:47] = thresh_sel > + * > + * if thresh_cmp: > + * MMCRA[22:24] = thresh_cmp[0:2] > + * MMCRA[25:31] = thresh_cmp[3:9] > + * > + * if unit == 6 or unit == 7 > + * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) > + * else if unit == 8 or unit == 9: > + * if cache_sel[0] == 0: # L3 bank > + * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) > + * else if cache_sel[0] == 1: > + * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) > + * else if cache_sel[1]: # L1 event > + * MMCR1[16] = cache_sel[2] > + * MMCR1[17] = cache_sel[3] > + * > + * if mark: > + * MMCRA[63]= 1(SAMPLE_ENABLE) > + * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) > + * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) > + * > + */ > + > +#define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */ > +#define EVENT_THR_CMP_MASK 0x3ff > +#define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) > */ > +#define EVENT_THR_CTL_MASK 0xffull > +#define
Re: [PATCH] powerpc/perf: Power8 PMU support
On Mon, 2013-04-15 at 14:17 +1000, Michael Ellerman wrote: This patch adds preliminary support for the power8 PMU to perf. Might be worthwhile to have a small blurb explaining roughly what you mean by preliminary :-) Cheers, Ben. Signed-off-by: Michael Ellerman mich...@ellerman.id.au --- arch/powerpc/perf/Makefile |3 +- arch/powerpc/perf/power8-pmu.c | 454 2 files changed, 456 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/perf/power8-pmu.c diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile index af3fac2..472db18 100644 --- a/arch/powerpc/perf/Makefile +++ b/arch/powerpc/perf/Makefile @@ -4,7 +4,8 @@ obj-$(CONFIG_PERF_EVENTS) += callchain.o obj-$(CONFIG_PPC_PERF_CTRS) += core-book3s.o obj64-$(CONFIG_PPC_PERF_CTRS)+= power4-pmu.o ppc970-pmu.o power5-pmu.o \ -power5+-pmu.o power6-pmu.o power7-pmu.o +power5+-pmu.o power6-pmu.o power7-pmu.o \ +power8-pmu.o obj32-$(CONFIG_PPC_PERF_CTRS)+= mpc7450-pmu.o obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c new file mode 100644 index 000..106ae0b --- /dev/null +++ b/arch/powerpc/perf/power8-pmu.c @@ -0,0 +1,454 @@ +/* + * Performance counter support for POWER8 processors. + * + * Copyright 2009 Paul Mackerras, IBM Corporation. + * Copyright 2013 Michael Ellerman, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include linux/kernel.h +#include linux/perf_event.h +#include asm/firmware.h + + +/* + * Some power8 event codes. + */ +#define PM_CYC 0x0001e +#define PM_GCT_NOSLOT_CYC0x100f8 +#define PM_CMPLU_STALL 0x4000a /* or 0x1e054 */ +#define PM_INST_CMPL 0x2 +#define PM_BRU_FIN 0x10068 +#define PM_BR_MPRED_CMPL 0x400f6 + + +/* + * Raw event encoding for POWER8: + * + *60565248444036 32 + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | + * [ thresh_cmp ] [ thresh_ctl ] + * | + * thresh start/stop OR FAB match -* + * + *2824201612 8 4 0 + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | + * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ pmcxsel] + * || | | | + * || | | *- mark + * || *- L1/L2/L3 cache_sel | + * || | + * |*- sampling mode for marked events *- combine + * | + * *- thresh_sel + * + * Below uses IBM bit numbering. + * + * MMCR1[x:y] = unit(PMCxUNIT) + * MMCR1[x] = combine (PMCxCOMB) + * + * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 + * # PM_MRK_FAB_RSP_MATCH + * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) + * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 + * # PM_MRK_FAB_RSP_MATCH_CYC + * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) + * else + * MMCRA[48:55] = thresh_ctl (THRESH START/END) + * + * if thresh_sel: + * MMCRA[45:47] = thresh_sel + * + * if thresh_cmp: + * MMCRA[22:24] = thresh_cmp[0:2] + * MMCRA[25:31] = thresh_cmp[3:9] + * + * if unit == 6 or unit == 7 + * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) + * else if unit == 8 or unit == 9: + * if cache_sel[0] == 0: # L3 bank + * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) + * else if cache_sel[0] == 1: + * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) + * else if cache_sel[1]: # L1 event + * MMCR1[16] = cache_sel[2] + * MMCR1[17] = cache_sel[3] + * + * if mark: + * MMCRA[63]= 1(SAMPLE_ENABLE) + * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) + * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) + * + */ + +#define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */ +#define EVENT_THR_CMP_MASK 0x3ff +#define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) */ +#define EVENT_THR_CTL_MASK 0xffull +#define EVENT_THR_SEL_SHIFT 29 /* Threshold select value */ +#define
Re: [PATCH] powerpc/perf: Power8 PMU support
On Mon, Apr 15, 2013 at 09:31:26AM +0200, Benjamin Herrenschmidt wrote: On Mon, 2013-04-15 at 14:17 +1000, Michael Ellerman wrote: This patch adds preliminary support for the power8 PMU to perf. Might be worthwhile to have a small blurb explaining roughly what you mean by preliminary :-) True. There's no alternative handling, and no cache events. I need to work with the HW folks on both of those. Also missing is EBB support. I will hopefully post that in the next few days. cheers -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] powerpc/perf: Power8 PMU support
This patch adds preliminary support for the power8 PMU to perf. Signed-off-by: Michael Ellerman --- arch/powerpc/perf/Makefile |3 +- arch/powerpc/perf/power8-pmu.c | 454 2 files changed, 456 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/perf/power8-pmu.c diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile index af3fac2..472db18 100644 --- a/arch/powerpc/perf/Makefile +++ b/arch/powerpc/perf/Makefile @@ -4,7 +4,8 @@ obj-$(CONFIG_PERF_EVENTS) += callchain.o obj-$(CONFIG_PPC_PERF_CTRS)+= core-book3s.o obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \ - power5+-pmu.o power6-pmu.o power7-pmu.o + power5+-pmu.o power6-pmu.o power7-pmu.o \ + power8-pmu.o obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c new file mode 100644 index 000..106ae0b --- /dev/null +++ b/arch/powerpc/perf/power8-pmu.c @@ -0,0 +1,454 @@ +/* + * Performance counter support for POWER8 processors. + * + * Copyright 2009 Paul Mackerras, IBM Corporation. + * Copyright 2013 Michael Ellerman, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include + + +/* + * Some power8 event codes. + */ +#define PM_CYC 0x0001e +#define PM_GCT_NOSLOT_CYC 0x100f8 +#define PM_CMPLU_STALL 0x4000a /* or 0x1e054 */ +#define PM_INST_CMPL 0x2 +#define PM_BRU_FIN 0x10068 +#define PM_BR_MPRED_CMPL 0x400f6 + + +/* + * Raw event encoding for POWER8: + * + *60565248444036 32 + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | + * [ thresh_cmp ] [ thresh_ctl ] + * | + * thresh start/stop OR FAB match -* + * + *2824201612 8 4 0 + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | + * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [pmcxsel ] + * || | | | + * || | | *- mark + * || *- L1/L2/L3 cache_sel | + * || | + * |*- sampling mode for marked events *- combine + * | + * *- thresh_sel + * + * Below uses IBM bit numbering. + * + * MMCR1[x:y] = unit(PMCxUNIT) + * MMCR1[x] = combine (PMCxCOMB) + * + * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 + * # PM_MRK_FAB_RSP_MATCH + * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) + * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 + * # PM_MRK_FAB_RSP_MATCH_CYC + * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) + * else + * MMCRA[48:55] = thresh_ctl (THRESH START/END) + * + * if thresh_sel: + * MMCRA[45:47] = thresh_sel + * + * if thresh_cmp: + * MMCRA[22:24] = thresh_cmp[0:2] + * MMCRA[25:31] = thresh_cmp[3:9] + * + * if unit == 6 or unit == 7 + * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) + * else if unit == 8 or unit == 9: + * if cache_sel[0] == 0: # L3 bank + * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) + * else if cache_sel[0] == 1: + * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) + * else if cache_sel[1]: # L1 event + * MMCR1[16] = cache_sel[2] + * MMCR1[17] = cache_sel[3] + * + * if mark: + * MMCRA[63]= 1(SAMPLE_ENABLE) + * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) + * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) + * + */ + +#define EVENT_THR_CMP_SHIFT40 /* Threshold CMP value */ +#define EVENT_THR_CMP_MASK 0x3ff +#define EVENT_THR_CTL_SHIFT32 /* Threshold control value (start/stop) */ +#define EVENT_THR_CTL_MASK 0xffull +#define EVENT_THR_SEL_SHIFT29 /* Threshold select value */ +#define EVENT_THR_SEL_MASK 0x7 +#define EVENT_THRESH_SHIFT 29 /* All threshold bits */ +#define EVENT_THRESH_MASK 0x1full +#define EVENT_SAMPLE_SHIFT 24 /* Sampling mode & eligibility */ +#define EVENT_SAMPLE_MASK 0x1f +#define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */ +#define
[PATCH] powerpc/perf: Power8 PMU support
This patch adds preliminary support for the power8 PMU to perf. Signed-off-by: Michael Ellerman mich...@ellerman.id.au --- arch/powerpc/perf/Makefile |3 +- arch/powerpc/perf/power8-pmu.c | 454 2 files changed, 456 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/perf/power8-pmu.c diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile index af3fac2..472db18 100644 --- a/arch/powerpc/perf/Makefile +++ b/arch/powerpc/perf/Makefile @@ -4,7 +4,8 @@ obj-$(CONFIG_PERF_EVENTS) += callchain.o obj-$(CONFIG_PPC_PERF_CTRS)+= core-book3s.o obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \ - power5+-pmu.o power6-pmu.o power7-pmu.o + power5+-pmu.o power6-pmu.o power7-pmu.o \ + power8-pmu.o obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c new file mode 100644 index 000..106ae0b --- /dev/null +++ b/arch/powerpc/perf/power8-pmu.c @@ -0,0 +1,454 @@ +/* + * Performance counter support for POWER8 processors. + * + * Copyright 2009 Paul Mackerras, IBM Corporation. + * Copyright 2013 Michael Ellerman, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include linux/kernel.h +#include linux/perf_event.h +#include asm/firmware.h + + +/* + * Some power8 event codes. + */ +#define PM_CYC 0x0001e +#define PM_GCT_NOSLOT_CYC 0x100f8 +#define PM_CMPLU_STALL 0x4000a /* or 0x1e054 */ +#define PM_INST_CMPL 0x2 +#define PM_BRU_FIN 0x10068 +#define PM_BR_MPRED_CMPL 0x400f6 + + +/* + * Raw event encoding for POWER8: + * + *60565248444036 32 + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | + * [ thresh_cmp ] [ thresh_ctl ] + * | + * thresh start/stop OR FAB match -* + * + *2824201612 8 4 0 + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | + * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [pmcxsel ] + * || | | | + * || | | *- mark + * || *- L1/L2/L3 cache_sel | + * || | + * |*- sampling mode for marked events *- combine + * | + * *- thresh_sel + * + * Below uses IBM bit numbering. + * + * MMCR1[x:y] = unit(PMCxUNIT) + * MMCR1[x] = combine (PMCxCOMB) + * + * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 + * # PM_MRK_FAB_RSP_MATCH + * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) + * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 + * # PM_MRK_FAB_RSP_MATCH_CYC + * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) + * else + * MMCRA[48:55] = thresh_ctl (THRESH START/END) + * + * if thresh_sel: + * MMCRA[45:47] = thresh_sel + * + * if thresh_cmp: + * MMCRA[22:24] = thresh_cmp[0:2] + * MMCRA[25:31] = thresh_cmp[3:9] + * + * if unit == 6 or unit == 7 + * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) + * else if unit == 8 or unit == 9: + * if cache_sel[0] == 0: # L3 bank + * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) + * else if cache_sel[0] == 1: + * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) + * else if cache_sel[1]: # L1 event + * MMCR1[16] = cache_sel[2] + * MMCR1[17] = cache_sel[3] + * + * if mark: + * MMCRA[63]= 1(SAMPLE_ENABLE) + * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) + * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) + * + */ + +#define EVENT_THR_CMP_SHIFT40 /* Threshold CMP value */ +#define EVENT_THR_CMP_MASK 0x3ff +#define EVENT_THR_CTL_SHIFT32 /* Threshold control value (start/stop) */ +#define EVENT_THR_CTL_MASK 0xffull +#define EVENT_THR_SEL_SHIFT29 /* Threshold select value */ +#define EVENT_THR_SEL_MASK 0x7 +#define EVENT_THRESH_SHIFT 29 /* All threshold bits */ +#define EVENT_THRESH_MASK 0x1full +#define EVENT_SAMPLE_SHIFT 24 /* Sampling mode eligibility */ +#define EVENT_SAMPLE_MASK 0x1f +#define
