Re: [PATCH] ppc64: Add IDE-pmac support for new "Shasta" chipset
On Thu, 2005-03-10 at 23:17 -0800, Andrew Morton wrote: > Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote: > > > > The iMac G5 and new single CPU PowerMac G5 come with a new revision of > > the K2 ASIC called Shasta. The PATA cell in there now does 133Mhz. This > > patch adds support for it. It also adds some power management bits to > > the old 100MHz cell that was in Intrepid based ppc32 machines. > > Compile fix: > > --- > 25/drivers/ide/ppc/pmac.c~ppc64-add-ide-pmac-support-for-new-shasta-chipset-fix >2005-03-11 07:12:01.0 -0700 > +++ 25-akpm/drivers/ide/ppc/pmac.c2005-03-11 07:12:20.0 -0700 > @@ -1301,7 +1301,7 @@ pmac_ide_setup_device(pmac_ide_hwif_t *p >*/ > if (device_is_compatible(np, "K2-UATA") || > device_is_compatible(np, "shasta-ata")) > - pmid->cable_80 = 1; > + pmif->cable_80 = 1; > > /* On Kauai-type controllers, we make sure the FCR is correct */ > if (pmif->kauai_fcr) > _ > > (Wonders how well tested this was). It was tested, sorry about the mistake, I fixed that compile error and forgot to run "quilt ref" :) My bad ... I'll double check that the other patches are indeed the right versions tomorrow... Ben. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ppc64: Add IDE-pmac support for new Shasta chipset
On Thu, 2005-03-10 at 23:17 -0800, Andrew Morton wrote: Benjamin Herrenschmidt [EMAIL PROTECTED] wrote: The iMac G5 and new single CPU PowerMac G5 come with a new revision of the K2 ASIC called Shasta. The PATA cell in there now does 133Mhz. This patch adds support for it. It also adds some power management bits to the old 100MHz cell that was in Intrepid based ppc32 machines. Compile fix: --- 25/drivers/ide/ppc/pmac.c~ppc64-add-ide-pmac-support-for-new-shasta-chipset-fix 2005-03-11 07:12:01.0 -0700 +++ 25-akpm/drivers/ide/ppc/pmac.c2005-03-11 07:12:20.0 -0700 @@ -1301,7 +1301,7 @@ pmac_ide_setup_device(pmac_ide_hwif_t *p */ if (device_is_compatible(np, K2-UATA) || device_is_compatible(np, shasta-ata)) - pmid-cable_80 = 1; + pmif-cable_80 = 1; /* On Kauai-type controllers, we make sure the FCR is correct */ if (pmif-kauai_fcr) _ (Wonders how well tested this was). It was tested, sorry about the mistake, I fixed that compile error and forgot to run quilt ref :) My bad ... I'll double check that the other patches are indeed the right versions tomorrow... Ben. - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ppc64: Add IDE-pmac support for new "Shasta" chipset
Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote: > > The iMac G5 and new single CPU PowerMac G5 come with a new revision of > the K2 ASIC called Shasta. The PATA cell in there now does 133Mhz. This > patch adds support for it. It also adds some power management bits to > the old 100MHz cell that was in Intrepid based ppc32 machines. Compile fix: --- 25/drivers/ide/ppc/pmac.c~ppc64-add-ide-pmac-support-for-new-shasta-chipset-fix 2005-03-11 07:12:01.0 -0700 +++ 25-akpm/drivers/ide/ppc/pmac.c 2005-03-11 07:12:20.0 -0700 @@ -1301,7 +1301,7 @@ pmac_ide_setup_device(pmac_ide_hwif_t *p */ if (device_is_compatible(np, "K2-UATA") || device_is_compatible(np, "shasta-ata")) - pmid->cable_80 = 1; + pmif->cable_80 = 1; /* On Kauai-type controllers, we make sure the FCR is correct */ if (pmif->kauai_fcr) _ (Wonders how well tested this was). - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ppc64: Add IDE-pmac support for new "Shasta" chipset
Hi !
The iMac G5 and new single CPU PowerMac G5 come with a new revision of
the K2 ASIC called Shasta. The PATA cell in there now does 133Mhz. This
patch adds support for it. It also adds some power management bits to
the old 100MHz cell that was in Intrepid based ppc32 machines.
The original iMac G5 bits are from J. Mayer <[EMAIL PROTECTED]>
Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Index: linux-work/drivers/ide/ppc/pmac.c
===
--- linux-work.orig/drivers/ide/ppc/pmac.c 2005-01-31 14:18:21.0
+1100
+++ linux-work/drivers/ide/ppc/pmac.c 2005-03-10 14:58:19.0 +1100
@@ -68,6 +68,7 @@
struct device_node* node;
struct macio_dev*mdev;
u32 timings[4];
+ volatile u32 __iomem * *kauai_fcr;
#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
/* Those fields are duplicating what is in hwif. We currently
* can't use the hwif ones because of some assumptions that are
@@ -89,7 +90,8 @@
controller_kl_ata3, /* KeyLargo ATA-3 */
controller_kl_ata4, /* KeyLargo ATA-4 */
controller_un_ata6, /* UniNorth2 ATA-6 */
- controller_k2_ata6 /* K2 ATA-6 */
+ controller_k2_ata6, /* K2 ATA-6 */
+ controller_sh_ata6, /* Shasta ATA-6 */
};
static const char* model_name[] = {
@@ -99,6 +101,7 @@
"KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
"UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
"K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
+ "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
};
/*
@@ -122,6 +125,15 @@
#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
+/* 133Mhz cell, found in shasta.
+ * See comments about 100 Mhz Uninorth 2...
+ * Note that PIO_MASK and MDMA_MASK seem to overlap
+ */
+#define TR_133_PIOREG_PIO_MASK 0xff000fff
+#define TR_133_PIOREG_MDMA_MASK0x00fff800
+#define TR_133_UDMAREG_UDMA_MASK 0x0003
+#define TR_133_UDMAREG_UDMA_EN 0x0001
+
/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
* this one yet, it appears as a pci device (106b/0033) on uninorth
* internal PCI bus and it's clock is controlled like gem or fw. It
@@ -209,6 +221,13 @@
#define IDE_INTR_DMA 0x8000
#define IDE_INTR_DEVICE0x4000
+/*
+ * FCR Register on Kauai. Not sure what bit 0x4 is ...
+ */
+#define KAUAI_FCR_UATA_MAGIC 0x0004
+#define KAUAI_FCR_UATA_RESET_N 0x0002
+#define KAUAI_FCR_UATA_ENABLE 0x0001
+
#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
/* Rounded Multiword DMA timings
@@ -322,6 +341,48 @@
{ 0 , 0 },
};
+static struct kauai_timing shasta_pio_timings[] __pmacdata =
+{
+ { 930 , 0x08000fff },
+ { 600 , 0x0A000c97 },
+ { 383 , 0x07000712 },
+ { 360 , 0x040003cd },
+ { 330 , 0x040003cd },
+ { 300 , 0x040003cd },
+ { 270 , 0x040003cd },
+ { 240 , 0x040003cd },
+ { 239 , 0x040003cd },
+ { 180 , 0x0400028b },
+ { 120 , 0x0400010a }
+};
+
+static struct kauai_timing shasta_mdma_timings[] __pmacdata =
+{
+ { 1260 , 0x00fff000 },
+ { 480 , 0x00820800 },
+ { 360 , 0x00820800 },
+ { 270 , 0x00820800 },
+ { 240 , 0x00820800 },
+ { 210 , 0x00820800 },
+ { 180 , 0x00820800 },
+ { 150 , 0x0028b000 },
+ { 120 , 0x001ca000 },
+ { 0 , 0 },
+};
+
+static struct kauai_timing shasta_udma133_timings[] __pmacdata =
+{
+ { 120 , 0x00035901, },
+ { 90, 0x000348b1, },
+ { 60, 0x00033881, },
+ { 45, 0x00033861, },
+ { 30, 0x00033841, },
+ { 20, 0x00033031, },
+ { 15, 0x00033021, },
+ { 0 , 0 },
+};
+
+
static inline u32
kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
{
@@ -547,7 +608,9 @@
if (pmif == NULL)
return;
- if (pmif->kind == controller_un_ata6 || pmif->kind ==
controller_k2_ata6)
+ if (pmif->kind == controller_sh_ata6 ||
+ pmif->kind == controller_un_ata6 ||
+ pmif->kind == controller_k2_ata6)
pmac_ide_kauai_selectproc(drive);
else
pmac_ide_selectproc(drive);
@@ -665,6 +728,14 @@
pio = ide_get_best_pio_mode(drive, pio, 4, );
switch (pmif->kind) {
+ case controller_sh_ata6: {
+ /* 133Mhz cell */
+ u32 tr = kauai_lookup_timing(shasta_pio_timings, d.cycle_time);
+ if (tr == 0)
+ return;
+ *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
+ break;
+ }
case controller_un_ata6:
case
[PATCH] ppc64: Add IDE-pmac support for new Shasta chipset
Hi !
The iMac G5 and new single CPU PowerMac G5 come with a new revision of
the K2 ASIC called Shasta. The PATA cell in there now does 133Mhz. This
patch adds support for it. It also adds some power management bits to
the old 100MHz cell that was in Intrepid based ppc32 machines.
The original iMac G5 bits are from J. Mayer [EMAIL PROTECTED]
Signed-off-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
Index: linux-work/drivers/ide/ppc/pmac.c
===
--- linux-work.orig/drivers/ide/ppc/pmac.c 2005-01-31 14:18:21.0
+1100
+++ linux-work/drivers/ide/ppc/pmac.c 2005-03-10 14:58:19.0 +1100
@@ -68,6 +68,7 @@
struct device_node* node;
struct macio_dev*mdev;
u32 timings[4];
+ volatile u32 __iomem * *kauai_fcr;
#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
/* Those fields are duplicating what is in hwif. We currently
* can't use the hwif ones because of some assumptions that are
@@ -89,7 +90,8 @@
controller_kl_ata3, /* KeyLargo ATA-3 */
controller_kl_ata4, /* KeyLargo ATA-4 */
controller_un_ata6, /* UniNorth2 ATA-6 */
- controller_k2_ata6 /* K2 ATA-6 */
+ controller_k2_ata6, /* K2 ATA-6 */
+ controller_sh_ata6, /* Shasta ATA-6 */
};
static const char* model_name[] = {
@@ -99,6 +101,7 @@
KeyLargo ATA-4, /* KeyLargo ATA-4 (UDMA/66) */
UniNorth ATA-6, /* UniNorth2 ATA-6 (UDMA/100) */
K2 ATA-6, /* K2 ATA-6 (UDMA/100) */
+ Shasta ATA-6, /* Shasta ATA-6 (UDMA/133) */
};
/*
@@ -122,6 +125,15 @@
#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
+/* 133Mhz cell, found in shasta.
+ * See comments about 100 Mhz Uninorth 2...
+ * Note that PIO_MASK and MDMA_MASK seem to overlap
+ */
+#define TR_133_PIOREG_PIO_MASK 0xff000fff
+#define TR_133_PIOREG_MDMA_MASK0x00fff800
+#define TR_133_UDMAREG_UDMA_MASK 0x0003
+#define TR_133_UDMAREG_UDMA_EN 0x0001
+
/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
* this one yet, it appears as a pci device (106b/0033) on uninorth
* internal PCI bus and it's clock is controlled like gem or fw. It
@@ -209,6 +221,13 @@
#define IDE_INTR_DMA 0x8000
#define IDE_INTR_DEVICE0x4000
+/*
+ * FCR Register on Kauai. Not sure what bit 0x4 is ...
+ */
+#define KAUAI_FCR_UATA_MAGIC 0x0004
+#define KAUAI_FCR_UATA_RESET_N 0x0002
+#define KAUAI_FCR_UATA_ENABLE 0x0001
+
#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
/* Rounded Multiword DMA timings
@@ -322,6 +341,48 @@
{ 0 , 0 },
};
+static struct kauai_timing shasta_pio_timings[] __pmacdata =
+{
+ { 930 , 0x08000fff },
+ { 600 , 0x0A000c97 },
+ { 383 , 0x07000712 },
+ { 360 , 0x040003cd },
+ { 330 , 0x040003cd },
+ { 300 , 0x040003cd },
+ { 270 , 0x040003cd },
+ { 240 , 0x040003cd },
+ { 239 , 0x040003cd },
+ { 180 , 0x0400028b },
+ { 120 , 0x0400010a }
+};
+
+static struct kauai_timing shasta_mdma_timings[] __pmacdata =
+{
+ { 1260 , 0x00fff000 },
+ { 480 , 0x00820800 },
+ { 360 , 0x00820800 },
+ { 270 , 0x00820800 },
+ { 240 , 0x00820800 },
+ { 210 , 0x00820800 },
+ { 180 , 0x00820800 },
+ { 150 , 0x0028b000 },
+ { 120 , 0x001ca000 },
+ { 0 , 0 },
+};
+
+static struct kauai_timing shasta_udma133_timings[] __pmacdata =
+{
+ { 120 , 0x00035901, },
+ { 90, 0x000348b1, },
+ { 60, 0x00033881, },
+ { 45, 0x00033861, },
+ { 30, 0x00033841, },
+ { 20, 0x00033031, },
+ { 15, 0x00033021, },
+ { 0 , 0 },
+};
+
+
static inline u32
kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
{
@@ -547,7 +608,9 @@
if (pmif == NULL)
return;
- if (pmif-kind == controller_un_ata6 || pmif-kind ==
controller_k2_ata6)
+ if (pmif-kind == controller_sh_ata6 ||
+ pmif-kind == controller_un_ata6 ||
+ pmif-kind == controller_k2_ata6)
pmac_ide_kauai_selectproc(drive);
else
pmac_ide_selectproc(drive);
@@ -665,6 +728,14 @@
pio = ide_get_best_pio_mode(drive, pio, 4, d);
switch (pmif-kind) {
+ case controller_sh_ata6: {
+ /* 133Mhz cell */
+ u32 tr = kauai_lookup_timing(shasta_pio_timings, d.cycle_time);
+ if (tr == 0)
+ return;
+ *timings = ((*timings) ~TR_133_PIOREG_PIO_MASK) | tr;
+ break;
+ }
case controller_un_ata6:
case controller_k2_ata6: {
Re: [PATCH] ppc64: Add IDE-pmac support for new Shasta chipset
Benjamin Herrenschmidt [EMAIL PROTECTED] wrote: The iMac G5 and new single CPU PowerMac G5 come with a new revision of the K2 ASIC called Shasta. The PATA cell in there now does 133Mhz. This patch adds support for it. It also adds some power management bits to the old 100MHz cell that was in Intrepid based ppc32 machines. Compile fix: --- 25/drivers/ide/ppc/pmac.c~ppc64-add-ide-pmac-support-for-new-shasta-chipset-fix 2005-03-11 07:12:01.0 -0700 +++ 25-akpm/drivers/ide/ppc/pmac.c 2005-03-11 07:12:20.0 -0700 @@ -1301,7 +1301,7 @@ pmac_ide_setup_device(pmac_ide_hwif_t *p */ if (device_is_compatible(np, K2-UATA) || device_is_compatible(np, shasta-ata)) - pmid-cable_80 = 1; + pmif-cable_80 = 1; /* On Kauai-type controllers, we make sure the FCR is correct */ if (pmif-kauai_fcr) _ (Wonders how well tested this was). - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
