Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-20 Thread Oleg Nesterov
On 04/09, Jacob Shin wrote:
>
> The following patchset adds address masks to existing perf hardware
> breakpoint mechanism to allow trapping on an address range (currently
> only single address) on supported architectures.
>
> perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
> beyond) is provided, and perf tool has been extended to do:
>
>   $ perf stat -e mem:0x1000:w:0xf a.out
>   ^^^
>   "don't care" bit mask
>
>   which will count writes to [0x1000 ~ 0x1010)

Please help me understand...

Assuming that cpu_has_bpext == T, suppose that

bp_addr = 0x1001;
bp_bp_addr_mask = 0xf;

Is it the same as 0x1000/0xf above?

IOW, what exactly this mask means? I guess, mem:ADDR:w:MASK
should trigger the trap if CPU writes to the addr and

(addr & ~MASK) == (ADDR & ~MASK)

correct?

And does attr.bp_len "contribute" to the mask?

I mean, if bp_len == X86_BREAKPOINT_LEN_8, does this mean that
bp_bp_addr_mask and (bp_bp_addr_mask | 7) have the same effect?

Oleg.

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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-20 Thread Oleg Nesterov
On 04/09, Jacob Shin wrote:

 The following patchset adds address masks to existing perf hardware
 breakpoint mechanism to allow trapping on an address range (currently
 only single address) on supported architectures.

 perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
 beyond) is provided, and perf tool has been extended to do:

   $ perf stat -e mem:0x1000:w:0xf a.out
   ^^^
   don't care bit mask

   which will count writes to [0x1000 ~ 0x1010)

Please help me understand...

Assuming that cpu_has_bpext == T, suppose that

bp_addr = 0x1001;
bp_bp_addr_mask = 0xf;

Is it the same as 0x1000/0xf above?

IOW, what exactly this mask means? I guess, mem:ADDR:w:MASK
should trigger the trap if CPU writes to the addr and

(addr  ~MASK) == (ADDR  ~MASK)

correct?

And does attr.bp_len contribute to the mask?

I mean, if bp_len == X86_BREAKPOINT_LEN_8, does this mean that
bp_bp_addr_mask and (bp_bp_addr_mask | 7) have the same effect?

Oleg.

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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-18 Thread Oleg Nesterov
Hi Jacob,

On 04/18, Jacob Shin wrote:
>
> Hi Frederic, Oleg. Could one of you take a look over this patchset
> when you get the chance? Thank you in advance for taking the time!

Not sure I can really help ;) But I'll try to study these patches on
weekend.

Could you send me (privately) mbox with the patches/discussion ?

Oleg.

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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-18 Thread Jacob Shin
On Tue, Apr 16, 2013 at 11:36:20AM +0200, Ingo Molnar wrote:
> 
> * Jacob Shin  wrote:
> 
> > On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
> > > The following patchset adds address masks to existing perf hardware
> > > breakpoint mechanism to allow trapping on an address range (currently
> > > only single address) on supported architectures.
> > > 
> > > perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
> > > beyond) is provided, and perf tool has been extended to do:
> > > 
> > >   $ perf stat -e mem:0x1000:w:0xf a.out
> > >   ^^^
> > >   "don't care" bit mask
> > > 
> > >   which will count writes to [0x1000 ~ 0x1010)
> > 
> > Ping .. Ingo?
> 
> breakpoint patches usually come to me through (or with the acks of) Frederic 
> and/or Oleg.
> 
> Frederic, Oleg, mind having a look?

Hi Frederic, Oleg. Could one of you take a look over this patchset
when you get the chance? Thank you in advance for taking the time!

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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-18 Thread Jacob Shin
On Tue, Apr 16, 2013 at 11:36:20AM +0200, Ingo Molnar wrote:
 
 * Jacob Shin jacob.s...@amd.com wrote:
 
  On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
   The following patchset adds address masks to existing perf hardware
   breakpoint mechanism to allow trapping on an address range (currently
   only single address) on supported architectures.
   
   perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
   beyond) is provided, and perf tool has been extended to do:
   
 $ perf stat -e mem:0x1000:w:0xf a.out
 ^^^
 don't care bit mask
   
 which will count writes to [0x1000 ~ 0x1010)
  
  Ping .. Ingo?
 
 breakpoint patches usually come to me through (or with the acks of) Frederic 
 and/or Oleg.
 
 Frederic, Oleg, mind having a look?

Hi Frederic, Oleg. Could one of you take a look over this patchset
when you get the chance? Thank you in advance for taking the time!

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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-18 Thread Oleg Nesterov
Hi Jacob,

On 04/18, Jacob Shin wrote:

 Hi Frederic, Oleg. Could one of you take a look over this patchset
 when you get the chance? Thank you in advance for taking the time!

Not sure I can really help ;) But I'll try to study these patches on
weekend.

Could you send me (privately) mbox with the patches/discussion ?

Oleg.

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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-16 Thread Ingo Molnar

* Jacob Shin  wrote:

> On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
> > The following patchset adds address masks to existing perf hardware
> > breakpoint mechanism to allow trapping on an address range (currently
> > only single address) on supported architectures.
> > 
> > perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
> > beyond) is provided, and perf tool has been extended to do:
> > 
> >   $ perf stat -e mem:0x1000:w:0xf a.out
> >   ^^^
> >   "don't care" bit mask
> > 
> >   which will count writes to [0x1000 ~ 0x1010)
> 
> Ping .. Ingo?

breakpoint patches usually come to me through (or with the acks of) Frederic 
and/or Oleg.

Frederic, Oleg, mind having a look?

Thanks,

Ingo
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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-16 Thread Ingo Molnar

* Jacob Shin jacob.s...@amd.com wrote:

 On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
  The following patchset adds address masks to existing perf hardware
  breakpoint mechanism to allow trapping on an address range (currently
  only single address) on supported architectures.
  
  perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
  beyond) is provided, and perf tool has been extended to do:
  
$ perf stat -e mem:0x1000:w:0xf a.out
^^^
don't care bit mask
  
which will count writes to [0x1000 ~ 0x1010)
 
 Ping .. Ingo?

breakpoint patches usually come to me through (or with the acks of) Frederic 
and/or Oleg.

Frederic, Oleg, mind having a look?

Thanks,

Ingo
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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-15 Thread Jiri Olsa
On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
> The following patchset adds address masks to existing perf hardware
> breakpoint mechanism to allow trapping on an address range (currently
> only single address) on supported architectures.
> 
> perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
> beyond) is provided, and perf tool has been extended to do:
> 
>   $ perf stat -e mem:0x1000:w:0xf a.out
>   ^^^
>   "don't care" bit mask
> 
>   which will count writes to [0x1000 ~ 0x1010)
> 
> Jacob Shin (2):
>   perf: Add hardware breakpoint address mask
>   perf, x86: AMD implementation for hardware breakpoint address mask
> 
> Suravee Suthikulpanit (3):
>   perf tools: Add breakpoint address mask to the mem event parser
>   perf tools: Add breakpoint address mask syntax to perf list and
> documentation
>   perf tools: Add breakpoint address mask test case to
> tests/parse-events
hi,
the perf tool patches look ok.. thanks for tests! ;)

jirka
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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-15 Thread Jacob Shin
On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
> The following patchset adds address masks to existing perf hardware
> breakpoint mechanism to allow trapping on an address range (currently
> only single address) on supported architectures.
> 
> perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
> beyond) is provided, and perf tool has been extended to do:
> 
>   $ perf stat -e mem:0x1000:w:0xf a.out
>   ^^^
>   "don't care" bit mask
> 
>   which will count writes to [0x1000 ~ 0x1010)

Ping .. Ingo?

> 
> Jacob Shin (2):
>   perf: Add hardware breakpoint address mask
>   perf, x86: AMD implementation for hardware breakpoint address mask
> 
> Suravee Suthikulpanit (3):
>   perf tools: Add breakpoint address mask to the mem event parser
>   perf tools: Add breakpoint address mask syntax to perf list and
> documentation
>   perf tools: Add breakpoint address mask test case to
> tests/parse-events
> 
>  arch/Kconfig |4 
>  arch/x86/Kconfig |1 +
>  arch/x86/include/asm/cpufeature.h|2 ++
>  arch/x86/include/asm/debugreg.h  |7 ++
>  arch/x86/include/asm/hw_breakpoint.h |6 ++
>  arch/x86/include/uapi/asm/msr-index.h|6 ++
>  arch/x86/kernel/cpu/amd.c|   19 +
>  arch/x86/kernel/hw_breakpoint.c  |5 +
>  include/linux/hw_breakpoint.h|6 ++
>  include/uapi/linux/perf_event.h  |5 -
>  kernel/events/hw_breakpoint.c|3 +++
>  tools/perf/Documentation/perf-record.txt |   14 
>  tools/perf/tests/parse-events.c  |   34 
> ++
>  tools/perf/util/parse-events.c   |5 +++--
>  tools/perf/util/parse-events.h   |2 +-
>  tools/perf/util/parse-events.y   |   14 ++--
>  16 files changed, 123 insertions(+), 10 deletions(-)
> 
> -- 
> 1.7.9.5
> 

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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-15 Thread Jacob Shin
On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
 The following patchset adds address masks to existing perf hardware
 breakpoint mechanism to allow trapping on an address range (currently
 only single address) on supported architectures.
 
 perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
 beyond) is provided, and perf tool has been extended to do:
 
   $ perf stat -e mem:0x1000:w:0xf a.out
   ^^^
   don't care bit mask
 
   which will count writes to [0x1000 ~ 0x1010)

Ping .. Ingo?

 
 Jacob Shin (2):
   perf: Add hardware breakpoint address mask
   perf, x86: AMD implementation for hardware breakpoint address mask
 
 Suravee Suthikulpanit (3):
   perf tools: Add breakpoint address mask to the mem event parser
   perf tools: Add breakpoint address mask syntax to perf list and
 documentation
   perf tools: Add breakpoint address mask test case to
 tests/parse-events
 
  arch/Kconfig |4 
  arch/x86/Kconfig |1 +
  arch/x86/include/asm/cpufeature.h|2 ++
  arch/x86/include/asm/debugreg.h  |7 ++
  arch/x86/include/asm/hw_breakpoint.h |6 ++
  arch/x86/include/uapi/asm/msr-index.h|6 ++
  arch/x86/kernel/cpu/amd.c|   19 +
  arch/x86/kernel/hw_breakpoint.c  |5 +
  include/linux/hw_breakpoint.h|6 ++
  include/uapi/linux/perf_event.h  |5 -
  kernel/events/hw_breakpoint.c|3 +++
  tools/perf/Documentation/perf-record.txt |   14 
  tools/perf/tests/parse-events.c  |   34 
 ++
  tools/perf/util/parse-events.c   |5 +++--
  tools/perf/util/parse-events.h   |2 +-
  tools/perf/util/parse-events.y   |   14 ++--
  16 files changed, 123 insertions(+), 10 deletions(-)
 
 -- 
 1.7.9.5
 

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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-15 Thread Jiri Olsa
On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
 The following patchset adds address masks to existing perf hardware
 breakpoint mechanism to allow trapping on an address range (currently
 only single address) on supported architectures.
 
 perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
 beyond) is provided, and perf tool has been extended to do:
 
   $ perf stat -e mem:0x1000:w:0xf a.out
   ^^^
   don't care bit mask
 
   which will count writes to [0x1000 ~ 0x1010)
 
 Jacob Shin (2):
   perf: Add hardware breakpoint address mask
   perf, x86: AMD implementation for hardware breakpoint address mask
 
 Suravee Suthikulpanit (3):
   perf tools: Add breakpoint address mask to the mem event parser
   perf tools: Add breakpoint address mask syntax to perf list and
 documentation
   perf tools: Add breakpoint address mask test case to
 tests/parse-events
hi,
the perf tool patches look ok.. thanks for tests! ;)

jirka
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[PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-09 Thread Jacob Shin
The following patchset adds address masks to existing perf hardware
breakpoint mechanism to allow trapping on an address range (currently
only single address) on supported architectures.

perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
beyond) is provided, and perf tool has been extended to do:

  $ perf stat -e mem:0x1000:w:0xf a.out
  ^^^
  "don't care" bit mask

  which will count writes to [0x1000 ~ 0x1010)

Jacob Shin (2):
  perf: Add hardware breakpoint address mask
  perf, x86: AMD implementation for hardware breakpoint address mask

Suravee Suthikulpanit (3):
  perf tools: Add breakpoint address mask to the mem event parser
  perf tools: Add breakpoint address mask syntax to perf list and
documentation
  perf tools: Add breakpoint address mask test case to
tests/parse-events

 arch/Kconfig |4 
 arch/x86/Kconfig |1 +
 arch/x86/include/asm/cpufeature.h|2 ++
 arch/x86/include/asm/debugreg.h  |7 ++
 arch/x86/include/asm/hw_breakpoint.h |6 ++
 arch/x86/include/uapi/asm/msr-index.h|6 ++
 arch/x86/kernel/cpu/amd.c|   19 +
 arch/x86/kernel/hw_breakpoint.c  |5 +
 include/linux/hw_breakpoint.h|6 ++
 include/uapi/linux/perf_event.h  |5 -
 kernel/events/hw_breakpoint.c|3 +++
 tools/perf/Documentation/perf-record.txt |   14 
 tools/perf/tests/parse-events.c  |   34 ++
 tools/perf/util/parse-events.c   |5 +++--
 tools/perf/util/parse-events.h   |2 +-
 tools/perf/util/parse-events.y   |   14 ++--
 16 files changed, 123 insertions(+), 10 deletions(-)

-- 
1.7.9.5


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[PATCH 0/5] perf: Add support for hardware breakpoint address masks

2013-04-09 Thread Jacob Shin
The following patchset adds address masks to existing perf hardware
breakpoint mechanism to allow trapping on an address range (currently
only single address) on supported architectures.

perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
beyond) is provided, and perf tool has been extended to do:

  $ perf stat -e mem:0x1000:w:0xf a.out
  ^^^
  don't care bit mask

  which will count writes to [0x1000 ~ 0x1010)

Jacob Shin (2):
  perf: Add hardware breakpoint address mask
  perf, x86: AMD implementation for hardware breakpoint address mask

Suravee Suthikulpanit (3):
  perf tools: Add breakpoint address mask to the mem event parser
  perf tools: Add breakpoint address mask syntax to perf list and
documentation
  perf tools: Add breakpoint address mask test case to
tests/parse-events

 arch/Kconfig |4 
 arch/x86/Kconfig |1 +
 arch/x86/include/asm/cpufeature.h|2 ++
 arch/x86/include/asm/debugreg.h  |7 ++
 arch/x86/include/asm/hw_breakpoint.h |6 ++
 arch/x86/include/uapi/asm/msr-index.h|6 ++
 arch/x86/kernel/cpu/amd.c|   19 +
 arch/x86/kernel/hw_breakpoint.c  |5 +
 include/linux/hw_breakpoint.h|6 ++
 include/uapi/linux/perf_event.h  |5 -
 kernel/events/hw_breakpoint.c|3 +++
 tools/perf/Documentation/perf-record.txt |   14 
 tools/perf/tests/parse-events.c  |   34 ++
 tools/perf/util/parse-events.c   |5 +++--
 tools/perf/util/parse-events.h   |2 +-
 tools/perf/util/parse-events.y   |   14 ++--
 16 files changed, 123 insertions(+), 10 deletions(-)

-- 
1.7.9.5


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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2012-12-14 Thread Jacob Shin
On Wed, Dec 12, 2012 at 10:30:38AM -0600, Jacob Shin wrote:
> The following patchset adds address masks to existing perf hardware
> breakpoint mechanism to allow trapping on an address range (currently
> only single address) on supported architectures.
> 
> perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
> beyond) is provided, and perf tool has been extended to do:
> 
>   $ perf stat -e mem:0x1000:w:0xf a.out
>   ^^^
>   "don't care" bit mask
> 
>   which will count writes to [0x1000 ~ 0x1010)
> 
> Jacob Shin (2):
>   perf: Add hardware breakpoint address mask
>   perf, x86: AMD implementation for hardware breakpoint address mask
> 
> Suravee Suthikulpanit (3):
>   perf tools: Add breakpoint address mask to the mem event parser
>   perf tools: Add breakpoint address mask syntax to perf list and
> documentation
>   perf tools: Add breakpoint address mask test case to
> tests/parse-events
> 
>  arch/Kconfig |4 
>  arch/x86/Kconfig |1 +
>  arch/x86/include/asm/cpufeature.h|2 ++
>  arch/x86/include/asm/hw_breakpoint.h |6 ++
>  arch/x86/include/asm/msr-index.h |6 ++
>  arch/x86/include/asm/processor.h |7 ++
>  arch/x86/kernel/cpu/amd.c|   21 ++
>  arch/x86/kernel/hw_breakpoint.c  |5 +
>  include/linux/hw_breakpoint.h|6 ++
>  include/uapi/linux/perf_event.h  |5 -
>  kernel/events/hw_breakpoint.c|3 +++
>  tools/perf/Documentation/perf-record.txt |   14 
>  tools/perf/tests/parse-events.c  |   34 
> ++
>  tools/perf/util/parse-events.c   |5 +++--
>  tools/perf/util/parse-events.h   |2 +-
>  tools/perf/util/parse-events.y   |   14 ++--
>  16 files changed, 125 insertions(+), 10 deletions(-)
> 
> -- 

Ping .. any comments / feedback ? If not, could you commit it into tip ?

Thank you,

-Jacob

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Re: [PATCH 0/5] perf: Add support for hardware breakpoint address masks

2012-12-14 Thread Jacob Shin
On Wed, Dec 12, 2012 at 10:30:38AM -0600, Jacob Shin wrote:
 The following patchset adds address masks to existing perf hardware
 breakpoint mechanism to allow trapping on an address range (currently
 only single address) on supported architectures.
 
 perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
 beyond) is provided, and perf tool has been extended to do:
 
   $ perf stat -e mem:0x1000:w:0xf a.out
   ^^^
   don't care bit mask
 
   which will count writes to [0x1000 ~ 0x1010)
 
 Jacob Shin (2):
   perf: Add hardware breakpoint address mask
   perf, x86: AMD implementation for hardware breakpoint address mask
 
 Suravee Suthikulpanit (3):
   perf tools: Add breakpoint address mask to the mem event parser
   perf tools: Add breakpoint address mask syntax to perf list and
 documentation
   perf tools: Add breakpoint address mask test case to
 tests/parse-events
 
  arch/Kconfig |4 
  arch/x86/Kconfig |1 +
  arch/x86/include/asm/cpufeature.h|2 ++
  arch/x86/include/asm/hw_breakpoint.h |6 ++
  arch/x86/include/asm/msr-index.h |6 ++
  arch/x86/include/asm/processor.h |7 ++
  arch/x86/kernel/cpu/amd.c|   21 ++
  arch/x86/kernel/hw_breakpoint.c  |5 +
  include/linux/hw_breakpoint.h|6 ++
  include/uapi/linux/perf_event.h  |5 -
  kernel/events/hw_breakpoint.c|3 +++
  tools/perf/Documentation/perf-record.txt |   14 
  tools/perf/tests/parse-events.c  |   34 
 ++
  tools/perf/util/parse-events.c   |5 +++--
  tools/perf/util/parse-events.h   |2 +-
  tools/perf/util/parse-events.y   |   14 ++--
  16 files changed, 125 insertions(+), 10 deletions(-)
 
 -- 

Ping .. any comments / feedback ? If not, could you commit it into tip ?

Thank you,

-Jacob

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[PATCH 0/5] perf: Add support for hardware breakpoint address masks

2012-12-12 Thread Jacob Shin
The following patchset adds address masks to existing perf hardware
breakpoint mechanism to allow trapping on an address range (currently
only single address) on supported architectures.

perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
beyond) is provided, and perf tool has been extended to do:

  $ perf stat -e mem:0x1000:w:0xf a.out
  ^^^
  "don't care" bit mask

  which will count writes to [0x1000 ~ 0x1010)

Jacob Shin (2):
  perf: Add hardware breakpoint address mask
  perf, x86: AMD implementation for hardware breakpoint address mask

Suravee Suthikulpanit (3):
  perf tools: Add breakpoint address mask to the mem event parser
  perf tools: Add breakpoint address mask syntax to perf list and
documentation
  perf tools: Add breakpoint address mask test case to
tests/parse-events

 arch/Kconfig |4 
 arch/x86/Kconfig |1 +
 arch/x86/include/asm/cpufeature.h|2 ++
 arch/x86/include/asm/hw_breakpoint.h |6 ++
 arch/x86/include/asm/msr-index.h |6 ++
 arch/x86/include/asm/processor.h |7 ++
 arch/x86/kernel/cpu/amd.c|   21 ++
 arch/x86/kernel/hw_breakpoint.c  |5 +
 include/linux/hw_breakpoint.h|6 ++
 include/uapi/linux/perf_event.h  |5 -
 kernel/events/hw_breakpoint.c|3 +++
 tools/perf/Documentation/perf-record.txt |   14 
 tools/perf/tests/parse-events.c  |   34 ++
 tools/perf/util/parse-events.c   |5 +++--
 tools/perf/util/parse-events.h   |2 +-
 tools/perf/util/parse-events.y   |   14 ++--
 16 files changed, 125 insertions(+), 10 deletions(-)

-- 
1.7.9.5


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[PATCH 0/5] perf: Add support for hardware breakpoint address masks

2012-12-12 Thread Jacob Shin
The following patchset adds address masks to existing perf hardware
breakpoint mechanism to allow trapping on an address range (currently
only single address) on supported architectures.

perf uapi is updated, x86 AMD implementation (for AMD Family 16h and
beyond) is provided, and perf tool has been extended to do:

  $ perf stat -e mem:0x1000:w:0xf a.out
  ^^^
  don't care bit mask

  which will count writes to [0x1000 ~ 0x1010)

Jacob Shin (2):
  perf: Add hardware breakpoint address mask
  perf, x86: AMD implementation for hardware breakpoint address mask

Suravee Suthikulpanit (3):
  perf tools: Add breakpoint address mask to the mem event parser
  perf tools: Add breakpoint address mask syntax to perf list and
documentation
  perf tools: Add breakpoint address mask test case to
tests/parse-events

 arch/Kconfig |4 
 arch/x86/Kconfig |1 +
 arch/x86/include/asm/cpufeature.h|2 ++
 arch/x86/include/asm/hw_breakpoint.h |6 ++
 arch/x86/include/asm/msr-index.h |6 ++
 arch/x86/include/asm/processor.h |7 ++
 arch/x86/kernel/cpu/amd.c|   21 ++
 arch/x86/kernel/hw_breakpoint.c  |5 +
 include/linux/hw_breakpoint.h|6 ++
 include/uapi/linux/perf_event.h  |5 -
 kernel/events/hw_breakpoint.c|3 +++
 tools/perf/Documentation/perf-record.txt |   14 
 tools/perf/tests/parse-events.c  |   34 ++
 tools/perf/util/parse-events.c   |5 +++--
 tools/perf/util/parse-events.h   |2 +-
 tools/perf/util/parse-events.y   |   14 ++--
 16 files changed, 125 insertions(+), 10 deletions(-)

-- 
1.7.9.5


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