Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T

2016-02-02 Thread Maxime Ripard 
On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
> A83T has similar bus gates that of H3, including single gating register has
> different clock parent.
> 
> As per H3 and A83T datasheet, usbhost is under AHB2.
> 
> However,below shows allwinner source code assignment:
> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
> 
> until, this confusion is cleared keep it H3 way.
> 
> Signed-off-by: Vishnu Patekar 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
> b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 7f19ef5..4514d77 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -59,6 +59,7 @@ Required properties:
>   "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
>   "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
>   "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
> + "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T

Please order them alphabetically next time.

Applied with the fix, and the Acked-bys

thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


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Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T

2016-02-02 Thread Maxime Ripard 
On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
> A83T has similar bus gates that of H3, including single gating register has
> different clock parent.
> 
> As per H3 and A83T datasheet, usbhost is under AHB2.
> 
> However,below shows allwinner source code assignment:
> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
> 
> until, this confusion is cleared keep it H3 way.
> 
> Signed-off-by: Vishnu Patekar 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
> b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 7f19ef5..4514d77 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -59,6 +59,7 @@ Required properties:
>   "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
>   "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
>   "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
> + "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T

Please order them alphabetically next time.

Applied with the fix, and the Acked-bys

thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


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Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T

2016-02-01 Thread Chen-Yu Tsai 
On Mon, Feb 1, 2016 at 11:03 PM, Rob Herring  wrote:
> On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
>> A83T has similar bus gates that of H3, including single gating register has
>> different clock parent.
>>
>> As per H3 and A83T datasheet, usbhost is under AHB2.
>>
>> However,below shows allwinner source code assignment:
>> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
>> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
>> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
>>
>> until, this confusion is cleared keep it H3 way.
>>
>> Signed-off-by: Vishnu Patekar 
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>>  drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 2 ++
>>  2 files changed, 3 insertions(+)
>
> Acked-by: Rob Herring 

Acked-by: Chen-Yu Tsai 

We should really get the clk parents sorted out though.

Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T

2016-02-01 Thread Rob Herring 
On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
> A83T has similar bus gates that of H3, including single gating register has
> different clock parent.
> 
> As per H3 and A83T datasheet, usbhost is under AHB2.
> 
> However,below shows allwinner source code assignment:
> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
> 
> until, this confusion is cleared keep it H3 way.
> 
> Signed-off-by: Vishnu Patekar 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 2 ++
>  2 files changed, 3 insertions(+)

Acked-by: Rob Herring

Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T

2016-02-01 Thread Rob Herring 
On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
> A83T has similar bus gates that of H3, including single gating register has
> different clock parent.
> 
> As per H3 and A83T datasheet, usbhost is under AHB2.
> 
> However,below shows allwinner source code assignment:
> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
> 
> until, this confusion is cleared keep it H3 way.
> 
> Signed-off-by: Vishnu Patekar 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 2 ++
>  2 files changed, 3 insertions(+)

Acked-by: Rob Herring

Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T

2016-02-01 Thread Chen-Yu Tsai 
On Mon, Feb 1, 2016 at 11:03 PM, Rob Herring  wrote:
> On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
>> A83T has similar bus gates that of H3, including single gating register has
>> different clock parent.
>>
>> As per H3 and A83T datasheet, usbhost is under AHB2.
>>
>> However,below shows allwinner source code assignment:
>> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
>> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
>> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
>>
>> until, this confusion is cleared keep it H3 way.
>>
>> Signed-off-by: Vishnu Patekar 
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>>  drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 2 ++
>>  2 files changed, 3 insertions(+)
>
> Acked-by: Rob Herring 

Acked-by: Chen-Yu Tsai 

We should really get the clk parents sorted out though.

[PATCH 03/14] clk: sunxi: add bus gates for A83T

2016-01-30 Thread Vishnu Patekar 
A83T has similar bus gates that of H3, including single gating register has
different clock parent.

As per H3 and A83T datasheet, usbhost is under AHB2.

However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.

until, this confusion is cleared keep it H3 way.

Signed-off-by: Vishnu Patekar 
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 7f19ef5..4514d77 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -59,6 +59,7 @@ Required properties:
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
+   "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c 
b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
index 1113eb9..63fdb79 100644
--- a/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
@@ -109,3 +109,5 @@ err_unmap:
 
 CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
   sun8i_h3_bus_gates_init);
+CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
+  sun8i_h3_bus_gates_init);
-- 
1.9.1

[PATCH 03/14] clk: sunxi: add bus gates for A83T

2016-01-30 Thread Vishnu Patekar 
A83T has similar bus gates that of H3, including single gating register has
different clock parent.

As per H3 and A83T datasheet, usbhost is under AHB2.

However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.

until, this confusion is cleared keep it H3 way.

Signed-off-by: Vishnu Patekar 
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 7f19ef5..4514d77 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -59,6 +59,7 @@ Required properties:
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
+   "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c 
b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
index 1113eb9..63fdb79 100644
--- a/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
@@ -109,3 +109,5 @@ err_unmap:
 
 CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
   sun8i_h3_bus_gates_init);
+CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
+  sun8i_h3_bus_gates_init);
-- 
1.9.1