Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
Hi, On 21-03-17 06:16, Chanwoo Choi wrote: Hi, On 2017년 03월 21일 04:57, Hans de Goede wrote: Hi, On 20-03-17 02:33, Chanwoo Choi wrote: Hi, On 2017년 03월 17일 18:55, Hans de Goede wrote: Add a driver for charger detection / control on the Intel Cherrytrail Whiskey Cove PMIC. Signed-off-by: Hans de Goede --- drivers/extcon/Kconfig | 7 + drivers/extcon/Makefile| 1 + drivers/extcon/extcon-cht-wc.c | 356 + 3 files changed, 364 insertions(+) create mode 100644 drivers/extcon/extcon-cht-wc.c diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig index 96bbae5..4cace6b 100644 --- a/drivers/extcon/Kconfig +++ b/drivers/extcon/Kconfig @@ -52,6 +52,13 @@ config EXTCON_INTEL_INT3496 This ACPI device is typically found on Intel Baytrail or Cherrytrail based tablets, or other Baytrail / Cherrytrail devices. +config EXTCON_CHT_WC Need to reorder it alpabetically as the following Makefile. The idea is to have the items alphabetically listed in "make menuconfig" and the name of the menu item starts with Intel: If you want to locate it under the EXTCON_INTEL_INT3496, you should change the filename as following style: - extcon-intel-cht-wc.c I want to locate all entry alphabetically. Ok, will fix for v3 +tristate "Intel Cherrytrail Whiskey Cove PMIC extcon driver" +depends on INTEL_SOC_PMIC_CHTWC +help + Say Y here to enable extcon support for charger detection / control + on the Intel Cherrytrail Whiskey Cove PMIC. + config EXTCON_MAX14577 tristate "Maxim MAX14577/77836 EXTCON Support" depends on MFD_MAX14577 diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile index 237ac3f..160f88b 100644 --- a/drivers/extcon/Makefile +++ b/drivers/extcon/Makefile @@ -7,6 +7,7 @@ extcon-core-objs+= extcon.o devres.o obj-$(CONFIG_EXTCON_ADC_JACK)+= extcon-adc-jack.o obj-$(CONFIG_EXTCON_ARIZONA)+= extcon-arizona.o obj-$(CONFIG_EXTCON_AXP288)+= extcon-axp288.o +obj-$(CONFIG_EXTCON_CHT_WC)+= extcon-cht-wc.o obj-$(CONFIG_EXTCON_GPIO)+= extcon-gpio.o obj-$(CONFIG_EXTCON_INTEL_INT3496) += extcon-intel-int3496.o obj-$(CONFIG_EXTCON_MAX14577)+= extcon-max14577.o diff --git a/drivers/extcon/extcon-cht-wc.c b/drivers/extcon/extcon-cht-wc.c new file mode 100644 index 000..896eee6 --- /dev/null +++ b/drivers/extcon/extcon-cht-wc.c @@ -0,0 +1,356 @@ +/* + * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC + * Copyright (C) 2017 Hans de Goede + * + * Based on various non upstream patches to support the CHT Whiskey Cove PMIC: Maybe, you don't need to add ':' at the end of line. Th ':' is there because the following copyright line: + * Copyright (C) 2013-2015 Intel Corporation. All rights reserved. Comes from those various non upstream patches. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define CHT_WC_PWRSRC_IRQ0x6e03 +#define CHT_WC_PWRSRC_IRQ_MASK0x6e0f +#define CHT_WC_PWRSRC_STS0x6e1e +#define CHT_WC_PWRSRC_VBUSBIT(0) +#define CHT_WC_PWRSRC_DCBIT(1) +#define CHT_WC_PWRSRC_BATBIT(2) +#define CHT_WC_PWRSRC_ID_GNDBIT(3) +#define CHT_WC_PWRSRC_ID_FLOATBIT(4) + +#define CHT_WC_PHYCTRL0x5e07 + +#define CHT_WC_CHGRCTRL00x5e16 + +#define CHT_WC_CHGRCTRL00x5e16 +#define CHT_WC_CHGRCTRL0_CHGRRESETBIT(0) +#define CHT_WC_CHGRCTRL0_EMRGCHRENBIT(1) +#define CHT_WC_CHGRCTRL0_EXTCHRDISBIT(2) +#define CHT_WC_CHGRCTRL0_SWCONTROLBIT(3) +#define CHT_WC_CHGRCTRL0_TTLCK_MASKBIT(4) +#define CHT_WC_CHGRCTRL0_CCSM_OFF_MASKBIT(5) +#define CHT_WC_CHGRCTRL0_DBPOFF_MASKBIT(6) +#define CHT_WC_CHGRCTRL0_WDT_NOKICKBIT(7) + +#define CHT_WC_CHGRCTRL10x5e17 + +#define CHT_WC_USBSRC0x5e29 +#define CHT_WC_USBSRC_STS_MASKGENMASK(1, 0) +#define CHT_WC_USBSRC_STS_SUCCESS2 +#define CHT_WC_USBSRC_STS_FAIL3 +#define CHT_WC_USBSRC_TYPE_SHIFT2 +#define CHT_WC_USBSRC_TYPE_MASKGENMASK(5, 2) +#define CHT_WC_USBSRC_TYPE_NONE0 +#define CHT_WC_USBSRC_TYPE_SDP1 +#define CHT_WC_USBSRC_TYPE_DCP2 +#define CHT_WC_USBSRC_TYPE_CDP3 +#define CHT_WC_USBSRC_TYPE_ACA4 +#define CHT_WC_USBSRC_TYPE_SE15 +#define CHT_WC_USBSRC_TYPE_MHL6 +#define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN7 +#define CHT_WC_USBSRC_TYPE_OTHER8 +#define CHT_WC_USBSRC_TYPE_DCP_EXTPH
Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
Hi,
I think it again.
The "cht_wcove_pwrsrc' is ok, if the register use the 'pwrsrc' word
and using the 'wcove' instead of 'wc'. It is not big matter.
I agree to use the 'cht_wcove_pwrsrc'.
Best Regards,
Chanwoo Choi
On 2017년 03월 21일 14:21, Chanwoo Choi wrote:
> On 2017년 03월 21일 12:54, Chanwoo Choi wrote:
>> On 2017년 03월 20일 22:00, Andy Shevchenko wrote:
>>> On Mon, 2017-03-20 at 10:33 +0900, Chanwoo Choi wrote:
On 2017년 03월 17일 18:55, Hans de Goede wrote:
>>>
> +static const struct platform_device_id cht_wc_extcon_table[] = {
> + { .name = "cht_wcove_pwrsrc" },
You use the 'cht_wc' word instead of 'cht_wcove_pwrsrc'.
So, To maintain the consistency, you better to use the 'cht-wc' as the
name.
- I prefer to use '-' instead of '_' in the name.
.name ="cht-wc"
>>>
>>> I would keep as Hans did for the sake of consistency among all Whiskey
>>> Cove device drivers (and predecessors like Crystal Cove).
>>
>> The 'wcove' short word is not used in this patch.
>> If the author want to use the 'wcove', I recommend that
>> you should use the 'wcove' instead of 'wc' in this patch.
>>
>> And, I think that 'pwrsrc' is not ambiguous.
>
> I'm sorry. I used the wrong word. I mean that 'pwrsrc' is not correct.
>
>> Hans might use the 'pwrsrc' as the 'Power Source'.
>> But, this driver is not power source. Instead,
>> this driver supports the detection of external connector.
>>
>> I think 'power source' means the power supply instead of detector.
>>
>>>
>>> I understand your point from extcon subsystem view, but PMICs like
>>> Whiskey Cove are multi-functional devices, and thus naming across them
>>> (same prefix in use to be precise) is better idea.
>>>
> + {},
> +};
> +MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
>>>
>>
>>
>
>
Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
On 2017년 03월 21일 12:54, Chanwoo Choi wrote:
> On 2017년 03월 20일 22:00, Andy Shevchenko wrote:
>> On Mon, 2017-03-20 at 10:33 +0900, Chanwoo Choi wrote:
>>> On 2017년 03월 17일 18:55, Hans de Goede wrote:
>>
+static const struct platform_device_id cht_wc_extcon_table[] = {
+ { .name = "cht_wcove_pwrsrc" },
>>>
>>> You use the 'cht_wc' word instead of 'cht_wcove_pwrsrc'.
>>> So, To maintain the consistency, you better to use the 'cht-wc' as the
>>> name.
>>> - I prefer to use '-' instead of '_' in the name.
>>> .name ="cht-wc"
>>
>> I would keep as Hans did for the sake of consistency among all Whiskey
>> Cove device drivers (and predecessors like Crystal Cove).
>
> The 'wcove' short word is not used in this patch.
> If the author want to use the 'wcove', I recommend that
> you should use the 'wcove' instead of 'wc' in this patch.
>
> And, I think that 'pwrsrc' is not ambiguous.
I'm sorry. I used the wrong word. I mean that 'pwrsrc' is not correct.
> Hans might use the 'pwrsrc' as the 'Power Source'.
> But, this driver is not power source. Instead,
> this driver supports the detection of external connector.
>
> I think 'power source' means the power supply instead of detector.
>
>>
>> I understand your point from extcon subsystem view, but PMICs like
>> Whiskey Cove are multi-functional devices, and thus naming across them
>> (same prefix in use to be precise) is better idea.
>>
>>>
+ {},
+};
+MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
>>
>
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
Hi, On 2017년 03월 21일 04:57, Hans de Goede wrote: > Hi, > > On 20-03-17 02:33, Chanwoo Choi wrote: >> Hi, >> >> On 2017년 03월 17일 18:55, Hans de Goede wrote: >>> Add a driver for charger detection / control on the Intel Cherrytrail >>> Whiskey Cove PMIC. >>> >>> Signed-off-by: Hans de Goede >>> --- >>> drivers/extcon/Kconfig | 7 + >>> drivers/extcon/Makefile| 1 + >>> drivers/extcon/extcon-cht-wc.c | 356 >>> + >>> 3 files changed, 364 insertions(+) >>> create mode 100644 drivers/extcon/extcon-cht-wc.c >>> >>> diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig >>> index 96bbae5..4cace6b 100644 >>> --- a/drivers/extcon/Kconfig >>> +++ b/drivers/extcon/Kconfig >>> @@ -52,6 +52,13 @@ config EXTCON_INTEL_INT3496 >>>This ACPI device is typically found on Intel Baytrail or Cherrytrail >>>based tablets, or other Baytrail / Cherrytrail devices. >>> >>> +config EXTCON_CHT_WC >> >> Need to reorder it alpabetically as the following Makefile. > > The idea is to have the items alphabetically listed in "make menuconfig" > and the name of the menu item starts with Intel: If you want to locate it under the EXTCON_INTEL_INT3496, you should change the filename as following style: - extcon-intel-cht-wc.c I want to locate all entry alphabetically. > >> >>> +tristate "Intel Cherrytrail Whiskey Cove PMIC extcon driver" >>> +depends on INTEL_SOC_PMIC_CHTWC >>> +help >>> + Say Y here to enable extcon support for charger detection / control >>> + on the Intel Cherrytrail Whiskey Cove PMIC. >>> + >>> config EXTCON_MAX14577 >>> tristate "Maxim MAX14577/77836 EXTCON Support" >>> depends on MFD_MAX14577 >>> diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile >>> index 237ac3f..160f88b 100644 >>> --- a/drivers/extcon/Makefile >>> +++ b/drivers/extcon/Makefile >>> @@ -7,6 +7,7 @@ extcon-core-objs+= extcon.o devres.o >>> obj-$(CONFIG_EXTCON_ADC_JACK)+= extcon-adc-jack.o >>> obj-$(CONFIG_EXTCON_ARIZONA)+= extcon-arizona.o >>> obj-$(CONFIG_EXTCON_AXP288)+= extcon-axp288.o >>> +obj-$(CONFIG_EXTCON_CHT_WC)+= extcon-cht-wc.o >>> obj-$(CONFIG_EXTCON_GPIO)+= extcon-gpio.o >>> obj-$(CONFIG_EXTCON_INTEL_INT3496) += extcon-intel-int3496.o >>> obj-$(CONFIG_EXTCON_MAX14577)+= extcon-max14577.o >>> diff --git a/drivers/extcon/extcon-cht-wc.c b/drivers/extcon/extcon-cht-wc.c >>> new file mode 100644 >>> index 000..896eee6 >>> --- /dev/null >>> +++ b/drivers/extcon/extcon-cht-wc.c >>> @@ -0,0 +1,356 @@ >>> +/* >>> + * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC >>> + * Copyright (C) 2017 Hans de Goede >>> + * >>> + * Based on various non upstream patches to support the CHT Whiskey Cove >>> PMIC: >> >> Maybe, you don't need to add ':' at the end of line. > > Th ':' is there because the following copyright line: >> >>> + * Copyright (C) 2013-2015 Intel Corporation. All rights reserved. > > Comes from those various non upstream patches. > >>> + * >>> + * This program is free software; you can redistribute it and/or modify it >>> + * under the terms and conditions of the GNU General Public License, >>> + * version 2, as published by the Free Software Foundation. >>> + * >>> + * This program is distributed in the hope it will be useful, but WITHOUT >>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or >>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License >>> for >>> + * more details. >>> + */ >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#define CHT_WC_PWRSRC_IRQ0x6e03 >>> +#define CHT_WC_PWRSRC_IRQ_MASK0x6e0f >>> +#define CHT_WC_PWRSRC_STS0x6e1e >>> +#define CHT_WC_PWRSRC_VBUSBIT(0) >>> +#define CHT_WC_PWRSRC_DCBIT(1) >>> +#define CHT_WC_PWRSRC_BATBIT(2) >>> +#define CHT_WC_PWRSRC_ID_GNDBIT(3) >>> +#define CHT_WC_PWRSRC_ID_FLOATBIT(4) >>> + >>> +#define CHT_WC_PHYCTRL0x5e07 >>> + >>> +#define CHT_WC_CHGRCTRL00x5e16 >>> + >>> +#define CHT_WC_CHGRCTRL00x5e16 >>> +#define CHT_WC_CHGRCTRL0_CHGRRESETBIT(0) >>> +#define CHT_WC_CHGRCTRL0_EMRGCHRENBIT(1) >>> +#define CHT_WC_CHGRCTRL0_EXTCHRDISBIT(2) >>> +#define CHT_WC_CHGRCTRL0_SWCONTROLBIT(3) >>> +#define CHT_WC_CHGRCTRL0_TTLCK_MASKBIT(4) >>> +#define CHT_WC_CHGRCTRL0_CCSM_OFF_MASKBIT(5) >>> +#define CHT_WC_CHGRCTRL0_DBPOFF_MASKBIT(6) >>> +#define CHT_WC_CHGRCTRL0_WDT_NOKICKBIT(7) >>> + >>> +#define CHT_WC_CHGRCTRL10x5e17 >>> + >>> +#define CHT_WC_USBSRC0x5e29 >>> +#define CHT_WC_USBSRC_STS_MASKGENMASK(1, 0) >>> +#define CHT_WC_USBSRC_STS_SUCCESS2 >>> +#define CHT_WC_USBSRC_STS_FAIL3 >>> +#define CHT_WC_USBSRC_TYPE_SHIFT2 >>> +#define CHT_WC_USBSRC_TYPE_MASKGENMASK(5, 2) >>> +#define CHT_WC
Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
On 2017년 03월 20일 22:00, Andy Shevchenko wrote:
> On Mon, 2017-03-20 at 10:33 +0900, Chanwoo Choi wrote:
>> On 2017년 03월 17일 18:55, Hans de Goede wrote:
>
>>> +static const struct platform_device_id cht_wc_extcon_table[] = {
>>> + { .name = "cht_wcove_pwrsrc" },
>>
>> You use the 'cht_wc' word instead of 'cht_wcove_pwrsrc'.
>> So, To maintain the consistency, you better to use the 'cht-wc' as the
>> name.
>> - I prefer to use '-' instead of '_' in the name.
>> .name ="cht-wc"
>
> I would keep as Hans did for the sake of consistency among all Whiskey
> Cove device drivers (and predecessors like Crystal Cove).
The 'wcove' short word is not used in this patch.
If the author want to use the 'wcove', I recommend that
you should use the 'wcove' instead of 'wc' in this patch.
And, I think that 'pwrsrc' is not ambiguous.
Hans might use the 'pwrsrc' as the 'Power Source'.
But, this driver is not power source. Instead,
this driver supports the detection of external connector.
I think 'power source' means the power supply instead of detector.
>
> I understand your point from extcon subsystem view, but PMICs like
> Whiskey Cove are multi-functional devices, and thus naming across them
> (same prefix in use to be precise) is better idea.
>
>>
>>> + {},
>>> +};
>>> +MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
Hi,
On 20-03-17 02:33, Chanwoo Choi wrote:
Hi,
On 2017년 03월 17일 18:55, Hans de Goede wrote:
Add a driver for charger detection / control on the Intel Cherrytrail
Whiskey Cove PMIC.
Signed-off-by: Hans de Goede
---
drivers/extcon/Kconfig | 7 +
drivers/extcon/Makefile| 1 +
drivers/extcon/extcon-cht-wc.c | 356 +
3 files changed, 364 insertions(+)
create mode 100644 drivers/extcon/extcon-cht-wc.c
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
index 96bbae5..4cace6b 100644
--- a/drivers/extcon/Kconfig
+++ b/drivers/extcon/Kconfig
@@ -52,6 +52,13 @@ config EXTCON_INTEL_INT3496
This ACPI device is typically found on Intel Baytrail or Cherrytrail
based tablets, or other Baytrail / Cherrytrail devices.
+config EXTCON_CHT_WC
Need to reorder it alpabetically as the following Makefile.
The idea is to have the items alphabetically listed in "make menuconfig"
and the name of the menu item starts with Intel:
+ tristate "Intel Cherrytrail Whiskey Cove PMIC extcon driver"
+ depends on INTEL_SOC_PMIC_CHTWC
+ help
+ Say Y here to enable extcon support for charger detection / control
+ on the Intel Cherrytrail Whiskey Cove PMIC.
+
config EXTCON_MAX14577
tristate "Maxim MAX14577/77836 EXTCON Support"
depends on MFD_MAX14577
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
index 237ac3f..160f88b 100644
--- a/drivers/extcon/Makefile
+++ b/drivers/extcon/Makefile
@@ -7,6 +7,7 @@ extcon-core-objs+= extcon.o devres.o
obj-$(CONFIG_EXTCON_ADC_JACK) += extcon-adc-jack.o
obj-$(CONFIG_EXTCON_ARIZONA) += extcon-arizona.o
obj-$(CONFIG_EXTCON_AXP288)+= extcon-axp288.o
+obj-$(CONFIG_EXTCON_CHT_WC)+= extcon-cht-wc.o
obj-$(CONFIG_EXTCON_GPIO) += extcon-gpio.o
obj-$(CONFIG_EXTCON_INTEL_INT3496) += extcon-intel-int3496.o
obj-$(CONFIG_EXTCON_MAX14577) += extcon-max14577.o
diff --git a/drivers/extcon/extcon-cht-wc.c b/drivers/extcon/extcon-cht-wc.c
new file mode 100644
index 000..896eee6
--- /dev/null
+++ b/drivers/extcon/extcon-cht-wc.c
@@ -0,0 +1,356 @@
+/*
+ * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
+ * Copyright (C) 2017 Hans de Goede
+ *
+ * Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
Maybe, you don't need to add ':' at the end of line.
Th ':' is there because the following copyright line:
+ * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
Comes from those various non upstream patches.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CHT_WC_PWRSRC_IRQ 0x6e03
+#define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
+#define CHT_WC_PWRSRC_STS 0x6e1e
+#define CHT_WC_PWRSRC_VBUS BIT(0)
+#define CHT_WC_PWRSRC_DC BIT(1)
+#define CHT_WC_PWRSRC_BAT BIT(2)
+#define CHT_WC_PWRSRC_ID_GND BIT(3)
+#define CHT_WC_PWRSRC_ID_FLOAT BIT(4)
+
+#define CHT_WC_PHYCTRL 0x5e07
+
+#define CHT_WC_CHGRCTRL0 0x5e16
+
+#define CHT_WC_CHGRCTRL0 0x5e16
+#define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0)
+#define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1)
+#define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2)
+#define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3)
+#define CHT_WC_CHGRCTRL0_TTLCK_MASKBIT(4)
+#define CHT_WC_CHGRCTRL0_CCSM_OFF_MASK BIT(5)
+#define CHT_WC_CHGRCTRL0_DBPOFF_MASK BIT(6)
+#define CHT_WC_CHGRCTRL0_WDT_NOKICKBIT(7)
+
+#define CHT_WC_CHGRCTRL1 0x5e17
+
+#define CHT_WC_USBSRC 0x5e29
+#define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0)
+#define CHT_WC_USBSRC_STS_SUCCESS 2
+#define CHT_WC_USBSRC_STS_FAIL 3
+#define CHT_WC_USBSRC_TYPE_SHIFT 2
+#define CHT_WC_USBSRC_TYPE_MASKGENMASK(5, 2)
+#define CHT_WC_USBSRC_TYPE_NONE0
+#define CHT_WC_USBSRC_TYPE_SDP 1
+#define CHT_WC_USBSRC_TYPE_DCP 2
+#define CHT_WC_USBSRC_TYPE_CDP 3
+#define CHT_WC_USBSRC_TYPE_ACA 4
+#define CHT_WC_USBSRC_TYPE_SE1 5
+#define CHT_WC_USBSRC_TYPE_MHL 6
+#define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN 7
+#define CHT_WC_USBSRC_TYPE_OTHER 8
+#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9
+
+enum cht_wc_usb_id {
+ USB_ID_OTG,
+ USB_ID_GND,
+ USB_ID_FLOAT,
+ USB_RID_A,
+ USB_RID_B,
+ USB_RID_C,
+};
+
+/* Strings matchi
Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
Hi,
On 17-03-17 18:18, Andy Shevchenko wrote:
On Fri, 2017-03-17 at 10:55 +0100, Hans de Goede wrote:
Add a driver for charger detection / control on the Intel Cherrytrail
Whiskey Cove PMIC.
+Cc: Felipe for some question(s) below.
drivers/extcon/extcon-cht-wc.c | 356
I would use same pattern across drivers, i.e. "chtwc" (same for the rest
of the drivers in this series).
I already answered this in another part of the thread,
but for the archives sake let me copy and paste my answer:
"One thing I disagree with is the cht_wc > chtwc rename you are
proposing for one Cherry Trail and Whiskey Cove are 2 different
words (4 if you look at spelling but 2 if you look at pronunciation,
so IMHO cht_wc is more readable other then that I see the suggested
rename as a lot of extra churn without any tangible benefits."
+#define CHT_WC_PWRSRC_IRQ 0x6e03
+#define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
+#define CHT_WC_PWRSRC_STS 0x6e1e
+#define CHT_WC_PWRSRC_VBUS BIT(0)
+#define CHT_WC_PWRSRC_DC BIT(1)
+#define CHT_WC_PWRSRC_BAT BIT(2)
+#define CHT_WC_PWRSRC_ID_GND BIT(3)
+#define CHT_WC_PWRSRC_ID_FLOAT BIT(4)
Not obvious for which register those bit definitions are.
They are for all 3 CHT_WC_PWRSRC_* registers, this is the
more or less usual irq setup for some i2c devices where
there is a status register, an irq register where the hardware
sets bits to 1 (and we write 1 to clear) when the corresponding
status bits changes and a mask register to select which irq
register bits actually will raise the interrupt line.
Also, keep them ordered by offset.
Will fix.
+
+#define CHT_WC_PHYCTRL 0x5e07
+
+#define CHT_WC_CHGRCTRL0 0x5e16
Dup!
Good catch, will fix.
+
+#define CHT_WC_CHGRCTRL0 0x5e16
+static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext)
+{
+ int ret, usbsrc, status, retries = 5;
+
+ do {
+ ret = regmap_read(ext->regmap, CHT_WC_USBSRC,
&usbsrc);
+ if (ret) {
+ dev_err(ext->dev, "Error reading usbsrc:
%d\n", ret);
+ return ret;
+ }
+ status = usbsrc & CHT_WC_USBSRC_STS_MASK;
+ if (status == CHT_WC_USBSRC_STS_SUCCESS ||
+ status == CHT_WC_USBSRC_STS_FAIL)
+ break;
+
+ msleep(200);
Comment why and why so long?
Fixed for v2 (actually switched to using jiffies +
time_before for a more accurate timeout).
+ } while (retries--);
+static void cht_wc_extcon_det_event(struct cht_wc_extcon_data *ext)
det -> detect ?
Renamed to more accurate cht_wc_extcon_pwrsrc_event
+static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
+{
+ struct cht_wc_extcon_data *ext = data;
+ int ret, irqs;
+
+ ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
+ if (ret)
+ dev_err(ext->dev, "Error reading irqs: %d\n", ret);
Shouldn't we return IRQ_NONE here?
I was wondering the same myself here, there is no good
answer here, this should simply never fail ... which does
make returning IRQ_NONE a good idea, I was worried that
would lead to a "nobody cared, disabling irq", but as said this
should never happen, so when it does, disabling the irq is
probably for the best. Will fix.
+
+ cht_wc_extcon_det_event(ext);
+
+ ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
+ if (ret)
+ dev_err(ext->dev, "Error writing irqs: %d\n", ret);
+
+ return IRQ_HANDLED;
+}
+
+/* usb_id sysfs attribute for debug / testing purposes */
Hmm... I would use debugfs for debug, otherwise it looks like it should
be framework (extcon) wide.
Unfortunately these kinda sysfs files are somewhat normal when
dealing with USB-OTG. For example my board does not have the
id-pin hooked up to the connector, so to test host mode
I need to echo "gnd" to the sysfs attr. But also if I actually
want to use host-mode (or anyone else with the same or a similar
board).
This definitely is not something which belongs in the extcon-core.
Perhaps Felipe can advise something here.
+static int cht_wc_extcon_probe(struct platform_device *pdev)
+{
+ struct cht_wc_extcon_data *ext;
+ struct intel_soc_pmic *pmic = dev_get_drvdata(pdev-
dev.parent);
Exchange them (assignment first).
Fixed.
+ int irq, ret;
+
+ ret = devm_request_threaded_irq(ext->dev, irq, NULL,
cht_wc_extcon_isr,
+ IRQF_ONESHOT, pdev->name,
ext);
+ if (ret) {
+ dev_err(ext->dev, "Failed to request interrupt\n");
+ return ret;
+ }
+
+ /* Unmask irqs */
+ ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK,
+ (int)~(CHT_WC_PWRSRC_VBUS |
Hmm... Do you need explicit casting here?
Yes because the BIT(
Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
On Mon, 2017-03-20 at 10:33 +0900, Chanwoo Choi wrote:
> On 2017년 03월 17일 18:55, Hans de Goede wrote:
> > +static const struct platform_device_id cht_wc_extcon_table[] = {
> > + { .name = "cht_wcove_pwrsrc" },
>
> You use the 'cht_wc' word instead of 'cht_wcove_pwrsrc'.
> So, To maintain the consistency, you better to use the 'cht-wc' as the
> name.
> - I prefer to use '-' instead of '_' in the name.
> .name ="cht-wc"
I would keep as Hans did for the sake of consistency among all Whiskey
Cove device drivers (and predecessors like Crystal Cove).
I understand your point from extcon subsystem view, but PMICs like
Whiskey Cove are multi-functional devices, and thus naming across them
(same prefix in use to be precise) is better idea.
>
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
--
Andy Shevchenko
Intel Finland Oy
Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
Hi,
On 2017년 03월 17일 18:55, Hans de Goede wrote:
> Add a driver for charger detection / control on the Intel Cherrytrail
> Whiskey Cove PMIC.
>
> Signed-off-by: Hans de Goede
> ---
> drivers/extcon/Kconfig | 7 +
> drivers/extcon/Makefile| 1 +
> drivers/extcon/extcon-cht-wc.c | 356
> +
> 3 files changed, 364 insertions(+)
> create mode 100644 drivers/extcon/extcon-cht-wc.c
>
> diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
> index 96bbae5..4cace6b 100644
> --- a/drivers/extcon/Kconfig
> +++ b/drivers/extcon/Kconfig
> @@ -52,6 +52,13 @@ config EXTCON_INTEL_INT3496
> This ACPI device is typically found on Intel Baytrail or Cherrytrail
> based tablets, or other Baytrail / Cherrytrail devices.
>
> +config EXTCON_CHT_WC
Need to reorder it alpabetically as the following Makefile.
> + tristate "Intel Cherrytrail Whiskey Cove PMIC extcon driver"
> + depends on INTEL_SOC_PMIC_CHTWC
> + help
> + Say Y here to enable extcon support for charger detection / control
> + on the Intel Cherrytrail Whiskey Cove PMIC.
> +
> config EXTCON_MAX14577
> tristate "Maxim MAX14577/77836 EXTCON Support"
> depends on MFD_MAX14577
> diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
> index 237ac3f..160f88b 100644
> --- a/drivers/extcon/Makefile
> +++ b/drivers/extcon/Makefile
> @@ -7,6 +7,7 @@ extcon-core-objs += extcon.o devres.o
> obj-$(CONFIG_EXTCON_ADC_JACK)+= extcon-adc-jack.o
> obj-$(CONFIG_EXTCON_ARIZONA) += extcon-arizona.o
> obj-$(CONFIG_EXTCON_AXP288) += extcon-axp288.o
> +obj-$(CONFIG_EXTCON_CHT_WC) += extcon-cht-wc.o
> obj-$(CONFIG_EXTCON_GPIO)+= extcon-gpio.o
> obj-$(CONFIG_EXTCON_INTEL_INT3496) += extcon-intel-int3496.o
> obj-$(CONFIG_EXTCON_MAX14577)+= extcon-max14577.o
> diff --git a/drivers/extcon/extcon-cht-wc.c b/drivers/extcon/extcon-cht-wc.c
> new file mode 100644
> index 000..896eee6
> --- /dev/null
> +++ b/drivers/extcon/extcon-cht-wc.c
> @@ -0,0 +1,356 @@
> +/*
> + * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
> + * Copyright (C) 2017 Hans de Goede
> + *
> + * Based on various non upstream patches to support the CHT Whiskey Cove
> PMIC:
Maybe, you don't need to add ':' at the end of line.
> + * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define CHT_WC_PWRSRC_IRQ0x6e03
> +#define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
> +#define CHT_WC_PWRSRC_STS0x6e1e
> +#define CHT_WC_PWRSRC_VBUS BIT(0)
> +#define CHT_WC_PWRSRC_DC BIT(1)
> +#define CHT_WC_PWRSRC_BATBIT(2)
> +#define CHT_WC_PWRSRC_ID_GND BIT(3)
> +#define CHT_WC_PWRSRC_ID_FLOAT BIT(4)
> +
> +#define CHT_WC_PHYCTRL 0x5e07
> +
> +#define CHT_WC_CHGRCTRL0 0x5e16
> +
> +#define CHT_WC_CHGRCTRL0 0x5e16
> +#define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0)
> +#define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1)
> +#define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2)
> +#define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3)
> +#define CHT_WC_CHGRCTRL0_TTLCK_MASK BIT(4)
> +#define CHT_WC_CHGRCTRL0_CCSM_OFF_MASK BIT(5)
> +#define CHT_WC_CHGRCTRL0_DBPOFF_MASK BIT(6)
> +#define CHT_WC_CHGRCTRL0_WDT_NOKICK BIT(7)
> +
> +#define CHT_WC_CHGRCTRL1 0x5e17
> +
> +#define CHT_WC_USBSRC0x5e29
> +#define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0)
> +#define CHT_WC_USBSRC_STS_SUCCESS2
> +#define CHT_WC_USBSRC_STS_FAIL 3
> +#define CHT_WC_USBSRC_TYPE_SHIFT 2
> +#define CHT_WC_USBSRC_TYPE_MASK GENMASK(5, 2)
> +#define CHT_WC_USBSRC_TYPE_NONE 0
> +#define CHT_WC_USBSRC_TYPE_SDP 1
> +#define CHT_WC_USBSRC_TYPE_DCP 2
> +#define CHT_WC_USBSRC_TYPE_CDP 3
> +#define CHT_WC_USBSRC_TYPE_ACA 4
> +#define CHT_WC_USBSRC_TYPE_SE1 5
> +#define CHT_WC_USBSRC_TYPE_MHL 6
> +#define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN 7
> +#define CHT_WC_USBSRC_TYPE_OTHER 8
> +#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY9
> +
> +enum cht_wc_usb_id {
> + USB_ID_OTG,
> + USB_ID_GND,
> + USB_ID_FLOAT,
> + USB_RID_A,
> + USB_RID_B,
> + USB_RID_C,
> +};
> +
> +/* Strings matching the c
Re: [PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
On Fri, 2017-03-17 at 10:55 +0100, Hans de Goede wrote:
> Add a driver for charger detection / control on the Intel Cherrytrail
> Whiskey Cove PMIC.
+Cc: Felipe for some question(s) below.
> drivers/extcon/extcon-cht-wc.c | 356
I would use same pattern across drivers, i.e. "chtwc" (same for the rest
of the drivers in this series).
> +#define CHT_WC_PWRSRC_IRQ0x6e03
> +#define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
> +#define CHT_WC_PWRSRC_STS0x6e1e
> +#define CHT_WC_PWRSRC_VBUS BIT(0)
> +#define CHT_WC_PWRSRC_DC BIT(1)
> +#define CHT_WC_PWRSRC_BATBIT(2)
> +#define CHT_WC_PWRSRC_ID_GND BIT(3)
> +#define CHT_WC_PWRSRC_ID_FLOAT BIT(4)
Not obvious for which register those bit definitions are.
Also, keep them ordered by offset.
> +
> +#define CHT_WC_PHYCTRL 0x5e07
> +
> +#define CHT_WC_CHGRCTRL0 0x5e16
Dup!
> +
> +#define CHT_WC_CHGRCTRL0 0x5e16
> +static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext)
> +{
> + int ret, usbsrc, status, retries = 5;
> +
> + do {
> + ret = regmap_read(ext->regmap, CHT_WC_USBSRC,
> &usbsrc);
> + if (ret) {
> + dev_err(ext->dev, "Error reading usbsrc:
> %d\n", ret);
> + return ret;
> + }
> + status = usbsrc & CHT_WC_USBSRC_STS_MASK;
> + if (status == CHT_WC_USBSRC_STS_SUCCESS ||
> + status == CHT_WC_USBSRC_STS_FAIL)
> + break;
> +
> + msleep(200);
Comment why and why so long?
> + } while (retries--);
> +static void cht_wc_extcon_det_event(struct cht_wc_extcon_data *ext)
det -> detect ?
>
+static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
> +{
> + struct cht_wc_extcon_data *ext = data;
> + int ret, irqs;
> +
> + ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
> + if (ret)
> + dev_err(ext->dev, "Error reading irqs: %d\n", ret);
Shouldn't we return IRQ_NONE here?
Perhaps comment is needed.
> +
> + cht_wc_extcon_det_event(ext);
> +
> + ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
> + if (ret)
> + dev_err(ext->dev, "Error writing irqs: %d\n", ret);
> +
> + return IRQ_HANDLED;
> +}
> +
> +/* usb_id sysfs attribute for debug / testing purposes */
Hmm... I would use debugfs for debug, otherwise it looks like it should
be framework (extcon) wide.
Perhaps Felipe can advise something here.
> +static int cht_wc_extcon_probe(struct platform_device *pdev)
> +{
> + struct cht_wc_extcon_data *ext;
> + struct intel_soc_pmic *pmic = dev_get_drvdata(pdev-
> >dev.parent);
Exchange them (assignment first).
> + int irq, ret;
> +
> + ret = devm_request_threaded_irq(ext->dev, irq, NULL,
> cht_wc_extcon_isr,
> + IRQF_ONESHOT, pdev->name,
> ext);
> + if (ret) {
> + dev_err(ext->dev, "Failed to request interrupt\n");
> + return ret;
> + }
> +
> + /* Unmask irqs */
> + ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK,
> + (int)~(CHT_WC_PWRSRC_VBUS |
Hmm... Do you need explicit casting here?
> CHT_WC_PWRSRC_ID_GND |
> + CHT_WC_PWRSRC_ID_FLOAT));
> + if (ret) {
> + dev_err(ext->dev, "Error writing irq-mask: %d\n",
> ret);
> + return ret;
> + }
--
Andy Shevchenko
Intel Finland Oy
[PATCH 03/15] extcon: cht-wc: Add Intel Cherry Trail Whiskey Cove PMIC extcon driver
Add a driver for charger detection / control on the Intel Cherrytrail
Whiskey Cove PMIC.
Signed-off-by: Hans de Goede
---
drivers/extcon/Kconfig | 7 +
drivers/extcon/Makefile| 1 +
drivers/extcon/extcon-cht-wc.c | 356 +
3 files changed, 364 insertions(+)
create mode 100644 drivers/extcon/extcon-cht-wc.c
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
index 96bbae5..4cace6b 100644
--- a/drivers/extcon/Kconfig
+++ b/drivers/extcon/Kconfig
@@ -52,6 +52,13 @@ config EXTCON_INTEL_INT3496
This ACPI device is typically found on Intel Baytrail or Cherrytrail
based tablets, or other Baytrail / Cherrytrail devices.
+config EXTCON_CHT_WC
+ tristate "Intel Cherrytrail Whiskey Cove PMIC extcon driver"
+ depends on INTEL_SOC_PMIC_CHTWC
+ help
+ Say Y here to enable extcon support for charger detection / control
+ on the Intel Cherrytrail Whiskey Cove PMIC.
+
config EXTCON_MAX14577
tristate "Maxim MAX14577/77836 EXTCON Support"
depends on MFD_MAX14577
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
index 237ac3f..160f88b 100644
--- a/drivers/extcon/Makefile
+++ b/drivers/extcon/Makefile
@@ -7,6 +7,7 @@ extcon-core-objs+= extcon.o devres.o
obj-$(CONFIG_EXTCON_ADC_JACK) += extcon-adc-jack.o
obj-$(CONFIG_EXTCON_ARIZONA) += extcon-arizona.o
obj-$(CONFIG_EXTCON_AXP288)+= extcon-axp288.o
+obj-$(CONFIG_EXTCON_CHT_WC)+= extcon-cht-wc.o
obj-$(CONFIG_EXTCON_GPIO) += extcon-gpio.o
obj-$(CONFIG_EXTCON_INTEL_INT3496) += extcon-intel-int3496.o
obj-$(CONFIG_EXTCON_MAX14577) += extcon-max14577.o
diff --git a/drivers/extcon/extcon-cht-wc.c b/drivers/extcon/extcon-cht-wc.c
new file mode 100644
index 000..896eee6
--- /dev/null
+++ b/drivers/extcon/extcon-cht-wc.c
@@ -0,0 +1,356 @@
+/*
+ * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
+ * Copyright (C) 2017 Hans de Goede
+ *
+ * Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
+ * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CHT_WC_PWRSRC_IRQ 0x6e03
+#define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
+#define CHT_WC_PWRSRC_STS 0x6e1e
+#define CHT_WC_PWRSRC_VBUS BIT(0)
+#define CHT_WC_PWRSRC_DC BIT(1)
+#define CHT_WC_PWRSRC_BAT BIT(2)
+#define CHT_WC_PWRSRC_ID_GND BIT(3)
+#define CHT_WC_PWRSRC_ID_FLOAT BIT(4)
+
+#define CHT_WC_PHYCTRL 0x5e07
+
+#define CHT_WC_CHGRCTRL0 0x5e16
+
+#define CHT_WC_CHGRCTRL0 0x5e16
+#define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0)
+#define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1)
+#define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2)
+#define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3)
+#define CHT_WC_CHGRCTRL0_TTLCK_MASKBIT(4)
+#define CHT_WC_CHGRCTRL0_CCSM_OFF_MASK BIT(5)
+#define CHT_WC_CHGRCTRL0_DBPOFF_MASK BIT(6)
+#define CHT_WC_CHGRCTRL0_WDT_NOKICKBIT(7)
+
+#define CHT_WC_CHGRCTRL1 0x5e17
+
+#define CHT_WC_USBSRC 0x5e29
+#define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0)
+#define CHT_WC_USBSRC_STS_SUCCESS 2
+#define CHT_WC_USBSRC_STS_FAIL 3
+#define CHT_WC_USBSRC_TYPE_SHIFT 2
+#define CHT_WC_USBSRC_TYPE_MASKGENMASK(5, 2)
+#define CHT_WC_USBSRC_TYPE_NONE0
+#define CHT_WC_USBSRC_TYPE_SDP 1
+#define CHT_WC_USBSRC_TYPE_DCP 2
+#define CHT_WC_USBSRC_TYPE_CDP 3
+#define CHT_WC_USBSRC_TYPE_ACA 4
+#define CHT_WC_USBSRC_TYPE_SE1 5
+#define CHT_WC_USBSRC_TYPE_MHL 6
+#define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN 7
+#define CHT_WC_USBSRC_TYPE_OTHER 8
+#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9
+
+enum cht_wc_usb_id {
+ USB_ID_OTG,
+ USB_ID_GND,
+ USB_ID_FLOAT,
+ USB_RID_A,
+ USB_RID_B,
+ USB_RID_C,
+};
+
+/* Strings matching the cht_wc_usb_id enum labels */
+static const char * const usb_id_str[] = {
+ "otg", "gnd", "float", "rid_a", "rid_b", "rid_c" };
+
+enum cht_wc_mux_select {
+ MUX_SEL_PMIC = 0,
+ MUX_SEL_SOC,
+};
+
+static const unsigned int cht_wc_extcon_cables[] = {
+ EXTCON_USB,
+ EXTCON_USB_HOST,
+ EXTCON_CHG_USB_SDP,
+ EXTCON_CHG_USB_CDP,
+ EXTCON_CHG_USB_DCP,
+ EXTCON_NONE,
+};
+
+struct cht_wc_extco
